blob_id stringlengths 40 40 | directory_id stringlengths 40 40 | path stringlengths 2 268 | content_id stringlengths 40 40 | detected_licenses listlengths 0 58 | license_type stringclasses 2
values | repo_name stringlengths 5 118 | snapshot_id stringlengths 40 40 | revision_id stringlengths 40 40 | branch_name stringclasses 816
values | visit_date timestamp[us] | revision_date timestamp[us] | committer_date timestamp[us] | github_id int64 2.31k 677M ⌀ | star_events_count int64 0 209k | fork_events_count int64 0 110k | gha_license_id stringclasses 23
values | gha_event_created_at timestamp[us] | gha_created_at timestamp[us] | gha_language stringclasses 151
values | src_encoding stringclasses 33
values | language stringclasses 1
value | is_vendor bool 2
classes | is_generated bool 2
classes | length_bytes int64 3 10.3M | extension stringclasses 119
values | content stringlengths 3 10.3M | authors listlengths 1 1 | author_id stringlengths 0 228 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
f71add6b50e128f449f5bf000bb9ac5fd8c14060 | c5889ad568e532cb62f98a2a95a05c72f0cde500 | /push_swap/src_checker/loop_hook.c | 5229c9672c0735400406e7452daf0a547a5796db | [] | no_license | antoinedauchy/push_swap | 8f59014679f94a82209ad7de838a82c1d6c5d334 | 92a7c48a649199d1d8e50fea5d30859d930a276d | refs/heads/master | 2020-03-14T14:21:21.089479 | 2018-05-07T20:05:47 | 2018-05-07T20:05:47 | 131,651,938 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,426 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* loop_hook.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: adauchy <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2018/02/27 20:15:01 by adauchy #+# #+# */
/* Updated: 2018/03/08 19:19:52 by adauchy ### ########.fr */
/* */
/* ************************************************************************** */
#include "checker.h"
void print_stacks_background(t_mlx mlx, t_data *data)
{
t_coord pos;
t_coord size;
pos.x = STACK_X;
pos.y = STACK_B_Y;
size.x = data->width_block * data->stk->size;
size.y = HEIGHT_STACK;
print_square(pos, size, 0xA4A4A4, mlx.img);
pos.y = STACK_A_Y;
print_square(pos, size, 0xA4A4A4, mlx.img);
}
void print_stack(char id, unsigned int *stack, int head, t_data *data)
{
int n;
t_coord pos;
t_coord size;
n = head;
size.x = data->width_block;
while (n < data->stk->size)
{
pos.x = STACK_X + n * data->width_block;
size.y = (HEIGHT_STACK - data->min_size) * stack[n] / data->diff +
data->min_size;
pos.y = (id == 'a' ? STACK_A_Y : STACK_B_Y) + HEIGHT_STACK - size.y;
print_square(pos, size, get_color((long)stack[n], MAX_COLOR, MIN_COLOR,
(long)data->diff), data->mlx.img);
n += 1;
}
}
void print_stacks(t_data *data)
{
print_stacks_background(data->mlx, data);
print_stack('a', (unsigned int*)data->stk->stack_a,
data->stk->head_a, data);
print_stack('b', (unsigned int*)data->stk->stack_b,
data->stk->head_b, data);
}
int loop_hook(void *ptr)
{
t_data *data;
static int n = 0;
static int print = 0;
data = (t_data*)ptr;
if (data->pause)
return (0);
if (data->speed >= 0 && print++ < data->speed)
{
if (data->instr[n])
call_instr(data->instr[n++], data->stk);
return (0);
}
if (print >= data->speed)
print = 0;
print_stacks(data);
mlx_put_image_to_window(data->mlx.mlx, data->mlx.win,
data->mlx.img.img, 0, 0);
return (0);
}
| [
"noreply@github.com"
] | antoinedauchy.noreply@github.com |
7c6be219da0ffa4ed5490482f323f0d54d9a5053 | d6ec83e5e19f565c28d39522e8ee090d67c17a5d | /src/mrb_libui.c | 26b128f397753d70b2cd68714a5834a77de893a5 | [
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | bamchoh/mruby-libui | de2036c166c026833a2ae6a435d12cd3be6f8345 | 2d9c54e82ad4c61871243fa1a03501c0c30176ca | refs/heads/master | 2021-08-24T07:05:04.650848 | 2017-12-08T14:48:55 | 2017-12-08T14:48:55 | 113,584,935 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,271 | c | /*
** mrb_libui.c - LibUI class
**
** Copyright (c) bamchoh 2016
**
** See Copyright Notice in LICENSE
*/
#include "mruby.h"
#include "mruby/data.h"
#include "mruby/variable.h"
#include "mrb_libui.h"
#include "ui.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "mrb_window.h"
#define DONE mrb_gc_arena_restore(mrb, 0);
static mrb_value mrb_libui_init(mrb_state *mrb, mrb_value self)
{
uiInitOptions o;
const char *err;
memset(&o, 0, sizeof (uiInitOptions));
err = uiInit(&o);
if (err != NULL) {
mrb_raisef(mrb, E_RUNTIME_ERROR, "error initializing ui: %S", mrb_str_new_cstr(mrb, err));
uiFreeInitError(err);
return mrb_nil_value();
}
return mrb_nil_value();
}
static mrb_value mrb_libui_uninit(mrb_state *mrb, mrb_value self)
{
uiUninit();
return mrb_nil_value();
}
static mrb_value mrb_libui_main(mrb_state *mrb, mrb_value self)
{
uiMain();
return mrb_nil_value();
}
static mrb_value mrb_libui_main_step(mrb_state *mrb, mrb_value self)
{
int wait;
mrb_get_args(mrb, "i", &wait);
if(uiMainStep(wait)) {
return mrb_true_value();
} else {
return mrb_false_value();
}
}
static mrb_value mrb_libui_quit(mrb_state *mrb, mrb_value self)
{
uiQuit();
return mrb_nil_value();
}
void mrb_mruby_libui_gem_init(mrb_state *mrb)
{
struct RClass *libui = mrb_define_module(mrb, "LibUI");
mrb_define_class_method(mrb, libui, "init", mrb_libui_init, MRB_ARGS_NONE());
mrb_define_class_method(mrb, libui, "uninit", mrb_libui_uninit, MRB_ARGS_NONE());
mrb_define_class_method(mrb, libui, "main", mrb_libui_main, MRB_ARGS_NONE());
mrb_define_class_method(mrb, libui, "main_step", mrb_libui_main_step, MRB_ARGS_REQ(1));
mrb_define_class_method(mrb, libui, "quit", mrb_libui_quit, MRB_ARGS_NONE());
mrb_libui_window_init(mrb, libui);
// TODO: need to figure out callback sequence for mruby
// mrb_define_class_method(mrb, libui, "queue_main", mrb_libui_queue_main, MRB_ARGS_NONE());
// mrb_define_class_method(mrb, libui, "on_should_quit", mrb_libui_on_should_quit, MRB_ARGS_NONE());
// TODO: it might be unnecessary for mruby
// mrb_define_class_method(mrb, libui, "free_text", mrb_libui_free_text, MRB_ARGS_NONE());
DONE;
}
void mrb_mruby_libui_gem_final(mrb_state *mrb)
{
}
| [
"bamchoh@gmail.com"
] | bamchoh@gmail.com |
e957e836a5baf1da19fccb688d32fac1fcf06c17 | 6c285ce3906c24504581f0868a1371d00361f80e | /UNIDAD 1/Proyecto Ensamblador/Proyecto ensamblador.c | 3160aaaf6ed15cbc88e17fc3d702af076cc170c8 | [] | no_license | Lalitec1/lalitec99 | fd6f3c0c0f3dace2dbaa2f5edadfe76e788fe65b | a7f61a794dc97aa635298185ecc407fb411e4a51 | refs/heads/master | 2021-08-28T16:19:07.017220 | 2017-12-12T18:08:56 | 2017-12-12T18:08:56 | 106,051,314 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,033 | c | /**main.c Presente en pantalla de 10 en 10 los bytes de
un arreglo que contiene un programa ejecutable para el procesador
ARC (A Risc Computer)
*/
#include <stdio.h>
#include <stdlib.h>
unsigned char Byte[]={0xc2, 0x00, 0x28, 0x10, 0xc4, 0x00, 0x28, 0x14, 0x86, 0x80, 0x40,
0x02, 0xc6, 0x20, 0x28, 0x18};//0x18 esta en 2063
int main(int argc, char *argv[])
{
int dir_inic=2048,i,tam,mostrados;
//cantidad de elementos del areeglo Byte
tam=sizeof(Byte)/sizeof(unsigned char);
if(tam>=10){
for(i=0;i<10;i++){
printf("%d\t%d\n",dir_inic+i,Byte[i]);
}
mostrados=10;
}else {
for(i=0;i<tam;i++){
printf("%d\t%d\n",dir_inic+i,Byte[i]);
}
mostrados=tam;
}
system("PAUSE");
if(tam-mostrados>=10){
for(i=mostrados;i<mostrados+10;i++){
printf("%d\t%d\n",dir_inic+i,Byte[i]);
}
return tam;
//mostrados=mostrados+10;
}else {
for(i=mostrados;i<tam;i++){
printf("%d\t%d\n",dir_inic+i,Byte[i]);
}
mostrados=tam-mostrados;
}
system("PAUSE");
return 0;
}
| [
"lalitec99@gmail.com"
] | lalitec99@gmail.com |
2aa95f124ece962d6667b63fb33b4614cc5c5f5e | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/reactos/dll/win32/usp10/extr_opentype.c_GPOS_get_value_record.c | d33d5e9d7ef555a91e3f50cdf3d42d5f811120ac | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,679 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
typedef struct TYPE_3__ TYPE_1__ ;
/* Type definitions */
typedef int WORD ;
struct TYPE_3__ {void* YAdvDevice; void* XAdvDevice; void* YPlaDevice; void* XPlaDevice; void* YAdvance; void* XAdvance; void* YPlacement; void* XPlacement; } ;
typedef size_t INT ;
typedef TYPE_1__ GPOS_ValueRecord ;
/* Variables and functions */
void* GET_BE_WORD (int const) ;
__attribute__((used)) static INT GPOS_get_value_record(WORD ValueFormat, const WORD data[], GPOS_ValueRecord *record)
{
INT offset = 0;
if (ValueFormat & 0x0001) { if (data) record->XPlacement = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0002) { if (data) record->YPlacement = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0004) { if (data) record->XAdvance = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0008) { if (data) record->YAdvance = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0010) { if (data) record->XPlaDevice = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0020) { if (data) record->YPlaDevice = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0040) { if (data) record->XAdvDevice = GET_BE_WORD(data[offset]); offset++; }
if (ValueFormat & 0x0080) { if (data) record->YAdvDevice = GET_BE_WORD(data[offset]); offset++; }
return offset;
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
b38cfbe692b31cc6b0005f9fc695a9b8aa93b5cb | cbd6c6a7c4e555e26c76dea6c827a3f36f8f449a | /SoftC/02/complex/complex_div.c | 09c2f4b84a61a055327aad8e5a2ac71f5b8aa647 | [
"MIT"
] | permissive | her0m31/Studys | 8a71d4ae2552cf285d7a5e16b8a6c0f81e259106 | f765310cd826356af04008a055905cade21fda4a | refs/heads/master | 2020-12-24T08:46:39.155718 | 2016-08-17T16:48:51 | 2016-08-17T16:48:51 | 23,060,547 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 381 | c | /* complex_div.c */
#include <stdio.h>
#include "complex.h"
struct complex div(struct complex x, struct complex y)
{
struct complex z;
z.real = (x.real * y.real - x.imaginary * y.imaginary)
/ (x.real * x.real) + (y.imaginary * y.imaginary);
z.imaginary = (x.real * y.imaginary + y.real * x.imaginary)
/ (x.real * x.real) + (y.imaginary * y.imaginary);
return z;
}
| [
"her0m@her0ms-Air.local"
] | her0m@her0ms-Air.local |
6a9888a8110533c69354af0403faddd51b2a49f8 | 306ccac7f385456cb284f932a1952279df544da4 | /main.c | 5f3e39ce2673dc95fac9deb1ff0a3aaa858408d3 | [] | no_license | hsdhatt/rb-tree | 4d5c9f8dc33ad2b023dd18db7f84d8d238ca018d | a682ff6ceef6ec9d793c37e02e0246d8e76fa9b7 | refs/heads/master | 2016-08-10T23:19:59.021677 | 2016-01-31T08:40:33 | 2016-01-31T08:40:33 | 49,702,484 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,301 | c |
#include "tree.h"
struct tree_node *rootptr;
void insert(struct tree_node **ptr, int input_val)
{
if (*ptr == NULL) {
*ptr = (struct tree_node *)malloc((sizeof(struct tree_node)));
(*ptr)->val = input_val;
(*ptr)->left = NULL;
(*ptr)->right = NULL;
(*ptr)->height = -1;
(*ptr)->color = RED;
LOG("node %p val %d\n", *ptr, (*ptr)->val);
return;
}
if (input_val < (*ptr)->val)
insert(&(*ptr)->left, input_val);
else if (input_val > (*ptr)->val)
insert(&(*ptr)->right, input_val);
return;
}
void free_tree(struct tree_node *ptr)
{
if (ptr == NULL)
return;
free_tree(ptr->left);
free_tree(ptr->right);
LOG("free ptr %p data %d\n", ptr, ptr->val);
free(ptr);
return;
}
int main(int argc, char *argv[])
{
int input_val;
while(1) {
printf("please enter a number, or 0 to exit\n");
scanf("%d",&input_val);
if (input_val == 0)
break;
else {
if (rootptr == NULL) {
rootptr = (struct tree_node*)malloc(sizeof(*rootptr));
rootptr->val = input_val;
rootptr->left = NULL;
rootptr->right = NULL;
rootptr->height = -1;
rootptr->color = BLACK;
}
else {
insert(&rootptr, input_val);
check_properties(&rootptr, NULL);
height(&rootptr, NULL);
pretty_print(rootptr);
}
}
}
free_tree(rootptr);
return 0;
}
| [
"09.harshdeep@gmail.com"
] | 09.harshdeep@gmail.com |
66bbfc0c770736f16f12c32d9a09c404eb94e358 | 62ce7ea592e696934b1508e50f6cfcb4527df74c | /scheduler_SJF.c | fed5967997cd470dd7e4e534884dcf0e31076d10 | [] | no_license | AndrewLiu0725/2020_OS_Project1 | 0d1f0d9cbfea4e06e3bc79a4391a9cd3d9452902 | 8fd15dd7e46d92bc5675decc4ddd5ff59bf03460 | refs/heads/master | 2022-05-30T05:42:45.928383 | 2020-05-03T14:09:04 | 2020-05-03T14:09:04 | 259,917,023 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,833 | c | #include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <string.h>
#include <sys/types.h>
#include <sys/wait.h>
#include <sys/syscall.h>
#include "process.h"
int find_shortest(Process *proc, int N_procs, int time){
int shortest = -1, excute_time = INT_MAX;
for (int i = 0; i < N_procs; i++){
// if the process is ready and its deadline is closer than the current deadline (also check if the execution time is null)
if ((proc[i].ready_time <= time) && (proc[i].exec_time) && (proc[i].exec_time < excute_time)){
excute_time = proc[i].exec_time;
shortest = i;
}
}
return shortest; // return index of the shortest process
}
int scheduler_SJF(Process *proc, int N_procs){
int N_fin = 0;
int time = 0;
// Keep looping until all process are finished
while (N_fin < N_procs){
int target = find_shortest(proc, N_procs, time);
// if such a target exists (initial value is -1)
if (target != -1){
// Note that here is non-preemptive, so every shortest process will be created and executed once only
// No need to check whether the process has been created or not
pid_t chpid = proc_create(proc[target]);
proc_exec( chpid );
proc[target].pid = chpid;
// Loop until the process is finished since it's non-preemptive
while (proc[target].exec_time > 0){
write(proc[target].pipe_fd[1], "run", strlen("run"));
TIME_UNIT();
time++;
proc[target].exec_time--;
}
N_fin++;
// Wait child process
int _return;
waitpid(proc[target].pid, &_return, 0);
if (WIFEXITED(_return) != 1){
fprintf(stderr, "error: child process terminated inappropriately");
return 1;
}
}
// if there is no such target (all non-finished process are not ready yet)
else{
TIME_UNIT();
time++;
}
}
return 0;
}
| [
"e5n41kb9n@gmail.com"
] | e5n41kb9n@gmail.com |
a5d16d0bdb0a64239f3691f33f69993f488e2a3f | bd1fea86d862456a2ec9f56d57f8948456d55ee6 | /000/247/863/CWE78_OS_Command_Injection__wchar_t_file_execlp_64a.c | 5a01812da3bbd079e6d6272c02e393a68af78702 | [] | no_license | CU-0xff/juliet-cpp | d62b8485104d8a9160f29213368324c946f38274 | d8586a217bc94cbcfeeec5d39b12d02e9c6045a2 | refs/heads/master | 2021-03-07T15:44:19.446957 | 2020-03-10T12:45:40 | 2020-03-10T12:45:40 | 246,275,244 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 3,561 | c | /* TEMPLATE GENERATED TESTCASE FILE
Filename: CWE78_OS_Command_Injection__wchar_t_file_execlp_64a.c
Label Definition File: CWE78_OS_Command_Injection.strings.label.xml
Template File: sources-sink-64a.tmpl.c
*/
/*
* @description
* CWE: 78 OS Command Injection
* BadSource: file Read input from a file
* GoodSource: Fixed string
* Sinks: execlp
* BadSink : execute command with wexeclp
* Flow Variant: 64 Data flow: void pointer to data passed from one function to another in different source files
*
* */
#include "std_testcase.h"
#include <wchar.h>
#ifdef _WIN32
#define COMMAND_INT_PATH L"%WINDIR%\\system32\\cmd.exe"
#define COMMAND_INT L"cmd.exe"
#define COMMAND_ARG1 L"/c"
#define COMMAND_ARG2 L"dir "
#define COMMAND_ARG3 data
#else /* NOT _WIN32 */
#include <unistd.h>
#define COMMAND_INT_PATH L"/bin/sh"
#define COMMAND_INT L"sh"
#define COMMAND_ARG1 L"-c"
#define COMMAND_ARG2 L"ls "
#define COMMAND_ARG3 data
#endif
#ifdef _WIN32
#define FILENAME "C:\\temp\\file.txt"
#else
#define FILENAME "/tmp/file.txt"
#endif
#ifdef _WIN32
#include <process.h>
#define EXECLP _wexeclp
#else /* NOT _WIN32 */
#define EXECLP execlp
#endif
#ifndef OMITBAD
/* bad function declaration */
void CWE78_OS_Command_Injection__wchar_t_file_execlp_64b_badSink(void * dataVoidPtr);
void CWE78_OS_Command_Injection__wchar_t_file_execlp_64_bad()
{
wchar_t * data;
wchar_t dataBuffer[100] = COMMAND_ARG2;
data = dataBuffer;
{
/* Read input from a file */
size_t dataLen = wcslen(data);
FILE * pFile;
/* if there is room in data, attempt to read the input from a file */
if (100-dataLen > 1)
{
pFile = fopen(FILENAME, "r");
if (pFile != NULL)
{
/* POTENTIAL FLAW: Read data from a file */
if (fgetws(data+dataLen, (int)(100-dataLen), pFile) == NULL)
{
printLine("fgetws() failed");
/* Restore NUL terminator if fgetws fails */
data[dataLen] = L'\0';
}
fclose(pFile);
}
}
}
CWE78_OS_Command_Injection__wchar_t_file_execlp_64b_badSink(&data);
}
#endif /* OMITBAD */
#ifndef OMITGOOD
/* goodG2B uses the GoodSource with the BadSink */
void CWE78_OS_Command_Injection__wchar_t_file_execlp_64b_goodG2BSink(void * dataVoidPtr);
static void goodG2B()
{
wchar_t * data;
wchar_t dataBuffer[100] = COMMAND_ARG2;
data = dataBuffer;
/* FIX: Append a fixed string to data (not user / external input) */
wcscat(data, L"*.*");
CWE78_OS_Command_Injection__wchar_t_file_execlp_64b_goodG2BSink(&data);
}
void CWE78_OS_Command_Injection__wchar_t_file_execlp_64_good()
{
goodG2B();
}
#endif /* OMITGOOD */
/* Below is the main(). It is only used when building this testcase on
* its own for testing or for building a binary to use in testing binary
* analysis tools. It is not used when compiling all the testcases as one
* application, which is how source code analysis tools are tested.
*/
#ifdef INCLUDEMAIN
int main(int argc, char * argv[])
{
/* seed randomness */
srand( (unsigned)time(NULL) );
#ifndef OMITGOOD
printLine("Calling good()...");
CWE78_OS_Command_Injection__wchar_t_file_execlp_64_good();
printLine("Finished good()");
#endif /* OMITGOOD */
#ifndef OMITBAD
printLine("Calling bad()...");
CWE78_OS_Command_Injection__wchar_t_file_execlp_64_bad();
printLine("Finished bad()");
#endif /* OMITBAD */
return 0;
}
#endif
| [
"frank@fischer.com.mt"
] | frank@fischer.com.mt |
77ffaef4bc572c506373621af90d9f5160f140bb | 5a0c4ce4ea56f3f44ae60ee1112f1e6e965b9364 | /LibraryMFP.framework/Headers/LibraryMFP-Swift.h | 58a361ee7a26c7ee033851399dd6001d7a3ded44 | [
"MIT"
] | permissive | rajarahul12/LibraryMFP | ac270258a1477dfd419d2c93e01824370106aa94 | 7ed24ecadb163e57791d1fc1ce48e92ed21bb14e | refs/heads/master | 2020-04-16T23:35:26.073189 | 2019-01-16T17:02:22 | 2019-01-16T17:02:22 | 166,011,082 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 6,587 | h | // Generated by Apple Swift version 4.2.1 (swiftlang-1000.11.42 clang-1000.11.45.1)
#pragma clang diagnostic push
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typedef float swift_float3 __attribute__((__ext_vector_type__(3)));
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typedef double swift_double3 __attribute__((__ext_vector_type__(3)));
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typedef int swift_int2 __attribute__((__ext_vector_type__(2)));
typedef int swift_int3 __attribute__((__ext_vector_type__(3)));
typedef int swift_int4 __attribute__((__ext_vector_type__(4)));
typedef unsigned int swift_uint2 __attribute__((__ext_vector_type__(2)));
typedef unsigned int swift_uint3 __attribute__((__ext_vector_type__(3)));
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#if !defined(SWIFT_ENUM)
# define SWIFT_ENUM(_type, _name, _extensibility) enum _name : _type _name; enum SWIFT_ENUM_ATTR(_extensibility) SWIFT_ENUM_EXTRA _name : _type
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# define SWIFT_ENUM_NAMED(_type, _name, SWIFT_NAME, _extensibility) enum _name : _type _name SWIFT_COMPILE_NAME(SWIFT_NAME); enum SWIFT_COMPILE_NAME(SWIFT_NAME) SWIFT_ENUM_ATTR(_extensibility) SWIFT_ENUM_EXTRA _name : _type
# else
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# endif
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#if !defined(SWIFT_DEPRECATED_MSG)
# define SWIFT_DEPRECATED_MSG(...) __attribute__((deprecated(__VA_ARGS__)))
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#if __has_feature(attribute_diagnose_if_objc)
# define SWIFT_DEPRECATED_OBJC(Msg) __attribute__((diagnose_if(1, Msg, "warning")))
#else
# define SWIFT_DEPRECATED_OBJC(Msg) SWIFT_DEPRECATED_MSG(Msg)
#endif
#if __has_feature(modules)
#endif
#pragma clang diagnostic ignored "-Wproperty-attribute-mismatch"
#pragma clang diagnostic ignored "-Wduplicate-method-arg"
#if __has_warning("-Wpragma-clang-attribute")
# pragma clang diagnostic ignored "-Wpragma-clang-attribute"
#endif
#pragma clang diagnostic ignored "-Wunknown-pragmas"
#pragma clang diagnostic ignored "-Wnullability"
#if __has_attribute(external_source_symbol)
# pragma push_macro("any")
# undef any
# pragma clang attribute push(__attribute__((external_source_symbol(language="Swift", defined_in="LibraryMFP",generated_declaration))), apply_to=any(function,enum,objc_interface,objc_category,objc_protocol))
# pragma pop_macro("any")
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# pragma clang attribute pop
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#pragma clang diagnostic pop
| [
"rajarahul@Rajas-MacBook-Pro.local"
] | rajarahul@Rajas-MacBook-Pro.local |
144a48d076963fdb482bc1724b2ced8c01a66316 | bade93cbfc1f25160dfbe9493bfa83f853326475 | /mwc/romana/relic/f/usr/include/sys/haiscsi.h | 106602ae6c0478ed03c0fd62e3ea9bad217ee938 | [
"BSD-3-Clause"
] | permissive | gspu/Coherent | c8a9b956b1126ffc34df3c874554ee2eb7194299 | 299bea1bb52a4dcc42a06eabd5b476fce77013ef | refs/heads/master | 2021-12-01T17:49:53.618512 | 2021-11-25T22:27:12 | 2021-11-25T22:27:12 | 214,182,273 | 26 | 6 | null | null | null | null | UTF-8 | C | false | false | 6,948 | h | /***********************************************************************
* Module: haiscsi.h
*
* Constants and structures used to access SCSI devices through the
* SCSI Driver in a Host Adapter inspecific manner.
*
* Copyright (c) 1993, Christopher Sean Hilton, All rights reserved.
*
* Last Modified: Fri Jul 23 15:38:08 1993 by [chris]
*
*/
#ifndef __SYS_HAISCSI_H__
#define __SYS_HAISCSI_H__
#define SCSIMAJOR 13
#define MAXTID 7
#define MAXDEVS (MAXTID + 1)
#define MAXLUN 7
#define MAXUNITS (MAXLUN + 1)
#define ST_GOOD 0x00 /* Status Good. */
#define ST_CHKCOND 0x02 /* Check Condition */
#define ST_CONDMET 0x04 /* Condition Met */
#define ST_BUSY 0x08 /* Busy */
#define ST_INTERM 0x10 /* Intermediate */
#define ST_INTCDMET 0x14 /* Intermediate Condtion Met */
#define ST_RESCONF 0x18 /* Reservation Conflict */
#define ST_COMTERM 0x22 /* Command Terminated */
#define ST_QFULL 0x28 /* Queue Full */
#define ST_TIMEOUT 0x0101 /* Command Timed out */
#define ST_USRABRT 0x0102 /* User pressed ^C */
#define ST_DRVABRT 0x0103 /* Command Aborted by driver */
#define ST_HATMOUT 0x0201 /* Host adapter Timed out command */
#define ST_PENDING 0xffff /* Command Pending */
#define DMAREAD 0x0001 /* Command Reads from SCSI device */
#define DMAWRITE 0x0002 /* Command Writes to SCSI device */
#define SENSELEN 18
#define PHYS_ADDR 0x0000 /* Physical Address - (who knows) */
#define KRNL_ADDR 0x0001 /* Kernal Address */
#define USER_ADDR 0x0002 /* User Address (Anything goes) */
#define SYSGLBL_ADDR 0x0003 /* System Global address (yeah) */
/***** Minor Device Number Bits *****/
#define SPECIAL 0x80 /* Special Bit to flag boot block / Tape */
#define TIDMASK 0x70
#define LUNMASK 0x0c
#define PARTMASK 0x03
#define TAPE 0x01
#define REWIND 0x02
#pragma align 1
typedef struct g0cmd_s *g0cmd_p;
typedef struct g0cmd_s {
unsigned char opcode; /* From opcode Table */
unsigned char lun_lba; /* LUN and high part of LBA */
unsigned char lba_mid; /* LBA Middle. */
unsigned char lba_low; /* LBA Low. */
unsigned char xfr_len; /* Transfer Length */
unsigned char control; /* Control byte. */
} g0cmd_t;
typedef struct g1cmd_s *g1cmd_p;
typedef struct g1cmd_s {
unsigned char opcode; /* From opcode Table */
unsigned char lun; /* LUN */
unsigned long lba; /* LBA */
unsigned char pad1; /* Reserved */
unsigned short xfr_len; /* Transfer Length's MSB. */
unsigned char control; /* Control byte. */
} g1cmd_t;
#define g2cmd_t g1cmd_t /* SCSI-2 Added Group 2 commands */
#define g2cmd_s g1cmd_s /* with the same size and layout as */
#define g2cmd_p g1cmd_p /* g1 commands. */
typedef struct g5cmd_s *g5cmd_p;
typedef struct g5cmd_s {
unsigned char opcode; /* From opcode Table */
unsigned char lun; /* LUN */
unsigned long lba; /* LBA's MSB */
unsigned char pad1[3]; /* Reserved */
unsigned short xfr_len; /* Transfer Length */
unsigned char control; /* Control byte. */
} g5cmd_t;
typedef union cdb_u *cdb_p;
typedef union cdb_u {
g0cmd_t g0;
g1cmd_t g1;
g5cmd_t g5;
} cdb_t;
typedef struct sense_s *sense_p;
typedef struct sense_s {
unsigned char errorcode; /* Error Code: 0x0? */
unsigned char lba_msb; /* LSB's MS 5 Bits */
unsigned char lba_mid; /* Middle 8 bits */
unsigned char lba_lsb; /* LS 8 Bits */
} sense_t;
typedef struct extsense_s *extsense_p;
typedef struct extsense_s {
unsigned char errorcode; /* Error Code (70H) */
unsigned char segmentnum; /* Number of current segment descriptor */
unsigned char sensekey; /* Sense Key(See bit definitions too) */
long info; /* Information MSB */
unsigned char addlen; /* Additional Sense Length */
unsigned char addbytes[1]; /* Additional Sense unsigned chars */
} extsense_t;
#ifdef __KERNEL__
/***** Device Control Array *****/
typedef struct dca_s *dca_p;
typedef struct dca_s {
int (*d_open)(); /* open routine for device */
int (*d_close)(); /* close routine */
int (*d_block)(); /* Block request routine (Strategy) */
int (*d_read)(); /* Character Read routine */
int (*d_write)(); /* Character Write routine */
int (*d_ioctl)(); /* I/O Control routine */
int (*d_load)(); /* Load or Init routine */
int (*d_unload)(); /* Unload routine */
int (*d_poll)(); /* Poll routine */
} dca_t;
typedef struct bufaddr_s *bufaddr_p;
typedef struct bufaddr_s {
int space; /* Address space */
union {
paddr_t paddr; /* Physical Address */
caddr_t caddr; /* Virtual Address */
} addr;
size_t size; /* Size of buffer */
} bufaddr_t;
typedef struct srb_s *srb_p; /* SCSI Request Block */
typedef struct srb_s {
unsigned short status; /* SCSI Status Byte */
unsigned short hastat; /* Host Adapter Status Byte */
dev_t dev; /* Device number (major/minor) */
unsigned char target; /* Target ID */
unsigned char lun; /* Logical Unit Number */
unsigned short tries; /* Current tries */
unsigned short timeout; /* Seconds til timeout */
bufaddr_t buf; /* Buffer to use */
unsigned short xferdir; /* Transfer Direction */
int (*cleanup)(); /* Cleanup Function. */
cdb_t cdb; /* Command to execute */
char sensebuf[SENSELEN];
} srb_t;
#pragma align
#ifdef HA_MODULE
extern dca_p mdca[MAXDEVS];
#else
extern int hapresent;
#endif
/***********************************************************************
* Host Adapter routines.
*
* These must be defined by the host adapter module. For each individual
* routine's functionality see the host adapter module aha154x.c.
*/
extern void hatimer();
extern void haintr();
extern int hainit();
extern int startscsi();
extern void abortscsi();
extern void resetdevice();
extern void haihdgeta();
extern void haihdseta();
extern char iofailmsg[];
extern int HAI_HAID;
#define bit(n) (1 << (n))
#define tid(d) (((d) & TIDMASK) >> 4)
#define lun(d) (((d) & LUNMASK) >> 2)
#define partn(d) (((d) & SPECIAL) ? 4 : ((d) & PARTMASK))
char *swapbytes();
#define flip(o) swapbytes(&(o), sizeof(o))
int cpycdb();
void reqsense();
void doscsi();
void printsense();
int printerror();
void haiioctl();
void hainonblk();
#endif /* KERNEL */
#endif /* !defined( __SYS_HAISCSI_H__ ) */
/* End of file */
| [
"gspurki@gmail.com"
] | gspurki@gmail.com |
00cabebbef4311806ce2be429343957cdbac84dc | f626e876ed8274181de8c0bb96d79901cb836430 | /前馈+反馈LQR控制实验程序/Control_linear_rtwin_win32/rtmodel.h | 2238449607a92b4928f4907d3ed9fcdf58470e1d | [] | no_license | BoZhu-SYSU/3-DOF-helicopter_modeling-identification-verification | 6aca8e2ccd4924091a02d343e15ceec138c1da04 | 83125f3d6158dc1012bfe2cff789a28d845be6d7 | refs/heads/master | 2023-05-07T01:03:15.301614 | 2021-05-28T13:09:15 | 2021-05-28T13:09:15 | 371,642,709 | 6 | 3 | null | null | null | null | UTF-8 | C | false | false | 724 | h | /*
* rtmodel.h:
*
* Code generation for model "Control_linear".
*
* Model version : 1.1019
* Simulink Coder version : 8.3 (R2012b) 20-Jul-2012
* C source code generated on : Wed Aug 17 19:48:18 2016
*
* Target selection: rtwin.tlc
* Note: GRT includes extra infrastructure and instrumentation for prototyping
* Embedded hardware selection: 32-bit Generic
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#ifndef RTW_HEADER_rtmodel_h_
#define RTW_HEADER_rtmodel_h_
/*
* Includes the appropriate headers when we are using rtModel
*/
#include "Control_linear.h"
#define GRTINTERFACE 1
#endif /* RTW_HEADER_rtmodel_h_ */
| [
"zhubo5@mail.sysu.edu.cn"
] | zhubo5@mail.sysu.edu.cn |
60ba1d5bb40590cfd16ab672722432efc5c86bb1 | ed69832fb338e34f343abbf188b4503d7be2e824 | /libftprintf/libft/get_next_line.c | ffd6c4748d1adba33270afcda56fdf63c0f272e4 | [] | no_license | oozkaya/42_corewar | 6561ba6c8a33759ea57a13cf9bcf05c087d5d904 | b6c7bbf4b2774cf75b5001b47e6603cd1facdad3 | refs/heads/master | 2023-02-02T19:41:35.926299 | 2019-05-03T11:50:28 | 2019-05-03T11:50:28 | 322,843,917 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,298 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* get_next_line.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: ade-verd <ade-verd@student.42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2017/12/05 16:13:45 by ade-verd #+# #+# */
/* Updated: 2019/03/05 13:54:23 by ade-verd ### ########.fr */
/* */
/* ************************************************************************** */
#include "get_next_line.h"
/*
** get_next_line
** Extracts a line from fd.
** A line is ended by '\n' or EOF (End Of File)
**
** Return
** (1) A line is read | (0) Reading is over | (-1) Error
*/
static t_list *ft_check_fd(t_list **begin, int fd)
{
t_list *file;
file = *begin;
while (file)
{
if (fd == (int)file->content_size)
return (file);
file = file->next;
}
file = ft_lstnew("\0", 1);
file->content_size = fd;
ft_lstadd(begin, file);
return (file);
}
static int new_content(t_list *f, int ret)
{
char *tmp;
tmp = f->content;
if (!(f->content = ft_strdup(f->content + ret)))
return (0);
ft_memdel((void**)&tmp);
return (1);
}
int get_next_line(int const fd, char **line)
{
static t_list *f;
t_list *begin;
char buf[BUFF_SIZE + 1];
int ret;
if (fd < 0 || !line || read(fd, buf, 0) < 0 || BUFF_SIZE < 0)
return (-1);
begin = f;
f = ft_check_fd(&begin, fd);
ft_bzero(buf, BUFF_SIZE + 1);
while (!ft_memchr(f->content, '\n', ft_strlen(f->content) + 1)
&& (ret = read(fd, buf, BUFF_SIZE)))
if (!(f->content = ft_strnjoinfree(f->content, buf, ret, 0)))
return (-1);
ret = 0;
while (((char *)f->content)[ret] && ((char *)f->content)[ret] != '\n')
++ret;
if (!(*line = ft_strndup(f->content, ret)))
return (-1);
(((char *)f->content)[ret] == '\n') ? ++ret : 0;
if (!(new_content(f, ret)))
return (-1);
f = begin;
return (ret ? 1 : 0);
}
| [
"oozkaya@e1r12p8.42.fr"
] | oozkaya@e1r12p8.42.fr |
eb27e0851a3f997d5d7827f6be94ea99c67a13c8 | 306b6f3bda83a13810125e439fe43debf71f1942 | /0.2.6/src/wl/sys/wlc_scb.c | 888e2e9db0b7fcca6308f9f12eff65b280ee541b | [] | no_license | yskcg/wifi-bcm | bfe3cc2861f9e4196d4a0da74bd42e007b1ba79a | ac5c76886fb2baf025501ca38c16ecacde8f815c | refs/heads/master | 2021-01-21T16:27:54.772401 | 2017-07-08T16:23:31 | 2017-07-08T16:23:31 | 91,888,046 | 6 | 0 | null | null | null | null | UTF-8 | C | false | false | 50,906 | c | /*
* Common interface to the 802.11 Station Control Block (scb) structure
*
* Copyright (C) 2010, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: wlc_scb.c,v 1.227.10.17 2011-01-07 22:52:13 Exp $
*/
#include <wlc_cfg.h>
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <bcmendian.h>
#include <proto/802.11.h>
#include <proto/wpa.h>
#include <sbconfig.h>
#include <pcicfg.h>
#include <bcmsrom.h>
#include <wlioctl.h>
#include <epivers.h>
#include <d11.h>
#include <wlc_rate.h>
#include <wlc_pub.h>
#include <wlc_key.h>
#include <wlc_bsscfg.h>
#include <wlc.h>
#include <wlc_scb.h>
#include <wlc_phy_hal.h>
#include <wlc_antsel.h>
#include <wl_export.h>
#include <wlc_ap.h>
#include <wlc_rate_sel.h>
#include <wlc_assoc.h>
#define SCB_MAX_CUBBY 16 /* max number of cubbies in container */
#define SCB_MAGIC 0x0505a5a5
#define INTERNAL_SCB 0x00000001
#define USER_SCB 0x00000002
#define SCBHASHINDEX(hash, id) ((id[3] ^ id[4] ^ id[5]) % (hash))
/* structure for storing per-cubby client info */
typedef struct cubby_info {
scb_cubby_init_t fn_init; /* fn called during scb malloc */
scb_cubby_deinit_t fn_deinit; /* fn called during scb free */
scb_cubby_dump_t fn_dump; /* fn called during scb dump */
void *context; /* context to be passed to all cb fns */
} cubby_info_t;
/* structure for storing public and private global scb module state */
struct scb_module {
wlc_pub_t *pub; /* public part of wlc */
struct scb *scb; /* station control block link list */
uint16 nscb; /* total number of allocated scbs */
struct scb **scbhash[MAXBANDS]; /* station control block hash */
uint scbtotsize; /* total scb size including container */
uint ncubby; /* current num of cubbies */
cubby_info_t *cubby_info; /* cubby client info */
uint8 nscbhash;
#ifdef SCBFREELIST
struct scb *free_list; /* Free list of SCBs */
#endif
};
/* station control block - one per remote MAC address */
struct scb_info {
struct scb *scbpub; /* public portion of scb */
struct scb_info *hashnext; /* pointer to next scb under same hash entry */
struct scb_info *next; /* pointer to next allocated scb */
struct wlcband *band; /* pointer to our associated band */
#ifdef MACOSX
struct scb_info *hashnext_copy;
struct scb_info *next_copy;
#endif
};
/* Helper macro for txpath in scb */
/* A feature in Tx path goes through following states:
* Unregisterd -> Registered [Global state]
* Registerd -> Configured -> Active -> Configured [Per-scb state]
*/
/* Set the next feature of given feature */
#define SCB_TXMOD_SET(scb, fid, _next_fid) { \
scb->tx_path[fid].next_tx_fn = wlc->txmod_fns[_next_fid].tx_fn; \
scb->tx_path[fid].next_handle = wlc->txmod_fns[_next_fid].ctx; \
}
static void wlc_scb_hash_add(wlc_info_t *wlc, struct scb *scb, int bandunit);
static void wlc_scb_hash_del(wlc_info_t *wlc, struct scb *scbd, int bandunit);
static struct scb *wlc_scbvictim(wlc_info_t *wlc);
static struct scb *wlc_scb_getnext(struct scb *scb);
static int wlc_scbinit(wlc_info_t *wlc, struct wlcband *band, struct scb_info *scbinfo,
uint32 scbflags);
static void wlc_scb_reset(scb_module_t *scbstate, struct scb_info *scbinfo);
static struct scb_info *wlc_scb_allocmem(scb_module_t *scbstate);
static void wlc_scb_freemem(scb_module_t *scbstate, struct scb_info *scbinfo);
#ifdef MFP
static void scb_sa_query_timeout(void *arg);
#endif
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
static int wlc_dump_scb(wlc_info_t *wlc, struct bcmstrbuf *b);
/* Dump the active txpath for the current SCB */
static int wlc_scb_txpath_dump(wlc_info_t *wlc, struct scb *scb, struct bcmstrbuf *b);
/* SCB Flags Names Initialization */
static const bcm_bit_desc_t scb_flags[] =
{
{SCB_NONERP, "NonERP"},
{SCB_LONGSLOT, "LgSlot"},
{SCB_SHORTPREAMBLE, "ShPre"},
{SCB_8021XHDR, "1X"},
{SCB_WPA_SUP, "WPASup"},
{SCB_DEAUTH, "DeA"},
{SCB_WMECAP, "WME"},
#ifdef WLAFTERBURNER
{SCB_ABCAP, "ABCAP"},
#endif /* WLAFTERBURNER */
{SCB_BRCM, "BRCM"},
{SCB_WDS_LINKUP, "WDSLinkUP"},
{SCB_LEGACY_AES, "LegacyAES"},
{SCB_LEGACY_CRAM, "LegacyCRAM"},
{SCB_MYAP, "MyAP"},
{SCB_PENDING_PROBE, "PendingProbe"},
{SCB_AMSDUCAP, "AMSDUCAP"},
{SCB_BACAP, "BACAP"},
{SCB_HTCAP, "HT"},
{SCB_RECV_PM, "RECV_PM"},
{SCB_AMPDUCAP, "AMPDUCAP"},
{SCB_IS40, "40MHz"},
{SCB_NONGF, "NONGFCAP"},
{SCB_APSDCAP, "APSDCAP"},
{SCB_PENDING_FREE, "PendingFree"},
{SCB_PENDING_PSPOLL, "PendingPSPoll"},
{SCB_RIFSCAP, "RIFSCAP"},
{SCB_HT40INTOLERANT, "40INTOL"},
{SCB_WMEPS, "WMEPSOK"},
{SCB_COEX_MGMT, "OBSSCoex"},
{SCB_IBSS_PEER, "IBSS Peer"},
{SCB_STBCCAP, "STBC"},
#ifdef WLBTAMP
{SCB_11ECAP, "11e"},
#endif
{0, NULL}
};
static const bcm_bit_desc_t scb_flags2[] =
{
{SCB2_SGI20_CAP, "SGI20"},
{SCB2_SGI40_CAP, "SGI40"},
{SCB2_LDPCCAP, "LDPC"},
{0, NULL}
};
static const bcm_bit_desc_t scb_states[] =
{
{AUTHENTICATED, "AUTH"},
{ASSOCIATED, "ASSOC"},
{PENDING_AUTH, "AUTH_PEND"},
{PENDING_ASSOC, "ASSOC_PEND"},
{AUTHORIZED, "AUTH_8021X"},
{TAKEN4IBSS, "IBSS"},
{0, NULL}
};
#endif /* BCMDBG || BCMDBG_DUMP */
#ifdef SCBFREELIST
static void wlc_scbfreelist_free(scb_module_t *scbstate);
#endif
#define SCBINFO(_scb) (_scb ? (struct scb_info *)((_scb)->scb_priv) : NULL)
#ifdef MACOSX
#ifdef panic
#undef panic
void panic(const char *str, ...);
#endif
#define SCBSANITYCHECK(_scb) { \
if (((_scb) != NULL) && \
((((_scb))->magic != SCB_MAGIC) || \
(SCBINFO(_scb)->hashnext != SCBINFO(_scb)->hashnext_copy) || \
(SCBINFO(_scb)->next != SCBINFO(_scb)->next_copy))) \
panic("scbinfo corrupted: magic: 0x%x hn: %p hnc: %p n: %p nc: %p\n", \
((_scb))->magic, SCBINFO(_scb)->hashnext, \
SCBINFO(_scb)->hashnext_copy, \
SCBINFO(_scb)->next, SCBINFO(_scb)->next_copy); \
}
#define SCBFREESANITYCHECK(_scb) { \
if (((_scb) != NULL) && \
((((_scb))->magic != ~SCB_MAGIC) || \
(SCBINFO(_scb)->next != SCBINFO(_scb)->next_copy))) \
panic("scbinfo corrupted: magic: 0x%x hn: %p hnc: %p n: %p nc: %p\n", \
((_scb))->magic, SCBINFO(_scb)->hashnext, \
SCBINFO(_scb)->hashnext_copy, \
SCBINFO(_scb)->next, SCBINFO(_scb)->next_copy); \
}
#else
#define SCBSANITYCHECK(_scbinfo) do {} while (0)
#define SCBFREESANITYCHECK(_scbinfo) do {} while (0)
#endif /* MACOSX */
scb_module_t *
BCMATTACHFN(wlc_scb_attach)(wlc_pub_t *pub, wlc_info_t *wlc)
{
scb_module_t *scbstate;
int len, i;
uint8 nscbhash;
nscbhash = ((pub->tunables->maxscb + 7)/8); /* # scb hash buckets */
len = sizeof(scb_module_t) + (sizeof(cubby_info_t) * SCB_MAX_CUBBY)
+ (sizeof(struct scb *) * MAXBANDS * nscbhash);
if ((scbstate = MALLOC(pub->osh, len)) == NULL)
return NULL;
bzero((char *)scbstate, len);
scbstate->pub = pub;
scbstate->cubby_info = (cubby_info_t *)((uintptr)scbstate + sizeof(scb_module_t));
scbstate->nscbhash = nscbhash; /* # scb hash buckets */
for (i = 0; i < MAXBANDS; i++) {
scbstate->scbhash[i] = (struct scb **)((uintptr)scbstate->cubby_info +
(sizeof(cubby_info_t) * SCB_MAX_CUBBY) +
(i * scbstate->nscbhash * sizeof(struct scb *)));
}
scbstate->scbtotsize = sizeof(struct scb);
scbstate->scbtotsize += sizeof(int) * MA_WINDOW_SZ; /* sizeof rssi_window */
scbstate->scbtotsize += sizeof(struct tx_path_node) * TXMOD_LAST;
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
wlc_dump_register(pub, "scb", (dump_fn_t)wlc_dump_scb, (void *)wlc);
#endif
return scbstate;
}
void
BCMATTACHFN(wlc_scb_detach)(scb_module_t *scbstate)
{
int len;
if (!scbstate)
return;
#ifdef SCBFREELIST
wlc_scbfreelist_free(scbstate);
#endif
ASSERT(scbstate->nscb == 0);
len = sizeof(scb_module_t) + (sizeof(cubby_info_t) * SCB_MAX_CUBBY)
+ (sizeof(struct scb *) * MAXBANDS * scbstate->nscbhash);
MFREE(scbstate->pub->osh, scbstate, len);
}
/* Methods for iterating along a list of scb */
/* Direct access to the next */
static struct scb *
wlc_scb_getnext(struct scb *scb)
{
if (scb) {
SCBSANITYCHECK(scb);
return (SCBINFO(scb)->next ? SCBINFO(scb)->next->scbpub : NULL);
}
return NULL;
}
/* Initialize an iterator keeping memory of the next scb as it moves along the list */
void
wlc_scb_iterinit(scb_module_t *scbstate, struct scb_iter *scbiter)
{
ASSERT(scbiter != NULL);
SCBSANITYCHECK(scbstate->scb);
/* Prefetch next scb, so caller can free an scb before going on to the next */
scbiter->next = scbstate->scb;
}
/* move the iterator */
struct scb *
wlc_scb_iternext(struct scb_iter *scbiter)
{
struct scb *scb;
ASSERT(scbiter != NULL);
if ((scb = scbiter->next)) {
SCBSANITYCHECK(scb);
scbiter->next = (SCBINFO(scb)->next ? SCBINFO(scb)->next->scbpub : NULL);
} else
scbiter->next = NULL;
return scb;
}
/*
* Accessors, nagative values are errors.
*/
int
BCMATTACHFN(wlc_scb_cubby_reserve)(wlc_info_t *wlc, uint size, scb_cubby_init_t fn_init,
scb_cubby_deinit_t fn_deinit, scb_cubby_dump_t fn_dump, void *context)
{
uint offset;
scb_module_t *scbstate = wlc->scbstate;
cubby_info_t *cubby_info;
ASSERT(scbstate->nscb == 0);
ASSERT((scbstate->scbtotsize % PTRSZ) == 0);
ASSERT(scbstate->ncubby < SCB_MAX_CUBBY);
if (scbstate->ncubby >= SCB_MAX_CUBBY) {
ASSERT(0);
return -1;
}
/* housekeeping info is stored in scb_module struct */
cubby_info = &scbstate->cubby_info[scbstate->ncubby++];
cubby_info->fn_init = fn_init;
cubby_info->fn_deinit = fn_deinit;
cubby_info->fn_dump = fn_dump;
cubby_info->context = context;
/* actual cubby data is stored at the end of scb's */
offset = scbstate->scbtotsize;
/* roundup to pointer boundary */
scbstate->scbtotsize = ROUNDUP(scbstate->scbtotsize + size, PTRSZ);
return offset;
}
struct wlcband *
wlc_scbband(struct scb *scb)
{
return SCBINFO(scb)->band;
}
#ifdef SCBFREELIST
static
struct scb_info *wlc_scbget_free(scb_module_t *scbstate)
{
struct scb_info *ret = NULL;
if (scbstate->free_list == NULL)
return NULL;
ret = SCBINFO(scbstate->free_list);
SCBFREESANITYCHECK(ret->scbpub);
scbstate->free_list = (ret->next ? ret->next->scbpub : NULL);
#ifdef MACOSX
ret->next_copy = NULL;
#endif
ret->next = NULL;
return ret;
}
static
void wlc_scbadd_free(scb_module_t *scbstate, struct scb_info *ret)
{
SCBFREESANITYCHECK(scbstate->free_list);
ret->next = SCBINFO(scbstate->free_list);
scbstate->free_list = ret->scbpub;
#ifdef MACOSX
ret->scbpub->magic = ~SCB_MAGIC;
ret->next_copy = ret->next;
#endif
}
static
void wlc_scbfreelist_free(scb_module_t *scbstate)
{
struct scb_info *ret = NULL;
ret = SCBINFO(scbstate->free_list);
while (ret) {
#ifdef MACOSX
SCBFREESANITYCHECK(ret->scbpub);
#endif
scbstate->free_list = (ret->next ? ret->next->scbpub : NULL);
wlc_scb_freemem(scbstate, ret);
ret = scbstate->free_list ? SCBINFO(scbstate->free_list) : NULL;
}
}
#endif /* MACOSX */
void
wlc_internalscb_free(wlc_info_t *wlc, struct scb *scb)
{
scb->permanent = FALSE;
wlc_scbfree(wlc, scb);
}
static void
wlc_scb_reset(scb_module_t *scbstate, struct scb_info *scbinfo)
{
struct scb *scbpub = scbinfo->scbpub;
bzero((char*)scbinfo, sizeof(struct scb_info));
scbinfo->scbpub = scbpub;
bzero(scbpub, scbstate->scbtotsize);
scbpub->scb_priv = (void *) scbinfo;
/* init substructure pointers */
scbpub->rssi_window = (int *)((char *)scbpub + sizeof(struct scb));
scbpub->tx_path = (struct tx_path_node *)
((char *)scbpub->rssi_window + (sizeof(int)*MA_WINDOW_SZ));
}
static struct scb_info *
wlc_scb_allocmem(scb_module_t *scbstate)
{
struct scb_info *scbinfo = NULL;
struct scb *scbpub;
scbinfo = MALLOC(scbstate->pub->osh, sizeof(struct scb_info));
if (!scbinfo) {
WL_ERROR(("wl%d: %s: Internalscb alloc failure\n", scbstate->pub->unit,
__FUNCTION__));
return NULL;
}
scbpub = MALLOC(scbstate->pub->osh, scbstate->scbtotsize);
if (!scbpub) {
wlc_scb_freemem(scbstate, scbinfo);
WL_ERROR(("wl%d: %s: Internalscb alloc failure\n", scbstate->pub->unit,
__FUNCTION__));
return NULL;
}
scbinfo->scbpub = scbpub;
wlc_scb_reset(scbstate, scbinfo);
return scbinfo;
}
struct scb *
wlc_internalscb_alloc(wlc_info_t *wlc, const struct ether_addr *ea, struct wlcband *band)
{
struct scb_info *scbinfo = NULL;
scb_module_t *scbstate = wlc->scbstate;
int bcmerror = 0;
#ifdef SCBFREELIST
/* If not found on freelist then allocate a new one */
if ((scbinfo = wlc_scbget_free(scbstate)) == NULL) {
#endif
scbinfo = wlc_scb_allocmem(scbstate);
if (!scbinfo)
return NULL;
#ifdef SCBFREELIST
}
#endif
wlc_scb_reset(scbstate, scbinfo);
bcmerror = wlc_scbinit(wlc, band, scbinfo, INTERNAL_SCB);
if (bcmerror) {
wlc_internalscb_free(wlc, scbinfo->scbpub);
WL_ERROR(("wl%d: %s failed with err %d\n", wlc->pub->unit, __FUNCTION__, bcmerror));
return NULL;
}
scbinfo->scbpub->permanent = TRUE;
bcopy(ea, &scbinfo->scbpub->ea, sizeof(struct ether_addr));
wlc_scb_set_bsscfg(scbinfo->scbpub, wlc->cfg);
return (scbinfo->scbpub);
}
struct scb *
wlc_userscb_alloc(wlc_info_t *wlc, struct wlcband *band)
{
scb_module_t *scbstate = wlc->scbstate;
struct scb_info *scbinfo = NULL;
struct scb *oldscb;
int bcmerror;
if (scbstate->nscb < wlc->pub->tunables->maxscb) {
scbinfo = wlc_scb_allocmem(scbstate);
if (!scbinfo) {
WL_ERROR(("wl%d: %s: out of memory, malloced %d bytes\n",
wlc->pub->unit, __FUNCTION__, MALLOCED(wlc->osh)));
}
}
if (!scbinfo) {
/* free the oldest entry */
if (!(oldscb = wlc_scbvictim(wlc))) {
WL_ERROR(("wl%d: %s: no SCBs available to reclaim\n",
wlc->pub->unit, __FUNCTION__));
return NULL;
}
if (!wlc_scbfree(wlc, oldscb)) {
WL_ERROR(("wl%d: %s: Couldn't free a victimized scb\n",
wlc->pub->unit, __FUNCTION__));
return NULL;
}
ASSERT(scbstate->nscb < wlc->pub->tunables->maxscb);
/* allocate memory for scb */
if (!(scbinfo = wlc_scb_allocmem(scbstate))) {
WL_ERROR(("wl%d: %s: out of memory(FAIL), malloced %d bytes\n",
wlc->pub->unit, __FUNCTION__, MALLOCED(wlc->osh)));
return NULL;
}
}
scbstate->nscb++;
SCBSANITYCHECK((scbstate)->scb);
/* update scb link list */
wlc_scb_reset(scbstate, scbinfo);
scbinfo->next = SCBINFO(scbstate->scb);
#ifdef MACOSX
scbinfo->next_copy = scbinfo->next;
#endif
scbstate->scb = scbinfo->scbpub;
bcmerror = wlc_scbinit(wlc, band, scbinfo, USER_SCB);
if (bcmerror) {
WL_ERROR(("wl%d: %s failed with err %d\n", wlc->pub->unit, __FUNCTION__, bcmerror));
wlc_scbfree(wlc, scbinfo->scbpub);
return NULL;
}
wlc_scb_set_bsscfg(scbinfo->scbpub, wlc->cfg);
return (scbinfo->scbpub);
}
static int
wlc_scbinit(wlc_info_t *wlc, struct wlcband *band, struct scb_info *scbinfo, uint32 scbflags)
{
struct scb *scb = NULL;
scb_module_t *scbstate = wlc->scbstate;
cubby_info_t *cubby_info;
uint i;
int bcmerror = 0;
scb = scbinfo->scbpub;
ASSERT(scb != NULL);
scb->used = wlc->pub->now;
scbinfo->band = band;
for (i = 0; i < NUMPRIO; i++)
scb->seqctl[i] = 0xFFFF;
scb->seqctl_nonqos = 0xFFFF;
#ifdef MACOSX
scb->magic = SCB_MAGIC;
#endif
if (scbflags & INTERNAL_SCB)
scb->flags2 |= SCB2_INTERNAL;
for (i = 0; i < scbstate->ncubby; i++) {
cubby_info = &scbstate->cubby_info[i];
if (cubby_info->fn_init) {
bcmerror = cubby_info->fn_init(cubby_info->context, scb);
if (bcmerror) {
WL_ERROR(("wl%d: %s: Cubby failed\n",
wlc->pub->unit, __FUNCTION__));
return bcmerror;
}
}
}
#ifdef MFP
if (!(scb->sa_query_timer = wl_init_timer(wlc->wl, scb_sa_query_timeout, scb, "sa_query")))
bcmerror = BCME_ERROR;
#endif /* MFP */
return bcmerror;
}
static void
wlc_scb_freemem(scb_module_t *scbstate, struct scb_info *scbinfo)
{
if (scbinfo->scbpub)
MFREE(scbstate->pub->osh, scbinfo->scbpub, scbstate->scbtotsize);
MFREE(scbstate->pub->osh, scbinfo, sizeof(struct scb_info));
}
bool
wlc_scbfree(wlc_info_t *wlc, struct scb *scbd)
{
struct scb_info *remove = SCBINFO(scbd);
struct scb_info *scbinfo;
scb_module_t *scbstate = wlc->scbstate;
cubby_info_t *cubby_info;
uint i;
uint8 prio;
#if defined(BCMDBG) || defined(WLMSG_WSEC)
char eabuf[ETHER_ADDR_STR_LEN];
#endif /* BCMDBG || WLMSG_WSEC */
if (scbd->permanent)
return FALSE;
/* Return if SCB is already being deleted else mark it */
if (scbd->flags & SCB_PENDING_FREE)
return FALSE;
else
scbd->flags |= SCB_PENDING_FREE;
#ifdef MFP
if (scbd->sa_query_timer) {
wl_free_timer(wlc->wl, scbd->sa_query_timer);
scbd->sa_query_timer = NULL;
}
#endif /* MFP */
/* free the per station key if one exists */
if (scbd->key) {
WL_WSEC(("wl%d: %s: deleting pairwise key for %s\n", wlc->pub->unit,
__FUNCTION__, bcm_ether_ntoa(&scbd->ea, eabuf)));
ASSERT(!bcmp((char*)&scbd->key->ea, (char*)&scbd->ea, ETHER_ADDR_LEN));
wlc_key_scb_delete(wlc, scbd);
}
for (i = 0; i < scbstate->ncubby; i++) {
cubby_info = &scbstate->cubby_info[i];
if (cubby_info->fn_deinit)
cubby_info->fn_deinit(cubby_info->context, scbd);
}
#ifdef AP
/* free any leftover authentication state */
if (scbd->challenge) {
MFREE(wlc->osh, scbd->challenge, 2 + scbd->challenge[1]);
scbd->challenge = NULL;
}
/* free WDS state */
if (scbd->wds != NULL) {
if (scbd->wds->wlif) {
wlc_if_event(wlc, WLC_E_IF_DEL, scbd->wds);
wl_del_if(wlc->wl, scbd->wds->wlif);
scbd->wds->wlif = NULL;
}
wlc_wlcif_free(wlc, wlc->osh, scbd->wds);
scbd->wds = NULL;
}
/* free wpaie if stored */
if (scbd->wpaie) {
MFREE(wlc->osh, scbd->wpaie, scbd->wpaie_len);
scbd->wpaie_len = 0;
scbd->wpaie = NULL;
}
#endif /* AP */
/* free any frame reassembly buffer */
for (prio = 0; prio < NUMPRIO; prio++) {
if (scbd->fragbuf[prio]) {
PKTFREE(wlc->osh, scbd->fragbuf[prio], FALSE);
scbd->fragbuf[prio] = NULL;
scbd->fragresid[prio] = 0;
}
}
scbd->state = 0;
if (!SCB_INTERNAL(scbd)) {
if (!ETHER_ISMULTI(scbd->ea.octet)) {
wlc_scb_hash_del(wlc, scbd, remove->band->bandunit);
}
/* delete it from the link list */
scbinfo = SCBINFO(scbstate->scb);
if (scbinfo == remove) {
scbstate->scb = wlc_scb_getnext(scbd);
} else {
while (scbinfo) {
SCBSANITYCHECK(scbinfo->scbpub);
if (scbinfo->next == remove) {
scbinfo->next = remove->next;
#ifdef MACOSX
scbinfo->next_copy = scbinfo->next;
#endif
break;
}
scbinfo = scbinfo->next;
}
ASSERT(scbinfo != NULL);
}
#ifdef AP
/* mark the aid unused */
if (scbd->aid) {
ASSERT(AID2AIDMAP(scbd->aid) < wlc->pub->tunables->maxscb);
clrbit(scbd->bsscfg->aidmap, AID2AIDMAP(scbd->aid));
}
#endif /* AP */
/* update total allocated scb number */
scbstate->nscb--;
}
#ifdef SCBFREELIST
wlc_scbadd_free(scbstate, remove);
#else
/* free scb memory */
wlc_scb_freemem(scbstate, remove);
#endif
return TRUE;
}
/* free all scbs, unless permanent. Force indicates reclaim permanent as well */
void
wlc_scbclear(struct wlc_info *wlc, bool force)
{
struct scb_iter scbiter;
struct scb *scb;
if (wlc->scbstate == NULL)
return;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (force)
scb->permanent = FALSE;
wlc_scbfree(wlc, scb);
}
if (force)
ASSERT(wlc->scbstate->nscb == 0);
}
static struct scb *
wlc_scbvictim(wlc_info_t *wlc)
{
uint oldest;
struct scb *scb;
struct scb *oldscb;
uint now, age;
struct scb_iter scbiter;
#if defined(BCMDBG) || defined(WLMSG_ASSOC)
char eabuf[ETHER_ADDR_STR_LEN];
#endif /* BCMDBG || WLMSG_ASSOC */
wlc_bsscfg_t *bsscfg = NULL;
#ifdef AP
/* search for an unauthenticated scb */
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (!scb->permanent && (scb->state == UNAUTHENTICATED))
return scb;
}
#endif /* AP */
/* free the oldest scb */
now = wlc->pub->now;
oldest = 0;
oldscb = NULL;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
bsscfg = SCB_BSSCFG(scb);
ASSERT(bsscfg != NULL);
if (BSSCFG_STA(bsscfg) && bsscfg->BSS && SCB_ASSOCIATED(scb))
continue;
if (!scb->permanent && ((age = (now - scb->used)) >= oldest)) {
oldest = age;
oldscb = scb;
}
}
/* handle extreme case(s): all are permanent ... or there are no scb's at all */
if (oldscb == NULL)
return NULL;
#ifdef AP
bsscfg = SCB_BSSCFG(oldscb);
if (BSSCFG_AP(bsscfg)) {
/* if the oldest authenticated SCB has only been idle a short time then
* it is not a candidate to reclaim
*/
if (oldest < SCB_SHORT_TIMEOUT)
return NULL;
/* notify the station that we are deauthenticating it */
(void)wlc_senddeauth(wlc, &oldscb->ea, &bsscfg->BSSID,
&bsscfg->cur_etheraddr,
oldscb, DOT11_RC_INACTIVITY);
wlc_deauth_complete(wlc, bsscfg, WLC_E_STATUS_SUCCESS, &oldscb->ea,
DOT11_RC_INACTIVITY, 0);
}
#endif /* AP */
WL_ASSOC(("wl%d: %s: relcaim scb %s, idle %d sec\n", wlc->pub->unit, __FUNCTION__,
bcm_ether_ntoa(&oldscb->ea, eabuf), oldest));
return oldscb;
}
/* "|" operation. */
void
wlc_scb_setstatebit(struct scb *scb, uint8 state)
{
WL_NONE(("set state %x\n", state));
ASSERT(scb != NULL);
if (state & AUTHENTICATED)
{
scb->state &= ~PENDING_AUTH;
}
if (state & ASSOCIATED)
{
ASSERT((scb->state | state) & AUTHENTICATED);
scb->state &= ~PENDING_ASSOC;
}
#if defined(BCMDBG) || defined(WLMSG_ASSOC)
if (state & AUTHORIZED)
{
if (!((scb->state | state) & ASSOCIATED) && !SCB_WDS(scb) &&
!SCB_IS_IBSS_PEER(scb)) {
char eabuf[ETHER_ADDR_STR_LEN];
WL_ASSOC(("wlc_scb : authorized %s is not a associated station, "
"state = %x\n", bcm_ether_ntoa(&scb->ea, eabuf),
scb->state));
}
}
#endif /* BCMDBG || WLMSG_ASSOC */
scb->state |= state;
WL_NONE(("wlc_scb : state = %x\n", scb->state));
}
/* "& ~" operation */
void
wlc_scb_clearstatebit(struct scb *scb, uint8 state)
{
ASSERT(scb != NULL);
WL_NONE(("clear state %x\n", state));
scb->state &= ~state;
WL_NONE(("wlc_scb : state = %x\n", scb->state));
}
/* "|" operation . idx = position of the bsscfg in the wlc array of multi ssids.
*/
void
wlc_scb_setstatebit_bsscfg(struct scb *scb, uint8 state, int idx)
{
ASSERT(scb != NULL);
WL_NONE(("set state : %x bsscfg idx : %d\n", state, idx));
if (state & ASSOCIATED)
{
ASSERT(SCB_AUTHENTICATED_BSSCFG(scb, idx));
/* clear all bits (idx is set below) */
memset(&scb->auth_bsscfg, 0, SCB_BSSCFG_BITSIZE);
scb->state &= ~PENDING_ASSOC;
}
if (state & AUTHORIZED)
{
ASSERT(SCB_ASSOCIATED_BSSCFG(scb, idx));
}
setbit(&scb->auth_bsscfg, idx);
scb->state |= state;
WL_NONE(("wlc_scb : state = %x\n", scb->state));
}
/*
* "& ~" operation .
* idx = position of the bsscfg in the wlc array of multi ssids.
*/
void
wlc_scb_clearstatebit_bsscfg(struct scb *scb, uint8 state, int idx)
{
int i;
ASSERT(scb != NULL);
WL_NONE(("clear state : %x bsscfg idx : %d\n", state, idx));
/*
any clear of a stable state should lead to clear a bit
Warning though : this implies that, if we want to switch from
associated to authenticated, the clear happens before the set
otherwise this bit will be clear in authenticated state.
*/
if ((state & AUTHENTICATED) || (state & ASSOCIATED) || (state & AUTHORIZED))
{
clrbit(&scb->auth_bsscfg, idx);
}
/* quik hack .. clear first ... */
scb->state &= ~state;
for (i = 0; i < SCB_BSSCFG_BITSIZE; i++)
{
/* reset if needed */
if (scb->auth_bsscfg[i])
{
scb->state |= state;
break;
}
}
}
/* reset all state. */
void
wlc_scb_resetstate(struct scb *scb)
{
WL_NONE(("reset state\n"));
ASSERT(scb != NULL);
memset(&scb->auth_bsscfg, 0, SCB_BSSCFG_BITSIZE);
scb->state = 0;
WL_NONE(("wlc_scb : state = %x\n", scb->state));
}
void
wlc_scb_ratesel_init_all(wlc_info_t *wlc)
{
struct scb *scb;
struct scb_iter scbiter;
FOREACHSCB(wlc->scbstate, &scbiter, scb)
wlc_scb_ratesel_init(wlc, scb);
}
void
wlc_scb_ratesel_init_bss(wlc_info_t *wlc, wlc_bsscfg_t *cfg)
{
struct scb *scb;
struct scb_iter scbiter;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (SCB_BSSCFG(scb) == cfg)
wlc_scb_ratesel_init(wlc, scb);
}
}
/* initialize per-scb state utilized by rate selection */
void
wlc_scb_ratesel_init(wlc_info_t *wlc, struct scb *scb)
{
bool is40 = FALSE;
int8 sgi_tx = OFF;
uint8 active_antcfg_num = 0;
uint8 antselid_init = 0;
int32 ac;
if (SCB_INTERNAL(scb))
return;
#ifdef WL11N
if (WLANTSEL_ENAB(wlc))
wlc_antsel_ratesel(wlc->asi, &active_antcfg_num, &antselid_init);
is40 = ((scb->flags & SCB_IS40) ? TRUE : FALSE) &&
wlc->band->mimo_cap_40 && CHSPEC_IS40(wlc->chanspec);
if (wlc->sgi_tx == AUTO) {
if ((is40 && (scb->flags2 & SCB2_SGI40_CAP)) ||
(!is40 && (scb->flags2 & SCB2_SGI20_CAP)))
sgi_tx = AUTO;
/* Disable SGI Tx in 20MHz on IPA chips */
if (!is40 && wlc->stf->ipaon)
sgi_tx = OFF;
}
#endif /* WL11N */
for (ac = 0; ac < WME_MAX_AC(wlc, scb); ac++) {
wlc_ratesel_init(wlc->rsi, scb, &scb->rateset, is40, sgi_tx,
#ifdef WLAFTERBURNER
wlc->afterburner,
#endif /* WLAFTERBURNER */
wlc_txc_get_cubby(wlc, scb),
active_antcfg_num, antselid_init, ac);
}
}
/* set/change bsscfg */
void
wlc_scb_set_bsscfg(struct scb *scb, wlc_bsscfg_t *cfg)
{
wlc_bsscfg_t *oldcfg = SCB_BSSCFG(scb);
wlc_info_t *wlc = cfg->wlc;
scb->bsscfg = cfg;
if (oldcfg == NULL || oldcfg != cfg) {
wlcband_t *band = wlc_scbband(scb);
wlc_rateset_t *rs;
/* flag the scb is used by IBSS */
if (cfg->BSS)
wlc_scb_clearstatebit(scb, TAKEN4IBSS);
else {
wlc_scb_resetstate(scb);
wlc_scb_setstatebit(scb, TAKEN4IBSS);
}
/* Invalidate Tx header cache */
wlc_txc_invalidate_cache(wlc_txc_get_cubby(wlc, scb));
/* use current, target, or per-band default rateset? */
if (wlc->pub->up && wlc_valid_chanspec(wlc->cmi, cfg->target_bss->chanspec))
if (cfg->associated)
rs = &cfg->current_bss->rateset;
else
rs = &cfg->target_bss->rateset;
else
rs = &band->defrateset;
/*
* Initialize the per-scb rateset:
* - if we are AP, start with only the basic subset of the
* network rates. It will be updated when receive the next
* probe request or association request.
* - if we are IBSS and gmode, special case:
* start with B-only subset of network rates and probe for ofdm rates
* - else start with the network rates.
* It will be updated on join attempts.
*/
/* initialize the scb rateset */
if (BSSCFG_AP(cfg)) {
#ifdef WLP2P
if (BSS_P2P_ENAB(wlc, cfg))
wlc_rateset_filter(rs, &scb->rateset, FALSE, WLC_RATES_OFDM,
RATE_MASK, BSS_N_ENAB(wlc, cfg));
else
#endif
wlc_rateset_filter(rs, &scb->rateset, TRUE, WLC_RATES_CCK_OFDM, RATE_MASK,
BSS_N_ENAB(wlc, cfg));
}
else if (!cfg->BSS && band->gmode) {
wlc_rateset_filter(rs, &scb->rateset, FALSE, WLC_RATES_CCK,
RATE_MASK, FALSE);
/* if resulting set is empty, then take all network rates instead */
if (scb->rateset.count == 0)
wlc_rateset_filter(rs, &scb->rateset, FALSE, WLC_RATES_CCK_OFDM,
RATE_MASK, FALSE);
}
else {
#ifdef WLP2P
if (BSS_P2P_ENAB(wlc, cfg))
wlc_rateset_filter(rs, &scb->rateset, FALSE, WLC_RATES_OFDM,
RATE_MASK, BSS_N_ENAB(wlc, cfg));
else
#endif
wlc_rateset_filter(rs, &scb->rateset, FALSE, WLC_RATES_CCK_OFDM,
RATE_MASK, FALSE);
}
if (!SCB_INTERNAL(scb))
wlc_scb_ratesel_init(wlc, scb);
}
}
void
wlc_scb_reinit(wlc_info_t *wlc)
{
uint prev_count;
const wlc_rateset_t *rs;
wlcband_t *band;
struct scb *scb;
struct scb_iter scbiter;
bool cck_only;
bool reinit_forced;
WL_INFORM(("wl%d: %s: bandunit 0x%x phy_type 0x%x gmode 0x%x\n", wlc->pub->unit,
__FUNCTION__, wlc->band->bandunit, wlc->band->phytype, wlc->band->gmode));
/* sanitize any existing scb rates against the current hardware rates */
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
prev_count = scb->rateset.count;
/* Keep only CCK if gmode == GMODE_LEGACY_B */
band = SCBINFO(scb)->band;
if (BAND_2G(band->bandtype) && (band->gmode == GMODE_LEGACY_B)) {
rs = &cck_rates;
cck_only = TRUE;
} else {
rs = &band->hw_rateset;
cck_only = FALSE;
}
if (!wlc_rate_hwrs_filter_sort_validate(&scb->rateset, rs, FALSE,
wlc->stf->txstreams)) {
/* continue with default rateset.
* since scb rateset does not carry basic rate indication,
* clear basic rate bit.
*/
WL_RATE(("wl%d: %s: invalid rateset in scb 0x%p bandunit 0x%x "
"phy_type 0x%x gmode 0x%x\n", wlc->pub->unit, __FUNCTION__,
scb, band->bandunit, band->phytype, band->gmode));
#ifdef BCMDBG
wlc_rateset_show(wlc, &scb->rateset, &scb->ea);
#endif
wlc_rateset_default(&scb->rateset, &band->hw_rateset, band->phytype,
band->bandtype, cck_only, RATE_MASK, BSS_N_ENAB(wlc, scb->bsscfg),
CHSPEC_WLC_BW(scb->bsscfg->current_bss->chanspec),
wlc->stf->txstreams);
reinit_forced = TRUE;
}
else
reinit_forced = FALSE;
/* if the count of rates is different, then the rate state
* needs to be reinitialized
*/
if (reinit_forced || (scb->rateset.count != prev_count))
wlc_scb_ratesel_init(wlc, scb);
WL_RATE(("wl%d: %s: bandunit 0x%x, phy_type 0x%x gmode 0x%x. final rateset is\n",
wlc->pub->unit, __FUNCTION__,
band->bandunit, band->phytype, band->gmode));
#ifdef BCMDBG
wlc_rateset_show(wlc, &scb->rateset, &scb->ea);
#endif
}
}
static INLINE struct scb* BCMFASTPATH
_wlc_scbfind(wlc_info_t *wlc, const struct ether_addr *ea, int bandunit)
{
int indx;
struct scb_info *scbinfo;
/* All callers of wlc_scbfind() should first be checking to see
* if the SCB they're looking for is a BC/MC address. Because we're
* using per bsscfg BCMC SCBs, we can't "find" BCMC SCBs without
* knowing which bsscfg.
*/
ASSERT(!ETHER_ISMULTI(ea));
indx = SCBHASHINDEX(wlc->scbstate->nscbhash, ea->octet);
/* search for the scb which corresponds to the remote station ea */
scbinfo = (wlc->scbstate->scbhash[bandunit][indx] ?
SCBINFO(wlc->scbstate->scbhash[bandunit][indx]) : NULL);
for (; scbinfo; scbinfo = scbinfo->hashnext) {
SCBSANITYCHECK(scbinfo->scbpub);
if (bcmp((const char*)ea, (const char*)&(scbinfo->scbpub->ea), ETHER_ADDR_LEN) == 0)
break;
}
return (scbinfo ? scbinfo->scbpub : NULL);
}
/* Find station control block corresponding to the remote id */
struct scb * BCMFASTPATH
wlc_scbfind(wlc_info_t *wlc, const struct ether_addr *ea)
{
return _wlc_scbfind(wlc, ea, wlc->band->bandunit);
}
/*
* Lookup station control block corresponding to the remote id.
* If not found, create a new entry.
*/
static INLINE struct scb *
_wlc_scblookup(wlc_info_t *wlc, const struct ether_addr *ea, int bandunit)
{
struct scb *scb;
struct wlcband *band;
#ifdef STA
wlc_bsscfg_t *bsscfg;
#endif
/* Don't allocate/find a BC/MC SCB this way. */
ASSERT(!ETHER_ISMULTI(ea));
if (ETHER_ISMULTI(ea))
return NULL;
if ((scb = _wlc_scbfind(wlc, ea, bandunit)))
return (scb);
/* no scb match, allocate one for the desired bandunit */
band = wlc->bandstate[bandunit];
scb = wlc_userscb_alloc(wlc, band);
if (!scb)
return (NULL);
scb->ea = *((const struct ether_addr*)ea);
/* install it in the cache */
wlc_scb_hash_add(wlc, scb, bandunit);
scb->bandunit = bandunit;
#ifdef STA
bsscfg = SCB_BSSCFG(scb);
ASSERT(bsscfg != NULL);
/* send ofdm rate probe */
if (BSSCFG_STA(bsscfg) && !bsscfg->BSS && band->gmode && wlc->pub->up)
wlc_rateprobe(wlc, &scb->ea, WLC_RATEPROBE_RATE);
#endif /* STA */
return (scb);
}
struct scb *
wlc_scblookup(wlc_info_t *wlc, const struct ether_addr *ea)
{
return (_wlc_scblookup(wlc, ea, wlc->band->bandunit));
}
struct scb *
wlc_scblookupband(wlc_info_t *wlc, const struct ether_addr *ea, int bandunit)
{
/* assert that the band is the current band, or we are dual band and it is the other band */
ASSERT((bandunit == (int)wlc->band->bandunit) ||
(NBANDS(wlc) > 1 && bandunit == (int)OTHERBANDUNIT(wlc)));
return (_wlc_scblookup(wlc, ea, bandunit));
}
/* Get scb from band */
struct scb * BCMFASTPATH
wlc_scbfindband(wlc_info_t *wlc, const struct ether_addr *ea, int bandunit)
{
/* assert that the band is the current band, or we are dual band and it is the other band */
ASSERT((bandunit == (int)wlc->band->bandunit) ||
(NBANDS(wlc) > 1 && bandunit == (int)OTHERBANDUNIT(wlc)));
return (_wlc_scbfind(wlc, ea, bandunit));
}
/* Determine if any SCB associated to ap cfg
* cfg specifies a specific ap cfg to compare to.
* If cfg is NULL, then compare to any ap cfg.
*/
bool
wlc_scb_associated_to_ap(wlc_info_t *wlc, wlc_bsscfg_t *cfg)
{
struct scb_iter scbiter;
struct scb *scb;
bool associated = FALSE;
ASSERT((cfg == NULL) || BSSCFG_AP(cfg));
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (SCB_ASSOCIATED(scb) && BSSCFG_AP(scb->bsscfg)) {
if ((cfg == NULL) || (cfg == scb->bsscfg)) {
associated = TRUE;
}
}
}
return (associated);
}
/* Move the scb's band info.
* Parameter description:
*
* wlc - global wlc_info structure
* bsscfg - the bsscfg that is about to move to a new chanspec
* chanspec - the new chanspec the bsscfg is moving to
*
*/
void
wlc_scb_update_band_for_cfg(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, chanspec_t chanspec)
{
struct scb_iter scbiter;
struct scb *scb, *stale_scb;
struct scb_info *scbinfo;
int bandunit;
bool reinit = FALSE;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (scb->bsscfg == bsscfg && SCB_ASSOCIATED(scb)) {
scbinfo = SCBINFO(scb);
bandunit = CHSPEC_WLCBANDUNIT(chanspec);
if (scb->bandunit != (uint)bandunit) {
/* We're about to move our scb to the new band.
* Check to make sure there isn't an scb entry for us there.
* If there is one for us, delete it first.
*/
if ((stale_scb = _wlc_scbfind(wlc, &bsscfg->BSSID, bandunit)) &&
(stale_scb->permanent == FALSE)) {
WL_ASSOC(("wl%d.%d: %s: found stale scb %p on %s band, "
"remove it\n",
wlc->pub->unit, bsscfg->_idx, __FUNCTION__,
stale_scb,
(bandunit == BAND_5G_INDEX) ? "5G" : "2G"));
/* mark the scb for removal */
stale_scb->stale_remove = TRUE;
}
/* Now perform the move of our scb to the new band */
/* first, del scb from hash table in old band */
wlc_scb_hash_del(wlc, scb, scb->bandunit);
/* next add scb to hash table in new band */
wlc_scb_hash_add(wlc, scb, bandunit);
/* update the scb's band */
scb->bandunit = bandunit;
scbinfo->band = wlc->bandstate[bandunit];
reinit = TRUE;
}
}
}
/* remove stale scb's marked for removal */
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (scb->stale_remove == TRUE) {
WL_ASSOC(("remove stale scb %p\n", scb));
scb->stale_remove = FALSE;
wlc_scbfree(wlc, scb);
}
}
if (reinit) {
wlc_scb_reinit(wlc);
}
}
/* (de)authorize/(de)authenticate single station
* 'enable' TRUE means authorize, FLASE means deauthorize/deauthenticate
* 'flag' is AUTHORIZED or AUTHENICATED for the type of operation
* 'rc' is the reason code for a deauthenticate packet
*/
void
wlc_scb_set_auth(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, struct scb *scb, bool enable, uint32 flag,
int rc)
{
#if defined(BCMDBG) || defined(WLMSG_ASSOC)
char eabuf[ETHER_ADDR_STR_LEN];
#endif /* BCMDBG || WLMSG_ASSOC */
void *pkt = NULL;
if (enable) {
if (flag == AUTHORIZED) {
wlc_scb_setstatebit(scb, AUTHORIZED);
scb->flags &= ~SCB_DEAUTH;
} else {
wlc_scb_setstatebit(scb, AUTHENTICATED);
}
} else {
if (flag == AUTHORIZED) {
wlc_scb_clearstatebit(scb, AUTHORIZED);
} else {
if (wlc->pub->up && (SCB_AUTHENTICATED(scb) || SCB_WDS(scb))) {
pkt = wlc_senddeauth(wlc, &scb->ea, &bsscfg->BSSID,
&bsscfg->cur_etheraddr,
scb, (uint16)rc);
}
if (pkt == NULL ||
wlc_pkt_callback_register(wlc, wlc_deauth_sendcomplete,
(void *)&scb->ea, pkt))
WL_ERROR(("wl%d: wlc_scb_set_auth: could not register callback\n",
wlc->pub->unit));
}
}
WL_ASSOC(("wl%d: %s: %s %s%s\n", wlc->pub->unit, __FUNCTION__,
bcm_ether_ntoa(&scb->ea, eabuf),
(enable ? "" : "de"),
((flag == AUTHORIZED) ? "authorized" : "authenticated")));
}
static void
wlc_scb_hash_add(wlc_info_t *wlc, struct scb *scb, int bandunit)
{
scb_module_t *scbstate = wlc->scbstate;
int indx = SCBHASHINDEX(scbstate->nscbhash, scb->ea.octet);
struct scb_info *scbinfo = (scbstate->scbhash[bandunit][indx] ?
SCBINFO(scbstate->scbhash[bandunit][indx]) : NULL);
SCBINFO(scb)->hashnext = scbinfo;
#ifdef MACOSX
SCBINFO(scb)->hashnext_copy = SCBINFO(scb)->hashnext;
#endif
scbstate->scbhash[bandunit][indx] = scb;
}
static void
wlc_scb_hash_del(wlc_info_t *wlc, struct scb *scbd, int bandunit)
{
scb_module_t *scbstate = wlc->scbstate;
int indx = SCBHASHINDEX(scbstate->nscbhash, scbd->ea.octet);
struct scb_info *scbinfo;
struct scb_info *remove = SCBINFO(scbd);
/* delete it from the hash */
scbinfo = (scbstate->scbhash[bandunit][indx] ?
SCBINFO(scbstate->scbhash[bandunit][indx]) : NULL);
ASSERT(scbinfo != NULL);
SCBSANITYCHECK(scbinfo->scbpub);
/* special case for the first */
if (scbinfo == remove) {
if (scbinfo->hashnext)
SCBSANITYCHECK(scbinfo->hashnext->scbpub);
scbstate->scbhash[bandunit][indx] =
(scbinfo->hashnext ? scbinfo->hashnext->scbpub : NULL);
} else {
for (; scbinfo; scbinfo = scbinfo->hashnext) {
SCBSANITYCHECK(scbinfo->hashnext->scbpub);
if (scbinfo->hashnext == remove) {
scbinfo->hashnext = remove->hashnext;
#ifdef MACOSX
scbinfo->hashnext_copy = scbinfo->hashnext;
#endif
break;
}
}
ASSERT(scbinfo != NULL);
}
}
#ifdef AP
void
wlc_scb_wds_free(struct wlc_info *wlc)
{
struct scb *scb;
struct scb_iter scbiter;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
if (scb->wds) {
scb->permanent = FALSE;
wlc_scbfree(wlc, scb);
}
}
}
#endif /* AP */
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
static int
wlc_dump_scb(wlc_info_t *wlc, struct bcmstrbuf *b)
{
uint k, i;
struct scb *scb;
struct scb_info *scbinfo;
char eabuf[ETHER_ADDR_STR_LEN];
char flagstr[64];
char flagstr2[64];
char statestr[64];
struct scb_iter scbiter;
cubby_info_t *cubby_info;
scb_module_t *scbstate = wlc->scbstate;
#ifdef AP
char ssidbuf[SSID_FMT_BUF_LEN] = "";
#endif /* AP */
wlc_bsscfg_t *cfg;
bcm_bprintf(b, "idx ether_addr\n");
k = 0;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
scbinfo = SCBINFO(scb);
cfg = SCB_BSSCFG(scb);
ASSERT(cfg != NULL);
bcm_format_flags(scb_flags, scb->flags, flagstr, 64);
bcm_format_flags(scb_flags2, scb->flags2, flagstr2, 64);
bcm_format_flags(scb_states, scb->state, statestr, 64);
bcm_bprintf(b, "%3d%s %s\n", k, (scb->permanent? "*":" "),
bcm_ether_ntoa(&scb->ea, eabuf));
bcm_bprintf(b, " State:0x%02x (%s) Used:%d(%d)\n",
scb->state, statestr, scb->used, (int)(scb->used - wlc->pub->now));
bcm_bprintf(b, " Band:%s",
((scb->bandunit == BAND_2G_INDEX) ? BAND_2G_NAME :
BAND_5G_NAME));
bcm_bprintf(b, " Flags:0x%x", scb->flags);
if (flagstr[0] != '\0')
bcm_bprintf(b, " (%s)", flagstr);
bcm_bprintf(b, " Flags2:0x%x", scb->flags2);
if (flagstr2[0] != '\0')
bcm_bprintf(b, " (%s)", flagstr2);
if (scb->key)
bcm_bprintf(b, " Key:%d", scb->key->idx);
bcm_bprintf(b, " Cfg:%d(%p)", WLC_BSSCFG_IDX(cfg), cfg);
if (scb->flags & SCB_AMSDUCAP)
bcm_bprintf(b, " AMSDU-MTU:%d", scb->amsdu_mtu_pref);
bcm_bprintf(b, "\n");
if (scb->key) {
bcm_bprintf(b, " Key ID:%d algo:%s length:%d data:",
scb->key->id,
bcm_crypto_algo_name(scb->key->algo),
scb->key->idx, scb->key->len);
if (scb->key->len)
bcm_bprintf(b, "0x");
for (i = 0; i < scb->key->len; i++)
bcm_bprintf(b, "%02X", scb->key->data[i]);
for (i = 0; i < scb->key->len; i++)
if (!bcm_isprint(scb->key->data[i]))
break;
if (i == scb->key->len)
bcm_bprintf(b, " (%.*s)", scb->key->len, scb->key->data);
bcm_bprintf(b, "\n");
}
wlc_dump_rateset(" rates", &scb->rateset, b);
bcm_bprintf(b, "\n");
if (scb->rateset.htphy_membership) {
bcm_bprintf(b, " membership %d(b)",
(scb->rateset.htphy_membership & RATE_MASK));
bcm_bprintf(b, "\n");
}
#ifdef AP
if (BSSCFG_AP(cfg)) {
bcm_bprintf(b, " AID:0x%x PS:%d Listen:%d WDS:%d(%p) RSSI:%d",
scb->aid, scb->PS, scb->listen, (scb->wds ? 1 : 0),
scb->wds, wlc_scb_rssi(scb));
wlc_format_ssid(ssidbuf, cfg->SSID, cfg->SSID_len);
bcm_bprintf(b, " BSS %d \"%s\"\n",
WLC_BSSCFG_IDX(cfg), ssidbuf);
}
#endif
if (BSSCFG_STA(cfg)) {
bcm_bprintf(b, " MAXSP:%u DEFL:0x%x TRIG:0x%x DELV:0x%x\n",
scb->apsd.maxsplen, scb->apsd.ac_defl,
scb->apsd.ac_trig, scb->apsd.ac_delv);
}
#ifdef WL11N
if (N_ENAB(wlc->pub) && SCB_HT_CAP(scb)) {
wlc_dump_mcsset(" HT mcsset :", &scb->rateset.mcs[0], b);
bcm_bprintf(b, "\n HT capabilites 0x%04x ampdu_params 0x%02x "
"mimops_enabled %d mimops_rtsmode %d",
scb->ht_capabilities, scb->ht_ampdu_params, scb->ht_mimops_enabled,
scb->ht_mimops_rtsmode);
bcm_bprintf(b, "\n wsec 0x%x", scb->wsec);
bcm_bprintf(b, "\n");
}
wlc_dump_rclist(" rclist", scb->rclist, scb->rclen, b);
#endif /* WL11N */
for (i = 0; i < scbstate->ncubby; i++) {
cubby_info = &scbstate->cubby_info[i];
if (cubby_info->fn_dump)
cubby_info->fn_dump(cubby_info->context, scb, b);
}
wlc_scb_txpath_dump(wlc, scb, b);
k++;
}
return 0;
}
#endif /* BCMDBG || BCMDBG_DUMP */
void
wlc_scb_sortrates(wlc_info_t *wlc, struct scb *scb)
{
struct scb_info *scbinfo = SCBINFO(scb);
wlc_rate_hwrs_filter_sort_validate(&scb->rateset, &scbinfo->band->hw_rateset, FALSE,
wlc->stf->txstreams);
}
void
BCMINITFN(wlc_scblist_validaterates)(wlc_info_t *wlc)
{
struct scb *scb;
struct scb_iter scbiter;
FOREACHSCB(wlc->scbstate, &scbiter, scb) {
wlc_scb_sortrates(wlc, scb);
if (scb->rateset.count == 0) {
wlc_scbfree(wlc, scb);
}
}
}
#if defined(AP)
int
wlc_scb_rssi(struct scb *scb)
{
int rssi = 0;
int i;
for (i = 0; i < MA_WINDOW_SZ; i++)
rssi += scb->rssi_window[i];
rssi /= MA_WINDOW_SZ;
return (rssi);
}
void
wlc_scb_rssi_init(struct scb *scb, int rssi)
{
int i;
for (i = 0; i < MA_WINDOW_SZ; i++)
scb->rssi_window[i] = rssi;
}
#endif
/* Give then tx_fn, return the feature id from txmod_fns array.
* If tx_fn is NULL, 0 will be returned
* If entry is not found, it's an ERROR!
*/
static INLINE scb_txmod_t
wlc_scb_txmod_fid(wlc_info_t *wlc, txmod_tx_fn_t tx_fn)
{
scb_txmod_t txmod;
for (txmod = TXMOD_START; txmod < TXMOD_LAST; txmod++)
if (tx_fn == wlc->txmod_fns[txmod].tx_fn)
return txmod;
/* Should not reach here */
ASSERT(txmod < TXMOD_LAST);
return txmod;
}
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
static int
wlc_scb_txpath_dump(wlc_info_t *wlc, struct scb *scb, struct bcmstrbuf *b)
{
const uchar txmod_names[][20] = {
"Start", "DPT", "CRAM", "APPS", "A-MSDU", "Block Ack", "A-MPDU", "Transmit"
};
scb_txmod_t fid;
bcm_bprintf(b, " Tx Path:");
fid = TXMOD_START;
do {
bcm_bprintf(b, " -> %s",
txmod_names[wlc_scb_txmod_fid(wlc, scb->tx_path[fid].next_tx_fn)]);
fid = wlc_scb_txmod_fid(wlc, scb->tx_path[fid].next_tx_fn);
} while (fid != TXMOD_TRANSMIT && fid != 0);
bcm_bprintf(b, "\n");
return 0;
}
#endif /* BCMDBG || BCMDBG_DUMP */
/* Add a feature to the path. It should not be already on the path and should be configured
* Does not take care of evicting anybody
*/
void
wlc_scb_txmod_activate(wlc_info_t *wlc, struct scb *scb, scb_txmod_t fid)
{
/* Numeric value designating this feature's position in tx_path */
static const uint8 txmod_position[TXMOD_LAST] = {
0, /* TXMOD_START */
1, /* TXMOD_DPT */
2, /* TXMOD_CRAM */
4, /* TXMOD_APPS */
2, /* TXMOD_AMSDU */
3, /* TXMOD_BA */
3, /* TXMOD_AMPDU */
5, /* TXMOD_TRANSMIT */
};
uint curr_mod_position;
scb_txmod_t prev, next;
txmod_info_t curr_mod_info = wlc->txmod_fns[fid];
ASSERT(SCB_TXMOD_CONFIGURED(scb, fid) &&
!SCB_TXMOD_ACTIVE(scb, fid));
curr_mod_position = txmod_position[fid];
prev = TXMOD_START;
while ((next = wlc_scb_txmod_fid(wlc, scb->tx_path[prev].next_tx_fn)) != 0 &&
txmod_position[next] < curr_mod_position)
prev = next;
/* next == 0 indicate this is the first addition to the path
* it HAS to be TXMOD_TRANSMIT as it's the one that puts the packet in
* txq. If this changes, then assert will need to be removed.
*/
ASSERT(next != 0 || fid == TXMOD_TRANSMIT);
ASSERT(txmod_position[next] != curr_mod_position);
SCB_TXMOD_SET(scb, prev, fid);
SCB_TXMOD_SET(scb, fid, next);
/* invoke any activate notify functions now that it's in the path */
if (curr_mod_info.activate_notify_fn)
curr_mod_info.activate_notify_fn(curr_mod_info.ctx, scb);
}
/* Remove a fid from the path. It should be already on the path
* Does not take care of replacing it with any other feature.
*/
void
wlc_scb_txmod_deactivate(wlc_info_t *wlc, struct scb *scb, scb_txmod_t fid)
{
scb_txmod_t prev, next;
txmod_info_t curr_mod_info = wlc->txmod_fns[fid];
/* If not active, do nothing */
if (!SCB_TXMOD_ACTIVE(scb, fid))
return;
/* if deactivate notify function is present, call it */
if (curr_mod_info.deactivate_notify_fn)
curr_mod_info.deactivate_notify_fn(curr_mod_info.ctx, scb);
prev = TXMOD_START;
while ((next = wlc_scb_txmod_fid(wlc, scb->tx_path[prev].next_tx_fn))
!= fid)
prev = next;
SCB_TXMOD_SET(scb, prev, wlc_scb_txmod_fid(wlc, scb->tx_path[fid].next_tx_fn));
scb->tx_path[fid].next_tx_fn = NULL;
}
#ifdef WDS
int
wlc_wds_create(wlc_info_t *wlc, struct scb *scb, uint flags)
{
ASSERT(scb != NULL);
/* honor the existing WDS link */
if (scb->wds != NULL) {
scb->permanent = TRUE;
return BCME_OK;
}
if (!(flags & WDS_INFRA_BSS) && SCB_ISMYAP(scb)) {
#ifdef BCMDBG_ERR
char eabuf[ETHER_ADDR_STR_LEN];
WL_ERROR(("wl%d: rejecting WDS %s, associated to it as our AP\n",
wlc->pub->unit, bcm_ether_ntoa(&scb->ea, eabuf)));
#endif /* BCMDBG_ERR */
return BCME_ERROR;
}
/* allocate a wlc_if_t for the wds interface and fill it out */
scb->wds = wlc_wlcif_alloc(wlc, wlc->osh, WLC_IFTYPE_WDS, wlc->active_queue);
if (scb->wds == NULL) {
WL_ERROR(("wl%d: wlc_wds_create: failed to alloc wlcif\n",
wlc->pub->unit));
return BCME_NOMEM;
}
scb->wds->u.scb = scb;
#ifdef AP
/* create an upper-edge interface */
if (!(flags & WDS_INFRA_BSS)) {
/* a WDS scb has an AID for a unique WDS interface unit number */
if (scb->aid == 0)
scb->aid = wlc_bsscfg_newaid(scb->bsscfg);
scb->wds->wlif = wl_add_if(wlc->wl, scb->wds, AID2PVBMAP(scb->aid), &scb->ea);
if (scb->wds->wlif == NULL) {
MFREE(wlc->osh, scb->wds, sizeof(wlc_if_t));
scb->wds = NULL;
return BCME_NOMEM;
}
scb->bsscfg->wlcif->flags |= WLC_IF_LINKED;
wlc_if_event(wlc, WLC_E_IF_ADD, scb->wds);
}
wlc_wds_wpa_role_set(wlc->ap, scb, WL_WDS_WPA_ROLE_AUTO);
#endif /* AP */
/* override WDS nodes rates to the full hw rate set */
wlc_rateset_filter(&wlc->band->hw_rateset, &scb->rateset, FALSE,
WLC_RATES_CCK_OFDM, RATE_MASK, BSS_N_ENAB(wlc, scb->bsscfg));
wlc_scb_ratesel_init(wlc, scb);
scb->permanent = TRUE;
scb->flags &= ~SCB_MYAP;
return BCME_OK;
}
#endif /* WDS */
#ifdef MFP
void *
wlc_scb_send_action_sa_query(wlc_info_t *wlc, struct scb *scb, uint8 action, uint16 id)
{
void *p;
uint8* pbody;
uint body_len;
struct dot11_action_sa_query *af;
body_len = sizeof(struct dot11_action_sa_query);
if ((p = wlc_frame_get_action(wlc, FC_ACTION, &scb->ea, &scb->bsscfg->cur_etheraddr,
&scb->bsscfg->BSSID, body_len, &pbody, DOT11_ACTION_CAT_SA_QUERY)) == NULL) {
return NULL;
}
af = (struct dot11_action_sa_query *)pbody;
af->category = DOT11_ACTION_CAT_SA_QUERY;
af->action = action;
af->id = id;
wlc_sendmgmt(wlc, p, scb->bsscfg->wlcif->qi, scb);
return p;
}
void
wlc_scb_start_sa_query(wlc_info_t *wlc, wlc_bsscfg_t *bsscfg, struct scb *scb)
{
if ((scb == NULL) || !SCB_ASSOCIATED(scb))
return;
if (scb->sa_query_started)
return;
scb->sa_query_started = TRUE;
scb->sa_query_count = 0;
/* Token needs to be non-zero, so burn the high bit */
scb->sa_query_id = (uint16)(wlc->counter | 0x8000);
/* start periodic timer */
wl_add_timer(wlc->wl, scb->sa_query_timer, 200, TRUE);
wlc_scb_send_action_sa_query(wlc, scb, SA_QUERY_REQUEST, scb->sa_query_id);
}
static void
wlc_scb_recv_sa_resp(wlc_info_t *wlc, struct scb *scb, struct dot11_action_sa_query *af)
{
if (scb->sa_query_started == FALSE)
return;
if (af->id == scb->sa_query_id) {
wl_del_timer(wlc->wl, scb->sa_query_timer);
scb->sa_query_started = FALSE;
scb->sa_query_count = 0;
return;
}
/* id mismatch, continue query */
scb->sa_query_id = (uint16)(wlc->counter | 0x8000);
wlc_scb_send_action_sa_query(wlc, scb, SA_QUERY_REQUEST, scb->sa_query_id);
}
static void
scb_sa_query_timeout(void *arg)
{
struct scb *scb = (struct scb *)arg;
wlc_bsscfg_t *cfg = scb->bsscfg;
wlc_info_t *wlc = cfg->wlc;
scb->sa_query_count++;
/* total time out = 25*200ms = 5 seconds */
if (scb->sa_query_count > 25) {
wl_del_timer(wlc->wl, scb->sa_query_timer);
scb->sa_query_count = 0;
scb->sa_query_started = FALSE;
/* disassoc scb */
wlc_senddisassoc(wlc, &scb->ea, &cfg->BSSID,
&cfg->cur_etheraddr,
scb, DOT11_RC_NOT_AUTH);
wlc_scb_clearstatebit(scb, ASSOCIATED | AUTHORIZED);
wlc_scb_disassoc_cleanup(wlc, scb);
wlc_disassoc_complete(cfg, WLC_E_STATUS_SUCCESS, &cfg->BSSID,
DOT11_RC_DISASSOC_LEAVING, DOT11_BSSTYPE_INFRASTRUCTURE);
} else {
scb->sa_query_id++;
scb->sa_query_id |= 0x8000;
wlc_scb_send_action_sa_query(wlc, scb, SA_QUERY_REQUEST, scb->sa_query_id);
}
}
void
wlc_scb_sa_query(wlc_info_t *wlc, uint action_id, struct scb *scb,
struct dot11_management_header *hdr, uint8 *body, int body_len)
{
struct dot11_action_sa_query *af;
if (scb == NULL)
return;
af = (struct dot11_action_sa_query *)body;
WL_WSEC(("wl%d: Rcvd SA Query action frame with id %d\n", wlc->pub->unit, action_id));
switch (action_id) {
case SA_QUERY_REQUEST:
if (SCB_ASSOCIATED(scb)) {
wlc_scb_send_action_sa_query(wlc, scb, SA_QUERY_RESPONSE, af->id);
}
break;
case SA_QUERY_RESPONSE:
wlc_scb_recv_sa_resp(wlc, scb, af);
break;
default:
WL_ERROR(("wl %d: unrecognised SA Query action frame\n", wlc->pub->unit));
}
}
#endif /* MFP */
| [
"yangshaokun@joyotime.com"
] | yangshaokun@joyotime.com |
de44696a1c697965265a1c80b9c082bd8a75034a | de8c0ea84980b6d9bb6e3e23b87e6066a65f4995 | /3pp/linux/drivers/media/dvb-frontends/stb0899_algo.c | df89c33dac23c58301a60569a29fd322e564aef5 | [
"Linux-syscall-note",
"GPL-2.0-only",
"MIT"
] | permissive | eerimoq/monolinux-example-project | 7cc19c6fc179a6d1fd3ec60f383f906b727e6715 | 57c4c2928b11cc04db59fb5ced962762099a9895 | refs/heads/master | 2021-02-08T10:57:58.215466 | 2020-07-02T08:04:25 | 2020-07-02T08:04:25 | 244,144,570 | 6 | 0 | MIT | 2020-07-02T08:15:50 | 2020-03-01T12:24:47 | C | UTF-8 | C | false | false | 50,002 | c | // SPDX-License-Identifier: GPL-2.0-or-later
/*
STB0899 Multistandard Frontend driver
Copyright (C) Manu Abraham (abraham.manu@gmail.com)
Copyright (C) ST Microelectronics
*/
#include <linux/bitops.h>
#include "stb0899_drv.h"
#include "stb0899_priv.h"
#include "stb0899_reg.h"
static inline u32 stb0899_do_div(u64 n, u32 d)
{
/* wrap do_div() for ease of use */
do_div(n, d);
return n;
}
#if 0
/* These functions are currently unused */
/*
* stb0899_calc_srate
* Compute symbol rate
*/
static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
{
u64 tmp;
/* srate = (SFR * master_clk) >> 20 */
/* sfr is of size 20 bit, stored with an offset of 4 bit */
tmp = (((u32)sfr[0]) << 16) | (((u32)sfr[1]) << 8) | sfr[2];
tmp &= ~0xf;
tmp *= master_clk;
tmp >>= 24;
return tmp;
}
/*
* stb0899_get_srate
* Get the current symbol rate
*/
static u32 stb0899_get_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u8 sfr[3];
stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
return stb0899_calc_srate(internal->master_clk, sfr);
}
#endif
/*
* stb0899_set_srate
* Set symbol frequency
* MasterClock: master clock frequency (hz)
* SymbolRate: symbol rate (bauds)
* return symbol frequency
*/
static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
{
u32 tmp;
u8 sfr[3];
dprintk(state->verbose, FE_DEBUG, 1, "-->");
/*
* in order to have the maximum precision, the symbol rate entered into
* the chip is computed as the closest value of the "true value".
* In this purpose, the symbol rate value is rounded (1 is added on the bit
* below the LSB )
*
* srate = (SFR * master_clk) >> 20
* <=>
* SFR = srate << 20 / master_clk
*
* rounded:
* SFR = (srate << 21 + master_clk) / (2 * master_clk)
*
* stored as 20 bit number with an offset of 4 bit:
* sfr = SFR << 4;
*/
tmp = stb0899_do_div((((u64)srate) << 21) + master_clk, 2 * master_clk);
tmp <<= 4;
sfr[0] = tmp >> 16;
sfr[1] = tmp >> 8;
sfr[2] = tmp;
stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
return srate;
}
/*
* stb0899_calc_derot_time
* Compute the amount of time needed by the derotator to lock
* SymbolRate: Symbol rate
* return: derotator time constant (ms)
*/
static long stb0899_calc_derot_time(long srate)
{
if (srate > 0)
return (100000 / (srate / 1000));
else
return 0;
}
/*
* stb0899_carr_width
* Compute the width of the carrier
* return: width of carrier (kHz or Mhz)
*/
long stb0899_carr_width(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
return (internal->srate + (internal->srate * internal->rolloff) / 100);
}
/*
* stb0899_first_subrange
* Compute the first subrange of the search
*/
static void stb0899_first_subrange(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
struct stb0899_config *config = state->config;
int range = 0;
u32 bandwidth = 0;
if (config->tuner_get_bandwidth) {
stb0899_i2c_gate_ctrl(&state->frontend, 1);
config->tuner_get_bandwidth(&state->frontend, &bandwidth);
stb0899_i2c_gate_ctrl(&state->frontend, 0);
range = bandwidth - stb0899_carr_width(state) / 2;
}
if (range > 0)
internal->sub_range = min(internal->srch_range, range);
else
internal->sub_range = 0;
internal->freq = params->freq;
internal->tuner_offst = 0L;
internal->sub_dir = 1;
}
/*
* stb0899_check_tmg
* check for timing lock
* internal.Ttiming: time to wait for loop lock
*/
static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
int lock;
u8 reg;
s8 timing;
msleep(internal->t_derot);
stb0899_write_reg(state, STB0899_RTF, 0xf2);
reg = stb0899_read_reg(state, STB0899_TLIR);
lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
timing = stb0899_read_reg(state, STB0899_RTF);
if (lock >= 42) {
if ((lock > 48) && (abs(timing) >= 110)) {
internal->status = ANALOGCARRIER;
dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
} else {
internal->status = TIMINGOK;
dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
}
} else {
internal->status = NOTIMING;
dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
}
return internal->status;
}
/*
* stb0899_search_tmg
* perform a fs/2 zig-zag to find timing
*/
static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
int index = 0;
u8 cfr[2];
internal->status = NOTIMING;
/* timing loop computation & symbol rate optimisation */
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_step = (params->srate / 2L) / internal->mclk;
while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
index++;
derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
}
internal->direction = -internal->direction; /* Change zigzag direction */
}
if (internal->status == TIMINGOK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
}
return internal->status;
}
/*
* stb0899_check_carrier
* Check for carrier found
*/
static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u8 reg;
msleep(internal->t_derot); /* wait for derotator ok */
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
reg = stb0899_read_reg(state, STB0899_DSTATUS);
dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
internal->status = CARRIEROK;
dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
} else {
internal->status = NOCARRIER;
dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
}
return internal->status;
}
/*
* stb0899_search_carrier
* Search for a QPSK carrier with the derotator
*/
static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
int index = 0;
u8 cfr[2];
u8 reg;
internal->status = NOCARRIER;
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_freq = internal->derot_freq;
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
do {
dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
if (stb0899_check_carrier(state) == NOCARRIER) {
index++;
last_derot_freq = derot_freq;
derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
if(abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
}
}
internal->direction = -internal->direction; /* Change zigzag direction */
} while ((internal->status != CARRIEROK) && next_loop);
if (internal->status == CARRIEROK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
} else {
internal->derot_freq = last_derot_freq;
}
return internal->status;
}
/*
* stb0899_check_data
* Check for data found
*/
static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
int lock = 0, index = 0, dataTime = 500, loop;
u8 reg;
internal->status = NODATA;
/* RESET FEC */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESACS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
msleep(1);
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESACS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
if (params->srate <= 2000000)
dataTime = 2000;
else if (params->srate <= 5000000)
dataTime = 1500;
else if (params->srate <= 15000000)
dataTime = 1000;
else
dataTime = 500;
/* clear previous failed END_LOOPVIT */
stb0899_read_reg(state, STB0899_VSTATUS);
stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
while (1) {
/* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
reg = stb0899_read_reg(state, STB0899_VSTATUS);
lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
if (lock || loop || (index > dataTime))
break;
index++;
}
if (lock) { /* DATA LOCK indicator */
internal->status = DATAOK;
dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
}
return internal->status;
}
/*
* stb0899_search_data
* Search for a QPSK carrier with the derotator
*/
static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
{
short int derot_freq, derot_step, derot_limit, next_loop = 3;
u8 cfr[2];
u8 reg;
int index = 1;
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
derot_step = (params->srate / 4L) / internal->mclk;
derot_limit = (internal->sub_range / 2L) / internal->mclk;
derot_freq = internal->derot_freq;
do {
if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
if (abs(derot_freq) > derot_limit)
next_loop--;
if (next_loop) {
dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(internal->inversion * derot_freq));
STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(internal->inversion * derot_freq));
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
stb0899_check_carrier(state);
index++;
}
}
internal->direction = -internal->direction; /* change zig zag direction */
} while ((internal->status != DATAOK) && next_loop);
if (internal->status == DATAOK) {
stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
/* store autodetected IQ swapping as default for DVB-S2 tuning */
reg = stb0899_read_reg(state, STB0899_IQSWAP);
if (STB0899_GETFIELD(SYM, reg))
internal->inversion = IQ_SWAP_ON;
else
internal->inversion = IQ_SWAP_OFF;
internal->derot_freq = internal->inversion * MAKEWORD16(cfr[0], cfr[1]);
dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
}
return internal->status;
}
/*
* stb0899_check_range
* check if the found frequency is in the correct range
*/
static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
int range_offst, tp_freq;
range_offst = internal->srch_range / 2000;
tp_freq = internal->freq - (internal->derot_freq * internal->mclk) / 1000;
if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
internal->status = RANGEOK;
dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
} else {
internal->status = OUTOFRANGE;
dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
}
return internal->status;
}
/*
* NextSubRange
* Compute the next subrange of the search
*/
static void next_sub_range(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_params *params = &state->params;
long old_sub_range;
if (internal->sub_dir > 0) {
old_sub_range = internal->sub_range;
internal->sub_range = min((internal->srch_range / 2) -
(internal->tuner_offst + internal->sub_range / 2),
internal->sub_range);
if (internal->sub_range < 0)
internal->sub_range = 0;
internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
}
internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
internal->sub_dir = -internal->sub_dir;
}
/*
* stb0899_dvbs_algo
* Search for a signal, timing, carrier and data for a
* given frequency in a given range
*/
enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
{
struct stb0899_params *params = &state->params;
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u8 bclc, reg;
u8 cfr[2];
u8 eq_const[10];
s32 clnI = 3;
u32 bandwidth = 0;
/* BETA values rated @ 99MHz */
s32 betaTab[5][4] = {
/* 5 10 20 30MBps */
{ 37, 34, 32, 31 }, /* QPSK 1/2 */
{ 37, 35, 33, 31 }, /* QPSK 2/3 */
{ 37, 35, 33, 31 }, /* QPSK 3/4 */
{ 37, 36, 33, 32 }, /* QPSK 5/6 */
{ 37, 36, 33, 32 } /* QPSK 7/8 */
};
internal->direction = 1;
stb0899_set_srate(state, internal->master_clk, params->srate);
/* Carrier loop optimization versus symbol rate for acquisition*/
if (params->srate <= 5000000) {
stb0899_write_reg(state, STB0899_ACLC, 0x89);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 0;
} else if (params->srate <= 15000000) {
stb0899_write_reg(state, STB0899_ACLC, 0xc9);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 1;
} else if(params->srate <= 25000000) {
stb0899_write_reg(state, STB0899_ACLC, 0x89);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 2;
} else {
stb0899_write_reg(state, STB0899_ACLC, 0xc8);
bclc = stb0899_read_reg(state, STB0899_BCLC);
STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
stb0899_write_reg(state, STB0899_BCLC, bclc);
clnI = 3;
}
dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
/* Set the timing loop to acquisition */
stb0899_write_reg(state, STB0899_RTC, 0x46);
stb0899_write_reg(state, STB0899_CFD, 0xee);
/* !! WARNING !!
* Do not read any status variables while acquisition,
* If any needed, read before the acquisition starts
* querying status while acquiring causes the
* acquisition to go bad and hence no locks.
*/
dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
internal->derot_percent, params->srate, internal->mclk);
/* Initial calculations */
internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
internal->t_derot = stb0899_calc_derot_time(params->srate);
internal->t_data = 500;
dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
/* RESET Stream merger */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/*
* Set KDIVIDER to an intermediate value between
* 1/2 and 7/8 for acquisition
*/
reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
stb0899_first_subrange(state);
do {
/* Initialisations */
cfr[0] = cfr[1] = 0;
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
stb0899_write_reg(state, STB0899_RTF, 0);
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
stb0899_write_reg(state, STB0899_CFD, reg);
internal->derot_freq = 0;
internal->status = NOAGC1;
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
/* Move tuner to frequency */
dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
if (state->config->tuner_set_frequency)
state->config->tuner_set_frequency(&state->frontend, internal->freq);
if (state->config->tuner_get_frequency)
state->config->tuner_get_frequency(&state->frontend, &internal->freq);
msleep(internal->t_agc1 + internal->t_agc2 + internal->t_derot); /* AGC1, AGC2 and timing loop */
dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
internal->status = AGC1OK;
/* There is signal in the band */
if (config->tuner_get_bandwidth)
config->tuner_get_bandwidth(&state->frontend, &bandwidth);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
if (params->srate <= bandwidth / 2)
stb0899_search_tmg(state); /* For low rates (SCPC) */
else
stb0899_check_tmg(state); /* For high rates (MCPC) */
if (internal->status == TIMINGOK) {
dprintk(state->verbose, FE_DEBUG, 1,
"TIMING OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
dprintk(state->verbose, FE_DEBUG, 1,
"CARRIER OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_search_data(state) == DATAOK) { /* Check for data */
dprintk(state->verbose, FE_DEBUG, 1,
"DATA OK ! Derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
if (stb0899_check_range(state) == RANGEOK) {
dprintk(state->verbose, FE_DEBUG, 1,
"RANGE OK ! derot freq=%d, mclk=%d",
internal->derot_freq, internal->mclk);
internal->freq = params->freq - ((internal->derot_freq * internal->mclk) / 1000);
reg = stb0899_read_reg(state, STB0899_PLPARM);
internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
dprintk(state->verbose, FE_DEBUG, 1,
"freq=%d, internal resultant freq=%d",
params->freq, internal->freq);
dprintk(state->verbose, FE_DEBUG, 1,
"internal puncture rate=%d",
internal->fecrate);
}
}
}
}
if (internal->status != RANGEOK)
next_sub_range(state);
} while (internal->sub_range && internal->status != RANGEOK);
/* Set the timing loop to tracking */
stb0899_write_reg(state, STB0899_RTC, 0x33);
stb0899_write_reg(state, STB0899_CFD, 0xf7);
/* if locked and range ok, set Kdiv */
if (internal->status == RANGEOK) {
dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
/*
* Carrier loop optimization versus
* symbol Rate/Puncture Rate for Tracking
*/
reg = stb0899_read_reg(state, STB0899_BCLC);
switch (internal->fecrate) {
case STB0899_FEC_1_2: /* 13 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_2_3: /* 18 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_3_4: /* 21 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_5_6: /* 24 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
case STB0899_FEC_6_7: /* 25 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
stb0899_write_reg(state, STB0899_ACLC, 0x88);
stb0899_write_reg(state, STB0899_BCLC, 0x9a);
break;
case STB0899_FEC_7_8: /* 26 */
stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
stb0899_write_reg(state, STB0899_BCLC, reg);
break;
default:
dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
break;
}
/* release stream merger RESET */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/* disable carrier detector */
reg = stb0899_read_reg(state, STB0899_CFD);
STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
stb0899_write_reg(state, STB0899_CFD, reg);
stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
}
return internal->status;
}
/*
* stb0899_dvbs2_config_uwp
* Configure UWP state machine
*/
static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 uwp1, uwp2, uwp3, reg;
uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
}
/*
* stb0899_dvbs2_config_csm_auto
* Set CSM to AUTO mode
*/
static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
{
u32 reg;
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
}
static long Log2Int(int number)
{
int i;
i = 0;
while ((1 << i) <= abs(number))
i++;
if (number == 0)
i = 1;
return i - 1;
}
/*
* stb0899_dvbs2_calc_srate
* compute BTR_NOM_FREQ for the symbol rate
*/
static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
u32 master_clk, srate;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
decim = 1 << dec_rate;
master_clk = internal->master_clk / 1000;
srate = internal->srate / 1000;
if (decim <= 4) {
intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
} else {
intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
}
btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
return btr_nom_freq;
}
/*
* stb0899_dvbs2_calc_dev
* compute the correction to be applied to symbol rate
*/
static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u32 dec_ratio, correction, master_clk, srate;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
master_clk = internal->master_clk / 1000; /* for integer Calculation*/
srate = internal->srate / 1000; /* for integer Calculation*/
correction = (512 * master_clk) / (2 * dec_ratio * srate);
return correction;
}
/*
* stb0899_dvbs2_set_srate
* Set DVBS2 symbol rate
*/
static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
u32 correction, freq_adj, band_lim, decim_cntrl, reg;
u8 anti_alias;
/*set decimation to 1*/
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
win_sel = 0;
if (dec_rate >= 5)
win_sel = dec_rate - 4;
decim = (1 << dec_rate);
/* (FSamp/Fsymbol *100) for integer Calculation */
f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
if (f_sym <= 2250) /* don't band limit signal going into btr block*/
band_lim = 1;
else
band_lim = 0; /* band limit signal going into btr block*/
decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
if (f_sym <= 3450)
anti_alias = 0;
else if (f_sym <= 4250)
anti_alias = 1;
else
anti_alias = 2;
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
btr_nom_freq = stb0899_dvbs2_calc_srate(state);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
correction = stb0899_dvbs2_calc_dev(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
/* scale UWP+CSM frequency to sample rate*/
freq_adj = internal->srate / (internal->master_clk / 4096);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
}
/*
* stb0899_dvbs2_set_btr_loopbw
* set bit timing loop bandwidth as a percentage of the symbol rate
*/
static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
u32 decim, K, wn, k_direct, k_indirect;
u32 reg;
dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
dec_rate = Log2Int(dec_ratio);
decim = (1 << dec_rate);
sym_peak *= 576000;
K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
if (K != 0) {
K = sym_peak / K;
wn = (4 * zeta * zeta) + 1000000;
wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
k_indirect = (wn * wn) / K; /*kindirect = kindirect 10^-6*/
k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
k_direct *= 100;
k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
k_btr1 = k_direct / (1 << k_direct_shift);
k_btr1 /= 10000;
k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
k_btr0 = k_indirect * (1 << (-k_indirect_shift));
k_btr0 /= 1000000;
k_btr2_rshft = 0;
if (k_btr0_rshft > 15) {
k_btr2_rshft = k_btr0_rshft - 15;
k_btr0_rshft = 15;
}
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
} else
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
}
/*
* stb0899_dvbs2_set_carr_freq
* set nominal frequency for carrier search
*/
static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
{
struct stb0899_config *config = state->config;
s32 crl_nom_freq;
u32 reg;
crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
crl_nom_freq *= carr_freq;
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
}
/*
* stb0899_dvbs2_init_calc
* Initialize DVBS2 UWP, CSM, carrier and timing loops
*/
static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
s32 steps, step_size;
u32 range, reg;
/* config uwp and csm */
stb0899_dvbs2_config_uwp(state);
stb0899_dvbs2_config_csm_auto(state);
/* initialize BTR */
stb0899_dvbs2_set_srate(state);
stb0899_dvbs2_set_btr_loopbw(state);
if (internal->srate / 1000000 >= 15)
step_size = (1 << 17) / 5;
else if (internal->srate / 1000000 >= 10)
step_size = (1 << 17) / 7;
else if (internal->srate / 1000000 >= 5)
step_size = (1 << 17) / 10;
else
step_size = (1 << 17) / 4;
range = internal->srch_range / 1000000;
steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
steps = (steps + 6) / 10;
steps = (steps == 0) ? 1 : steps;
if (steps % 2 == 0)
stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
(internal->step_size * (internal->srate / 20000000)),
(internal->master_clk) / 1000000);
else
stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
/*Set Carrier Search params (zigzag, num steps and freq step size*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
}
/*
* stb0899_dvbs2_btr_init
* initialize the timing loop
*/
static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
{
u32 reg;
/* set enable BTR loopback */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
/* fix btr freq accum at 0 */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
/* fix btr freq accum at 0 */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
}
/*
* stb0899_dvbs2_reacquire
* trigger a DVB-S2 acquisition
*/
static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
{
u32 reg = 0;
/* demod soft reset */
STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
/*Reset Timing Loop */
stb0899_dvbs2_btr_init(state);
/* reset Carrier loop */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
/*release demod soft reset */
reg = 0;
STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
/* start acquisition process */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
/* equalizer Init */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
/*Start equilizer */
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
/* RESET Packet delineator */
stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
}
/*
* stb0899_dvbs2_get_dmd_status
* get DVB-S2 Demod LOCK status
*/
static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
{
int time = -10, lock = 0, uwp, csm;
u32 reg;
do {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
uwp = STB0899_GETFIELD(UWP_LOCK, reg);
csm = STB0899_GETFIELD(CSM_LOCK, reg);
if (uwp && csm)
lock = 1;
time += 10;
msleep(10);
} while ((!lock) && (time <= timeout));
if (lock) {
dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
return DVBS2_DEMOD_LOCK;
} else {
return DVBS2_DEMOD_NOLOCK;
}
}
/*
* stb0899_dvbs2_get_data_lock
* get FEC status
*/
static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
{
int time = 0, lock = 0;
u8 reg;
while ((!lock) && (time < timeout)) {
reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
time++;
}
return lock;
}
/*
* stb0899_dvbs2_get_fec_status
* get DVB-S2 FEC LOCK status
*/
static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
{
int time = 0, Locked;
do {
Locked = stb0899_dvbs2_get_data_lock(state, 1);
time++;
msleep(1);
} while ((!Locked) && (time < timeout));
if (Locked) {
dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
return DVBS2_FEC_LOCK;
} else {
return DVBS2_FEC_NOLOCK;
}
}
/*
* stb0899_dvbs2_init_csm
* set parameters for manual mode
*/
static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
{
struct stb0899_internal *internal = &state->internal;
s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
u32 csm1, csm2, csm3, csm4;
if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
switch (modcod) {
case STB0899_QPSK_12:
gamma_acq = 25;
gamma_rho_acq = 2700;
gamma_trk = 12;
gamma_rho_trk = 180;
lock_count_thr = 8;
break;
case STB0899_QPSK_35:
gamma_acq = 38;
gamma_rho_acq = 7182;
gamma_trk = 14;
gamma_rho_trk = 308;
lock_count_thr = 8;
break;
case STB0899_QPSK_23:
gamma_acq = 42;
gamma_rho_acq = 9408;
gamma_trk = 17;
gamma_rho_trk = 476;
lock_count_thr = 8;
break;
case STB0899_QPSK_34:
gamma_acq = 53;
gamma_rho_acq = 16642;
gamma_trk = 19;
gamma_rho_trk = 646;
lock_count_thr = 8;
break;
case STB0899_QPSK_45:
gamma_acq = 53;
gamma_rho_acq = 17119;
gamma_trk = 22;
gamma_rho_trk = 880;
lock_count_thr = 8;
break;
case STB0899_QPSK_56:
gamma_acq = 55;
gamma_rho_acq = 19250;
gamma_trk = 23;
gamma_rho_trk = 989;
lock_count_thr = 8;
break;
case STB0899_QPSK_89:
gamma_acq = 60;
gamma_rho_acq = 24240;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
case STB0899_QPSK_910:
gamma_acq = 66;
gamma_rho_acq = 29634;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
default:
gamma_acq = 66;
gamma_rho_acq = 29634;
gamma_trk = 24;
gamma_rho_trk = 1176;
lock_count_thr = 8;
break;
}
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
}
}
/*
* stb0899_dvbs2_get_srate
* get DVB-S2 Symbol Rate
*/
static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
struct stb0899_config *config = state->config;
u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
int div1, div2, rem1, rem2;
div1 = config->btr_nco_bits / 2;
div2 = config->btr_nco_bits - div1 - 1;
bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
decimRate = (1 << decimRate);
intval1 = internal->master_clk / (1 << div1);
intval2 = bTrNomFreq / (1 << div2);
rem1 = internal->master_clk % (1 << div1);
rem2 = bTrNomFreq % (1 << div2);
/* only for integer calculation */
srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
return srate;
}
/*
* stb0899_dvbs2_algo
* Search for signal, timing, carrier and data for a given
* frequency in a given range
*/
enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
{
struct stb0899_internal *internal = &state->internal;
enum stb0899_modcod modcod;
s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
int i = 0;
u32 reg, csm1;
if (internal->srate <= 2000000) {
searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
} else if (internal->srate <= 5000000) {
searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
} else if (internal->srate <= 10000000) {
searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
} else if (internal->srate <= 15000000) {
searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
} else if (internal->srate <= 20000000) {
searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
} else if (internal->srate <= 25000000) {
searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
} else {
searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
}
/* Maintain Stream Merger in reset during acquisition */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 1);
stb0899_write_reg(state, STB0899_TSTRES, reg);
/* enable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 1);
/* Move tuner to frequency */
if (state->config->tuner_set_frequency)
state->config->tuner_set_frequency(&state->frontend, internal->freq);
if (state->config->tuner_get_frequency)
state->config->tuner_get_frequency(&state->frontend, &internal->freq);
/* disable tuner I/O */
stb0899_i2c_gate_ctrl(&state->frontend, 0);
/* Set IF AGC to acquisition */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
/* Initialisation */
stb0899_dvbs2_init_calc(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
switch (internal->inversion) {
case IQ_SWAP_OFF:
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
break;
case IQ_SWAP_ON:
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
break;
}
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
stb0899_dvbs2_reacquire(state);
/* Wait for demod lock (UWP and CSM) */
internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
if (internal->status == DVBS2_DEMOD_LOCK) {
dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
i = 0;
/* Demod Locked, check FEC status */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
/*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
/* Read the frequency offset*/
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
/* Set the Nominal frequency to the found frequency offset for the next reacquire*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
stb0899_dvbs2_reacquire(state);
internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
i++;
}
}
if (internal->status != DVBS2_FEC_LOCK) {
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
/* IQ Spectrum Inversion */
STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
/* start acquistion process */
stb0899_dvbs2_reacquire(state);
/* Wait for demod lock (UWP and CSM) */
internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
if (internal->status == DVBS2_DEMOD_LOCK) {
i = 0;
/* Demod Locked, check FEC */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
/*try thrice for false locks, (UWP and CSM Locked but no FEC) */
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
/* Read the frequency offset*/
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
/* Set the Nominal frequency to the found frequency offset for the next reacquire*/
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
stb0899_dvbs2_reacquire(state);
internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
i++;
}
}
/*
if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
pParams->IQLocked = !iqSpectrum;
*/
}
if (internal->status == DVBS2_FEC_LOCK) {
dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
(INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
(pilots == 1)) {
stb0899_dvbs2_init_csm(state, pilots, modcod);
/* Wait for UWP,CSM and data LOCK 20ms max */
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
i = 0;
while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
i++;
}
}
if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
(INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
(pilots == 1)) {
/* Equalizer Disable update */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
}
/* slow down the Equalizer once locked */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
/* Store signal parameters */
offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
offsetfreq = sign_extend32(offsetfreq, 29);
offsetfreq = offsetfreq / ((1 << 30) / 1000);
offsetfreq *= (internal->master_clk / 1000000);
/* store current inversion for next run */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
internal->inversion = IQ_SWAP_ON;
else
internal->inversion = IQ_SWAP_OFF;
internal->freq = internal->freq + offsetfreq;
internal->srate = stb0899_dvbs2_get_srate(state);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
/* Set IF AGC to tracking */
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
/* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
}
/* Release Stream Merger Reset */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
return internal->status;
}
| [
"erik.moqvist@gmail.com"
] | erik.moqvist@gmail.com |
fe75e8cc7da20b492d15370f292e8139f2f66ae2 | 46367579a54a09dd220dd9a678b1452f06897f11 | /tags/hdf5-1_6_2/test/ttsafe_acreate.c | d5ed7b71e2f441d95c48bc1b087dfc9160240a52 | [
"LicenseRef-scancode-llnl",
"LicenseRef-scancode-warranty-disclaimer"
] | permissive | TPLink32/hdf5 | 33ff24c9b6133f0f51cb6cc2b722fba7bb1777dd | 0d6987c15284bd9f34c7e44452a152833d42a738 | refs/heads/master | 2021-05-31T01:15:39.463663 | 2016-04-14T23:02:09 | 2016-04-14T23:02:09 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 5,386 | c | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Copyright by the Board of Trustees of the University of Illinois. *
* All rights reserved. *
* *
* This file is part of HDF5. The full HDF5 copyright notice, including *
* terms governing use, modification, and redistribution, is contained in *
* the files COPYING and Copyright.html. COPYING can be found at the root *
* of the source code distribution tree; Copyright.html can be found at the *
* root level of an installed copy of the electronic HDF5 document set and *
* is linked from the top-level documents page. It can also be found at *
* http://hdf.ncsa.uiuc.edu/HDF5/doc/Copyright.html. If you do not have *
* access to either file, you may request a copy from hdfhelp@ncsa.uiuc.edu. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
/********************************************************************
*
* Testing for thread safety in H5A (dataset attribute) library
* operations. -- Threaded program --
* ------------------------------------------------------------------
*
* Plan: Attempt to break H5Acreate by making many simultaneous create
* calls.
*
* Claim: N calls to H5Acreate should create N attributes for a dataset
* if threadsafe. If some unprotected shared data exists for the
* dataset (eg, a count of the number of attributes in the
* dataset), there is a small chance that consecutive reads occur
* before a write to that shared variable.
*
* HDF5 APIs exercised in thread:
* H5Acreate, H5Awrite, H5Aclose.
*
* Created: Oct 5 1999
* Programmer: Chee Wai LEE
*
* Modification History
* --------------------
*
* 15 May 2000, Chee Wai LEE
* Incorporated into library tests.
*
* 19 May 2000, Bill Wendling
* Changed so that it creates its own HDF5 file and removes it at cleanup
* time. Added num_errs flag.
*
********************************************************************/
#include "ttsafe.h"
#ifdef H5_HAVE_THREADSAFE
#include <stdio.h>
#include <stdlib.h>
#define FILENAME "ttsafe_acreate.h5"
#define DATASETNAME "IntData"
#define NUM_THREADS 16
void *tts_acreate_thread(void *);
typedef struct acreate_data_struct {
hid_t dataset;
hid_t datatype;
hid_t dataspace;
int current_index;
} ttsafe_name_data_t;
void tts_acreate(void)
{
/* Pthread declarations */
pthread_t threads[NUM_THREADS];
/* HDF5 data declarations */
hid_t file, dataset;
hid_t dataspace, datatype;
hid_t attribute;
hsize_t dimsf[1]; /* dataset dimensions */
/* data declarations */
int data; /* data to write */
int buffer, ret, i;
ttsafe_name_data_t *attrib_data;
/*
* Create an HDF5 file using H5F_ACC_TRUNC access, default file
* creation plist and default file access plist
*/
file = H5Fcreate(FILENAME, H5F_ACC_TRUNC, H5P_DEFAULT, H5P_DEFAULT);
/* create a simple dataspace for the dataset */
dimsf[0] = 1;
dataspace = H5Screate_simple(1, dimsf, NULL);
/* define datatype for the data using native little endian integers */
datatype = H5Tcopy(H5T_NATIVE_INT);
H5Tset_order(datatype, H5T_ORDER_LE);
/* create a new dataset within the file */
dataset = H5Dcreate(file, DATASETNAME, datatype, dataspace,
H5P_DEFAULT);
/* initialize data for dataset and write value to dataset */
data = NUM_THREADS;
H5Dwrite(dataset, H5T_NATIVE_INT, H5S_ALL, H5S_ALL,
H5P_DEFAULT, &data);
/*
* Simultaneously create a large number of attributes to be associated
* with the dataset
*/
for (i = 0; i < NUM_THREADS; i++) {
attrib_data = malloc(sizeof(ttsafe_name_data_t));
attrib_data->dataset = dataset;
attrib_data->datatype = datatype;
attrib_data->dataspace = dataspace;
attrib_data->current_index = i;
pthread_create(&threads[i], NULL, tts_acreate_thread,
attrib_data);
}
for (i = 0; i < NUM_THREADS; i++)
pthread_join(threads[i], NULL);
/* verify the correctness of the test */
for (i = 0; i < NUM_THREADS; i++) {
attribute = H5Aopen_name(dataset,gen_name(i));
if (attribute < 0) {
TestErrPrintf(
"unable to open appropriate attribute. "
"Test failed!\n");
} else {
ret = H5Aread(attribute, H5T_NATIVE_INT, &buffer);
if (ret < 0 || buffer != i) {
TestErrPrintf("wrong data values. Test failed!\n");
}
H5Aclose(attribute);
}
}
/* close remaining resources */
H5Sclose(dataspace);
H5Tclose(datatype);
H5Dclose(dataset);
H5Fclose(file);
}
void *tts_acreate_thread(void *client_data)
{
hid_t attribute;
char *attribute_name;
int *attribute_data; /* data for attributes */
ttsafe_name_data_t *attrib_data;
attrib_data = (ttsafe_name_data_t *)client_data;
/* Create attribute */
attribute_name = gen_name(attrib_data->current_index);
attribute = H5Acreate(attrib_data->dataset, attribute_name,
attrib_data->datatype, attrib_data->dataspace,
H5P_DEFAULT);
/* Write data to the attribute */
attribute_data = malloc(sizeof(int));
*attribute_data = attrib_data->current_index;
H5Awrite(attribute, H5T_NATIVE_INT, attribute_data);
H5Aclose(attribute);
return NULL;
}
void cleanup_acreate(void)
{
HDunlink(FILENAME);
}
#endif /*H5_HAVE_THREADSAFE*/
| [
"(no author)@dab4d1a6-ed17-0410-a064-d1ae371a2980"
] | (no author)@dab4d1a6-ed17-0410-a064-d1ae371a2980 |
632fba6fc18c5c1a16e99099113fa406e1017c94 | 7baf8e219624f892d340d75a57d01081d4db0880 | /src/symbols.c | 1a3ef829050ad0a445ad4368c765727b077842ad | [] | no_license | mickael-guene/exe2obj | 8006d6434afed7c2854c35f326530e5dd9562e2d | 159d151f8f4fd3881672f525c81803ee5c05be81 | refs/heads/master | 2021-01-17T17:51:54.816319 | 2016-07-05T08:12:37 | 2016-07-05T08:12:37 | 60,621,393 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 2,331 | c | #include <stdlib.h>
#include <string.h>
#include "symbols.h"
#include "utils.h"
#include "section.h"
static char *e2o_find_symbol_name(Elf *elf, uint32_t st_name)
{
Elf_Scn *strtab;
Elf_Data *d;
d = e2o_find_section_data_by_name(elf, ".strtab");
if (d == NULL)
display_elf_error_and_exit();
return st_name >= d->d_size ? NULL : d->d_buf + st_name;
}
uint32_t e2o_add_name_in_symbol_table(Elf *elf, char *name)
{
Elf_Scn *strtab;
Elf_Data *d;
strtab = e2o_find_section_by_name(elf, ".strtab");
if (strtab == NULL)
display_error_and_exit("Unable to find .strtab section\n");
d = elf_getdata(strtab, NULL);
if (d == NULL)
display_elf_error_and_exit();
d->d_buf = realloc(d->d_buf, d->d_size + strlen(name) + 1);
memcpy(d->d_buf + d->d_size, name, strlen(name));
d->d_size += strlen(name) + 1;
*(char *)(d->d_buf + d->d_size - 1) = 0;
return d->d_size - strlen(name) -1;
}
void e2o_add_symbol(Elf *elf, GElf_Sym *sym)
{
Elf_Scn *symtab;
Elf_Data *d;
Elf32_Sym sym32;
sym32.st_name = sym->st_name;
sym32.st_value = sym->st_value;
sym32.st_size = sym->st_size;
sym32.st_info = sym->st_info;
sym32.st_other = sym->st_other;
sym32.st_shndx = sym->st_shndx;
symtab = e2o_find_section_by_name(elf, ".symtab");
if (symtab == NULL)
display_error_and_exit("Unable to find .symtab section\n");
if (symtab == NULL)
display_elf_error_and_exit();
d = elf_getdata(symtab, NULL);
if (d == NULL)
display_elf_error_and_exit();
d->d_buf = realloc(d->d_buf, d->d_size + gelf_fsize(elf, ELF_T_SYM, 1, EV_CURRENT));
memcpy(d->d_buf + d->d_size, &sym32, gelf_fsize(elf, ELF_T_SYM, 1, EV_CURRENT));
d->d_size += gelf_fsize(elf, ELF_T_SYM, 1, EV_CURRENT);
}
size_t e2o_find_symbol_index_by_name(Elf *elf, char *name)
{
Elf_Data *d;
Elf32_Sym *sym;
int ndx = 0;
d = e2o_find_section_data_by_name(elf, ".symtab");
if (d == NULL)
display_elf_error_and_exit();
sym = d->d_buf;
while(sym < (Elf32_Sym *)(d->d_buf + d->d_size)) {
char *name_strtab = e2o_find_symbol_name(elf, sym->st_name);
if (name_strtab && strcmp(name, name_strtab) == 0)
return ndx;
ndx++;
sym++;
}
return 0;
}
| [
"mickael.guene@st.com"
] | mickael.guene@st.com |
f043250a751ebcbefbe7c8dc4ea1bf6a70cdfcb0 | 7d1798b4b15e1ca84689af394c49fb85e0497586 | /aurbrokenpkgcheck.c | 14ccebf642bdca98fe1d0e85c6cecfd251871205 | [
"MIT"
] | permissive | popsUlfr/aurbrokenpkgcheck | ff159dc1c991e87d7c62fc184dbbe4e84f456d6d | a1d78a8d1fdb7d6f452a5f86b810e8cb3183ae56 | refs/heads/master | 2021-03-13T01:30:54.051133 | 2017-05-16T15:50:23 | 2017-05-16T15:50:23 | 91,476,687 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 23,109 | c | /*
* MIT License
*
* Copyright (c) 2017 Philipp Richter
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <alpm.h>
#include <dirent.h>
#include <string.h>
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/wait.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <elf.h>
/* MACROS */
#define LIB_DIR "/lib"
#define LD_PREFIX "ld-linux"
#define LD_PREFIX_LENGTH 8
#define PACMAN_ROOT_PATH_KEY "Root"
#define PACMAN_DB_PATH_KEY "DB Path"
#define BUFFER_SIZE 256
/* MACROS */
/* STRUCTURES */
/* Stores intermediate states between parses */
struct stream_t {
/* Will be set by stream_parser() if NULL
* DO NOT CHANGE */
char *buffer;
/* Should reflect the maximum size of the buffer
* overwriten if buffer is NULL
* DO NOT CHANGE */
size_t maxsize;
/* Handled by stream_parser() should not be manually set
* DO NO CHANGE */
ssize_t length;
/* If left NULL will be set to "\r\n" by stream_parser()
* CAN BE CHANGED IN THE CALLBACK */
const char *delims;
/* represents the current token position
* DO NOT CHANGE */
int pos;
/* true if string is the beginning of a new token
* DO NOT CHANGE */
int beg;
/* true if string is the end of the current token
* DO NOT CHANGE */
int end;
/* the current '\0' terminated token
* DO NOT CHANGE */
char *string;
/* the length of the current token
* DO NOT CHANGE */
size_t string_length;
/* the delimiter that was replaced by '\0' for the current token
* DO NOT CHANGE */
char string_delim;
/* function to call once more data is available
* CAN BE CHANGED IN THE CALLBACK */
void (*callback)(struct stream_t *);
/* optional data to pass between calls
* CAN BE CHANGED IN THE CALLBACK */
void *data;
};
/* data for pacman_config_paths parses */
struct stream_pacman_config_paths_t {
/* will store the root path */
char *root_path;
/* maximum allowed size for the root path */
size_t root_path_maxsize;
/* real length of the root path */
size_t root_path_length;
/* will store the db path */
char *db_path;
/* maxium allowed path for the db path */
size_t db_path_maxsize;
/* real length of the db path */
size_t db_path_length;
/* pointer to the current path */
char *curr_path;
/* pointer to the current path maxsize */
size_t *curr_maxsize;
/* pointer to the current real length of path */
size_t *curr_length;
/* skip flag, 1 = will skip until next line */
int skip;
/* root path key */
const char* root_path_key;
/* db path key */
const char* db_path_key;
/* pointer to the current path key */
const char* curr_path_key;
};
/* data for foreign_pkgs parses */
struct stream_foreign_pkgs_t {
/* stores the pkgname */
char pkg[NAME_MAX];
/* real length of pkg */
size_t length;
/* the linked list containing the final pkgnames */
alpm_list_t *list;
};
/* data for pacman_config_paths stream handler */
struct pacman_config_paths_t {
/* the root path buffer */
char *root_path;
/* the root path maxsize and real length after the call */
size_t *root_path_length;
/* the db path buffer */
char *db_path;
/* the db path maxsize and real length after the call */
size_t *db_path_length;
};
/* data for check_package stream handler */
struct check_package_t {
/* package name */
const char* pkgname;
/* filename currently getting checked */
const char* filename;
/* the line we are at in the error output */
int line;
/* the token position we are at on the line */
int pos;
/* is set when a package is determined to be broken */
int broken;
/* flag set if the filename has already been printed */
int filename_printed;
/* flag sets color output */
int colors;
};
/* STRUCTURES */
/*
* error handler
*/
static inline int error_handler(const char* function_name) {
perror(function_name);
return errno;
}
/*
* Init the struct stream_t
*/
static inline void stream_parser_init(struct stream_t *st) {
memset(st, 0, sizeof(struct stream_t));
}
/*
* The stream parser reads by blocks instead of line by line
* The initial and intermediate states are stored in struct stream_t
* buffer and delims may be empty inside the struct, internal values will be used
*/
static void stream_parser(int fd, struct stream_t *st) {
char buffer[BUFFER_SIZE];
if (!st->buffer) {
st->buffer = buffer;
st->maxsize = BUFFER_SIZE;
st->length = 0;
}
if (!st->delims) st->delims = "\r\n";
st->beg = 1;
st->end = 0;
/* Subtract one to the size for there to be always the space for '\0' */
while((st->length = read(fd, st->buffer, (st->maxsize - 1))) > 0) {
st->buffer[st->length] = 0;
for (st->string = st->buffer;
;
st->string += st->string_length + 1) {
st->string_length = strcspn(st->string, st->delims);
if (!st->string_length && !st->string[st->string_length]) break;
st->string_delim = st->string[st->string_length];
st->string[st->string_length] = '\0';
if (st->end) {
++st->pos;
st->beg = 1;
st->end = 0;
}
if (st->string_delim) st->end = 1;
st->callback(st);
st->beg = 0;
if (!st->string_delim) break;
}
}
}
/*
* Consumes the whole stream
*/
static inline void noop_stream_handler(int fd, void* data) {
static char buffer[BUFFER_SIZE];
(void)data;
for(;read(fd,buffer, BUFFER_SIZE) > 0;) ;
}
/*
* Execs a command delegating stdout and stderr output to stream handlers
* noop_stream_handler for the handlers and NULL for the data may be used
* Will return the program exit code or -1 if an internal error occurred
*/
static int stream_exec(char *const* argv,
void (*stdout_stream_handler)(int,void*),
void * stdout_data,
void (*stderr_stream_handler)(int,void*),
void * stderr_data) {
int stderr_pipefd[2],stdout_pipefd[2];
pid_t pid;
if (pipe(stdout_pipefd) < 0 || pipe(stderr_pipefd) < 0) {
error_handler("pipe()");
return -1;
}
if ((pid = fork()) == 0) { // child
close(STDIN_FILENO);
close(stderr_pipefd[0]);
close(stdout_pipefd[0]);
dup2(stderr_pipefd[1], STDERR_FILENO);
close(stderr_pipefd[1]);
dup2(stdout_pipefd[1], STDOUT_FILENO);
close(stdout_pipefd[1]);
if (execvp(argv[0], argv) < 0) {
error_handler(argv[0]);
exit(-1);
}
}
else if (pid < 0) { //parent
close(stderr_pipefd[0]); close(stderr_pipefd[1]);
close(stdout_pipefd[0]); close(stdout_pipefd[1]);
error_handler("fork()");
return -1;
}
else { //parent
int wstatus;
close(stderr_pipefd[1]);
close(stdout_pipefd[1]);
stderr_stream_handler(stderr_pipefd[0], stderr_data);
close(stderr_pipefd[0]);
stdout_stream_handler(stdout_pipefd[0], stdout_data);
close(stdout_pipefd[0]);
if (waitpid(pid, &wstatus, 0) < 0) {
error_handler("waitpid()");
return -1;
}
if (WIFEXITED(wstatus)) return WEXITSTATUS(wstatus);
}
return -1;
}
/*
* Init struct stream_pacman_config_paths_t
* ATTENTION : root_path, db_path, root_path_maxsize, db_path_maxsize
* must be set before calling this function
*/
static void stream_parser_pacman_config_paths_init(
struct stream_pacman_config_paths_t *pst) {
pst->root_path_length = 0;
pst->db_path_length = 0;
pst->curr_path = pst->root_path;
pst->curr_maxsize = &(pst->root_path_maxsize);
pst->curr_length = &(pst->root_path_length);
pst->skip = 0;
pst->root_path_key = PACMAN_ROOT_PATH_KEY;
pst->db_path_key = PACMAN_DB_PATH_KEY;
pst->curr_path_key = pst->root_path_key;
}
/*
* Stream parser callback for pacman_config_paths
* st->data is struct stream_pacman_config_paths_t
* It looks for Root and DB Path
*/
static void stream_parser_pacman_config_paths_callback(struct stream_t *st) {
struct stream_pacman_config_paths_t * pst;
size_t len;
char * trimstart;
pst = (struct stream_pacman_config_paths_t *)(st->data);
/* Just return as fast as possible if all the info we needed has been collected */
if (!pst->curr_path) return;
if (pst->skip) {
/* The first token is the key while the second is the path
* skip is removed since we arrived at the end of the line
*/
if (st->end && st->pos % 2 == 1) pst->skip = 0;
return;
}
trimstart = st->string;
if (st->beg) {
*pst->curr_length = 0;
/* Trims the leading whitespace if any */
for (; *trimstart == ' ' ; ++trimstart) ;
len = st->string_length - (size_t)(trimstart - st->string);
}
else len = st->string_length;
/* Here's a check to prevent from writing out of bounds */
if (*pst->curr_length + len >= *(pst->curr_maxsize)) {
if (*pst->curr_length < *(pst->curr_maxsize) - 1)
len = *pst->curr_maxsize - *pst->curr_length - 1;
else
len = 0;
}
strncpy(pst->curr_path + (*pst->curr_length), trimstart, len);
(*pst->curr_length) += len;
if (st->end) {
char *trimend;
/* Trim the trailing whitespace */
for (trimend = pst->curr_path + *pst->curr_length;
trimend > pst->curr_path && *(trimend - 1) == ' '; --trimend) ;
if (trimend == pst->curr_path) {
/* This means our current token is completely empty, so skip this garbage */
pst->skip = 1;
return;
}
*pst->curr_length = (size_t)(trimend - pst->curr_path);
if (st->pos % 2 == 0) {
/* This is the key token, since we're at the end we can test if it's
* the one we want
*/
if (*pst->curr_length != strlen(pst->curr_path_key)
|| strncmp(pst->curr_path_key, pst->curr_path, *pst->curr_length)) {
/* It wasn't the one so skip the whole line */
pst->skip = 1;
return;
}
}
else {
/* This is the end of the line, our token is inside our buffer
* just set the terminating '\0'
*/
pst->curr_path[*pst->curr_length] = 0;
if (pst->curr_path == pst->root_path) {
/* For all this to work, it expects the Root key to happend before
* the DB Path key.
* Once the Root key is done, switch the links to the DB Path
*/
pst->curr_path = pst->db_path;
pst->curr_length = &(pst->db_path_length);
pst->curr_maxsize = &(pst->db_path_maxsize);
pst->curr_path_key = pst->db_path_key;
}
else {
/* We got all we need */
pst->curr_path = NULL;
pst->curr_length = NULL;
pst->curr_maxsize = NULL;
pst->curr_path_key = NULL;
}
}
}
}
/*
* Stream handler for pacman_config_paths
* fd is stdout
* data is struct pacman_config_paths_t
*/
static void pacman_config_paths_stream_handler(int fd, void * data) {
struct stream_pacman_config_paths_t pst;
struct stream_t st;
struct pacman_config_paths_t *pcp = (struct pacman_config_paths_t*)data;
pst.root_path = pcp->root_path;
pst.root_path_maxsize = *(pcp->root_path_length);
pst.db_path = pcp->db_path;
pst.db_path_maxsize = *(pcp->db_path_length);
stream_parser_pacman_config_paths_init(&pst);
stream_parser_init(&st);
st.callback = stream_parser_pacman_config_paths_callback;
st.data = &pst;
st.delims = ":\r\n";
stream_parser(fd, &st);
*pcp->root_path_length = pst.root_path_length;
*pcp->db_path_length = pst.db_path_length;
}
/*
* Runs pacman --verbose in order to get default root and dbpath
* root_path_length and db_path_length are pointers to the maximum allowed size
* of the respective buffers. After the call they will contain the real length
* of the contents
*/
static int pacman_config_paths(
char *root_path,
size_t *root_path_length,
char *db_path,
size_t *db_path_length
) {
struct pacman_config_paths_t pcp;
char *const cmd[] = { "pacman", "--verbose", NULL };
pcp.root_path = root_path;
pcp.root_path_length = root_path_length;
pcp.db_path = db_path;
pcp.db_path_length = db_path_length;
return stream_exec(cmd,
pacman_config_paths_stream_handler, &pcp, noop_stream_handler, NULL);
}
/* Just a filter checking for the allowed ld prefix for scandir() */
static inline int ld_filter(const struct dirent* entry) {
return !strncmp(LD_PREFIX, entry->d_name, LD_PREFIX_LENGTH);
}
/*
* Finds the best ld for bin
* The ld path is stored inside ld_bin_path
* Anything other than 0 returned is an error
*/
static int ld_bin_finder(char * ld_bin_path, size_t ld_bin_path_length, char* bin) {
int nbentries, i, last_error;
struct dirent **list;
char *const cmd[] = {ld_bin_path, "--verify", bin, NULL};
last_error = 0;
if ((nbentries = scandir(LIB_DIR, &list, ld_filter, alphasort)) < 0)
return error_handler("scandir()");
if (nbentries <= 0) return 1;
for (i = 0; i < nbentries; ++i) {
struct stat statbuf;
int ret;
last_error = 0;
snprintf(ld_bin_path, ld_bin_path_length, "%s/%s", LIB_DIR, list[i]->d_name);
free(list[i]);
if (stat(ld_bin_path, &statbuf) < 0) {
last_error = error_handler(ld_bin_path);
continue;
}
/* Check if it's user executable */
if (!S_ISREG(statbuf.st_mode) || !(statbuf.st_mode & S_IXUSR)) {
last_error = 1;
continue;
}
/* The ld --verify command may return 0 or 2 in order to catch the compatible ld */
if ((ret = stream_exec(
cmd,
noop_stream_handler,
NULL,
noop_stream_handler,
NULL)) == 0 || ret == 2) break;
}
for (; ++i < nbentries;) free(list[i]);
free(list);
return last_error;
}
/*
* Init struct stream_foreign_pkgs_t
*/
static inline void stream_parser_foreign_pkgs_init(struct stream_foreign_pkgs_t *sfp) {
sfp->length = 0;
sfp->list = NULL;
}
/*
* Stream parser callback for foreign_packages
* st->data is struct stream_foreign_pkgs_t
*/
static void stream_parser_foreign_pkgs_callback(struct stream_t *st) {
struct stream_foreign_pkgs_t *sfp = (struct stream_foreign_pkgs_t*)(st->data);
if (st->beg) sfp->length = 0;
strncpy(sfp->pkg + sfp->length, st->string, st->string_length);
sfp->length += st->string_length;
if (st->end) {
sfp->pkg[sfp->length] = 0;
sfp->list = alpm_list_add(sfp->list, strdup(sfp->pkg));
}
}
/*
* Stream handler for foreign_packages
* fd is stdout
* data is alpm_list_t**
*/
static void foreign_packages_stream_handler(int fd, void * data) {
struct stream_t st;
struct stream_foreign_pkgs_t sfp;
alpm_list_t **list = (alpm_list_t **)data;
stream_parser_foreign_pkgs_init(&sfp);
sfp.list = *list;
stream_parser_init(&st);
st.delims = "\r\n";
st.callback = stream_parser_foreign_pkgs_callback;
st.data = &sfp;
stream_parser(fd, &st);
*list = sfp.list;
}
/*
* Stores the foreign packages in list
* Anything other than 0 returned is an error
* However even if list is set to NULL, it needs to be freed afterwards
*/
static inline int foreign_packages(
alpm_list_t **list,
char* root_path,
char* db_path) {
char *const cmd[] = {
"pacman",
"--root", root_path,
"--dbpath", db_path,
"--query",
"--foreign",
"--quiet",
NULL };
return stream_exec(
cmd,
foreign_packages_stream_handler,
list,
noop_stream_handler,
NULL);
}
/*
* Simple check for the ELF magic bytes on the file
* Anything other than 0 returned is not an ELF or an error
*/
static int check_for_elf_header(const char* filename) {
int fd;
char elfbuffer[4];
ssize_t len;
if ((fd = open(filename, O_RDONLY)) < 0)
return error_handler(filename);
if ((len = read(fd, elfbuffer, 4)) < 0) {
int ret = error_handler(filename);
close(fd);
return ret;
}
close(fd);
return (len != 4
|| elfbuffer[0] != ELFMAG0
|| elfbuffer[1] != ELFMAG1
|| elfbuffer[2] != ELFMAG2
|| elfbuffer[3] != ELFMAG3);
}
/*
* The stream parser callback for check_package
* st->data carries a struct check_package_t
*/
static void stream_parser_check_package_callback(struct stream_t *st) {
struct check_package_t* cpt = (struct check_package_t*)(st->data);
if (!cpt->broken) {
/* Print the stdout package name only once */
if (cpt->colors) fprintf(stdout, "\033[0;34m%s\033[0m\n", cpt->pkgname);
else fprintf(stdout, "%s\n", cpt->pkgname);
cpt->broken = 1;
}
if (!cpt->filename_printed) {
/* This is the filename line */
fprintf(stderr, " └── %s\n", cpt->filename);
cpt->filename_printed = 1;
}
if (st->beg && cpt->pos == 2) {
/* We are positioned directly after the second colon, start printing */
if (cpt->colors) fprintf(stderr, " └──\033[0;31m");
else fprintf(stderr, " └──");
}
if (cpt->pos > 1)
fprintf(stderr, "%.*s", (int)(st->string_length), st->string);
if (st->end) {
if (st->string_delim == '\r' || st->string_delim == '\n') {
/* We hit the end of a line here */
if (cpt->colors) fprintf(stderr, "\033[0m\n");
else fprintf(stderr, "\n");
++cpt->line;
cpt->pos = 0;
}
else {
/* The stream parser overwrote the delimiter, so we print it ourselves */
if (cpt->pos > 1) fprintf(stderr, "%c", st->string_delim);
++cpt->pos;
}
}
}
/*
* Stream handler callback for check_package
* fd is the error output
* data is a struct check_package_t
*/
static void check_package_stream_handler(int fd, void * data) {
struct stream_t st;
stream_parser_init(&st);
/* The goal is to start printing the ld error output after the second colon
* Anything before that is redundant information
*/
st.delims = ":\r\n";
st.callback = stream_parser_check_package_callback;
st.data = data;
stream_parser(fd, &st);
}
/*
* Checks a package for broken dependencies
* colors enables/disables colored output
*
* Anything other than 0 returned is a fatal error
*/
static int check_package(
alpm_handle_t *handle,
alpm_db_t *db_local,
const char* pkgname,
const char* root_path,
int colors) {
alpm_pkg_t *pkg;
alpm_filelist_t *filelist;
size_t i;
char filename[PATH_MAX];
char ld_bin_path[PATH_MAX];
char * slash;
int has_ending_slash;
struct check_package_t cpt;
/* Calling ld with --list will produce error output in case of broken lib */
char *const cmd[] = {ld_bin_path, "--list", filename, NULL};
if (!(pkg = alpm_db_get_pkg(db_local, pkgname))) {
fprintf(stderr, "%s\n", alpm_strerror(alpm_errno(handle)));
return 1;
}
if (!(filelist = alpm_pkg_get_files(pkg))) {
alpm_pkg_free(pkg);
fprintf(stderr, "%s\n", alpm_strerror(alpm_errno(handle)));
return 1;
}
has_ending_slash = ((slash = strrchr(root_path, '/')) && slash[1] == 0);
cpt.pkgname = pkgname;
cpt.filename = filename;
cpt.broken = 0;
cpt.colors = colors;
for (i = 0; i < filelist->count; ++i) {
struct stat statbuf;
/* If the name ends with a '/' then it's a directory */
if ((slash = strrchr(filelist->files[i].name, '/')) && slash[1] == 0)
continue;
/* Filenames do not have a leading '/' */
snprintf(filename, PATH_MAX, "%s%s%s",
root_path, (has_ending_slash)?"":"/", filelist->files[i].name);
if (stat(filename, &statbuf) < 0) {
/* Not caring about handling stat errors */
continue;
}
/* Check if the file is user executable */
if (!S_ISREG(statbuf.st_mode) || !(statbuf.st_mode & S_IXUSR))
continue;
/* We are only interested in ELF files, so quickly check the header */
if (check_for_elf_header(filename)) continue;
/* Find the correct ld binary which can do something useful with the file */
if (ld_bin_finder(ld_bin_path, PATH_MAX, filename))
continue;
cpt.line = 0;
cpt.pos = 0;
cpt.filename_printed = 0;
/* Exec ld on our file, only stderr output is interesting */
stream_exec(
cmd,
noop_stream_handler,
NULL,
check_package_stream_handler,
&cpt);
}
alpm_pkg_free(pkg);
return 0;
}
static void usage(const char* arg0) {
fprintf(stdout, "Usage: %s [-h|--help] [-b|--dbpath DBPATH] [-r|--root ROOT] [--colors] [--no-colors]\n", arg0);
fprintf(stdout, "Options:\n");
fprintf(stdout, "\t -h,--help : This help\n");
fprintf(stdout, "\t -b,--dbpath DBPATH : The database location to use (see man 8 pacman)\n");
fprintf(stdout, "\t -r,--root ROOT : The installation root to use (see man 8 pacman)\n");
fprintf(stdout, "\t --colors : Enable colored output (default)\n");
fprintf(stdout, "\t --no-colors : Disable colored output\n");
}
int main(int argc, const char* argv[]) {
alpm_list_t *list,*i;
alpm_db_t *db_local;
alpm_errno_t err;
alpm_handle_t *handle;
const char** arg;
char root_path[PATH_MAX],db_path[PATH_MAX];
size_t root_path_length,db_path_length;
int colors;
(void)argc;
root_path_length = PATH_MAX;
db_path_length = PATH_MAX;
colors = 1;
/* The default pacman paths are taken from its verbose output */
if (pacman_config_paths(
root_path, &root_path_length,
db_path, &db_path_length) < 0 || !root_path_length || !db_path_length) {
return EXIT_FAILURE;
}
for (arg = argv + 1; *arg ; ++arg) {
if (!strcmp(*arg, "-b") || !strcmp(*arg, "--dbpath")) {
if (!*(++arg)) {
fprintf(stderr, "Missing argument for '%s'\n", *(arg - 1));
usage(*argv);
return EXIT_FAILURE;
}
strncpy(db_path, *arg, PATH_MAX);
}
else if (!strcmp(*arg, "-r") || !strcmp(*arg, "--root")) {
if (!*(++arg)) {
fprintf(stderr, "Missing argument for '%s'\n", *(arg - 1));
usage(*argv);
return EXIT_FAILURE;
}
strncpy(root_path, *arg, PATH_MAX);
}
else if (!strcmp(*arg, "-h") || !strcmp(*arg, "--help")) {
usage(*argv);
return EXIT_SUCCESS;
}
else if (!strcmp(*arg, "--colors")) {
colors = 1;
}
else if (!strcmp(*arg, "--no-colors")) {
colors = 0;
}
else {
fprintf(stderr, "Unknown option '%s'\n", *arg);
usage(*argv);
return EXIT_FAILURE;
}
}
/* Print the used paths */
fprintf(stderr, "%-8s : %s\n", PACMAN_ROOT_PATH_KEY, root_path);
fprintf(stderr, "%-8s : %s\n", PACMAN_DB_PATH_KEY, db_path);
list = NULL;
/* This calls pacman for foreign packages and loads them into our list */
if (foreign_packages(&list, root_path, db_path)) {
FREELIST(list);
return EXIT_FAILURE;
}
/* Initialize alpm handle */
if (!(handle = alpm_initialize(root_path, db_path, &err))) {
fprintf(stderr, "%s\n", alpm_strerror(err));
return EXIT_FAILURE;
}
if (!(db_local = alpm_get_localdb(handle))) {
fprintf(stderr, "%s\n", alpm_strerror(alpm_errno(handle)));
return EXIT_FAILURE;
}
/* Check each package for broken libs or binaries */
for (i = list; i; i = alpm_list_next(i))
check_package(handle, db_local, (char*)(i->data), root_path, colors);
FREELIST(list);
/* Always release the handle */
if (alpm_release(handle) < 0) {
fprintf(stderr, "%s\n", alpm_strerror(alpm_errno(handle)));
return EXIT_FAILURE;
}
return EXIT_SUCCESS;
}
| [
"richterphilipp.pops@gmail.com"
] | richterphilipp.pops@gmail.com |
d79d043e234666a7d11135098094248efc45ca98 | bc75d6ae5eb56b79f02cf4acd5ec456f8340875e | /src/index.h | 4d0fe853602e840989b32c8188fddead89c744d3 | [] | no_license | wkkuna/music_generator | ab4b756b7f35a60a78df0d77efce2535bea15b08 | 07440f03e67699987ac309b3d299a1a98448fbaf | refs/heads/master | 2023-04-02T21:52:44.276954 | 2021-04-10T21:03:28 | 2021-04-10T21:03:28 | 233,657,665 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 245 | h | #ifndef INDEX_H
#define INDEX_H
#include <stdio.h>
#include <stdlib.h>
//#include <stddef.h>
#include <string.h>
#include <stdbool.h>
#include <time.h>
#define NUM_OF_CHORDS 834
#define CHORD_LENGHT 100
const char *separator = "$\n";
#endif
| [
"wi256@o2.pl"
] | wi256@o2.pl |
30357243a9ac767d04908924e763da26732f9d20 | 340a375029cbd87d774801299371f1c782b2f944 | /include/my_temp_sens.h | 5d8e61b94389b8af4e6e28e28360e6faa1f762da | [] | no_license | M4444/MS-project | b4e4ed5b35a6ba3ceb11dc659f8fd9ea32f12e83 | b343b311ce2dc7e0bf2edbbdc45e02bedac2fab9 | refs/heads/master | 2020-03-21T11:57:28.997361 | 2018-06-25T01:43:22 | 2018-06-25T01:43:22 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 787 | h | #ifndef _my_temp_sens_h_
#define _my_temp_sens_h_
#include <stm32f4xx_hal.h>
#include "my_tim.h"
/* my constants */
#define DS1820_ID (uint8_t) 0x10
/* my structures */
typedef struct temp_sens
{
uint16_t _dq_pin;
GPIO_TypeDef * _dq_GPIO_port;
float temp;
uint16_t error_flag;
} TempSens;
/* my functions */
void MY_TEMPSENS_GPIO_Init();
void MY_TEMPSENS_Init(TempSens *ts);
uint8_t getTemp(TempSens *ts);
void storeAndReadTemp(TempSens *ts);
void readTemp(TempSens *ts);
uint8_t reset(TempSens *ts);
void skip(TempSens *ts);
void tempConvert(TempSens *ts);
void readSP(TempSens *ts);
void writeTS(TempSens *ts, uint8_t v);
void write_bit(TempSens *ts, uint8_t v);
uint8_t read(TempSens *ts);
GPIO_PinState read_bit(TempSens *ts);
#endif /* _my_temp_sens_h_ */
| [
"mc.cm.mail@gmail.com"
] | mc.cm.mail@gmail.com |
4b8fa8d767178dbc9b7bd6d92f6e7cfc174fba6f | 550107f80a36a19c6ae44ce1331b1bc1dda43b25 | /IAR/FlashIMXRT1050RT1020_EVK_FlexSPI_All_in_One_IAR/devices/MIMXRT1050/MIMXRT1052.h | 59546fd5635127f83dc5ed7b135f98e1e6e6164b | [] | no_license | Marous-LXB/All-in-One-Flash-Algorithm-for-RT1050-RT1020 | eef55e79853f91069ba171e240702a8ff09f3954 | fccf6b48ec612edee30785aae5c190cb2c67f3f8 | refs/heads/master | 2023-04-05T01:07:05.998226 | 2021-02-01T02:26:20 | 2021-02-01T02:26:20 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,083,915 | h | /*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** MCUXpresso Compiler
**
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 0.1, 2017-01-10
** Build: b180509
**
** Abstract:
** CMSIS Peripheral Access Layer for MIMXRT1052
**
** The Clear BSD License
** Copyright 1997-2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted (subject to the limitations in the
** disclaimer below) provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright
** notice, this list of conditions and the following disclaimer.
**
** * Redistributions in binary form must reproduce the above copyright
** notice, this list of conditions and the following disclaimer in the
** documentation and/or other materials provided with the distribution.
**
** * Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from
** this software without specific prior written permission.
**
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 0.1 (2017-01-10)
** Initial version.
**
** ###################################################################
*/
/*!
* @file MIMXRT1052.h
* @version 0.1
* @date 2017-01-10
* @brief CMSIS Peripheral Access Layer for MIMXRT1052
*
* CMSIS Peripheral Access Layer for MIMXRT1052
*/
#ifndef _MIMXRT1052_H_
#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0000U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 176 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
/* Device specific interrupts */
DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
CTI0_ERROR_IRQn = 17, /**< CTI0_Error */
CTI1_ERROR_IRQn = 18, /**< CTI1_Error */
CORE_IRQn = 19, /**< CorePlatform exception IRQ */
LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
CAN1_IRQn = 36, /**< CAN1 interrupt */
CAN2_IRQn = 37, /**< CAN2 interrupt */
FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
KPP_IRQn = 39, /**< Keypad nterrupt */
TSC_DIG_IRQn = 40, /**< TSC interrupt */
GPR_IRQ_IRQn = 41, /**< GPR interrupt */
LCDIF_IRQn = 42, /**< LCDIF interrupt */
CSI_IRQn = 43, /**< CSI interrupt */
PXP_IRQn = 44, /**< PXP interrupt */
WDOG2_IRQn = 45, /**< WDOG2 interrupt */
SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */
SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */
SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
CSU_IRQn = 49, /**< CSU interrupt */
DCP_IRQn = 50, /**< DCP_IRQ interrupt */
DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */
Reserved68_IRQn = 52, /**< Reserved interrupt */
TRNG_IRQn = 53, /**< TRNG interrupt */
SJC_IRQn = 54, /**< SJC interrupt */
BEE_IRQn = 55, /**< BEE interrupt */
SAI1_IRQn = 56, /**< SAI1 interrupt */
SAI2_IRQn = 57, /**< SAI1 interrupt */
SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
SPDIF_IRQn = 60, /**< SPDIF interrupt */
ANATOP_EVENT0_IRQn = 61, /**< ANATOP interrupt */
ANATOP_EVENT1_IRQn = 62, /**< ANATOP interrupt */
ANATOP_TAMP_LOW_HIGH_IRQn = 63, /**< ANATOP interrupt */
ANATOP_TEMP_PANIC_IRQn = 64, /**< ANATOP interrupt */
USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */
USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */
ADC1_IRQn = 67, /**< ADC1 interrupt */
ADC2_IRQn = 68, /**< ADC2 interrupt */
DCDC_IRQn = 69, /**< DCDC interrupt */
Reserved86_IRQn = 70, /**< Reserved interrupt */
Reserved87_IRQn = 71, /**< Reserved interrupt */
GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */
WDOG1_IRQn = 92, /**< WDOG1 interrupt */
RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
EWM_IRQn = 94, /**< EWM interrupt */
CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
GPC_IRQn = 97, /**< GPC interrupt */
SRC_IRQn = 98, /**< SRC interrupt */
Reserved115_IRQn = 99, /**< Reserved interrupt */
GPT1_IRQn = 100, /**< GPT1 interrupt */
GPT2_IRQn = 101, /**< GPT2 interrupt */
PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
Reserved123_IRQn = 107, /**< Reserved interrupt */
FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
SEMC_IRQn = 109, /**< Reserved interrupt */
USDHC1_IRQn = 110, /**< USDHC1 interrupt */
USDHC2_IRQn = 111, /**< USDHC2 interrupt */
USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */
USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
ENET_IRQn = 114, /**< ENET interrupt */
ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
PIT_IRQn = 122, /**< PIT interrupt */
ACMP1_IRQn = 123, /**< ACMP interrupt */
ACMP2_IRQn = 124, /**< ACMP interrupt */
ACMP3_IRQn = 125, /**< ACMP interrupt */
ACMP4_IRQn = 126, /**< ACMP interrupt */
Reserved143_IRQn = 127, /**< Reserved interrupt */
Reserved144_IRQn = 128, /**< Reserved interrupt */
ENC1_IRQn = 129, /**< ENC1 interrupt */
ENC2_IRQn = 130, /**< ENC2 interrupt */
ENC3_IRQn = 131, /**< ENC3 interrupt */
ENC4_IRQn = 132, /**< ENC4 interrupt */
TMR1_IRQn = 133, /**< TMR1 interrupt */
TMR2_IRQn = 134, /**< TMR2 interrupt */
TMR3_IRQn = 135, /**< TMR3 interrupt */
TMR4_IRQn = 136, /**< TMR4 interrupt */
PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */
PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */
PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */
Reserved168_IRQn = 152, /**< Reserved interrupt */
Reserved169_IRQn = 153, /**< Reserved interrupt */
Reserved170_IRQn = 154, /**< Reserved interrupt */
Reserved171_IRQn = 155, /**< Reserved interrupt */
Reserved172_IRQn = 156, /**< Reserved interrupt */
Reserved173_IRQn = 157, /**< Reserved interrupt */
SJC_ARM_DEBUG_IRQn = 158, /**< SJC ARM debug interrupt */
NMI_WAKEUP_IRQn = 159 /**< NMI wake up */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M7 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
* @{
*/
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
#include "core_cm7.h" /* Core Peripheral Access Layer */
//#include "system_MIMXRT1052.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @addtogroup edma_request
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the DMA0 hardware request
*
* Defines the enumeration for the DMA0 hardware request collections.
*/
typedef enum _dma_request_source
{
kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 */
kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 */
kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
kDmaRequestMuxCSI = 12|0x100U, /**< CSI */
kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
kDmaRequestMuxSai1Rx = 19|0x100U, /**< Sai1 Receive */
kDmaRequestMuxSai1Tx = 20|0x100U, /**< Sai1 Transmit */
kDmaRequestMuxSai2Rx = 21|0x100U, /**< Sai2 Receive */
kDmaRequestMuxSai2Tx = 22|0x100U, /**< Sai2 Transmit */
kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
kDmaRequestMuxACMP2 = 26|0x100U, /**< ACMP2 */
kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */
kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */
kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */
kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */
kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */
kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */
kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */
kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< QTIMER3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 57|0x100U, /**< QTIMER3 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 58|0x100U, /**< QTIMER3 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 59|0x100U, /**< QTIMER3 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 */
kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 */
kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
kDmaRequestMuxPxp = 75|0x100U, /**< PXP */
kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */
kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
kDmaRequestMuxSai3Rx = 83|0x100U, /**< Sai3 Receive */
kDmaRequestMuxSai3Tx = 84|0x100U, /**< Sai3 Transmit */
kDmaRequestMuxSpdifRx = 85|0x100U, /**< Spdif Receive */
kDmaRequestMuxSpdifTx = 86|0x100U, /**< Spdif Transmit */
kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
kDmaRequestMuxACMP3 = 89|0x100U, /**< ACMP3 */
kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< Enet Timer0 */
kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< Enet Timer1 */
kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */
kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */
kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */
kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */
kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< QTIMER2 Capture timer 0 */
kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< QTIMER2 Capture timer 1 */
kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< QTIMER2 Capture timer 2 */
kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< QTIMER2 Capture timer 3 */
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< QTIMER2 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< QTIMER2 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< QTIMER2 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< QTIMER2 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< QTIMER4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer0Cmpld2Timer1 = 121|0x100U, /**< QTIMER4 capture timer 1, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer0Cmpld2Timer1 = 122|0x100U, /**< QTIMER4 capture timer 2, cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer0Cmpld2Timer1 = 123|0x100U, /**< QTIMER4 capture timer 3, cmpld1 in timer 0 or cmpld2 in timer 1 */
} dma_request_source_t;
/* @} */
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_mux_ctl_pad
{
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
} iomuxc_sw_mux_ctl_pad_t;
/* @} */
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_pad_ctl_pad
{
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
} iomuxc_sw_pad_ctl_pad_t;
/* @} */
/*!
* @brief Enumeration for the IOMUXC select input
*
* Defines the enumeration for the IOMUXC select input collections.
*/
typedef enum _iomuxc_select_input
{
kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */
kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */
kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */
kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */
kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */
kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */
kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */
kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */
kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */
kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */
kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */
kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */
kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */
kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */
kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */
kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */
kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */
kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */
kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */
kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */
kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */
kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */
kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */
kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */
kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */
kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */
kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */
kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */
kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */
kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */
kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */
kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */
kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */
kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */
kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */
kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */
kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */
kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */
kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */
kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */
kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */
kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */
kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */
} iomuxc_select_input_t;
typedef enum _xbar_input_signal
{
kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */
kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */
kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */
kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */
kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */
kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */
kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */
kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */
kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */
kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */
kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */
kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */
kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */
kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */
kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
} xbar_input_signal_t;
typedef enum _xbar_output_signal
{
kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */
kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */
kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */
kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */
kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */
kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */
kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
} xbar_output_signal_t;
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#else
#pragma push
#pragma anon_unions
#endif
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
__I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
__I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
__IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
__IO uint32_t GC; /**< General control register, offset: 0x48 */
__IO uint32_t GS; /**< General status register, offset: 0x4C */
__IO uint32_t CV; /**< Compare value register, offset: 0x50 */
__IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
__IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/*! @name HC - Control register for hardware triggers */
/*! @{ */
#define ADC_HC_ADCH_MASK (0x1FU)
#define ADC_HC_ADCH_SHIFT (0U)
#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
#define ADC_HC_AIEN_MASK (0x80U)
#define ADC_HC_AIEN_SHIFT (7U)
#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
/*! @} */
/* The count of ADC_HC */
#define ADC_HC_COUNT (8U)
/*! @name HS - Status register for HW triggers */
/*! @{ */
#define ADC_HS_COCO0_MASK (0x1U)
#define ADC_HS_COCO0_SHIFT (0U)
#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
/*! @} */
/*! @name R - Data result register for HW triggers */
/*! @{ */
#define ADC_R_CDATA_MASK (0xFFFU)
#define ADC_R_CDATA_SHIFT (0U)
#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
/*! @} */
/* The count of ADC_R */
#define ADC_R_COUNT (8U)
/*! @name CFG - Configuration register */
/*! @{ */
#define ADC_CFG_ADICLK_MASK (0x3U)
#define ADC_CFG_ADICLK_SHIFT (0U)
#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
#define ADC_CFG_MODE_MASK (0xCU)
#define ADC_CFG_MODE_SHIFT (2U)
#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
#define ADC_CFG_ADLSMP_MASK (0x10U)
#define ADC_CFG_ADLSMP_SHIFT (4U)
#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
#define ADC_CFG_ADIV_MASK (0x60U)
#define ADC_CFG_ADIV_SHIFT (5U)
#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
#define ADC_CFG_ADLPC_MASK (0x80U)
#define ADC_CFG_ADLPC_SHIFT (7U)
#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
#define ADC_CFG_ADSTS_MASK (0x300U)
#define ADC_CFG_ADSTS_SHIFT (8U)
#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
#define ADC_CFG_ADHSC_MASK (0x400U)
#define ADC_CFG_ADHSC_SHIFT (10U)
#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
#define ADC_CFG_REFSEL_MASK (0x1800U)
#define ADC_CFG_REFSEL_SHIFT (11U)
#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define ADC_CFG_ADTRG_MASK (0x2000U)
#define ADC_CFG_ADTRG_SHIFT (13U)
#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
#define ADC_CFG_AVGS_MASK (0xC000U)
#define ADC_CFG_AVGS_SHIFT (14U)
#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
#define ADC_CFG_OVWREN_MASK (0x10000U)
#define ADC_CFG_OVWREN_SHIFT (16U)
#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
/*! @} */
/*! @name GC - General control register */
/*! @{ */
#define ADC_GC_ADACKEN_MASK (0x1U)
#define ADC_GC_ADACKEN_SHIFT (0U)
#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
#define ADC_GC_DMAEN_MASK (0x2U)
#define ADC_GC_DMAEN_SHIFT (1U)
#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
#define ADC_GC_ACREN_MASK (0x4U)
#define ADC_GC_ACREN_SHIFT (2U)
#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
#define ADC_GC_ACFGT_MASK (0x8U)
#define ADC_GC_ACFGT_SHIFT (3U)
#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
#define ADC_GC_ACFE_MASK (0x10U)
#define ADC_GC_ACFE_SHIFT (4U)
#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
#define ADC_GC_AVGE_MASK (0x20U)
#define ADC_GC_AVGE_SHIFT (5U)
#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
#define ADC_GC_ADCO_MASK (0x40U)
#define ADC_GC_ADCO_SHIFT (6U)
#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
#define ADC_GC_CAL_MASK (0x80U)
#define ADC_GC_CAL_SHIFT (7U)
#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
/*! @} */
/*! @name GS - General status register */
/*! @{ */
#define ADC_GS_ADACT_MASK (0x1U)
#define ADC_GS_ADACT_SHIFT (0U)
#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
#define ADC_GS_CALF_MASK (0x2U)
#define ADC_GS_CALF_SHIFT (1U)
#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
#define ADC_GS_AWKST_MASK (0x4U)
#define ADC_GS_AWKST_SHIFT (2U)
#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
/*! @} */
/*! @name CV - Compare value register */
/*! @{ */
#define ADC_CV_CV1_MASK (0xFFFU)
#define ADC_CV_CV1_SHIFT (0U)
#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
#define ADC_CV_CV2_MASK (0xFFF0000U)
#define ADC_CV_CV2_SHIFT (16U)
#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
/*! @} */
/*! @name OFS - Offset correction value register */
/*! @{ */
#define ADC_OFS_OFS_MASK (0xFFFU)
#define ADC_OFS_OFS_SHIFT (0U)
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define ADC_OFS_SIGN_MASK (0x1000U)
#define ADC_OFS_SIGN_SHIFT (12U)
#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
/*! @} */
/*! @name CAL - Calibration value register */
/*! @{ */
#define ADC_CAL_CAL_CODE_MASK (0xFU)
#define ADC_CAL_CAL_CODE_SHIFT (0U)
#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x400C4000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
/** Peripheral ADC2 base address */
#define ADC2_BASE (0x400C8000u)
/** Peripheral ADC2 base pointer */
#define ADC2 ((ADC_Type *)ADC2_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ADC_ETC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
* @{
*/
/** ADC_ETC - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
__IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
__IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
__IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x28 */
__IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */
__IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
__I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
__I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
__I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
__I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
} TRIG[8];
} ADC_ETC_Type;
/* ----------------------------------------------------------------------------
-- ADC_ETC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
* @{
*/
/*! @name CTRL - ADC_ETC Global Control Register */
/*! @{ */
#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
/*! @} */
/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
/*! @{ */
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
/*! @} */
/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
/*! @{ */
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
/*! @} */
/*! @name DMA_CTRL - ETC DMA control Register */
/*! @{ */
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
/*! @} */
/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
/*! @{ */
#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CTRL */
#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
/*! @{ */
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_COUNTER */
#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
/*!
* @}
*/ /* end of group ADC_ETC_Register_Masks */
/* ADC_ETC - Peripheral instance base addresses */
/** Peripheral ADC_ETC base address */
#define ADC_ETC_BASE (0x403B0000u)
/** Peripheral ADC_ETC base pointer */
#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
/** Array initializer of ADC_ETC peripheral base addresses */
#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
/** Array initializer of ADC_ETC peripheral base pointers */
#define ADC_ETC_BASE_PTRS { ADC_ETC }
/** Interrupt vectors for the ADC_ETC peripheral type */
#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
/*!
* @}
*/ /* end of group ADC_ETC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AIPSTZ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
* @{
*/
/** AIPSTZ - Register Layout Typedef */
typedef struct {
__IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
uint8_t RESERVED_0[60];
__IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
__IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
__IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
__IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
__IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
} AIPSTZ_Type;
/* ----------------------------------------------------------------------------
-- AIPSTZ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
* @{
*/
/*! @name MPR - Master Priviledge Registers */
/*! @{ */
#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
/*! @} */
/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
/*! @} */
/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
/*! @} */
/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
/*! @} */
/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
/*! @} */
/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AIPSTZ_Register_Masks */
/* AIPSTZ - Peripheral instance base addresses */
/** Peripheral AIPSTZ1 base address */
#define AIPSTZ1_BASE (0x4007C000u)
/** Peripheral AIPSTZ1 base pointer */
#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
/** Peripheral AIPSTZ2 base address */
#define AIPSTZ2_BASE (0x4017C000u)
/** Peripheral AIPSTZ2 base pointer */
#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
/** Peripheral AIPSTZ3 base address */
#define AIPSTZ3_BASE (0x4027C000u)
/** Peripheral AIPSTZ3 base pointer */
#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
/** Peripheral AIPSTZ4 base address */
#define AIPSTZ4_BASE (0x4037C000u)
/** Peripheral AIPSTZ4 base pointer */
#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
/** Array initializer of AIPSTZ peripheral base addresses */
#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
/** Array initializer of AIPSTZ peripheral base pointers */
#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
/*!
* @}
*/ /* end of group AIPSTZ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AOI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
* @{
*/
/** AOI - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x4 */
__IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
__IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
} BFCRT[4];
} AOI_Type;
/* ----------------------------------------------------------------------------
-- AOI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AOI_Register_Masks AOI Register Masks
* @{
*/
/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
/*! @{ */
#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
/*! @} */
/* The count of AOI_BFCRT01 */
#define AOI_BFCRT01_COUNT (4U)
/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
/*! @{ */
#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
/*! @} */
/* The count of AOI_BFCRT23 */
#define AOI_BFCRT23_COUNT (4U)
/*!
* @}
*/ /* end of group AOI_Register_Masks */
/* AOI - Peripheral instance base addresses */
/** Peripheral AOI1 base address */
#define AOI1_BASE (0x403B4000u)
/** Peripheral AOI1 base pointer */
#define AOI1 ((AOI_Type *)AOI1_BASE)
/** Peripheral AOI2 base address */
#define AOI2_BASE (0x403B8000u)
/** Peripheral AOI2 base pointer */
#define AOI2 ((AOI_Type *)AOI2_BASE)
/** Array initializer of AOI peripheral base addresses */
#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
/** Array initializer of AOI peripheral base pointers */
#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
/*!
* @}
*/ /* end of group AOI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- BEE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
* @{
*/
/** BEE - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */
__IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */
__IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */
__IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */
__IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */
__IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */
__IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */
__IO uint32_t STATUS; /**< , offset: 0x1C */
__O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */
__O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */
__O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */
__O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */
__O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */
__O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */
__O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */
__O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */
__IO uint32_t REGION1_TOP; /**< , offset: 0x40 */
__IO uint32_t REGION1_BOT; /**< , offset: 0x44 */
} BEE_Type;
/* ----------------------------------------------------------------------------
-- BEE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup BEE_Register_Masks BEE Register Masks
* @{
*/
/*! @name CTRL - BEE Control Register */
/*! @{ */
#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
#define BEE_CTRL_KEY_VALID_MASK (0x10U)
#define BEE_CTRL_KEY_VALID_SHIFT (4U)
#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
/*! @} */
/*! @name ADDR_OFFSET0 - */
/*! @{ */
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
/*! @} */
/*! @name ADDR_OFFSET1 - */
/*! @{ */
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK (0xFFFFU)
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT (0U)
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_MASK)
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT (16U)
#define BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET0_LOCK_MASK)
/*! @} */
/*! @name AES_KEY0_W0 - */
/*! @{ */
#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
/*! @} */
/*! @name AES_KEY0_W1 - */
/*! @{ */
#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
/*! @} */
/*! @name AES_KEY0_W2 - */
/*! @{ */
#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
/*! @} */
/*! @name AES_KEY0_W3 - */
/*! @{ */
#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
/*! @} */
/*! @name STATUS - */
/*! @{ */
#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
/*! @} */
/*! @name CTR_NONCE0_W0 - */
/*! @{ */
#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
/*! @} */
/*! @name CTR_NONCE0_W1 - */
/*! @{ */
#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
/*! @} */
/*! @name CTR_NONCE0_W2 - */
/*! @{ */
#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
/*! @} */
/*! @name CTR_NONCE0_W3 - */
/*! @{ */
#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
/*! @} */
/*! @name CTR_NONCE1_W0 - */
/*! @{ */
#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
/*! @} */
/*! @name CTR_NONCE1_W1 - */
/*! @{ */
#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
/*! @} */
/*! @name CTR_NONCE1_W2 - */
/*! @{ */
#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
/*! @} */
/*! @name CTR_NONCE1_W3 - */
/*! @{ */
#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
/*! @} */
/*! @name REGION1_TOP - */
/*! @{ */
#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
/*! @} */
/*! @name REGION1_BOT - */
/*! @{ */
#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group BEE_Register_Masks */
/* BEE - Peripheral instance base addresses */
/** Peripheral BEE base address */
#define BEE_BASE (0x403EC000u)
/** Peripheral BEE base pointer */
#define BEE ((BEE_Type *)BEE_BASE)
/** Array initializer of BEE peripheral base addresses */
#define BEE_BASE_ADDRS { BEE_BASE }
/** Array initializer of BEE peripheral base pointers */
#define BEE_BASE_PTRS { BEE }
/*!
* @}
*/ /* end of group BEE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
__IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
__IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
__IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
uint8_t RESERVED_1[8];
__I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
uint8_t RESERVED_2[48];
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[64];
uint8_t RESERVED_3[1024];
__IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
uint8_t RESERVED_4[96];
__IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
} CAN_Type;
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/*! @name MCR - Module Configuration Register */
/*! @{ */
#define CAN_MCR_MAXMB_MASK (0x7FU)
#define CAN_MCR_MAXMB_SHIFT (0U)
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK (0x300U)
#define CAN_MCR_IDAM_SHIFT (8U)
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK (0x1000U)
#define CAN_MCR_AEN_SHIFT (12U)
#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
#define CAN_MCR_LPRIOEN_MASK (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT (13U)
#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
#define CAN_MCR_IRMQ_MASK (0x10000U)
#define CAN_MCR_IRMQ_SHIFT (16U)
#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
#define CAN_MCR_SRXDIS_MASK (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT (17U)
#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
#define CAN_MCR_WAKSRC_MASK (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT (19U)
#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
#define CAN_MCR_LPMACK_MASK (0x100000U)
#define CAN_MCR_LPMACK_SHIFT (20U)
#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
#define CAN_MCR_WRNEN_MASK (0x200000U)
#define CAN_MCR_WRNEN_SHIFT (21U)
#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
#define CAN_MCR_SLFWAK_MASK (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT (22U)
#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
#define CAN_MCR_SUPV_MASK (0x800000U)
#define CAN_MCR_SUPV_SHIFT (23U)
#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
#define CAN_MCR_FRZACK_MASK (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT (24U)
#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
#define CAN_MCR_SOFTRST_MASK (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT (25U)
#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
#define CAN_MCR_WAKMSK_MASK (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT (26U)
#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
#define CAN_MCR_NOTRDY_MASK (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT (27U)
#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
#define CAN_MCR_HALT_MASK (0x10000000U)
#define CAN_MCR_HALT_SHIFT (28U)
#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
#define CAN_MCR_RFEN_MASK (0x20000000U)
#define CAN_MCR_RFEN_SHIFT (29U)
#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
#define CAN_MCR_FRZ_MASK (0x40000000U)
#define CAN_MCR_FRZ_SHIFT (30U)
#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
#define CAN_MCR_MDIS_MASK (0x80000000U)
#define CAN_MCR_MDIS_SHIFT (31U)
#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */
/*! @name CTRL1 - Control 1 Register */
/*! @{ */
#define CAN_CTRL1_PROPSEG_MASK (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT (0U)
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK (0x8U)
#define CAN_CTRL1_LOM_SHIFT (3U)
#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
#define CAN_CTRL1_LBUF_MASK (0x10U)
#define CAN_CTRL1_LBUF_SHIFT (4U)
#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
#define CAN_CTRL1_TSYN_MASK (0x20U)
#define CAN_CTRL1_TSYN_SHIFT (5U)
#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
#define CAN_CTRL1_BOFFREC_MASK (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT (6U)
#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
#define CAN_CTRL1_SMP_MASK (0x80U)
#define CAN_CTRL1_SMP_SHIFT (7U)
#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
#define CAN_CTRL1_LPB_MASK (0x1000U)
#define CAN_CTRL1_LPB_SHIFT (12U)
#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT (14U)
#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
#define CAN_CTRL1_PSEG2_MASK (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT (16U)
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT (19U)
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT (22U)
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT (24U)
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */
/*! @name TIMER - Free Running Timer Register */
/*! @{ */
#define CAN_TIMER_TIMER_MASK (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT (0U)
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */
/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
/*! @{ */
#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT (0U)
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */
/*! @name RX14MASK - Rx Buffer 14 Mask Register */
/*! @{ */
#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT (0U)
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */
/*! @name RX15MASK - Rx Buffer 15 Mask Register */
/*! @{ */
#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT (0U)
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */
/*! @name ECR - Error Counter Register */
/*! @{ */
#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
/*! @} */
/*! @name ESR1 - Error and Status 1 Register */
/*! @{ */
#define CAN_ESR1_WAKINT_MASK (0x1U)
#define CAN_ESR1_WAKINT_SHIFT (0U)
#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
#define CAN_ESR1_ERRINT_MASK (0x2U)
#define CAN_ESR1_ERRINT_SHIFT (1U)
#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
#define CAN_ESR1_BOFFINT_MASK (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT (2U)
#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
#define CAN_ESR1_RX_MASK (0x8U)
#define CAN_ESR1_RX_SHIFT (3U)
#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
#define CAN_ESR1_FLTCONF_MASK (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT (4U)
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK (0x40U)
#define CAN_ESR1_TX_SHIFT (6U)
#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
#define CAN_ESR1_IDLE_MASK (0x80U)
#define CAN_ESR1_IDLE_SHIFT (7U)
#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
#define CAN_ESR1_RXWRN_MASK (0x100U)
#define CAN_ESR1_RXWRN_SHIFT (8U)
#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
#define CAN_ESR1_TXWRN_MASK (0x200U)
#define CAN_ESR1_TXWRN_SHIFT (9U)
#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
#define CAN_ESR1_STFERR_MASK (0x400U)
#define CAN_ESR1_STFERR_SHIFT (10U)
#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
#define CAN_ESR1_FRMERR_MASK (0x800U)
#define CAN_ESR1_FRMERR_SHIFT (11U)
#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
#define CAN_ESR1_CRCERR_MASK (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT (12U)
#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
#define CAN_ESR1_ACKERR_MASK (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT (13U)
#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT (14U)
#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT (15U)
#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
#define CAN_ESR1_RWRNINT_MASK (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT (16U)
#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
#define CAN_ESR1_TWRNINT_MASK (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT (17U)
#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
#define CAN_ESR1_SYNCH_MASK (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT (18U)
#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
/*! @} */
/*! @name IMASK2 - Interrupt Masks 2 Register */
/*! @{ */
#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
#define CAN_IMASK2_BUFHM_SHIFT (0U)
#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
/*! @} */
/*! @name IMASK1 - Interrupt Masks 1 Register */
/*! @{ */
#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
#define CAN_IMASK1_BUFLM_SHIFT (0U)
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
/*! @} */
/*! @name IFLAG2 - Interrupt Flags 2 Register */
/*! @{ */
#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
#define CAN_IFLAG2_BUFHI_SHIFT (0U)
#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
/*! @} */
/*! @name IFLAG1 - Interrupt Flags 1 Register */
/*! @{ */
#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT (5U)
#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
#define CAN_IFLAG1_BUF6I_MASK (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT (6U)
#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
#define CAN_IFLAG1_BUF7I_MASK (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT (7U)
#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */
/*! @name CTRL2 - Control 2 Register */
/*! @{ */
#define CAN_CTRL2_EACEN_MASK (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT (16U)
#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
#define CAN_CTRL2_RRS_MASK (0x20000U)
#define CAN_CTRL2_RRS_SHIFT (17U)
#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
#define CAN_CTRL2_MRP_MASK (0x40000U)
#define CAN_CTRL2_MRP_SHIFT (18U)
#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
#define CAN_CTRL2_TASD_MASK (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT (19U)
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT (24U)
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
/*! @} */
/*! @name ESR2 - Error and Status 2 Register */
/*! @{ */
#define CAN_ESR2_IMB_MASK (0x2000U)
#define CAN_ESR2_IMB_SHIFT (13U)
#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
#define CAN_ESR2_VPS_MASK (0x4000U)
#define CAN_ESR2_VPS_SHIFT (14U)
#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
#define CAN_ESR2_LPTM_MASK (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT (16U)
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */
/*! @name CRCR - CRC Register */
/*! @{ */
#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT (0U)
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT (16U)
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */
/*! @name RXFGMASK - Rx FIFO Global Mask Register */
/*! @{ */
#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT (0U)
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */
/*! @name RXFIR - Rx FIFO Information Register */
/*! @{ */
#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT (0U)
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */
/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
/*! @{ */
#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT (0U)
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK (0xF0000U)
#define CAN_CS_DLC_SHIFT (16U)
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK (0x100000U)
#define CAN_CS_RTR_SHIFT (20U)
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK (0x200000U)
#define CAN_CS_IDE_SHIFT (21U)
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK (0x400000U)
#define CAN_CS_SRR_SHIFT (22U)
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK (0xF000000U)
#define CAN_CS_CODE_SHIFT (24U)
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
/*! @} */
/* The count of CAN_CS */
#define CAN_CS_COUNT (64U)
/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
/*! @{ */
#define CAN_ID_EXT_MASK (0x3FFFFU)
#define CAN_ID_EXT_SHIFT (0U)
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK (0x1FFC0000U)
#define CAN_ID_STD_SHIFT (18U)
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK (0xE0000000U)
#define CAN_ID_PRIO_SHIFT (29U)
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */
/* The count of CAN_ID */
#define CAN_ID_COUNT (64U)
/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
/*! @{ */
#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */
/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT (64U)
/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
/*! @{ */
#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */
/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT (64U)
/*! @name RXIMR - Rx Individual Mask Registers */
/*! @{ */
#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT (0U)
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */
/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT (64U)
/*! @name GFWR - Glitch Filter Width Registers */
/*! @{ */
#define CAN_GFWR_GFWR_MASK (0xFFU)
#define CAN_GFWR_GFWR_SHIFT (0U)
#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN1 base address */
#define CAN1_BASE (0x401D0000u)
/** Peripheral CAN1 base pointer */
#define CAN1 ((CAN_Type *)CAN1_BASE)
/** Peripheral CAN2 base address */
#define CAN2_BASE (0x401D4000u)
/** Peripheral CAN2 base pointer */
#define CAN2 ((CAN_Type *)CAN2_BASE)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
/* Backward compatibility */
#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
* @{
*/
/** CCM - Register Layout Typedef */
typedef struct {
__IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
uint8_t RESERVED_0[4];
__I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
__IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
__IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
__IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
__IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
__IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
__IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
__IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
__IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
__IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
__IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
uint8_t RESERVED_1[4];
__IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
__IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
uint8_t RESERVED_2[8];
__I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
uint8_t RESERVED_3[8];
__IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
__IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
__IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
__IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
__IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
__IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
__IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
__IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
__IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
__IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
__IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
__IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
uint8_t RESERVED_4[4];
__IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
} CCM_Type;
/* ----------------------------------------------------------------------------
-- CCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Register_Masks CCM Register Masks
* @{
*/
/*! @name CCR - CCM Control Register */
/*! @{ */
#define CCM_CCR_OSCNT_MASK (0xFFU)
#define CCM_CCR_OSCNT_SHIFT (0U)
#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
#define CCM_CCR_COSC_EN_MASK (0x1000U)
#define CCM_CCR_COSC_EN_SHIFT (12U)
#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
#define CCM_CCR_RBC_EN_MASK (0x8000000U)
#define CCM_CCR_RBC_EN_SHIFT (27U)
#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
/*! @} */
/*! @name CSR - CCM Status Register */
/*! @{ */
#define CCM_CSR_REF_EN_B_MASK (0x1U)
#define CCM_CSR_REF_EN_B_SHIFT (0U)
#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
#define CCM_CSR_CAMP2_READY_MASK (0x8U)
#define CCM_CSR_CAMP2_READY_SHIFT (3U)
#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
#define CCM_CSR_COSC_READY_MASK (0x20U)
#define CCM_CSR_COSC_READY_SHIFT (5U)
#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
/*! @} */
/*! @name CCSR - CCM Clock Switcher Register */
/*! @{ */
#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
/*! @} */
/*! @name CACRR - CCM Arm Clock Root Register */
/*! @{ */
#define CCM_CACRR_ARM_PODF_MASK (0x7U)
#define CCM_CACRR_ARM_PODF_SHIFT (0U)
#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
/*! @} */
/*! @name CBCDR - CCM Bus Clock Divider Register */
/*! @{ */
#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
/*! @} */
/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
/*! @{ */
#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
/*! @} */
/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
/*! @{ */
#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
/*! @} */
/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
/*! @{ */
#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
/*! @} */
/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
/*! @{ */
#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
/*! @} */
/*! @name CS1CDR - CCM Clock Divider Register */
/*! @{ */
#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
/*! @} */
/*! @name CS2CDR - CCM Clock Divider Register */
/*! @{ */
#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
/*! @} */
/*! @name CDCDR - CCM D1 Clock Divider Register */
/*! @{ */
#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
/*! @} */
/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
/*! @{ */
#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
/*! @} */
/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */
/*! @{ */
#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
/*! @} */
/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
/*! @{ */
#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
/*! @} */
/*! @name CLPCR - CCM Low Power Control Register */
/*! @{ */
#define CCM_CLPCR_LPM_MASK (0x3U)
#define CCM_CLPCR_LPM_SHIFT (0U)
#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
#define CCM_CLPCR_SBYOS_MASK (0x40U)
#define CCM_CLPCR_SBYOS_SHIFT (6U)
#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
#define CCM_CLPCR_VSTBY_MASK (0x100U)
#define CCM_CLPCR_VSTBY_SHIFT (8U)
#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
/*! @} */
/*! @name CISR - CCM Interrupt Status Register */
/*! @{ */
#define CCM_CISR_LRF_PLL_MASK (0x1U)
#define CCM_CISR_LRF_PLL_SHIFT (0U)
#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
#define CCM_CISR_COSC_READY_MASK (0x40U)
#define CCM_CISR_COSC_READY_SHIFT (6U)
#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
/*! @} */
/*! @name CIMR - CCM Interrupt Mask Register */
/*! @{ */
#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
/*! @} */
/*! @name CCOSR - CCM Clock Output Source Register */
/*! @{ */
#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
/*! @} */
/*! @name CGPR - CCM General Purpose Register */
/*! @{ */
#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
#define CCM_CGPR_FPL_MASK (0x10000U)
#define CCM_CGPR_FPL_SHIFT (16U)
#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
/*! @} */
/*! @name CCGR0 - CCM Clock Gating Register 0 */
/*! @{ */
#define CCM_CCGR0_CG0_MASK (0x3U)
#define CCM_CCGR0_CG0_SHIFT (0U)
#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
#define CCM_CCGR0_CG1_MASK (0xCU)
#define CCM_CCGR0_CG1_SHIFT (2U)
#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
#define CCM_CCGR0_CG2_MASK (0x30U)
#define CCM_CCGR0_CG2_SHIFT (4U)
#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
#define CCM_CCGR0_CG3_MASK (0xC0U)
#define CCM_CCGR0_CG3_SHIFT (6U)
#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
#define CCM_CCGR0_CG4_MASK (0x300U)
#define CCM_CCGR0_CG4_SHIFT (8U)
#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
#define CCM_CCGR0_CG5_MASK (0xC00U)
#define CCM_CCGR0_CG5_SHIFT (10U)
#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
#define CCM_CCGR0_CG6_MASK (0x3000U)
#define CCM_CCGR0_CG6_SHIFT (12U)
#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
#define CCM_CCGR0_CG7_MASK (0xC000U)
#define CCM_CCGR0_CG7_SHIFT (14U)
#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
#define CCM_CCGR0_CG8_MASK (0x30000U)
#define CCM_CCGR0_CG8_SHIFT (16U)
#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
#define CCM_CCGR0_CG9_MASK (0xC0000U)
#define CCM_CCGR0_CG9_SHIFT (18U)
#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
#define CCM_CCGR0_CG10_MASK (0x300000U)
#define CCM_CCGR0_CG10_SHIFT (20U)
#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
#define CCM_CCGR0_CG11_MASK (0xC00000U)
#define CCM_CCGR0_CG11_SHIFT (22U)
#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
#define CCM_CCGR0_CG12_MASK (0x3000000U)
#define CCM_CCGR0_CG12_SHIFT (24U)
#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
#define CCM_CCGR0_CG13_MASK (0xC000000U)
#define CCM_CCGR0_CG13_SHIFT (26U)
#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
#define CCM_CCGR0_CG14_MASK (0x30000000U)
#define CCM_CCGR0_CG14_SHIFT (28U)
#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
#define CCM_CCGR0_CG15_MASK (0xC0000000U)
#define CCM_CCGR0_CG15_SHIFT (30U)
#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
/*! @} */
/*! @name CCGR1 - CCM Clock Gating Register 1 */
/*! @{ */
#define CCM_CCGR1_CG0_MASK (0x3U)
#define CCM_CCGR1_CG0_SHIFT (0U)
#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
#define CCM_CCGR1_CG1_MASK (0xCU)
#define CCM_CCGR1_CG1_SHIFT (2U)
#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
#define CCM_CCGR1_CG2_MASK (0x30U)
#define CCM_CCGR1_CG2_SHIFT (4U)
#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
#define CCM_CCGR1_CG3_MASK (0xC0U)
#define CCM_CCGR1_CG3_SHIFT (6U)
#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
#define CCM_CCGR1_CG4_MASK (0x300U)
#define CCM_CCGR1_CG4_SHIFT (8U)
#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
#define CCM_CCGR1_CG5_MASK (0xC00U)
#define CCM_CCGR1_CG5_SHIFT (10U)
#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
#define CCM_CCGR1_CG6_MASK (0x3000U)
#define CCM_CCGR1_CG6_SHIFT (12U)
#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
#define CCM_CCGR1_CG7_MASK (0xC000U)
#define CCM_CCGR1_CG7_SHIFT (14U)
#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
#define CCM_CCGR1_CG8_MASK (0x30000U)
#define CCM_CCGR1_CG8_SHIFT (16U)
#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
#define CCM_CCGR1_CG9_MASK (0xC0000U)
#define CCM_CCGR1_CG9_SHIFT (18U)
#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
#define CCM_CCGR1_CG10_MASK (0x300000U)
#define CCM_CCGR1_CG10_SHIFT (20U)
#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
#define CCM_CCGR1_CG11_MASK (0xC00000U)
#define CCM_CCGR1_CG11_SHIFT (22U)
#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
#define CCM_CCGR1_CG12_MASK (0x3000000U)
#define CCM_CCGR1_CG12_SHIFT (24U)
#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
#define CCM_CCGR1_CG13_MASK (0xC000000U)
#define CCM_CCGR1_CG13_SHIFT (26U)
#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
#define CCM_CCGR1_CG14_MASK (0x30000000U)
#define CCM_CCGR1_CG14_SHIFT (28U)
#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
#define CCM_CCGR1_CG15_MASK (0xC0000000U)
#define CCM_CCGR1_CG15_SHIFT (30U)
#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
/*! @} */
/*! @name CCGR2 - CCM Clock Gating Register 2 */
/*! @{ */
#define CCM_CCGR2_CG0_MASK (0x3U)
#define CCM_CCGR2_CG0_SHIFT (0U)
#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
#define CCM_CCGR2_CG1_MASK (0xCU)
#define CCM_CCGR2_CG1_SHIFT (2U)
#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
#define CCM_CCGR2_CG2_MASK (0x30U)
#define CCM_CCGR2_CG2_SHIFT (4U)
#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
#define CCM_CCGR2_CG3_MASK (0xC0U)
#define CCM_CCGR2_CG3_SHIFT (6U)
#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
#define CCM_CCGR2_CG4_MASK (0x300U)
#define CCM_CCGR2_CG4_SHIFT (8U)
#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
#define CCM_CCGR2_CG5_MASK (0xC00U)
#define CCM_CCGR2_CG5_SHIFT (10U)
#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
#define CCM_CCGR2_CG6_MASK (0x3000U)
#define CCM_CCGR2_CG6_SHIFT (12U)
#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
#define CCM_CCGR2_CG7_MASK (0xC000U)
#define CCM_CCGR2_CG7_SHIFT (14U)
#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
#define CCM_CCGR2_CG8_MASK (0x30000U)
#define CCM_CCGR2_CG8_SHIFT (16U)
#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
#define CCM_CCGR2_CG9_MASK (0xC0000U)
#define CCM_CCGR2_CG9_SHIFT (18U)
#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
#define CCM_CCGR2_CG10_MASK (0x300000U)
#define CCM_CCGR2_CG10_SHIFT (20U)
#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
#define CCM_CCGR2_CG11_MASK (0xC00000U)
#define CCM_CCGR2_CG11_SHIFT (22U)
#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
#define CCM_CCGR2_CG12_MASK (0x3000000U)
#define CCM_CCGR2_CG12_SHIFT (24U)
#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
#define CCM_CCGR2_CG13_MASK (0xC000000U)
#define CCM_CCGR2_CG13_SHIFT (26U)
#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
#define CCM_CCGR2_CG14_MASK (0x30000000U)
#define CCM_CCGR2_CG14_SHIFT (28U)
#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
#define CCM_CCGR2_CG15_MASK (0xC0000000U)
#define CCM_CCGR2_CG15_SHIFT (30U)
#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
/*! @} */
/*! @name CCGR3 - CCM Clock Gating Register 3 */
/*! @{ */
#define CCM_CCGR3_CG0_MASK (0x3U)
#define CCM_CCGR3_CG0_SHIFT (0U)
#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
#define CCM_CCGR3_CG1_MASK (0xCU)
#define CCM_CCGR3_CG1_SHIFT (2U)
#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
#define CCM_CCGR3_CG2_MASK (0x30U)
#define CCM_CCGR3_CG2_SHIFT (4U)
#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
#define CCM_CCGR3_CG3_MASK (0xC0U)
#define CCM_CCGR3_CG3_SHIFT (6U)
#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
#define CCM_CCGR3_CG4_MASK (0x300U)
#define CCM_CCGR3_CG4_SHIFT (8U)
#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
#define CCM_CCGR3_CG5_MASK (0xC00U)
#define CCM_CCGR3_CG5_SHIFT (10U)
#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
#define CCM_CCGR3_CG6_MASK (0x3000U)
#define CCM_CCGR3_CG6_SHIFT (12U)
#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
#define CCM_CCGR3_CG7_MASK (0xC000U)
#define CCM_CCGR3_CG7_SHIFT (14U)
#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
#define CCM_CCGR3_CG8_MASK (0x30000U)
#define CCM_CCGR3_CG8_SHIFT (16U)
#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
#define CCM_CCGR3_CG9_MASK (0xC0000U)
#define CCM_CCGR3_CG9_SHIFT (18U)
#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
#define CCM_CCGR3_CG10_MASK (0x300000U)
#define CCM_CCGR3_CG10_SHIFT (20U)
#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
#define CCM_CCGR3_CG11_MASK (0xC00000U)
#define CCM_CCGR3_CG11_SHIFT (22U)
#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
#define CCM_CCGR3_CG12_MASK (0x3000000U)
#define CCM_CCGR3_CG12_SHIFT (24U)
#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
#define CCM_CCGR3_CG13_MASK (0xC000000U)
#define CCM_CCGR3_CG13_SHIFT (26U)
#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
#define CCM_CCGR3_CG14_MASK (0x30000000U)
#define CCM_CCGR3_CG14_SHIFT (28U)
#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
#define CCM_CCGR3_CG15_MASK (0xC0000000U)
#define CCM_CCGR3_CG15_SHIFT (30U)
#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
/*! @} */
/*! @name CCGR4 - CCM Clock Gating Register 4 */
/*! @{ */
#define CCM_CCGR4_CG0_MASK (0x3U)
#define CCM_CCGR4_CG0_SHIFT (0U)
#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
#define CCM_CCGR4_CG1_MASK (0xCU)
#define CCM_CCGR4_CG1_SHIFT (2U)
#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
#define CCM_CCGR4_CG2_MASK (0x30U)
#define CCM_CCGR4_CG2_SHIFT (4U)
#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
#define CCM_CCGR4_CG3_MASK (0xC0U)
#define CCM_CCGR4_CG3_SHIFT (6U)
#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
#define CCM_CCGR4_CG4_MASK (0x300U)
#define CCM_CCGR4_CG4_SHIFT (8U)
#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
#define CCM_CCGR4_CG5_MASK (0xC00U)
#define CCM_CCGR4_CG5_SHIFT (10U)
#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
#define CCM_CCGR4_CG6_MASK (0x3000U)
#define CCM_CCGR4_CG6_SHIFT (12U)
#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
#define CCM_CCGR4_CG7_MASK (0xC000U)
#define CCM_CCGR4_CG7_SHIFT (14U)
#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
#define CCM_CCGR4_CG8_MASK (0x30000U)
#define CCM_CCGR4_CG8_SHIFT (16U)
#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
#define CCM_CCGR4_CG9_MASK (0xC0000U)
#define CCM_CCGR4_CG9_SHIFT (18U)
#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
#define CCM_CCGR4_CG10_MASK (0x300000U)
#define CCM_CCGR4_CG10_SHIFT (20U)
#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
#define CCM_CCGR4_CG11_MASK (0xC00000U)
#define CCM_CCGR4_CG11_SHIFT (22U)
#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
#define CCM_CCGR4_CG12_MASK (0x3000000U)
#define CCM_CCGR4_CG12_SHIFT (24U)
#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
#define CCM_CCGR4_CG13_MASK (0xC000000U)
#define CCM_CCGR4_CG13_SHIFT (26U)
#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
#define CCM_CCGR4_CG14_MASK (0x30000000U)
#define CCM_CCGR4_CG14_SHIFT (28U)
#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
#define CCM_CCGR4_CG15_MASK (0xC0000000U)
#define CCM_CCGR4_CG15_SHIFT (30U)
#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
/*! @} */
/*! @name CCGR5 - CCM Clock Gating Register 5 */
/*! @{ */
#define CCM_CCGR5_CG0_MASK (0x3U)
#define CCM_CCGR5_CG0_SHIFT (0U)
#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
#define CCM_CCGR5_CG1_MASK (0xCU)
#define CCM_CCGR5_CG1_SHIFT (2U)
#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
#define CCM_CCGR5_CG2_MASK (0x30U)
#define CCM_CCGR5_CG2_SHIFT (4U)
#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
#define CCM_CCGR5_CG3_MASK (0xC0U)
#define CCM_CCGR5_CG3_SHIFT (6U)
#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
#define CCM_CCGR5_CG4_MASK (0x300U)
#define CCM_CCGR5_CG4_SHIFT (8U)
#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
#define CCM_CCGR5_CG5_MASK (0xC00U)
#define CCM_CCGR5_CG5_SHIFT (10U)
#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
#define CCM_CCGR5_CG6_MASK (0x3000U)
#define CCM_CCGR5_CG6_SHIFT (12U)
#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
#define CCM_CCGR5_CG7_MASK (0xC000U)
#define CCM_CCGR5_CG7_SHIFT (14U)
#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
#define CCM_CCGR5_CG8_MASK (0x30000U)
#define CCM_CCGR5_CG8_SHIFT (16U)
#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
#define CCM_CCGR5_CG9_MASK (0xC0000U)
#define CCM_CCGR5_CG9_SHIFT (18U)
#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
#define CCM_CCGR5_CG10_MASK (0x300000U)
#define CCM_CCGR5_CG10_SHIFT (20U)
#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
#define CCM_CCGR5_CG11_MASK (0xC00000U)
#define CCM_CCGR5_CG11_SHIFT (22U)
#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
#define CCM_CCGR5_CG12_MASK (0x3000000U)
#define CCM_CCGR5_CG12_SHIFT (24U)
#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
#define CCM_CCGR5_CG13_MASK (0xC000000U)
#define CCM_CCGR5_CG13_SHIFT (26U)
#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
#define CCM_CCGR5_CG14_MASK (0x30000000U)
#define CCM_CCGR5_CG14_SHIFT (28U)
#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
#define CCM_CCGR5_CG15_MASK (0xC0000000U)
#define CCM_CCGR5_CG15_SHIFT (30U)
#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
/*! @} */
/*! @name CCGR6 - CCM Clock Gating Register 6 */
/*! @{ */
#define CCM_CCGR6_CG0_MASK (0x3U)
#define CCM_CCGR6_CG0_SHIFT (0U)
#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
#define CCM_CCGR6_CG1_MASK (0xCU)
#define CCM_CCGR6_CG1_SHIFT (2U)
#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
#define CCM_CCGR6_CG2_MASK (0x30U)
#define CCM_CCGR6_CG2_SHIFT (4U)
#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
#define CCM_CCGR6_CG3_MASK (0xC0U)
#define CCM_CCGR6_CG3_SHIFT (6U)
#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
#define CCM_CCGR6_CG4_MASK (0x300U)
#define CCM_CCGR6_CG4_SHIFT (8U)
#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
#define CCM_CCGR6_CG5_MASK (0xC00U)
#define CCM_CCGR6_CG5_SHIFT (10U)
#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
#define CCM_CCGR6_CG6_MASK (0x3000U)
#define CCM_CCGR6_CG6_SHIFT (12U)
#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
#define CCM_CCGR6_CG7_MASK (0xC000U)
#define CCM_CCGR6_CG7_SHIFT (14U)
#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
#define CCM_CCGR6_CG8_MASK (0x30000U)
#define CCM_CCGR6_CG8_SHIFT (16U)
#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
#define CCM_CCGR6_CG9_MASK (0xC0000U)
#define CCM_CCGR6_CG9_SHIFT (18U)
#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
#define CCM_CCGR6_CG10_MASK (0x300000U)
#define CCM_CCGR6_CG10_SHIFT (20U)
#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
#define CCM_CCGR6_CG11_MASK (0xC00000U)
#define CCM_CCGR6_CG11_SHIFT (22U)
#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
#define CCM_CCGR6_CG12_MASK (0x3000000U)
#define CCM_CCGR6_CG12_SHIFT (24U)
#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
#define CCM_CCGR6_CG13_MASK (0xC000000U)
#define CCM_CCGR6_CG13_SHIFT (26U)
#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
#define CCM_CCGR6_CG14_MASK (0x30000000U)
#define CCM_CCGR6_CG14_SHIFT (28U)
#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
#define CCM_CCGR6_CG15_MASK (0xC0000000U)
#define CCM_CCGR6_CG15_SHIFT (30U)
#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
/*! @} */
/*! @name CMEOR - CCM Module Enable Overide Register */
/*! @{ */
#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CCM_Register_Masks */
/* CCM - Peripheral instance base addresses */
/** Peripheral CCM base address */
#define CCM_BASE (0x400FC000u)
/** Peripheral CCM base pointer */
#define CCM ((CCM_Type *)CCM_BASE)
/** Array initializer of CCM peripheral base addresses */
#define CCM_BASE_ADDRS { CCM_BASE }
/** Array initializer of CCM peripheral base pointers */
#define CCM_BASE_PTRS { CCM }
/** Interrupt vectors for the CCM peripheral type */
#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
/*!
* @}
*/ /* end of group CCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM_ANALOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
* @{
*/
/** CCM_ANALOG - Register Layout Typedef */
typedef struct {
__IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */
__IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */
__IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */
__IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */
__IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
__IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
__IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
__IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
__IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
__IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
__IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
__IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
__IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
__IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
__IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
__IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
__IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
uint8_t RESERVED_1[12];
__IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
uint8_t RESERVED_2[12];
__IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
__IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
__IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
__IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
__IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
uint8_t RESERVED_3[12];
__IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
uint8_t RESERVED_4[12];
__IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */
__IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */
__IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */
__IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */
__IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
uint8_t RESERVED_5[12];
__IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
uint8_t RESERVED_6[28];
__IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
__IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
__IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
__IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
__IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
__IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
__IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
__IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
__IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
__IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
__IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
__IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
uint8_t RESERVED_7[64];
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
__IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
__IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
__IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
__IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
__IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
__IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
__IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
__IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
} CCM_ANALOG_Type;
/* ----------------------------------------------------------------------------
-- CCM_ANALOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
* @{
*/
/*! @name PLL_ARM - Analog ARM PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
/*! @} */
/*! @name PLL_ARM_SET - Analog ARM PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
/*! @} */
/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
/*! @} */
/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_SYS - Analog System PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
/*! @} */
/*! @name PLL_SYS_SET - Analog System PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
/*! @} */
/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
/*! @} */
/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
/*! @} */
/*! @name PLL_AUDIO - Analog Audio PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
/*! @} */
/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
/*! @} */
/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
/*! @} */
/*! @name PLL_VIDEO - Analog Video PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
/*! @} */
/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
/*! @} */
/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
/*! @} */
/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
/*! @{ */
#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
/*! @} */
/*! @name PLL_ENET - Analog ENET PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
/*! @} */
/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
/*! @} */
/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
/*! @} */
/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
/*! @{ */
#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)
#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)
#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
/*! @} */
/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
/*! @{ */
#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
/*! @} */
/*! @name MISC0 - Miscellaneous Register 0 */
/*! @{ */
#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
/*! @} */
/*! @name MISC0_SET - Miscellaneous Register 0 */
/*! @{ */
#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
/*! @} */
/*! @name MISC0_CLR - Miscellaneous Register 0 */
/*! @{ */
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
/*! @} */
/*! @name MISC0_TOG - Miscellaneous Register 0 */
/*! @{ */
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
/*! @} */
/*! @name MISC1 - Miscellaneous Register 1 */
/*! @{ */
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_SET - Miscellaneous Register 1 */
/*! @{ */
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_CLR - Miscellaneous Register 1 */
/*! @{ */
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_TOG - Miscellaneous Register 1 */
/*! @{ */
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC2 - Miscellaneous Register 2 */
/*! @{ */
#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)
#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)
#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)
#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_SET - Miscellaneous Register 2 */
/*! @{ */
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)
#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)
#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_CLR - Miscellaneous Register 2 */
/*! @{ */
#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)
#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)
#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_TOG - Miscellaneous Register 2 */
/*! @{ */
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)
#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)
#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CCM_ANALOG_Register_Masks */
/* CCM_ANALOG - Peripheral instance base addresses */
/** Peripheral CCM_ANALOG base address */
#define CCM_ANALOG_BASE (0x400D8000u)
/** Peripheral CCM_ANALOG base pointer */
#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
/** Array initializer of CCM_ANALOG peripheral base addresses */
#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
/** Array initializer of CCM_ANALOG peripheral base pointers */
#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
/*!
* @}
*/ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
__IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
__IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/*! @name CR0 - CMP Control Register 0 */
/*! @{ */
#define CMP_CR0_HYSTCTR_MASK (0x3U)
#define CMP_CR0_HYSTCTR_SHIFT (0U)
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK (0x70U)
#define CMP_CR0_FILTER_CNT_SHIFT (4U)
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
/*! @} */
/*! @name CR1 - CMP Control Register 1 */
/*! @{ */
#define CMP_CR1_EN_MASK (0x1U)
#define CMP_CR1_EN_SHIFT (0U)
#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define CMP_CR1_OPE_MASK (0x2U)
#define CMP_CR1_OPE_SHIFT (1U)
#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define CMP_CR1_COS_MASK (0x4U)
#define CMP_CR1_COS_SHIFT (2U)
#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define CMP_CR1_INV_MASK (0x8U)
#define CMP_CR1_INV_SHIFT (3U)
#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define CMP_CR1_PMODE_MASK (0x10U)
#define CMP_CR1_PMODE_SHIFT (4U)
#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define CMP_CR1_WE_MASK (0x40U)
#define CMP_CR1_WE_SHIFT (6U)
#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define CMP_CR1_SE_MASK (0x80U)
#define CMP_CR1_SE_SHIFT (7U)
#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
/*! @} */
/*! @name FPR - CMP Filter Period Register */
/*! @{ */
#define CMP_FPR_FILT_PER_MASK (0xFFU)
#define CMP_FPR_FILT_PER_SHIFT (0U)
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
/*! @} */
/*! @name SCR - CMP Status and Control Register */
/*! @{ */
#define CMP_SCR_COUT_MASK (0x1U)
#define CMP_SCR_COUT_SHIFT (0U)
#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define CMP_SCR_CFF_MASK (0x2U)
#define CMP_SCR_CFF_SHIFT (1U)
#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define CMP_SCR_CFR_MASK (0x4U)
#define CMP_SCR_CFR_SHIFT (2U)
#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define CMP_SCR_IEF_MASK (0x8U)
#define CMP_SCR_IEF_SHIFT (3U)
#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define CMP_SCR_IER_MASK (0x10U)
#define CMP_SCR_IER_SHIFT (4U)
#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define CMP_SCR_DMAEN_MASK (0x40U)
#define CMP_SCR_DMAEN_SHIFT (6U)
#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
/*! @} */
/*! @name DACCR - DAC Control Register */
/*! @{ */
#define CMP_DACCR_VOSEL_MASK (0x3FU)
#define CMP_DACCR_VOSEL_SHIFT (0U)
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK (0x40U)
#define CMP_DACCR_VRSEL_SHIFT (6U)
#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define CMP_DACCR_DACEN_MASK (0x80U)
#define CMP_DACCR_DACEN_SHIFT (7U)
#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/*! @} */
/*! @name MUXCR - MUX Control Register */
/*! @{ */
#define CMP_MUXCR_MSEL_MASK (0x7U)
#define CMP_MUXCR_MSEL_SHIFT (0U)
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK (0x38U)
#define CMP_MUXCR_PSEL_SHIFT (3U)
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40094000u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Peripheral CMP2 base address */
#define CMP2_BASE (0x40094008u)
/** Peripheral CMP2 base pointer */
#define CMP2 ((CMP_Type *)CMP2_BASE)
/** Peripheral CMP3 base address */
#define CMP3_BASE (0x40094010u)
/** Peripheral CMP3 base pointer */
#define CMP3 ((CMP_Type *)CMP3_BASE)
/** Peripheral CMP4 base address */
#define CMP4_BASE (0x40094018u)
/** Peripheral CMP4 base pointer */
#define CMP4 ((CMP_Type *)CMP4_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
* @{
*/
/** CSI - Register Layout Typedef */
typedef struct {
__IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */
__IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */
__IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */
__I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
__I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
__IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */
__IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
__IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
__IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
__IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
__IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
__IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
uint8_t RESERVED_1[16];
__IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */
__IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */
} CSI_Type;
/* ----------------------------------------------------------------------------
-- CSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSI_Register_Masks CSI Register Masks
* @{
*/
/*! @name CSICR1 - CSI Control Register 1 */
/*! @{ */
#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
#define CSI_CSICR1_REDGE_MASK (0x2U)
#define CSI_CSICR1_REDGE_SHIFT (1U)
#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
#define CSI_CSICR1_INV_PCLK_MASK (0x4U)
#define CSI_CSICR1_INV_PCLK_SHIFT (2U)
#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
#define CSI_CSICR1_INV_DATA_MASK (0x8U)
#define CSI_CSICR1_INV_DATA_SHIFT (3U)
#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
#define CSI_CSICR1_PACK_DIR_MASK (0x80U)
#define CSI_CSICR1_PACK_DIR_SHIFT (7U)
#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
#define CSI_CSICR1_FCC_MASK (0x100U)
#define CSI_CSICR1_FCC_SHIFT (8U)
#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
#define CSI_CSICR1_CCIR_EN_MASK (0x400U)
#define CSI_CSICR1_CCIR_EN_SHIFT (10U)
#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
#define CSI_CSICR1_SOF_POL_MASK (0x20000U)
#define CSI_CSICR1_SOF_POL_SHIFT (17U)
#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
#define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
/*! @} */
/*! @name CSICR2 - CSI Control Register 2 */
/*! @{ */
#define CSI_CSICR2_HSC_MASK (0xFFU)
#define CSI_CSICR2_HSC_SHIFT (0U)
#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
#define CSI_CSICR2_VSC_MASK (0xFF00U)
#define CSI_CSICR2_VSC_SHIFT (8U)
#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
#define CSI_CSICR2_LVRM_MASK (0x70000U)
#define CSI_CSICR2_LVRM_SHIFT (16U)
#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
#define CSI_CSICR2_BTS_MASK (0x180000U)
#define CSI_CSICR2_BTS_SHIFT (19U)
#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
#define CSI_CSICR2_SCE_MASK (0x800000U)
#define CSI_CSICR2_SCE_SHIFT (23U)
#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
#define CSI_CSICR2_AFS_MASK (0x3000000U)
#define CSI_CSICR2_AFS_SHIFT (24U)
#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
#define CSI_CSICR2_DRM_MASK (0x4000000U)
#define CSI_CSICR2_DRM_SHIFT (26U)
#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
/*! @} */
/*! @name CSICR3 - CSI Control Register 3 */
/*! @{ */
#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
#define CSI_CSICR3_FRMCNT_SHIFT (16U)
#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
/*! @} */
/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
/*! @{ */
#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
#define CSI_CSISTATFIFO_STAT_SHIFT (0U)
#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
/*! @} */
/*! @name CSIRFIFO - CSI RX FIFO Register */
/*! @{ */
#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
/*! @} */
/*! @name CSIRXCNT - CSI RX Count Register */
/*! @{ */
#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
/*! @} */
/*! @name CSISR - CSI Status Register */
/*! @{ */
#define CSI_CSISR_DRDY_MASK (0x1U)
#define CSI_CSISR_DRDY_SHIFT (0U)
#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
#define CSI_CSISR_ECC_INT_MASK (0x2U)
#define CSI_CSISR_ECC_INT_SHIFT (1U)
#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
#define CSI_CSISR_COF_INT_MASK (0x2000U)
#define CSI_CSISR_COF_INT_SHIFT (13U)
#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
#define CSI_CSISR_F1_INT_MASK (0x4000U)
#define CSI_CSISR_F1_INT_SHIFT (14U)
#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
#define CSI_CSISR_F2_INT_MASK (0x8000U)
#define CSI_CSISR_F2_INT_SHIFT (15U)
#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
#define CSI_CSISR_SOF_INT_MASK (0x10000U)
#define CSI_CSISR_SOF_INT_SHIFT (16U)
#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
#define CSI_CSISR_EOF_INT_MASK (0x20000U)
#define CSI_CSISR_EOF_INT_SHIFT (17U)
#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
#define CSI_CSISR_RxFF_INT_MASK (0x40000U)
#define CSI_CSISR_RxFF_INT_SHIFT (18U)
#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
#define CSI_CSISR_STATFF_INT_MASK (0x200000U)
#define CSI_CSISR_STATFF_INT_SHIFT (21U)
#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
#define CSI_CSISR_RF_OR_INT_SHIFT (24U)
#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
#define CSI_CSISR_SF_OR_INT_SHIFT (25U)
#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
/*! @} */
/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
/*! @{ */
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
/*! @} */
/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
/*! @{ */
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
/*! @} */
/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
/*! @{ */
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
/*! @} */
/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
/*! @{ */
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
/*! @} */
/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
/*! @{ */
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
/*! @} */
/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
/*! @{ */
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
/*! @} */
/*! @name CSICR18 - CSI Control Register 18 */
/*! @{ */
#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
/*! @} */
/*! @name CSICR19 - CSI Control Register 19 */
/*! @{ */
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CSI_Register_Masks */
/* CSI - Peripheral instance base addresses */
/** Peripheral CSI base address */
#define CSI_BASE (0x402BC000u)
/** Peripheral CSI base pointer */
#define CSI ((CSI_Type *)CSI_BASE)
/** Array initializer of CSI peripheral base addresses */
#define CSI_BASE_ADDRS { CSI_BASE }
/** Array initializer of CSI peripheral base pointers */
#define CSI_BASE_PTRS { CSI }
/** Interrupt vectors for the CSI peripheral type */
#define CSI_IRQS { CSI_IRQn }
/*!
* @}
*/ /* end of group CSI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CSU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
* @{
*/
/** CSU - Register Layout Typedef */
typedef struct {
__IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */
uint8_t RESERVED_0[384];
__IO uint32_t HP0; /**< HP0 register, offset: 0x200 */
uint8_t RESERVED_1[20];
__IO uint32_t SA; /**< Secure access register, offset: 0x218 */
uint8_t RESERVED_2[316];
__IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */
} CSU_Type;
/* ----------------------------------------------------------------------------
-- CSU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSU_Register_Masks CSU Register Masks
* @{
*/
/*! @name CSL - Config security level register */
/*! @{ */
#define CSU_CSL_SUR_S2_MASK (0x1U)
#define CSU_CSL_SUR_S2_SHIFT (0U)
#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
#define CSU_CSL_SSR_S2_MASK (0x2U)
#define CSU_CSL_SSR_S2_SHIFT (1U)
#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
#define CSU_CSL_NUR_S2_MASK (0x4U)
#define CSU_CSL_NUR_S2_SHIFT (2U)
#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
#define CSU_CSL_NSR_S2_MASK (0x8U)
#define CSU_CSL_NSR_S2_SHIFT (3U)
#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
#define CSU_CSL_SUW_S2_MASK (0x10U)
#define CSU_CSL_SUW_S2_SHIFT (4U)
#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
#define CSU_CSL_SSW_S2_MASK (0x20U)
#define CSU_CSL_SSW_S2_SHIFT (5U)
#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
#define CSU_CSL_NUW_S2_MASK (0x40U)
#define CSU_CSL_NUW_S2_SHIFT (6U)
#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
#define CSU_CSL_NSW_S2_MASK (0x80U)
#define CSU_CSL_NSW_S2_SHIFT (7U)
#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
#define CSU_CSL_LOCK_S2_MASK (0x100U)
#define CSU_CSL_LOCK_S2_SHIFT (8U)
#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
#define CSU_CSL_SUR_S1_MASK (0x10000U)
#define CSU_CSL_SUR_S1_SHIFT (16U)
#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
#define CSU_CSL_SSR_S1_MASK (0x20000U)
#define CSU_CSL_SSR_S1_SHIFT (17U)
#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
#define CSU_CSL_NUR_S1_MASK (0x40000U)
#define CSU_CSL_NUR_S1_SHIFT (18U)
#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
#define CSU_CSL_NSR_S1_MASK (0x80000U)
#define CSU_CSL_NSR_S1_SHIFT (19U)
#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
#define CSU_CSL_SUW_S1_MASK (0x100000U)
#define CSU_CSL_SUW_S1_SHIFT (20U)
#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
#define CSU_CSL_SSW_S1_MASK (0x200000U)
#define CSU_CSL_SSW_S1_SHIFT (21U)
#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
#define CSU_CSL_NUW_S1_MASK (0x400000U)
#define CSU_CSL_NUW_S1_SHIFT (22U)
#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
#define CSU_CSL_NSW_S1_MASK (0x800000U)
#define CSU_CSL_NSW_S1_SHIFT (23U)
#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
#define CSU_CSL_LOCK_S1_SHIFT (24U)
#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
/*! @} */
/* The count of CSU_CSL */
#define CSU_CSL_COUNT (32U)
/*! @name HP0 - HP0 register */
/*! @{ */
#define CSU_HP0_HP_DMA_MASK (0x4U)
#define CSU_HP0_HP_DMA_SHIFT (2U)
#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
#define CSU_HP0_L_DMA_MASK (0x8U)
#define CSU_HP0_L_DMA_SHIFT (3U)
#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
#define CSU_HP0_HP_LCDIF_MASK (0x10U)
#define CSU_HP0_HP_LCDIF_SHIFT (4U)
#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
#define CSU_HP0_L_LCDIF_MASK (0x20U)
#define CSU_HP0_L_LCDIF_SHIFT (5U)
#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
#define CSU_HP0_HP_CSI_MASK (0x40U)
#define CSU_HP0_HP_CSI_SHIFT (6U)
#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
#define CSU_HP0_L_CSI_MASK (0x80U)
#define CSU_HP0_L_CSI_SHIFT (7U)
#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
#define CSU_HP0_HP_PXP_MASK (0x100U)
#define CSU_HP0_HP_PXP_SHIFT (8U)
#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
#define CSU_HP0_L_PXP_MASK (0x200U)
#define CSU_HP0_L_PXP_SHIFT (9U)
#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
#define CSU_HP0_HP_DCP_MASK (0x400U)
#define CSU_HP0_HP_DCP_SHIFT (10U)
#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
#define CSU_HP0_L_DCP_MASK (0x800U)
#define CSU_HP0_L_DCP_SHIFT (11U)
#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
#define CSU_HP0_HP_ENET_MASK (0x4000U)
#define CSU_HP0_HP_ENET_SHIFT (14U)
#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
#define CSU_HP0_L_ENET_MASK (0x8000U)
#define CSU_HP0_L_ENET_SHIFT (15U)
#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
#define CSU_HP0_HP_USDHC1_SHIFT (16U)
#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
#define CSU_HP0_L_USDHC1_MASK (0x20000U)
#define CSU_HP0_L_USDHC1_SHIFT (17U)
#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
#define CSU_HP0_HP_USDHC2_SHIFT (18U)
#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
#define CSU_HP0_L_USDHC2_MASK (0x80000U)
#define CSU_HP0_L_USDHC2_SHIFT (19U)
#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
#define CSU_HP0_HP_TPSMP_SHIFT (20U)
#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
#define CSU_HP0_L_TPSMP_MASK (0x200000U)
#define CSU_HP0_L_TPSMP_SHIFT (21U)
#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
#define CSU_HP0_HP_USB_MASK (0x400000U)
#define CSU_HP0_HP_USB_SHIFT (22U)
#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
#define CSU_HP0_L_USB_MASK (0x800000U)
#define CSU_HP0_L_USB_SHIFT (23U)
#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
/*! @} */
/*! @name SA - Secure access register */
/*! @{ */
#define CSU_SA_NSA_DMA_MASK (0x4U)
#define CSU_SA_NSA_DMA_SHIFT (2U)
#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
#define CSU_SA_L_DMA_MASK (0x8U)
#define CSU_SA_L_DMA_SHIFT (3U)
#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
#define CSU_SA_NSA_LCDIF_MASK (0x10U)
#define CSU_SA_NSA_LCDIF_SHIFT (4U)
#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
#define CSU_SA_L_LCDIF_MASK (0x20U)
#define CSU_SA_L_LCDIF_SHIFT (5U)
#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
#define CSU_SA_NSA_CSI_MASK (0x40U)
#define CSU_SA_NSA_CSI_SHIFT (6U)
#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
#define CSU_SA_L_CSI_MASK (0x80U)
#define CSU_SA_L_CSI_SHIFT (7U)
#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
#define CSU_SA_NSA_PXP_MASK (0x100U)
#define CSU_SA_NSA_PXP_SHIFT (8U)
#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
#define CSU_SA_L_PXP_MASK (0x200U)
#define CSU_SA_L_PXP_SHIFT (9U)
#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
#define CSU_SA_NSA_DCP_MASK (0x400U)
#define CSU_SA_NSA_DCP_SHIFT (10U)
#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
#define CSU_SA_L_DCP_MASK (0x800U)
#define CSU_SA_L_DCP_SHIFT (11U)
#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
#define CSU_SA_NSA_ENET_MASK (0x4000U)
#define CSU_SA_NSA_ENET_SHIFT (14U)
#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
#define CSU_SA_L_ENET_MASK (0x8000U)
#define CSU_SA_L_ENET_SHIFT (15U)
#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
#define CSU_SA_NSA_USDHC1_SHIFT (16U)
#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
#define CSU_SA_L_USDHC1_MASK (0x20000U)
#define CSU_SA_L_USDHC1_SHIFT (17U)
#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
#define CSU_SA_NSA_USDHC2_SHIFT (18U)
#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
#define CSU_SA_L_USDHC2_MASK (0x80000U)
#define CSU_SA_L_USDHC2_SHIFT (19U)
#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
#define CSU_SA_NSA_TPSMP_SHIFT (20U)
#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
#define CSU_SA_L_TPSMP_MASK (0x200000U)
#define CSU_SA_L_TPSMP_SHIFT (21U)
#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
#define CSU_SA_NSA_USB_MASK (0x400000U)
#define CSU_SA_NSA_USB_SHIFT (22U)
#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
#define CSU_SA_L_USB_MASK (0x800000U)
#define CSU_SA_L_USB_SHIFT (23U)
#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
/*! @} */
/*! @name HPCONTROL0 - HPCONTROL0 register */
/*! @{ */
#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
#define CSU_HPCONTROL0_L_USB_SHIFT (23U)
#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CSU_Register_Masks */
/* CSU - Peripheral instance base addresses */
/** Peripheral CSU base address */
#define CSU_BASE (0x400DC000u)
/** Peripheral CSU base pointer */
#define CSU ((CSU_Type *)CSU_BASE)
/** Array initializer of CSU peripheral base addresses */
#define CSU_BASE_ADDRS { CSU_BASE }
/** Array initializer of CSU peripheral base pointers */
#define CSU_BASE_PTRS { CSU }
/*!
* @}
*/ /* end of group CSU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DCDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
* @{
*/
/** DCDC - Register Layout Typedef */
typedef struct {
__IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */
__IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */
__IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */
__IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */
} DCDC_Type;
/* ----------------------------------------------------------------------------
-- DCDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCDC_Register_Masks DCDC Register Masks
* @{
*/
/*! @name REG0 - DCDC Register 0 */
/*! @{ */
#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define DCDC_REG0_SEL_CLK_MASK (0x4U)
#define DCDC_REG0_SEL_CLK_SHIFT (2U)
#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
/*! @} */
/*! @name REG1 - DCDC Register 1 */
/*! @{ */
#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
#define DCDC_REG1_VBG_TRIM_SHIFT (24U)
#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
/*! @} */
/*! @name REG2 - DCDC Register 2 */
/*! @{ */
#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
/*! @} */
/*! @name REG3 - DCDC Register 3 */
/*! @{ */
#define DCDC_REG3_TRG_MASK (0x1FU)
#define DCDC_REG3_TRG_SHIFT (0U)
#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
#define DCDC_REG3_TARGET_LP_MASK (0x700U)
#define DCDC_REG3_TARGET_LP_SHIFT (8U)
#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DCDC_Register_Masks */
/* DCDC - Peripheral instance base addresses */
/** Peripheral DCDC base address */
#define DCDC_BASE (0x40080000u)
/** Peripheral DCDC base pointer */
#define DCDC ((DCDC_Type *)DCDC_BASE)
/** Array initializer of DCDC peripheral base addresses */
#define DCDC_BASE_ADDRS { DCDC_BASE }
/** Array initializer of DCDC peripheral base pointers */
#define DCDC_BASE_PTRS { DCDC }
/** Interrupt vectors for the DCDC peripheral type */
#define DCDC_IRQS { DCDC_IRQn }
/*!
* @}
*/ /* end of group DCDC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DCP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer
* @{
*/
/** DCP - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */
uint8_t RESERVED_0[12];
__IO uint32_t STAT; /**< DCP status register, offset: 0x10 */
uint8_t RESERVED_1[12];
__IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */
uint8_t RESERVED_2[12];
__IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */
uint8_t RESERVED_3[12];
__I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */
uint8_t RESERVED_4[12];
__IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */
uint8_t RESERVED_5[12];
__IO uint32_t KEY; /**< DCP key index, offset: 0x60 */
uint8_t RESERVED_6[12];
__IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */
uint8_t RESERVED_7[12];
__I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */
uint8_t RESERVED_8[12];
__I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */
uint8_t RESERVED_9[12];
__I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */
uint8_t RESERVED_10[12];
__I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */
uint8_t RESERVED_11[12];
__I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */
uint8_t RESERVED_12[12];
__I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */
uint8_t RESERVED_13[12];
__I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */
uint8_t RESERVED_14[28];
__IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */
uint8_t RESERVED_15[12];
__IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */
uint8_t RESERVED_16[12];
__IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */
uint8_t RESERVED_17[12];
__IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */
uint8_t RESERVED_18[12];
__IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */
uint8_t RESERVED_19[12];
__IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */
uint8_t RESERVED_20[12];
__IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */
uint8_t RESERVED_21[12];
__IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */
uint8_t RESERVED_22[12];
__IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */
uint8_t RESERVED_23[12];
__IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */
uint8_t RESERVED_24[12];
__IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */
uint8_t RESERVED_25[12];
__IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */
uint8_t RESERVED_26[12];
__IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */
uint8_t RESERVED_27[12];
__IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */
uint8_t RESERVED_28[12];
__IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */
uint8_t RESERVED_29[12];
__IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */
uint8_t RESERVED_30[524];
__IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */
uint8_t RESERVED_31[12];
__I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */
uint8_t RESERVED_32[12];
__IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */
uint8_t RESERVED_33[12];
__I uint32_t VERSION; /**< DCP version register, offset: 0x430 */
} DCP_Type;
/* ----------------------------------------------------------------------------
-- DCP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCP_Register_Masks DCP Register Masks
* @{
*/
/*! @name CTRL - DCP control register 0 */
/*! @{ */
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
#define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
#define DCP_CTRL_CLKGATE_MASK (0x40000000U)
#define DCP_CTRL_CLKGATE_SHIFT (30U)
#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
#define DCP_CTRL_SFTRST_MASK (0x80000000U)
#define DCP_CTRL_SFTRST_SHIFT (31U)
#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
/*! @} */
/*! @name STAT - DCP status register */
/*! @{ */
#define DCP_STAT_IRQ_MASK (0xFU)
#define DCP_STAT_IRQ_SHIFT (0U)
#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
#define DCP_STAT_RSVD_IRQ_MASK (0x100U)
#define DCP_STAT_RSVD_IRQ_SHIFT (8U)
#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
#define DCP_STAT_READY_CHANNELS_SHIFT (16U)
#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
#define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
#define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
/*! @} */
/*! @name CHANNELCTRL - DCP channel control register */
/*! @{ */
#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
#define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
/*! @} */
/*! @name CAPABILITY0 - DCP capability 0 register */
/*! @{ */
#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
#define DCP_CAPABILITY0_RSVD_SHIFT (12U)
#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
/*! @} */
/*! @name CAPABILITY1 - DCP capability 1 register */
/*! @{ */
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
/*! @} */
/*! @name CONTEXT - DCP context buffer pointer */
/*! @{ */
#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
#define DCP_CONTEXT_ADDR_SHIFT (0U)
#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
/*! @} */
/*! @name KEY - DCP key index */
/*! @{ */
#define DCP_KEY_SUBWORD_MASK (0x3U)
#define DCP_KEY_SUBWORD_SHIFT (0U)
#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
#define DCP_KEY_INDEX_MASK (0x30U)
#define DCP_KEY_INDEX_SHIFT (4U)
#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
#define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
#define DCP_KEY_RSVD_INDEX_SHIFT (6U)
#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
#define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
#define DCP_KEY_RSVD_SHIFT (8U)
#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
/*! @} */
/*! @name KEYDATA - DCP key data */
/*! @{ */
#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
#define DCP_KEYDATA_DATA_SHIFT (0U)
#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
/*! @} */
/*! @name PACKET0 - DCP work packet 0 status register */
/*! @{ */
#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
#define DCP_PACKET0_ADDR_SHIFT (0U)
#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
/*! @} */
/*! @name PACKET1 - DCP work packet 1 status register */
/*! @{ */
#define DCP_PACKET1_INTERRUPT_MASK (0x1U)
#define DCP_PACKET1_INTERRUPT_SHIFT (0U)
#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
#define DCP_PACKET1_CHAIN_MASK (0x4U)
#define DCP_PACKET1_CHAIN_SHIFT (2U)
#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
#define DCP_PACKET1_OTP_KEY_MASK (0x400U)
#define DCP_PACKET1_OTP_KEY_SHIFT (10U)
#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
#define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
#define DCP_PACKET1_HASH_INIT_SHIFT (12U)
#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
#define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
#define DCP_PACKET1_HASH_TERM_SHIFT (13U)
#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
#define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
#define DCP_PACKET1_TAG_MASK (0xFF000000U)
#define DCP_PACKET1_TAG_SHIFT (24U)
#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
/*! @} */
/*! @name PACKET2 - DCP work packet 2 status register */
/*! @{ */
#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
#define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
#define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
#define DCP_PACKET2_RSVD_MASK (0xF00000U)
#define DCP_PACKET2_RSVD_SHIFT (20U)
#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
/*! @} */
/*! @name PACKET3 - DCP work packet 3 status register */
/*! @{ */
#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
#define DCP_PACKET3_ADDR_SHIFT (0U)
#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
/*! @} */
/*! @name PACKET4 - DCP work packet 4 status register */
/*! @{ */
#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
#define DCP_PACKET4_ADDR_SHIFT (0U)
#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
/*! @} */
/*! @name PACKET5 - DCP work packet 5 status register */
/*! @{ */
#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
#define DCP_PACKET5_COUNT_SHIFT (0U)
#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
/*! @} */
/*! @name PACKET6 - DCP work packet 6 status register */
/*! @{ */
#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
#define DCP_PACKET6_ADDR_SHIFT (0U)
#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
/*! @} */
/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */
/*! @{ */
#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
/*! @} */
/*! @name CH0SEMA - DCP channel 0 semaphore register */
/*! @{ */
#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
#define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
#define DCP_CH0SEMA_VALUE_SHIFT (16U)
#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
/*! @} */
/*! @name CH0STAT - DCP channel 0 status register */
/*! @{ */
#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
#define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
#define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
#define DCP_CH0STAT_TAG_MASK (0xFF000000U)
#define DCP_CH0STAT_TAG_SHIFT (24U)
#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
/*! @} */
/*! @name CH0OPTS - DCP channel 0 options register */
/*! @{ */
#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
#define DCP_CH0OPTS_RSVD_SHIFT (16U)
#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
/*! @} */
/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */
/*! @{ */
#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
/*! @} */
/*! @name CH1SEMA - DCP channel 1 semaphore register */
/*! @{ */
#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
#define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
#define DCP_CH1SEMA_VALUE_SHIFT (16U)
#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
/*! @} */
/*! @name CH1STAT - DCP channel 1 status register */
/*! @{ */
#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
#define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
#define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
#define DCP_CH1STAT_TAG_MASK (0xFF000000U)
#define DCP_CH1STAT_TAG_SHIFT (24U)
#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
/*! @} */
/*! @name CH1OPTS - DCP channel 1 options register */
/*! @{ */
#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
#define DCP_CH1OPTS_RSVD_SHIFT (16U)
#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
/*! @} */
/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */
/*! @{ */
#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
/*! @} */
/*! @name CH2SEMA - DCP channel 2 semaphore register */
/*! @{ */
#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
#define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
#define DCP_CH2SEMA_VALUE_SHIFT (16U)
#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
/*! @} */
/*! @name CH2STAT - DCP channel 2 status register */
/*! @{ */
#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
#define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
#define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
#define DCP_CH2STAT_TAG_MASK (0xFF000000U)
#define DCP_CH2STAT_TAG_SHIFT (24U)
#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
/*! @} */
/*! @name CH2OPTS - DCP channel 2 options register */
/*! @{ */
#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
#define DCP_CH2OPTS_RSVD_SHIFT (16U)
#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
/*! @} */
/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */
/*! @{ */
#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
#define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
/*! @} */
/*! @name CH3SEMA - DCP channel 3 semaphore register */
/*! @{ */
#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
#define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
#define DCP_CH3SEMA_VALUE_SHIFT (16U)
#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
/*! @} */
/*! @name CH3STAT - DCP channel 3 status register */
/*! @{ */
#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
#define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
#define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
#define DCP_CH3STAT_TAG_MASK (0xFF000000U)
#define DCP_CH3STAT_TAG_SHIFT (24U)
#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
/*! @} */
/*! @name CH3OPTS - DCP channel 3 options register */
/*! @{ */
#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
#define DCP_CH3OPTS_RSVD_SHIFT (16U)
#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
/*! @} */
/*! @name DBGSELECT - DCP debug select register */
/*! @{ */
#define DCP_DBGSELECT_INDEX_MASK (0xFFU)
#define DCP_DBGSELECT_INDEX_SHIFT (0U)
#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
#define DCP_DBGSELECT_RSVD_SHIFT (8U)
#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
/*! @} */
/*! @name DBGDATA - DCP debug data register */
/*! @{ */
#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
#define DCP_DBGDATA_DATA_SHIFT (0U)
#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
/*! @} */
/*! @name PAGETABLE - DCP page table register */
/*! @{ */
#define DCP_PAGETABLE_ENABLE_MASK (0x1U)
#define DCP_PAGETABLE_ENABLE_SHIFT (0U)
#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
#define DCP_PAGETABLE_FLUSH_MASK (0x2U)
#define DCP_PAGETABLE_FLUSH_SHIFT (1U)
#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
#define DCP_PAGETABLE_BASE_SHIFT (2U)
#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
/*! @} */
/*! @name VERSION - DCP version register */
/*! @{ */
#define DCP_VERSION_STEP_MASK (0xFFFFU)
#define DCP_VERSION_STEP_SHIFT (0U)
#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
#define DCP_VERSION_MINOR_MASK (0xFF0000U)
#define DCP_VERSION_MINOR_SHIFT (16U)
#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
#define DCP_VERSION_MAJOR_MASK (0xFF000000U)
#define DCP_VERSION_MAJOR_SHIFT (24U)
#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DCP_Register_Masks */
/* DCP - Peripheral instance base addresses */
/** Peripheral DCP base address */
#define DCP_BASE (0x402FC000u)
/** Peripheral DCP base pointer */
#define DCP ((DCP_Type *)DCP_BASE)
/** Array initializer of DCP peripheral base addresses */
#define DCP_BASE_ADDRS { DCP_BASE }
/** Array initializer of DCP peripheral base pointers */
#define DCP_BASE_PTRS { DCP }
/** Interrupt vectors for the DCP peripheral type */
#define DCP_IRQS { DCP_IRQn }
#define DCP_VMI_IRQS { DCP_VMI_IRQn }
/*!
* @}
*/ /* end of group DCP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control Register, offset: 0x0 */
__I uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
__I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
__IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
__IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
__IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
__IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
__IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
__IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
__IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
__IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
__IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
__IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
__IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
__IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
__IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
__IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
__IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
__IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
__IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
__IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
__IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
__IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
__IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
__IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
__IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
__IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
uint8_t RESERVED_7[3808];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[32];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/*! @name CR - Control Register */
/*! @{ */
#define DMA_CR_EDBG_MASK (0x2U)
#define DMA_CR_EDBG_SHIFT (1U)
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
#define DMA_CR_ERCA_MASK (0x4U)
#define DMA_CR_ERCA_SHIFT (2U)
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
#define DMA_CR_ERGA_MASK (0x8U)
#define DMA_CR_ERGA_SHIFT (3U)
#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
#define DMA_CR_HOE_MASK (0x10U)
#define DMA_CR_HOE_SHIFT (4U)
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
#define DMA_CR_HALT_MASK (0x20U)
#define DMA_CR_HALT_SHIFT (5U)
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
#define DMA_CR_CLM_MASK (0x40U)
#define DMA_CR_CLM_SHIFT (6U)
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
#define DMA_CR_EMLM_MASK (0x80U)
#define DMA_CR_EMLM_SHIFT (7U)
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
#define DMA_CR_GRP0PRI_MASK (0x100U)
#define DMA_CR_GRP0PRI_SHIFT (8U)
#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
#define DMA_CR_GRP1PRI_MASK (0x400U)
#define DMA_CR_GRP1PRI_SHIFT (10U)
#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
#define DMA_CR_ECX_MASK (0x10000U)
#define DMA_CR_ECX_SHIFT (16U)
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
#define DMA_CR_CX_MASK (0x20000U)
#define DMA_CR_CX_SHIFT (17U)
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
#define DMA_CR_ACTIVE_MASK (0x80000000U)
#define DMA_CR_ACTIVE_SHIFT (31U)
#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
/*! @} */
/*! @name ES - Error Status Register */
/*! @{ */
#define DMA_ES_DBE_MASK (0x1U)
#define DMA_ES_DBE_SHIFT (0U)
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
#define DMA_ES_SBE_MASK (0x2U)
#define DMA_ES_SBE_SHIFT (1U)
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
#define DMA_ES_SGE_MASK (0x4U)
#define DMA_ES_SGE_SHIFT (2U)
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
#define DMA_ES_NCE_MASK (0x8U)
#define DMA_ES_NCE_SHIFT (3U)
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
#define DMA_ES_DOE_MASK (0x10U)
#define DMA_ES_DOE_SHIFT (4U)
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
#define DMA_ES_DAE_MASK (0x20U)
#define DMA_ES_DAE_SHIFT (5U)
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
#define DMA_ES_SOE_MASK (0x40U)
#define DMA_ES_SOE_SHIFT (6U)
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
#define DMA_ES_SAE_MASK (0x80U)
#define DMA_ES_SAE_SHIFT (7U)
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
#define DMA_ES_ERRCHN_MASK (0x1F00U)
#define DMA_ES_ERRCHN_SHIFT (8U)
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK (0x4000U)
#define DMA_ES_CPE_SHIFT (14U)
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
#define DMA_ES_GPE_MASK (0x8000U)
#define DMA_ES_GPE_SHIFT (15U)
#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
#define DMA_ES_ECX_MASK (0x10000U)
#define DMA_ES_ECX_SHIFT (16U)
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
#define DMA_ES_VLD_MASK (0x80000000U)
#define DMA_ES_VLD_SHIFT (31U)
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
/*! @} */
/*! @name ERQ - Enable Request Register */
/*! @{ */
#define DMA_ERQ_ERQ0_MASK (0x1U)
#define DMA_ERQ_ERQ0_SHIFT (0U)
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
#define DMA_ERQ_ERQ1_MASK (0x2U)
#define DMA_ERQ_ERQ1_SHIFT (1U)
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
#define DMA_ERQ_ERQ2_MASK (0x4U)
#define DMA_ERQ_ERQ2_SHIFT (2U)
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
#define DMA_ERQ_ERQ3_MASK (0x8U)
#define DMA_ERQ_ERQ3_SHIFT (3U)
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
#define DMA_ERQ_ERQ4_MASK (0x10U)
#define DMA_ERQ_ERQ4_SHIFT (4U)
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
#define DMA_ERQ_ERQ5_MASK (0x20U)
#define DMA_ERQ_ERQ5_SHIFT (5U)
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
#define DMA_ERQ_ERQ6_MASK (0x40U)
#define DMA_ERQ_ERQ6_SHIFT (6U)
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
#define DMA_ERQ_ERQ7_MASK (0x80U)
#define DMA_ERQ_ERQ7_SHIFT (7U)
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
#define DMA_ERQ_ERQ8_MASK (0x100U)
#define DMA_ERQ_ERQ8_SHIFT (8U)
#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
#define DMA_ERQ_ERQ9_MASK (0x200U)
#define DMA_ERQ_ERQ9_SHIFT (9U)
#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
#define DMA_ERQ_ERQ10_MASK (0x400U)
#define DMA_ERQ_ERQ10_SHIFT (10U)
#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
#define DMA_ERQ_ERQ11_MASK (0x800U)
#define DMA_ERQ_ERQ11_SHIFT (11U)
#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
#define DMA_ERQ_ERQ12_MASK (0x1000U)
#define DMA_ERQ_ERQ12_SHIFT (12U)
#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
#define DMA_ERQ_ERQ13_MASK (0x2000U)
#define DMA_ERQ_ERQ13_SHIFT (13U)
#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
#define DMA_ERQ_ERQ14_MASK (0x4000U)
#define DMA_ERQ_ERQ14_SHIFT (14U)
#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
#define DMA_ERQ_ERQ15_MASK (0x8000U)
#define DMA_ERQ_ERQ15_SHIFT (15U)
#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
#define DMA_ERQ_ERQ16_MASK (0x10000U)
#define DMA_ERQ_ERQ16_SHIFT (16U)
#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
#define DMA_ERQ_ERQ17_MASK (0x20000U)
#define DMA_ERQ_ERQ17_SHIFT (17U)
#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
#define DMA_ERQ_ERQ18_MASK (0x40000U)
#define DMA_ERQ_ERQ18_SHIFT (18U)
#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
#define DMA_ERQ_ERQ19_MASK (0x80000U)
#define DMA_ERQ_ERQ19_SHIFT (19U)
#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
#define DMA_ERQ_ERQ20_MASK (0x100000U)
#define DMA_ERQ_ERQ20_SHIFT (20U)
#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
#define DMA_ERQ_ERQ21_MASK (0x200000U)
#define DMA_ERQ_ERQ21_SHIFT (21U)
#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
#define DMA_ERQ_ERQ22_MASK (0x400000U)
#define DMA_ERQ_ERQ22_SHIFT (22U)
#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
#define DMA_ERQ_ERQ23_MASK (0x800000U)
#define DMA_ERQ_ERQ23_SHIFT (23U)
#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
#define DMA_ERQ_ERQ24_MASK (0x1000000U)
#define DMA_ERQ_ERQ24_SHIFT (24U)
#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
#define DMA_ERQ_ERQ25_MASK (0x2000000U)
#define DMA_ERQ_ERQ25_SHIFT (25U)
#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
#define DMA_ERQ_ERQ26_MASK (0x4000000U)
#define DMA_ERQ_ERQ26_SHIFT (26U)
#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
#define DMA_ERQ_ERQ27_MASK (0x8000000U)
#define DMA_ERQ_ERQ27_SHIFT (27U)
#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
#define DMA_ERQ_ERQ28_MASK (0x10000000U)
#define DMA_ERQ_ERQ28_SHIFT (28U)
#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
#define DMA_ERQ_ERQ29_MASK (0x20000000U)
#define DMA_ERQ_ERQ29_SHIFT (29U)
#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
#define DMA_ERQ_ERQ30_MASK (0x40000000U)
#define DMA_ERQ_ERQ30_SHIFT (30U)
#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
#define DMA_ERQ_ERQ31_MASK (0x80000000U)
#define DMA_ERQ_ERQ31_SHIFT (31U)
#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
/*! @} */
/*! @name EEI - Enable Error Interrupt Register */
/*! @{ */
#define DMA_EEI_EEI0_MASK (0x1U)
#define DMA_EEI_EEI0_SHIFT (0U)
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
#define DMA_EEI_EEI1_MASK (0x2U)
#define DMA_EEI_EEI1_SHIFT (1U)
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
#define DMA_EEI_EEI2_MASK (0x4U)
#define DMA_EEI_EEI2_SHIFT (2U)
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
#define DMA_EEI_EEI3_MASK (0x8U)
#define DMA_EEI_EEI3_SHIFT (3U)
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
#define DMA_EEI_EEI4_MASK (0x10U)
#define DMA_EEI_EEI4_SHIFT (4U)
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
#define DMA_EEI_EEI5_MASK (0x20U)
#define DMA_EEI_EEI5_SHIFT (5U)
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
#define DMA_EEI_EEI6_MASK (0x40U)
#define DMA_EEI_EEI6_SHIFT (6U)
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
#define DMA_EEI_EEI7_MASK (0x80U)
#define DMA_EEI_EEI7_SHIFT (7U)
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
#define DMA_EEI_EEI8_MASK (0x100U)
#define DMA_EEI_EEI8_SHIFT (8U)
#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
#define DMA_EEI_EEI9_MASK (0x200U)
#define DMA_EEI_EEI9_SHIFT (9U)
#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
#define DMA_EEI_EEI10_MASK (0x400U)
#define DMA_EEI_EEI10_SHIFT (10U)
#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
#define DMA_EEI_EEI11_MASK (0x800U)
#define DMA_EEI_EEI11_SHIFT (11U)
#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
#define DMA_EEI_EEI12_MASK (0x1000U)
#define DMA_EEI_EEI12_SHIFT (12U)
#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
#define DMA_EEI_EEI13_MASK (0x2000U)
#define DMA_EEI_EEI13_SHIFT (13U)
#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
#define DMA_EEI_EEI14_MASK (0x4000U)
#define DMA_EEI_EEI14_SHIFT (14U)
#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
#define DMA_EEI_EEI15_MASK (0x8000U)
#define DMA_EEI_EEI15_SHIFT (15U)
#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
#define DMA_EEI_EEI16_MASK (0x10000U)
#define DMA_EEI_EEI16_SHIFT (16U)
#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
#define DMA_EEI_EEI17_MASK (0x20000U)
#define DMA_EEI_EEI17_SHIFT (17U)
#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
#define DMA_EEI_EEI18_MASK (0x40000U)
#define DMA_EEI_EEI18_SHIFT (18U)
#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
#define DMA_EEI_EEI19_MASK (0x80000U)
#define DMA_EEI_EEI19_SHIFT (19U)
#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
#define DMA_EEI_EEI20_MASK (0x100000U)
#define DMA_EEI_EEI20_SHIFT (20U)
#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
#define DMA_EEI_EEI21_MASK (0x200000U)
#define DMA_EEI_EEI21_SHIFT (21U)
#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
#define DMA_EEI_EEI22_MASK (0x400000U)
#define DMA_EEI_EEI22_SHIFT (22U)
#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
#define DMA_EEI_EEI23_MASK (0x800000U)
#define DMA_EEI_EEI23_SHIFT (23U)
#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
#define DMA_EEI_EEI24_MASK (0x1000000U)
#define DMA_EEI_EEI24_SHIFT (24U)
#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
#define DMA_EEI_EEI25_MASK (0x2000000U)
#define DMA_EEI_EEI25_SHIFT (25U)
#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
#define DMA_EEI_EEI26_MASK (0x4000000U)
#define DMA_EEI_EEI26_SHIFT (26U)
#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
#define DMA_EEI_EEI27_MASK (0x8000000U)
#define DMA_EEI_EEI27_SHIFT (27U)
#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
#define DMA_EEI_EEI28_MASK (0x10000000U)
#define DMA_EEI_EEI28_SHIFT (28U)
#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
#define DMA_EEI_EEI29_MASK (0x20000000U)
#define DMA_EEI_EEI29_SHIFT (29U)
#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
#define DMA_EEI_EEI30_MASK (0x40000000U)
#define DMA_EEI_EEI30_SHIFT (30U)
#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
#define DMA_EEI_EEI31_MASK (0x80000000U)
#define DMA_EEI_EEI31_SHIFT (31U)
#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
/*! @} */
/*! @name CEEI - Clear Enable Error Interrupt Register */
/*! @{ */
#define DMA_CEEI_CEEI_MASK (0x1FU)
#define DMA_CEEI_CEEI_SHIFT (0U)
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK (0x40U)
#define DMA_CEEI_CAEE_SHIFT (6U)
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
#define DMA_CEEI_NOP_MASK (0x80U)
#define DMA_CEEI_NOP_SHIFT (7U)
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
/*! @} */
/*! @name SEEI - Set Enable Error Interrupt Register */
/*! @{ */
#define DMA_SEEI_SEEI_MASK (0x1FU)
#define DMA_SEEI_SEEI_SHIFT (0U)
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK (0x40U)
#define DMA_SEEI_SAEE_SHIFT (6U)
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
#define DMA_SEEI_NOP_MASK (0x80U)
#define DMA_SEEI_NOP_SHIFT (7U)
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
/*! @} */
/*! @name CERQ - Clear Enable Request Register */
/*! @{ */
#define DMA_CERQ_CERQ_MASK (0x1FU)
#define DMA_CERQ_CERQ_SHIFT (0U)
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK (0x40U)
#define DMA_CERQ_CAER_SHIFT (6U)
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
#define DMA_CERQ_NOP_MASK (0x80U)
#define DMA_CERQ_NOP_SHIFT (7U)
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
/*! @} */
/*! @name SERQ - Set Enable Request Register */
/*! @{ */
#define DMA_SERQ_SERQ_MASK (0x1FU)
#define DMA_SERQ_SERQ_SHIFT (0U)
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK (0x40U)
#define DMA_SERQ_SAER_SHIFT (6U)
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
#define DMA_SERQ_NOP_MASK (0x80U)
#define DMA_SERQ_NOP_SHIFT (7U)
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
/*! @} */
/*! @name CDNE - Clear DONE Status Bit Register */
/*! @{ */
#define DMA_CDNE_CDNE_MASK (0x1FU)
#define DMA_CDNE_CDNE_SHIFT (0U)
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK (0x40U)
#define DMA_CDNE_CADN_SHIFT (6U)
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
#define DMA_CDNE_NOP_MASK (0x80U)
#define DMA_CDNE_NOP_SHIFT (7U)
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
/*! @} */
/*! @name SSRT - Set START Bit Register */
/*! @{ */
#define DMA_SSRT_SSRT_MASK (0x1FU)
#define DMA_SSRT_SSRT_SHIFT (0U)
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK (0x40U)
#define DMA_SSRT_SAST_SHIFT (6U)
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
#define DMA_SSRT_NOP_MASK (0x80U)
#define DMA_SSRT_NOP_SHIFT (7U)
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
/*! @} */
/*! @name CERR - Clear Error Register */
/*! @{ */
#define DMA_CERR_CERR_MASK (0x1FU)
#define DMA_CERR_CERR_SHIFT (0U)
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK (0x40U)
#define DMA_CERR_CAEI_SHIFT (6U)
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
#define DMA_CERR_NOP_MASK (0x80U)
#define DMA_CERR_NOP_SHIFT (7U)
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
/*! @} */
/*! @name CINT - Clear Interrupt Request Register */
/*! @{ */
#define DMA_CINT_CINT_MASK (0x1FU)
#define DMA_CINT_CINT_SHIFT (0U)
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK (0x40U)
#define DMA_CINT_CAIR_SHIFT (6U)
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
#define DMA_CINT_NOP_MASK (0x80U)
#define DMA_CINT_NOP_SHIFT (7U)
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
/*! @} */
/*! @name INT - Interrupt Request Register */
/*! @{ */
#define DMA_INT_INT0_MASK (0x1U)
#define DMA_INT_INT0_SHIFT (0U)
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
#define DMA_INT_INT1_MASK (0x2U)
#define DMA_INT_INT1_SHIFT (1U)
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
#define DMA_INT_INT2_MASK (0x4U)
#define DMA_INT_INT2_SHIFT (2U)
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
#define DMA_INT_INT3_MASK (0x8U)
#define DMA_INT_INT3_SHIFT (3U)
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
#define DMA_INT_INT4_MASK (0x10U)
#define DMA_INT_INT4_SHIFT (4U)
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
#define DMA_INT_INT5_MASK (0x20U)
#define DMA_INT_INT5_SHIFT (5U)
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
#define DMA_INT_INT6_MASK (0x40U)
#define DMA_INT_INT6_SHIFT (6U)
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
#define DMA_INT_INT7_MASK (0x80U)
#define DMA_INT_INT7_SHIFT (7U)
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
#define DMA_INT_INT8_MASK (0x100U)
#define DMA_INT_INT8_SHIFT (8U)
#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
#define DMA_INT_INT9_MASK (0x200U)
#define DMA_INT_INT9_SHIFT (9U)
#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
#define DMA_INT_INT10_MASK (0x400U)
#define DMA_INT_INT10_SHIFT (10U)
#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
#define DMA_INT_INT11_MASK (0x800U)
#define DMA_INT_INT11_SHIFT (11U)
#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
#define DMA_INT_INT12_MASK (0x1000U)
#define DMA_INT_INT12_SHIFT (12U)
#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
#define DMA_INT_INT13_MASK (0x2000U)
#define DMA_INT_INT13_SHIFT (13U)
#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
#define DMA_INT_INT14_MASK (0x4000U)
#define DMA_INT_INT14_SHIFT (14U)
#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
#define DMA_INT_INT15_MASK (0x8000U)
#define DMA_INT_INT15_SHIFT (15U)
#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
#define DMA_INT_INT16_MASK (0x10000U)
#define DMA_INT_INT16_SHIFT (16U)
#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
#define DMA_INT_INT17_MASK (0x20000U)
#define DMA_INT_INT17_SHIFT (17U)
#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
#define DMA_INT_INT18_MASK (0x40000U)
#define DMA_INT_INT18_SHIFT (18U)
#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
#define DMA_INT_INT19_MASK (0x80000U)
#define DMA_INT_INT19_SHIFT (19U)
#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
#define DMA_INT_INT20_MASK (0x100000U)
#define DMA_INT_INT20_SHIFT (20U)
#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
#define DMA_INT_INT21_MASK (0x200000U)
#define DMA_INT_INT21_SHIFT (21U)
#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
#define DMA_INT_INT22_MASK (0x400000U)
#define DMA_INT_INT22_SHIFT (22U)
#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
#define DMA_INT_INT23_MASK (0x800000U)
#define DMA_INT_INT23_SHIFT (23U)
#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
#define DMA_INT_INT24_MASK (0x1000000U)
#define DMA_INT_INT24_SHIFT (24U)
#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
#define DMA_INT_INT25_MASK (0x2000000U)
#define DMA_INT_INT25_SHIFT (25U)
#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
#define DMA_INT_INT26_MASK (0x4000000U)
#define DMA_INT_INT26_SHIFT (26U)
#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
#define DMA_INT_INT27_MASK (0x8000000U)
#define DMA_INT_INT27_SHIFT (27U)
#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
#define DMA_INT_INT28_MASK (0x10000000U)
#define DMA_INT_INT28_SHIFT (28U)
#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
#define DMA_INT_INT29_MASK (0x20000000U)
#define DMA_INT_INT29_SHIFT (29U)
#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
#define DMA_INT_INT30_MASK (0x40000000U)
#define DMA_INT_INT30_SHIFT (30U)
#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
#define DMA_INT_INT31_MASK (0x80000000U)
#define DMA_INT_INT31_SHIFT (31U)
#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
/*! @} */
/*! @name ERR - Error Register */
/*! @{ */
#define DMA_ERR_ERR0_MASK (0x1U)
#define DMA_ERR_ERR0_SHIFT (0U)
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
#define DMA_ERR_ERR1_MASK (0x2U)
#define DMA_ERR_ERR1_SHIFT (1U)
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
#define DMA_ERR_ERR2_MASK (0x4U)
#define DMA_ERR_ERR2_SHIFT (2U)
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
#define DMA_ERR_ERR3_MASK (0x8U)
#define DMA_ERR_ERR3_SHIFT (3U)
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
#define DMA_ERR_ERR4_MASK (0x10U)
#define DMA_ERR_ERR4_SHIFT (4U)
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
#define DMA_ERR_ERR5_MASK (0x20U)
#define DMA_ERR_ERR5_SHIFT (5U)
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
#define DMA_ERR_ERR6_MASK (0x40U)
#define DMA_ERR_ERR6_SHIFT (6U)
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
#define DMA_ERR_ERR7_MASK (0x80U)
#define DMA_ERR_ERR7_SHIFT (7U)
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
#define DMA_ERR_ERR8_MASK (0x100U)
#define DMA_ERR_ERR8_SHIFT (8U)
#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
#define DMA_ERR_ERR9_MASK (0x200U)
#define DMA_ERR_ERR9_SHIFT (9U)
#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
#define DMA_ERR_ERR10_MASK (0x400U)
#define DMA_ERR_ERR10_SHIFT (10U)
#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
#define DMA_ERR_ERR11_MASK (0x800U)
#define DMA_ERR_ERR11_SHIFT (11U)
#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
#define DMA_ERR_ERR12_MASK (0x1000U)
#define DMA_ERR_ERR12_SHIFT (12U)
#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
#define DMA_ERR_ERR13_MASK (0x2000U)
#define DMA_ERR_ERR13_SHIFT (13U)
#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
#define DMA_ERR_ERR14_MASK (0x4000U)
#define DMA_ERR_ERR14_SHIFT (14U)
#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
#define DMA_ERR_ERR15_MASK (0x8000U)
#define DMA_ERR_ERR15_SHIFT (15U)
#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
#define DMA_ERR_ERR16_MASK (0x10000U)
#define DMA_ERR_ERR16_SHIFT (16U)
#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
#define DMA_ERR_ERR17_MASK (0x20000U)
#define DMA_ERR_ERR17_SHIFT (17U)
#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
#define DMA_ERR_ERR18_MASK (0x40000U)
#define DMA_ERR_ERR18_SHIFT (18U)
#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
#define DMA_ERR_ERR19_MASK (0x80000U)
#define DMA_ERR_ERR19_SHIFT (19U)
#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
#define DMA_ERR_ERR20_MASK (0x100000U)
#define DMA_ERR_ERR20_SHIFT (20U)
#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
#define DMA_ERR_ERR21_MASK (0x200000U)
#define DMA_ERR_ERR21_SHIFT (21U)
#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
#define DMA_ERR_ERR22_MASK (0x400000U)
#define DMA_ERR_ERR22_SHIFT (22U)
#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
#define DMA_ERR_ERR23_MASK (0x800000U)
#define DMA_ERR_ERR23_SHIFT (23U)
#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
#define DMA_ERR_ERR24_MASK (0x1000000U)
#define DMA_ERR_ERR24_SHIFT (24U)
#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
#define DMA_ERR_ERR25_MASK (0x2000000U)
#define DMA_ERR_ERR25_SHIFT (25U)
#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
#define DMA_ERR_ERR26_MASK (0x4000000U)
#define DMA_ERR_ERR26_SHIFT (26U)
#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
#define DMA_ERR_ERR27_MASK (0x8000000U)
#define DMA_ERR_ERR27_SHIFT (27U)
#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
#define DMA_ERR_ERR28_MASK (0x10000000U)
#define DMA_ERR_ERR28_SHIFT (28U)
#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
#define DMA_ERR_ERR29_MASK (0x20000000U)
#define DMA_ERR_ERR29_SHIFT (29U)
#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
#define DMA_ERR_ERR30_MASK (0x40000000U)
#define DMA_ERR_ERR30_SHIFT (30U)
#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
#define DMA_ERR_ERR31_MASK (0x80000000U)
#define DMA_ERR_ERR31_SHIFT (31U)
#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
/*! @} */
/*! @name HRS - Hardware Request Status Register */
/*! @{ */
#define DMA_HRS_HRS0_MASK (0x1U)
#define DMA_HRS_HRS0_SHIFT (0U)
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
#define DMA_HRS_HRS1_MASK (0x2U)
#define DMA_HRS_HRS1_SHIFT (1U)
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
#define DMA_HRS_HRS2_MASK (0x4U)
#define DMA_HRS_HRS2_SHIFT (2U)
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
#define DMA_HRS_HRS3_MASK (0x8U)
#define DMA_HRS_HRS3_SHIFT (3U)
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
#define DMA_HRS_HRS4_MASK (0x10U)
#define DMA_HRS_HRS4_SHIFT (4U)
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
#define DMA_HRS_HRS5_MASK (0x20U)
#define DMA_HRS_HRS5_SHIFT (5U)
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
#define DMA_HRS_HRS6_MASK (0x40U)
#define DMA_HRS_HRS6_SHIFT (6U)
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
#define DMA_HRS_HRS7_MASK (0x80U)
#define DMA_HRS_HRS7_SHIFT (7U)
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
#define DMA_HRS_HRS8_MASK (0x100U)
#define DMA_HRS_HRS8_SHIFT (8U)
#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
#define DMA_HRS_HRS9_MASK (0x200U)
#define DMA_HRS_HRS9_SHIFT (9U)
#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
#define DMA_HRS_HRS10_MASK (0x400U)
#define DMA_HRS_HRS10_SHIFT (10U)
#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
#define DMA_HRS_HRS11_MASK (0x800U)
#define DMA_HRS_HRS11_SHIFT (11U)
#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
#define DMA_HRS_HRS12_MASK (0x1000U)
#define DMA_HRS_HRS12_SHIFT (12U)
#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
#define DMA_HRS_HRS13_MASK (0x2000U)
#define DMA_HRS_HRS13_SHIFT (13U)
#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
#define DMA_HRS_HRS14_MASK (0x4000U)
#define DMA_HRS_HRS14_SHIFT (14U)
#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
#define DMA_HRS_HRS15_MASK (0x8000U)
#define DMA_HRS_HRS15_SHIFT (15U)
#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
#define DMA_HRS_HRS16_MASK (0x10000U)
#define DMA_HRS_HRS16_SHIFT (16U)
#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
#define DMA_HRS_HRS17_MASK (0x20000U)
#define DMA_HRS_HRS17_SHIFT (17U)
#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
#define DMA_HRS_HRS18_MASK (0x40000U)
#define DMA_HRS_HRS18_SHIFT (18U)
#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
#define DMA_HRS_HRS19_MASK (0x80000U)
#define DMA_HRS_HRS19_SHIFT (19U)
#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
#define DMA_HRS_HRS20_MASK (0x100000U)
#define DMA_HRS_HRS20_SHIFT (20U)
#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
#define DMA_HRS_HRS21_MASK (0x200000U)
#define DMA_HRS_HRS21_SHIFT (21U)
#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
#define DMA_HRS_HRS22_MASK (0x400000U)
#define DMA_HRS_HRS22_SHIFT (22U)
#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
#define DMA_HRS_HRS23_MASK (0x800000U)
#define DMA_HRS_HRS23_SHIFT (23U)
#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
#define DMA_HRS_HRS24_MASK (0x1000000U)
#define DMA_HRS_HRS24_SHIFT (24U)
#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
#define DMA_HRS_HRS25_MASK (0x2000000U)
#define DMA_HRS_HRS25_SHIFT (25U)
#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
#define DMA_HRS_HRS26_MASK (0x4000000U)
#define DMA_HRS_HRS26_SHIFT (26U)
#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
#define DMA_HRS_HRS27_MASK (0x8000000U)
#define DMA_HRS_HRS27_SHIFT (27U)
#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
#define DMA_HRS_HRS28_MASK (0x10000000U)
#define DMA_HRS_HRS28_SHIFT (28U)
#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
#define DMA_HRS_HRS29_MASK (0x20000000U)
#define DMA_HRS_HRS29_SHIFT (29U)
#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
#define DMA_HRS_HRS30_MASK (0x40000000U)
#define DMA_HRS_HRS30_SHIFT (30U)
#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
#define DMA_HRS_HRS31_MASK (0x80000000U)
#define DMA_HRS_HRS31_SHIFT (31U)
#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
/*! @} */
/*! @name EARS - Enable Asynchronous Request in Stop Register */
/*! @{ */
#define DMA_EARS_EDREQ_0_MASK (0x1U)
#define DMA_EARS_EDREQ_0_SHIFT (0U)
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
#define DMA_EARS_EDREQ_1_MASK (0x2U)
#define DMA_EARS_EDREQ_1_SHIFT (1U)
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
#define DMA_EARS_EDREQ_2_MASK (0x4U)
#define DMA_EARS_EDREQ_2_SHIFT (2U)
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
#define DMA_EARS_EDREQ_3_MASK (0x8U)
#define DMA_EARS_EDREQ_3_SHIFT (3U)
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
#define DMA_EARS_EDREQ_4_MASK (0x10U)
#define DMA_EARS_EDREQ_4_SHIFT (4U)
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
#define DMA_EARS_EDREQ_5_MASK (0x20U)
#define DMA_EARS_EDREQ_5_SHIFT (5U)
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
#define DMA_EARS_EDREQ_6_MASK (0x40U)
#define DMA_EARS_EDREQ_6_SHIFT (6U)
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
#define DMA_EARS_EDREQ_7_MASK (0x80U)
#define DMA_EARS_EDREQ_7_SHIFT (7U)
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
#define DMA_EARS_EDREQ_8_MASK (0x100U)
#define DMA_EARS_EDREQ_8_SHIFT (8U)
#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
#define DMA_EARS_EDREQ_9_MASK (0x200U)
#define DMA_EARS_EDREQ_9_SHIFT (9U)
#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
#define DMA_EARS_EDREQ_10_MASK (0x400U)
#define DMA_EARS_EDREQ_10_SHIFT (10U)
#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
#define DMA_EARS_EDREQ_11_MASK (0x800U)
#define DMA_EARS_EDREQ_11_SHIFT (11U)
#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
#define DMA_EARS_EDREQ_12_MASK (0x1000U)
#define DMA_EARS_EDREQ_12_SHIFT (12U)
#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
#define DMA_EARS_EDREQ_13_MASK (0x2000U)
#define DMA_EARS_EDREQ_13_SHIFT (13U)
#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
#define DMA_EARS_EDREQ_14_MASK (0x4000U)
#define DMA_EARS_EDREQ_14_SHIFT (14U)
#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
#define DMA_EARS_EDREQ_15_MASK (0x8000U)
#define DMA_EARS_EDREQ_15_SHIFT (15U)
#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
#define DMA_EARS_EDREQ_16_MASK (0x10000U)
#define DMA_EARS_EDREQ_16_SHIFT (16U)
#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
#define DMA_EARS_EDREQ_17_MASK (0x20000U)
#define DMA_EARS_EDREQ_17_SHIFT (17U)
#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
#define DMA_EARS_EDREQ_18_MASK (0x40000U)
#define DMA_EARS_EDREQ_18_SHIFT (18U)
#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
#define DMA_EARS_EDREQ_19_MASK (0x80000U)
#define DMA_EARS_EDREQ_19_SHIFT (19U)
#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
#define DMA_EARS_EDREQ_20_MASK (0x100000U)
#define DMA_EARS_EDREQ_20_SHIFT (20U)
#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
#define DMA_EARS_EDREQ_21_MASK (0x200000U)
#define DMA_EARS_EDREQ_21_SHIFT (21U)
#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
#define DMA_EARS_EDREQ_22_MASK (0x400000U)
#define DMA_EARS_EDREQ_22_SHIFT (22U)
#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
#define DMA_EARS_EDREQ_23_MASK (0x800000U)
#define DMA_EARS_EDREQ_23_SHIFT (23U)
#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define DMA_EARS_EDREQ_24_SHIFT (24U)
#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define DMA_EARS_EDREQ_25_SHIFT (25U)
#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define DMA_EARS_EDREQ_26_SHIFT (26U)
#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define DMA_EARS_EDREQ_27_SHIFT (27U)
#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define DMA_EARS_EDREQ_28_SHIFT (28U)
#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define DMA_EARS_EDREQ_29_SHIFT (29U)
#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define DMA_EARS_EDREQ_30_SHIFT (30U)
#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define DMA_EARS_EDREQ_31_SHIFT (31U)
#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
/*! @} */
/*! @name DCHPRI3 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK (0x40U)
#define DMA_DCHPRI3_DPA_SHIFT (6U)
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
#define DMA_DCHPRI3_ECP_MASK (0x80U)
#define DMA_DCHPRI3_ECP_SHIFT (7U)
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
/*! @} */
/*! @name DCHPRI2 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK (0x40U)
#define DMA_DCHPRI2_DPA_SHIFT (6U)
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
#define DMA_DCHPRI2_ECP_MASK (0x80U)
#define DMA_DCHPRI2_ECP_SHIFT (7U)
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
/*! @} */
/*! @name DCHPRI1 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK (0x40U)
#define DMA_DCHPRI1_DPA_SHIFT (6U)
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
#define DMA_DCHPRI1_ECP_MASK (0x80U)
#define DMA_DCHPRI1_ECP_SHIFT (7U)
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
/*! @} */
/*! @name DCHPRI0 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK (0x40U)
#define DMA_DCHPRI0_DPA_SHIFT (6U)
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
#define DMA_DCHPRI0_ECP_MASK (0x80U)
#define DMA_DCHPRI0_ECP_SHIFT (7U)
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
/*! @} */
/*! @name DCHPRI7 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK (0x40U)
#define DMA_DCHPRI7_DPA_SHIFT (6U)
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
#define DMA_DCHPRI7_ECP_MASK (0x80U)
#define DMA_DCHPRI7_ECP_SHIFT (7U)
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
/*! @} */
/*! @name DCHPRI6 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK (0x40U)
#define DMA_DCHPRI6_DPA_SHIFT (6U)
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
#define DMA_DCHPRI6_ECP_MASK (0x80U)
#define DMA_DCHPRI6_ECP_SHIFT (7U)
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
/*! @} */
/*! @name DCHPRI5 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK (0x40U)
#define DMA_DCHPRI5_DPA_SHIFT (6U)
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
#define DMA_DCHPRI5_ECP_MASK (0x80U)
#define DMA_DCHPRI5_ECP_SHIFT (7U)
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
/*! @} */
/*! @name DCHPRI4 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK (0x40U)
#define DMA_DCHPRI4_DPA_SHIFT (6U)
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
#define DMA_DCHPRI4_ECP_MASK (0x80U)
#define DMA_DCHPRI4_ECP_SHIFT (7U)
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
/*! @} */
/*! @name DCHPRI11 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
#define DMA_DCHPRI11_DPA_MASK (0x40U)
#define DMA_DCHPRI11_DPA_SHIFT (6U)
#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
#define DMA_DCHPRI11_ECP_MASK (0x80U)
#define DMA_DCHPRI11_ECP_SHIFT (7U)
#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
/*! @} */
/*! @name DCHPRI10 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
#define DMA_DCHPRI10_DPA_MASK (0x40U)
#define DMA_DCHPRI10_DPA_SHIFT (6U)
#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
#define DMA_DCHPRI10_ECP_MASK (0x80U)
#define DMA_DCHPRI10_ECP_SHIFT (7U)
#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
/*! @} */
/*! @name DCHPRI9 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
#define DMA_DCHPRI9_DPA_MASK (0x40U)
#define DMA_DCHPRI9_DPA_SHIFT (6U)
#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
#define DMA_DCHPRI9_ECP_MASK (0x80U)
#define DMA_DCHPRI9_ECP_SHIFT (7U)
#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
/*! @} */
/*! @name DCHPRI8 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
#define DMA_DCHPRI8_DPA_MASK (0x40U)
#define DMA_DCHPRI8_DPA_SHIFT (6U)
#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
#define DMA_DCHPRI8_ECP_MASK (0x80U)
#define DMA_DCHPRI8_ECP_SHIFT (7U)
#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
/*! @} */
/*! @name DCHPRI15 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
#define DMA_DCHPRI15_DPA_MASK (0x40U)
#define DMA_DCHPRI15_DPA_SHIFT (6U)
#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
#define DMA_DCHPRI15_ECP_MASK (0x80U)
#define DMA_DCHPRI15_ECP_SHIFT (7U)
#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
/*! @} */
/*! @name DCHPRI14 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
#define DMA_DCHPRI14_DPA_MASK (0x40U)
#define DMA_DCHPRI14_DPA_SHIFT (6U)
#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
#define DMA_DCHPRI14_ECP_MASK (0x80U)
#define DMA_DCHPRI14_ECP_SHIFT (7U)
#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
/*! @} */
/*! @name DCHPRI13 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
#define DMA_DCHPRI13_DPA_MASK (0x40U)
#define DMA_DCHPRI13_DPA_SHIFT (6U)
#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
#define DMA_DCHPRI13_ECP_MASK (0x80U)
#define DMA_DCHPRI13_ECP_SHIFT (7U)
#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
/*! @} */
/*! @name DCHPRI12 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
#define DMA_DCHPRI12_DPA_MASK (0x40U)
#define DMA_DCHPRI12_DPA_SHIFT (6U)
#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
#define DMA_DCHPRI12_ECP_MASK (0x80U)
#define DMA_DCHPRI12_ECP_SHIFT (7U)
#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
/*! @} */
/*! @name DCHPRI19 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
#define DMA_DCHPRI19_DPA_MASK (0x40U)
#define DMA_DCHPRI19_DPA_SHIFT (6U)
#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
#define DMA_DCHPRI19_ECP_MASK (0x80U)
#define DMA_DCHPRI19_ECP_SHIFT (7U)
#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
/*! @} */
/*! @name DCHPRI18 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
#define DMA_DCHPRI18_DPA_MASK (0x40U)
#define DMA_DCHPRI18_DPA_SHIFT (6U)
#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
#define DMA_DCHPRI18_ECP_MASK (0x80U)
#define DMA_DCHPRI18_ECP_SHIFT (7U)
#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
/*! @} */
/*! @name DCHPRI17 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
#define DMA_DCHPRI17_DPA_MASK (0x40U)
#define DMA_DCHPRI17_DPA_SHIFT (6U)
#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
#define DMA_DCHPRI17_ECP_MASK (0x80U)
#define DMA_DCHPRI17_ECP_SHIFT (7U)
#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
/*! @} */
/*! @name DCHPRI16 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
#define DMA_DCHPRI16_DPA_MASK (0x40U)
#define DMA_DCHPRI16_DPA_SHIFT (6U)
#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
#define DMA_DCHPRI16_ECP_MASK (0x80U)
#define DMA_DCHPRI16_ECP_SHIFT (7U)
#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
/*! @} */
/*! @name DCHPRI23 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
#define DMA_DCHPRI23_DPA_MASK (0x40U)
#define DMA_DCHPRI23_DPA_SHIFT (6U)
#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
#define DMA_DCHPRI23_ECP_MASK (0x80U)
#define DMA_DCHPRI23_ECP_SHIFT (7U)
#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
/*! @} */
/*! @name DCHPRI22 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
#define DMA_DCHPRI22_DPA_MASK (0x40U)
#define DMA_DCHPRI22_DPA_SHIFT (6U)
#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
#define DMA_DCHPRI22_ECP_MASK (0x80U)
#define DMA_DCHPRI22_ECP_SHIFT (7U)
#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
/*! @} */
/*! @name DCHPRI21 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
#define DMA_DCHPRI21_DPA_MASK (0x40U)
#define DMA_DCHPRI21_DPA_SHIFT (6U)
#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
#define DMA_DCHPRI21_ECP_MASK (0x80U)
#define DMA_DCHPRI21_ECP_SHIFT (7U)
#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
/*! @} */
/*! @name DCHPRI20 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
#define DMA_DCHPRI20_DPA_MASK (0x40U)
#define DMA_DCHPRI20_DPA_SHIFT (6U)
#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
#define DMA_DCHPRI20_ECP_MASK (0x80U)
#define DMA_DCHPRI20_ECP_SHIFT (7U)
#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
/*! @} */
/*! @name DCHPRI27 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
#define DMA_DCHPRI27_DPA_MASK (0x40U)
#define DMA_DCHPRI27_DPA_SHIFT (6U)
#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
#define DMA_DCHPRI27_ECP_MASK (0x80U)
#define DMA_DCHPRI27_ECP_SHIFT (7U)
#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
/*! @} */
/*! @name DCHPRI26 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
#define DMA_DCHPRI26_DPA_MASK (0x40U)
#define DMA_DCHPRI26_DPA_SHIFT (6U)
#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
#define DMA_DCHPRI26_ECP_MASK (0x80U)
#define DMA_DCHPRI26_ECP_SHIFT (7U)
#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
/*! @} */
/*! @name DCHPRI25 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
#define DMA_DCHPRI25_DPA_MASK (0x40U)
#define DMA_DCHPRI25_DPA_SHIFT (6U)
#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
#define DMA_DCHPRI25_ECP_MASK (0x80U)
#define DMA_DCHPRI25_ECP_SHIFT (7U)
#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
/*! @} */
/*! @name DCHPRI24 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
#define DMA_DCHPRI24_DPA_MASK (0x40U)
#define DMA_DCHPRI24_DPA_SHIFT (6U)
#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
#define DMA_DCHPRI24_ECP_MASK (0x80U)
#define DMA_DCHPRI24_ECP_SHIFT (7U)
#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
/*! @} */
/*! @name DCHPRI31 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
#define DMA_DCHPRI31_DPA_MASK (0x40U)
#define DMA_DCHPRI31_DPA_SHIFT (6U)
#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
#define DMA_DCHPRI31_ECP_MASK (0x80U)
#define DMA_DCHPRI31_ECP_SHIFT (7U)
#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
/*! @} */
/*! @name DCHPRI30 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
#define DMA_DCHPRI30_DPA_MASK (0x40U)
#define DMA_DCHPRI30_DPA_SHIFT (6U)
#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
#define DMA_DCHPRI30_ECP_MASK (0x80U)
#define DMA_DCHPRI30_ECP_SHIFT (7U)
#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
/*! @} */
/*! @name DCHPRI29 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
#define DMA_DCHPRI29_DPA_MASK (0x40U)
#define DMA_DCHPRI29_DPA_SHIFT (6U)
#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
#define DMA_DCHPRI29_ECP_MASK (0x80U)
#define DMA_DCHPRI29_ECP_SHIFT (7U)
#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
/*! @} */
/*! @name DCHPRI28 - Channel n Priority Register */
/*! @{ */
#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
#define DMA_DCHPRI28_DPA_MASK (0x40U)
#define DMA_DCHPRI28_DPA_SHIFT (6U)
#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
#define DMA_DCHPRI28_ECP_MASK (0x80U)
#define DMA_DCHPRI28_ECP_SHIFT (7U)
#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
/*! @} */
/*! @name SADDR - TCD Source Address */
/*! @{ */
#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define DMA_SADDR_SADDR_SHIFT (0U)
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
/*! @} */
/* The count of DMA_SADDR */
#define DMA_SADDR_COUNT (32U)
/*! @name SOFF - TCD Signed Source Address Offset */
/*! @{ */
#define DMA_SOFF_SOFF_MASK (0xFFFFU)
#define DMA_SOFF_SOFF_SHIFT (0U)
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
/*! @} */
/* The count of DMA_SOFF */
#define DMA_SOFF_COUNT (32U)
/*! @name ATTR - TCD Transfer Attributes */
/*! @{ */
#define DMA_ATTR_DSIZE_MASK (0x7U)
#define DMA_ATTR_DSIZE_SHIFT (0U)
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK (0xF8U)
#define DMA_ATTR_DMOD_SHIFT (3U)
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK (0x700U)
#define DMA_ATTR_SSIZE_SHIFT (8U)
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK (0xF800U)
#define DMA_ATTR_SMOD_SHIFT (11U)
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
/*! @} */
/* The count of DMA_ATTR */
#define DMA_ATTR_COUNT (32U)
/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
/*! @{ */
#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLNO */
#define DMA_NBYTES_MLNO_COUNT (32U)
/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
/*! @{ */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLOFFNO */
#define DMA_NBYTES_MLOFFNO_COUNT (32U)
/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
/*! @{ */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLOFFYES */
#define DMA_NBYTES_MLOFFYES_COUNT (32U)
/*! @name SLAST - TCD Last Source Address Adjustment */
/*! @{ */
#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define DMA_SLAST_SLAST_SHIFT (0U)
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
/*! @} */
/* The count of DMA_SLAST */
#define DMA_SLAST_COUNT (32U)
/*! @name DADDR - TCD Destination Address */
/*! @{ */
#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define DMA_DADDR_DADDR_SHIFT (0U)
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
/*! @} */
/* The count of DMA_DADDR */
#define DMA_DADDR_COUNT (32U)
/*! @name DOFF - TCD Signed Destination Address Offset */
/*! @{ */
#define DMA_DOFF_DOFF_MASK (0xFFFFU)
#define DMA_DOFF_DOFF_SHIFT (0U)
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
/*! @} */
/* The count of DMA_DOFF */
#define DMA_DOFF_COUNT (32U)
/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
/*! @{ */
#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_CITER_ELINKNO */
#define DMA_CITER_ELINKNO_COUNT (32U)
/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
/*! @{ */
#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_CITER_ELINKYES */
#define DMA_CITER_ELINKYES_COUNT (32U)
/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
/*! @{ */
#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
/*! @} */
/* The count of DMA_DLAST_SGA */
#define DMA_DLAST_SGA_COUNT (32U)
/*! @name CSR - TCD Control and Status */
/*! @{ */
#define DMA_CSR_START_MASK (0x1U)
#define DMA_CSR_START_SHIFT (0U)
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
#define DMA_CSR_INTMAJOR_MASK (0x2U)
#define DMA_CSR_INTMAJOR_SHIFT (1U)
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
#define DMA_CSR_INTHALF_MASK (0x4U)
#define DMA_CSR_INTHALF_SHIFT (2U)
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
#define DMA_CSR_DREQ_MASK (0x8U)
#define DMA_CSR_DREQ_SHIFT (3U)
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
#define DMA_CSR_ESG_MASK (0x10U)
#define DMA_CSR_ESG_SHIFT (4U)
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
#define DMA_CSR_MAJORELINK_MASK (0x20U)
#define DMA_CSR_MAJORELINK_SHIFT (5U)
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
#define DMA_CSR_ACTIVE_MASK (0x40U)
#define DMA_CSR_ACTIVE_SHIFT (6U)
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
#define DMA_CSR_DONE_MASK (0x80U)
#define DMA_CSR_DONE_SHIFT (7U)
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK (0xC000U)
#define DMA_CSR_BWC_SHIFT (14U)
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
/*! @} */
/* The count of DMA_CSR */
#define DMA_CSR_COUNT (32U)
/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
/*! @{ */
#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_BITER_ELINKNO */
#define DMA_BITER_ELINKNO_COUNT (32U)
/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
/*! @{ */
#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_BITER_ELINKYES */
#define DMA_BITER_ELINKYES_COUNT (32U)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE (0x400E8000u)
/** Peripheral DMA0 base pointer */
#define DMA0 ((DMA_Type *)DMA0_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA0_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
/*! @{ */
#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/*! @} */
/* The count of DMAMUX_CHCFG */
#define DMAMUX_CHCFG_COUNT (32U)
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX base address */
#define DMAMUX_BASE (0x400EC000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX }
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
* @{
*/
/** ENC - Register Layout Typedef */
typedef struct {
__IO uint16_t CTRL; /**< Control Register, offset: 0x0 */
__IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */
__IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */
__IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */
__I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */
__IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */
__I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */
__IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */
__IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */
__I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */
__I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */
__IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */
__IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */
__I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */
__IO uint16_t TST; /**< Test Register, offset: 0x1C */
__IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */
__IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */
__IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */
__IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */
__IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */
} ENC_Type;
/* ----------------------------------------------------------------------------
-- ENC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENC_Register_Masks ENC Register Masks
* @{
*/
/*! @name CTRL - Control Register */
/*! @{ */
#define ENC_CTRL_CMPIE_MASK (0x1U)
#define ENC_CTRL_CMPIE_SHIFT (0U)
#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define ENC_CTRL_CMPIRQ_MASK (0x2U)
#define ENC_CTRL_CMPIRQ_SHIFT (1U)
#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define ENC_CTRL_WDE_MASK (0x4U)
#define ENC_CTRL_WDE_SHIFT (2U)
#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define ENC_CTRL_DIE_MASK (0x8U)
#define ENC_CTRL_DIE_SHIFT (3U)
#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define ENC_CTRL_DIRQ_MASK (0x10U)
#define ENC_CTRL_DIRQ_SHIFT (4U)
#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define ENC_CTRL_XNE_MASK (0x20U)
#define ENC_CTRL_XNE_SHIFT (5U)
#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define ENC_CTRL_XIP_MASK (0x40U)
#define ENC_CTRL_XIP_SHIFT (6U)
#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define ENC_CTRL_XIE_MASK (0x80U)
#define ENC_CTRL_XIE_SHIFT (7U)
#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define ENC_CTRL_XIRQ_MASK (0x100U)
#define ENC_CTRL_XIRQ_SHIFT (8U)
#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define ENC_CTRL_PH1_MASK (0x200U)
#define ENC_CTRL_PH1_SHIFT (9U)
#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define ENC_CTRL_REV_MASK (0x400U)
#define ENC_CTRL_REV_SHIFT (10U)
#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define ENC_CTRL_SWIP_MASK (0x800U)
#define ENC_CTRL_SWIP_SHIFT (11U)
#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define ENC_CTRL_HNE_MASK (0x1000U)
#define ENC_CTRL_HNE_SHIFT (12U)
#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define ENC_CTRL_HIP_MASK (0x2000U)
#define ENC_CTRL_HIP_SHIFT (13U)
#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define ENC_CTRL_HIE_MASK (0x4000U)
#define ENC_CTRL_HIE_SHIFT (14U)
#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define ENC_CTRL_HIRQ_MASK (0x8000U)
#define ENC_CTRL_HIRQ_SHIFT (15U)
#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
/*! @} */
/*! @name FILT - Input Filter Register */
/*! @{ */
#define ENC_FILT_FILT_PER_MASK (0xFFU)
#define ENC_FILT_FILT_PER_SHIFT (0U)
#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
#define ENC_FILT_FILT_CNT_MASK (0x700U)
#define ENC_FILT_FILT_CNT_SHIFT (8U)
#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
/*! @} */
/*! @name WTR - Watchdog Timeout Register */
/*! @{ */
#define ENC_WTR_WDOG_MASK (0xFFFFU)
#define ENC_WTR_WDOG_SHIFT (0U)
#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
/*! @} */
/*! @name POSD - Position Difference Counter Register */
/*! @{ */
#define ENC_POSD_POSD_MASK (0xFFFFU)
#define ENC_POSD_POSD_SHIFT (0U)
#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
/*! @} */
/*! @name POSDH - Position Difference Hold Register */
/*! @{ */
#define ENC_POSDH_POSDH_MASK (0xFFFFU)
#define ENC_POSDH_POSDH_SHIFT (0U)
#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
/*! @} */
/*! @name REV - Revolution Counter Register */
/*! @{ */
#define ENC_REV_REV_MASK (0xFFFFU)
#define ENC_REV_REV_SHIFT (0U)
#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
/*! @} */
/*! @name REVH - Revolution Hold Register */
/*! @{ */
#define ENC_REVH_REVH_MASK (0xFFFFU)
#define ENC_REVH_REVH_SHIFT (0U)
#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
/*! @} */
/*! @name UPOS - Upper Position Counter Register */
/*! @{ */
#define ENC_UPOS_POS_MASK (0xFFFFU)
#define ENC_UPOS_POS_SHIFT (0U)
#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
/*! @} */
/*! @name LPOS - Lower Position Counter Register */
/*! @{ */
#define ENC_LPOS_POS_MASK (0xFFFFU)
#define ENC_LPOS_POS_SHIFT (0U)
#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
/*! @} */
/*! @name UPOSH - Upper Position Hold Register */
/*! @{ */
#define ENC_UPOSH_POSH_MASK (0xFFFFU)
#define ENC_UPOSH_POSH_SHIFT (0U)
#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
/*! @} */
/*! @name LPOSH - Lower Position Hold Register */
/*! @{ */
#define ENC_LPOSH_POSH_MASK (0xFFFFU)
#define ENC_LPOSH_POSH_SHIFT (0U)
#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
/*! @} */
/*! @name UINIT - Upper Initialization Register */
/*! @{ */
#define ENC_UINIT_INIT_MASK (0xFFFFU)
#define ENC_UINIT_INIT_SHIFT (0U)
#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
/*! @} */
/*! @name LINIT - Lower Initialization Register */
/*! @{ */
#define ENC_LINIT_INIT_MASK (0xFFFFU)
#define ENC_LINIT_INIT_SHIFT (0U)
#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
/*! @} */
/*! @name IMR - Input Monitor Register */
/*! @{ */
#define ENC_IMR_HOME_MASK (0x1U)
#define ENC_IMR_HOME_SHIFT (0U)
#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
#define ENC_IMR_INDEX_MASK (0x2U)
#define ENC_IMR_INDEX_SHIFT (1U)
#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
#define ENC_IMR_PHB_MASK (0x4U)
#define ENC_IMR_PHB_SHIFT (2U)
#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
#define ENC_IMR_PHA_MASK (0x8U)
#define ENC_IMR_PHA_SHIFT (3U)
#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
#define ENC_IMR_FHOM_MASK (0x10U)
#define ENC_IMR_FHOM_SHIFT (4U)
#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
#define ENC_IMR_FIND_MASK (0x20U)
#define ENC_IMR_FIND_SHIFT (5U)
#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
#define ENC_IMR_FPHB_MASK (0x40U)
#define ENC_IMR_FPHB_SHIFT (6U)
#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
#define ENC_IMR_FPHA_MASK (0x80U)
#define ENC_IMR_FPHA_SHIFT (7U)
#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
/*! @} */
/*! @name TST - Test Register */
/*! @{ */
#define ENC_TST_TEST_COUNT_MASK (0xFFU)
#define ENC_TST_TEST_COUNT_SHIFT (0U)
#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
#define ENC_TST_TEST_PERIOD_SHIFT (8U)
#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
#define ENC_TST_QDN_MASK (0x2000U)
#define ENC_TST_QDN_SHIFT (13U)
#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
#define ENC_TST_TCE_MASK (0x4000U)
#define ENC_TST_TCE_SHIFT (14U)
#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
#define ENC_TST_TEN_MASK (0x8000U)
#define ENC_TST_TEN_SHIFT (15U)
#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
/*! @} */
/*! @name CTRL2 - Control 2 Register */
/*! @{ */
#define ENC_CTRL2_UPDHLD_MASK (0x1U)
#define ENC_CTRL2_UPDHLD_SHIFT (0U)
#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
#define ENC_CTRL2_UPDPOS_MASK (0x2U)
#define ENC_CTRL2_UPDPOS_SHIFT (1U)
#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
#define ENC_CTRL2_MOD_MASK (0x4U)
#define ENC_CTRL2_MOD_SHIFT (2U)
#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
#define ENC_CTRL2_DIR_MASK (0x8U)
#define ENC_CTRL2_DIR_SHIFT (3U)
#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
#define ENC_CTRL2_RUIE_MASK (0x10U)
#define ENC_CTRL2_RUIE_SHIFT (4U)
#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
#define ENC_CTRL2_RUIRQ_MASK (0x20U)
#define ENC_CTRL2_RUIRQ_SHIFT (5U)
#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
#define ENC_CTRL2_ROIE_MASK (0x40U)
#define ENC_CTRL2_ROIE_SHIFT (6U)
#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
#define ENC_CTRL2_ROIRQ_MASK (0x80U)
#define ENC_CTRL2_ROIRQ_SHIFT (7U)
#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
#define ENC_CTRL2_REVMOD_MASK (0x100U)
#define ENC_CTRL2_REVMOD_SHIFT (8U)
#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
#define ENC_CTRL2_OUTCTL_MASK (0x200U)
#define ENC_CTRL2_OUTCTL_SHIFT (9U)
#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
#define ENC_CTRL2_SABIE_MASK (0x400U)
#define ENC_CTRL2_SABIE_SHIFT (10U)
#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
#define ENC_CTRL2_SABIRQ_MASK (0x800U)
#define ENC_CTRL2_SABIRQ_SHIFT (11U)
#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
/*! @} */
/*! @name UMOD - Upper Modulus Register */
/*! @{ */
#define ENC_UMOD_MOD_MASK (0xFFFFU)
#define ENC_UMOD_MOD_SHIFT (0U)
#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
/*! @} */
/*! @name LMOD - Lower Modulus Register */
/*! @{ */
#define ENC_LMOD_MOD_MASK (0xFFFFU)
#define ENC_LMOD_MOD_SHIFT (0U)
#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
/*! @} */
/*! @name UCOMP - Upper Position Compare Register */
/*! @{ */
#define ENC_UCOMP_COMP_MASK (0xFFFFU)
#define ENC_UCOMP_COMP_SHIFT (0U)
#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
/*! @} */
/*! @name LCOMP - Lower Position Compare Register */
/*! @{ */
#define ENC_LCOMP_COMP_MASK (0xFFFFU)
#define ENC_LCOMP_COMP_SHIFT (0U)
#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ENC_Register_Masks */
/* ENC - Peripheral instance base addresses */
/** Peripheral ENC1 base address */
#define ENC1_BASE (0x403C8000u)
/** Peripheral ENC1 base pointer */
#define ENC1 ((ENC_Type *)ENC1_BASE)
/** Peripheral ENC2 base address */
#define ENC2_BASE (0x403CC000u)
/** Peripheral ENC2 base pointer */
#define ENC2 ((ENC_Type *)ENC2_BASE)
/** Peripheral ENC3 base address */
#define ENC3_BASE (0x403D0000u)
/** Peripheral ENC3 base pointer */
#define ENC3 ((ENC_Type *)ENC3_BASE)
/** Peripheral ENC4 base address */
#define ENC4_BASE (0x403D4000u)
/** Peripheral ENC4 base pointer */
#define ENC4 ((ENC_Type *)ENC4_BASE)
/** Array initializer of ENC peripheral base addresses */
#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
/** Array initializer of ENC peripheral base pointers */
#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
/** Interrupt vectors for the ENC peripheral type */
#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
/*!
* @}
*/ /* end of group ENC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENET Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
* @{
*/
/** ENET - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
__IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
uint8_t RESERVED_1[4];
__IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
__IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
uint8_t RESERVED_2[12];
__IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
uint8_t RESERVED_3[24];
__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
uint8_t RESERVED_4[28];
__IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
uint8_t RESERVED_5[28];
__IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
uint8_t RESERVED_6[60];
__IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
uint8_t RESERVED_7[28];
__IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
__IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
__IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
__IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */
uint8_t RESERVED_8[12];
__IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */
uint8_t RESERVED_9[20];
__IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
__IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
__IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
__IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
uint8_t RESERVED_10[28];
__IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
uint8_t RESERVED_11[56];
__IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
__IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
__IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
uint8_t RESERVED_12[4];
__IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
__IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
__IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
__IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
__IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
__IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
__IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
__IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
__IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
uint8_t RESERVED_13[12];
__IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
__IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
uint8_t RESERVED_14[56];
uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
__I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
__I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
__I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
__I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
__I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
__I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
__I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
__I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
__I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
__I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
__I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
__I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
__I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
__I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
__I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
__I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
__I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
__I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
__I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
__I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
__I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
__I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
__I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
__I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
__I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
__I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
__I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
__I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
uint8_t RESERVED_15[12];
__I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
__I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
__I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
__I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
__I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
__I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
__I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
__I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
__I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
__I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
__I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
__I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
__I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
__I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
__I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
__I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
__I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
__I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
__I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
__I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
__I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
__I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
__I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
uint8_t RESERVED_16[284];
__IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
__IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
__IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
__IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
__IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
__IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
__I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
uint8_t RESERVED_17[488];
__IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
struct { /* offset: 0x608, array step: 0x8 */
__IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
__IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
} CHANNEL[4];
} ENET_Type;
/* ----------------------------------------------------------------------------
-- ENET Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Register_Masks ENET Register Masks
* @{
*/
/*! @name EIR - Interrupt Event Register */
/*! @{ */
#define ENET_EIR_TS_TIMER_MASK (0x8000U)
#define ENET_EIR_TS_TIMER_SHIFT (15U)
#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIR_TS_AVAIL_SHIFT (16U)
#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define ENET_EIR_WAKEUP_MASK (0x20000U)
#define ENET_EIR_WAKEUP_SHIFT (17U)
#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define ENET_EIR_PLR_MASK (0x40000U)
#define ENET_EIR_PLR_SHIFT (18U)
#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define ENET_EIR_UN_MASK (0x80000U)
#define ENET_EIR_UN_SHIFT (19U)
#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define ENET_EIR_RL_MASK (0x100000U)
#define ENET_EIR_RL_SHIFT (20U)
#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define ENET_EIR_LC_MASK (0x200000U)
#define ENET_EIR_LC_SHIFT (21U)
#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define ENET_EIR_EBERR_MASK (0x400000U)
#define ENET_EIR_EBERR_SHIFT (22U)
#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define ENET_EIR_MII_MASK (0x800000U)
#define ENET_EIR_MII_SHIFT (23U)
#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define ENET_EIR_RXB_MASK (0x1000000U)
#define ENET_EIR_RXB_SHIFT (24U)
#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define ENET_EIR_RXF_MASK (0x2000000U)
#define ENET_EIR_RXF_SHIFT (25U)
#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define ENET_EIR_TXB_MASK (0x4000000U)
#define ENET_EIR_TXB_SHIFT (26U)
#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define ENET_EIR_TXF_MASK (0x8000000U)
#define ENET_EIR_TXF_SHIFT (27U)
#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define ENET_EIR_GRA_MASK (0x10000000U)
#define ENET_EIR_GRA_SHIFT (28U)
#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define ENET_EIR_BABT_MASK (0x20000000U)
#define ENET_EIR_BABT_SHIFT (29U)
#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define ENET_EIR_BABR_MASK (0x40000000U)
#define ENET_EIR_BABR_SHIFT (30U)
#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
/*! @} */
/*! @name EIMR - Interrupt Mask Register */
/*! @{ */
#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
#define ENET_EIMR_TS_TIMER_SHIFT (15U)
#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define ENET_EIMR_WAKEUP_MASK (0x20000U)
#define ENET_EIMR_WAKEUP_SHIFT (17U)
#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define ENET_EIMR_PLR_MASK (0x40000U)
#define ENET_EIMR_PLR_SHIFT (18U)
#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define ENET_EIMR_UN_MASK (0x80000U)
#define ENET_EIMR_UN_SHIFT (19U)
#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define ENET_EIMR_RL_MASK (0x100000U)
#define ENET_EIMR_RL_SHIFT (20U)
#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define ENET_EIMR_LC_MASK (0x200000U)
#define ENET_EIMR_LC_SHIFT (21U)
#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define ENET_EIMR_EBERR_MASK (0x400000U)
#define ENET_EIMR_EBERR_SHIFT (22U)
#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define ENET_EIMR_MII_MASK (0x800000U)
#define ENET_EIMR_MII_SHIFT (23U)
#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define ENET_EIMR_RXB_MASK (0x1000000U)
#define ENET_EIMR_RXB_SHIFT (24U)
#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define ENET_EIMR_RXF_MASK (0x2000000U)
#define ENET_EIMR_RXF_SHIFT (25U)
#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define ENET_EIMR_TXB_MASK (0x4000000U)
#define ENET_EIMR_TXB_SHIFT (26U)
#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define ENET_EIMR_TXF_MASK (0x8000000U)
#define ENET_EIMR_TXF_SHIFT (27U)
#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define ENET_EIMR_GRA_MASK (0x10000000U)
#define ENET_EIMR_GRA_SHIFT (28U)
#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define ENET_EIMR_BABT_MASK (0x20000000U)
#define ENET_EIMR_BABT_SHIFT (29U)
#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define ENET_EIMR_BABR_MASK (0x40000000U)
#define ENET_EIMR_BABR_SHIFT (30U)
#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
/*! @} */
/*! @name RDAR - Receive Descriptor Active Register */
/*! @{ */
#define ENET_RDAR_RDAR_MASK (0x1000000U)
#define ENET_RDAR_RDAR_SHIFT (24U)
#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
/*! @} */
/*! @name TDAR - Transmit Descriptor Active Register */
/*! @{ */
#define ENET_TDAR_TDAR_MASK (0x1000000U)
#define ENET_TDAR_TDAR_SHIFT (24U)
#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
/*! @} */
/*! @name ECR - Ethernet Control Register */
/*! @{ */
#define ENET_ECR_RESET_MASK (0x1U)
#define ENET_ECR_RESET_SHIFT (0U)
#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define ENET_ECR_ETHEREN_MASK (0x2U)
#define ENET_ECR_ETHEREN_SHIFT (1U)
#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define ENET_ECR_MAGICEN_MASK (0x4U)
#define ENET_ECR_MAGICEN_SHIFT (2U)
#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define ENET_ECR_SLEEP_MASK (0x8U)
#define ENET_ECR_SLEEP_SHIFT (3U)
#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define ENET_ECR_EN1588_MASK (0x10U)
#define ENET_ECR_EN1588_SHIFT (4U)
#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define ENET_ECR_DBGEN_MASK (0x40U)
#define ENET_ECR_DBGEN_SHIFT (6U)
#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define ENET_ECR_DBSWP_MASK (0x100U)
#define ENET_ECR_DBSWP_SHIFT (8U)
#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
/*! @} */
/*! @name MMFR - MII Management Frame Register */
/*! @{ */
#define ENET_MMFR_DATA_MASK (0xFFFFU)
#define ENET_MMFR_DATA_SHIFT (0U)
#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define ENET_MMFR_TA_MASK (0x30000U)
#define ENET_MMFR_TA_SHIFT (16U)
#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define ENET_MMFR_RA_MASK (0x7C0000U)
#define ENET_MMFR_RA_SHIFT (18U)
#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define ENET_MMFR_PA_MASK (0xF800000U)
#define ENET_MMFR_PA_SHIFT (23U)
#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define ENET_MMFR_OP_MASK (0x30000000U)
#define ENET_MMFR_OP_SHIFT (28U)
#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define ENET_MMFR_ST_MASK (0xC0000000U)
#define ENET_MMFR_ST_SHIFT (30U)
#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
/*! @} */
/*! @name MSCR - MII Speed Control Register */
/*! @{ */
#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
#define ENET_MSCR_MII_SPEED_SHIFT (1U)
#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define ENET_MSCR_DIS_PRE_MASK (0x80U)
#define ENET_MSCR_DIS_PRE_SHIFT (7U)
#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define ENET_MSCR_HOLDTIME_MASK (0x700U)
#define ENET_MSCR_HOLDTIME_SHIFT (8U)
#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
/*! @} */
/*! @name MIBC - MIB Control Register */
/*! @{ */
#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
#define ENET_MIBC_MIB_DIS_SHIFT (31U)
#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
/*! @} */
/*! @name RCR - Receive Control Register */
/*! @{ */
#define ENET_RCR_LOOP_MASK (0x1U)
#define ENET_RCR_LOOP_SHIFT (0U)
#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define ENET_RCR_DRT_MASK (0x2U)
#define ENET_RCR_DRT_SHIFT (1U)
#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define ENET_RCR_MII_MODE_MASK (0x4U)
#define ENET_RCR_MII_MODE_SHIFT (2U)
#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define ENET_RCR_PROM_MASK (0x8U)
#define ENET_RCR_PROM_SHIFT (3U)
#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define ENET_RCR_BC_REJ_MASK (0x10U)
#define ENET_RCR_BC_REJ_SHIFT (4U)
#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define ENET_RCR_FCE_MASK (0x20U)
#define ENET_RCR_FCE_SHIFT (5U)
#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define ENET_RCR_RMII_MODE_MASK (0x100U)
#define ENET_RCR_RMII_MODE_SHIFT (8U)
#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define ENET_RCR_RMII_10T_MASK (0x200U)
#define ENET_RCR_RMII_10T_SHIFT (9U)
#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define ENET_RCR_PADEN_MASK (0x1000U)
#define ENET_RCR_PADEN_SHIFT (12U)
#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define ENET_RCR_PAUFWD_MASK (0x2000U)
#define ENET_RCR_PAUFWD_SHIFT (13U)
#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define ENET_RCR_CRCFWD_MASK (0x4000U)
#define ENET_RCR_CRCFWD_SHIFT (14U)
#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define ENET_RCR_CFEN_MASK (0x8000U)
#define ENET_RCR_CFEN_SHIFT (15U)
#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
#define ENET_RCR_MAX_FL_SHIFT (16U)
#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define ENET_RCR_NLC_MASK (0x40000000U)
#define ENET_RCR_NLC_SHIFT (30U)
#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define ENET_RCR_GRS_MASK (0x80000000U)
#define ENET_RCR_GRS_SHIFT (31U)
#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
/*! @} */
/*! @name TCR - Transmit Control Register */
/*! @{ */
#define ENET_TCR_GTS_MASK (0x1U)
#define ENET_TCR_GTS_SHIFT (0U)
#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define ENET_TCR_FDEN_MASK (0x4U)
#define ENET_TCR_FDEN_SHIFT (2U)
#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define ENET_TCR_ADDSEL_MASK (0xE0U)
#define ENET_TCR_ADDSEL_SHIFT (5U)
#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define ENET_TCR_ADDINS_MASK (0x100U)
#define ENET_TCR_ADDINS_SHIFT (8U)
#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define ENET_TCR_CRCFWD_MASK (0x200U)
#define ENET_TCR_CRCFWD_SHIFT (9U)
#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
/*! @} */
/*! @name PALR - Physical Address Lower Register */
/*! @{ */
#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
#define ENET_PALR_PADDR1_SHIFT (0U)
#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
/*! @} */
/*! @name PAUR - Physical Address Upper Register */
/*! @{ */
#define ENET_PAUR_TYPE_MASK (0xFFFFU)
#define ENET_PAUR_TYPE_SHIFT (0U)
#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
#define ENET_PAUR_PADDR2_SHIFT (16U)
#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
/*! @} */
/*! @name OPD - Opcode/Pause Duration Register */
/*! @{ */
#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
#define ENET_OPD_OPCODE_SHIFT (16U)
#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
/*! @} */
/*! @name TXIC - Transmit Interrupt Coalescing Register */
/*! @{ */
#define ENET_TXIC_ICTT_MASK (0xFFFFU)
#define ENET_TXIC_ICTT_SHIFT (0U)
#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
#define ENET_TXIC_ICFT_MASK (0xFF00000U)
#define ENET_TXIC_ICFT_SHIFT (20U)
#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
#define ENET_TXIC_ICCS_MASK (0x40000000U)
#define ENET_TXIC_ICCS_SHIFT (30U)
#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
#define ENET_TXIC_ICEN_MASK (0x80000000U)
#define ENET_TXIC_ICEN_SHIFT (31U)
#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
/*! @} */
/*! @name RXIC - Receive Interrupt Coalescing Register */
/*! @{ */
#define ENET_RXIC_ICTT_MASK (0xFFFFU)
#define ENET_RXIC_ICTT_SHIFT (0U)
#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
#define ENET_RXIC_ICFT_MASK (0xFF00000U)
#define ENET_RXIC_ICFT_SHIFT (20U)
#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
#define ENET_RXIC_ICCS_MASK (0x40000000U)
#define ENET_RXIC_ICCS_SHIFT (30U)
#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
#define ENET_RXIC_ICEN_MASK (0x80000000U)
#define ENET_RXIC_ICEN_SHIFT (31U)
#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
/*! @} */
/*! @name IAUR - Descriptor Individual Upper Address Register */
/*! @{ */
#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
#define ENET_IAUR_IADDR1_SHIFT (0U)
#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
/*! @} */
/*! @name IALR - Descriptor Individual Lower Address Register */
/*! @{ */
#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
#define ENET_IALR_IADDR2_SHIFT (0U)
#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
/*! @} */
/*! @name GAUR - Descriptor Group Upper Address Register */
/*! @{ */
#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
#define ENET_GAUR_GADDR1_SHIFT (0U)
#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
/*! @} */
/*! @name GALR - Descriptor Group Lower Address Register */
/*! @{ */
#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
#define ENET_GALR_GADDR2_SHIFT (0U)
#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
/*! @} */
/*! @name TFWR - Transmit FIFO Watermark Register */
/*! @{ */
#define ENET_TFWR_TFWR_MASK (0x3FU)
#define ENET_TFWR_TFWR_SHIFT (0U)
#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define ENET_TFWR_STRFWD_MASK (0x100U)
#define ENET_TFWR_STRFWD_SHIFT (8U)
#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
/*! @} */
/*! @name RDSR - Receive Descriptor Ring Start Register */
/*! @{ */
#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR_R_DES_START_SHIFT (3U)
#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
/*! @} */
/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
/*! @{ */
#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR_X_DES_START_SHIFT (3U)
#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
/*! @} */
/*! @name MRBR - Maximum Receive Buffer Size Register */
/*! @{ */
#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RSFL - Receive FIFO Section Full Threshold */
/*! @{ */
#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
/*! @} */
/*! @name RSEM - Receive FIFO Section Empty Threshold */
/*! @{ */
#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
/*! @} */
/*! @name RAEM - Receive FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
/*! @} */
/*! @name RAFL - Receive FIFO Almost Full Threshold */
/*! @{ */
#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
/*! @} */
/*! @name TSEM - Transmit FIFO Section Empty Threshold */
/*! @{ */
#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
/*! @} */
/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
/*! @} */
/*! @name TAFL - Transmit FIFO Almost Full Threshold */
/*! @{ */
#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
/*! @} */
/*! @name TIPG - Transmit Inter-Packet Gap */
/*! @{ */
#define ENET_TIPG_IPG_MASK (0x1FU)
#define ENET_TIPG_IPG_SHIFT (0U)
#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
/*! @} */
/*! @name FTRL - Frame Truncation Length */
/*! @{ */
#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
/*! @} */
/*! @name TACC - Transmit Accelerator Function Configuration */
/*! @{ */
#define ENET_TACC_SHIFT16_MASK (0x1U)
#define ENET_TACC_SHIFT16_SHIFT (0U)
#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define ENET_TACC_IPCHK_MASK (0x8U)
#define ENET_TACC_IPCHK_SHIFT (3U)
#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define ENET_TACC_PROCHK_MASK (0x10U)
#define ENET_TACC_PROCHK_SHIFT (4U)
#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
/*! @} */
/*! @name RACC - Receive Accelerator Function Configuration */
/*! @{ */
#define ENET_RACC_PADREM_MASK (0x1U)
#define ENET_RACC_PADREM_SHIFT (0U)
#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define ENET_RACC_IPDIS_MASK (0x2U)
#define ENET_RACC_IPDIS_SHIFT (1U)
#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define ENET_RACC_PRODIS_MASK (0x4U)
#define ENET_RACC_PRODIS_SHIFT (2U)
#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define ENET_RACC_LINEDIS_MASK (0x40U)
#define ENET_RACC_LINEDIS_SHIFT (6U)
#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define ENET_RACC_SHIFT16_MASK (0x80U)
#define ENET_RACC_SHIFT16_SHIFT (7U)
#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
/*! @} */
/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
/*! @} */
/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
/*! @{ */
#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_SQE - Reserved Statistic Register */
/*! @{ */
#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
/*! @} */
/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
/*! @} */
/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
/*! @} */
/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
/*! @{ */
#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
/*! @{ */
#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name ATCR - Adjustable Timer Control Register */
/*! @{ */
#define ENET_ATCR_EN_MASK (0x1U)
#define ENET_ATCR_EN_SHIFT (0U)
#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define ENET_ATCR_OFFEN_MASK (0x4U)
#define ENET_ATCR_OFFEN_SHIFT (2U)
#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define ENET_ATCR_OFFRST_MASK (0x8U)
#define ENET_ATCR_OFFRST_SHIFT (3U)
#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define ENET_ATCR_PEREN_MASK (0x10U)
#define ENET_ATCR_PEREN_SHIFT (4U)
#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define ENET_ATCR_PINPER_MASK (0x80U)
#define ENET_ATCR_PINPER_SHIFT (7U)
#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define ENET_ATCR_RESTART_MASK (0x200U)
#define ENET_ATCR_RESTART_SHIFT (9U)
#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define ENET_ATCR_CAPTURE_MASK (0x800U)
#define ENET_ATCR_CAPTURE_SHIFT (11U)
#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define ENET_ATCR_SLAVE_MASK (0x2000U)
#define ENET_ATCR_SLAVE_SHIFT (13U)
#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
/*! @} */
/*! @name ATVR - Timer Value Register */
/*! @{ */
#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
#define ENET_ATVR_ATIME_SHIFT (0U)
#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
/*! @} */
/*! @name ATOFF - Timer Offset Register */
/*! @{ */
#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
#define ENET_ATOFF_OFFSET_SHIFT (0U)
#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
/*! @} */
/*! @name ATPER - Timer Period Register */
/*! @{ */
#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
#define ENET_ATPER_PERIOD_SHIFT (0U)
#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
/*! @} */
/*! @name ATCOR - Timer Correction Register */
/*! @{ */
#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
#define ENET_ATCOR_COR_SHIFT (0U)
#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
/*! @} */
/*! @name ATINC - Time-Stamping Clock Period Register */
/*! @{ */
#define ENET_ATINC_INC_MASK (0x7FU)
#define ENET_ATINC_INC_SHIFT (0U)
#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
#define ENET_ATINC_INC_CORR_SHIFT (8U)
#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
/*! @} */
/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
/*! @{ */
#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
/*! @} */
/*! @name TGSR - Timer Global Status Register */
/*! @{ */
#define ENET_TGSR_TF0_MASK (0x1U)
#define ENET_TGSR_TF0_SHIFT (0U)
#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define ENET_TGSR_TF1_MASK (0x2U)
#define ENET_TGSR_TF1_SHIFT (1U)
#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define ENET_TGSR_TF2_MASK (0x4U)
#define ENET_TGSR_TF2_SHIFT (2U)
#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define ENET_TGSR_TF3_MASK (0x8U)
#define ENET_TGSR_TF3_SHIFT (3U)
#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
/*! @} */
/*! @name TCSR - Timer Control Status Register */
/*! @{ */
#define ENET_TCSR_TDRE_MASK (0x1U)
#define ENET_TCSR_TDRE_SHIFT (0U)
#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define ENET_TCSR_TMODE_MASK (0x3CU)
#define ENET_TCSR_TMODE_SHIFT (2U)
#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define ENET_TCSR_TIE_MASK (0x40U)
#define ENET_TCSR_TIE_SHIFT (6U)
#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define ENET_TCSR_TF_MASK (0x80U)
#define ENET_TCSR_TF_SHIFT (7U)
#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define ENET_TCSR_TPWC_MASK (0xF800U)
#define ENET_TCSR_TPWC_SHIFT (11U)
#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
/*! @} */
/* The count of ENET_TCSR */
#define ENET_TCSR_COUNT (4U)
/*! @name TCCR - Timer Compare Capture Register */
/*! @{ */
#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
#define ENET_TCCR_TCC_SHIFT (0U)
#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
/*! @} */
/* The count of ENET_TCCR */
#define ENET_TCCR_COUNT (4U)
/*!
* @}
*/ /* end of group ENET_Register_Masks */
/* ENET - Peripheral instance base addresses */
/** Peripheral ENET base address */
#define ENET_BASE (0x402D8000u)
/** Peripheral ENET base pointer */
#define ENET ((ENET_Type *)ENET_BASE)
/** Array initializer of ENET peripheral base addresses */
#define ENET_BASE_ADDRS { ENET_BASE }
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASE_PTRS { ENET }
/** Interrupt vectors for the ENET peripheral type */
#define ENET_Transmit_IRQS { ENET_IRQn }
#define ENET_Receive_IRQS { ENET_IRQn }
#define ENET_Error_IRQS { ENET_IRQn }
#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT (64U)
/*!
* @}
*/ /* end of group ENET_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
* @{
*/
/** EWM - Register Layout Typedef */
typedef struct {
__IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
__IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;
/* ----------------------------------------------------------------------------
-- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
/*! @name CTRL - Control Register */
/*! @{ */
#define EWM_CTRL_EWMEN_MASK (0x1U)
#define EWM_CTRL_EWMEN_SHIFT (0U)
#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define EWM_CTRL_ASSIN_MASK (0x2U)
#define EWM_CTRL_ASSIN_SHIFT (1U)
#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define EWM_CTRL_INEN_MASK (0x4U)
#define EWM_CTRL_INEN_SHIFT (2U)
#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define EWM_CTRL_INTEN_MASK (0x8U)
#define EWM_CTRL_INTEN_SHIFT (3U)
#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
/*! @} */
/*! @name SERV - Service Register */
/*! @{ */
#define EWM_SERV_SERVICE_MASK (0xFFU)
#define EWM_SERV_SERVICE_SHIFT (0U)
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
/*! @} */
/*! @name CMPL - Compare Low Register */
/*! @{ */
#define EWM_CMPL_COMPAREL_MASK (0xFFU)
#define EWM_CMPL_COMPAREL_SHIFT (0U)
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
/*! @} */
/*! @name CMPH - Compare High Register */
/*! @{ */
#define EWM_CMPH_COMPAREH_MASK (0xFFU)
#define EWM_CMPH_COMPAREH_SHIFT (0U)
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
/*! @} */
/*! @name CLKCTRL - Clock Control Register */
/*! @{ */
#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
/*! @} */
/*! @name CLKPRESCALER - Clock Prescaler Register */
/*! @{ */
#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
/*! @} */
/*!
* @}
*/ /* end of group EWM_Register_Masks */
/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base address */
#define EWM_BASE (0x400B4000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASE_PTRS { EWM }
/** Interrupt vectors for the EWM peripheral type */
#define EWM_IRQS { EWM_IRQn }
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
* @{
*/
/** FLEXIO - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
uint8_t RESERVED_1[4];
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
uint8_t RESERVED_3[60];
__IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_4[112];
__IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_5[240];
__IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_6[112];
__IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
uint8_t RESERVED_7[112];
__IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
uint8_t RESERVED_8[112];
__IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
uint8_t RESERVED_9[112];
__IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_10[112];
__IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
uint8_t RESERVED_11[112];
__IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
uint8_t RESERVED_12[368];
__IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
uint8_t RESERVED_13[112];
__IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
uint8_t RESERVED_14[112];
__IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
} FLEXIO_Type;
/* ----------------------------------------------------------------------------
-- FLEXIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT (0U)
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT (16U)
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT (24U)
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT (8U)
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT (16U)
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */
/*! @name CTRL - FlexIO Control Register */
/*! @{ */
#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT (1U)
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT (30U)
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */
/*! @name PIN - Pin State Register */
/*! @{ */
#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
#define FLEXIO_PIN_PDI_SHIFT (0U)
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */
/*! @name SHIFTSTAT - Shifter Status Register */
/*! @{ */
#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */
/*! @name SHIFTERR - Shifter Error Register */
/*! @{ */
#define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */
/*! @name TIMSTAT - Timer Status Register */
/*! @{ */
#define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */
/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */
/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */
/*! @name TIMIEN - Timer Interrupt Enable Register */
/*! @{ */
#define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */
/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */
#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */
/*! @name SHIFTSTATE - Shifter State Register */
/*! @{ */
#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */
/*! @name SHIFTCTL - Shifter Control N Register */
/*! @{ */
#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT (4U)
/*! @name SHIFTCFG - Shifter Configuration N Register */
/*! @{ */
#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT (4U)
/*! @name SHIFTBUF - Shifter Buffer N Register */
/*! @{ */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT (4U)
/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT (4U)
/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT (4U)
/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT (4U)
/*! @name TIMCTL - Timer Control N Register */
/*! @{ */
#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */
/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT (4U)
/*! @name TIMCFG - Timer Configuration N Register */
/*! @{ */
#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */
/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT (4U)
/*! @name TIMCMP - Timer Compare N Register */
/*! @{ */
#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */
/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT (4U)
/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT (4U)
/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT (4U)
/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT (4U)
/*!
* @}
*/ /* end of group FLEXIO_Register_Masks */
/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO1 base address */
#define FLEXIO1_BASE (0x401AC000u)
/** Peripheral FLEXIO1 base pointer */
#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
/** Peripheral FLEXIO2 base address */
#define FLEXIO2_BASE (0x401B0000u)
/** Peripheral FLEXIO2 base pointer */
#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
/** Interrupt vectors for the FLEXIO peripheral type */
#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
/*!
* @}
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXRAM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
* @{
*/
/** FLEXRAM - Register Layout Typedef */
typedef struct {
__IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */
__IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */
__IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */
__IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */
__IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */
__IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */
__IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */
} FLEXRAM_Type;
/* ----------------------------------------------------------------------------
-- FLEXRAM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
* @{
*/
/*! @name TCM_CTRL - TCM CRTL Register */
/*! @{ */
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)
#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)
#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
/*! @} */
/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
/*! @{ */
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x1FFFEU)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (17U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
/*! @{ */
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
/*! @{ */
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFFFFC0U)
#define FLEXRAM_INT_STATUS_Reserved_SHIFT (6U)
#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
/*! @} */
/*! @name INT_STAT_EN - Interrupt Status Enable Register */
/*! @{ */
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFFFFC0U)
#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (6U)
#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
/*! @} */
/*! @name INT_SIG_EN - Interrupt Enable Register */
/*! @{ */
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFFFFC0U)
#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (6U)
#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
/*! @} */
/*!
* @}
*/ /* end of group FLEXRAM_Register_Masks */
/* FLEXRAM - Peripheral instance base addresses */
/** Peripheral FLEXRAM base address */
#define FLEXRAM_BASE (0x400B0000u)
/** Peripheral FLEXRAM base pointer */
#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
/** Array initializer of FLEXRAM peripheral base addresses */
#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
/** Array initializer of FLEXRAM peripheral base pointers */
#define FLEXRAM_BASE_PTRS { FLEXRAM }
/** Interrupt vectors for the FLEXRAM peripheral type */
#define FLEXRAM_IRQS { FLEXRAM_IRQn }
/*!
* @}
*/ /* end of group FLEXRAM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
* @{
*/
/** FLEXSPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
__IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
__IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
__IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
__IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
__IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
__IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
__IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_0[48];
__IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */
__IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */
__IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_1[4];
__IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
uint8_t RESERVED_2[8];
__IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
__IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
uint8_t RESERVED_3[8];
__IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
uint8_t RESERVED_4[4];
__IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
__IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
__IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_5[24];
__I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
__I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
__I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
__I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
__I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
__I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
uint8_t RESERVED_6[8];
__I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
__O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
__IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
} FLEXSPI_Type;
/* ----------------------------------------------------------------------------
-- FLEXSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
* @{
*/
/*! @name MCR0 - Module Control Register 0 */
/*! @{ */
#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */
/*! @name MCR1 - Module Control Register 1 */
/*! @{ */
#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */
/*! @name MCR2 - Module Control Register 2 */
/*! @{ */
#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */
/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */
#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
/*! @} */
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
/*! @} */
/*! @name INTR - Interrupt Register */
/*! @{ */
#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
/*! @} */
/*! @name LUTKEY - LUT Key Register */
/*! @{ */
#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */
/*! @name LUTCR - LUT Control Register */
/*! @{ */
#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
/*! @} */
/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */
/*! @{ */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */
/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */
/*! @{ */
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT (4U)
/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */
/*! @{ */
#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT (4U)
/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */
/*! @{ */
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT (4U)
/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */
#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
/*! @} */
/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */
#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */
/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */
#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */
/*! @name IPCMD - IP Command Register */
/*! @{ */
#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */
/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */
/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */
/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */
#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */
/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT (2U)
/*! @name STS0 - Status Register 0 */
/*! @{ */
#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
/*! @} */
/*! @name STS1 - Status Register 1 */
/*! @{ */
#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */
/*! @name STS2 - Status Register 2 */
/*! @{ */
#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */
/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */
/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */
/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */
/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT (32U)
/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT (32U)
/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */
/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT (64U)
/*!
* @}
*/ /* end of group FLEXSPI_Register_Masks */
/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI base address */
#define FLEXSPI_BASE (0x402A8000u)
/** Peripheral FLEXSPI base pointer */
#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS { FLEXSPI }
/** Interrupt vectors for the FLEXSPI peripheral type */
#define FLEXSPI_IRQS { FLEXSPI_IRQn }
/* FlexSPI AMBA address. */
#define FlexSPI_AMBA_BASE (0x60000000U)
/* FlexSPI ASFM address. */
#define FlexSPI_ASFM_BASE (0x00000000U)
/* Base Address of AHB address space mapped to IP RX FIFO. */
#define FlexSPI_ARDF_BASE (0x7FC00000U)
/* Base Address of AHB address space mapped to IP TX FIFO. */
#define FlexSPI_ATDF_BASE (0x7F800000U)
/*!
* @}
*/ /* end of group FLEXSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
* @{
*/
/** GPC - Register Layout Typedef */
typedef struct {
__IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */
uint8_t RESERVED_0[4];
__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */
__I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */
uint8_t RESERVED_1[12];
__IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */
__I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */
} GPC_Type;
/* ----------------------------------------------------------------------------
-- GPC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_Register_Masks GPC Register Masks
* @{
*/
/*! @name CNTR - GPC Interface control register */
/*! @{ */
#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
/*! @} */
/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */
/*! @{ */
#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
#define GPC_IMR_IMR1_SHIFT (0U)
#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
#define GPC_IMR_IMR2_SHIFT (0U)
#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
#define GPC_IMR_IMR3_SHIFT (0U)
#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
#define GPC_IMR_IMR4_SHIFT (0U)
#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/*! @} */
/* The count of GPC_IMR */
#define GPC_IMR_COUNT (4U)
/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */
/*! @{ */
#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
#define GPC_ISR_ISR1_SHIFT (0U)
#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
#define GPC_ISR_ISR2_SHIFT (0U)
#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
#define GPC_ISR_ISR3_SHIFT (0U)
#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
#define GPC_ISR_ISR4_SHIFT (0U)
#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
/*! @} */
/* The count of GPC_ISR */
#define GPC_ISR_COUNT (4U)
/*! @name IMR5 - IRQ masking register 5 */
/*! @{ */
#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
#define GPC_IMR5_IMR5_SHIFT (0U)
#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
/*! @} */
/*! @name ISR5 - IRQ status resister 5 */
/*! @{ */
#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
#define GPC_ISR5_ISR4_SHIFT (0U)
#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPC_Register_Masks */
/* GPC - Peripheral instance base addresses */
/** Peripheral GPC base address */
#define GPC_BASE (0x400F4000u)
/** Peripheral GPC base pointer */
#define GPC ((GPC_Type *)GPC_BASE)
/** Array initializer of GPC peripheral base addresses */
#define GPC_BASE_ADDRS { GPC_BASE }
/** Array initializer of GPC peripheral base pointers */
#define GPC_BASE_PTRS { GPC }
/** Interrupt vectors for the GPC peripheral type */
#define GPC_IRQS { GPC_IRQn }
/*!
* @}
*/ /* end of group GPC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
__IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
__I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
__IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
__IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
__IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
__IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
uint8_t RESERVED_0[100];
__O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */
__O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */
__O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name DR - GPIO data register */
/*! @{ */
#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
#define GPIO_DR_DR_SHIFT (0U)
#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
/*! @} */
/*! @name GDIR - GPIO direction register */
/*! @{ */
#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
#define GPIO_GDIR_GDIR_SHIFT (0U)
#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
/*! @} */
/*! @name PSR - GPIO pad status register */
/*! @{ */
#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
#define GPIO_PSR_PSR_SHIFT (0U)
#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
/*! @} */
/*! @name ICR1 - GPIO interrupt configuration register1 */
/*! @{ */
#define GPIO_ICR1_ICR0_MASK (0x3U)
#define GPIO_ICR1_ICR0_SHIFT (0U)
#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
#define GPIO_ICR1_ICR1_MASK (0xCU)
#define GPIO_ICR1_ICR1_SHIFT (2U)
#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
#define GPIO_ICR1_ICR2_MASK (0x30U)
#define GPIO_ICR1_ICR2_SHIFT (4U)
#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
#define GPIO_ICR1_ICR3_MASK (0xC0U)
#define GPIO_ICR1_ICR3_SHIFT (6U)
#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
#define GPIO_ICR1_ICR4_MASK (0x300U)
#define GPIO_ICR1_ICR4_SHIFT (8U)
#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
#define GPIO_ICR1_ICR5_MASK (0xC00U)
#define GPIO_ICR1_ICR5_SHIFT (10U)
#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
#define GPIO_ICR1_ICR6_MASK (0x3000U)
#define GPIO_ICR1_ICR6_SHIFT (12U)
#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
#define GPIO_ICR1_ICR7_MASK (0xC000U)
#define GPIO_ICR1_ICR7_SHIFT (14U)
#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
#define GPIO_ICR1_ICR8_MASK (0x30000U)
#define GPIO_ICR1_ICR8_SHIFT (16U)
#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
#define GPIO_ICR1_ICR9_MASK (0xC0000U)
#define GPIO_ICR1_ICR9_SHIFT (18U)
#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
#define GPIO_ICR1_ICR10_MASK (0x300000U)
#define GPIO_ICR1_ICR10_SHIFT (20U)
#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
#define GPIO_ICR1_ICR11_MASK (0xC00000U)
#define GPIO_ICR1_ICR11_SHIFT (22U)
#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
#define GPIO_ICR1_ICR12_MASK (0x3000000U)
#define GPIO_ICR1_ICR12_SHIFT (24U)
#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
#define GPIO_ICR1_ICR13_MASK (0xC000000U)
#define GPIO_ICR1_ICR13_SHIFT (26U)
#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
#define GPIO_ICR1_ICR14_MASK (0x30000000U)
#define GPIO_ICR1_ICR14_SHIFT (28U)
#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
#define GPIO_ICR1_ICR15_SHIFT (30U)
#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
/*! @} */
/*! @name ICR2 - GPIO interrupt configuration register2 */
/*! @{ */
#define GPIO_ICR2_ICR16_MASK (0x3U)
#define GPIO_ICR2_ICR16_SHIFT (0U)
#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
#define GPIO_ICR2_ICR17_MASK (0xCU)
#define GPIO_ICR2_ICR17_SHIFT (2U)
#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
#define GPIO_ICR2_ICR18_MASK (0x30U)
#define GPIO_ICR2_ICR18_SHIFT (4U)
#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
#define GPIO_ICR2_ICR19_MASK (0xC0U)
#define GPIO_ICR2_ICR19_SHIFT (6U)
#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
#define GPIO_ICR2_ICR20_MASK (0x300U)
#define GPIO_ICR2_ICR20_SHIFT (8U)
#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
#define GPIO_ICR2_ICR21_MASK (0xC00U)
#define GPIO_ICR2_ICR21_SHIFT (10U)
#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
#define GPIO_ICR2_ICR22_MASK (0x3000U)
#define GPIO_ICR2_ICR22_SHIFT (12U)
#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
#define GPIO_ICR2_ICR23_MASK (0xC000U)
#define GPIO_ICR2_ICR23_SHIFT (14U)
#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
#define GPIO_ICR2_ICR24_MASK (0x30000U)
#define GPIO_ICR2_ICR24_SHIFT (16U)
#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
#define GPIO_ICR2_ICR25_MASK (0xC0000U)
#define GPIO_ICR2_ICR25_SHIFT (18U)
#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
#define GPIO_ICR2_ICR26_MASK (0x300000U)
#define GPIO_ICR2_ICR26_SHIFT (20U)
#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
#define GPIO_ICR2_ICR27_MASK (0xC00000U)
#define GPIO_ICR2_ICR27_SHIFT (22U)
#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
#define GPIO_ICR2_ICR28_MASK (0x3000000U)
#define GPIO_ICR2_ICR28_SHIFT (24U)
#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
#define GPIO_ICR2_ICR29_MASK (0xC000000U)
#define GPIO_ICR2_ICR29_SHIFT (26U)
#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
#define GPIO_ICR2_ICR30_MASK (0x30000000U)
#define GPIO_ICR2_ICR30_SHIFT (28U)
#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
#define GPIO_ICR2_ICR31_SHIFT (30U)
#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
/*! @} */
/*! @name IMR - GPIO interrupt mask register */
/*! @{ */
#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
#define GPIO_IMR_IMR_SHIFT (0U)
#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
/*! @} */
/*! @name ISR - GPIO interrupt status register */
/*! @{ */
#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
#define GPIO_ISR_ISR_SHIFT (0U)
#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
/*! @} */
/*! @name EDGE_SEL - GPIO edge select register */
/*! @{ */
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
/*! @} */
/*! @name DR_SET - GPIO data register SET */
/*! @{ */
#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
#define GPIO_DR_SET_DR_SET_SHIFT (0U)
#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
/*! @} */
/*! @name DR_CLEAR - GPIO data register CLEAR */
/*! @{ */
#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
/*! @} */
/*! @name DR_TOGGLE - GPIO data register TOGGLE */
/*! @{ */
#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIO1 base address */
#define GPIO1_BASE (0x401B8000u)
/** Peripheral GPIO1 base pointer */
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
/** Peripheral GPIO2 base address */
#define GPIO2_BASE (0x401BC000u)
/** Peripheral GPIO2 base pointer */
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
/** Peripheral GPIO3 base address */
#define GPIO3_BASE (0x401C0000u)
/** Peripheral GPIO3 base pointer */
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
/** Peripheral GPIO4 base address */
#define GPIO4_BASE (0x401C4000u)
/** Peripheral GPIO4 base pointer */
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
/** Peripheral GPIO5 base address */
#define GPIO5_BASE (0x400C0000u)
/** Peripheral GPIO5 base pointer */
#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
/** Interrupt vectors for the GPIO peripheral type */
#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
* @{
*/
/** GPT - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
__IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
__IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
__IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
__IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
__I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
__I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
} GPT_Type;
/* ----------------------------------------------------------------------------
-- GPT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Register_Masks GPT Register Masks
* @{
*/
/*! @name CR - GPT Control Register */
/*! @{ */
#define GPT_CR_EN_MASK (0x1U)
#define GPT_CR_EN_SHIFT (0U)
#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define GPT_CR_ENMOD_MASK (0x2U)
#define GPT_CR_ENMOD_SHIFT (1U)
#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define GPT_CR_DBGEN_MASK (0x4U)
#define GPT_CR_DBGEN_SHIFT (2U)
#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define GPT_CR_WAITEN_MASK (0x8U)
#define GPT_CR_WAITEN_SHIFT (3U)
#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define GPT_CR_DOZEEN_MASK (0x10U)
#define GPT_CR_DOZEEN_SHIFT (4U)
#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define GPT_CR_STOPEN_MASK (0x20U)
#define GPT_CR_STOPEN_SHIFT (5U)
#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define GPT_CR_CLKSRC_MASK (0x1C0U)
#define GPT_CR_CLKSRC_SHIFT (6U)
#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define GPT_CR_FRR_MASK (0x200U)
#define GPT_CR_FRR_SHIFT (9U)
#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define GPT_CR_EN_24M_MASK (0x400U)
#define GPT_CR_EN_24M_SHIFT (10U)
#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define GPT_CR_SWR_MASK (0x8000U)
#define GPT_CR_SWR_SHIFT (15U)
#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define GPT_CR_IM1_MASK (0x30000U)
#define GPT_CR_IM1_SHIFT (16U)
#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define GPT_CR_IM2_MASK (0xC0000U)
#define GPT_CR_IM2_SHIFT (18U)
#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define GPT_CR_OM1_MASK (0x700000U)
#define GPT_CR_OM1_SHIFT (20U)
#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define GPT_CR_OM2_MASK (0x3800000U)
#define GPT_CR_OM2_SHIFT (23U)
#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define GPT_CR_OM3_MASK (0x1C000000U)
#define GPT_CR_OM3_SHIFT (26U)
#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define GPT_CR_FO1_MASK (0x20000000U)
#define GPT_CR_FO1_SHIFT (29U)
#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define GPT_CR_FO2_MASK (0x40000000U)
#define GPT_CR_FO2_SHIFT (30U)
#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define GPT_CR_FO3_MASK (0x80000000U)
#define GPT_CR_FO3_SHIFT (31U)
#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
/*! @} */
/*! @name PR - GPT Prescaler Register */
/*! @{ */
#define GPT_PR_PRESCALER_MASK (0xFFFU)
#define GPT_PR_PRESCALER_SHIFT (0U)
#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define GPT_PR_PRESCALER24M_MASK (0xF000U)
#define GPT_PR_PRESCALER24M_SHIFT (12U)
#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
/*! @} */
/*! @name SR - GPT Status Register */
/*! @{ */
#define GPT_SR_OF1_MASK (0x1U)
#define GPT_SR_OF1_SHIFT (0U)
#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define GPT_SR_OF2_MASK (0x2U)
#define GPT_SR_OF2_SHIFT (1U)
#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define GPT_SR_OF3_MASK (0x4U)
#define GPT_SR_OF3_SHIFT (2U)
#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define GPT_SR_IF1_MASK (0x8U)
#define GPT_SR_IF1_SHIFT (3U)
#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define GPT_SR_IF2_MASK (0x10U)
#define GPT_SR_IF2_SHIFT (4U)
#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define GPT_SR_ROV_MASK (0x20U)
#define GPT_SR_ROV_SHIFT (5U)
#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
/*! @} */
/*! @name IR - GPT Interrupt Register */
/*! @{ */
#define GPT_IR_OF1IE_MASK (0x1U)
#define GPT_IR_OF1IE_SHIFT (0U)
#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define GPT_IR_OF2IE_MASK (0x2U)
#define GPT_IR_OF2IE_SHIFT (1U)
#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define GPT_IR_OF3IE_MASK (0x4U)
#define GPT_IR_OF3IE_SHIFT (2U)
#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define GPT_IR_IF1IE_MASK (0x8U)
#define GPT_IR_IF1IE_SHIFT (3U)
#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define GPT_IR_IF2IE_MASK (0x10U)
#define GPT_IR_IF2IE_SHIFT (4U)
#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define GPT_IR_ROVIE_MASK (0x20U)
#define GPT_IR_ROVIE_SHIFT (5U)
#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
/*! @} */
/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
/*! @{ */
#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
#define GPT_OCR_COMP_SHIFT (0U)
#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
/*! @} */
/* The count of GPT_OCR */
#define GPT_OCR_COUNT (3U)
/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
/*! @{ */
#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
#define GPT_ICR_CAPT_SHIFT (0U)
#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
/*! @} */
/* The count of GPT_ICR */
#define GPT_ICR_COUNT (2U)
/*! @name CNT - GPT Counter Register */
/*! @{ */
#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
#define GPT_CNT_COUNT_SHIFT (0U)
#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPT_Register_Masks */
/* GPT - Peripheral instance base addresses */
/** Peripheral GPT1 base address */
#define GPT1_BASE (0x401EC000u)
/** Peripheral GPT1 base pointer */
#define GPT1 ((GPT_Type *)GPT1_BASE)
/** Peripheral GPT2 base address */
#define GPT2_BASE (0x401F0000u)
/** Peripheral GPT2 base pointer */
#define GPT2 ((GPT_Type *)GPT2_BASE)
/** Array initializer of GPT peripheral base addresses */
#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
/** Array initializer of GPT peripheral base pointers */
#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
/** Interrupt vectors for the GPT peripheral type */
#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
/*!
* @}
*/ /* end of group GPT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
__O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_0[16];
__I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_1[16];
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
uint8_t RESERVED_2[36];
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
__I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
uint8_t RESERVED_3[16];
__I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_4[16];
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define I2S_VERID_FEATURE_MASK (0xFFFFU)
#define I2S_VERID_FEATURE_SHIFT (0U)
#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define I2S_VERID_MINOR_MASK (0xFF0000U)
#define I2S_VERID_MINOR_SHIFT (16U)
#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define I2S_VERID_MAJOR_MASK (0xFF000000U)
#define I2S_VERID_MAJOR_SHIFT (24U)
#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define I2S_PARAM_DATALINE_MASK (0xFU)
#define I2S_PARAM_DATALINE_SHIFT (0U)
#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define I2S_PARAM_FIFO_MASK (0xF00U)
#define I2S_PARAM_FIFO_SHIFT (8U)
#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define I2S_PARAM_FRAME_MASK (0xF0000U)
#define I2S_PARAM_FRAME_SHIFT (16U)
#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
/*! @} */
/*! @name TCSR - SAI Transmit Control Register */
/*! @{ */
#define I2S_TCSR_FRDE_MASK (0x1U)
#define I2S_TCSR_FRDE_SHIFT (0U)
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK (0x2U)
#define I2S_TCSR_FWDE_SHIFT (1U)
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK (0x100U)
#define I2S_TCSR_FRIE_SHIFT (8U)
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK (0x200U)
#define I2S_TCSR_FWIE_SHIFT (9U)
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK (0x400U)
#define I2S_TCSR_FEIE_SHIFT (10U)
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK (0x800U)
#define I2S_TCSR_SEIE_SHIFT (11U)
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK (0x1000U)
#define I2S_TCSR_WSIE_SHIFT (12U)
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK (0x10000U)
#define I2S_TCSR_FRF_SHIFT (16U)
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK (0x20000U)
#define I2S_TCSR_FWF_SHIFT (17U)
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK (0x40000U)
#define I2S_TCSR_FEF_SHIFT (18U)
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK (0x80000U)
#define I2S_TCSR_SEF_SHIFT (19U)
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK (0x100000U)
#define I2S_TCSR_WSF_SHIFT (20U)
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK (0x1000000U)
#define I2S_TCSR_SR_SHIFT (24U)
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK (0x2000000U)
#define I2S_TCSR_FR_SHIFT (25U)
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK (0x10000000U)
#define I2S_TCSR_BCE_SHIFT (28U)
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT (29U)
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT (30U)
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK (0x80000000U)
#define I2S_TCSR_TE_SHIFT (31U)
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */
/*! @name TCR1 - SAI Transmit Configuration 1 Register */
/*! @{ */
#define I2S_TCR1_TFW_MASK (0x1FU)
#define I2S_TCR1_TFW_SHIFT (0U)
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */
/*! @name TCR2 - SAI Transmit Configuration 2 Register */
/*! @{ */
#define I2S_TCR2_DIV_MASK (0xFFU)
#define I2S_TCR2_DIV_SHIFT (0U)
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BCD_MASK (0x1000000U)
#define I2S_TCR2_BCD_SHIFT (24U)
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK (0x2000000U)
#define I2S_TCR2_BCP_SHIFT (25U)
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT (26U)
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK (0x10000000U)
#define I2S_TCR2_BCI_SHIFT (28U)
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK (0x20000000U)
#define I2S_TCR2_BCS_SHIFT (29U)
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK (0xC0000000U)
#define I2S_TCR2_SYNC_SHIFT (30U)
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @} */
/*! @name TCR3 - SAI Transmit Configuration 3 Register */
/*! @{ */
#define I2S_TCR3_WDFL_MASK (0x1FU)
#define I2S_TCR3_WDFL_SHIFT (0U)
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK (0xF0000U)
#define I2S_TCR3_TCE_SHIFT (16U)
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define I2S_TCR3_CFR_MASK (0xF000000U)
#define I2S_TCR3_CFR_SHIFT (24U)
#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
/*! @} */
/*! @name TCR4 - SAI Transmit Configuration 4 Register */
/*! @{ */
#define I2S_TCR4_FSD_MASK (0x1U)
#define I2S_TCR4_FSD_SHIFT (0U)
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK (0x2U)
#define I2S_TCR4_FSP_SHIFT (1U)
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK (0x4U)
#define I2S_TCR4_ONDEM_SHIFT (2U)
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK (0x8U)
#define I2S_TCR4_FSE_SHIFT (3U)
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK (0x10U)
#define I2S_TCR4_MF_SHIFT (4U)
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define I2S_TCR4_CHMOD_MASK (0x20U)
#define I2S_TCR4_CHMOD_SHIFT (5U)
#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define I2S_TCR4_SYWD_MASK (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT (8U)
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
#define I2S_TCR4_FRSZ_SHIFT (16U)
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT (24U)
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCOMB_MASK (0xC000000U)
#define I2S_TCR4_FCOMB_SHIFT (26U)
#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define I2S_TCR4_FCONT_MASK (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT (28U)
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */
/*! @name TCR5 - SAI Transmit Configuration 5 Register */
/*! @{ */
#define I2S_TCR5_FBT_MASK (0x1F00U)
#define I2S_TCR5_FBT_SHIFT (8U)
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT (16U)
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT (24U)
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */
/*! @name TDR - SAI Transmit Data Register */
/*! @{ */
#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT (0U)
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */
/* The count of I2S_TDR */
#define I2S_TDR_COUNT (4U)
/*! @name TFR - SAI Transmit FIFO Register */
/*! @{ */
#define I2S_TFR_RFP_MASK (0x3FU)
#define I2S_TFR_RFP_SHIFT (0U)
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK (0x3F0000U)
#define I2S_TFR_WFP_SHIFT (16U)
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define I2S_TFR_WCP_MASK (0x80000000U)
#define I2S_TFR_WCP_SHIFT (31U)
#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
/*! @} */
/* The count of I2S_TFR */
#define I2S_TFR_COUNT (4U)
/*! @name TMR - SAI Transmit Mask Register */
/*! @{ */
#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
#define I2S_TMR_TWM_SHIFT (0U)
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @} */
/*! @name RCSR - SAI Receive Control Register */
/*! @{ */
#define I2S_RCSR_FRDE_MASK (0x1U)
#define I2S_RCSR_FRDE_SHIFT (0U)
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK (0x2U)
#define I2S_RCSR_FWDE_SHIFT (1U)
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK (0x100U)
#define I2S_RCSR_FRIE_SHIFT (8U)
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK (0x200U)
#define I2S_RCSR_FWIE_SHIFT (9U)
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK (0x400U)
#define I2S_RCSR_FEIE_SHIFT (10U)
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK (0x800U)
#define I2S_RCSR_SEIE_SHIFT (11U)
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK (0x1000U)
#define I2S_RCSR_WSIE_SHIFT (12U)
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK (0x10000U)
#define I2S_RCSR_FRF_SHIFT (16U)
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK (0x20000U)
#define I2S_RCSR_FWF_SHIFT (17U)
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK (0x40000U)
#define I2S_RCSR_FEF_SHIFT (18U)
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK (0x80000U)
#define I2S_RCSR_SEF_SHIFT (19U)
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK (0x100000U)
#define I2S_RCSR_WSF_SHIFT (20U)
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK (0x1000000U)
#define I2S_RCSR_SR_SHIFT (24U)
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK (0x2000000U)
#define I2S_RCSR_FR_SHIFT (25U)
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK (0x10000000U)
#define I2S_RCSR_BCE_SHIFT (28U)
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT (29U)
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT (30U)
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK (0x80000000U)
#define I2S_RCSR_RE_SHIFT (31U)
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */
/*! @name RCR1 - SAI Receive Configuration 1 Register */
/*! @{ */
#define I2S_RCR1_RFW_MASK (0x1FU)
#define I2S_RCR1_RFW_SHIFT (0U)
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */
/*! @name RCR2 - SAI Receive Configuration 2 Register */
/*! @{ */
#define I2S_RCR2_DIV_MASK (0xFFU)
#define I2S_RCR2_DIV_SHIFT (0U)
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BCD_MASK (0x1000000U)
#define I2S_RCR2_BCD_SHIFT (24U)
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK (0x2000000U)
#define I2S_RCR2_BCP_SHIFT (25U)
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT (26U)
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK (0x10000000U)
#define I2S_RCR2_BCI_SHIFT (28U)
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK (0x20000000U)
#define I2S_RCR2_BCS_SHIFT (29U)
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK (0xC0000000U)
#define I2S_RCR2_SYNC_SHIFT (30U)
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @} */
/*! @name RCR3 - SAI Receive Configuration 3 Register */
/*! @{ */
#define I2S_RCR3_WDFL_MASK (0x1FU)
#define I2S_RCR3_WDFL_SHIFT (0U)
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK (0xF0000U)
#define I2S_RCR3_RCE_SHIFT (16U)
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define I2S_RCR3_CFR_MASK (0xF000000U)
#define I2S_RCR3_CFR_SHIFT (24U)
#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
/*! @} */
/*! @name RCR4 - SAI Receive Configuration 4 Register */
/*! @{ */
#define I2S_RCR4_FSD_MASK (0x1U)
#define I2S_RCR4_FSD_SHIFT (0U)
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK (0x2U)
#define I2S_RCR4_FSP_SHIFT (1U)
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK (0x4U)
#define I2S_RCR4_ONDEM_SHIFT (2U)
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK (0x8U)
#define I2S_RCR4_FSE_SHIFT (3U)
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK (0x10U)
#define I2S_RCR4_MF_SHIFT (4U)
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT (8U)
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
#define I2S_RCR4_FRSZ_SHIFT (16U)
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT (24U)
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCOMB_MASK (0xC000000U)
#define I2S_RCR4_FCOMB_SHIFT (26U)
#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define I2S_RCR4_FCONT_MASK (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT (28U)
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */
/*! @name RCR5 - SAI Receive Configuration 5 Register */
/*! @{ */
#define I2S_RCR5_FBT_MASK (0x1F00U)
#define I2S_RCR5_FBT_SHIFT (8U)
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT (16U)
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT (24U)
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */
/*! @name RDR - SAI Receive Data Register */
/*! @{ */
#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT (0U)
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */
/* The count of I2S_RDR */
#define I2S_RDR_COUNT (4U)
/*! @name RFR - SAI Receive FIFO Register */
/*! @{ */
#define I2S_RFR_RFP_MASK (0x3FU)
#define I2S_RFR_RFP_SHIFT (0U)
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define I2S_RFR_RCP_MASK (0x8000U)
#define I2S_RFR_RCP_SHIFT (15U)
#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define I2S_RFR_WFP_MASK (0x3F0000U)
#define I2S_RFR_WFP_SHIFT (16U)
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */
/* The count of I2S_RFR */
#define I2S_RFR_COUNT (4U)
/*! @name RMR - SAI Receive Mask Register */
/*! @{ */
#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
#define I2S_RMR_RWM_SHIFT (0U)
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral SAI1 base address */
#define SAI1_BASE (0x40384000u)
/** Peripheral SAI1 base pointer */
#define SAI1 ((I2S_Type *)SAI1_BASE)
/** Peripheral SAI2 base address */
#define SAI2_BASE (0x40388000u)
/** Peripheral SAI2 base pointer */
#define SAI2 ((I2S_Type *)SAI2_BASE)
/** Peripheral SAI3 base address */
#define SAI3_BASE (0x4038C000u)
/** Peripheral SAI3 base pointer */
#define SAI3 ((I2S_Type *)SAI3_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
* @{
*/
/** IOMUXC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[20];
__IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */
__IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */
__IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */
} IOMUXC_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */
/*! @{ */
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
/*! @} */
/* The count of IOMUXC_SW_MUX_CTL_PAD */
#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */
/*! @{ */
#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
/*! @} */
/* The count of IOMUXC_SW_PAD_CTL_PAD */
#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */
/*! @{ */
#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
/*! @} */
/* The count of IOMUXC_SELECT_INPUT */
#define IOMUXC_SELECT_INPUT_COUNT (154U)
/*!
* @}
*/ /* end of group IOMUXC_Register_Masks */
/* IOMUXC - Peripheral instance base addresses */
/** Peripheral IOMUXC base address */
#define IOMUXC_BASE (0x401F8000u)
/** Peripheral IOMUXC base pointer */
#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
/** Array initializer of IOMUXC peripheral base addresses */
#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
/** Array initializer of IOMUXC peripheral base pointers */
#define IOMUXC_BASE_PTRS { IOMUXC }
/*!
* @}
*/ /* end of group IOMUXC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_GPR - Register Layout Typedef */
typedef struct {
uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
__IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
__IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */
__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */
__IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */
__IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */
__IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */
uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */
__IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */
__IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */
__IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */
__IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */
__IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */
uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */
__IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */
__IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */
__IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */
__IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */
__IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */
__IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */
__IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */
__IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */
__IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */
__IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */
} IOMUXC_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
* @{
*/
/*! @name GPR1 - GPR1 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
/*! @} */
/*! @name GPR2 - GPR2 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
/*! @} */
/*! @name GPR3 - GPR3 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
/*! @} */
/*! @name GPR4 - GPR4 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
/*! @} */
/*! @name GPR5 - GPR5 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
/*! @} */
/*! @name GPR6 - GPR6 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
/*! @} */
/*! @name GPR7 - GPR7 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
/*! @} */
/*! @name GPR8 - GPR8 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
/*! @} */
/*! @name GPR10 - GPR10 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
/*! @} */
/*! @name GPR11 - GPR11 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (0x30000U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT (16U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (0xC0000U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT (18U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (0x300000U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT (20U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (0xC00000U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT (22U)
#define IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK)
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xF000000U)
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT (24U)
#define IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK)
/*! @} */
/*! @name GPR12 - GPR12 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
/*! @} */
/*! @name GPR13 - GPR13 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
/*! @} */
/*! @name GPR14 - GPR14 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
/*! @} */
/*! @name GPR16 - GPR16 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK (0xFFFFFF80U)
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT (7U)
#define IOMUXC_GPR_GPR16_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR16_CM7_INIT_VTOR_MASK)
/*! @} */
/*! @name GPR17 - GPR17 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
/*! @} */
/*! @name GPR18 - GPR18 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
/*! @} */
/*! @name GPR19 - GPR19 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
/*! @} */
/*! @name GPR20 - GPR20 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
/*! @} */
/*! @name GPR21 - GPR21 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
/*! @} */
/*! @name GPR22 - GPR22 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
/*! @} */
/*! @name GPR23 - GPR23 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R1_TOP_MASK)
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
/*! @} */
/*! @name GPR24 - GPR24 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT (3U)
#define IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R2_BOT_MASK)
/*! @} */
/*! @name GPR25 - GPR25 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_GPR_Register_Masks */
/* IOMUXC_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_GPR base address */
#define IOMUXC_GPR_BASE (0x400AC000u)
/** Peripheral IOMUXC_GPR base pointer */
#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
/** Array initializer of IOMUXC_GPR peripheral base addresses */
#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
/** Array initializer of IOMUXC_GPR peripheral base pointers */
#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
/*!
* @}
*/ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
* @{
*/
/** IOMUXC_SNVS - Register Layout Typedef */
typedef struct {
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */
__IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */
__IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */
} IOMUXC_SNVS_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_SNVS_Register_Masks */
/* IOMUXC_SNVS - Peripheral instance base addresses */
/** Peripheral IOMUXC_SNVS base address */
#define IOMUXC_SNVS_BASE (0x400A8000u)
/** Peripheral IOMUXC_SNVS base pointer */
#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
/** Array initializer of IOMUXC_SNVS peripheral base addresses */
#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
/** Array initializer of IOMUXC_SNVS peripheral base pointers */
#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
/*!
* @}
*/ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_SNVS_GPR - Register Layout Typedef */
typedef struct {
uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
} IOMUXC_SNVS_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
* @{
*/
/*! @name GPR3 - GPR3 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_SNVS_GPR base address */
#define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
/** Peripheral IOMUXC_SNVS_GPR base pointer */
#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
/*!
* @}
*/ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- KPP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
* @{
*/
/** KPP - Register Layout Typedef */
typedef struct {
__IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */
__IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */
__IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */
__IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */
} KPP_Type;
/* ----------------------------------------------------------------------------
-- KPP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup KPP_Register_Masks KPP Register Masks
* @{
*/
/*! @name KPCR - Keypad Control Register */
/*! @{ */
#define KPP_KPCR_KRE_MASK (0xFFU)
#define KPP_KPCR_KRE_SHIFT (0U)
#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
#define KPP_KPCR_KCO_MASK (0xFF00U)
#define KPP_KPCR_KCO_SHIFT (8U)
#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
/*! @} */
/*! @name KPSR - Keypad Status Register */
/*! @{ */
#define KPP_KPSR_KPKD_MASK (0x1U)
#define KPP_KPSR_KPKD_SHIFT (0U)
#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
#define KPP_KPSR_KPKR_MASK (0x2U)
#define KPP_KPSR_KPKR_SHIFT (1U)
#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
#define KPP_KPSR_KDSC_MASK (0x4U)
#define KPP_KPSR_KDSC_SHIFT (2U)
#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
#define KPP_KPSR_KRSS_MASK (0x8U)
#define KPP_KPSR_KRSS_SHIFT (3U)
#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
#define KPP_KPSR_KDIE_MASK (0x100U)
#define KPP_KPSR_KDIE_SHIFT (8U)
#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
#define KPP_KPSR_KRIE_MASK (0x200U)
#define KPP_KPSR_KRIE_SHIFT (9U)
#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
/*! @} */
/*! @name KDDR - Keypad Data Direction Register */
/*! @{ */
#define KPP_KDDR_KRDD_MASK (0xFFU)
#define KPP_KDDR_KRDD_SHIFT (0U)
#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
#define KPP_KDDR_KCDD_MASK (0xFF00U)
#define KPP_KDDR_KCDD_SHIFT (8U)
#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
/*! @} */
/*! @name KPDR - Keypad Data Register */
/*! @{ */
#define KPP_KPDR_KRD_MASK (0xFFU)
#define KPP_KPDR_KRD_SHIFT (0U)
#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
#define KPP_KPDR_KCD_MASK (0xFF00U)
#define KPP_KPDR_KCD_SHIFT (8U)
#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group KPP_Register_Masks */
/* KPP - Peripheral instance base addresses */
/** Peripheral KPP base address */
#define KPP_BASE (0x401FC000u)
/** Peripheral KPP base pointer */
#define KPP ((KPP_Type *)KPP_BASE)
/** Array initializer of KPP peripheral base addresses */
#define KPP_BASE_ADDRS { KPP_BASE }
/** Array initializer of KPP peripheral base pointers */
#define KPP_BASE_PTRS { KPP }
/** Interrupt vectors for the KPP peripheral type */
#define KPP_IRQS { KPP_IRQn }
/*!
* @}
*/ /* end of group KPP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LCDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
* @{
*/
/** LCDIF - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */
__IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */
__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */
__IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */
__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */
__IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */
__IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */
__IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */
__IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */
__IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
uint8_t RESERVED_0[12];
__IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
uint8_t RESERVED_2[28];
__IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
__IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
__IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
__IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
uint8_t RESERVED_3[12];
__IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
uint8_t RESERVED_4[12];
__IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
uint8_t RESERVED_5[12];
__IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
uint8_t RESERVED_6[220];
__IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */
uint8_t RESERVED_7[12];
__IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */
uint8_t RESERVED_8[12];
__I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */
uint8_t RESERVED_9[76];
__IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */
uint8_t RESERVED_10[380];
__IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
__IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
__IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
__IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
__IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
__IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
__IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
__IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
__IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
__IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
__IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
__IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
uint8_t RESERVED_11[1104];
struct { /* offset: 0x800, array step: 0x40 */
__IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
uint8_t RESERVED_2[28];
} PIGEON[12];
__IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */
uint8_t RESERVED_12[12];
__IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */
uint8_t RESERVED_13[12];
__IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */
uint8_t RESERVED_14[12];
__IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */
uint8_t RESERVED_15[12];
__IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */
} LCDIF_Type;
/* ----------------------------------------------------------------------------
-- LCDIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Register_Masks LCDIF Register Masks
* @{
*/
/*! @name CTRL - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_RUN_MASK (0x1U)
#define LCDIF_CTRL_RUN_SHIFT (0U)
#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
#define LCDIF_CTRL_MASTER_MASK (0x20U)
#define LCDIF_CTRL_MASTER_SHIFT (5U)
#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name CTRL1 - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_SET - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_CLR - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_TOG - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL2 - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_SET - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_CLR - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_TOG - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/*! @} */
/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
/*! @{ */
#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
/*! @} */
/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
/*! @{ */
#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
/*! @} */
/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
/*! @{ */
#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
/*! @} */
/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_RSRVD2_MASK (0xE0000000U)
#define LCDIF_VDCTRL0_RSRVD2_SHIFT (29U)
#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xE0000000U)
#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (29U)
#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xE0000000U)
#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (29U)
#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xE0000000U)
#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (29U)
#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
/*! @{ */
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
/*! @} */
/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
/*! @{ */
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
/*! @} */
/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
/*! @{ */
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/*! @} */
/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
/*! @{ */
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
/*! @} */
/*! @name BM_ERROR_STAT - Bus Master Error Status Register */
/*! @{ */
#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
/*! @} */
/*! @name CRC_STAT - CRC Status Register */
/*! @{ */
#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
/*! @} */
/*! @name STAT - LCD Interface Status Register */
/*! @{ */
#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
#define LCDIF_STAT_RSRVD0_SHIFT (9U)
#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
#define LCDIF_STAT_DMA_REQ_SHIFT (30U)
#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
#define LCDIF_STAT_PRESENT_SHIFT (31U)
#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
/*! @} */
/*! @name THRES - LCDIF Threshold Register */
/*! @{ */
#define LCDIF_THRES_PANIC_MASK (0x1FFU)
#define LCDIF_THRES_PANIC_SHIFT (0U)
#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
#define LCDIF_THRES_RSRVD1_SHIFT (9U)
#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
#define LCDIF_THRES_RSRVD2_SHIFT (25U)
#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
/*! @} */
/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEON_0 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_0_EN_MASK (0x1U)
#define LCDIF_PIGEON_0_EN_SHIFT (0U)
#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
#define LCDIF_PIGEON_0_POL_MASK (0x2U)
#define LCDIF_PIGEON_0_POL_SHIFT (1U)
#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_0 */
#define LCDIF_PIGEON_0_COUNT (12U)
/*! @name PIGEON_1 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_1 */
#define LCDIF_PIGEON_1_COUNT (12U)
/*! @name PIGEON_2 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
#define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_2 */
#define LCDIF_PIGEON_2_COUNT (12U)
/*! @name LUT_CTRL - Lookup Table Data Register. */
/*! @{ */
#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
/*! @} */
/*! @name LUT0_ADDR - Lookup Table Control Register. */
/*! @{ */
#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
/*! @} */
/*! @name LUT0_DATA - Lookup Table Data Register. */
/*! @{ */
#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
#define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
/*! @} */
/*! @name LUT1_ADDR - Lookup Table Control Register. */
/*! @{ */
#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
/*! @} */
/*! @name LUT1_DATA - Lookup Table Data Register. */
/*! @{ */
#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
#define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LCDIF_Register_Masks */
/* LCDIF - Peripheral instance base addresses */
/** Peripheral LCDIF base address */
#define LCDIF_BASE (0x402B8000u)
/** Peripheral LCDIF base pointer */
#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
/** Array initializer of LCDIF peripheral base addresses */
#define LCDIF_BASE_ADDRS { LCDIF_BASE }
/** Array initializer of LCDIF peripheral base pointers */
#define LCDIF_BASE_PTRS { LCDIF }
/** Interrupt vectors for the LCDIF peripheral type */
#define LCDIF_IRQ0_IRQS { LCDIF_IRQn }
/*!
* @}
*/ /* end of group LCDIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPI2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
* @{
*/
/** LPI2C - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */
__IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */
__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */
__IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */
__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */
__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */
__IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */
__IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */
uint8_t RESERVED_3[4];
__IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */
uint8_t RESERVED_4[4];
__IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */
__I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */
__O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */
uint8_t RESERVED_5[12];
__I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */
uint8_t RESERVED_6[156];
__IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */
__IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */
__IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */
__IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */
uint8_t RESERVED_7[4];
__IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */
__IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */
uint8_t RESERVED_8[20];
__IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */
uint8_t RESERVED_9[12];
__I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */
__IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */
uint8_t RESERVED_10[8];
__O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */
uint8_t RESERVED_11[12];
__I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */
} LPI2C_Type;
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT (0U)
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT (16U)
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT (24U)
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */
/*! @name MCR - Master Control Register */
/*! @{ */
#define LPI2C_MCR_MEN_MASK (0x1U)
#define LPI2C_MCR_MEN_SHIFT (0U)
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK (0x2U)
#define LPI2C_MCR_RST_SHIFT (1U)
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT (2U)
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT (3U)
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK (0x100U)
#define LPI2C_MCR_RTF_SHIFT (8U)
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK (0x200U)
#define LPI2C_MCR_RRF_SHIFT (9U)
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */
/*! @name MSR - Master Status Register */
/*! @{ */
#define LPI2C_MSR_TDF_MASK (0x1U)
#define LPI2C_MSR_TDF_SHIFT (0U)
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK (0x2U)
#define LPI2C_MSR_RDF_SHIFT (1U)
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK (0x100U)
#define LPI2C_MSR_EPF_SHIFT (8U)
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK (0x200U)
#define LPI2C_MSR_SDF_SHIFT (9U)
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK (0x400U)
#define LPI2C_MSR_NDF_SHIFT (10U)
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK (0x800U)
#define LPI2C_MSR_ALF_SHIFT (11U)
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK (0x1000U)
#define LPI2C_MSR_FEF_SHIFT (12U)
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT (13U)
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK (0x4000U)
#define LPI2C_MSR_DMF_SHIFT (14U)
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT (24U)
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT (25U)
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */
/*! @name MIER - Master Interrupt Enable Register */
/*! @{ */
#define LPI2C_MIER_TDIE_MASK (0x1U)
#define LPI2C_MIER_TDIE_SHIFT (0U)
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK (0x2U)
#define LPI2C_MIER_RDIE_SHIFT (1U)
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK (0x100U)
#define LPI2C_MIER_EPIE_SHIFT (8U)
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK (0x200U)
#define LPI2C_MIER_SDIE_SHIFT (9U)
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK (0x400U)
#define LPI2C_MIER_NDIE_SHIFT (10U)
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK (0x800U)
#define LPI2C_MIER_ALIE_SHIFT (11U)
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT (12U)
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT (13U)
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT (14U)
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @} */
/*! @name MDER - Master DMA Enable Register */
/*! @{ */
#define LPI2C_MDER_TDDE_MASK (0x1U)
#define LPI2C_MDER_TDDE_SHIFT (0U)
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK (0x2U)
#define LPI2C_MDER_RDDE_SHIFT (1U)
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */
/*! @name MCFGR0 - Master Configuration Register 0 */
/*! @{ */
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @} */
/*! @name MCFGR1 - Master Configuration Register 1 */
/*! @{ */
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
/*! @} */
/*! @name MCFGR2 - Master Configuration Register 2 */
/*! @{ */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */
/*! @name MCFGR3 - Master Configuration Register 3 */
/*! @{ */
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */
/*! @name MDMR - Master Data Match Register */
/*! @{ */
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT (16U)
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */
/*! @name MCCR0 - Master Clock Configuration Register 0 */
/*! @{ */
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */
/*! @name MCCR1 - Master Clock Configuration Register 1 */
/*! @{ */
#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */
/*! @name MFCR - Master FIFO Control Register */
/*! @{ */
#define LPI2C_MFCR_TXWATER_MASK (0x3U)
#define LPI2C_MFCR_TXWATER_SHIFT (0U)
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
#define LPI2C_MFCR_RXWATER_SHIFT (16U)
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @} */
/*! @name MFSR - Master FIFO Status Register */
/*! @{ */
#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @} */
/*! @name MTDR - Master Transmit Data Register */
/*! @{ */
#define LPI2C_MTDR_DATA_MASK (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT (0U)
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK (0x700U)
#define LPI2C_MTDR_CMD_SHIFT (8U)
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */
/*! @name MRDR - Master Receive Data Register */
/*! @{ */
#define LPI2C_MRDR_DATA_MASK (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT (0U)
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */
/*! @name SCR - Slave Control Register */
/*! @{ */
#define LPI2C_SCR_SEN_MASK (0x1U)
#define LPI2C_SCR_SEN_SHIFT (0U)
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK (0x2U)
#define LPI2C_SCR_RST_SHIFT (1U)
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT (4U)
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT (5U)
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK (0x100U)
#define LPI2C_SCR_RTF_SHIFT (8U)
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK (0x200U)
#define LPI2C_SCR_RRF_SHIFT (9U)
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */
/*! @name SSR - Slave Status Register */
/*! @{ */
#define LPI2C_SSR_TDF_MASK (0x1U)
#define LPI2C_SSR_TDF_SHIFT (0U)
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK (0x2U)
#define LPI2C_SSR_RDF_SHIFT (1U)
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK (0x4U)
#define LPI2C_SSR_AVF_SHIFT (2U)
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK (0x8U)
#define LPI2C_SSR_TAF_SHIFT (3U)
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK (0x100U)
#define LPI2C_SSR_RSF_SHIFT (8U)
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK (0x200U)
#define LPI2C_SSR_SDF_SHIFT (9U)
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK (0x400U)
#define LPI2C_SSR_BEF_SHIFT (10U)
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK (0x800U)
#define LPI2C_SSR_FEF_SHIFT (11U)
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT (12U)
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT (13U)
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK (0x4000U)
#define LPI2C_SSR_GCF_SHIFT (14U)
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK (0x8000U)
#define LPI2C_SSR_SARF_SHIFT (15U)
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT (24U)
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT (25U)
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */
/*! @name SIER - Slave Interrupt Enable Register */
/*! @{ */
#define LPI2C_SIER_TDIE_MASK (0x1U)
#define LPI2C_SIER_TDIE_SHIFT (0U)
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK (0x2U)
#define LPI2C_SIER_RDIE_SHIFT (1U)
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK (0x4U)
#define LPI2C_SIER_AVIE_SHIFT (2U)
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK (0x8U)
#define LPI2C_SIER_TAIE_SHIFT (3U)
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK (0x100U)
#define LPI2C_SIER_RSIE_SHIFT (8U)
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK (0x200U)
#define LPI2C_SIER_SDIE_SHIFT (9U)
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK (0x400U)
#define LPI2C_SIER_BEIE_SHIFT (10U)
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK (0x800U)
#define LPI2C_SIER_FEIE_SHIFT (11U)
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT (12U)
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1F_MASK (0x2000U)
#define LPI2C_SIER_AM1F_SHIFT (13U)
#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
#define LPI2C_SIER_GCIE_MASK (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT (14U)
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT (15U)
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */
/*! @name SDER - Slave DMA Enable Register */
/*! @{ */
#define LPI2C_SDER_TDDE_MASK (0x1U)
#define LPI2C_SDER_TDDE_SHIFT (0U)
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK (0x2U)
#define LPI2C_SDER_RDDE_SHIFT (1U)
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK (0x4U)
#define LPI2C_SDER_AVDE_SHIFT (2U)
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
/*! @} */
/*! @name SCFGR1 - Slave Configuration Register 1 */
/*! @{ */
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @} */
/*! @name SCFGR2 - Slave Configuration Register 2 */
/*! @{ */
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */
/*! @name SAMR - Slave Address Match Register */
/*! @{ */
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */
/*! @name SASR - Slave Address Status Register */
/*! @{ */
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT (0U)
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK (0x4000U)
#define LPI2C_SASR_ANV_SHIFT (14U)
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */
/*! @name STAR - Slave Transmit ACK Register */
/*! @{ */
#define LPI2C_STAR_TXNACK_MASK (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT (0U)
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */
/*! @name STDR - Slave Transmit Data Register */
/*! @{ */
#define LPI2C_STDR_DATA_MASK (0xFFU)
#define LPI2C_STDR_DATA_SHIFT (0U)
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */
/*! @name SRDR - Slave Receive Data Register */
/*! @{ */
#define LPI2C_SRDR_DATA_MASK (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT (0U)
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT (15U)
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPI2C_Register_Masks */
/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE (0x403F0000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
/** Peripheral LPI2C2 base address */
#define LPI2C2_BASE (0x403F4000u)
/** Peripheral LPI2C2 base pointer */
#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
/** Peripheral LPI2C3 base address */
#define LPI2C3_BASE (0x403F8000u)
/** Peripheral LPI2C3 base pointer */
#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
/** Peripheral LPI2C4 base address */
#define LPI2C4_BASE (0x403FC000u)
/** Peripheral LPI2C4 base pointer */
#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
/*!
* @}
*/ /* end of group LPI2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
* @{
*/
/** LPSPI - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t CR; /**< Control Register, offset: 0x10 */
__IO uint32_t SR; /**< Status Register, offset: 0x14 */
__IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */
__IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */
__IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */
__IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */
__IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */
uint8_t RESERVED_2[8];
__IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */
uint8_t RESERVED_3[20];
__IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */
__I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */
__IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */
__O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */
uint8_t RESERVED_4[8];
__I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */
__I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */
} LPSPI_Type;
/* ----------------------------------------------------------------------------
-- LPSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT (0U)
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT (16U)
#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT (24U)
#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
/*! @} */
/*! @name CR - Control Register */
/*! @{ */
#define LPSPI_CR_MEN_MASK (0x1U)
#define LPSPI_CR_MEN_SHIFT (0U)
#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define LPSPI_CR_RST_MASK (0x2U)
#define LPSPI_CR_RST_SHIFT (1U)
#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define LPSPI_CR_DOZEN_MASK (0x4U)
#define LPSPI_CR_DOZEN_SHIFT (2U)
#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define LPSPI_CR_DBGEN_MASK (0x8U)
#define LPSPI_CR_DBGEN_SHIFT (3U)
#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define LPSPI_CR_RTF_MASK (0x100U)
#define LPSPI_CR_RTF_SHIFT (8U)
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define LPSPI_CR_RRF_MASK (0x200U)
#define LPSPI_CR_RRF_SHIFT (9U)
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */
/*! @name SR - Status Register */
/*! @{ */
#define LPSPI_SR_TDF_MASK (0x1U)
#define LPSPI_SR_TDF_SHIFT (0U)
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define LPSPI_SR_RDF_MASK (0x2U)
#define LPSPI_SR_RDF_SHIFT (1U)
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define LPSPI_SR_WCF_MASK (0x100U)
#define LPSPI_SR_WCF_SHIFT (8U)
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define LPSPI_SR_FCF_MASK (0x200U)
#define LPSPI_SR_FCF_SHIFT (9U)
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define LPSPI_SR_TCF_MASK (0x400U)
#define LPSPI_SR_TCF_SHIFT (10U)
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define LPSPI_SR_TEF_MASK (0x800U)
#define LPSPI_SR_TEF_SHIFT (11U)
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define LPSPI_SR_REF_MASK (0x1000U)
#define LPSPI_SR_REF_SHIFT (12U)
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define LPSPI_SR_DMF_MASK (0x2000U)
#define LPSPI_SR_DMF_SHIFT (13U)
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define LPSPI_SR_MBF_MASK (0x1000000U)
#define LPSPI_SR_MBF_SHIFT (24U)
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */
/*! @name IER - Interrupt Enable Register */
/*! @{ */
#define LPSPI_IER_TDIE_MASK (0x1U)
#define LPSPI_IER_TDIE_SHIFT (0U)
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define LPSPI_IER_RDIE_MASK (0x2U)
#define LPSPI_IER_RDIE_SHIFT (1U)
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define LPSPI_IER_WCIE_MASK (0x100U)
#define LPSPI_IER_WCIE_SHIFT (8U)
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define LPSPI_IER_FCIE_MASK (0x200U)
#define LPSPI_IER_FCIE_SHIFT (9U)
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define LPSPI_IER_TCIE_MASK (0x400U)
#define LPSPI_IER_TCIE_SHIFT (10U)
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define LPSPI_IER_TEIE_MASK (0x800U)
#define LPSPI_IER_TEIE_SHIFT (11U)
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define LPSPI_IER_REIE_MASK (0x1000U)
#define LPSPI_IER_REIE_SHIFT (12U)
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define LPSPI_IER_DMIE_MASK (0x2000U)
#define LPSPI_IER_DMIE_SHIFT (13U)
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */
/*! @name DER - DMA Enable Register */
/*! @{ */
#define LPSPI_DER_TDDE_MASK (0x1U)
#define LPSPI_DER_TDDE_SHIFT (0U)
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define LPSPI_DER_RDDE_MASK (0x2U)
#define LPSPI_DER_RDDE_SHIFT (1U)
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
/*! @} */
/*! @name CFGR0 - Configuration Register 0 */
/*! @{ */
#define LPSPI_CFGR0_HREN_MASK (0x1U)
#define LPSPI_CFGR0_HREN_SHIFT (0U)
#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define LPSPI_CFGR0_RDMO_MASK (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT (9U)
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */
/*! @name CFGR1 - Configuration Register 1 */
/*! @{ */
#define LPSPI_CFGR1_MASTER_MASK (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT (0U)
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */
/*! @name DMR0 - Data Match Register 0 */
/*! @{ */
#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT (0U)
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */
/*! @name DMR1 - Data Match Register 1 */
/*! @{ */
#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT (0U)
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */
/*! @name CCR - Clock Configuration Register */
/*! @{ */
#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT (0U)
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_MASK (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT (8U)
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT (16U)
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT (24U)
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */
/*! @name FCR - FIFO Control Register */
/*! @{ */
#define LPSPI_FCR_TXWATER_MASK (0xFU)
#define LPSPI_FCR_TXWATER_SHIFT (0U)
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
#define LPSPI_FCR_RXWATER_SHIFT (16U)
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @} */
/*! @name FSR - FIFO Status Register */
/*! @{ */
#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @} */
/*! @name TCR - Transmit Command Register */
/*! @{ */
#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define LPSPI_TCR_WIDTH_MASK (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT (16U)
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define LPSPI_TCR_TXMSK_MASK (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT (18U)
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define LPSPI_TCR_RXMSK_MASK (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT (19U)
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define LPSPI_TCR_CONTC_MASK (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT (20U)
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define LPSPI_TCR_CONT_MASK (0x200000U)
#define LPSPI_TCR_CONT_SHIFT (21U)
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define LPSPI_TCR_BYSW_MASK (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT (22U)
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define LPSPI_TCR_LSBF_MASK (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT (23U)
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define LPSPI_TCR_PCS_MASK (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT (24U)
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT (27U)
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define LPSPI_TCR_CPHA_MASK (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT (30U)
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define LPSPI_TCR_CPOL_MASK (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT (31U)
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */
/*! @name TDR - Transmit Data Register */
/*! @{ */
#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT (0U)
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */
/*! @name RSR - Receive Status Register */
/*! @{ */
#define LPSPI_RSR_SOF_MASK (0x1U)
#define LPSPI_RSR_SOF_SHIFT (0U)
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */
/*! @name RDR - Receive Data Register */
/*! @{ */
#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT (0U)
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPSPI_Register_Masks */
/* LPSPI - Peripheral instance base addresses */
/** Peripheral LPSPI1 base address */
#define LPSPI1_BASE (0x40394000u)
/** Peripheral LPSPI1 base pointer */
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
/** Peripheral LPSPI2 base address */
#define LPSPI2_BASE (0x40398000u)
/** Peripheral LPSPI2 base pointer */
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
/** Peripheral LPSPI3 base address */
#define LPSPI3_BASE (0x4039C000u)
/** Peripheral LPSPI3 base pointer */
#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
/** Peripheral LPSPI4 base address */
#define LPSPI4_BASE (0x403A0000u)
/** Peripheral LPSPI4 base pointer */
#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
/*!
* @}
*/ /* end of group LPSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
__IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
__IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
__IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT (0U)
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define LPUART_VERID_MINOR_MASK (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT (16U)
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT (24U)
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT (0U)
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT (8U)
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */
/*! @name GLOBAL - LPUART Global Register */
/*! @{ */
#define LPUART_GLOBAL_RST_MASK (0x2U)
#define LPUART_GLOBAL_RST_SHIFT (1U)
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */
/*! @name PINCFG - LPUART Pin Configuration Register */
/*! @{ */
#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */
/*! @name BAUD - LPUART Baud Rate Register */
/*! @{ */
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT (0U)
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT (13U)
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT (18U)
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RIDMAE_MASK (0x100000U)
#define LPUART_BAUD_RIDMAE_SHIFT (20U)
#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
#define LPUART_BAUD_RDMAE_MASK (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT (21U)
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT (23U)
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT (24U)
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK (0x20000000U)
#define LPUART_BAUD_M10_SHIFT (29U)
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT (30U)
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT (31U)
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */
/*! @name STAT - LPUART Status Register */
/*! @{ */
#define LPUART_STAT_MA2F_MASK (0x4000U)
#define LPUART_STAT_MA2F_SHIFT (14U)
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK (0x8000U)
#define LPUART_STAT_MA1F_SHIFT (15U)
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK (0x10000U)
#define LPUART_STAT_PF_SHIFT (16U)
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK (0x20000U)
#define LPUART_STAT_FE_SHIFT (17U)
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK (0x40000U)
#define LPUART_STAT_NF_SHIFT (18U)
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK (0x80000U)
#define LPUART_STAT_OR_SHIFT (19U)
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK (0x100000U)
#define LPUART_STAT_IDLE_SHIFT (20U)
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK (0x200000U)
#define LPUART_STAT_RDRF_SHIFT (21U)
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK (0x400000U)
#define LPUART_STAT_TC_SHIFT (22U)
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK (0x800000U)
#define LPUART_STAT_TDRE_SHIFT (23U)
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK (0x1000000U)
#define LPUART_STAT_RAF_SHIFT (24U)
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT (25U)
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT (26U)
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT (27U)
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT (28U)
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT (29U)
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT (31U)
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */
/*! @name CTRL - LPUART Control Register */
/*! @{ */
#define LPUART_CTRL_PT_MASK (0x1U)
#define LPUART_CTRL_PT_SHIFT (0U)
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK (0x2U)
#define LPUART_CTRL_PE_SHIFT (1U)
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK (0x4U)
#define LPUART_CTRL_ILT_SHIFT (2U)
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK (0x8U)
#define LPUART_CTRL_WAKE_SHIFT (3U)
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK (0x10U)
#define LPUART_CTRL_M_SHIFT (4U)
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK (0x20U)
#define LPUART_CTRL_RSRC_SHIFT (5U)
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT (7U)
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_M7_MASK (0x800U)
#define LPUART_CTRL_M7_SHIFT (11U)
#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT (14U)
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT (15U)
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK (0x10000U)
#define LPUART_CTRL_SBK_SHIFT (16U)
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK (0x20000U)
#define LPUART_CTRL_RWU_SHIFT (17U)
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK (0x40000U)
#define LPUART_CTRL_RE_SHIFT (18U)
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK (0x80000U)
#define LPUART_CTRL_TE_SHIFT (19U)
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT (20U)
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK (0x200000U)
#define LPUART_CTRL_RIE_SHIFT (21U)
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT (22U)
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK (0x800000U)
#define LPUART_CTRL_TIE_SHIFT (23U)
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT (24U)
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT (25U)
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT (26U)
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT (27U)
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT (28U)
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT (29U)
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT (30U)
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT (31U)
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */
/*! @name DATA - LPUART Data Register */
/*! @{ */
#define LPUART_DATA_R0T0_MASK (0x1U)
#define LPUART_DATA_R0T0_SHIFT (0U)
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK (0x2U)
#define LPUART_DATA_R1T1_SHIFT (1U)
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK (0x4U)
#define LPUART_DATA_R2T2_SHIFT (2U)
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK (0x8U)
#define LPUART_DATA_R3T3_SHIFT (3U)
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK (0x10U)
#define LPUART_DATA_R4T4_SHIFT (4U)
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK (0x20U)
#define LPUART_DATA_R5T5_SHIFT (5U)
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK (0x40U)
#define LPUART_DATA_R6T6_SHIFT (6U)
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK (0x80U)
#define LPUART_DATA_R7T7_SHIFT (7U)
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK (0x100U)
#define LPUART_DATA_R8T8_SHIFT (8U)
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK (0x200U)
#define LPUART_DATA_R9T9_SHIFT (9U)
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK (0x800U)
#define LPUART_DATA_IDLINE_SHIFT (11U)
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT (12U)
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT (13U)
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT (14U)
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK (0x8000U)
#define LPUART_DATA_NOISY_SHIFT (15U)
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */
/*! @name MATCH - LPUART Match Address Register */
/*! @{ */
#define LPUART_MATCH_MA1_MASK (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT (0U)
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT (16U)
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */
/*! @name MODIR - LPUART Modem IrDA Register */
/*! @{ */
#define LPUART_MODIR_TXCTSE_MASK (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT (0U)
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT (1U)
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT (3U)
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT (4U)
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_RTSWATER_MASK (0x300U)
#define LPUART_MODIR_RTSWATER_SHIFT (8U)
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
#define LPUART_MODIR_TNP_MASK (0x30000U)
#define LPUART_MODIR_TNP_SHIFT (16U)
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK (0x40000U)
#define LPUART_MODIR_IREN_SHIFT (18U)
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */
/*! @name FIFO - LPUART FIFO Register */
/*! @{ */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
#define LPUART_FIFO_RXFE_MASK (0x8U)
#define LPUART_FIFO_RXFE_SHIFT (3U)
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
#define LPUART_FIFO_TXFE_MASK (0x80U)
#define LPUART_FIFO_TXFE_SHIFT (7U)
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
#define LPUART_FIFO_RXUFE_MASK (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT (8U)
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
#define LPUART_FIFO_TXOFE_MASK (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT (9U)
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT (10U)
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
#define LPUART_FIFO_RXUF_MASK (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT (16U)
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
#define LPUART_FIFO_TXOF_MASK (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT (17U)
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT (22U)
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT (23U)
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */
/*! @name WATER - LPUART Watermark Register */
/*! @{ */
#define LPUART_WATER_TXWATER_MASK (0x3U)
#define LPUART_WATER_TXWATER_SHIFT (0U)
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
#define LPUART_WATER_TXCOUNT_MASK (0x700U)
#define LPUART_WATER_TXCOUNT_SHIFT (8U)
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
#define LPUART_WATER_RXWATER_MASK (0x30000U)
#define LPUART_WATER_RXWATER_SHIFT (16U)
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
#define LPUART_WATER_RXCOUNT_SHIFT (24U)
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART1 base address */
#define LPUART1_BASE (0x40184000u)
/** Peripheral LPUART1 base pointer */
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
/** Peripheral LPUART2 base address */
#define LPUART2_BASE (0x40188000u)
/** Peripheral LPUART2 base pointer */
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
/** Peripheral LPUART3 base address */
#define LPUART3_BASE (0x4018C000u)
/** Peripheral LPUART3 base pointer */
#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
/** Peripheral LPUART4 base address */
#define LPUART4_BASE (0x40190000u)
/** Peripheral LPUART4 base pointer */
#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
/** Peripheral LPUART5 base address */
#define LPUART5_BASE (0x40194000u)
/** Peripheral LPUART5 base pointer */
#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
/** Peripheral LPUART6 base address */
#define LPUART6_BASE (0x40198000u)
/** Peripheral LPUART6 base pointer */
#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
/** Peripheral LPUART7 base address */
#define LPUART7_BASE (0x4019C000u)
/** Peripheral LPUART7 base pointer */
#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
/** Peripheral LPUART8 base address */
#define LPUART8_BASE (0x401A0000u)
/** Peripheral LPUART8 base pointer */
#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OCOTP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
* @{
*/
/** OCOTP - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */
__IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
uint8_t RESERVED_1[12];
__IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */
uint8_t RESERVED_3[12];
__IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */
uint8_t RESERVED_4[12];
__IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */
__IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */
__IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */
__IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */
uint8_t RESERVED_5[32];
__I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */
uint8_t RESERVED_6[108];
__IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */
uint8_t RESERVED_7[764];
__IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
uint8_t RESERVED_8[12];
__IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */
uint8_t RESERVED_9[12];
__IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */
uint8_t RESERVED_10[12];
__IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */
uint8_t RESERVED_11[12];
__IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */
uint8_t RESERVED_12[12];
__IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */
uint8_t RESERVED_13[12];
__IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */
uint8_t RESERVED_14[12];
__IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */
uint8_t RESERVED_15[12];
__IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */
uint8_t RESERVED_16[12];
__IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */
uint8_t RESERVED_17[12];
__IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */
uint8_t RESERVED_18[12];
__IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */
uint8_t RESERVED_19[12];
__IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */
uint8_t RESERVED_20[12];
__IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Analog Info.), offset: 0x4D0 */
uint8_t RESERVED_21[12];
__IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (Analog Info.), offset: 0x4E0 */
uint8_t RESERVED_22[12];
__IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (Analog Info.), offset: 0x4F0 */
uint8_t RESERVED_23[140];
__IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */
uint8_t RESERVED_24[12];
__IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */
uint8_t RESERVED_25[12];
__IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */
uint8_t RESERVED_26[12];
__IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */
uint8_t RESERVED_27[12];
__IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */
uint8_t RESERVED_28[12];
__IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */
uint8_t RESERVED_29[12];
__IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */
uint8_t RESERVED_30[12];
__IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */
uint8_t RESERVED_31[12];
__IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */
uint8_t RESERVED_32[12];
__IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */
uint8_t RESERVED_33[12];
__IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */
uint8_t RESERVED_34[12];
__IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */
uint8_t RESERVED_35[12];
__IO uint32_t GP3; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */
uint8_t RESERVED_36[28];
__IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */
uint8_t RESERVED_37[12];
__IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */
uint8_t RESERVED_38[12];
__IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */
uint8_t RESERVED_39[12];
__IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */
uint8_t RESERVED_40[12];
__IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */
uint8_t RESERVED_41[12];
__IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */
uint8_t RESERVED_42[12];
__IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */
uint8_t RESERVED_43[12];
__IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */
uint8_t RESERVED_44[12];
__IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */
uint8_t RESERVED_45[12];
__IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */
} OCOTP_Type;
/* ----------------------------------------------------------------------------
-- OCOTP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Register_Masks OCOTP Register Masks
* @{
*/
/*! @name CTRL - OTP Controller Control Register */
/*! @{ */
#define OCOTP_CTRL_ADDR_MASK (0x3FU)
#define OCOTP_CTRL_ADDR_SHIFT (0U)
#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
#define OCOTP_CTRL_BUSY_MASK (0x100U)
#define OCOTP_CTRL_BUSY_SHIFT (8U)
#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
#define OCOTP_CTRL_ERROR_MASK (0x200U)
#define OCOTP_CTRL_ERROR_SHIFT (9U)
#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_SET - OTP Controller Control Register */
/*! @{ */
#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
#define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
#define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
#define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
#define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_CLR - OTP Controller Control Register */
/*! @{ */
#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_TOG - OTP Controller Control Register */
/*! @{ */
#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
/*! @} */
/*! @name TIMING - OTP Controller Timing Register */
/*! @{ */
#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
#define OCOTP_TIMING_RELAX_MASK (0xF000U)
#define OCOTP_TIMING_RELAX_SHIFT (12U)
#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
#define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
#define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
#define OCOTP_TIMING_WAIT_SHIFT (22U)
#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
/*! @} */
/*! @name DATA - OTP Controller Write Data Register */
/*! @{ */
#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_DATA_DATA_SHIFT (0U)
#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
/*! @} */
/*! @name READ_CTRL - OTP Controller Write Data Register */
/*! @{ */
#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
/*! @} */
/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */
/*! @{ */
#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
/*! @} */
/*! @name SW_STICKY - Sticky bit Register */
/*! @{ */
#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
/*! @} */
/*! @name SCS - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_SCS_HAB_JDE_MASK (0x1U)
#define OCOTP_SCS_HAB_JDE_SHIFT (0U)
#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_SCS_SPARE_SHIFT (1U)
#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
#define OCOTP_SCS_LOCK_MASK (0x80000000U)
#define OCOTP_SCS_LOCK_SHIFT (31U)
#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
/*! @} */
/*! @name SCS_SET - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_SCS_SET_SPARE_SHIFT (1U)
#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
#define OCOTP_SCS_SET_LOCK_SHIFT (31U)
#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
/*! @} */
/*! @name SCS_CLR - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
#define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
/*! @} */
/*! @name SCS_TOG - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
#define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
/*! @} */
/*! @name VERSION - OTP Controller Version Register */
/*! @{ */
#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
#define OCOTP_VERSION_STEP_SHIFT (0U)
#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
#define OCOTP_VERSION_MINOR_SHIFT (16U)
#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
#define OCOTP_VERSION_MAJOR_SHIFT (24U)
#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
/*! @} */
/*! @name TIMING2 - OTP Controller Timing Register 2 */
/*! @{ */
#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U)
#define OCOTP_TIMING2_RELAX1_SHIFT (22U)
#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK)
/*! @} */
/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */
/*! @{ */
#define OCOTP_LOCK_TESTER_MASK (0x3U)
#define OCOTP_LOCK_TESTER_SHIFT (0U)
#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
#define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
#define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
#define OCOTP_LOCK_GP1_MASK (0xC00U)
#define OCOTP_LOCK_GP1_SHIFT (10U)
#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
#define OCOTP_LOCK_GP2_MASK (0x3000U)
#define OCOTP_LOCK_GP2_SHIFT (12U)
#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
#define OCOTP_LOCK_SRK_MASK (0x4000U)
#define OCOTP_LOCK_SRK_SHIFT (14U)
#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK)
#define OCOTP_LOCK_OTPMK_MSB_MASK (0x8000U)
#define OCOTP_LOCK_OTPMK_MSB_SHIFT (15U)
#define OCOTP_LOCK_OTPMK_MSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_MSB_SHIFT)) & OCOTP_LOCK_OTPMK_MSB_MASK)
#define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
#define OCOTP_LOCK_SW_GP1_SHIFT (16U)
#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
#define OCOTP_LOCK_OTPMK_LSB_MASK (0x20000U)
#define OCOTP_LOCK_OTPMK_LSB_SHIFT (17U)
#define OCOTP_LOCK_OTPMK_LSB(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_LSB_SHIFT)) & OCOTP_LOCK_OTPMK_LSB_MASK)
#define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
#define OCOTP_LOCK_ANALOG_SHIFT (18U)
#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
#define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
#define OCOTP_LOCK_GP3_MASK (0xC000000U)
#define OCOTP_LOCK_GP3_SHIFT (26U)
#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
/*! @} */
/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG0_BITS_SHIFT (0U)
#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
/*! @} */
/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG1_BITS_SHIFT (0U)
#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
/*! @} */
/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG2_BITS_SHIFT (0U)
#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
/*! @} */
/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG3_BITS_SHIFT (0U)
#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
/*! @} */
/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG4_BITS_SHIFT (0U)
#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
/*! @} */
/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG5_BITS_SHIFT (0U)
#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
/*! @} */
/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */
/*! @{ */
#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_CFG6_BITS_SHIFT (0U)
#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
/*! @} */
/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */
/*! @{ */
#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MEM0_BITS_SHIFT (0U)
#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
/*! @} */
/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */
/*! @{ */
#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MEM1_BITS_SHIFT (0U)
#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
/*! @} */
/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */
/*! @{ */
#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MEM2_BITS_SHIFT (0U)
#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
/*! @} */
/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */
/*! @{ */
#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MEM3_BITS_SHIFT (0U)
#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
/*! @} */
/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */
/*! @{ */
#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MEM4_BITS_SHIFT (0U)
#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
/*! @} */
/*! @name ANA0 - Value of OTP Bank1 Word5 (Analog Info.) */
/*! @{ */
#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_ANA0_BITS_SHIFT (0U)
#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
/*! @} */
/*! @name ANA1 - Value of OTP Bank1 Word6 (Analog Info.) */
/*! @{ */
#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_ANA1_BITS_SHIFT (0U)
#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
/*! @} */
/*! @name ANA2 - Value of OTP Bank1 Word7 (Analog Info.) */
/*! @{ */
#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_ANA2_BITS_SHIFT (0U)
#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
/*! @} */
/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK0_BITS_SHIFT (0U)
#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
/*! @} */
/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK1_BITS_SHIFT (0U)
#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
/*! @} */
/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK2_BITS_SHIFT (0U)
#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
/*! @} */
/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK3_BITS_SHIFT (0U)
#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
/*! @} */
/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK4_BITS_SHIFT (0U)
#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
/*! @} */
/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK5_BITS_SHIFT (0U)
#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
/*! @} */
/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK6_BITS_SHIFT (0U)
#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
/*! @} */
/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */
/*! @{ */
#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK7_BITS_SHIFT (0U)
#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
/*! @} */
/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
/*! @{ */
#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
/*! @} */
/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
/*! @{ */
#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
/*! @} */
/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */
/*! @{ */
#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MAC0_BITS_SHIFT (0U)
#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
/*! @} */
/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */
/*! @{ */
#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MAC1_BITS_SHIFT (0U)
#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
/*! @} */
/*! @name GP3 - Value of OTP Bank4 Word4 (MAC Address) */
/*! @{ */
#define OCOTP_GP3_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_GP3_BITS_SHIFT (0U)
#define OCOTP_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_BITS_SHIFT)) & OCOTP_GP3_BITS_MASK)
/*! @} */
/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */
/*! @{ */
#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_GP1_BITS_SHIFT (0U)
#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
/*! @} */
/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */
/*! @{ */
#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_GP2_BITS_SHIFT (0U)
#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
/*! @} */
/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */
/*! @{ */
#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SW_GP1_BITS_SHIFT (0U)
#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
/*! @} */
/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */
/*! @{ */
#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SW_GP20_BITS_SHIFT (0U)
#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
/*! @} */
/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */
/*! @{ */
#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SW_GP21_BITS_SHIFT (0U)
#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
/*! @} */
/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */
/*! @{ */
#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SW_GP22_BITS_SHIFT (0U)
#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
/*! @} */
/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */
/*! @{ */
#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SW_GP23_BITS_SHIFT (0U)
#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
/*! @} */
/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */
/*! @{ */
#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
/*! @} */
/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */
/*! @{ */
#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
/*! @} */
/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */
/*! @{ */
#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group OCOTP_Register_Masks */
/* OCOTP - Peripheral instance base addresses */
/** Peripheral OCOTP base address */
#define OCOTP_BASE (0x401F4000u)
/** Peripheral OCOTP base pointer */
#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
/** Array initializer of OCOTP peripheral base addresses */
#define OCOTP_BASE_ADDRS { OCOTP_BASE }
/** Array initializer of OCOTP peripheral base pointers */
#define OCOTP_BASE_PTRS { OCOTP }
/*!
* @}
*/ /* end of group OCOTP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PGC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer
* @{
*/
/** PGC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[544];
__IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */
__IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */
__IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */
__IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */
uint8_t RESERVED_1[112];
__IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */
__IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */
__IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */
__IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */
} PGC_Type;
/* ----------------------------------------------------------------------------
-- PGC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGC_Register_Masks PGC Register Masks
* @{
*/
/*! @name MEGA_CTRL - PGC Mega Control Register */
/*! @{ */
#define PGC_MEGA_CTRL_PCR_MASK (0x1U)
#define PGC_MEGA_CTRL_PCR_SHIFT (0U)
#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
/*! @} */
/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */
/*! @{ */
#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
#define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
/*! @} */
/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */
/*! @{ */
#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
/*! @} */
/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */
/*! @{ */
#define PGC_MEGA_SR_PSR_MASK (0x1U)
#define PGC_MEGA_SR_PSR_SHIFT (0U)
#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
/*! @} */
/*! @name CPU_CTRL - PGC CPU Control Register */
/*! @{ */
#define PGC_CPU_CTRL_PCR_MASK (0x1U)
#define PGC_CPU_CTRL_PCR_SHIFT (0U)
#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
/*! @} */
/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */
/*! @{ */
#define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
#define PGC_CPU_PUPSCR_SW_SHIFT (0U)
#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
/*! @} */
/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */
/*! @{ */
#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
#define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
/*! @} */
/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */
/*! @{ */
#define PGC_CPU_SR_PSR_MASK (0x1U)
#define PGC_CPU_SR_PSR_SHIFT (0U)
#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PGC_Register_Masks */
/* PGC - Peripheral instance base addresses */
/** Peripheral PGC base address */
#define PGC_BASE (0x400F4000u)
/** Peripheral PGC base pointer */
#define PGC ((PGC_Type *)PGC_BASE)
/** Array initializer of PGC peripheral base addresses */
#define PGC_BASE_ADDRS { PGC_BASE }
/** Array initializer of PGC peripheral base pointers */
#define PGC_BASE_PTRS { PGC }
/*!
* @}
*/ /* end of group PGC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
* @{
*/
/** PIT - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
uint8_t RESERVED_0[220];
__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
uint8_t RESERVED_1[24];
struct { /* offset: 0x100, array step: 0x10 */
__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
} PIT_Type;
/* ----------------------------------------------------------------------------
-- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
/*! @name MCR - PIT Module Control Register */
/*! @{ */
#define PIT_MCR_FRZ_MASK (0x1U)
#define PIT_MCR_FRZ_SHIFT (0U)
#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define PIT_MCR_MDIS_MASK (0x2U)
#define PIT_MCR_MDIS_SHIFT (1U)
#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
/*! @} */
/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
/*! @{ */
#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
#define PIT_LTMR64H_LTH_SHIFT (0U)
#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
/*! @} */
/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
/*! @{ */
#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
#define PIT_LTMR64L_LTL_SHIFT (0U)
#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
/*! @} */
/*! @name LDVAL - Timer Load Value Register */
/*! @{ */
#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
#define PIT_LDVAL_TSV_SHIFT (0U)
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
/*! @} */
/* The count of PIT_LDVAL */
#define PIT_LDVAL_COUNT (4U)
/*! @name CVAL - Current Timer Value Register */
/*! @{ */
#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
#define PIT_CVAL_TVL_SHIFT (0U)
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/*! @} */
/* The count of PIT_CVAL */
#define PIT_CVAL_COUNT (4U)
/*! @name TCTRL - Timer Control Register */
/*! @{ */
#define PIT_TCTRL_TEN_MASK (0x1U)
#define PIT_TCTRL_TEN_SHIFT (0U)
#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define PIT_TCTRL_TIE_MASK (0x2U)
#define PIT_TCTRL_TIE_SHIFT (1U)
#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define PIT_TCTRL_CHN_MASK (0x4U)
#define PIT_TCTRL_CHN_SHIFT (2U)
#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/*! @} */
/* The count of PIT_TCTRL */
#define PIT_TCTRL_COUNT (4U)
/*! @name TFLG - Timer Flag Register */
/*! @{ */
#define PIT_TFLG_TIF_MASK (0x1U)
#define PIT_TFLG_TIF_SHIFT (0U)
#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
/*! @} */
/* The count of PIT_TFLG */
#define PIT_TFLG_COUNT (4U)
/*!
* @}
*/ /* end of group PIT_Register_Masks */
/* PIT - Peripheral instance base addresses */
/** Peripheral PIT base address */
#define PIT_BASE (0x40084000u)
/** Peripheral PIT base pointer */
#define PIT ((PIT_Type *)PIT_BASE)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { PIT_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { PIT }
/** Interrupt vectors for the PIT peripheral type */
#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
/*!
* @}
*/ /* end of group PIT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
* @{
*/
/** PMU - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[272];
__IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */
__IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */
__IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */
__IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */
__IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */
__IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */
__IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */
__IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */
__IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */
__IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */
__IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */
__IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */
__IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */
__IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */
__IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */
__IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
__IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
__IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
__IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
__IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
__IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */
__IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */
__IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */
__IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */
} PMU_Type;
/* ----------------------------------------------------------------------------
-- PMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMU_Register_Masks PMU Register Masks
* @{
*/
/*! @name REG_1P1 - Regulator 1P1 Register */
/*! @{ */
#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_1P1_SET - Regulator 1P1 Register */
/*! @{ */
#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_1P1_CLR - Regulator 1P1 Register */
/*! @{ */
#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_1P1_TOG - Regulator 1P1 Register */
/*! @{ */
#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_3P0 - Regulator 3P0 Register */
/*! @{ */
#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
/*! @} */
/*! @name REG_3P0_SET - Regulator 3P0 Register */
/*! @{ */
#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
/*! @} */
/*! @name REG_3P0_CLR - Regulator 3P0 Register */
/*! @{ */
#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
/*! @} */
/*! @name REG_3P0_TOG - Regulator 3P0 Register */
/*! @{ */
#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
/*! @} */
/*! @name REG_2P5 - Regulator 2P5 Register */
/*! @{ */
#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_2P5_SET - Regulator 2P5 Register */
/*! @{ */
#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_2P5_CLR - Regulator 2P5 Register */
/*! @{ */
#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_2P5_TOG - Regulator 2P5 Register */
/*! @{ */
#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
/*! @} */
/*! @name REG_CORE - Digital Regulator Core Register */
/*! @{ */
#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
/*! @} */
/*! @name REG_CORE_SET - Digital Regulator Core Register */
/*! @{ */
#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
/*! @} */
/*! @name REG_CORE_CLR - Digital Regulator Core Register */
/*! @{ */
#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
/*! @} */
/*! @name REG_CORE_TOG - Digital Regulator Core Register */
/*! @{ */
#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
/*! @} */
/*! @name MISC0 - Miscellaneous Register 0 */
/*! @{ */
#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
#define PMU_MISC0_OSC_I_MASK (0x6000U)
#define PMU_MISC0_OSC_I_SHIFT (13U)
#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_SET - Miscellaneous Register 0 */
/*! @{ */
#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
#define PMU_MISC0_SET_OSC_I_SHIFT (13U)
#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_CLR - Miscellaneous Register 0 */
/*! @{ */
#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_TOG - Miscellaneous Register 0 */
/*! @{ */
#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC1 - Miscellaneous Register 1 */
/*! @{ */
#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_SET - Miscellaneous Register 1 */
/*! @{ */
#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_CLR - Miscellaneous Register 1 */
/*! @{ */
#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC1_TOG - Miscellaneous Register 1 */
/*! @{ */
#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
/*! @} */
/*! @name MISC2 - Miscellaneous Control Register */
/*! @{ */
#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
#define PMU_MISC2_PLL3_disable_MASK (0x80U)
#define PMU_MISC2_PLL3_disable_SHIFT (7U)
#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
#define PMU_MISC2_REG2_OK_MASK (0x400000U)
#define PMU_MISC2_REG2_OK_SHIFT (22U)
#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_SET - Miscellaneous Control Register */
/*! @{ */
#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_CLR - Miscellaneous Control Register */
/*! @{ */
#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
/*! @} */
/*! @name MISC2_TOG - Miscellaneous Control Register */
/*! @{ */
#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PMU_Register_Masks */
/* PMU - Peripheral instance base addresses */
/** Peripheral PMU base address */
#define PMU_BASE (0x400D8000u)
/** Peripheral PMU base pointer */
#define PMU ((PMU_Type *)PMU_BASE)
/** Array initializer of PMU peripheral base addresses */
#define PMU_BASE_ADDRS { PMU_BASE }
/** Array initializer of PMU peripheral base pointers */
#define PMU_BASE_PTRS { PMU }
/*!
* @}
*/ /* end of group PMU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
* @{
*/
/** PWM - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x60 */
__I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */
__IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
__IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
__IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */
uint8_t RESERVED_0[2];
__IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */
__IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
__IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */
__IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
__IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */
__IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
__IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */
__IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
__IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
__IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
__IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
__IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
__IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */
__IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */
__IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
__IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
__IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */
__IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
__IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
__IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
__IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
__IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
__IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
__IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
__IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
__I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
__I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
__I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
__I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
__I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
__I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
__I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
__I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
__I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
__I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
__I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
__I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
uint8_t RESERVED_1[8];
} SM[4];
__IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */
__IO uint16_t MASK; /**< Mask Register, offset: 0x182 */
__IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */
__IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */
__IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */
__IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */
__IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */
__IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */
__IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */
__IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */
__IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */
} PWM_Type;
/* ----------------------------------------------------------------------------
-- PWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Register_Masks PWM Register Masks
* @{
*/
/*! @name CNT - Counter Register */
/*! @{ */
#define PWM_CNT_CNT_MASK (0xFFFFU)
#define PWM_CNT_CNT_SHIFT (0U)
#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
/*! @} */
/* The count of PWM_CNT */
#define PWM_CNT_COUNT (4U)
/*! @name INIT - Initial Count Register */
/*! @{ */
#define PWM_INIT_INIT_MASK (0xFFFFU)
#define PWM_INIT_INIT_SHIFT (0U)
#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
/*! @} */
/* The count of PWM_INIT */
#define PWM_INIT_COUNT (4U)
/*! @name CTRL2 - Control 2 Register */
/*! @{ */
#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
#define PWM_CTRL2_FORCE_MASK (0x40U)
#define PWM_CTRL2_FORCE_SHIFT (6U)
#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
#define PWM_CTRL2_FRCEN_MASK (0x80U)
#define PWM_CTRL2_FRCEN_SHIFT (7U)
#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
#define PWM_CTRL2_INDEP_MASK (0x2000U)
#define PWM_CTRL2_INDEP_SHIFT (13U)
#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
#define PWM_CTRL2_WAITEN_MASK (0x4000U)
#define PWM_CTRL2_WAITEN_SHIFT (14U)
#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
#define PWM_CTRL2_DBGEN_MASK (0x8000U)
#define PWM_CTRL2_DBGEN_SHIFT (15U)
#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
/*! @} */
/* The count of PWM_CTRL2 */
#define PWM_CTRL2_COUNT (4U)
/*! @name CTRL - Control Register */
/*! @{ */
#define PWM_CTRL_DBLEN_MASK (0x1U)
#define PWM_CTRL_DBLEN_SHIFT (0U)
#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define PWM_CTRL_DBLX_MASK (0x2U)
#define PWM_CTRL_DBLX_SHIFT (1U)
#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define PWM_CTRL_LDMOD_MASK (0x4U)
#define PWM_CTRL_LDMOD_SHIFT (2U)
#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define PWM_CTRL_SPLIT_MASK (0x8U)
#define PWM_CTRL_SPLIT_SHIFT (3U)
#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define PWM_CTRL_PRSC_MASK (0x70U)
#define PWM_CTRL_PRSC_SHIFT (4U)
#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define PWM_CTRL_COMPMODE_MASK (0x80U)
#define PWM_CTRL_COMPMODE_SHIFT (7U)
#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define PWM_CTRL_DT_MASK (0x300U)
#define PWM_CTRL_DT_SHIFT (8U)
#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define PWM_CTRL_FULL_MASK (0x400U)
#define PWM_CTRL_FULL_SHIFT (10U)
#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define PWM_CTRL_HALF_MASK (0x800U)
#define PWM_CTRL_HALF_SHIFT (11U)
#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define PWM_CTRL_LDFQ_MASK (0xF000U)
#define PWM_CTRL_LDFQ_SHIFT (12U)
#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
/*! @} */
/* The count of PWM_CTRL */
#define PWM_CTRL_COUNT (4U)
/*! @name VAL0 - Value Register 0 */
/*! @{ */
#define PWM_VAL0_VAL0_MASK (0xFFFFU)
#define PWM_VAL0_VAL0_SHIFT (0U)
#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
/*! @} */
/* The count of PWM_VAL0 */
#define PWM_VAL0_COUNT (4U)
/*! @name FRACVAL1 - Fractional Value Register 1 */
/*! @{ */
#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
/*! @} */
/* The count of PWM_FRACVAL1 */
#define PWM_FRACVAL1_COUNT (4U)
/*! @name VAL1 - Value Register 1 */
/*! @{ */
#define PWM_VAL1_VAL1_MASK (0xFFFFU)
#define PWM_VAL1_VAL1_SHIFT (0U)
#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
/*! @} */
/* The count of PWM_VAL1 */
#define PWM_VAL1_COUNT (4U)
/*! @name FRACVAL2 - Fractional Value Register 2 */
/*! @{ */
#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
/*! @} */
/* The count of PWM_FRACVAL2 */
#define PWM_FRACVAL2_COUNT (4U)
/*! @name VAL2 - Value Register 2 */
/*! @{ */
#define PWM_VAL2_VAL2_MASK (0xFFFFU)
#define PWM_VAL2_VAL2_SHIFT (0U)
#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
/*! @} */
/* The count of PWM_VAL2 */
#define PWM_VAL2_COUNT (4U)
/*! @name FRACVAL3 - Fractional Value Register 3 */
/*! @{ */
#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
/*! @} */
/* The count of PWM_FRACVAL3 */
#define PWM_FRACVAL3_COUNT (4U)
/*! @name VAL3 - Value Register 3 */
/*! @{ */
#define PWM_VAL3_VAL3_MASK (0xFFFFU)
#define PWM_VAL3_VAL3_SHIFT (0U)
#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
/*! @} */
/* The count of PWM_VAL3 */
#define PWM_VAL3_COUNT (4U)
/*! @name FRACVAL4 - Fractional Value Register 4 */
/*! @{ */
#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
/*! @} */
/* The count of PWM_FRACVAL4 */
#define PWM_FRACVAL4_COUNT (4U)
/*! @name VAL4 - Value Register 4 */
/*! @{ */
#define PWM_VAL4_VAL4_MASK (0xFFFFU)
#define PWM_VAL4_VAL4_SHIFT (0U)
#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
/*! @} */
/* The count of PWM_VAL4 */
#define PWM_VAL4_COUNT (4U)
/*! @name FRACVAL5 - Fractional Value Register 5 */
/*! @{ */
#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
/*! @} */
/* The count of PWM_FRACVAL5 */
#define PWM_FRACVAL5_COUNT (4U)
/*! @name VAL5 - Value Register 5 */
/*! @{ */
#define PWM_VAL5_VAL5_MASK (0xFFFFU)
#define PWM_VAL5_VAL5_SHIFT (0U)
#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
/*! @} */
/* The count of PWM_VAL5 */
#define PWM_VAL5_COUNT (4U)
/*! @name FRCTRL - Fractional Control Register */
/*! @{ */
#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
#define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
#define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
#define PWM_FRCTRL_TEST_MASK (0x8000U)
#define PWM_FRCTRL_TEST_SHIFT (15U)
#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
/*! @} */
/* The count of PWM_FRCTRL */
#define PWM_FRCTRL_COUNT (4U)
/*! @name OCTRL - Output Control Register */
/*! @{ */
#define PWM_OCTRL_PWMXFS_MASK (0x3U)
#define PWM_OCTRL_PWMXFS_SHIFT (0U)
#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
#define PWM_OCTRL_PWMBFS_MASK (0xCU)
#define PWM_OCTRL_PWMBFS_SHIFT (2U)
#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
#define PWM_OCTRL_PWMAFS_MASK (0x30U)
#define PWM_OCTRL_PWMAFS_SHIFT (4U)
#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
#define PWM_OCTRL_POLX_MASK (0x100U)
#define PWM_OCTRL_POLX_SHIFT (8U)
#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
#define PWM_OCTRL_POLB_MASK (0x200U)
#define PWM_OCTRL_POLB_SHIFT (9U)
#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
#define PWM_OCTRL_POLA_MASK (0x400U)
#define PWM_OCTRL_POLA_SHIFT (10U)
#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
/*! @} */
/* The count of PWM_OCTRL */
#define PWM_OCTRL_COUNT (4U)
/*! @name STS - Status Register */
/*! @{ */
#define PWM_STS_CMPF_MASK (0x3FU)
#define PWM_STS_CMPF_SHIFT (0U)
#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
#define PWM_STS_CFX0_MASK (0x40U)
#define PWM_STS_CFX0_SHIFT (6U)
#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
#define PWM_STS_CFX1_MASK (0x80U)
#define PWM_STS_CFX1_SHIFT (7U)
#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
#define PWM_STS_CFB0_MASK (0x100U)
#define PWM_STS_CFB0_SHIFT (8U)
#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
#define PWM_STS_CFB1_MASK (0x200U)
#define PWM_STS_CFB1_SHIFT (9U)
#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
#define PWM_STS_CFA0_MASK (0x400U)
#define PWM_STS_CFA0_SHIFT (10U)
#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
#define PWM_STS_CFA1_MASK (0x800U)
#define PWM_STS_CFA1_SHIFT (11U)
#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
#define PWM_STS_RF_MASK (0x1000U)
#define PWM_STS_RF_SHIFT (12U)
#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
#define PWM_STS_REF_MASK (0x2000U)
#define PWM_STS_REF_SHIFT (13U)
#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
#define PWM_STS_RUF_MASK (0x4000U)
#define PWM_STS_RUF_SHIFT (14U)
#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
/*! @} */
/* The count of PWM_STS */
#define PWM_STS_COUNT (4U)
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define PWM_INTEN_CMPIE_MASK (0x3FU)
#define PWM_INTEN_CMPIE_SHIFT (0U)
#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
#define PWM_INTEN_CX0IE_MASK (0x40U)
#define PWM_INTEN_CX0IE_SHIFT (6U)
#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
#define PWM_INTEN_CX1IE_MASK (0x80U)
#define PWM_INTEN_CX1IE_SHIFT (7U)
#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
#define PWM_INTEN_CB0IE_MASK (0x100U)
#define PWM_INTEN_CB0IE_SHIFT (8U)
#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
#define PWM_INTEN_CB1IE_MASK (0x200U)
#define PWM_INTEN_CB1IE_SHIFT (9U)
#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
#define PWM_INTEN_CA0IE_MASK (0x400U)
#define PWM_INTEN_CA0IE_SHIFT (10U)
#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
#define PWM_INTEN_CA1IE_MASK (0x800U)
#define PWM_INTEN_CA1IE_SHIFT (11U)
#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
#define PWM_INTEN_RIE_MASK (0x1000U)
#define PWM_INTEN_RIE_SHIFT (12U)
#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
#define PWM_INTEN_REIE_MASK (0x2000U)
#define PWM_INTEN_REIE_SHIFT (13U)
#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
/*! @} */
/* The count of PWM_INTEN */
#define PWM_INTEN_COUNT (4U)
/*! @name DMAEN - DMA Enable Register */
/*! @{ */
#define PWM_DMAEN_CX0DE_MASK (0x1U)
#define PWM_DMAEN_CX0DE_SHIFT (0U)
#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
#define PWM_DMAEN_CX1DE_MASK (0x2U)
#define PWM_DMAEN_CX1DE_SHIFT (1U)
#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
#define PWM_DMAEN_CB0DE_MASK (0x4U)
#define PWM_DMAEN_CB0DE_SHIFT (2U)
#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
#define PWM_DMAEN_CB1DE_MASK (0x8U)
#define PWM_DMAEN_CB1DE_SHIFT (3U)
#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
#define PWM_DMAEN_CA0DE_MASK (0x10U)
#define PWM_DMAEN_CA0DE_SHIFT (4U)
#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
#define PWM_DMAEN_CA1DE_MASK (0x20U)
#define PWM_DMAEN_CA1DE_SHIFT (5U)
#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
#define PWM_DMAEN_CAPTDE_SHIFT (6U)
#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
#define PWM_DMAEN_FAND_MASK (0x100U)
#define PWM_DMAEN_FAND_SHIFT (8U)
#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
#define PWM_DMAEN_VALDE_MASK (0x200U)
#define PWM_DMAEN_VALDE_SHIFT (9U)
#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
/*! @} */
/* The count of PWM_DMAEN */
#define PWM_DMAEN_COUNT (4U)
/*! @name TCTRL - Output Trigger Control Register */
/*! @{ */
#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
#define PWM_TCTRL_PWBOT1_SHIFT (14U)
#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
#define PWM_TCTRL_PWAOT0_SHIFT (15U)
#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
/*! @} */
/* The count of PWM_TCTRL */
#define PWM_TCTRL_COUNT (4U)
/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */
/*! @{ */
#define PWM_DISMAP_DIS0A_MASK (0xFU)
#define PWM_DISMAP_DIS0A_SHIFT (0U)
#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
#define PWM_DISMAP_DIS1A_MASK (0xFU)
#define PWM_DISMAP_DIS1A_SHIFT (0U)
#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
#define PWM_DISMAP_DIS0B_MASK (0xF0U)
#define PWM_DISMAP_DIS0B_SHIFT (4U)
#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
#define PWM_DISMAP_DIS1B_MASK (0xF0U)
#define PWM_DISMAP_DIS1B_SHIFT (4U)
#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
#define PWM_DISMAP_DIS0X_MASK (0xF00U)
#define PWM_DISMAP_DIS0X_SHIFT (8U)
#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
#define PWM_DISMAP_DIS1X_MASK (0xF00U)
#define PWM_DISMAP_DIS1X_SHIFT (8U)
#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
/*! @} */
/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT (4U)
/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT2 (2U)
/*! @name DTCNT0 - Deadtime Count Register 0 */
/*! @{ */
#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
/*! @} */
/* The count of PWM_DTCNT0 */
#define PWM_DTCNT0_COUNT (4U)
/*! @name DTCNT1 - Deadtime Count Register 1 */
/*! @{ */
#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
/*! @} */
/* The count of PWM_DTCNT1 */
#define PWM_DTCNT1_COUNT (4U)
/*! @name CAPTCTRLA - Capture Control A Register */
/*! @{ */
#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLA */
#define PWM_CAPTCTRLA_COUNT (4U)
/*! @name CAPTCOMPA - Capture Compare A Register */
/*! @{ */
#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPA */
#define PWM_CAPTCOMPA_COUNT (4U)
/*! @name CAPTCTRLB - Capture Control B Register */
/*! @{ */
#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLB */
#define PWM_CAPTCTRLB_COUNT (4U)
/*! @name CAPTCOMPB - Capture Compare B Register */
/*! @{ */
#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPB */
#define PWM_CAPTCOMPB_COUNT (4U)
/*! @name CAPTCTRLX - Capture Control X Register */
/*! @{ */
#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLX */
#define PWM_CAPTCTRLX_COUNT (4U)
/*! @name CAPTCOMPX - Capture Compare X Register */
/*! @{ */
#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPX */
#define PWM_CAPTCOMPX_COUNT (4U)
/*! @name CVAL0 - Capture Value 0 Register */
/*! @{ */
#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
/*! @} */
/* The count of PWM_CVAL0 */
#define PWM_CVAL0_COUNT (4U)
/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
/*! @{ */
#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
/*! @} */
/* The count of PWM_CVAL0CYC */
#define PWM_CVAL0CYC_COUNT (4U)
/*! @name CVAL1 - Capture Value 1 Register */
/*! @{ */
#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
/*! @} */
/* The count of PWM_CVAL1 */
#define PWM_CVAL1_COUNT (4U)
/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
/*! @{ */
#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
/*! @} */
/* The count of PWM_CVAL1CYC */
#define PWM_CVAL1CYC_COUNT (4U)
/*! @name CVAL2 - Capture Value 2 Register */
/*! @{ */
#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
/*! @} */
/* The count of PWM_CVAL2 */
#define PWM_CVAL2_COUNT (4U)
/*! @name CVAL2CYC - Capture Value 2 Cycle Register */
/*! @{ */
#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
/*! @} */
/* The count of PWM_CVAL2CYC */
#define PWM_CVAL2CYC_COUNT (4U)
/*! @name CVAL3 - Capture Value 3 Register */
/*! @{ */
#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
/*! @} */
/* The count of PWM_CVAL3 */
#define PWM_CVAL3_COUNT (4U)
/*! @name CVAL3CYC - Capture Value 3 Cycle Register */
/*! @{ */
#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
/*! @} */
/* The count of PWM_CVAL3CYC */
#define PWM_CVAL3CYC_COUNT (4U)
/*! @name CVAL4 - Capture Value 4 Register */
/*! @{ */
#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
/*! @} */
/* The count of PWM_CVAL4 */
#define PWM_CVAL4_COUNT (4U)
/*! @name CVAL4CYC - Capture Value 4 Cycle Register */
/*! @{ */
#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
/*! @} */
/* The count of PWM_CVAL4CYC */
#define PWM_CVAL4CYC_COUNT (4U)
/*! @name CVAL5 - Capture Value 5 Register */
/*! @{ */
#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
/*! @} */
/* The count of PWM_CVAL5 */
#define PWM_CVAL5_COUNT (4U)
/*! @name CVAL5CYC - Capture Value 5 Cycle Register */
/*! @{ */
#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
/*! @} */
/* The count of PWM_CVAL5CYC */
#define PWM_CVAL5CYC_COUNT (4U)
/*! @name OUTEN - Output Enable Register */
/*! @{ */
#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
/*! @} */
/*! @name MASK - Mask Register */
/*! @{ */
#define PWM_MASK_MASKX_MASK (0xFU)
#define PWM_MASK_MASKX_SHIFT (0U)
#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
#define PWM_MASK_MASKB_MASK (0xF0U)
#define PWM_MASK_MASKB_SHIFT (4U)
#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
#define PWM_MASK_MASKA_MASK (0xF00U)
#define PWM_MASK_MASKA_SHIFT (8U)
#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
#define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
#define PWM_MASK_UPDATE_MASK_SHIFT (12U)
#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
/*! @} */
/*! @name SWCOUT - Software Controlled Output Register */
/*! @{ */
#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
/*! @} */
/*! @name DTSRCSEL - PWM Source Select Register */
/*! @{ */
#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
/*! @} */
/*! @name MCTRL - Master Control Register */
/*! @{ */
#define PWM_MCTRL_LDOK_MASK (0xFU)
#define PWM_MCTRL_LDOK_SHIFT (0U)
#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
#define PWM_MCTRL_CLDOK_MASK (0xF0U)
#define PWM_MCTRL_CLDOK_SHIFT (4U)
#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
#define PWM_MCTRL_RUN_MASK (0xF00U)
#define PWM_MCTRL_RUN_SHIFT (8U)
#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
#define PWM_MCTRL_IPOL_MASK (0xF000U)
#define PWM_MCTRL_IPOL_SHIFT (12U)
#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
/*! @} */
/*! @name MCTRL2 - Master Control 2 Register */
/*! @{ */
#define PWM_MCTRL2_MONPLL_MASK (0x3U)
#define PWM_MCTRL2_MONPLL_SHIFT (0U)
#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
/*! @} */
/*! @name FCTRL - Fault Control Register */
/*! @{ */
#define PWM_FCTRL_FIE_MASK (0xFU)
#define PWM_FCTRL_FIE_SHIFT (0U)
#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
#define PWM_FCTRL_FSAFE_MASK (0xF0U)
#define PWM_FCTRL_FSAFE_SHIFT (4U)
#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
#define PWM_FCTRL_FAUTO_MASK (0xF00U)
#define PWM_FCTRL_FAUTO_SHIFT (8U)
#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
#define PWM_FCTRL_FLVL_MASK (0xF000U)
#define PWM_FCTRL_FLVL_SHIFT (12U)
#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
/*! @} */
/*! @name FSTS - Fault Status Register */
/*! @{ */
#define PWM_FSTS_FFLAG_MASK (0xFU)
#define PWM_FSTS_FFLAG_SHIFT (0U)
#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
#define PWM_FSTS_FFULL_MASK (0xF0U)
#define PWM_FSTS_FFULL_SHIFT (4U)
#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
#define PWM_FSTS_FFPIN_MASK (0xF00U)
#define PWM_FSTS_FFPIN_SHIFT (8U)
#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
#define PWM_FSTS_FHALF_MASK (0xF000U)
#define PWM_FSTS_FHALF_SHIFT (12U)
#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
/*! @} */
/*! @name FFILT - Fault Filter Register */
/*! @{ */
#define PWM_FFILT_FILT_PER_MASK (0xFFU)
#define PWM_FFILT_FILT_PER_SHIFT (0U)
#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
#define PWM_FFILT_FILT_CNT_MASK (0x700U)
#define PWM_FFILT_FILT_CNT_SHIFT (8U)
#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
#define PWM_FFILT_GSTR_MASK (0x8000U)
#define PWM_FFILT_GSTR_SHIFT (15U)
#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
/*! @} */
/*! @name FTST - Fault Test Register */
/*! @{ */
#define PWM_FTST_FTEST_MASK (0x1U)
#define PWM_FTST_FTEST_SHIFT (0U)
#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
/*! @} */
/*! @name FCTRL2 - Fault Control 2 Register */
/*! @{ */
#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PWM_Register_Masks */
/* PWM - Peripheral instance base addresses */
/** Peripheral PWM1 base address */
#define PWM1_BASE (0x403DC000u)
/** Peripheral PWM1 base pointer */
#define PWM1 ((PWM_Type *)PWM1_BASE)
/** Peripheral PWM2 base address */
#define PWM2_BASE (0x403E0000u)
/** Peripheral PWM2 base pointer */
#define PWM2 ((PWM_Type *)PWM2_BASE)
/** Peripheral PWM3 base address */
#define PWM3_BASE (0x403E4000u)
/** Peripheral PWM3 base pointer */
#define PWM3 ((PWM_Type *)PWM3_BASE)
/** Peripheral PWM4 base address */
#define PWM4_BASE (0x403E8000u)
/** Peripheral PWM4 base pointer */
#define PWM4 ((PWM_Type *)PWM4_BASE)
/** Array initializer of PWM peripheral base addresses */
#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
/** Array initializer of PWM peripheral base pointers */
#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
/** Interrupt vectors for the PWM peripheral type */
#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
/*!
* @}
*/ /* end of group PWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PXP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
* @{
*/
/** PXP - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */
__IO uint32_t STAT; /**< Status Register, offset: 0x10 */
__IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */
__IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */
__IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */
__IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */
__IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */
__IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */
__IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */
__IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */
uint8_t RESERVED_0[12];
__IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */
uint8_t RESERVED_2[12];
__IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */
uint8_t RESERVED_3[12];
__IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
uint8_t RESERVED_4[12];
__IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
uint8_t RESERVED_5[12];
__IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
uint8_t RESERVED_6[12];
__IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
uint8_t RESERVED_7[12];
__IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */
__IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */
__IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */
__IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */
__IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */
uint8_t RESERVED_8[12];
__IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
uint8_t RESERVED_9[12];
__IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
uint8_t RESERVED_10[12];
__IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */
uint8_t RESERVED_11[12];
__IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */
uint8_t RESERVED_12[12];
__IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */
uint8_t RESERVED_13[12];
__IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */
uint8_t RESERVED_14[12];
__IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */
uint8_t RESERVED_15[12];
__IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */
uint8_t RESERVED_16[12];
__IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */
uint8_t RESERVED_17[12];
__IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */
uint8_t RESERVED_18[12];
__IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */
uint8_t RESERVED_19[12];
__IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */
uint8_t RESERVED_20[12];
__IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */
uint8_t RESERVED_21[12];
__IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
uint8_t RESERVED_22[12];
__IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
uint8_t RESERVED_23[12];
__IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
uint8_t RESERVED_24[348];
__IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */
uint8_t RESERVED_25[220];
__IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */
uint8_t RESERVED_26[60];
__IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */
} PXP_Type;
/* ----------------------------------------------------------------------------
-- PXP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PXP_Register_Masks PXP Register Masks
* @{
*/
/*! @name CTRL - Control Register 0 */
/*! @{ */
#define PXP_CTRL_ENABLE_MASK (0x1U)
#define PXP_CTRL_ENABLE_SHIFT (0U)
#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_RSVD0_MASK (0xE0U)
#define PXP_CTRL_RSVD0_SHIFT (5U)
#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK)
#define PXP_CTRL_ROTATE_MASK (0x300U)
#define PXP_CTRL_ROTATE_SHIFT (8U)
#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
#define PXP_CTRL_HFLIP_MASK (0x400U)
#define PXP_CTRL_HFLIP_SHIFT (10U)
#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
#define PXP_CTRL_VFLIP_MASK (0x800U)
#define PXP_CTRL_VFLIP_SHIFT (11U)
#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
#define PXP_CTRL_RSVD1_MASK (0x3FF000U)
#define PXP_CTRL_RSVD1_SHIFT (12U)
#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK)
#define PXP_CTRL_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_ROT_POS_SHIFT (22U)
#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
#define PXP_CTRL_RSVD3_MASK (0xF000000U)
#define PXP_CTRL_RSVD3_SHIFT (24U)
#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK)
#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_EN_REPEAT_SHIFT (28U)
#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
#define PXP_CTRL_RSVD4_MASK (0x20000000U)
#define PXP_CTRL_RSVD4_SHIFT (29U)
#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK)
#define PXP_CTRL_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_CLKGATE_SHIFT (30U)
#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
#define PXP_CTRL_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_SFTRST_SHIFT (31U)
#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - Control Register 0 */
/*! @{ */
#define PXP_CTRL_SET_ENABLE_MASK (0x1U)
#define PXP_CTRL_SET_ENABLE_SHIFT (0U)
#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_SET_RSVD0_MASK (0xE0U)
#define PXP_CTRL_SET_RSVD0_SHIFT (5U)
#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK)
#define PXP_CTRL_SET_ROTATE_MASK (0x300U)
#define PXP_CTRL_SET_ROTATE_SHIFT (8U)
#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
#define PXP_CTRL_SET_HFLIP_MASK (0x400U)
#define PXP_CTRL_SET_HFLIP_SHIFT (10U)
#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
#define PXP_CTRL_SET_VFLIP_MASK (0x800U)
#define PXP_CTRL_SET_VFLIP_SHIFT (11U)
#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U)
#define PXP_CTRL_SET_RSVD1_SHIFT (12U)
#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK)
#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U)
#define PXP_CTRL_SET_RSVD3_SHIFT (24U)
#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK)
#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U)
#define PXP_CTRL_SET_RSVD4_SHIFT (29U)
#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK)
#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_SET_SFTRST_SHIFT (31U)
#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - Control Register 0 */
/*! @{ */
#define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
#define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U)
#define PXP_CTRL_CLR_RSVD0_SHIFT (5U)
#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK)
#define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
#define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
#define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
#define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
#define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
#define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U)
#define PXP_CTRL_CLR_RSVD1_SHIFT (12U)
#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK)
#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U)
#define PXP_CTRL_CLR_RSVD3_SHIFT (24U)
#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK)
#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U)
#define PXP_CTRL_CLR_RSVD4_SHIFT (29U)
#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK)
#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - Control Register 0 */
/*! @{ */
#define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
#define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U)
#define PXP_CTRL_TOG_RSVD0_SHIFT (5U)
#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK)
#define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
#define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
#define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
#define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
#define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
#define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U)
#define PXP_CTRL_TOG_RSVD1_SHIFT (12U)
#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK)
#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U)
#define PXP_CTRL_TOG_RSVD3_SHIFT (24U)
#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK)
#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U)
#define PXP_CTRL_TOG_RSVD4_SHIFT (29U)
#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK)
#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STAT - Status Register */
/*! @{ */
#define PXP_STAT_IRQ_MASK (0x1U)
#define PXP_STAT_IRQ_SHIFT (0U)
#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
#define PXP_STAT_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_RSVD2_MASK (0xFE00U)
#define PXP_STAT_RSVD2_SHIFT (9U)
#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK)
#define PXP_STAT_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_BLOCKY_SHIFT (16U)
#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
#define PXP_STAT_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_BLOCKX_SHIFT (24U)
#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
/*! @} */
/*! @name STAT_SET - Status Register */
/*! @{ */
#define PXP_STAT_SET_IRQ_MASK (0x1U)
#define PXP_STAT_SET_IRQ_SHIFT (0U)
#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_SET_RSVD2_MASK (0xFE00U)
#define PXP_STAT_SET_RSVD2_SHIFT (9U)
#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK)
#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_SET_BLOCKY_SHIFT (16U)
#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_SET_BLOCKX_SHIFT (24U)
#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
/*! @} */
/*! @name STAT_CLR - Status Register */
/*! @{ */
#define PXP_STAT_CLR_IRQ_MASK (0x1U)
#define PXP_STAT_CLR_IRQ_SHIFT (0U)
#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U)
#define PXP_STAT_CLR_RSVD2_SHIFT (9U)
#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK)
#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
/*! @} */
/*! @name STAT_TOG - Status Register */
/*! @{ */
#define PXP_STAT_TOG_IRQ_MASK (0x1U)
#define PXP_STAT_TOG_IRQ_SHIFT (0U)
#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U)
#define PXP_STAT_TOG_RSVD2_SHIFT (9U)
#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK)
#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
/*! @} */
/*! @name OUT_CTRL - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U)
#define PXP_OUT_CTRL_RSVD0_SHIFT (5U)
#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U)
#define PXP_OUT_CTRL_RSVD1_SHIFT (10U)
#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK)
#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_SET - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U)
#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U)
#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U)
#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U)
#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_CLR - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U)
#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U)
#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U)
#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U)
#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_TOG - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U)
#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U)
#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U)
#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U)
#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
/*! @} */
/*! @name OUT_BUF - Output Frame Buffer Pointer */
/*! @{ */
#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_OUT_BUF_ADDR_SHIFT (0U)
#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
/*! @} */
/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
/*! @{ */
#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
#define PXP_OUT_BUF2_ADDR_SHIFT (0U)
#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
/*! @} */
/*! @name OUT_PITCH - Output Buffer Pitch */
/*! @{ */
#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_OUT_PITCH_PITCH_SHIFT (0U)
#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U)
#define PXP_OUT_PITCH_RSVD_SHIFT (16U)
#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK)
/*! @} */
/*! @name OUT_LRC - Output Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_LRC_Y_SHIFT (0U)
#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
#define PXP_OUT_LRC_RSVD0_MASK (0xC000U)
#define PXP_OUT_LRC_RSVD0_SHIFT (14U)
#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK)
#define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_LRC_X_SHIFT (16U)
#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U)
#define PXP_OUT_LRC_RSVD1_SHIFT (30U)
#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK)
/*! @} */
/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
/*! @{ */
#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
#define PXP_OUT_PS_ULC_Y_SHIFT (0U)
#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U)
#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U)
#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK)
#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
#define PXP_OUT_PS_ULC_X_SHIFT (16U)
#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U)
#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U)
#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK)
/*! @} */
/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_PS_LRC_Y_SHIFT (0U)
#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U)
#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U)
#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK)
#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_PS_LRC_X_SHIFT (16U)
#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U)
#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U)
#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK)
/*! @} */
/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
/*! @{ */
#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
#define PXP_OUT_AS_ULC_Y_SHIFT (0U)
#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U)
#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U)
#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK)
#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
#define PXP_OUT_AS_ULC_X_SHIFT (16U)
#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U)
#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U)
#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK)
/*! @} */
/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_AS_LRC_Y_SHIFT (0U)
#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U)
#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U)
#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK)
#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_AS_LRC_X_SHIFT (16U)
#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U)
#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U)
#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK)
/*! @} */
/*! @name PS_CTRL - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_FORMAT_MASK (0x1FU)
#define PXP_PS_CTRL_FORMAT_SHIFT (0U)
#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
#define PXP_PS_CTRL_WB_SWAP_MASK (0x20U)
#define PXP_PS_CTRL_WB_SWAP_SHIFT (5U)
#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
#define PXP_PS_CTRL_RSVD0_MASK (0xC0U)
#define PXP_PS_CTRL_RSVD0_SHIFT (6U)
#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK)
#define PXP_PS_CTRL_DECY_MASK (0x300U)
#define PXP_PS_CTRL_DECY_SHIFT (8U)
#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
#define PXP_PS_CTRL_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_DECX_SHIFT (10U)
#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U)
#define PXP_PS_CTRL_RSVD1_SHIFT (12U)
#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK)
/*! @} */
/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_SET_FORMAT_MASK (0x1FU)
#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x20U)
#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (5U)
#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
#define PXP_PS_CTRL_SET_RSVD0_MASK (0xC0U)
#define PXP_PS_CTRL_SET_RSVD0_SHIFT (6U)
#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK)
#define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
#define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U)
#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U)
#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK)
/*! @} */
/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x1FU)
#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x20U)
#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (5U)
#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
#define PXP_PS_CTRL_CLR_RSVD0_MASK (0xC0U)
#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (6U)
#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK)
#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U)
#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U)
#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK)
/*! @} */
/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x1FU)
#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x20U)
#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (5U)
#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
#define PXP_PS_CTRL_TOG_RSVD0_MASK (0xC0U)
#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (6U)
#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK)
#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U)
#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U)
#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK)
/*! @} */
/*! @name PS_BUF - PS Input Buffer Address */
/*! @{ */
#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_BUF_ADDR_SHIFT (0U)
#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
/*! @} */
/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
/*! @{ */
#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_UBUF_ADDR_SHIFT (0U)
#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
/*! @} */
/*! @name PS_VBUF - PS V/Cr Input Buffer Address */
/*! @{ */
#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_VBUF_ADDR_SHIFT (0U)
#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
/*! @} */
/*! @name PS_PITCH - Processed Surface Pitch */
/*! @{ */
#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_PS_PITCH_PITCH_SHIFT (0U)
#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U)
#define PXP_PS_PITCH_RSVD_SHIFT (16U)
#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK)
/*! @} */
/*! @name PS_BACKGROUND - PS Background Color */
/*! @{ */
#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U)
#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U)
#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK)
/*! @} */
/*! @name PS_SCALE - PS Scale Factor Register */
/*! @{ */
#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
#define PXP_PS_SCALE_XSCALE_SHIFT (0U)
#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
#define PXP_PS_SCALE_RSVD1_MASK (0x8000U)
#define PXP_PS_SCALE_RSVD1_SHIFT (15U)
#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK)
#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
#define PXP_PS_SCALE_YSCALE_SHIFT (16U)
#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U)
#define PXP_PS_SCALE_RSVD2_SHIFT (31U)
#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK)
/*! @} */
/*! @name PS_OFFSET - PS Scale Offset Register */
/*! @{ */
#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U)
#define PXP_PS_OFFSET_RSVD1_SHIFT (12U)
#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK)
#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U)
#define PXP_PS_OFFSET_RSVD2_SHIFT (28U)
#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK)
/*! @} */
/*! @name PS_CLRKEYLOW - PS Color Key Low */
/*! @{ */
#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U)
#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK)
/*! @} */
/*! @name PS_CLRKEYHIGH - PS Color Key High */
/*! @{ */
#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U)
#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK)
/*! @} */
/*! @name AS_CTRL - Alpha Surface Control */
/*! @{ */
#define PXP_AS_CTRL_RSVD0_MASK (0x1U)
#define PXP_AS_CTRL_RSVD0_SHIFT (0U)
#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK)
#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
#define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
#define PXP_AS_CTRL_FORMAT_SHIFT (4U)
#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
#define PXP_AS_CTRL_ALPHA_SHIFT (8U)
#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
#define PXP_AS_CTRL_ROP_MASK (0xF0000U)
#define PXP_AS_CTRL_ROP_SHIFT (16U)
#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U)
#define PXP_AS_CTRL_RSVD1_SHIFT (21U)
#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK)
/*! @} */
/*! @name AS_BUF - Alpha Surface Buffer Pointer */
/*! @{ */
#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_AS_BUF_ADDR_SHIFT (0U)
#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
/*! @} */
/*! @name AS_PITCH - Alpha Surface Pitch */
/*! @{ */
#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_AS_PITCH_PITCH_SHIFT (0U)
#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U)
#define PXP_AS_PITCH_RSVD_SHIFT (16U)
#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK)
/*! @} */
/*! @name AS_CLRKEYLOW - Overlay Color Key Low */
/*! @{ */
#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK)
/*! @} */
/*! @name AS_CLRKEYHIGH - Overlay Color Key High */
/*! @{ */
#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK)
/*! @} */
/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
#define PXP_CSC1_COEF0_C0_SHIFT (18U)
#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U)
#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U)
#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK)
#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
/*! @} */
/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
#define PXP_CSC1_COEF1_C4_SHIFT (0U)
#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U)
#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U)
#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK)
#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
#define PXP_CSC1_COEF1_C1_SHIFT (16U)
#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U)
#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U)
#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK)
/*! @} */
/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
#define PXP_CSC1_COEF2_C3_SHIFT (0U)
#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U)
#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U)
#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK)
#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
#define PXP_CSC1_COEF2_C2_SHIFT (16U)
#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U)
#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U)
#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK)
/*! @} */
/*! @name POWER - PXP Power Control Register */
/*! @{ */
#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
#define PXP_POWER_CTRL_MASK (0xFFFFF000U)
#define PXP_POWER_CTRL_SHIFT (12U)
#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK)
/*! @} */
/*! @name NEXT - Next Frame Pointer */
/*! @{ */
#define PXP_NEXT_ENABLED_MASK (0x1U)
#define PXP_NEXT_ENABLED_SHIFT (0U)
#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
#define PXP_NEXT_RSVD_MASK (0x2U)
#define PXP_NEXT_RSVD_SHIFT (1U)
#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK)
#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
#define PXP_NEXT_POINTER_SHIFT (2U)
#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
/*! @} */
/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
/*! @{ */
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U)
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U)
#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PXP_Register_Masks */
/* PXP - Peripheral instance base addresses */
/** Peripheral PXP base address */
#define PXP_BASE (0x402B4000u)
/** Peripheral PXP base pointer */
#define PXP ((PXP_Type *)PXP_BASE)
/** Array initializer of PXP peripheral base addresses */
#define PXP_BASE_ADDRS { PXP_BASE }
/** Array initializer of PXP peripheral base pointers */
#define PXP_BASE_PTRS { PXP }
/** Interrupt vectors for the PXP peripheral type */
#define PXP_IRQ0_IRQS { PXP_IRQn }
/*!
* @}
*/ /* end of group PXP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ROMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
* @{
*/
/** ROMC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[212];
__IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */
__IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */
uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */
__IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */
__IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_1[200];
__IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */
} ROMC_Type;
/* ----------------------------------------------------------------------------
-- ROMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ROMC_Register_Masks ROMC Register Masks
* @{
*/
/*! @name ROMPATCHD - ROMC Data Registers */
/*! @{ */
#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
#define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
/*! @} */
/* The count of ROMC_ROMPATCHD */
#define ROMC_ROMPATCHD_COUNT (8U)
/*! @name ROMPATCHCNTL - ROMC Control Register */
/*! @{ */
#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
/*! @} */
/*! @name ROMPATCHENL - ROMC Enable Register Low */
/*! @{ */
#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
/*! @} */
/*! @name ROMPATCHA - ROMC Address Registers */
/*! @{ */
#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
/*! @} */
/* The count of ROMC_ROMPATCHA */
#define ROMC_ROMPATCHA_COUNT (16U)
/*! @name ROMPATCHSR - ROMC Status Register */
/*! @{ */
#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
#define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
#define ROMC_ROMPATCHSR_SW_SHIFT (17U)
#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ROMC_Register_Masks */
/* ROMC - Peripheral instance base addresses */
/** Peripheral ROMC base address */
#define ROMC_BASE (0x40180000u)
/** Peripheral ROMC base pointer */
#define ROMC ((ROMC_Type *)ROMC_BASE)
/** Array initializer of ROMC peripheral base addresses */
#define ROMC_BASE_ADDRS { ROMC_BASE }
/** Array initializer of ROMC peripheral base pointers */
#define ROMC_BASE_PTRS { ROMC }
/*!
* @}
*/ /* end of group ROMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTWDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
* @{
*/
/** RTWDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */
__IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */
__IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
__IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */
} RTWDOG_Type;
/* ----------------------------------------------------------------------------
-- RTWDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
* @{
*/
/*! @name CS - Watchdog Control and Status Register */
/*! @{ */
#define RTWDOG_CS_STOP_MASK (0x1U)
#define RTWDOG_CS_STOP_SHIFT (0U)
#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
#define RTWDOG_CS_WAIT_MASK (0x2U)
#define RTWDOG_CS_WAIT_SHIFT (1U)
#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
#define RTWDOG_CS_DBG_MASK (0x4U)
#define RTWDOG_CS_DBG_SHIFT (2U)
#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
#define RTWDOG_CS_TST_MASK (0x18U)
#define RTWDOG_CS_TST_SHIFT (3U)
#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
#define RTWDOG_CS_UPDATE_MASK (0x20U)
#define RTWDOG_CS_UPDATE_SHIFT (5U)
#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
#define RTWDOG_CS_INT_MASK (0x40U)
#define RTWDOG_CS_INT_SHIFT (6U)
#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
#define RTWDOG_CS_EN_MASK (0x80U)
#define RTWDOG_CS_EN_SHIFT (7U)
#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
#define RTWDOG_CS_CLK_MASK (0x300U)
#define RTWDOG_CS_CLK_SHIFT (8U)
#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
#define RTWDOG_CS_RCS_MASK (0x400U)
#define RTWDOG_CS_RCS_SHIFT (10U)
#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
#define RTWDOG_CS_ULK_MASK (0x800U)
#define RTWDOG_CS_ULK_SHIFT (11U)
#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
#define RTWDOG_CS_PRES_MASK (0x1000U)
#define RTWDOG_CS_PRES_SHIFT (12U)
#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
#define RTWDOG_CS_CMD32EN_SHIFT (13U)
#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
#define RTWDOG_CS_FLG_MASK (0x4000U)
#define RTWDOG_CS_FLG_SHIFT (14U)
#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
#define RTWDOG_CS_WIN_MASK (0x8000U)
#define RTWDOG_CS_WIN_SHIFT (15U)
#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
/*! @} */
/*! @name CNT - Watchdog Counter Register */
/*! @{ */
#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
/*! @} */
/*! @name TOVAL - Watchdog Timeout Value Register */
/*! @{ */
#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
/*! @} */
/*! @name WIN - Watchdog Window Register */
/*! @{ */
#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
#define RTWDOG_WIN_WINLOW_SHIFT (0U)
#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group RTWDOG_Register_Masks */
/* RTWDOG - Peripheral instance base addresses */
/** Peripheral RTWDOG base address */
#define RTWDOG_BASE (0x400BC000u)
/** Peripheral RTWDOG base pointer */
#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
/** Array initializer of RTWDOG peripheral base addresses */
#define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
/** Array initializer of RTWDOG peripheral base pointers */
#define RTWDOG_BASE_PTRS { RTWDOG }
/** Interrupt vectors for the RTWDOG peripheral type */
#define RTWDOG_IRQS { RTWDOG_IRQn }
/* Extra definition */
#define RTWDOG_UPDATE_KEY (0xD928C520U)
#define RTWDOG_REFRESH_KEY (0xB480A602U)
/*!
* @}
*/ /* end of group RTWDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SEMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
* @{
*/
/** SEMC - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */
__IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */
__IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */
__IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */
__IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */
__IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */
__IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */
__IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */
__IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */
__IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */
__IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */
__IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */
__IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */
__IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */
__IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */
__IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */
__IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */
uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */
__IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */
__IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */
__IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */
uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */
__IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */
__IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */
uint8_t RESERVED_1[8];
__IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */
__IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */
__IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */
__IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */
__IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */
uint8_t RESERVED_2[12];
__I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */
uint8_t RESERVED_3[12];
__I uint32_t STS0; /**< Status register 0, offset: 0xC0 */
uint32_t STS1; /**< Status register 1, offset: 0xC4 */
__I uint32_t STS2; /**< Status register 2, offset: 0xC8 */
uint32_t STS3; /**< Status register 3, offset: 0xCC */
uint32_t STS4; /**< Status register 4, offset: 0xD0 */
uint32_t STS5; /**< Status register 5, offset: 0xD4 */
uint32_t STS6; /**< Status register 6, offset: 0xD8 */
uint32_t STS7; /**< Status register 7, offset: 0xDC */
uint32_t STS8; /**< Status register 8, offset: 0xE0 */
uint32_t STS9; /**< Status register 9, offset: 0xE4 */
uint32_t STS10; /**< Status register 10, offset: 0xE8 */
uint32_t STS11; /**< Status register 11, offset: 0xEC */
__I uint32_t STS12; /**< Status register 12, offset: 0xF0 */
uint32_t STS13; /**< Status register 13, offset: 0xF4 */
uint32_t STS14; /**< Status register 14, offset: 0xF8 */
uint32_t STS15; /**< Status register 15, offset: 0xFC */
} SEMC_Type;
/* ----------------------------------------------------------------------------
-- SEMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMC_Register_Masks SEMC Register Masks
* @{
*/
/*! @name MCR - Module Control Register */
/*! @{ */
#define SEMC_MCR_SWRST_MASK (0x1U)
#define SEMC_MCR_SWRST_SHIFT (0U)
#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
#define SEMC_MCR_MDIS_MASK (0x2U)
#define SEMC_MCR_MDIS_SHIFT (1U)
#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
#define SEMC_MCR_DQSMD_MASK (0x4U)
#define SEMC_MCR_DQSMD_SHIFT (2U)
#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
#define SEMC_MCR_WPOL0_MASK (0x40U)
#define SEMC_MCR_WPOL0_SHIFT (6U)
#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
#define SEMC_MCR_WPOL1_MASK (0x80U)
#define SEMC_MCR_WPOL1_SHIFT (7U)
#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
#define SEMC_MCR_CTO_MASK (0xFF0000U)
#define SEMC_MCR_CTO_SHIFT (16U)
#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
#define SEMC_MCR_BTO_MASK (0x1F000000U)
#define SEMC_MCR_BTO_SHIFT (24U)
#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
/*! @} */
/*! @name IOCR - IO Mux Control Register */
/*! @{ */
#define SEMC_IOCR_MUX_A8_MASK (0x7U)
#define SEMC_IOCR_MUX_A8_SHIFT (0U)
#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
#define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
#define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
#define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
#define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
#define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
#define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
#define SEMC_IOCR_MUX_RDY_SHIFT (15U)
#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
/*! @} */
/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */
/*! @{ */
#define SEMC_BMCR0_WQOS_MASK (0xFU)
#define SEMC_BMCR0_WQOS_SHIFT (0U)
#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
#define SEMC_BMCR0_WAGE_MASK (0xF0U)
#define SEMC_BMCR0_WAGE_SHIFT (4U)
#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
#define SEMC_BMCR0_WSH_MASK (0xFF00U)
#define SEMC_BMCR0_WSH_SHIFT (8U)
#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
#define SEMC_BMCR0_WRWS_SHIFT (16U)
#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
/*! @} */
/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */
/*! @{ */
#define SEMC_BMCR1_WQOS_MASK (0xFU)
#define SEMC_BMCR1_WQOS_SHIFT (0U)
#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
#define SEMC_BMCR1_WAGE_MASK (0xF0U)
#define SEMC_BMCR1_WAGE_SHIFT (4U)
#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
#define SEMC_BMCR1_WPH_MASK (0xFF00U)
#define SEMC_BMCR1_WPH_SHIFT (8U)
#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
#define SEMC_BMCR1_WRWS_SHIFT (16U)
#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
#define SEMC_BMCR1_WBR_SHIFT (24U)
#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
/*! @} */
/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */
/*! @{ */
#define SEMC_BR_VLD_MASK (0x1U)
#define SEMC_BR_VLD_SHIFT (0U)
#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
#define SEMC_BR_MS_MASK (0x3EU)
#define SEMC_BR_MS_SHIFT (1U)
#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
#define SEMC_BR_BA_MASK (0xFFFFF000U)
#define SEMC_BR_BA_SHIFT (12U)
#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
/*! @} */
/* The count of SEMC_BR */
#define SEMC_BR_COUNT (9U)
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
/*! @} */
/*! @name INTR - Interrupt Enable Register */
/*! @{ */
#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
#define SEMC_INTR_IPCMDERR_MASK (0x2U)
#define SEMC_INTR_IPCMDERR_SHIFT (1U)
#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
#define SEMC_INTR_AXICMDERR_MASK (0x4U)
#define SEMC_INTR_AXICMDERR_SHIFT (2U)
#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
#define SEMC_INTR_NDNOPEND_MASK (0x20U)
#define SEMC_INTR_NDNOPEND_SHIFT (5U)
#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
/*! @} */
/*! @name SDRAMCR0 - SDRAM control register 0 */
/*! @{ */
#define SEMC_SDRAMCR0_PS_MASK (0x1U)
#define SEMC_SDRAMCR0_PS_SHIFT (0U)
#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
#define SEMC_SDRAMCR0_BL_MASK (0x70U)
#define SEMC_SDRAMCR0_BL_SHIFT (4U)
#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
#define SEMC_SDRAMCR0_COL_MASK (0x300U)
#define SEMC_SDRAMCR0_COL_SHIFT (8U)
#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
#define SEMC_SDRAMCR0_CL_SHIFT (10U)
#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
/*! @} */
/*! @name SDRAMCR1 - SDRAM control register 1 */
/*! @{ */
#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
/*! @} */
/*! @name SDRAMCR2 - SDRAM control register 2 */
/*! @{ */
#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
/*! @} */
/*! @name SDRAMCR3 - SDRAM control register 3 */
/*! @{ */
#define SEMC_SDRAMCR3_REN_MASK (0x1U)
#define SEMC_SDRAMCR3_REN_SHIFT (0U)
#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
#define SEMC_SDRAMCR3_RT_SHIFT (16U)
#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
#define SEMC_SDRAMCR3_UT_SHIFT (24U)
#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
/*! @} */
/*! @name NANDCR0 - NAND control register 0 */
/*! @{ */
#define SEMC_NANDCR0_PS_MASK (0x1U)
#define SEMC_NANDCR0_PS_SHIFT (0U)
#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
#define SEMC_NANDCR0_BL_MASK (0x70U)
#define SEMC_NANDCR0_BL_SHIFT (4U)
#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
#define SEMC_NANDCR0_EDO_MASK (0x80U)
#define SEMC_NANDCR0_EDO_SHIFT (7U)
#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
#define SEMC_NANDCR0_COL_MASK (0x700U)
#define SEMC_NANDCR0_COL_SHIFT (8U)
#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
/*! @} */
/*! @name NANDCR1 - NAND control register 1 */
/*! @{ */
#define SEMC_NANDCR1_CES_MASK (0xFU)
#define SEMC_NANDCR1_CES_SHIFT (0U)
#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
#define SEMC_NANDCR1_CEH_MASK (0xF0U)
#define SEMC_NANDCR1_CEH_SHIFT (4U)
#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
#define SEMC_NANDCR1_WEL_MASK (0xF00U)
#define SEMC_NANDCR1_WEL_SHIFT (8U)
#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
#define SEMC_NANDCR1_WEH_MASK (0xF000U)
#define SEMC_NANDCR1_WEH_SHIFT (12U)
#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
#define SEMC_NANDCR1_REL_MASK (0xF0000U)
#define SEMC_NANDCR1_REL_SHIFT (16U)
#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
#define SEMC_NANDCR1_REH_MASK (0xF00000U)
#define SEMC_NANDCR1_REH_SHIFT (20U)
#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
#define SEMC_NANDCR1_TA_MASK (0xF000000U)
#define SEMC_NANDCR1_TA_SHIFT (24U)
#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
#define SEMC_NANDCR1_CEITV_SHIFT (28U)
#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
/*! @} */
/*! @name NANDCR2 - NAND control register 2 */
/*! @{ */
#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
#define SEMC_NANDCR2_TWHR_SHIFT (0U)
#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
#define SEMC_NANDCR2_TRHW_SHIFT (6U)
#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
#define SEMC_NANDCR2_TADL_SHIFT (12U)
#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
#define SEMC_NANDCR2_TRR_SHIFT (18U)
#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
#define SEMC_NANDCR2_TWB_SHIFT (24U)
#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
/*! @} */
/*! @name NANDCR3 - NAND control register 3 */
/*! @{ */
#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
/*! @} */
/*! @name NORCR0 - NOR control register 0 */
/*! @{ */
#define SEMC_NORCR0_PS_MASK (0x1U)
#define SEMC_NORCR0_PS_SHIFT (0U)
#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
#define SEMC_NORCR0_BL_MASK (0x70U)
#define SEMC_NORCR0_BL_SHIFT (4U)
#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
#define SEMC_NORCR0_AM_MASK (0x300U)
#define SEMC_NORCR0_AM_SHIFT (8U)
#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
#define SEMC_NORCR0_ADVP_MASK (0x400U)
#define SEMC_NORCR0_ADVP_SHIFT (10U)
#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
#define SEMC_NORCR0_COL_MASK (0xF000U)
#define SEMC_NORCR0_COL_SHIFT (12U)
#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
/*! @} */
/*! @name NORCR1 - NOR control register 1 */
/*! @{ */
#define SEMC_NORCR1_CES_MASK (0xFU)
#define SEMC_NORCR1_CES_SHIFT (0U)
#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
#define SEMC_NORCR1_CEH_MASK (0xF0U)
#define SEMC_NORCR1_CEH_SHIFT (4U)
#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
#define SEMC_NORCR1_AS_MASK (0xF00U)
#define SEMC_NORCR1_AS_SHIFT (8U)
#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
#define SEMC_NORCR1_AH_MASK (0xF000U)
#define SEMC_NORCR1_AH_SHIFT (12U)
#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
#define SEMC_NORCR1_WEL_MASK (0xF0000U)
#define SEMC_NORCR1_WEL_SHIFT (16U)
#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
#define SEMC_NORCR1_WEH_MASK (0xF00000U)
#define SEMC_NORCR1_WEH_SHIFT (20U)
#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
#define SEMC_NORCR1_REL_MASK (0xF000000U)
#define SEMC_NORCR1_REL_SHIFT (24U)
#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
#define SEMC_NORCR1_REH_MASK (0xF0000000U)
#define SEMC_NORCR1_REH_SHIFT (28U)
#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
/*! @} */
/*! @name NORCR2 - NOR control register 2 */
/*! @{ */
#define SEMC_NORCR2_WDS_MASK (0xFU)
#define SEMC_NORCR2_WDS_SHIFT (0U)
#define SEMC_NORCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDS_SHIFT)) & SEMC_NORCR2_WDS_MASK)
#define SEMC_NORCR2_WDH_MASK (0xF0U)
#define SEMC_NORCR2_WDH_SHIFT (4U)
#define SEMC_NORCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_WDH_SHIFT)) & SEMC_NORCR2_WDH_MASK)
#define SEMC_NORCR2_TA_MASK (0xF00U)
#define SEMC_NORCR2_TA_SHIFT (8U)
#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
#define SEMC_NORCR2_AWDH_MASK (0xF000U)
#define SEMC_NORCR2_AWDH_SHIFT (12U)
#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
#define SEMC_NORCR2_LC_MASK (0xF0000U)
#define SEMC_NORCR2_LC_SHIFT (16U)
#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
#define SEMC_NORCR2_RD_MASK (0xF00000U)
#define SEMC_NORCR2_RD_SHIFT (20U)
#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
#define SEMC_NORCR2_CEITV_SHIFT (24U)
#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
/*! @} */
/*! @name SRAMCR0 - SRAM control register 0 */
/*! @{ */
#define SEMC_SRAMCR0_PS_MASK (0x1U)
#define SEMC_SRAMCR0_PS_SHIFT (0U)
#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
#define SEMC_SRAMCR0_BL_MASK (0x70U)
#define SEMC_SRAMCR0_BL_SHIFT (4U)
#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
#define SEMC_SRAMCR0_AM_MASK (0x300U)
#define SEMC_SRAMCR0_AM_SHIFT (8U)
#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
#define SEMC_SRAMCR0_COL_MASK (0xF000U)
#define SEMC_SRAMCR0_COL_SHIFT (12U)
#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
/*! @} */
/*! @name SRAMCR1 - SRAM control register 1 */
/*! @{ */
#define SEMC_SRAMCR1_CES_MASK (0xFU)
#define SEMC_SRAMCR1_CES_SHIFT (0U)
#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
#define SEMC_SRAMCR1_CEH_SHIFT (4U)
#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
#define SEMC_SRAMCR1_AS_MASK (0xF00U)
#define SEMC_SRAMCR1_AS_SHIFT (8U)
#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
#define SEMC_SRAMCR1_AH_MASK (0xF000U)
#define SEMC_SRAMCR1_AH_SHIFT (12U)
#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
#define SEMC_SRAMCR1_WEL_SHIFT (16U)
#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
#define SEMC_SRAMCR1_WEH_SHIFT (20U)
#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
#define SEMC_SRAMCR1_REL_SHIFT (24U)
#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
#define SEMC_SRAMCR1_REH_SHIFT (28U)
#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
/*! @} */
/*! @name SRAMCR2 - SRAM control register 2 */
/*! @{ */
#define SEMC_SRAMCR2_WDS_MASK (0xFU)
#define SEMC_SRAMCR2_WDS_SHIFT (0U)
#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
#define SEMC_SRAMCR2_WDH_MASK (0xF0U)
#define SEMC_SRAMCR2_WDH_SHIFT (4U)
#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
#define SEMC_SRAMCR2_TA_MASK (0xF00U)
#define SEMC_SRAMCR2_TA_SHIFT (8U)
#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
#define SEMC_SRAMCR2_LC_MASK (0xF0000U)
#define SEMC_SRAMCR2_LC_SHIFT (16U)
#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
#define SEMC_SRAMCR2_RD_MASK (0xF00000U)
#define SEMC_SRAMCR2_RD_SHIFT (20U)
#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
/*! @} */
/*! @name DBICR0 - DBI-B control register 0 */
/*! @{ */
#define SEMC_DBICR0_PS_MASK (0x1U)
#define SEMC_DBICR0_PS_SHIFT (0U)
#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
#define SEMC_DBICR0_BL_MASK (0x70U)
#define SEMC_DBICR0_BL_SHIFT (4U)
#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
#define SEMC_DBICR0_COL_MASK (0xF000U)
#define SEMC_DBICR0_COL_SHIFT (12U)
#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
/*! @} */
/*! @name DBICR1 - DBI-B control register 1 */
/*! @{ */
#define SEMC_DBICR1_CES_MASK (0xFU)
#define SEMC_DBICR1_CES_SHIFT (0U)
#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
#define SEMC_DBICR1_CEH_MASK (0xF0U)
#define SEMC_DBICR1_CEH_SHIFT (4U)
#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
#define SEMC_DBICR1_WEL_MASK (0xF00U)
#define SEMC_DBICR1_WEL_SHIFT (8U)
#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
#define SEMC_DBICR1_WEH_MASK (0xF000U)
#define SEMC_DBICR1_WEH_SHIFT (12U)
#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
#define SEMC_DBICR1_REL_MASK (0xF0000U)
#define SEMC_DBICR1_REL_SHIFT (16U)
#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
#define SEMC_DBICR1_REH_MASK (0xF00000U)
#define SEMC_DBICR1_REH_SHIFT (20U)
#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
#define SEMC_DBICR1_CEITV_MASK (0xF000000U)
#define SEMC_DBICR1_CEITV_SHIFT (24U)
#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
#define SEMC_DBICR1_REL2_MASK (0x30000000U)
#define SEMC_DBICR1_REL2_SHIFT (28U)
#define SEMC_DBICR1_REL2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL2_SHIFT)) & SEMC_DBICR1_REL2_MASK)
#define SEMC_DBICR1_REH2_MASK (0xC0000000U)
#define SEMC_DBICR1_REH2_SHIFT (30U)
#define SEMC_DBICR1_REH2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH2_SHIFT)) & SEMC_DBICR1_REH2_MASK)
/*! @} */
/*! @name IPCR0 - IP Command control register 0 */
/*! @{ */
#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
#define SEMC_IPCR0_SA_SHIFT (0U)
#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
/*! @} */
/*! @name IPCR1 - IP Command control register 1 */
/*! @{ */
#define SEMC_IPCR1_DATSZ_MASK (0x7U)
#define SEMC_IPCR1_DATSZ_SHIFT (0U)
#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
/*! @} */
/*! @name IPCR2 - IP Command control register 2 */
/*! @{ */
#define SEMC_IPCR2_BM0_MASK (0x1U)
#define SEMC_IPCR2_BM0_SHIFT (0U)
#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
#define SEMC_IPCR2_BM1_MASK (0x2U)
#define SEMC_IPCR2_BM1_SHIFT (1U)
#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
#define SEMC_IPCR2_BM2_MASK (0x4U)
#define SEMC_IPCR2_BM2_SHIFT (2U)
#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
#define SEMC_IPCR2_BM3_MASK (0x8U)
#define SEMC_IPCR2_BM3_SHIFT (3U)
#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/*! @} */
/*! @name IPCMD - IP Command register */
/*! @{ */
#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
#define SEMC_IPCMD_CMD_SHIFT (0U)
#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
#define SEMC_IPCMD_KEY_SHIFT (16U)
#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
/*! @} */
/*! @name IPTXDAT - TX DATA register (for IP Command) */
/*! @{ */
#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
#define SEMC_IPTXDAT_DAT_SHIFT (0U)
#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
/*! @} */
/*! @name IPRXDAT - RX DATA register (for IP Command) */
/*! @{ */
#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
#define SEMC_IPRXDAT_DAT_SHIFT (0U)
#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
/*! @} */
/*! @name STS0 - Status register 0 */
/*! @{ */
#define SEMC_STS0_IDLE_MASK (0x1U)
#define SEMC_STS0_IDLE_SHIFT (0U)
#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
#define SEMC_STS0_NARDY_MASK (0x2U)
#define SEMC_STS0_NARDY_SHIFT (1U)
#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
/*! @} */
/*! @name STS2 - Status register 2 */
/*! @{ */
#define SEMC_STS2_NDWRPEND_MASK (0x8U)
#define SEMC_STS2_NDWRPEND_SHIFT (3U)
#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
/*! @} */
/*! @name STS12 - Status register 12 */
/*! @{ */
#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
#define SEMC_STS12_NDADDR_SHIFT (0U)
#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SEMC_Register_Masks */
/* SEMC - Peripheral instance base addresses */
/** Peripheral SEMC base address */
#define SEMC_BASE (0x402F0000u)
/** Peripheral SEMC base pointer */
#define SEMC ((SEMC_Type *)SEMC_BASE)
/** Array initializer of SEMC peripheral base addresses */
#define SEMC_BASE_ADDRS { SEMC_BASE }
/** Array initializer of SEMC peripheral base pointers */
#define SEMC_BASE_PTRS { SEMC }
/** Interrupt vectors for the SEMC peripheral type */
#define SEMC_IRQS { SEMC_IRQn }
/*!
* @}
*/ /* end of group SEMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
* @{
*/
/** SNVS - Register Layout Typedef */
typedef struct {
__IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */
__IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
__IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
__IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
__IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
__IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
__IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
__IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
__I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
__IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
__IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
__IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
__IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
__IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
__IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
__IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */
__IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
uint8_t RESERVED_0[4];
__IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */
__IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
__IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
__IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
__IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */
__I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
__I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
__IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
__IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
__IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
uint8_t RESERVED_1[4];
__IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
uint8_t RESERVED_2[96];
__IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_3[2776];
__I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
__I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
} SNVS_Type;
/* ----------------------------------------------------------------------------
-- SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Register_Masks SNVS Register Masks
* @{
*/
/*! @name HPLR - SNVS_HP Lock Register */
/*! @{ */
#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
#define SNVS_HPLR_MC_SL_MASK (0x10U)
#define SNVS_HPLR_MC_SL_SHIFT (4U)
#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
#define SNVS_HPLR_GPR_SL_MASK (0x20U)
#define SNVS_HPLR_GPR_SL_SHIFT (5U)
#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
#define SNVS_HPLR_MKS_SL_MASK (0x200U)
#define SNVS_HPLR_MKS_SL_SHIFT (9U)
#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
#define SNVS_HPLR_HAC_L_MASK (0x40000U)
#define SNVS_HPLR_HAC_L_SHIFT (18U)
#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
/*! @} */
/*! @name HPCOMR - SNVS_HP Command Register */
/*! @{ */
#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
/*! @} */
/*! @name HPCR - SNVS_HP Control Register */
/*! @{ */
#define SNVS_HPCR_RTC_EN_MASK (0x1U)
#define SNVS_HPCR_RTC_EN_SHIFT (0U)
#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
#define SNVS_HPCR_DIS_PI_MASK (0x4U)
#define SNVS_HPCR_DIS_PI_SHIFT (2U)
#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
#define SNVS_HPCR_PI_EN_MASK (0x8U)
#define SNVS_HPCR_PI_EN_SHIFT (3U)
#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
#define SNVS_HPCR_HP_TS_MASK (0x10000U)
#define SNVS_HPCR_HP_TS_SHIFT (16U)
#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
/*! @} */
/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
/*! @{ */
#define SNVS_HPSICR_SV0_EN_MASK (0x1U)
#define SNVS_HPSICR_SV0_EN_SHIFT (0U)
#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
#define SNVS_HPSICR_SV1_EN_MASK (0x2U)
#define SNVS_HPSICR_SV1_EN_SHIFT (1U)
#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
#define SNVS_HPSICR_SV2_EN_MASK (0x4U)
#define SNVS_HPSICR_SV2_EN_SHIFT (2U)
#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
#define SNVS_HPSICR_SV3_EN_MASK (0x8U)
#define SNVS_HPSICR_SV3_EN_SHIFT (3U)
#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
#define SNVS_HPSICR_SV4_EN_MASK (0x10U)
#define SNVS_HPSICR_SV4_EN_SHIFT (4U)
#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
#define SNVS_HPSICR_SV5_EN_MASK (0x20U)
#define SNVS_HPSICR_SV5_EN_SHIFT (5U)
#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
/*! @} */
/*! @name HPSVCR - SNVS_HP Security Violation Control Register */
/*! @{ */
#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
/*! @} */
/*! @name HPSR - SNVS_HP Status Register */
/*! @{ */
#define SNVS_HPSR_HPTA_MASK (0x1U)
#define SNVS_HPSR_HPTA_SHIFT (0U)
#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
#define SNVS_HPSR_PI_MASK (0x2U)
#define SNVS_HPSR_PI_SHIFT (1U)
#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
#define SNVS_HPSR_LPDIS_MASK (0x10U)
#define SNVS_HPSR_LPDIS_SHIFT (4U)
#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
#define SNVS_HPSR_BTN_MASK (0x40U)
#define SNVS_HPSR_BTN_SHIFT (6U)
#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
#define SNVS_HPSR_BI_MASK (0x80U)
#define SNVS_HPSR_BI_SHIFT (7U)
#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
/*! @} */
/*! @name HPSVSR - SNVS_HP Security Violation Status Register */
/*! @{ */
#define SNVS_HPSVSR_SV0_MASK (0x1U)
#define SNVS_HPSVSR_SV0_SHIFT (0U)
#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
#define SNVS_HPSVSR_SV1_MASK (0x2U)
#define SNVS_HPSVSR_SV1_SHIFT (1U)
#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
#define SNVS_HPSVSR_SV2_MASK (0x4U)
#define SNVS_HPSVSR_SV2_SHIFT (2U)
#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
#define SNVS_HPSVSR_SV3_MASK (0x8U)
#define SNVS_HPSVSR_SV3_SHIFT (3U)
#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
#define SNVS_HPSVSR_SV4_MASK (0x10U)
#define SNVS_HPSVSR_SV4_SHIFT (4U)
#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
#define SNVS_HPSVSR_SV5_MASK (0x20U)
#define SNVS_HPSVSR_SV5_SHIFT (5U)
#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
/*! @} */
/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
/*! @{ */
#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
/*! @} */
/*! @name HPHACR - SNVS_HP High Assurance Counter Register */
/*! @{ */
#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
/*! @} */
/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
/*! @{ */
#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
#define SNVS_HPRTCMR_RTC_SHIFT (0U)
#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
/*! @} */
/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
/*! @{ */
#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
#define SNVS_HPRTCLR_RTC_SHIFT (0U)
#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
/*! @} */
/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
/*! @{ */
#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
/*! @} */
/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
/*! @{ */
#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
/*! @} */
/*! @name LPLR - SNVS_LP Lock Register */
/*! @{ */
#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
#define SNVS_LPLR_MC_HL_MASK (0x10U)
#define SNVS_LPLR_MC_HL_SHIFT (4U)
#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
#define SNVS_LPLR_GPR_HL_MASK (0x20U)
#define SNVS_LPLR_GPR_HL_SHIFT (5U)
#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
#define SNVS_LPLR_MKS_HL_MASK (0x200U)
#define SNVS_LPLR_MKS_HL_SHIFT (9U)
#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
/*! @} */
/*! @name LPCR - SNVS_LP Control Register */
/*! @{ */
#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
#define SNVS_LPCR_MC_ENV_MASK (0x4U)
#define SNVS_LPCR_MC_ENV_SHIFT (2U)
#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
#define SNVS_LPCR_DP_EN_MASK (0x20U)
#define SNVS_LPCR_DP_EN_SHIFT (5U)
#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
#define SNVS_LPCR_TOP_MASK (0x40U)
#define SNVS_LPCR_TOP_SHIFT (6U)
#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
#define SNVS_LPCR_ON_TIME_SHIFT (20U)
#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
#define SNVS_LPCR_PK_EN_MASK (0x400000U)
#define SNVS_LPCR_PK_EN_SHIFT (22U)
#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
/*! @} */
/*! @name LPMKCR - SNVS_LP Master Key Control Register */
/*! @{ */
#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
/*! @} */
/*! @name LPSVCR - SNVS_LP Security Violation Control Register */
/*! @{ */
#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
/*! @} */
/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */
/*! @{ */
#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
#define SNVS_LPTDCR_ET1P_MASK (0x800U)
#define SNVS_LPTDCR_ET1P_SHIFT (11U)
#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
#define SNVS_LPTDCR_OSCB_SHIFT (28U)
#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
/*! @} */
/*! @name LPSR - SNVS_LP Status Register */
/*! @{ */
#define SNVS_LPSR_LPTA_MASK (0x1U)
#define SNVS_LPSR_LPTA_SHIFT (0U)
#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
#define SNVS_LPSR_SRTCR_MASK (0x2U)
#define SNVS_LPSR_SRTCR_SHIFT (1U)
#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
#define SNVS_LPSR_MCR_MASK (0x4U)
#define SNVS_LPSR_MCR_SHIFT (2U)
#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
#define SNVS_LPSR_PGD_MASK (0x8U)
#define SNVS_LPSR_PGD_SHIFT (3U)
#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
#define SNVS_LPSR_ET1D_MASK (0x200U)
#define SNVS_LPSR_ET1D_SHIFT (9U)
#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
#define SNVS_LPSR_ESVD_MASK (0x10000U)
#define SNVS_LPSR_ESVD_SHIFT (16U)
#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
#define SNVS_LPSR_EO_MASK (0x20000U)
#define SNVS_LPSR_EO_SHIFT (17U)
#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
#define SNVS_LPSR_SPO_MASK (0x40000U)
#define SNVS_LPSR_SPO_SHIFT (18U)
#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
#define SNVS_LPSR_SED_MASK (0x100000U)
#define SNVS_LPSR_SED_SHIFT (20U)
#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
#define SNVS_LPSR_LPNS_MASK (0x40000000U)
#define SNVS_LPSR_LPNS_SHIFT (30U)
#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
#define SNVS_LPSR_LPS_MASK (0x80000000U)
#define SNVS_LPSR_LPS_SHIFT (31U)
#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
/*! @} */
/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
/*! @{ */
#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
/*! @} */
/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
/*! @{ */
#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
/*! @} */
/*! @name LPTAR - SNVS_LP Time Alarm Register */
/*! @{ */
#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
#define SNVS_LPTAR_LPTA_SHIFT (0U)
#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
/*! @} */
/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
/*! @{ */
#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
/*! @} */
/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
/*! @{ */
#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
/*! @} */
/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
/*! @{ */
#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
#define SNVS_LPPGDR_PGD_SHIFT (0U)
#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
/*! @} */
/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
/*! @{ */
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
/*! @} */
/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
/*! @{ */
#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
#define SNVS_LPZMKR_ZMK_SHIFT (0U)
#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
/*! @} */
/* The count of SNVS_LPZMKR */
#define SNVS_LPZMKR_COUNT (8U)
/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
/*! @{ */
#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR_ALIAS */
#define SNVS_LPGPR_ALIAS_COUNT (4U)
/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */
/*! @{ */
#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_GPR_SHIFT (0U)
#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR */
#define SNVS_LPGPR_COUNT (8U)
/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
/*! @{ */
#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
/*! @} */
/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
/*! @{ */
#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SNVS_Register_Masks */
/* SNVS - Peripheral instance base addresses */
/** Peripheral SNVS base address */
#define SNVS_BASE (0x400D4000u)
/** Peripheral SNVS base pointer */
#define SNVS ((SNVS_Type *)SNVS_BASE)
/** Array initializer of SNVS peripheral base addresses */
#define SNVS_BASE_ADDRS { SNVS_BASE }
/** Array initializer of SNVS peripheral base pointers */
#define SNVS_BASE_PTRS { SNVS }
/** Interrupt vectors for the SNVS peripheral type */
#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
/*!
* @}
*/ /* end of group SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
* @{
*/
/** SPDIF - Register Layout Typedef */
typedef struct {
__IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */
__IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */
__IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */
__IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */
union { /* offset: 0x10 */
__O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */
__I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */
};
__I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */
__I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */
__I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */
__I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */
__I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */
__I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */
__O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */
__O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */
__IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
__IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
uint8_t RESERVED_0[8];
__I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */
uint8_t RESERVED_1[8];
__IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */
} SPDIF_Type;
/* ----------------------------------------------------------------------------
-- SPDIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPDIF_Register_Masks SPDIF Register Masks
* @{
*/
/*! @name SCR - SPDIF Configuration Register */
/*! @{ */
#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
#define SPDIF_SCR_TXSEL_MASK (0x1CU)
#define SPDIF_SCR_TXSEL_SHIFT (2U)
#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
#define SPDIF_SCR_VALCTRL_MASK (0x20U)
#define SPDIF_SCR_VALCTRL_SHIFT (5U)
#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
/*! @} */
/*! @name SRCD - CDText Control Register */
/*! @{ */
#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
/*! @} */
/*! @name SRPC - PhaseConfig Register */
/*! @{ */
#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
#define SPDIF_SRPC_LOCK_MASK (0x40U)
#define SPDIF_SRPC_LOCK_SHIFT (6U)
#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
/*! @} */
/*! @name SIE - InterruptEn Register */
/*! @{ */
#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
#define SPDIF_SIE_TXEM_MASK (0x2U)
#define SPDIF_SIE_TXEM_SHIFT (1U)
#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
#define SPDIF_SIE_UQERR_MASK (0x20U)
#define SPDIF_SIE_UQERR_SHIFT (5U)
#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
#define SPDIF_SIE_UQSYNC_MASK (0x40U)
#define SPDIF_SIE_UQSYNC_SHIFT (6U)
#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
#define SPDIF_SIE_QRXOV_MASK (0x80U)
#define SPDIF_SIE_QRXOV_SHIFT (7U)
#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
#define SPDIF_SIE_QRXFUL_MASK (0x100U)
#define SPDIF_SIE_QRXFUL_SHIFT (8U)
#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
#define SPDIF_SIE_URXOV_MASK (0x200U)
#define SPDIF_SIE_URXOV_SHIFT (9U)
#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
#define SPDIF_SIE_URXFUL_MASK (0x400U)
#define SPDIF_SIE_URXFUL_SHIFT (10U)
#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
#define SPDIF_SIE_BITERR_MASK (0x4000U)
#define SPDIF_SIE_BITERR_SHIFT (14U)
#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
#define SPDIF_SIE_SYMERR_MASK (0x8000U)
#define SPDIF_SIE_SYMERR_SHIFT (15U)
#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
#define SPDIF_SIE_CNEW_MASK (0x20000U)
#define SPDIF_SIE_CNEW_SHIFT (17U)
#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
#define SPDIF_SIE_TXRESYN_SHIFT (18U)
#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
#define SPDIF_SIE_TXUNOV_SHIFT (19U)
#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
#define SPDIF_SIE_LOCK_MASK (0x100000U)
#define SPDIF_SIE_LOCK_SHIFT (20U)
#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
/*! @} */
/*! @name SIC - InterruptClear Register */
/*! @{ */
#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
#define SPDIF_SIC_UQERR_MASK (0x20U)
#define SPDIF_SIC_UQERR_SHIFT (5U)
#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
#define SPDIF_SIC_UQSYNC_MASK (0x40U)
#define SPDIF_SIC_UQSYNC_SHIFT (6U)
#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
#define SPDIF_SIC_QRXOV_MASK (0x80U)
#define SPDIF_SIC_QRXOV_SHIFT (7U)
#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
#define SPDIF_SIC_URXOV_MASK (0x200U)
#define SPDIF_SIC_URXOV_SHIFT (9U)
#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
#define SPDIF_SIC_BITERR_MASK (0x4000U)
#define SPDIF_SIC_BITERR_SHIFT (14U)
#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
#define SPDIF_SIC_SYMERR_MASK (0x8000U)
#define SPDIF_SIC_SYMERR_SHIFT (15U)
#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
#define SPDIF_SIC_CNEW_MASK (0x20000U)
#define SPDIF_SIC_CNEW_SHIFT (17U)
#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
#define SPDIF_SIC_TXRESYN_SHIFT (18U)
#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
#define SPDIF_SIC_TXUNOV_SHIFT (19U)
#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
#define SPDIF_SIC_LOCK_MASK (0x100000U)
#define SPDIF_SIC_LOCK_SHIFT (20U)
#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
/*! @} */
/*! @name SIS - InterruptStat Register */
/*! @{ */
#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
#define SPDIF_SIS_TXEM_MASK (0x2U)
#define SPDIF_SIS_TXEM_SHIFT (1U)
#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
#define SPDIF_SIS_UQERR_MASK (0x20U)
#define SPDIF_SIS_UQERR_SHIFT (5U)
#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
#define SPDIF_SIS_UQSYNC_MASK (0x40U)
#define SPDIF_SIS_UQSYNC_SHIFT (6U)
#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
#define SPDIF_SIS_QRXOV_MASK (0x80U)
#define SPDIF_SIS_QRXOV_SHIFT (7U)
#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
#define SPDIF_SIS_QRXFUL_MASK (0x100U)
#define SPDIF_SIS_QRXFUL_SHIFT (8U)
#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
#define SPDIF_SIS_URXOV_MASK (0x200U)
#define SPDIF_SIS_URXOV_SHIFT (9U)
#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
#define SPDIF_SIS_URXFUL_MASK (0x400U)
#define SPDIF_SIS_URXFUL_SHIFT (10U)
#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
#define SPDIF_SIS_BITERR_MASK (0x4000U)
#define SPDIF_SIS_BITERR_SHIFT (14U)
#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
#define SPDIF_SIS_SYMERR_MASK (0x8000U)
#define SPDIF_SIS_SYMERR_SHIFT (15U)
#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
#define SPDIF_SIS_CNEW_MASK (0x20000U)
#define SPDIF_SIS_CNEW_SHIFT (17U)
#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
#define SPDIF_SIS_TXRESYN_SHIFT (18U)
#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
#define SPDIF_SIS_TXUNOV_SHIFT (19U)
#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
#define SPDIF_SIS_LOCK_MASK (0x100000U)
#define SPDIF_SIS_LOCK_SHIFT (20U)
#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
/*! @} */
/*! @name SRL - SPDIFRxLeft Register */
/*! @{ */
#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
/*! @} */
/*! @name SRR - SPDIFRxRight Register */
/*! @{ */
#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
/*! @} */
/*! @name SRCSH - SPDIFRxCChannel_h Register */
/*! @{ */
#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
/*! @} */
/*! @name SRCSL - SPDIFRxCChannel_l Register */
/*! @{ */
#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
/*! @} */
/*! @name SRU - UchannelRx Register */
/*! @{ */
#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
/*! @} */
/*! @name SRQ - QchannelRx Register */
/*! @{ */
#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
/*! @} */
/*! @name STL - SPDIFTxLeft Register */
/*! @{ */
#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
/*! @} */
/*! @name STR - SPDIFTxRight Register */
/*! @{ */
#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
/*! @} */
/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
/*! @{ */
#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
/*! @} */
/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
/*! @{ */
#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
/*! @} */
/*! @name SRFM - FreqMeas Register */
/*! @{ */
#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
/*! @} */
/*! @name STC - SPDIFTxClk Register */
/*! @{ */
#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SPDIF_Register_Masks */
/* SPDIF - Peripheral instance base addresses */
/** Peripheral SPDIF base address */
#define SPDIF_BASE (0x40380000u)
/** Peripheral SPDIF base pointer */
#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
/** Array initializer of SPDIF peripheral base addresses */
#define SPDIF_BASE_ADDRS { SPDIF_BASE }
/** Array initializer of SPDIF peripheral base pointers */
#define SPDIF_BASE_PTRS { SPDIF }
/** Interrupt vectors for the SPDIF peripheral type */
#define SPDIF_IRQS { SPDIF_IRQn }
/*!
* @}
*/ /* end of group SPDIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
* @{
*/
/** SRC - Register Layout Typedef */
typedef struct {
__IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */
__I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */
__IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */
uint8_t RESERVED_0[16];
__I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */
__IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */
} SRC_Type;
/* ----------------------------------------------------------------------------
-- SRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Register_Masks SRC Register Masks
* @{
*/
/*! @name SCR - SRC Control Register */
/*! @{ */
#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
#define SRC_SCR_CORE0_RST_MASK (0x2000U)
#define SRC_SCR_CORE0_RST_SHIFT (13U)
#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
/*! @} */
/*! @name SBMR1 - SRC Boot Mode Register 1 */
/*! @{ */
#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
/*! @} */
/*! @name SRSR - SRC Reset Status Register */
/*! @{ */
#define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
#define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
#define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
#define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
/*! @} */
/*! @name SBMR2 - SRC Boot Mode Register 2 */
/*! @{ */
#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
#define SRC_SBMR2_BMOD_MASK (0x3000000U)
#define SRC_SBMR2_BMOD_SHIFT (24U)
#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
/*! @} */
/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */
/*! @{ */
#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
/*! @} */
/* The count of SRC_GPR */
#define SRC_GPR_COUNT (10U)
/*!
* @}
*/ /* end of group SRC_Register_Masks */
/* SRC - Peripheral instance base addresses */
/** Peripheral SRC base address */
#define SRC_BASE (0x400F8000u)
/** Peripheral SRC base pointer */
#define SRC ((SRC_Type *)SRC_BASE)
/** Array initializer of SRC peripheral base addresses */
#define SRC_BASE_ADDRS { SRC_BASE }
/** Array initializer of SRC peripheral base pointers */
#define SRC_BASE_PTRS { SRC }
/** Interrupt vectors for the SRC peripheral type */
#define SRC_IRQS { SRC_IRQn }
/* Backward compatibility */
#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
/* Extra definition */
#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
| SRC_SRSR_JTAG_SW_RST_MASK \
| SRC_SRSR_JTAG_RST_B_MASK \
| SRC_SRSR_WDOG_RST_B_MASK \
| SRC_SRSR_IPP_USER_RESET_B_MASK \
| SRC_SRSR_CSU_RESET_B_MASK \
| SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
| SRC_SRSR_IPP_RESET_B_MASK)
/*!
* @}
*/ /* end of group SRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TEMPMON Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
* @{
*/
/** TEMPMON - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[384];
__IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */
__IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */
__IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */
__IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */
__IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */
__IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */
__IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */
__IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */
uint8_t RESERVED_1[240];
__IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */
__IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */
__IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */
__IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */
} TEMPMON_Type;
/* ----------------------------------------------------------------------------
-- TEMPMON Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
* @{
*/
/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */
/*! @{ */
#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */
/*! @{ */
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */
/*! @{ */
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */
/*! @{ */
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */
/*! @{ */
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
/*! @} */
/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */
/*! @{ */
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
/*! @} */
/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */
/*! @{ */
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
/*! @} */
/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */
/*! @{ */
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
/*! @} */
/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */
/*! @{ */
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */
/*! @{ */
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */
/*! @{ */
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
/*! @} */
/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */
/*! @{ */
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TEMPMON_Register_Masks */
/* TEMPMON - Peripheral instance base addresses */
/** Peripheral TEMPMON base address */
#define TEMPMON_BASE (0x400D8000u)
/** Peripheral TEMPMON base pointer */
#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
/** Array initializer of TEMPMON peripheral base addresses */
#define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
/** Array initializer of TEMPMON peripheral base pointers */
#define TEMPMON_BASE_PTRS { TEMPMON }
/*!
* @}
*/ /* end of group TEMPMON_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
* @{
*/
/** TMR - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x20 */
__IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
__IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
__IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
__IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
__IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
__IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
__IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
__IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
__IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
__IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
__IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
__IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
uint8_t RESERVED_0[4];
__IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
} CHANNEL[4];
} TMR_Type;
/* ----------------------------------------------------------------------------
-- TMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMR_Register_Masks TMR Register Masks
* @{
*/
/*! @name COMP1 - Timer Channel Compare Register 1 */
/*! @{ */
#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
/*! @} */
/* The count of TMR_COMP1 */
#define TMR_COMP1_COUNT (4U)
/*! @name COMP2 - Timer Channel Compare Register 2 */
/*! @{ */
#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
/*! @} */
/* The count of TMR_COMP2 */
#define TMR_COMP2_COUNT (4U)
/*! @name CAPT - Timer Channel Capture Register */
/*! @{ */
#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
#define TMR_CAPT_CAPTURE_SHIFT (0U)
#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
/*! @} */
/* The count of TMR_CAPT */
#define TMR_CAPT_COUNT (4U)
/*! @name LOAD - Timer Channel Load Register */
/*! @{ */
#define TMR_LOAD_LOAD_MASK (0xFFFFU)
#define TMR_LOAD_LOAD_SHIFT (0U)
#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
/*! @} */
/* The count of TMR_LOAD */
#define TMR_LOAD_COUNT (4U)
/*! @name HOLD - Timer Channel Hold Register */
/*! @{ */
#define TMR_HOLD_HOLD_MASK (0xFFFFU)
#define TMR_HOLD_HOLD_SHIFT (0U)
#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
/*! @} */
/* The count of TMR_HOLD */
#define TMR_HOLD_COUNT (4U)
/*! @name CNTR - Timer Channel Counter Register */
/*! @{ */
#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
#define TMR_CNTR_COUNTER_SHIFT (0U)
#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
/*! @} */
/* The count of TMR_CNTR */
#define TMR_CNTR_COUNT (4U)
/*! @name CTRL - Timer Channel Control Register */
/*! @{ */
#define TMR_CTRL_OUTMODE_MASK (0x7U)
#define TMR_CTRL_OUTMODE_SHIFT (0U)
#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
#define TMR_CTRL_COINIT_MASK (0x8U)
#define TMR_CTRL_COINIT_SHIFT (3U)
#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
#define TMR_CTRL_DIR_MASK (0x10U)
#define TMR_CTRL_DIR_SHIFT (4U)
#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
#define TMR_CTRL_LENGTH_MASK (0x20U)
#define TMR_CTRL_LENGTH_SHIFT (5U)
#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
#define TMR_CTRL_ONCE_MASK (0x40U)
#define TMR_CTRL_ONCE_SHIFT (6U)
#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
#define TMR_CTRL_SCS_MASK (0x180U)
#define TMR_CTRL_SCS_SHIFT (7U)
#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
#define TMR_CTRL_PCS_MASK (0x1E00U)
#define TMR_CTRL_PCS_SHIFT (9U)
#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
#define TMR_CTRL_CM_MASK (0xE000U)
#define TMR_CTRL_CM_SHIFT (13U)
#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
/*! @} */
/* The count of TMR_CTRL */
#define TMR_CTRL_COUNT (4U)
/*! @name SCTRL - Timer Channel Status and Control Register */
/*! @{ */
#define TMR_SCTRL_OEN_MASK (0x1U)
#define TMR_SCTRL_OEN_SHIFT (0U)
#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
#define TMR_SCTRL_OPS_MASK (0x2U)
#define TMR_SCTRL_OPS_SHIFT (1U)
#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
#define TMR_SCTRL_FORCE_MASK (0x4U)
#define TMR_SCTRL_FORCE_SHIFT (2U)
#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
#define TMR_SCTRL_VAL_MASK (0x8U)
#define TMR_SCTRL_VAL_SHIFT (3U)
#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
#define TMR_SCTRL_EEOF_MASK (0x10U)
#define TMR_SCTRL_EEOF_SHIFT (4U)
#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
#define TMR_SCTRL_MSTR_MASK (0x20U)
#define TMR_SCTRL_MSTR_SHIFT (5U)
#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
#define TMR_SCTRL_INPUT_MASK (0x100U)
#define TMR_SCTRL_INPUT_SHIFT (8U)
#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
#define TMR_SCTRL_IPS_MASK (0x200U)
#define TMR_SCTRL_IPS_SHIFT (9U)
#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
#define TMR_SCTRL_IEFIE_MASK (0x400U)
#define TMR_SCTRL_IEFIE_SHIFT (10U)
#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
#define TMR_SCTRL_IEF_MASK (0x800U)
#define TMR_SCTRL_IEF_SHIFT (11U)
#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
#define TMR_SCTRL_TOFIE_MASK (0x1000U)
#define TMR_SCTRL_TOFIE_SHIFT (12U)
#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
#define TMR_SCTRL_TOF_MASK (0x2000U)
#define TMR_SCTRL_TOF_SHIFT (13U)
#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
#define TMR_SCTRL_TCFIE_MASK (0x4000U)
#define TMR_SCTRL_TCFIE_SHIFT (14U)
#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
#define TMR_SCTRL_TCF_MASK (0x8000U)
#define TMR_SCTRL_TCF_SHIFT (15U)
#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
/*! @} */
/* The count of TMR_SCTRL */
#define TMR_SCTRL_COUNT (4U)
/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
/*! @{ */
#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
/*! @} */
/* The count of TMR_CMPLD1 */
#define TMR_CMPLD1_COUNT (4U)
/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
/*! @{ */
#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
/*! @} */
/* The count of TMR_CMPLD2 */
#define TMR_CMPLD2_COUNT (4U)
/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
/*! @{ */
#define TMR_CSCTRL_CL1_MASK (0x3U)
#define TMR_CSCTRL_CL1_SHIFT (0U)
#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
#define TMR_CSCTRL_CL2_MASK (0xCU)
#define TMR_CSCTRL_CL2_SHIFT (2U)
#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
#define TMR_CSCTRL_TCF1_MASK (0x10U)
#define TMR_CSCTRL_TCF1_SHIFT (4U)
#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
#define TMR_CSCTRL_TCF2_MASK (0x20U)
#define TMR_CSCTRL_TCF2_SHIFT (5U)
#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
#define TMR_CSCTRL_UP_MASK (0x200U)
#define TMR_CSCTRL_UP_SHIFT (9U)
#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
#define TMR_CSCTRL_TCI_MASK (0x400U)
#define TMR_CSCTRL_TCI_SHIFT (10U)
#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
#define TMR_CSCTRL_ROC_MASK (0x800U)
#define TMR_CSCTRL_ROC_SHIFT (11U)
#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
#define TMR_CSCTRL_FAULT_MASK (0x2000U)
#define TMR_CSCTRL_FAULT_SHIFT (13U)
#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
/*! @} */
/* The count of TMR_CSCTRL */
#define TMR_CSCTRL_COUNT (4U)
/*! @name FILT - Timer Channel Input Filter Register */
/*! @{ */
#define TMR_FILT_FILT_PER_MASK (0xFFU)
#define TMR_FILT_FILT_PER_SHIFT (0U)
#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
#define TMR_FILT_FILT_CNT_MASK (0x700U)
#define TMR_FILT_FILT_CNT_SHIFT (8U)
#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
/*! @} */
/* The count of TMR_FILT */
#define TMR_FILT_COUNT (4U)
/*! @name DMA - Timer Channel DMA Enable Register */
/*! @{ */
#define TMR_DMA_IEFDE_MASK (0x1U)
#define TMR_DMA_IEFDE_SHIFT (0U)
#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
#define TMR_DMA_CMPLD1DE_MASK (0x2U)
#define TMR_DMA_CMPLD1DE_SHIFT (1U)
#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
#define TMR_DMA_CMPLD2DE_MASK (0x4U)
#define TMR_DMA_CMPLD2DE_SHIFT (2U)
#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
/*! @} */
/* The count of TMR_DMA */
#define TMR_DMA_COUNT (4U)
/*! @name ENBL - Timer Channel Enable Register */
/*! @{ */
#define TMR_ENBL_ENBL_MASK (0xFU)
#define TMR_ENBL_ENBL_SHIFT (0U)
#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
/*! @} */
/* The count of TMR_ENBL */
#define TMR_ENBL_COUNT (4U)
/*!
* @}
*/ /* end of group TMR_Register_Masks */
/* TMR - Peripheral instance base addresses */
/** Peripheral TMR1 base address */
#define TMR1_BASE (0x401DC000u)
/** Peripheral TMR1 base pointer */
#define TMR1 ((TMR_Type *)TMR1_BASE)
/** Peripheral TMR2 base address */
#define TMR2_BASE (0x401E0000u)
/** Peripheral TMR2 base pointer */
#define TMR2 ((TMR_Type *)TMR2_BASE)
/** Peripheral TMR3 base address */
#define TMR3_BASE (0x401E4000u)
/** Peripheral TMR3 base pointer */
#define TMR3 ((TMR_Type *)TMR3_BASE)
/** Peripheral TMR4 base address */
#define TMR4_BASE (0x401E8000u)
/** Peripheral TMR4 base pointer */
#define TMR4 ((TMR_Type *)TMR4_BASE)
/** Array initializer of TMR peripheral base addresses */
#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/** Array initializer of TMR peripheral base pointers */
#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
/** Interrupt vectors for the TMR peripheral type */
#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
/*!
* @}
*/ /* end of group TMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TRNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
* @{
*/
/** TRNG - Register Layout Typedef */
typedef struct {
__IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */
__IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */
__IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */
union { /* offset: 0xC */
__IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */
__I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */
};
__IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */
union { /* offset: 0x14 */
__IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */
__I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */
};
__IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */
union { /* offset: 0x1C */
__I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */
__IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */
};
union { /* offset: 0x20 */
__I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */
__IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */
};
union { /* offset: 0x24 */
__I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
__IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
};
union { /* offset: 0x28 */
__I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
__IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
};
union { /* offset: 0x2C */
__I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
__IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
};
union { /* offset: 0x30 */
__I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
__IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
};
union { /* offset: 0x34 */
__I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
__IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
};
union { /* offset: 0x38 */
__I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
__IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
};
__I uint32_t STATUS; /**< Status Register, offset: 0x3C */
__I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
__I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
__I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
__I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
__I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
__I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
__I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
__I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
__I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
__IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */
__IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */
__IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */
__I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */
uint8_t RESERVED_0[64];
__I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */
__I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */
} TRNG_Type;
/* ----------------------------------------------------------------------------
-- TRNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRNG_Register_Masks TRNG Register Masks
* @{
*/
/*! @name MCTL - Miscellaneous Control Register */
/*! @{ */
#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
#define TRNG_MCTL_UNUSED4_MASK (0x10U)
#define TRNG_MCTL_UNUSED4_SHIFT (4U)
#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
#define TRNG_MCTL_UNUSED5_MASK (0x20U)
#define TRNG_MCTL_UNUSED5_SHIFT (5U)
#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
#define TRNG_MCTL_RST_DEF_MASK (0x40U)
#define TRNG_MCTL_RST_DEF_SHIFT (6U)
#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
#define TRNG_MCTL_TST_OUT_MASK (0x800U)
#define TRNG_MCTL_TST_OUT_SHIFT (11U)
#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
#define TRNG_MCTL_ERR_MASK (0x1000U)
#define TRNG_MCTL_ERR_SHIFT (12U)
#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
#define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
#define TRNG_MCTL_PRGM_MASK (0x10000U)
#define TRNG_MCTL_PRGM_SHIFT (16U)
#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
/*! @} */
/*! @name SCMISC - Statistical Check Miscellaneous Register */
/*! @{ */
#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
/*! @} */
/*! @name PKRRNG - Poker Range Register */
/*! @{ */
#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
/*! @} */
/*! @name PKRMAX - Poker Maximum Limit Register */
/*! @{ */
#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
/*! @} */
/*! @name PKRSQ - Poker Square Calculation Result Register */
/*! @{ */
#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
/*! @} */
/*! @name SDCTL - Seed Control Register */
/*! @{ */
#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
/*! @} */
/*! @name SBLIM - Sparse Bit Limit Register */
/*! @{ */
#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
/*! @} */
/*! @name TOTSAM - Total Samples Register */
/*! @{ */
#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
/*! @} */
/*! @name FRQMIN - Frequency Count Minimum Limit Register */
/*! @{ */
#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
/*! @} */
/*! @name FRQCNT - Frequency Count Register */
/*! @{ */
#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
/*! @} */
/*! @name FRQMAX - Frequency Count Maximum Limit Register */
/*! @{ */
#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
/*! @} */
/*! @name SCMC - Statistical Check Monobit Count Register */
/*! @{ */
#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
#define TRNG_SCMC_MONO_CT_SHIFT (0U)
#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
/*! @} */
/*! @name SCML - Statistical Check Monobit Limit Register */
/*! @{ */
#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
#define TRNG_SCML_MONO_MAX_SHIFT (0U)
#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
#define TRNG_SCML_MONO_RNG_SHIFT (16U)
#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
/*! @} */
/*! @name SCR1C - Statistical Check Run Length 1 Count Register */
/*! @{ */
#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
/*! @} */
/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
/*! @{ */
#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
/*! @} */
/*! @name SCR2C - Statistical Check Run Length 2 Count Register */
/*! @{ */
#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
/*! @} */
/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
/*! @{ */
#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
/*! @} */
/*! @name SCR3C - Statistical Check Run Length 3 Count Register */
/*! @{ */
#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
/*! @} */
/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
/*! @{ */
#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
/*! @} */
/*! @name SCR4C - Statistical Check Run Length 4 Count Register */
/*! @{ */
#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
/*! @} */
/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
/*! @{ */
#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
/*! @} */
/*! @name SCR5C - Statistical Check Run Length 5 Count Register */
/*! @{ */
#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
/*! @} */
/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
/*! @{ */
#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
/*! @} */
/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
/*! @{ */
#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
/*! @} */
/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
/*! @{ */
#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
/*! @} */
/*! @name STATUS - Status Register */
/*! @{ */
#define TRNG_STATUS_TF1BR0_MASK (0x1U)
#define TRNG_STATUS_TF1BR0_SHIFT (0U)
#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
#define TRNG_STATUS_TF1BR1_MASK (0x2U)
#define TRNG_STATUS_TF1BR1_SHIFT (1U)
#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
#define TRNG_STATUS_TF2BR0_MASK (0x4U)
#define TRNG_STATUS_TF2BR0_SHIFT (2U)
#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
#define TRNG_STATUS_TF2BR1_MASK (0x8U)
#define TRNG_STATUS_TF2BR1_SHIFT (3U)
#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
#define TRNG_STATUS_TF3BR0_MASK (0x10U)
#define TRNG_STATUS_TF3BR0_SHIFT (4U)
#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
#define TRNG_STATUS_TF3BR1_MASK (0x20U)
#define TRNG_STATUS_TF3BR1_SHIFT (5U)
#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
#define TRNG_STATUS_TF4BR0_MASK (0x40U)
#define TRNG_STATUS_TF4BR0_SHIFT (6U)
#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
#define TRNG_STATUS_TF4BR1_MASK (0x80U)
#define TRNG_STATUS_TF4BR1_SHIFT (7U)
#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
#define TRNG_STATUS_TF5BR0_MASK (0x100U)
#define TRNG_STATUS_TF5BR0_SHIFT (8U)
#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
#define TRNG_STATUS_TF5BR1_MASK (0x200U)
#define TRNG_STATUS_TF5BR1_SHIFT (9U)
#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
#define TRNG_STATUS_TFSB_MASK (0x1000U)
#define TRNG_STATUS_TFSB_SHIFT (12U)
#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
#define TRNG_STATUS_TFLR_MASK (0x2000U)
#define TRNG_STATUS_TFLR_SHIFT (13U)
#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
#define TRNG_STATUS_TFP_MASK (0x4000U)
#define TRNG_STATUS_TFP_SHIFT (14U)
#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
#define TRNG_STATUS_TFMB_MASK (0x8000U)
#define TRNG_STATUS_TFMB_SHIFT (15U)
#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
/*! @} */
/*! @name ENT - Entropy Read Register */
/*! @{ */
#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
#define TRNG_ENT_ENT_SHIFT (0U)
#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
/*! @} */
/* The count of TRNG_ENT */
#define TRNG_ENT_COUNT (16U)
/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
/*! @{ */
#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
/*! @} */
/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
/*! @{ */
#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
/*! @} */
/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
/*! @{ */
#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
/*! @} */
/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
/*! @{ */
#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
/*! @} */
/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
/*! @{ */
#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
/*! @} */
/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
/*! @{ */
#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
/*! @} */
/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
/*! @{ */
#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
/*! @} */
/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
/*! @{ */
#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
/*! @} */
/*! @name SEC_CFG - Security Configuration Register */
/*! @{ */
#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
/*! @} */
/*! @name INT_CTRL - Interrupt Control Register */
/*! @{ */
#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
/*! @} */
/*! @name INT_MASK - Mask Register */
/*! @{ */
#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
/*! @} */
/*! @name VID1 - Version ID Register (MS) */
/*! @{ */
#define TRNG_VID1_MIN_REV_MASK (0xFFU)
#define TRNG_VID1_MIN_REV_SHIFT (0U)
#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
#define TRNG_VID1_MAJ_REV_SHIFT (8U)
#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
#define TRNG_VID1_IP_ID_SHIFT (16U)
#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
/*! @} */
/*! @name VID2 - Version ID Register (LS) */
/*! @{ */
#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
#define TRNG_VID2_ECO_REV_SHIFT (8U)
#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
#define TRNG_VID2_INTG_OPT_SHIFT (16U)
#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
#define TRNG_VID2_ERA_MASK (0xFF000000U)
#define TRNG_VID2_ERA_SHIFT (24U)
#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TRNG_Register_Masks */
/* TRNG - Peripheral instance base addresses */
/** Peripheral TRNG base address */
#define TRNG_BASE (0x400CC000u)
/** Peripheral TRNG base pointer */
#define TRNG ((TRNG_Type *)TRNG_BASE)
/** Array initializer of TRNG peripheral base addresses */
#define TRNG_BASE_ADDRS { TRNG_BASE }
/** Array initializer of TRNG peripheral base pointers */
#define TRNG_BASE_PTRS { TRNG }
/** Interrupt vectors for the TRNG peripheral type */
#define TRNG_IRQS { TRNG_IRQn }
/*!
* @}
*/ /* end of group TRNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer
* @{
*/
/** TSC - Register Layout Typedef */
typedef struct {
__IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */
uint8_t RESERVED_0[12];
__IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */
uint8_t RESERVED_1[12];
__IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */
uint8_t RESERVED_2[12];
__I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */
uint8_t RESERVED_3[12];
__IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */
uint8_t RESERVED_4[12];
__IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */
uint8_t RESERVED_5[12];
__IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */
uint8_t RESERVED_6[12];
__IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */
uint8_t RESERVED_7[12];
__IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */
} TSC_Type;
/* ----------------------------------------------------------------------------
-- TSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSC_Register_Masks TSC Register Masks
* @{
*/
/*! @name BASIC_SETTING - */
/*! @{ */
#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U)
#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U)
#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
/*! @} */
/*! @name PRE_CHARGE_TIME - */
/*! @{ */
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
/*! @} */
/*! @name FLOW_CONTROL - Flow Control */
/*! @{ */
#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
/*! @} */
/*! @name MEASEURE_VALUE - Measure Value */
/*! @{ */
#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
/*! @} */
/*! @name INT_EN - Interrupt Enable */
/*! @{ */
#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
/*! @} */
/*! @name INT_SIG_EN - Interrupt Signal Enable */
/*! @{ */
#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
/*! @} */
/*! @name INT_STATUS - Intterrupt Status */
/*! @{ */
#define TSC_INT_STATUS_MEASURE_MASK (0x1U)
#define TSC_INT_STATUS_MEASURE_SHIFT (0U)
#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
#define TSC_INT_STATUS_DETECT_MASK (0x10U)
#define TSC_INT_STATUS_DETECT_SHIFT (4U)
#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
#define TSC_INT_STATUS_VALID_MASK (0x100U)
#define TSC_INT_STATUS_VALID_SHIFT (8U)
#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
/*! @} */
/*! @name DEBUG_MODE - */
/*! @{ */
#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
/*! @} */
/*! @name DEBUG_MODE2 - */
/*! @{ */
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TSC_Register_Masks */
/* TSC - Peripheral instance base addresses */
/** Peripheral TSC base address */
#define TSC_BASE (0x400E0000u)
/** Peripheral TSC base pointer */
#define TSC ((TSC_Type *)TSC_BASE)
/** Array initializer of TSC peripheral base addresses */
#define TSC_BASE_ADDRS { TSC_BASE }
/** Array initializer of TSC peripheral base pointers */
#define TSC_BASE_PTRS { TSC }
/** Interrupt vectors for the TSC peripheral type */
#define TSC_IRQS { TSC_DIG_IRQn }
/* Backward compatibility */
#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK
#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT
#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x)
/*!
* @}
*/ /* end of group TSC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint32_t ID; /**< Identification register, offset: 0x0 */
__I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */
__I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */
__I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */
__I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */
__I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */
uint8_t RESERVED_0[104];
__IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */
__IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */
__IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */
__IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */
__IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */
uint8_t RESERVED_1[108];
__I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */
uint8_t RESERVED_2[1];
__I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */
__I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */
__I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */
uint8_t RESERVED_3[20];
__I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */
uint8_t RESERVED_4[2];
__I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
uint8_t RESERVED_5[24];
__IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
__IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
__IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */
__IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */
uint8_t RESERVED_6[4];
union { /* offset: 0x154 */
__IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */
__IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */
};
union { /* offset: 0x158 */
__IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */
__IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */
};
uint8_t RESERVED_7[4];
__IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */
__IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */
uint8_t RESERVED_8[16];
__IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */
__IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */
__I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
__IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */
uint8_t RESERVED_9[28];
__IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */
__IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */
__IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */
__IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */
__IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */
__I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */
__IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */
__IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */
__IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/*! @name ID - Identification register */
/*! @{ */
#define USB_ID_ID_MASK (0x3FU)
#define USB_ID_ID_SHIFT (0U)
#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
#define USB_ID_NID_MASK (0x3F00U)
#define USB_ID_NID_SHIFT (8U)
#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
#define USB_ID_REVISION_MASK (0xFF0000U)
#define USB_ID_REVISION_SHIFT (16U)
#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
/*! @} */
/*! @name HWGENERAL - Hardware General */
/*! @{ */
#define USB_HWGENERAL_PHYW_MASK (0x30U)
#define USB_HWGENERAL_PHYW_SHIFT (4U)
#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
#define USB_HWGENERAL_PHYM_SHIFT (6U)
#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
#define USB_HWGENERAL_SM_MASK (0x600U)
#define USB_HWGENERAL_SM_SHIFT (9U)
#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
/*! @} */
/*! @name HWHOST - Host Hardware Parameters */
/*! @{ */
#define USB_HWHOST_HC_MASK (0x1U)
#define USB_HWHOST_HC_SHIFT (0U)
#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
#define USB_HWHOST_NPORT_MASK (0xEU)
#define USB_HWHOST_NPORT_SHIFT (1U)
#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
/*! @} */
/*! @name HWDEVICE - Device Hardware Parameters */
/*! @{ */
#define USB_HWDEVICE_DC_MASK (0x1U)
#define USB_HWDEVICE_DC_SHIFT (0U)
#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
#define USB_HWDEVICE_DEVEP_SHIFT (1U)
#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
/*! @} */
/*! @name HWTXBUF - TX Buffer Hardware Parameters */
/*! @{ */
#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
#define USB_HWTXBUF_TXBURST_SHIFT (0U)
#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
/*! @} */
/*! @name HWRXBUF - RX Buffer Hardware Parameters */
/*! @{ */
#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
#define USB_HWRXBUF_RXBURST_SHIFT (0U)
#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
#define USB_HWRXBUF_RXADD_SHIFT (8U)
#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
/*! @} */
/*! @name GPTIMER0LD - General Purpose Timer #0 Load */
/*! @{ */
#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
/*! @} */
/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
/*! @{ */
#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
/*! @} */
/*! @name GPTIMER1LD - General Purpose Timer #1 Load */
/*! @{ */
#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
/*! @} */
/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
/*! @{ */
#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
/*! @} */
/*! @name SBUSCFG - System Bus Config */
/*! @{ */
#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
/*! @} */
/*! @name CAPLENGTH - Capability Registers Length */
/*! @{ */
#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
/*! @} */
/*! @name HCIVERSION - Host Controller Interface Version */
/*! @{ */
#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
/*! @} */
/*! @name HCSPARAMS - Host Controller Structural Parameters */
/*! @{ */
#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
#define USB_HCSPARAMS_PPC_MASK (0x10U)
#define USB_HCSPARAMS_PPC_SHIFT (4U)
#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
#define USB_HCSPARAMS_N_CC_SHIFT (12U)
#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
#define USB_HCSPARAMS_PI_MASK (0x10000U)
#define USB_HCSPARAMS_PI_SHIFT (16U)
#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
#define USB_HCSPARAMS_N_TT_SHIFT (24U)
#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
/*! @} */
/*! @name HCCPARAMS - Host Controller Capability Parameters */
/*! @{ */
#define USB_HCCPARAMS_ADC_MASK (0x1U)
#define USB_HCCPARAMS_ADC_SHIFT (0U)
#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
#define USB_HCCPARAMS_PFL_MASK (0x2U)
#define USB_HCCPARAMS_PFL_SHIFT (1U)
#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
#define USB_HCCPARAMS_ASP_MASK (0x4U)
#define USB_HCCPARAMS_ASP_SHIFT (2U)
#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
#define USB_HCCPARAMS_IST_MASK (0xF0U)
#define USB_HCCPARAMS_IST_SHIFT (4U)
#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
#define USB_HCCPARAMS_EECP_SHIFT (8U)
#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
/*! @} */
/*! @name DCIVERSION - Device Controller Interface Version */
/*! @{ */
#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
/*! @} */
/*! @name DCCPARAMS - Device Controller Capability Parameters */
/*! @{ */
#define USB_DCCPARAMS_DEN_MASK (0x1FU)
#define USB_DCCPARAMS_DEN_SHIFT (0U)
#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
#define USB_DCCPARAMS_DC_MASK (0x80U)
#define USB_DCCPARAMS_DC_SHIFT (7U)
#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
#define USB_DCCPARAMS_HC_MASK (0x100U)
#define USB_DCCPARAMS_HC_SHIFT (8U)
#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
/*! @} */
/*! @name USBCMD - USB Command Register */
/*! @{ */
#define USB_USBCMD_RS_MASK (0x1U)
#define USB_USBCMD_RS_SHIFT (0U)
#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
#define USB_USBCMD_RST_MASK (0x2U)
#define USB_USBCMD_RST_SHIFT (1U)
#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
#define USB_USBCMD_FS_1_MASK (0xCU)
#define USB_USBCMD_FS_1_SHIFT (2U)
#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
#define USB_USBCMD_PSE_MASK (0x10U)
#define USB_USBCMD_PSE_SHIFT (4U)
#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
#define USB_USBCMD_ASE_MASK (0x20U)
#define USB_USBCMD_ASE_SHIFT (5U)
#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
#define USB_USBCMD_IAA_MASK (0x40U)
#define USB_USBCMD_IAA_SHIFT (6U)
#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
#define USB_USBCMD_ASP_MASK (0x300U)
#define USB_USBCMD_ASP_SHIFT (8U)
#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
#define USB_USBCMD_ASPE_MASK (0x800U)
#define USB_USBCMD_ASPE_SHIFT (11U)
#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
#define USB_USBCMD_ATDTW_MASK (0x1000U)
#define USB_USBCMD_ATDTW_SHIFT (12U)
#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
#define USB_USBCMD_SUTW_MASK (0x2000U)
#define USB_USBCMD_SUTW_SHIFT (13U)
#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
#define USB_USBCMD_FS_2_MASK (0x8000U)
#define USB_USBCMD_FS_2_SHIFT (15U)
#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
#define USB_USBCMD_ITC_MASK (0xFF0000U)
#define USB_USBCMD_ITC_SHIFT (16U)
#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
/*! @} */
/*! @name USBSTS - USB Status Register */
/*! @{ */
#define USB_USBSTS_UI_MASK (0x1U)
#define USB_USBSTS_UI_SHIFT (0U)
#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
#define USB_USBSTS_UEI_MASK (0x2U)
#define USB_USBSTS_UEI_SHIFT (1U)
#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
#define USB_USBSTS_PCI_MASK (0x4U)
#define USB_USBSTS_PCI_SHIFT (2U)
#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
#define USB_USBSTS_FRI_MASK (0x8U)
#define USB_USBSTS_FRI_SHIFT (3U)
#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
#define USB_USBSTS_SEI_MASK (0x10U)
#define USB_USBSTS_SEI_SHIFT (4U)
#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
#define USB_USBSTS_AAI_MASK (0x20U)
#define USB_USBSTS_AAI_SHIFT (5U)
#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
#define USB_USBSTS_URI_MASK (0x40U)
#define USB_USBSTS_URI_SHIFT (6U)
#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
#define USB_USBSTS_SRI_MASK (0x80U)
#define USB_USBSTS_SRI_SHIFT (7U)
#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
#define USB_USBSTS_SLI_MASK (0x100U)
#define USB_USBSTS_SLI_SHIFT (8U)
#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
#define USB_USBSTS_ULPII_MASK (0x400U)
#define USB_USBSTS_ULPII_SHIFT (10U)
#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
#define USB_USBSTS_HCH_MASK (0x1000U)
#define USB_USBSTS_HCH_SHIFT (12U)
#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
#define USB_USBSTS_RCL_MASK (0x2000U)
#define USB_USBSTS_RCL_SHIFT (13U)
#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
#define USB_USBSTS_PS_MASK (0x4000U)
#define USB_USBSTS_PS_SHIFT (14U)
#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
#define USB_USBSTS_AS_MASK (0x8000U)
#define USB_USBSTS_AS_SHIFT (15U)
#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
#define USB_USBSTS_NAKI_MASK (0x10000U)
#define USB_USBSTS_NAKI_SHIFT (16U)
#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
#define USB_USBSTS_TI0_MASK (0x1000000U)
#define USB_USBSTS_TI0_SHIFT (24U)
#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
#define USB_USBSTS_TI1_MASK (0x2000000U)
#define USB_USBSTS_TI1_SHIFT (25U)
#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
/*! @} */
/*! @name USBINTR - Interrupt Enable Register */
/*! @{ */
#define USB_USBINTR_UE_MASK (0x1U)
#define USB_USBINTR_UE_SHIFT (0U)
#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
#define USB_USBINTR_UEE_MASK (0x2U)
#define USB_USBINTR_UEE_SHIFT (1U)
#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
#define USB_USBINTR_PCE_MASK (0x4U)
#define USB_USBINTR_PCE_SHIFT (2U)
#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
#define USB_USBINTR_FRE_MASK (0x8U)
#define USB_USBINTR_FRE_SHIFT (3U)
#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
#define USB_USBINTR_SEE_MASK (0x10U)
#define USB_USBINTR_SEE_SHIFT (4U)
#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
#define USB_USBINTR_AAE_MASK (0x20U)
#define USB_USBINTR_AAE_SHIFT (5U)
#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
#define USB_USBINTR_URE_MASK (0x40U)
#define USB_USBINTR_URE_SHIFT (6U)
#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
#define USB_USBINTR_SRE_MASK (0x80U)
#define USB_USBINTR_SRE_SHIFT (7U)
#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
#define USB_USBINTR_SLE_MASK (0x100U)
#define USB_USBINTR_SLE_SHIFT (8U)
#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
#define USB_USBINTR_ULPIE_MASK (0x400U)
#define USB_USBINTR_ULPIE_SHIFT (10U)
#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
#define USB_USBINTR_NAKE_MASK (0x10000U)
#define USB_USBINTR_NAKE_SHIFT (16U)
#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
#define USB_USBINTR_UAIE_MASK (0x40000U)
#define USB_USBINTR_UAIE_SHIFT (18U)
#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
#define USB_USBINTR_UPIE_MASK (0x80000U)
#define USB_USBINTR_UPIE_SHIFT (19U)
#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
#define USB_USBINTR_TIE0_MASK (0x1000000U)
#define USB_USBINTR_TIE0_SHIFT (24U)
#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
#define USB_USBINTR_TIE1_MASK (0x2000000U)
#define USB_USBINTR_TIE1_SHIFT (25U)
#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
/*! @} */
/*! @name FRINDEX - USB Frame Index */
/*! @{ */
#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
#define USB_FRINDEX_FRINDEX_SHIFT (0U)
#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
/*! @} */
/*! @name DEVICEADDR - Device Address */
/*! @{ */
#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
#define USB_DEVICEADDR_USBADR_SHIFT (25U)
#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
/*! @} */
/*! @name PERIODICLISTBASE - Frame List Base Address */
/*! @{ */
#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
/*! @} */
/*! @name ASYNCLISTADDR - Next Asynch. Address */
/*! @{ */
#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
/*! @} */
/*! @name ENDPTLISTADDR - Endpoint List Address */
/*! @{ */
#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
/*! @} */
/*! @name BURSTSIZE - Programmable Burst Size */
/*! @{ */
#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
/*! @} */
/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
/*! @{ */
#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
/*! @} */
/*! @name ENDPTNAK - Endpoint NAK */
/*! @{ */
#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
#define USB_ENDPTNAK_EPRN_SHIFT (0U)
#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
#define USB_ENDPTNAK_EPTN_SHIFT (16U)
#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
/*! @} */
/*! @name ENDPTNAKEN - Endpoint NAK Enable */
/*! @{ */
#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
/*! @} */
/*! @name CONFIGFLAG - Configure Flag Register */
/*! @{ */
#define USB_CONFIGFLAG_CF_MASK (0x1U)
#define USB_CONFIGFLAG_CF_SHIFT (0U)
#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
/*! @} */
/*! @name PORTSC1 - Port Status & Control */
/*! @{ */
#define USB_PORTSC1_CCS_MASK (0x1U)
#define USB_PORTSC1_CCS_SHIFT (0U)
#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
#define USB_PORTSC1_CSC_MASK (0x2U)
#define USB_PORTSC1_CSC_SHIFT (1U)
#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
#define USB_PORTSC1_PE_MASK (0x4U)
#define USB_PORTSC1_PE_SHIFT (2U)
#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
#define USB_PORTSC1_PEC_MASK (0x8U)
#define USB_PORTSC1_PEC_SHIFT (3U)
#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
#define USB_PORTSC1_OCA_MASK (0x10U)
#define USB_PORTSC1_OCA_SHIFT (4U)
#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
#define USB_PORTSC1_OCC_MASK (0x20U)
#define USB_PORTSC1_OCC_SHIFT (5U)
#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
#define USB_PORTSC1_FPR_MASK (0x40U)
#define USB_PORTSC1_FPR_SHIFT (6U)
#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
#define USB_PORTSC1_SUSP_MASK (0x80U)
#define USB_PORTSC1_SUSP_SHIFT (7U)
#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
#define USB_PORTSC1_PR_MASK (0x100U)
#define USB_PORTSC1_PR_SHIFT (8U)
#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
#define USB_PORTSC1_HSP_MASK (0x200U)
#define USB_PORTSC1_HSP_SHIFT (9U)
#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
#define USB_PORTSC1_LS_MASK (0xC00U)
#define USB_PORTSC1_LS_SHIFT (10U)
#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
#define USB_PORTSC1_PP_MASK (0x1000U)
#define USB_PORTSC1_PP_SHIFT (12U)
#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
#define USB_PORTSC1_PO_MASK (0x2000U)
#define USB_PORTSC1_PO_SHIFT (13U)
#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
#define USB_PORTSC1_PIC_MASK (0xC000U)
#define USB_PORTSC1_PIC_SHIFT (14U)
#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
#define USB_PORTSC1_PTC_MASK (0xF0000U)
#define USB_PORTSC1_PTC_SHIFT (16U)
#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
#define USB_PORTSC1_WKCN_MASK (0x100000U)
#define USB_PORTSC1_WKCN_SHIFT (20U)
#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
#define USB_PORTSC1_WKDC_MASK (0x200000U)
#define USB_PORTSC1_WKDC_SHIFT (21U)
#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
#define USB_PORTSC1_WKOC_MASK (0x400000U)
#define USB_PORTSC1_WKOC_SHIFT (22U)
#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
#define USB_PORTSC1_PHCD_MASK (0x800000U)
#define USB_PORTSC1_PHCD_SHIFT (23U)
#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
#define USB_PORTSC1_PFSC_MASK (0x1000000U)
#define USB_PORTSC1_PFSC_SHIFT (24U)
#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
#define USB_PORTSC1_PTS_2_SHIFT (25U)
#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
#define USB_PORTSC1_PSPD_MASK (0xC000000U)
#define USB_PORTSC1_PSPD_SHIFT (26U)
#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
#define USB_PORTSC1_PTW_MASK (0x10000000U)
#define USB_PORTSC1_PTW_SHIFT (28U)
#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
#define USB_PORTSC1_STS_MASK (0x20000000U)
#define USB_PORTSC1_STS_SHIFT (29U)
#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
#define USB_PORTSC1_PTS_1_SHIFT (30U)
#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
/*! @} */
/*! @name OTGSC - On-The-Go Status & control */
/*! @{ */
#define USB_OTGSC_VD_MASK (0x1U)
#define USB_OTGSC_VD_SHIFT (0U)
#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
#define USB_OTGSC_VC_MASK (0x2U)
#define USB_OTGSC_VC_SHIFT (1U)
#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
#define USB_OTGSC_OT_MASK (0x8U)
#define USB_OTGSC_OT_SHIFT (3U)
#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
#define USB_OTGSC_DP_MASK (0x10U)
#define USB_OTGSC_DP_SHIFT (4U)
#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
#define USB_OTGSC_IDPU_MASK (0x20U)
#define USB_OTGSC_IDPU_SHIFT (5U)
#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
#define USB_OTGSC_ID_MASK (0x100U)
#define USB_OTGSC_ID_SHIFT (8U)
#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
#define USB_OTGSC_AVV_MASK (0x200U)
#define USB_OTGSC_AVV_SHIFT (9U)
#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
#define USB_OTGSC_ASV_MASK (0x400U)
#define USB_OTGSC_ASV_SHIFT (10U)
#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
#define USB_OTGSC_BSV_MASK (0x800U)
#define USB_OTGSC_BSV_SHIFT (11U)
#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
#define USB_OTGSC_BSE_MASK (0x1000U)
#define USB_OTGSC_BSE_SHIFT (12U)
#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
#define USB_OTGSC_TOG_1MS_SHIFT (13U)
#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
#define USB_OTGSC_DPS_MASK (0x4000U)
#define USB_OTGSC_DPS_SHIFT (14U)
#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
#define USB_OTGSC_IDIS_MASK (0x10000U)
#define USB_OTGSC_IDIS_SHIFT (16U)
#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
#define USB_OTGSC_AVVIS_MASK (0x20000U)
#define USB_OTGSC_AVVIS_SHIFT (17U)
#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
#define USB_OTGSC_ASVIS_MASK (0x40000U)
#define USB_OTGSC_ASVIS_SHIFT (18U)
#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
#define USB_OTGSC_BSVIS_MASK (0x80000U)
#define USB_OTGSC_BSVIS_SHIFT (19U)
#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
#define USB_OTGSC_BSEIS_MASK (0x100000U)
#define USB_OTGSC_BSEIS_SHIFT (20U)
#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
#define USB_OTGSC_DPIS_MASK (0x400000U)
#define USB_OTGSC_DPIS_SHIFT (22U)
#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
#define USB_OTGSC_IDIE_MASK (0x1000000U)
#define USB_OTGSC_IDIE_SHIFT (24U)
#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
#define USB_OTGSC_AVVIE_MASK (0x2000000U)
#define USB_OTGSC_AVVIE_SHIFT (25U)
#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
#define USB_OTGSC_ASVIE_MASK (0x4000000U)
#define USB_OTGSC_ASVIE_SHIFT (26U)
#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
#define USB_OTGSC_BSVIE_MASK (0x8000000U)
#define USB_OTGSC_BSVIE_SHIFT (27U)
#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
#define USB_OTGSC_BSEIE_MASK (0x10000000U)
#define USB_OTGSC_BSEIE_SHIFT (28U)
#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
#define USB_OTGSC_EN_1MS_SHIFT (29U)
#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
#define USB_OTGSC_DPIE_MASK (0x40000000U)
#define USB_OTGSC_DPIE_SHIFT (30U)
#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
/*! @} */
/*! @name USBMODE - USB Device Mode */
/*! @{ */
#define USB_USBMODE_CM_MASK (0x3U)
#define USB_USBMODE_CM_SHIFT (0U)
#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
#define USB_USBMODE_ES_MASK (0x4U)
#define USB_USBMODE_ES_SHIFT (2U)
#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
#define USB_USBMODE_SLOM_MASK (0x8U)
#define USB_USBMODE_SLOM_SHIFT (3U)
#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
#define USB_USBMODE_SDIS_MASK (0x10U)
#define USB_USBMODE_SDIS_SHIFT (4U)
#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
/*! @} */
/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
/*! @{ */
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
/*! @} */
/*! @name ENDPTPRIME - Endpoint Prime */
/*! @{ */
#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
#define USB_ENDPTPRIME_PERB_SHIFT (0U)
#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
#define USB_ENDPTPRIME_PETB_SHIFT (16U)
#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
/*! @} */
/*! @name ENDPTFLUSH - Endpoint Flush */
/*! @{ */
#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
/*! @} */
/*! @name ENDPTSTAT - Endpoint Status */
/*! @{ */
#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
/*! @} */
/*! @name ENDPTCOMPLETE - Endpoint Complete */
/*! @{ */
#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
/*! @} */
/*! @name ENDPTCTRL0 - Endpoint Control0 */
/*! @{ */
#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
/*! @} */
/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
/*! @{ */
#define USB_ENDPTCTRL_RXS_MASK (0x1U)
#define USB_ENDPTCTRL_RXS_SHIFT (0U)
#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
#define USB_ENDPTCTRL_RXD_MASK (0x2U)
#define USB_ENDPTCTRL_RXD_SHIFT (1U)
#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
#define USB_ENDPTCTRL_RXT_MASK (0xCU)
#define USB_ENDPTCTRL_RXT_SHIFT (2U)
#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
#define USB_ENDPTCTRL_RXI_MASK (0x20U)
#define USB_ENDPTCTRL_RXI_SHIFT (5U)
#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
#define USB_ENDPTCTRL_RXR_MASK (0x40U)
#define USB_ENDPTCTRL_RXR_SHIFT (6U)
#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
#define USB_ENDPTCTRL_RXE_MASK (0x80U)
#define USB_ENDPTCTRL_RXE_SHIFT (7U)
#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
#define USB_ENDPTCTRL_TXS_SHIFT (16U)
#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
#define USB_ENDPTCTRL_TXD_SHIFT (17U)
#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
#define USB_ENDPTCTRL_TXT_SHIFT (18U)
#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
#define USB_ENDPTCTRL_TXI_SHIFT (21U)
#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
#define USB_ENDPTCTRL_TXR_SHIFT (22U)
#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
#define USB_ENDPTCTRL_TXE_SHIFT (23U)
#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
/*! @} */
/* The count of USB_ENDPTCTRL */
#define USB_ENDPTCTRL_COUNT (7U)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB1 base address */
#define USB1_BASE (0x402E0000u)
/** Peripheral USB1 base pointer */
#define USB1 ((USB_Type *)USB1_BASE)
/** Peripheral USB2 base address */
#define USB2_BASE (0x402E0200u)
/** Peripheral USB2 base pointer */
#define USB2 ((USB_Type *)USB2_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
/* Backward compatibility */
#define GPTIMER0CTL GPTIMER0CTRL
#define GPTIMER1CTL GPTIMER1CTRL
#define USB_SBUSCFG SBUSCFG
#define EPLISTADDR ENDPTLISTADDR
#define EPSETUPSR ENDPTSETUPSTAT
#define EPPRIME ENDPTPRIME
#define EPFLUSH ENDPTFLUSH
#define EPSR ENDPTSTAT
#define EPCOMPLETE ENDPTCOMPLETE
#define EPCR ENDPTCTRL
#define EPCR0 ENDPTCTRL0
#define USBHS_ID_ID_MASK USB_ID_ID_MASK
#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
#define USBHS_ID_ID(x) USB_ID_ID(x)
#define USBHS_ID_NID_MASK USB_ID_NID_MASK
#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
#define USBHS_ID_NID(x) USB_ID_NID(x)
#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
#define USBHS_Type USB_Type
#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
#define USBHS_IRQHandler USB_OTG1_IRQHandler
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USBNC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
* @{
*/
/** USBNC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[2048];
__IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */
uint8_t RESERVED_1[20];
__IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */
} USBNC_Type;
/* ----------------------------------------------------------------------------
-- USBNC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBNC_Register_Masks USBNC Register Masks
* @{
*/
/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */
/*! @{ */
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
/*! @} */
/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */
/*! @{ */
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USBNC_Register_Masks */
/* USBNC - Peripheral instance base addresses */
/** Peripheral USBNC1 base address */
#define USBNC1_BASE (0x402E0000u)
/** Peripheral USBNC1 base pointer */
#define USBNC1 ((USBNC_Type *)USBNC1_BASE)
/** Peripheral USBNC2 base address */
#define USBNC2_BASE (0x402E0004u)
/** Peripheral USBNC2 base pointer */
#define USBNC2 ((USBNC_Type *)USBNC2_BASE)
/** Array initializer of USBNC peripheral base addresses */
#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
/** Array initializer of USBNC peripheral base pointers */
#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
/*!
* @}
*/ /* end of group USBNC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USBPHY Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
* @{
*/
/** USBPHY - Register Layout Typedef */
typedef struct {
__IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
__IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
__IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
__IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
__IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
__IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
__IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
__IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
__IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
__IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
__IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
__IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
__IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
__IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
__IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
__IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
__IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
__IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
__IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
__I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
uint8_t RESERVED_1[12];
__IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
__IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
__IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
__IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
__I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
} USBPHY_Type;
/* ----------------------------------------------------------------------------
-- USBPHY Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBPHY_Register_Masks USBPHY Register Masks
* @{
*/
/*! @name PWD - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_RSVD0_MASK (0x3FFU)
#define USBPHY_PWD_RSVD0_SHIFT (0U)
#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
#define USBPHY_PWD_RSVD1_MASK (0x1E000U)
#define USBPHY_PWD_RSVD1_SHIFT (13U)
#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
#define USBPHY_PWD_RSVD2_SHIFT (21U)
#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
/*! @} */
/*! @name PWD_SET - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
#define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
#define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
#define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
/*! @} */
/*! @name PWD_CLR - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
/*! @} */
/*! @name PWD_TOG - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
/*! @} */
/*! @name TX - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_D_CAL_MASK (0xFU)
#define USBPHY_TX_D_CAL_SHIFT (0U)
#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
#define USBPHY_TX_RSVD0_MASK (0xF0U)
#define USBPHY_TX_RSVD0_SHIFT (4U)
#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
#define USBPHY_TX_RSVD1_MASK (0xF000U)
#define USBPHY_TX_RSVD1_SHIFT (12U)
#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
#define USBPHY_TX_RSVD2_MASK (0x3F00000U)
#define USBPHY_TX_RSVD2_SHIFT (20U)
#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
#define USBPHY_TX_RSVD5_MASK (0xE0000000U)
#define USBPHY_TX_RSVD5_SHIFT (29U)
#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
/*! @} */
/*! @name TX_SET - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
#define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
#define USBPHY_TX_SET_RSVD0_SHIFT (4U)
#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
#define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
#define USBPHY_TX_SET_RSVD1_SHIFT (12U)
#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
#define USBPHY_TX_SET_RSVD2_SHIFT (20U)
#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
#define USBPHY_TX_SET_RSVD5_SHIFT (29U)
#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
/*! @} */
/*! @name TX_CLR - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
#define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
#define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
#define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
#define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
/*! @} */
/*! @name TX_TOG - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
#define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
#define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
#define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
#define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
/*! @} */
/*! @name RX - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_ENVADJ_MASK (0x7U)
#define USBPHY_RX_ENVADJ_SHIFT (0U)
#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
#define USBPHY_RX_RSVD0_MASK (0x8U)
#define USBPHY_RX_RSVD0_SHIFT (3U)
#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
#define USBPHY_RX_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_DISCONADJ_SHIFT (4U)
#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
#define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
#define USBPHY_RX_RSVD1_SHIFT (7U)
#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
#define USBPHY_RX_RSVD2_MASK (0xFF800000U)
#define USBPHY_RX_RSVD2_SHIFT (23U)
#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
/*! @} */
/*! @name RX_SET - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
#define USBPHY_RX_SET_RSVD0_MASK (0x8U)
#define USBPHY_RX_SET_RSVD0_SHIFT (3U)
#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
#define USBPHY_RX_SET_RSVD1_SHIFT (7U)
#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
#define USBPHY_RX_SET_RSVD2_SHIFT (23U)
#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
/*! @} */
/*! @name RX_CLR - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
#define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
#define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
#define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
#define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
/*! @} */
/*! @name RX_TOG - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
#define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
#define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
#define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
#define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
/*! @} */
/*! @name CTRL - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
#define USBPHY_CTRL_RSVD1_SHIFT (25U)
#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_SFTRST_SHIFT (31U)
#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STATUS - USB PHY Status Register */
/*! @{ */
#define USBPHY_STATUS_RSVD0_MASK (0x7U)
#define USBPHY_STATUS_RSVD0_SHIFT (0U)
#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
#define USBPHY_STATUS_RSVD1_MASK (0x30U)
#define USBPHY_STATUS_RSVD1_SHIFT (4U)
#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
#define USBPHY_STATUS_RSVD2_MASK (0x80U)
#define USBPHY_STATUS_RSVD2_SHIFT (7U)
#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
#define USBPHY_STATUS_RSVD3_MASK (0x200U)
#define USBPHY_STATUS_RSVD3_SHIFT (9U)
#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
#define USBPHY_STATUS_RSVD4_SHIFT (11U)
#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
/*! @} */
/*! @name DEBUG - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
#define USBPHY_DEBUG_RSVD0_SHIFT (6U)
#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
#define USBPHY_DEBUG_RSVD1_SHIFT (13U)
#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
#define USBPHY_DEBUG_RSVD2_SHIFT (21U)
#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
#define USBPHY_DEBUG_RSVD3_SHIFT (31U)
#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
/*! @} */
/*! @name DEBUG_SET - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
/*! @} */
/*! @name DEBUG_CLR - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
/*! @} */
/*! @name DEBUG_TOG - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
/*! @} */
/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
/*! @{ */
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
/*! @} */
/*! @name DEBUG1 - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
#define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
#define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
/*! @} */
/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
/*! @} */
/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
/*! @} */
/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
/*! @} */
/*! @name VERSION - UTMI RTL Version */
/*! @{ */
#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
#define USBPHY_VERSION_STEP_SHIFT (0U)
#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
#define USBPHY_VERSION_MINOR_SHIFT (16U)
#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
#define USBPHY_VERSION_MAJOR_SHIFT (24U)
#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USBPHY_Register_Masks */
/* USBPHY - Peripheral instance base addresses */
/** Peripheral USBPHY1 base address */
#define USBPHY1_BASE (0x400D9000u)
/** Peripheral USBPHY1 base pointer */
#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
/** Peripheral USBPHY2 base address */
#define USBPHY2_BASE (0x400DA000u)
/** Peripheral USBPHY2 base pointer */
#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
/** Array initializer of USBPHY peripheral base addresses */
#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
/** Array initializer of USBPHY peripheral base pointers */
#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/** Interrupt vectors for the USBPHY peripheral type */
#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
/* Backward compatibility */
#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
/*!
* @}
*/ /* end of group USBPHY_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB_ANALOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
* @{
*/
/** USB_ANALOG - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[416];
struct { /* offset: 0x1A0, array step: 0x60 */
__IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */
__IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */
__IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */
__IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */
__IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */
__IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */
__IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */
__IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */
__I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */
uint8_t RESERVED_0[12];
__I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */
uint8_t RESERVED_1[28];
__IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
__IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
__IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
__IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
} INSTANCE[2];
__I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */
} USB_ANALOG_Type;
/* ----------------------------------------------------------------------------
-- USB_ANALOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
* @{
*/
/*! @name VBUS_DETECT - USB VBUS Detect Register */
/*! @{ */
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
/*! @} */
/* The count of USB_ANALOG_VBUS_DETECT */
#define USB_ANALOG_VBUS_DETECT_COUNT (2U)
/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */
/*! @{ */
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
/*! @} */
/* The count of USB_ANALOG_VBUS_DETECT_SET */
#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */
/*! @{ */
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
/*! @} */
/* The count of USB_ANALOG_VBUS_DETECT_CLR */
#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */
/*! @{ */
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
/*! @} */
/* The count of USB_ANALOG_VBUS_DETECT_TOG */
#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
/*! @name CHRG_DETECT - USB Charger Detect Register */
/*! @{ */
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
/*! @} */
/* The count of USB_ANALOG_CHRG_DETECT */
#define USB_ANALOG_CHRG_DETECT_COUNT (2U)
/*! @name CHRG_DETECT_SET - USB Charger Detect Register */
/*! @{ */
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
/*! @} */
/* The count of USB_ANALOG_CHRG_DETECT_SET */
#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */
/*! @{ */
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
/*! @} */
/* The count of USB_ANALOG_CHRG_DETECT_CLR */
#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */
/*! @{ */
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
/*! @} */
/* The count of USB_ANALOG_CHRG_DETECT_TOG */
#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */
/*! @{ */
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
/*! @} */
/* The count of USB_ANALOG_VBUS_DETECT_STAT */
#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */
/*! @{ */
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
/*! @} */
/* The count of USB_ANALOG_CHRG_DETECT_STAT */
#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
/*! @name MISC - USB Misc Register */
/*! @{ */
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
/*! @} */
/* The count of USB_ANALOG_MISC */
#define USB_ANALOG_MISC_COUNT (2U)
/*! @name MISC_SET - USB Misc Register */
/*! @{ */
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
/*! @} */
/* The count of USB_ANALOG_MISC_SET */
#define USB_ANALOG_MISC_SET_COUNT (2U)
/*! @name MISC_CLR - USB Misc Register */
/*! @{ */
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
/*! @} */
/* The count of USB_ANALOG_MISC_CLR */
#define USB_ANALOG_MISC_CLR_COUNT (2U)
/*! @name MISC_TOG - USB Misc Register */
/*! @{ */
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
/*! @} */
/* The count of USB_ANALOG_MISC_TOG */
#define USB_ANALOG_MISC_TOG_COUNT (2U)
/*! @name DIGPROG - Chip Silicon Version */
/*! @{ */
#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USB_ANALOG_Register_Masks */
/* USB_ANALOG - Peripheral instance base addresses */
/** Peripheral USB_ANALOG base address */
#define USB_ANALOG_BASE (0x400D8000u)
/** Peripheral USB_ANALOG base pointer */
#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
/** Array initializer of USB_ANALOG peripheral base addresses */
#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
/** Array initializer of USB_ANALOG peripheral base pointers */
#define USB_ANALOG_BASE_PTRS { USB_ANALOG }
/*!
* @}
*/ /* end of group USB_ANALOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USDHC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
* @{
*/
/** USDHC - Register Layout Typedef */
typedef struct {
__IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
__IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
__IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
__IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
__I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
__I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
__I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
__I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
__IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
__I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
__IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
__IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
__IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
__IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
__IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
__IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
__IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
__IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
uint8_t RESERVED_0[4];
__O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
__I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */
__IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
uint8_t RESERVED_1[4];
__IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
__I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
__IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
uint8_t RESERVED_2[84];
__IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
__IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */
__IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
__IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */
} USDHC_Type;
/* ----------------------------------------------------------------------------
-- USDHC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Register_Masks USDHC Register Masks
* @{
*/
/*! @name DS_ADDR - DMA System Address */
/*! @{ */
#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */
/*! @name BLK_ATT - Block Attributes */
/*! @{ */
#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */
/*! @name CMD_ARG - Command Argument */
/*! @{ */
#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */
/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */
/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */
#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */
/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */
#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */
/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */
#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */
/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */
#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */
/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */
/*! @name PRES_STATE - Present State */
/*! @{ */
#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define USDHC_PRES_STATE_DLA_MASK (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT (2U)
#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define USDHC_PRES_STATE_WTA_MASK (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT (8U)
#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define USDHC_PRES_STATE_RTA_MASK (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT (9U)
#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define USDHC_PRES_STATE_BREN_MASK (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT (11U)
#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT (12U)
#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT (16U)
#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */
/*! @name PROT_CTRL - Protocol Control */
/*! @{ */
#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
/*! @} */
/*! @name SYS_CTRL - System Control */
/*! @{ */
#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status */
/*! @{ */
#define USDHC_INT_STATUS_CC_MASK (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT (0U)
#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define USDHC_INT_STATUS_TC_MASK (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT (1U)
#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define USDHC_INT_STATUS_BGE_MASK (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT (2U)
#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define USDHC_INT_STATUS_DINT_MASK (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT (3U)
#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define USDHC_INT_STATUS_BWR_MASK (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT (4U)
#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define USDHC_INT_STATUS_BRR_MASK (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT (5U)
#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define USDHC_INT_STATUS_CINS_MASK (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT (6U)
#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define USDHC_INT_STATUS_CRM_MASK (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT (7U)
#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define USDHC_INT_STATUS_CINT_MASK (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT (8U)
#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT (12U)
#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define USDHC_INT_STATUS_TP_MASK (0x4000U)
#define USDHC_INT_STATUS_TP_SHIFT (14U)
#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT (17U)
#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT (19U)
#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT (21U)
#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT (26U)
#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */
/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */
#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */
/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */
/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */
/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */
/*! @name WTMK_LVL - Watermark Level */
/*! @{ */
#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
/*! @} */
/*! @name MIX_CTRL - Mixer Control */
/*! @{ */
#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
/*! @} */
/*! @name FORCE_EVENT - Force Event */
/*! @{ */
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */
/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
/*! @{ */
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */
/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */
/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name DLL_STATUS - DLL Status */
/*! @{ */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */
/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */
/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */
#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */
/*! @name MMC_BOOT - MMC Boot Register */
/*! @{ */
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */
/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
/*! @} */
/*! @name TUNING_CTRL - Tuning Control Register */
/*! @{ */
#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USDHC_Register_Masks */
/* USDHC - Peripheral instance base addresses */
/** Peripheral USDHC1 base address */
#define USDHC1_BASE (0x402C0000u)
/** Peripheral USDHC1 base pointer */
#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
/** Peripheral USDHC2 base address */
#define USDHC2_BASE (0x402C4000u)
/** Peripheral USDHC2 base pointer */
#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
/** Interrupt vectors for the USDHC peripheral type */
#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
/*!
* @}
*/ /* end of group USDHC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
__IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/*! @name WCR - Watchdog Control Register */
/*! @{ */
#define WDOG_WCR_WDZST_MASK (0x1U)
#define WDOG_WCR_WDZST_SHIFT (0U)
#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
#define WDOG_WCR_WDBG_MASK (0x2U)
#define WDOG_WCR_WDBG_SHIFT (1U)
#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
#define WDOG_WCR_WDE_MASK (0x4U)
#define WDOG_WCR_WDE_SHIFT (2U)
#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
#define WDOG_WCR_WDT_MASK (0x8U)
#define WDOG_WCR_WDT_SHIFT (3U)
#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
#define WDOG_WCR_SRS_MASK (0x10U)
#define WDOG_WCR_SRS_SHIFT (4U)
#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
#define WDOG_WCR_WDA_MASK (0x20U)
#define WDOG_WCR_WDA_SHIFT (5U)
#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
#define WDOG_WCR_SRE_MASK (0x40U)
#define WDOG_WCR_SRE_SHIFT (6U)
#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
#define WDOG_WCR_WDW_MASK (0x80U)
#define WDOG_WCR_WDW_SHIFT (7U)
#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
#define WDOG_WCR_WT_MASK (0xFF00U)
#define WDOG_WCR_WT_SHIFT (8U)
#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
/*! @} */
/*! @name WSR - Watchdog Service Register */
/*! @{ */
#define WDOG_WSR_WSR_MASK (0xFFFFU)
#define WDOG_WSR_WSR_SHIFT (0U)
#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
/*! @} */
/*! @name WRSR - Watchdog Reset Status Register */
/*! @{ */
#define WDOG_WRSR_SFTW_MASK (0x1U)
#define WDOG_WRSR_SFTW_SHIFT (0U)
#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
#define WDOG_WRSR_TOUT_MASK (0x2U)
#define WDOG_WRSR_TOUT_SHIFT (1U)
#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
#define WDOG_WRSR_POR_MASK (0x10U)
#define WDOG_WRSR_POR_SHIFT (4U)
#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
/*! @} */
/*! @name WICR - Watchdog Interrupt Control Register */
/*! @{ */
#define WDOG_WICR_WICT_MASK (0xFFU)
#define WDOG_WICR_WICT_SHIFT (0U)
#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
#define WDOG_WICR_WTIS_MASK (0x4000U)
#define WDOG_WICR_WTIS_SHIFT (14U)
#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
#define WDOG_WICR_WIE_MASK (0x8000U)
#define WDOG_WICR_WIE_SHIFT (15U)
#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
/*! @} */
/*! @name WMCR - Watchdog Miscellaneous Control Register */
/*! @{ */
#define WDOG_WMCR_PDE_MASK (0x1U)
#define WDOG_WMCR_PDE_SHIFT (0U)
#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG1 base address */
#define WDOG1_BASE (0x400B8000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
/** Peripheral WDOG2 base address */
#define WDOG2_BASE (0x400D0000u)
/** Peripheral WDOG2 base pointer */
#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XBARA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
* @{
*/
/** XBARA - Register Layout Typedef */
typedef struct {
__IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */
__IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */
__IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */
__IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */
__IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */
__IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */
__IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */
__IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */
__IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */
__IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */
__IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */
__IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */
__IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */
__IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */
__IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */
__IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */
__IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */
__IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */
__IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */
__IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */
__IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */
__IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */
__IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */
__IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */
__IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */
__IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */
__IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */
__IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */
__IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */
__IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */
__IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */
__IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */
__IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */
__IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */
__IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */
__IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */
__IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */
__IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */
__IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */
__IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */
__IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */
__IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */
__IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */
__IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */
__IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */
__IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */
__IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */
__IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */
__IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */
__IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */
__IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */
__IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */
__IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */
__IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */
__IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */
__IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */
__IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */
__IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */
__IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */
__IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */
__IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */
__IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */
__IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */
__IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */
__IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */
__IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */
__IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */
__IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */
} XBARA_Type;
/* ----------------------------------------------------------------------------
-- XBARA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARA_Register_Masks XBARA Register Masks
* @{
*/
/*! @name SEL0 - Crossbar A Select Register 0 */
/*! @{ */
#define XBARA_SEL0_SEL0_MASK (0x7FU)
#define XBARA_SEL0_SEL0_SHIFT (0U)
#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
#define XBARA_SEL0_SEL1_MASK (0x7F00U)
#define XBARA_SEL0_SEL1_SHIFT (8U)
#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
/*! @} */
/*! @name SEL1 - Crossbar A Select Register 1 */
/*! @{ */
#define XBARA_SEL1_SEL2_MASK (0x7FU)
#define XBARA_SEL1_SEL2_SHIFT (0U)
#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
#define XBARA_SEL1_SEL3_MASK (0x7F00U)
#define XBARA_SEL1_SEL3_SHIFT (8U)
#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
/*! @} */
/*! @name SEL2 - Crossbar A Select Register 2 */
/*! @{ */
#define XBARA_SEL2_SEL4_MASK (0x7FU)
#define XBARA_SEL2_SEL4_SHIFT (0U)
#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
#define XBARA_SEL2_SEL5_MASK (0x7F00U)
#define XBARA_SEL2_SEL5_SHIFT (8U)
#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
/*! @} */
/*! @name SEL3 - Crossbar A Select Register 3 */
/*! @{ */
#define XBARA_SEL3_SEL6_MASK (0x7FU)
#define XBARA_SEL3_SEL6_SHIFT (0U)
#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
#define XBARA_SEL3_SEL7_MASK (0x7F00U)
#define XBARA_SEL3_SEL7_SHIFT (8U)
#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
/*! @} */
/*! @name SEL4 - Crossbar A Select Register 4 */
/*! @{ */
#define XBARA_SEL4_SEL8_MASK (0x7FU)
#define XBARA_SEL4_SEL8_SHIFT (0U)
#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
#define XBARA_SEL4_SEL9_MASK (0x7F00U)
#define XBARA_SEL4_SEL9_SHIFT (8U)
#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
/*! @} */
/*! @name SEL5 - Crossbar A Select Register 5 */
/*! @{ */
#define XBARA_SEL5_SEL10_MASK (0x7FU)
#define XBARA_SEL5_SEL10_SHIFT (0U)
#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
#define XBARA_SEL5_SEL11_MASK (0x7F00U)
#define XBARA_SEL5_SEL11_SHIFT (8U)
#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
/*! @} */
/*! @name SEL6 - Crossbar A Select Register 6 */
/*! @{ */
#define XBARA_SEL6_SEL12_MASK (0x7FU)
#define XBARA_SEL6_SEL12_SHIFT (0U)
#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
#define XBARA_SEL6_SEL13_MASK (0x7F00U)
#define XBARA_SEL6_SEL13_SHIFT (8U)
#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
/*! @} */
/*! @name SEL7 - Crossbar A Select Register 7 */
/*! @{ */
#define XBARA_SEL7_SEL14_MASK (0x7FU)
#define XBARA_SEL7_SEL14_SHIFT (0U)
#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
#define XBARA_SEL7_SEL15_MASK (0x7F00U)
#define XBARA_SEL7_SEL15_SHIFT (8U)
#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
/*! @} */
/*! @name SEL8 - Crossbar A Select Register 8 */
/*! @{ */
#define XBARA_SEL8_SEL16_MASK (0x7FU)
#define XBARA_SEL8_SEL16_SHIFT (0U)
#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
#define XBARA_SEL8_SEL17_MASK (0x7F00U)
#define XBARA_SEL8_SEL17_SHIFT (8U)
#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
/*! @} */
/*! @name SEL9 - Crossbar A Select Register 9 */
/*! @{ */
#define XBARA_SEL9_SEL18_MASK (0x7FU)
#define XBARA_SEL9_SEL18_SHIFT (0U)
#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
#define XBARA_SEL9_SEL19_MASK (0x7F00U)
#define XBARA_SEL9_SEL19_SHIFT (8U)
#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
/*! @} */
/*! @name SEL10 - Crossbar A Select Register 10 */
/*! @{ */
#define XBARA_SEL10_SEL20_MASK (0x7FU)
#define XBARA_SEL10_SEL20_SHIFT (0U)
#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
#define XBARA_SEL10_SEL21_MASK (0x7F00U)
#define XBARA_SEL10_SEL21_SHIFT (8U)
#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
/*! @} */
/*! @name SEL11 - Crossbar A Select Register 11 */
/*! @{ */
#define XBARA_SEL11_SEL22_MASK (0x7FU)
#define XBARA_SEL11_SEL22_SHIFT (0U)
#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
#define XBARA_SEL11_SEL23_MASK (0x7F00U)
#define XBARA_SEL11_SEL23_SHIFT (8U)
#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
/*! @} */
/*! @name SEL12 - Crossbar A Select Register 12 */
/*! @{ */
#define XBARA_SEL12_SEL24_MASK (0x7FU)
#define XBARA_SEL12_SEL24_SHIFT (0U)
#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
#define XBARA_SEL12_SEL25_MASK (0x7F00U)
#define XBARA_SEL12_SEL25_SHIFT (8U)
#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
/*! @} */
/*! @name SEL13 - Crossbar A Select Register 13 */
/*! @{ */
#define XBARA_SEL13_SEL26_MASK (0x7FU)
#define XBARA_SEL13_SEL26_SHIFT (0U)
#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
#define XBARA_SEL13_SEL27_MASK (0x7F00U)
#define XBARA_SEL13_SEL27_SHIFT (8U)
#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
/*! @} */
/*! @name SEL14 - Crossbar A Select Register 14 */
/*! @{ */
#define XBARA_SEL14_SEL28_MASK (0x7FU)
#define XBARA_SEL14_SEL28_SHIFT (0U)
#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
#define XBARA_SEL14_SEL29_MASK (0x7F00U)
#define XBARA_SEL14_SEL29_SHIFT (8U)
#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
/*! @} */
/*! @name SEL15 - Crossbar A Select Register 15 */
/*! @{ */
#define XBARA_SEL15_SEL30_MASK (0x7FU)
#define XBARA_SEL15_SEL30_SHIFT (0U)
#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
#define XBARA_SEL15_SEL31_MASK (0x7F00U)
#define XBARA_SEL15_SEL31_SHIFT (8U)
#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
/*! @} */
/*! @name SEL16 - Crossbar A Select Register 16 */
/*! @{ */
#define XBARA_SEL16_SEL32_MASK (0x7FU)
#define XBARA_SEL16_SEL32_SHIFT (0U)
#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
#define XBARA_SEL16_SEL33_MASK (0x7F00U)
#define XBARA_SEL16_SEL33_SHIFT (8U)
#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
/*! @} */
/*! @name SEL17 - Crossbar A Select Register 17 */
/*! @{ */
#define XBARA_SEL17_SEL34_MASK (0x7FU)
#define XBARA_SEL17_SEL34_SHIFT (0U)
#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
#define XBARA_SEL17_SEL35_MASK (0x7F00U)
#define XBARA_SEL17_SEL35_SHIFT (8U)
#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
/*! @} */
/*! @name SEL18 - Crossbar A Select Register 18 */
/*! @{ */
#define XBARA_SEL18_SEL36_MASK (0x7FU)
#define XBARA_SEL18_SEL36_SHIFT (0U)
#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
#define XBARA_SEL18_SEL37_MASK (0x7F00U)
#define XBARA_SEL18_SEL37_SHIFT (8U)
#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
/*! @} */
/*! @name SEL19 - Crossbar A Select Register 19 */
/*! @{ */
#define XBARA_SEL19_SEL38_MASK (0x7FU)
#define XBARA_SEL19_SEL38_SHIFT (0U)
#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
#define XBARA_SEL19_SEL39_MASK (0x7F00U)
#define XBARA_SEL19_SEL39_SHIFT (8U)
#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
/*! @} */
/*! @name SEL20 - Crossbar A Select Register 20 */
/*! @{ */
#define XBARA_SEL20_SEL40_MASK (0x7FU)
#define XBARA_SEL20_SEL40_SHIFT (0U)
#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
#define XBARA_SEL20_SEL41_MASK (0x7F00U)
#define XBARA_SEL20_SEL41_SHIFT (8U)
#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
/*! @} */
/*! @name SEL21 - Crossbar A Select Register 21 */
/*! @{ */
#define XBARA_SEL21_SEL42_MASK (0x7FU)
#define XBARA_SEL21_SEL42_SHIFT (0U)
#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
#define XBARA_SEL21_SEL43_MASK (0x7F00U)
#define XBARA_SEL21_SEL43_SHIFT (8U)
#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
/*! @} */
/*! @name SEL22 - Crossbar A Select Register 22 */
/*! @{ */
#define XBARA_SEL22_SEL44_MASK (0x7FU)
#define XBARA_SEL22_SEL44_SHIFT (0U)
#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
#define XBARA_SEL22_SEL45_MASK (0x7F00U)
#define XBARA_SEL22_SEL45_SHIFT (8U)
#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
/*! @} */
/*! @name SEL23 - Crossbar A Select Register 23 */
/*! @{ */
#define XBARA_SEL23_SEL46_MASK (0x7FU)
#define XBARA_SEL23_SEL46_SHIFT (0U)
#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
#define XBARA_SEL23_SEL47_MASK (0x7F00U)
#define XBARA_SEL23_SEL47_SHIFT (8U)
#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
/*! @} */
/*! @name SEL24 - Crossbar A Select Register 24 */
/*! @{ */
#define XBARA_SEL24_SEL48_MASK (0x7FU)
#define XBARA_SEL24_SEL48_SHIFT (0U)
#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
#define XBARA_SEL24_SEL49_MASK (0x7F00U)
#define XBARA_SEL24_SEL49_SHIFT (8U)
#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
/*! @} */
/*! @name SEL25 - Crossbar A Select Register 25 */
/*! @{ */
#define XBARA_SEL25_SEL50_MASK (0x7FU)
#define XBARA_SEL25_SEL50_SHIFT (0U)
#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
#define XBARA_SEL25_SEL51_MASK (0x7F00U)
#define XBARA_SEL25_SEL51_SHIFT (8U)
#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
/*! @} */
/*! @name SEL26 - Crossbar A Select Register 26 */
/*! @{ */
#define XBARA_SEL26_SEL52_MASK (0x7FU)
#define XBARA_SEL26_SEL52_SHIFT (0U)
#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
#define XBARA_SEL26_SEL53_MASK (0x7F00U)
#define XBARA_SEL26_SEL53_SHIFT (8U)
#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
/*! @} */
/*! @name SEL27 - Crossbar A Select Register 27 */
/*! @{ */
#define XBARA_SEL27_SEL54_MASK (0x7FU)
#define XBARA_SEL27_SEL54_SHIFT (0U)
#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
#define XBARA_SEL27_SEL55_MASK (0x7F00U)
#define XBARA_SEL27_SEL55_SHIFT (8U)
#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
/*! @} */
/*! @name SEL28 - Crossbar A Select Register 28 */
/*! @{ */
#define XBARA_SEL28_SEL56_MASK (0x7FU)
#define XBARA_SEL28_SEL56_SHIFT (0U)
#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
#define XBARA_SEL28_SEL57_MASK (0x7F00U)
#define XBARA_SEL28_SEL57_SHIFT (8U)
#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
/*! @} */
/*! @name SEL29 - Crossbar A Select Register 29 */
/*! @{ */
#define XBARA_SEL29_SEL58_MASK (0x7FU)
#define XBARA_SEL29_SEL58_SHIFT (0U)
#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
#define XBARA_SEL29_SEL59_MASK (0x7F00U)
#define XBARA_SEL29_SEL59_SHIFT (8U)
#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
/*! @} */
/*! @name SEL30 - Crossbar A Select Register 30 */
/*! @{ */
#define XBARA_SEL30_SEL60_MASK (0x7FU)
#define XBARA_SEL30_SEL60_SHIFT (0U)
#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
#define XBARA_SEL30_SEL61_MASK (0x7F00U)
#define XBARA_SEL30_SEL61_SHIFT (8U)
#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
/*! @} */
/*! @name SEL31 - Crossbar A Select Register 31 */
/*! @{ */
#define XBARA_SEL31_SEL62_MASK (0x7FU)
#define XBARA_SEL31_SEL62_SHIFT (0U)
#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
#define XBARA_SEL31_SEL63_MASK (0x7F00U)
#define XBARA_SEL31_SEL63_SHIFT (8U)
#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
/*! @} */
/*! @name SEL32 - Crossbar A Select Register 32 */
/*! @{ */
#define XBARA_SEL32_SEL64_MASK (0x7FU)
#define XBARA_SEL32_SEL64_SHIFT (0U)
#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
#define XBARA_SEL32_SEL65_MASK (0x7F00U)
#define XBARA_SEL32_SEL65_SHIFT (8U)
#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
/*! @} */
/*! @name SEL33 - Crossbar A Select Register 33 */
/*! @{ */
#define XBARA_SEL33_SEL66_MASK (0x7FU)
#define XBARA_SEL33_SEL66_SHIFT (0U)
#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
#define XBARA_SEL33_SEL67_MASK (0x7F00U)
#define XBARA_SEL33_SEL67_SHIFT (8U)
#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
/*! @} */
/*! @name SEL34 - Crossbar A Select Register 34 */
/*! @{ */
#define XBARA_SEL34_SEL68_MASK (0x7FU)
#define XBARA_SEL34_SEL68_SHIFT (0U)
#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
#define XBARA_SEL34_SEL69_MASK (0x7F00U)
#define XBARA_SEL34_SEL69_SHIFT (8U)
#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
/*! @} */
/*! @name SEL35 - Crossbar A Select Register 35 */
/*! @{ */
#define XBARA_SEL35_SEL70_MASK (0x7FU)
#define XBARA_SEL35_SEL70_SHIFT (0U)
#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
#define XBARA_SEL35_SEL71_MASK (0x7F00U)
#define XBARA_SEL35_SEL71_SHIFT (8U)
#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
/*! @} */
/*! @name SEL36 - Crossbar A Select Register 36 */
/*! @{ */
#define XBARA_SEL36_SEL72_MASK (0x7FU)
#define XBARA_SEL36_SEL72_SHIFT (0U)
#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
#define XBARA_SEL36_SEL73_MASK (0x7F00U)
#define XBARA_SEL36_SEL73_SHIFT (8U)
#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
/*! @} */
/*! @name SEL37 - Crossbar A Select Register 37 */
/*! @{ */
#define XBARA_SEL37_SEL74_MASK (0x7FU)
#define XBARA_SEL37_SEL74_SHIFT (0U)
#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
#define XBARA_SEL37_SEL75_MASK (0x7F00U)
#define XBARA_SEL37_SEL75_SHIFT (8U)
#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
/*! @} */
/*! @name SEL38 - Crossbar A Select Register 38 */
/*! @{ */
#define XBARA_SEL38_SEL76_MASK (0x7FU)
#define XBARA_SEL38_SEL76_SHIFT (0U)
#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
#define XBARA_SEL38_SEL77_MASK (0x7F00U)
#define XBARA_SEL38_SEL77_SHIFT (8U)
#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
/*! @} */
/*! @name SEL39 - Crossbar A Select Register 39 */
/*! @{ */
#define XBARA_SEL39_SEL78_MASK (0x7FU)
#define XBARA_SEL39_SEL78_SHIFT (0U)
#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
#define XBARA_SEL39_SEL79_MASK (0x7F00U)
#define XBARA_SEL39_SEL79_SHIFT (8U)
#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
/*! @} */
/*! @name SEL40 - Crossbar A Select Register 40 */
/*! @{ */
#define XBARA_SEL40_SEL80_MASK (0x7FU)
#define XBARA_SEL40_SEL80_SHIFT (0U)
#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
#define XBARA_SEL40_SEL81_MASK (0x7F00U)
#define XBARA_SEL40_SEL81_SHIFT (8U)
#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
/*! @} */
/*! @name SEL41 - Crossbar A Select Register 41 */
/*! @{ */
#define XBARA_SEL41_SEL82_MASK (0x7FU)
#define XBARA_SEL41_SEL82_SHIFT (0U)
#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
#define XBARA_SEL41_SEL83_MASK (0x7F00U)
#define XBARA_SEL41_SEL83_SHIFT (8U)
#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
/*! @} */
/*! @name SEL42 - Crossbar A Select Register 42 */
/*! @{ */
#define XBARA_SEL42_SEL84_MASK (0x7FU)
#define XBARA_SEL42_SEL84_SHIFT (0U)
#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
#define XBARA_SEL42_SEL85_MASK (0x7F00U)
#define XBARA_SEL42_SEL85_SHIFT (8U)
#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
/*! @} */
/*! @name SEL43 - Crossbar A Select Register 43 */
/*! @{ */
#define XBARA_SEL43_SEL86_MASK (0x7FU)
#define XBARA_SEL43_SEL86_SHIFT (0U)
#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
#define XBARA_SEL43_SEL87_MASK (0x7F00U)
#define XBARA_SEL43_SEL87_SHIFT (8U)
#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
/*! @} */
/*! @name SEL44 - Crossbar A Select Register 44 */
/*! @{ */
#define XBARA_SEL44_SEL88_MASK (0x7FU)
#define XBARA_SEL44_SEL88_SHIFT (0U)
#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
#define XBARA_SEL44_SEL89_MASK (0x7F00U)
#define XBARA_SEL44_SEL89_SHIFT (8U)
#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
/*! @} */
/*! @name SEL45 - Crossbar A Select Register 45 */
/*! @{ */
#define XBARA_SEL45_SEL90_MASK (0x7FU)
#define XBARA_SEL45_SEL90_SHIFT (0U)
#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
#define XBARA_SEL45_SEL91_MASK (0x7F00U)
#define XBARA_SEL45_SEL91_SHIFT (8U)
#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
/*! @} */
/*! @name SEL46 - Crossbar A Select Register 46 */
/*! @{ */
#define XBARA_SEL46_SEL92_MASK (0x7FU)
#define XBARA_SEL46_SEL92_SHIFT (0U)
#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
#define XBARA_SEL46_SEL93_MASK (0x7F00U)
#define XBARA_SEL46_SEL93_SHIFT (8U)
#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
/*! @} */
/*! @name SEL47 - Crossbar A Select Register 47 */
/*! @{ */
#define XBARA_SEL47_SEL94_MASK (0x7FU)
#define XBARA_SEL47_SEL94_SHIFT (0U)
#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
#define XBARA_SEL47_SEL95_MASK (0x7F00U)
#define XBARA_SEL47_SEL95_SHIFT (8U)
#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
/*! @} */
/*! @name SEL48 - Crossbar A Select Register 48 */
/*! @{ */
#define XBARA_SEL48_SEL96_MASK (0x7FU)
#define XBARA_SEL48_SEL96_SHIFT (0U)
#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
#define XBARA_SEL48_SEL97_MASK (0x7F00U)
#define XBARA_SEL48_SEL97_SHIFT (8U)
#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
/*! @} */
/*! @name SEL49 - Crossbar A Select Register 49 */
/*! @{ */
#define XBARA_SEL49_SEL98_MASK (0x7FU)
#define XBARA_SEL49_SEL98_SHIFT (0U)
#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
#define XBARA_SEL49_SEL99_MASK (0x7F00U)
#define XBARA_SEL49_SEL99_SHIFT (8U)
#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
/*! @} */
/*! @name SEL50 - Crossbar A Select Register 50 */
/*! @{ */
#define XBARA_SEL50_SEL100_MASK (0x7FU)
#define XBARA_SEL50_SEL100_SHIFT (0U)
#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
#define XBARA_SEL50_SEL101_MASK (0x7F00U)
#define XBARA_SEL50_SEL101_SHIFT (8U)
#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
/*! @} */
/*! @name SEL51 - Crossbar A Select Register 51 */
/*! @{ */
#define XBARA_SEL51_SEL102_MASK (0x7FU)
#define XBARA_SEL51_SEL102_SHIFT (0U)
#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
#define XBARA_SEL51_SEL103_MASK (0x7F00U)
#define XBARA_SEL51_SEL103_SHIFT (8U)
#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
/*! @} */
/*! @name SEL52 - Crossbar A Select Register 52 */
/*! @{ */
#define XBARA_SEL52_SEL104_MASK (0x7FU)
#define XBARA_SEL52_SEL104_SHIFT (0U)
#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
#define XBARA_SEL52_SEL105_MASK (0x7F00U)
#define XBARA_SEL52_SEL105_SHIFT (8U)
#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
/*! @} */
/*! @name SEL53 - Crossbar A Select Register 53 */
/*! @{ */
#define XBARA_SEL53_SEL106_MASK (0x7FU)
#define XBARA_SEL53_SEL106_SHIFT (0U)
#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
#define XBARA_SEL53_SEL107_MASK (0x7F00U)
#define XBARA_SEL53_SEL107_SHIFT (8U)
#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
/*! @} */
/*! @name SEL54 - Crossbar A Select Register 54 */
/*! @{ */
#define XBARA_SEL54_SEL108_MASK (0x7FU)
#define XBARA_SEL54_SEL108_SHIFT (0U)
#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
#define XBARA_SEL54_SEL109_MASK (0x7F00U)
#define XBARA_SEL54_SEL109_SHIFT (8U)
#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
/*! @} */
/*! @name SEL55 - Crossbar A Select Register 55 */
/*! @{ */
#define XBARA_SEL55_SEL110_MASK (0x7FU)
#define XBARA_SEL55_SEL110_SHIFT (0U)
#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
#define XBARA_SEL55_SEL111_MASK (0x7F00U)
#define XBARA_SEL55_SEL111_SHIFT (8U)
#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
/*! @} */
/*! @name SEL56 - Crossbar A Select Register 56 */
/*! @{ */
#define XBARA_SEL56_SEL112_MASK (0x7FU)
#define XBARA_SEL56_SEL112_SHIFT (0U)
#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
#define XBARA_SEL56_SEL113_MASK (0x7F00U)
#define XBARA_SEL56_SEL113_SHIFT (8U)
#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
/*! @} */
/*! @name SEL57 - Crossbar A Select Register 57 */
/*! @{ */
#define XBARA_SEL57_SEL114_MASK (0x7FU)
#define XBARA_SEL57_SEL114_SHIFT (0U)
#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
#define XBARA_SEL57_SEL115_MASK (0x7F00U)
#define XBARA_SEL57_SEL115_SHIFT (8U)
#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
/*! @} */
/*! @name SEL58 - Crossbar A Select Register 58 */
/*! @{ */
#define XBARA_SEL58_SEL116_MASK (0x7FU)
#define XBARA_SEL58_SEL116_SHIFT (0U)
#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
#define XBARA_SEL58_SEL117_MASK (0x7F00U)
#define XBARA_SEL58_SEL117_SHIFT (8U)
#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
/*! @} */
/*! @name SEL59 - Crossbar A Select Register 59 */
/*! @{ */
#define XBARA_SEL59_SEL118_MASK (0x7FU)
#define XBARA_SEL59_SEL118_SHIFT (0U)
#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
#define XBARA_SEL59_SEL119_MASK (0x7F00U)
#define XBARA_SEL59_SEL119_SHIFT (8U)
#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
/*! @} */
/*! @name SEL60 - Crossbar A Select Register 60 */
/*! @{ */
#define XBARA_SEL60_SEL120_MASK (0x7FU)
#define XBARA_SEL60_SEL120_SHIFT (0U)
#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
#define XBARA_SEL60_SEL121_MASK (0x7F00U)
#define XBARA_SEL60_SEL121_SHIFT (8U)
#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
/*! @} */
/*! @name SEL61 - Crossbar A Select Register 61 */
/*! @{ */
#define XBARA_SEL61_SEL122_MASK (0x7FU)
#define XBARA_SEL61_SEL122_SHIFT (0U)
#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
#define XBARA_SEL61_SEL123_MASK (0x7F00U)
#define XBARA_SEL61_SEL123_SHIFT (8U)
#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
/*! @} */
/*! @name SEL62 - Crossbar A Select Register 62 */
/*! @{ */
#define XBARA_SEL62_SEL124_MASK (0x7FU)
#define XBARA_SEL62_SEL124_SHIFT (0U)
#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
#define XBARA_SEL62_SEL125_MASK (0x7F00U)
#define XBARA_SEL62_SEL125_SHIFT (8U)
#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
/*! @} */
/*! @name SEL63 - Crossbar A Select Register 63 */
/*! @{ */
#define XBARA_SEL63_SEL126_MASK (0x7FU)
#define XBARA_SEL63_SEL126_SHIFT (0U)
#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
#define XBARA_SEL63_SEL127_MASK (0x7F00U)
#define XBARA_SEL63_SEL127_SHIFT (8U)
#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
/*! @} */
/*! @name SEL64 - Crossbar A Select Register 64 */
/*! @{ */
#define XBARA_SEL64_SEL128_MASK (0x7FU)
#define XBARA_SEL64_SEL128_SHIFT (0U)
#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
#define XBARA_SEL64_SEL129_MASK (0x7F00U)
#define XBARA_SEL64_SEL129_SHIFT (8U)
#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
/*! @} */
/*! @name SEL65 - Crossbar A Select Register 65 */
/*! @{ */
#define XBARA_SEL65_SEL130_MASK (0x7FU)
#define XBARA_SEL65_SEL130_SHIFT (0U)
#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
#define XBARA_SEL65_SEL131_MASK (0x7F00U)
#define XBARA_SEL65_SEL131_SHIFT (8U)
#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
/*! @} */
/*! @name CTRL0 - Crossbar A Control Register 0 */
/*! @{ */
#define XBARA_CTRL0_DEN0_MASK (0x1U)
#define XBARA_CTRL0_DEN0_SHIFT (0U)
#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
#define XBARA_CTRL0_IEN0_MASK (0x2U)
#define XBARA_CTRL0_IEN0_SHIFT (1U)
#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
#define XBARA_CTRL0_EDGE0_MASK (0xCU)
#define XBARA_CTRL0_EDGE0_SHIFT (2U)
#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
#define XBARA_CTRL0_STS0_MASK (0x10U)
#define XBARA_CTRL0_STS0_SHIFT (4U)
#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
#define XBARA_CTRL0_DEN1_MASK (0x100U)
#define XBARA_CTRL0_DEN1_SHIFT (8U)
#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
#define XBARA_CTRL0_IEN1_MASK (0x200U)
#define XBARA_CTRL0_IEN1_SHIFT (9U)
#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
#define XBARA_CTRL0_EDGE1_SHIFT (10U)
#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
#define XBARA_CTRL0_STS1_MASK (0x1000U)
#define XBARA_CTRL0_STS1_SHIFT (12U)
#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
/*! @} */
/*! @name CTRL1 - Crossbar A Control Register 1 */
/*! @{ */
#define XBARA_CTRL1_DEN2_MASK (0x1U)
#define XBARA_CTRL1_DEN2_SHIFT (0U)
#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
#define XBARA_CTRL1_IEN2_MASK (0x2U)
#define XBARA_CTRL1_IEN2_SHIFT (1U)
#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
#define XBARA_CTRL1_EDGE2_MASK (0xCU)
#define XBARA_CTRL1_EDGE2_SHIFT (2U)
#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
#define XBARA_CTRL1_STS2_MASK (0x10U)
#define XBARA_CTRL1_STS2_SHIFT (4U)
#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
#define XBARA_CTRL1_DEN3_MASK (0x100U)
#define XBARA_CTRL1_DEN3_SHIFT (8U)
#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
#define XBARA_CTRL1_IEN3_MASK (0x200U)
#define XBARA_CTRL1_IEN3_SHIFT (9U)
#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
#define XBARA_CTRL1_EDGE3_SHIFT (10U)
#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
#define XBARA_CTRL1_STS3_MASK (0x1000U)
#define XBARA_CTRL1_STS3_SHIFT (12U)
#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XBARA_Register_Masks */
/* XBARA - Peripheral instance base addresses */
/** Peripheral XBARA1 base address */
#define XBARA1_BASE (0x403BC000u)
/** Peripheral XBARA1 base pointer */
#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
/** Array initializer of XBARA peripheral base addresses */
#define XBARA_BASE_ADDRS { XBARA1_BASE }
/** Array initializer of XBARA peripheral base pointers */
#define XBARA_BASE_PTRS { XBARA1 }
/*!
* @}
*/ /* end of group XBARA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XBARB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
* @{
*/
/** XBARB - Register Layout Typedef */
typedef struct {
__IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */
__IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */
__IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */
__IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */
__IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */
__IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */
__IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */
__IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */
} XBARB_Type;
/* ----------------------------------------------------------------------------
-- XBARB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARB_Register_Masks XBARB Register Masks
* @{
*/
/*! @name SEL0 - Crossbar B Select Register 0 */
/*! @{ */
#define XBARB_SEL0_SEL0_MASK (0x3FU)
#define XBARB_SEL0_SEL0_SHIFT (0U)
#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
#define XBARB_SEL0_SEL1_MASK (0x3F00U)
#define XBARB_SEL0_SEL1_SHIFT (8U)
#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
/*! @} */
/*! @name SEL1 - Crossbar B Select Register 1 */
/*! @{ */
#define XBARB_SEL1_SEL2_MASK (0x3FU)
#define XBARB_SEL1_SEL2_SHIFT (0U)
#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
#define XBARB_SEL1_SEL3_MASK (0x3F00U)
#define XBARB_SEL1_SEL3_SHIFT (8U)
#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
/*! @} */
/*! @name SEL2 - Crossbar B Select Register 2 */
/*! @{ */
#define XBARB_SEL2_SEL4_MASK (0x3FU)
#define XBARB_SEL2_SEL4_SHIFT (0U)
#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
#define XBARB_SEL2_SEL5_MASK (0x3F00U)
#define XBARB_SEL2_SEL5_SHIFT (8U)
#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
/*! @} */
/*! @name SEL3 - Crossbar B Select Register 3 */
/*! @{ */
#define XBARB_SEL3_SEL6_MASK (0x3FU)
#define XBARB_SEL3_SEL6_SHIFT (0U)
#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
#define XBARB_SEL3_SEL7_MASK (0x3F00U)
#define XBARB_SEL3_SEL7_SHIFT (8U)
#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
/*! @} */
/*! @name SEL4 - Crossbar B Select Register 4 */
/*! @{ */
#define XBARB_SEL4_SEL8_MASK (0x3FU)
#define XBARB_SEL4_SEL8_SHIFT (0U)
#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
#define XBARB_SEL4_SEL9_MASK (0x3F00U)
#define XBARB_SEL4_SEL9_SHIFT (8U)
#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
/*! @} */
/*! @name SEL5 - Crossbar B Select Register 5 */
/*! @{ */
#define XBARB_SEL5_SEL10_MASK (0x3FU)
#define XBARB_SEL5_SEL10_SHIFT (0U)
#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
#define XBARB_SEL5_SEL11_MASK (0x3F00U)
#define XBARB_SEL5_SEL11_SHIFT (8U)
#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
/*! @} */
/*! @name SEL6 - Crossbar B Select Register 6 */
/*! @{ */
#define XBARB_SEL6_SEL12_MASK (0x3FU)
#define XBARB_SEL6_SEL12_SHIFT (0U)
#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
#define XBARB_SEL6_SEL13_MASK (0x3F00U)
#define XBARB_SEL6_SEL13_SHIFT (8U)
#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
/*! @} */
/*! @name SEL7 - Crossbar B Select Register 7 */
/*! @{ */
#define XBARB_SEL7_SEL14_MASK (0x3FU)
#define XBARB_SEL7_SEL14_SHIFT (0U)
#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
#define XBARB_SEL7_SEL15_MASK (0x3F00U)
#define XBARB_SEL7_SEL15_SHIFT (8U)
#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XBARB_Register_Masks */
/* XBARB - Peripheral instance base addresses */
/** Peripheral XBARB2 base address */
#define XBARB2_BASE (0x403C0000u)
/** Peripheral XBARB2 base pointer */
#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
/** Peripheral XBARB3 base address */
#define XBARB3_BASE (0x403C4000u)
/** Peripheral XBARB3 base pointer */
#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
/** Array initializer of XBARB peripheral base addresses */
#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
/** Array initializer of XBARB peripheral base pointers */
#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
/*!
* @}
*/ /* end of group XBARB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XTALOSC24M Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer
* @{
*/
/** XTALOSC24M - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[336];
__IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
__IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
__IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
__IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
uint8_t RESERVED_1[272];
__IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */
__IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */
__IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */
__IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */
uint8_t RESERVED_2[32];
__IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */
__IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */
__IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */
__IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */
__IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */
__IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */
__IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */
__IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */
__IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */
__IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */
__IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */
__IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */
} XTALOSC24M_Type;
/* ----------------------------------------------------------------------------
-- XTALOSC24M Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks
* @{
*/
/*! @name MISC0 - Miscellaneous Register 0 */
/*! @{ */
#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_SET - Miscellaneous Register 0 */
/*! @{ */
#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_CLR - Miscellaneous Register 0 */
/*! @{ */
#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name MISC0_TOG - Miscellaneous Register 0 */
/*! @{ */
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
/*! @} */
/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */
/*! @{ */
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
/*! @} */
/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */
/*! @{ */
#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
/*! @} */
/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */
/*! @{ */
#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
/*! @} */
/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */
/*! @{ */
#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
/*! @} */
/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
/*! @} */
/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
/*! @} */
/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
/*! @} */
/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
/*! @} */
/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */
/*! @{ */
#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XTALOSC24M_Register_Masks */
/* XTALOSC24M - Peripheral instance base addresses */
/** Peripheral XTALOSC24M base address */
#define XTALOSC24M_BASE (0x400D8000u)
/** Peripheral XTALOSC24M base pointer */
#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
/** Array initializer of XTALOSC24M peripheral base addresses */
#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
/** Array initializer of XTALOSC24M peripheral base pointers */
#define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/*!
* @}
*/ /* end of group XTALOSC24M_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#else
#pragma pop
#endif
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
---------------------------------------------------------------------------- */
/*!
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
* @{
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang system_header
#endif
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma system_include
#endif
/**
* @brief Mask and left-shift a bit field value for use in a register bit range.
* @param field Name of the register bit field.
* @param value Value of the bit field.
* @return Masked and shifted value.
*/
#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
* @brief Mask and right-shift a register value to extract a bit field value.
* @param field Name of the register bit field.
* @param value Value of the register.
* @return Masked and shifted bit field value.
*/
#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
/*!
* @}
*/ /* end of group Bit_Field_Generic_Macros */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
/* No SDK compatibility issues. */
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _MIMXRT1052_H_ */
| [
"noreply@github.com"
] | Marous-LXB.noreply@github.com |
080332078a234e946ed79e635af70dd697b9fb82 | 9670de11489d39c0923b11b371eacb89cbf20db2 | /xt_KEYBRDLED.c | 3b16b393c0baf1fe6bb8a8efbf7d1555c99d8186 | [] | no_license | supermartian/xt_KEYBRDLED | 77a7a286782c20e0de63979e2641334be2abf465 | dad02c73c007f869c61caf7cc3849ab2f7969058 | refs/heads/master | 2016-09-06T14:41:21.880199 | 2012-11-12T01:05:35 | 2012-11-12T01:05:35 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,411 | c | /*
* xt_KEYBRDLED.c - netfilter target to make LEDs blink upon packet matches
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301 USA.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/skbuff.h>
#include <linux/netfilter/x_tables.h>
#include <linux/init.h>
#include <linux/tty.h>
#include <linux/kbd_kern.h>
#include <linux/vt_kern.h>
#include <linux/console_struct.h>
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Yuzhong Wen <supermartian@gmail.com>");
MODULE_DESCRIPTION("Xtables: trigger Keyboard LEDs on packet match");
MODULE_ALIAS("ipt_KEYBRDLED");
MODULE_ALIAS("ip6t_KEYBRDLED");
#define ALL_LEDS_ON 0x07
#define RESTORE_LEDS 0xFF
struct tty_driver *tty;
static unsigned long status;
static void blink()
{
if (status == ALL_LEDS_ON) {
status = RESTORE_LEDS;
} else {
status = ALL_LEDS_ON;
}
(tty->ops->ioctl) (vc_cons[fg_console].d->vc_tty, NULL, KDSETLED, status);
}
static unsigned int
keybrdled_tg(struct sk_buff *skb, const struct xt_action_param *par)
{
blink();
return XT_CONTINUE;
}
static struct xt_target keybrdled_tg_reg __read_mostly = {
.name = "KEYBRDLED",
.revision = 0,
.family = NFPROTO_UNSPEC,
.target = keybrdled_tg,
.me = THIS_MODULE,
};
static int __init keybrdled_tg_init(void)
{
status = ALL_LEDS_ON;
int i;
for (i = 0; i < MAX_NR_CONSOLES; i++) {
if (!vc_cons[i].d) {
break;
}
}
tty = vc_cons[fg_console].d->vc_tty->driver;
return xt_register_target(&keybrdled_tg_reg);
}
static void __exit keybrdled_tg_exit(void)
{
(tty->ops->ioctl) (vc_cons[fg_console].d->vc_tty, NULL, KDSETLED, RESTORE_LEDS);
xt_unregister_target(&keybrdled_tg_reg);
}
module_init(keybrdled_tg_init);
module_exit(keybrdled_tg_exit);
| [
"supermartian@gmail.com"
] | supermartian@gmail.com |
fb3e169a181d0a3d764916eb15ff205a22d58c7e | 85928c48de769b07867cd2145f2123d391e14f1b | /STM32F429_uCOS_III/STM32F429_uCOS_III/APP/TASK_thread_tel.c | 9acc496c40dbe2b905351e99039c026e9f487bff | [] | no_license | pandy1208/git-github.com-pandy1208-home | a05149ba016939c90e18c609c1657f6b7742530a | 56bb4d101b38af1eadb305e04f03891eb2b9cf13 | refs/heads/master | 2021-01-15T22:51:37.317751 | 2017-08-16T02:51:23 | 2017-08-16T02:51:23 | 99,919,125 | 1 | 0 | null | null | null | null | GB18030 | C | false | false | 487 | c | #include <includes.h>
#include <task_variable.h>
void task_thread_tel(void *p_arg)
{
OS_ERR err;
OS_MSG_SIZE size;
unsigned char *p_rev,*p_data;//p_rev指向动态内存头结点用于释放内存
//p_data指向数据用于查找
p_rev = OSQPend(TEL_Q,0,OS_OPT_PEND_BLOCKING,&size,(CPU_TS*)0,&err); //阻塞等待管道TEL_Q数据
/*数据处理*/
/*数据处理*/
OSMemPut(buf_s485,p_rev,&err); //释放内存，内存池为buf_s485
}
| [
"15968183760@163.com"
] | 15968183760@163.com |
ae14cb90379ba1a9629c359164803732e978d9cf | 91766ab9dba0fb155c373cfddab70481a76424c0 | /network.h | 3053334ef7927ca41a2c8a42f0304de023438e7f | [] | no_license | Alecppt/lyrebirdTweet | 3df9104a70eb55d1bbecbae5caa1771e916dc249 | 7bfd2ec1173127e8e550bf924b3389f25c589005 | refs/heads/master | 2021-01-13T00:48:21.784670 | 2016-01-26T08:43:12 | 2016-01-26T08:43:12 | 50,415,089 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 322 | h | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <netinet/in.h>
#include <netdb.h>
#include <arpa/inet.h>
#include <ifaddrs.h>
#include <unistd.h>
#pragma once
#define BACKLOG 10
int socket_setup();
int getPortNum(int sockfd);
void getIPAddr(char* ip);
| [
"cca169@sfu.ca"
] | cca169@sfu.ca |
f41288c4981852b82ef664c0f8020a277fed3b12 | 0edbcda83b7a9542f15f706573a8e21da51f6020 | /private/inet/mshtml/tried/triedit/resource.h | 137d94c6d92e08037125c1b06812c92c280e6e25 | [] | no_license | yair-k/Win2000SRC | fe9f6f62e60e9bece135af15359bb80d3b65dc6a | fd809a81098565b33f52d0f65925159de8f4c337 | refs/heads/main | 2023-04-12T08:28:31.485426 | 2021-05-08T22:47:00 | 2021-05-08T22:47:00 | 365,623,923 | 1 | 3 | null | null | null | null | UTF-8 | C | false | false | 2,131 | h | //{{NO_DEPENDENCIES}}
// Microsoft Developer Studio generated include file.
// Copyright (c)1997-1999 Microsoft Corporation, All Rights Reserved
// Used by triedit.rc
//
#define IDS_PROJNAME 100
#define IDR_TRIEDITDOCUMENT 101
#define IDR_FEEDBACKRECTBMP 102
#define IDS_HTML 101
#define IDS_IEXP3 103
#define IDR_HTML 104
#define IDS_RFC1866 105
#define IDR_ASP 106
#define IDR_HTMPARSE 107
#define IDR_TRIEDITPARSE 107
#define IDS_GLYPHTABLE1 201
#define IDS_GLYPHTABLE2 202
#define IDS_GLYPHTABLE3 203
#define IDS_GLYPHTABLE4 204
#define IDS_GLYPHTABLE5 205
#define IDS_GLYPHTABLE6 206
#define IDS_GLYPHTABLE7 207
#define IDS_GLYPHTABLE8 208
#define IDS_GLYPHTABLE9 209
#define IDS_GLYPHTABLE10 210
#define IDS_GLYPHTABLE11 211
#define IDS_GLYPHTABLE12 212
#define IDS_GLYPHTABLE13 213
#define IDS_GLYPHTABLE14 214
#define IDS_GLYPHTABLE15 215
#define IDS_GLYPHTABLE16 216
#define IDS_GLYPHTABLE17 217
#define IDS_GLYPHTABLE18 218
#define IDS_GLYPHTABLE19 219
#define IDS_GLYPHTABLE20 220
#define IDS_GLYPHTABLE21 221
#define IDS_GLYPHTABLE22 222
#define IDS_GLYPHTABLE23 223
#define IDS_GLYPHTABLE24 224
#define IDS_GLYPHTABLESTART IDS_GLYPHTABLE1
#define IDS_GLYPHTABLEFORMEND IDS_GLYPHTABLE2
#define IDS_GLYPHTABLEEND IDS_GLYPHTABLE24
// Next default values for new objects
//
#ifdef APSTUDIO_INVOKED
#ifndef APSTUDIO_READONLY_SYMBOLS
#define _APS_NEXT_RESOURCE_VALUE 202
#define _APS_NEXT_COMMAND_VALUE 32768
#define _APS_NEXT_CONTROL_VALUE 201
#define _APS_NEXT_SYMED_VALUE 150
#endif
#endif
| [
"ykorokhov@pace.ca"
] | ykorokhov@pace.ca |
17787a08ca11667cac400399861036002140854e | 5b3110de8aaa18bdc72770b56e7941481209923c | /0x01-variables_if_else_while/7-print_tebahpla.c | b8ab9d7f893bcb11b90298328886af36c7e580e3 | [] | no_license | divinej/alx-low_level_programming | dcbe231332a8b92927a6a3131b33853b8e5adba8 | f435cad9176e0581e6955698023c3ad4a40e465d | refs/heads/main | 2023-08-22T11:46:50.984438 | 2021-11-02T13:56:28 | 2021-11-02T13:56:28 | 401,829,592 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 242 | c | #include <stdio.h>
/**
* main - Entry point
* prints the lowercase alphabets in reverse
* followed by a new line
* Return: 0
*/
int main(void)
{
char i;
for (i = 'z'; i >= 'a'; i--)
{
putchar(i);
}
putchar('\n');
return (0);
}
| [
"okodivinejustice@gmail.com"
] | okodivinejustice@gmail.com |
f99a05d417f67388b33cffb87f65d36dab84e401 | e4c82b7f3f0b00ef9ec41e40519ce4418243a792 | /examples/drivers_bm/inc/led.h | e33309a60a1d3e87bfffb99555948afa2879e2bf | [] | no_license | sambranaivan/CIAA-Firmware | 227f4b1d84fb1f9f5b048d3fc910c0f6b684d7bb | c4f688a50330d0d5ed15499c08aa5e17b75085f5 | refs/heads/master | 2021-01-22T23:07:23.526595 | 2017-06-21T20:55:36 | 2017-06-21T20:55:36 | 85,613,316 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,072 | h | /* Copyright 2016, XXXXXXXXXX
* All rights reserved.
*
* This file is part of CIAA Firmware.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef LED_H
#define LED_H
/** \brief Bare Metal example header file
**
** This is a mini example of the CIAA Firmware
**
**/
/** \addtogroup CIAA_Firmware CIAA Firmware
** @{ */
/** \addtogroup Examples CIAA Firmware Examples
** @{ */
/** \addtogroup Baremetal Bare Metal example header file
** @{ */
/*
* Initials Name
* ---------------------------
*
*/
/*
* modification history (new versions first)
* -----------------------------------------------------------
* yyyymmdd v0.0.1 initials initial version
*/
/*==================[inclusions]=============================================*/
#include "stdint.h"
/*==================[macros]=================================================*/
#define lpc4337 1
#define mk60fx512vlq15 2
//#define TRUE 1
//#define FALSE 0
#define LED_ROJO 1
#define LED_VERDE 2
#define LED_AZUL 3
#define LED1 4
#define LED2 5
#define LED3 6
#define LED_PROTO 7
#define LED_GPIO8 8
/*==================[typedef]================================================*/
/*==================[external data declaration]==============================*/
void InitLed(void);
void EncenderLed(uint8_t led);
void ApagarLed(uint8_t led);
void ApagarLeds(void);
void CambiarLed(uint8_t led);
/*==================[external functions declaration]=========================*/
/*==================[end of file]============================================*/
#endif /* #ifndef MI_NUEVO_PROYECTO_H */
| [
"sambranaivan@gmail.com"
] | sambranaivan@gmail.com |
4ae3d60c82ad0a184541b4426a71026ecb84d361 | f79ef81e6e4e989ed14ed0283a9737f731101aab | /Unix Family/Linux.Urk/login/mailpath.c | 4abf5cf49069b0457961af8181a5ee0af3cdb775 | [
"MIT"
] | permissive | TheWover/Family | 9d5597eda68aeee5e99de993176b6bd1366b57f1 | f3ed1713c6b71823d8236b80148b60982dd906e1 | refs/heads/master | 2020-09-11T15:11:21.601776 | 2019-10-30T04:33:43 | 2019-10-30T04:33:43 | 222,106,609 | 3 | 4 | MIT | 2019-11-16T13:54:02 | 2019-11-16T13:54:01 | null | UTF-8 | C | false | false | 2,495 | c | #include "sys_defs.h"
#include <stdio.h>
#include <sys/param.h>
#include <string.h>
char *realpath();
#define _PATH_MAILDIR "/var/spool/mail"
/* Macros to hide the differences between SunOS 4.x and SunOS 5.x. */
#ifdef USE_SYS_MNTTAB_H
#include <sys/mnttab.h>
#define _PATH_MTAB "/etc/mnttab"
#define SETMNTENT(file,mode) fopen(file,mode)
#define GETMNTENT(fp,mp) (getmntent(fp, mp) == 0)
#define ENDMNTENT(fp) fclose(fp)
#define SPECIAL(mp) (mp)->mnt_special
#define MOUNTPOINT(mp) (mp)->mnt_mountp
#else
#include <mntent.h>
#define _PATH_MTAB "/etc/mtab"
#define SETMNTENT(file,mode) setmntent(file,mode)
#define GETMNTENT(fp,mp) ((mp = getmntent(fp)) != 0)
#define ENDMNTENT(fp) endmntent(fp)
#define SPECIAL(mp) (mp)->mnt_fsname
#define MOUNTPOINT(mp) (mp)->mnt_dir
#endif
/* mailpath - map homedir to mailbox path */
char *mail_path(home, user)
char *home;
char *user;
{
static char mailpath[BUFSIZ];
char home_info[BUFSIZ];
char real_home[MAXPATHLEN];
FILE *fp;
int longest_match = 0;
int len_mountp;
char *cp;
#ifdef SYSV4
struct mnttab mnt;
#define mp (&mnt)
#else
struct mntent *mp;
#endif
/*
* Try to deduce mailpath from home directory mount information. Use
* /var/spool/mail/user when the mount is local, otherwise insert the
* unqualified name of the home directory file server before the
* username.
*/
if (realpath(home, real_home) && (fp = SETMNTENT(_PATH_MTAB, "r")) != 0) {
while (GETMNTENT(fp, mp)) {
len_mountp = strlen(MOUNTPOINT(mp));
if (len_mountp > longest_match && real_home[len_mountp] == '/'
&& strncmp(real_home, MOUNTPOINT(mp), len_mountp) == 0) {
longest_match = len_mountp;
strcpy(home_info, SPECIAL(mp));
}
}
ENDMNTENT(fp);
}
/*
* If the home directory comes from a remote host the filesystem name is
* of the form host:/some/path. Truncate the host to unqualified form.
*/
if (longest_match > 0 && (cp = strchr(home_info, ':')) != 0) {
*cp = 0;
if ((cp = strchr(home_info, '.')) != 0)
*cp = 0;
sprintf(mailpath, "%s/%s/%s", _PATH_MAILDIR, home_info, user);
} else {
sprintf(mailpath, "%s/%s", _PATH_MAILDIR, user);
}
return (mailpath);
}
#ifdef STANDALONE
#include <pwd.h>
main()
{
struct passwd *pwd;
if ((pwd = getpwuid(getuid())) == 0) {
fprintf(stderr, "Who are you?\n");
exit(1);
}
printf("%s\n", mail_path(pwd->pw_dir, pwd->pw_name));
}
#endif
| [
"57078196+vxunderground@users.noreply.github.com"
] | 57078196+vxunderground@users.noreply.github.com |
2309c2f19c66764264ea3ab769a6bd864c44f632 | 57d8c8f129bfb7cd600fbc4f68f68d83e3451f68 | /cupy/cuda/cupy_common.h | e1b2ac01e839dc6a929c78d5c0593aa34920a67d | [
"MIT",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | anurocks1/cupy | 4f979c6b16ef7f53dcccebf944103e7ec7e3de3b | 1011b8085228c978ffad2154aba4b31e71f97c14 | refs/heads/master | 2021-01-06T00:49:18.441306 | 2020-02-17T13:10:15 | 2020-02-17T13:10:15 | 241,181,747 | 2 | 0 | MIT | 2020-02-17T18:44:06 | 2020-02-17T18:44:06 | null | UTF-8 | C | false | false | 413 | h | #ifndef INCLUDE_GUARD_CUPY_CUDA_COMMON_H
#define INCLUDE_GUARD_CUPY_CUDA_COMMON_H
typedef char cpy_byte;
typedef unsigned char cpy_ubyte;
typedef short cpy_short;
typedef unsigned short cpy_ushort;
typedef int cpy_int;
typedef unsigned int cpy_uint;
typedef long long cpy_long;
typedef unsigned long long cpy_ulong;
typedef float cpy_float;
typedef double cpy_double;
#endif // INCLUDE_GUARD_CUPY_CUDA_COMMON_H
| [
"kamonama@gmail.com"
] | kamonama@gmail.com |
ef344213f993795f9208ee9cf48a277f71b08c89 | 50c1465a0c1abeeafdae1d1cb6c623ca63900e42 | /grafika/btnArmory.h | 528efdc1dc7597ad445d86d3860e0bf6c3c959ac | [] | no_license | siof/hellground-launcher | 62f3579277ef9b45c37ef2c188a35b9d3c6cf0eb | 7c607c87264eb213443e1ab6f95a10125f8f404b | refs/heads/master | 2020-08-12T17:46:26.093391 | 2010-05-23T20:28:06 | 2010-05-23T20:28:06 | 214,812,269 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 20,828 | h | #ifndef BTNARMORY_H_INCLUDED
#define BTNARMORY_H_INCLUDED
/* XPM */
static char * btnArmoryXpm[] = {
"127 63 256 2",
" c #6D92A5",
". c #1A72A9",
"+ c #1D5170",
"@ c #2E627E",
"# c #40758F",
"$ c #093554",
"% c #376881",
"& c #1D5574",
"* c #84ABBC",
"= c #235B79",
"- c #688A9A",
"; c #113A55",
"> c #194E6D",
", c #063251",
"' c #184561",
") c #24516C",
"! c #113D59",
"~ c #144866",
"{ c #0D3956",
"] c #214A65",
"^ c #7BAABD",
"/ c #11415D",
"( c #154461",
"_ c #0D3C5A",
": c #1C4E6D",
"< c #1A4966",
"[ c #236A96",
"} c #0D4160",
"| c #0D405E",
"1 c #3D728D",
"2 c #1A7DBA",
"3 c #0D3E5C",
"4 c #257292",
"5 c #2A536C",
"6 c #1D5472",
"7 c #1A5170",
"8 c #145274",
"9 c #1E2B37",
"0 c #114564",
"a c #194C69",
"b c #1A506D",
"c c #1D506E",
"d c #7295A7",
"e c #2482BB",
"f c #8BAEC0",
"g c #215876",
"h c #1E597A",
"i c #154A69",
"j c #39454E",
"k c #154C6A",
"l c #224D68",
"m c #18425E",
"n c #2E6580",
"o c #032D4D",
"p c #2B5A74",
"q c #598297",
"r c #68737A",
"s c #093452",
"t c #093856",
"u c #2B89C4",
"v c #134E72",
"w c #0A3A58",
"x c #164D6C",
"y c #2B83BB",
"z c #093E5D",
"A c #143E59",
"B c #205575",
"C c #247DB3",
"D c #478BA4",
"E c #246281",
"F c #2273A6",
"G c #114968",
"H c #0E4565",
"I c #5B8AA0",
"J c #194A68",
"K c #1B7AB4",
"L c #0D4A6C",
"M c #114462",
"N c #1D4A64",
"O c #58656D",
"P c #3B839E",
"Q c #297594",
"R c #1C4C6A",
"S c #3396CE",
"T c #19628D",
"U c #0B466D",
"V c #505B64",
"W c #298DC9",
"X c #104260",
"Y c #13537B",
"Z c #1A5578",
"` c #1C6591",
" . c #6F7B82",
".. c #1C4A68",
"+. c #2B83A1",
"@. c #1273AF",
"#. c #5B9BB3",
"$. c #3687A5",
"%. c #145984",
"&. c #6EA4BA",
"*. c #1A6B9C",
"=. c #308BC4",
"-. c #194664",
";. c #1E5775",
">. c #073452",
",. c #156DA3",
"'. c #0D3A58",
"). c #1C80BC",
"!. c #154664",
"~. c #083251",
"{. c #1A5474",
"]. c #154360",
"^. c #327995",
"/. c #14425E",
"(. c #2389C4",
"_. c #1C5B81",
":. c #073554",
"<. c #2284C0",
"[. c #166593",
"}. c #1C4561",
"|. c #145D89",
"1. c #626C73",
"2. c #16425E",
"3. c #0A4161",
"4. c #073B5B",
"5. c #2D556F",
"6. c #0C527A",
"7. c #205270",
"8. c #8A9AA4",
"9. c #15679B",
"0. c #153F5A",
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"V d z+N m A A O.}.p+5.j+m A 0.0.e.0.X.}.5 0+0+) N ' E.i+5.0+0+l E.2.( ( ].].) 0+0+l ].E.l 0+5...E./ / ].].5 ) B.m+/./.' E.) 5.5 < B.! 3 3 _ 3 / < ) ) N ].]././.E.l E._ t t t :.<+$ { m ] ] N.! '.t l+l+<+{ N.] N.! l+g+t I./.l l p+].! '.t g+w g+_ w 3 } `.=+",
"V z+N m 0.0.0.A m 5.j+0.0.e.e.e.e.e.e.5 5.) B.].B.B.D.i+0+5 ].( ( ].( X.) 0+0+E.( ( ].( ) 5 /./.].].].i+0+0+N m+m+/ / / N 5 p+I.3 ! _ 3 / /.l 5 N _ t _ _ _ _ w '.X.] e.:.:.>., l., , ] ] '.:.l+>.:.:.'.] i+m t l+g+g+t t t X.l ] d+t t t t l+t t _ w 3.G Q ",
"k.d z+] m 0.0.0.0.0.] p+O.A A 0.e.0.e.X.0+0+' /./.D.2.2.l 0+5 ].].].].( ) 0+5.E.]././.].( l ) ].B.( ].' 5.0+5 F././ / / 4+N 5 l I.3 3 ! 3 /.) p+N t g+g+_ _ '.w t t g+' ] ! >., , , , , ] ] '., , >.<+d+N ] m :.l+:.t t d+t t 2.l 2+t d+d+d+d+d+d+l+:.t } 8+=+",
"k. p N m 0.A 0.0.0.O.5 m A A 0.e.0.e.p+0+) /./././.D./.l 0+5 ].].].( i+5.5.E.].].]./.].( l ) ].( ( ].l 5.5.' l i+/ I.I./ N 5 l I._ I.I.3 l p+l { t g+w _ '.w t d+$ >.t ] ] '., , >., , ] ] { , , , >.2+] }.:.:.l+l+l+d+d+d+l+m l 2+d+d+d+d+l+'.t w >.l+4.c+4 ",
"k. F.N.O.A A 0.0.0.A j+l 0.0.A e.e.m 5.0+E././.D.D.B.B.l 5.p+/.].X.E.5 5 N B././.B.B.].( N ) B.( B.( 5 5.< / /.5 ].I.I./ N 5 E.'._ _ _ 2.p+p+X.d+g+g+_ { g+$ >.>.>.:.$ ' ] X., , >., , ] ] d+<+>., }.] 2+l+l+:.l+l+l+g+t $ $ O.] 2+$ s :.$ $ $ $ $ , :.4.H 4 ",
"k. F.N.O.A A 0.0.A ! A 5 p+p+p+p+p+5 5.5 /.e.e.%+D.2.D.] 5.p+/.].-.p+l ] ].].B.B.B.B.B.].E.i+( ].%+i+) l / 4+4+' ) I.I.I.}.5 ' '.'.'.'.-.p+l ! $ t w w $ >.>.<+>.>.:.$ /.] ] >., , >., ] ] { , , 2.j+] n.:.:.>.:.:.:.$ $ $ s m ] 2+>.>.>.>., >.>.l.l.>.a+o+Z.",
"k. 5 N.O.A A 0.A A A A j+] 0.0.A e.5.5.N././.e.e.2./.e.N 5 5 l i+l i+N ( ]./.( ( ].].]./.' E./.e.2.] l /.I.! I.I.l N _ '.' p+' { { { { N p+l s >.g+:.t $ :.>., >.>.>.>.A ] j+{ , , , , ] ] }.X.}.] ] ! >.>.s >.9+9+>.9+$ $ { ] l j+'.$ >., , , , [+l., a+3.u.",
"k. F.N O.A A A m.m.m.m.6+5 D.0.m.}.5.5 O.e.$+/.2.e.e.4+j+5 ] 2.].].X.E.E.X.].].]././././.2.E.e.e.B.N.X.I.I.I.! ! P.l ! { ' p+X.{ { g+$ }.l ] , , , >.l+$ $ >., :.>.>.>.P.j+] { , >., , j+j+n., , >.^+N.D.g+:.>.>.>.>.$ $ 9+}.] m '.}.9+l., , l.[+[+l., a+C.u.",
"V - F.N O.A A A ; m.m.A A ] 2+A A p+5 j+e.e./.$+2.$+0.e.] p+N 2.2.2././.' E.]./.]././.e.e./.X.4+D.' m 4+I.I.I._ '.'.X.] { X.l X.{ { $ >.m.] ] , , , , >.:.>.>.>.s >., , m j+j+, >.<+, , j+j+{ <+, >.>.$ ] }.g+>.>.9+s s >.P.] 2+$ , ! 6+[+[+[+[+[+o l., a+C.u.",
"V - F.N.6+A A ; ; m.m.m.! 6+p+P._+p+5 2.e.0.e.$+e.e.4+e.N.] }./././././.m }.-././.e.4+4+4+4+B.! X.' /.I.I._ '._ '.'.{ N.P.2.] 2.{ s , , s }.}.'.9+:., >., , $ s s $ >.$ 2+2+6+, , , , <+j+2+{ 9+<+9+:.<+m 2+P.9+>.>.>.>.$ }.2+n., l.l._+n.[+[+[+[+[+[+<+a+C.u.",
"V - F.N.6+A m.; ; { m.m.m.A }.X.}.l 2+A ! A A A P.P.0.e.X.}.X.e.e.D.2.e.].' ' /.4+4+4+4+! I.e.e././.! _ _ '.{ '.'.'.{ '.m P.m ^+9+, , , , { _+! $ 9+9+9+9+s s 9+$ $ s m._+m s , , , , , _+m n., :., <+, ! _+P., >.9+>., P._+m., l.l.[+l.A l.[+[+[+[+[+, a+C.u.",
"V I F.N.O.A &+&+n.&+; ; m.A O.m }.}.O.A m.m.A m.A A e.0.D.m 2./.D.B.2.D.2.X.2.e.4+4+4+! ! ! e.4+4+^+^+^+^+'.^+^+'.{ { { { ; { { $ ~., , , , { m.n.<+s 9+9+s s $ $ s d+! ! n., , , , , , m.m.$ >.9+, , , m.m.n., , , , 9+m.{ l.[+[+[+o o ~.g.[+o o o [+l.a+C.u.",
"V - ) E.0.; &+&+&+,+,+; m.m.; 6+6+_+m.! A ! A A ! A ! ! D.2.D.e.e.%+/./.2.2.e.4+! ! ! ! ! ! ^+^+'.{ ^+{ '.'.{ { { g+n.s s n.n.{ s , , , , , , n.{ ,+$ >.s s $ $ $ { m.^+g+'.'.{ $ s >.~.,+{ s l., , ~.g.,+n., , , , $ ,+n.~.[+[+[+o o o o ~.~.o o o o l.:.C.u.",
"V q ) ' A &+&+&+,+; ; m.; ; ; ; 6+A ; ; m.! A m.; m.A 0.O.O.D.D.e.D.2.D.e.4+I.4+! ; ^+{ g+{ { ; { { { '.^+'.'.'.{ ~.n.n.$ { { g+g+n.~.~., , , , g+n.^+{ { { { m.m.{ { '.! I.! ^+n.$ { { ,+{ { ,+{ { n.n.~.l., , ~.n.n.n.g.~.l.[+o [+[+l.~.s s ~.~.[+o l.:.C.u.",
"V q ) }.; &+&+&+,+; ; m.m.; m.; ; ; ; ; m.; ; ; ; m.m.A e.e.P.A A 4+4+! ! m.m.m.'.n.s s s g+n.^+^+^+^+^+^+^+{ $ n.{ { { g+g+n.$ $ $ $ ~.~.~.~.~.$ $ $ $ { { { g+d+{ '.{ $ $ s s s ~.9+9+, , , , , , l.l.l.l., , , l.l.[+o [+[+[+o [+[+[+[+o o o [+[+o l.a+C.u.",
"O - ) m ; &+&+,+,+; ; m.; ; ; ; ,+,+; &+{ ; ; ; m.m.m.P.P.A A A A m.m.! m.m.{ n.~.~.s n.s n.^+^+^+^+^+m.{ n.{ n.{ n.{ { g+n.$ s $ g+$ s s >., s $ $ '.{ d+d+d+d+{ d+s $ g+$ s $ s ~.9+~.9+~.~., , , , , , , l., l.[+l.o o [+[+[+o o o o o o o o [+o [+l.a+C.)+",
"V d ) ' ; &+&+&+,+&+; ; ; ; ; ; &+,+,+,+; ; ; ,+; m.A A A A A ! m.m.; m.m.,+~.~.~.~.s n.n.^+m._ ^+^+'.n.{ g+n.n.n.g+{ { g+n.g+$ $ $ $ $ $ ~.9+s $ d+n.d+d+d+d+d+d+9+9+$ d+$ 9+$ 9+~.~., s $ $ 9+, , , , >., l.l.[+[+[+[+[+[+o [+o o o o o o o o o o [+, a+C.-+",
"k.b.% E.A ; ,+&+&+&+&+&+&+; &+&+g.g.g.; ; ; ,+&+,+m.! A ! ! m.! A ! m.; g.~.s ~.s $ $ n.^+! _ _ _ '.d+n.d+n.d+n.{ { { n.n.g+$ n.n.n.$ s $ $ 9+d+d+g+g+d+$ $ s $ $ $ $ $ d+9+9+$ $ 9+9+$ $ d+$ <+<+<+l., , , , l.l.l.l.l.[+[+o o o o o o o o o o o o [+<+a+@+p+",
"j 1.q i+m m.; ,+&+&+&+&+,+,+,+&+g.&+; ; ; &+{ &+,+m.A A A m.A A P.m.n.s s n.~.s s s n.^+I.'.^+'.d+{ { d+n.n.$ { { { n.n.n.n.s $ $ s $ $ $ $ d+d+d+d+d+d+$ $ $ $ $ 9+$ $ 9+$ $ 9+9+$ $ $ $ $ $ 9+, <+, , , , , l.l.[+l.[+[+o o o o o o o o o o o o o [+:.4.H.9 ",
"9 j - % N m m.; &+&+&+; ; ; ; ,+&+; ; ; ; ; ,+&+; A A A A A P.P.m.n.g.s g.s ~.s n.n.^+^+! ! ! { g+{ { '.d+d+{ '.{ { { { n.$ $ $ d+$ $ $ $ $ d+d+'.{ '.{ { d+n.n.$ 9+$ 9+9+$ $ 9+9+$ d+$ $ $ 9+<+9+9+, , , , , , , , , , l.l.l.[+l.l.l.l.l.l.l.[+l.l.:.a+8 p+9 ",
"9 j.O - % N.D.A A ; A 0.A A A ! ; ^+A A A ; ; ! D.D.m m 2.e.4+4+! { { g.s g.g.g.,+^+4+4+! e.4+'.'.'.'.'.{ _ _ _ m._ ! _ { d+{ g+g+d+l+g+t t g+_ _ '._ _ '.'.'.d+t t g+$ $ t g+t t t t w w w $ $ $ $ s >.>.>.:.$ $ >.>.>.>.:.>., , >.>.>.>.s ~., , :.a+@+w.9 9 ",
"9 9 j O - % i+N.' }.' }.' ' D.B.D.D.D.D.D.e.e.E.N.N N N E.B.2.B.B.B.I.! ^+^+^+^+I.B.' -.' !.!./ | 3 3 3 | m+X X m+X ( m+I.| / _ _ h.h.3 3 3 _ | X X X / I.| | | 3 3 h.h.h.h.3 h.3 3 3 | | h.w w w w w w h.h.3 h._ _ h.h.h.h.h.w t w w w w t l+l+a+4.k+s+9 9 9 ",
"9 9 9 j O 8.q % 5 ) ) ) ) c l 7.c l : ) : F+F.F.F.F.F.) F.F.7.c c ) ~ ~ ~ ~ ~ i ++c 7.7.7.7.> ~ ~ Y.~ G J e+e+e+e+e+f+e+~ ~ Y.0 0 H H Y.Y.Y.Y.Y.G G i G Y.Y.Y.Y.Y.H H H K.H H .+Y.H H G H .+.+.+.+} .+t+K.H Y.G H H 0 .+H .+.+3.3.t+t+.+.+3.3.3.6.-+j.9 9 9 9 ",
"9 9 9 j.j k.r 8.d - q q q q q q I /+I I I d d d /+/+d d I I d.d.v.d.d.d.I I I I I I v.'+'+^.^.v.v.v.d.d.d.v.'+v.v.5+5+^.^.5+^.=+=+Q 5+^.Q ^.^.^.5+=+=+Q 4 4 4 4 4 4 4 Q 4 Q Q {+Q Q 4 Z.Z.)+4 4 4 4 4 4 Q Q 4 4 4 4 Z.4 4 Z.Z.Z.)+)+Z.-+p+9 9 9 9 9 9 "};
#endif // BTNARMORY_H_INCLUDED
| [
"siof@siof.pl"
] | siof@siof.pl |
5f65c149b19a80fc7dcdf73508c388b6ba09347c | fb708a7e0a3e76dfa42c63db2ead698bb78298f8 | /srcs/read.c | 3d21e8c8b71720ca44166daaeae1350fde8b68e6 | [] | no_license | gabrieleficara/lem-in | 0cd4a1fdff0bd632b922bee90be2f2ee6034d309 | 6a72aa74a208f784077fb93b069998cf8c811325 | refs/heads/master | 2020-03-22T10:04:38.266261 | 2018-07-05T17:13:08 | 2018-07-05T17:13:08 | 125,050,284 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,620 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* read.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: syboeuf <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2018/04/04 12:32:38 by syboeuf #+# #+# */
/* Updated: 2018/04/04 13:04:22 by syboeuf ### ########.fr */
/* */
/* ************************************************************************** */
#include "../includes/lemin.h"
void read_array(t_infos *infos, char *file)
{
char **array;
int i;
i = -1;
array = ft_strsplit(file, '\n');
while (array[++i])
{
if (ft_strstr(array[i], "##start"))
start_and_end(infos, array, &infos->new, &i);
if (ft_strchr(array[i], ' ') && !ft_strchr(array[i], '#'))
{
infos->new = ft_sfstrjoin(infos->new, array[i], 1);
infos->new = ft_sfstrjoin(infos->new, "\n", 1);
infos->count++;
}
if (ft_strstr(array[i], "##end"))
start_and_end(infos, array, &infos->new, &i);
if (ft_strchr(array[i], '-'))
{
infos->count_link++;
infos->tmp = ft_sfstrjoin(infos->tmp, array[i], 1);
infos->tmp = ft_sfstrjoin(infos->tmp, "\n", 1);
}
}
freedoom(array);
}
| [
"gficara@e1r4p10.42.fr"
] | gficara@e1r4p10.42.fr |
940c7c38f1a8ed5950786b52ae39a27919fc07e4 | 230764d82733fac64c3e0eae1ce0a4030965dc4a | /third_party/gst-plugins-bad/ext/sctp/gstsctpdec.h | 845fac4d41e1a7d5e07f95d71731f5ea009ba3bd | [
"BSD-3-Clause",
"LGPL-2.1-only",
"LGPL-2.0-or-later",
"LicenseRef-scancode-other-copyleft",
"LicenseRef-scancode-warranty-disclaimer",
"GPL-1.0-or-later",
"GPL-2.0-only",
"LGPL-2.0-only",
"Apache-2.0",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | isabella232/aistreams | 478f6ae94189aecdfd9a9cc19742bcb4b4e20bcc | 209f4385425405676a581a749bb915e257dbc1c1 | refs/heads/master | 2023-03-06T14:49:27.864415 | 2020-09-25T19:48:04 | 2020-09-25T19:48:04 | 298,772,653 | 0 | 0 | Apache-2.0 | 2021-02-23T10:11:29 | 2020-09-26T08:40:34 | null | UTF-8 | C | false | false | 2,392 | h | /*
* Copyright (c) 2015, Collabora Ltd.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
#ifndef __GST_SCTP_DEC_H__
#define __GST_SCTP_DEC_H__
#include <gst/gst.h>
#include "sctpassociation.h"
G_BEGIN_DECLS
#define GST_TYPE_SCTP_DEC (gst_sctp_dec_get_type())
#define GST_SCTP_DEC(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), GST_TYPE_SCTP_DEC, GstSctpDec))
#define GST_SCTP_DEC_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), GST_TYPE_SCTP_DEC, GstSctpDecClass))
#define GST_IS_SCTP_DEC(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), GST_TYPE_SCTP_DEC))
#define GST_IS_SCTP_DEC_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), GST_TYPE_SCTP_DEC))
typedef struct _GstSctpDec GstSctpDec;
typedef struct _GstSctpDecClass GstSctpDecClass;
struct _GstSctpDec
{
GstElement element;
GstPad *sink_pad;
guint sctp_association_id;
guint local_sctp_port;
GstSctpAssociation *sctp_association;
gulong signal_handler_stream_reset;
};
struct _GstSctpDecClass
{
GstElementClass parent_class;
void (*on_reset_stream) (GstSctpDec * sctp_dec, guint stream_id);
};
GType gst_sctp_dec_get_type (void);
G_END_DECLS
#endif /* __GST_SCTP_DEC_H__ */
| [
"dschao@google.com"
] | dschao@google.com |
0e08567c071db0a42327543cf2ea83407599e8df | 0641d87fac176bab11c613e64050330246569e5c | /tags/release-2-4-d01/source/common/ucnv_io.c | 0240df6ec46d74d2644d52b58e50c093394dffc8 | [
"ICU"
] | permissive | svn2github/libicu_full | ecf883cedfe024efa5aeda4c8527f227a9dbf100 | f1246dcb7fec5a23ebd6d36ff3515ff0395aeb29 | refs/heads/master | 2021-01-01T17:00:58.555108 | 2015-01-27T16:59:40 | 2015-01-27T16:59:40 | 9,308,333 | 0 | 2 | null | null | null | null | UTF-8 | C | false | false | 35,354 | c | /*
******************************************************************************
*
* Copyright (C) 1999-2001, International Business Machines
* Corporation and others. All Rights Reserved.
*
******************************************************************************
*
*
* ucnv_io.c:
* initializes global variables and defines functions pertaining to file
* access, and name resolution aspect of the library.
*
* new implementation:
*
* created on: 1999nov22
* created by: Markus W. Scherer
*
* Use the binary cnvalias.icu (created from convrtrs.txt) to work
* with aliases for converter names.
*
* Date Name Description
* 11/22/1999 markus Created
* 06/28/2002 grhoten Major overhaul of the converter alias design.
* Now an alias can map to different converters
* depending on the specified standard.
*******************************************************************************
*/
#include "unicode/utypes.h"
#include "unicode/putil.h"
#include "unicode/ucnv.h" /* This file implements ucnv_xXXX() APIs */
#include "unicode/udata.h"
#include "umutex.h"
#include "cstring.h"
#include "cmemory.h"
#include "ucnv_io.h"
#include "uenumimp.h"
#include "ucln_cmn.h"
/* Format of cnvalias.icu -----------------------------------------------------
*
* cnvalias.icu is a binary, memory-mappable form of convrtrs.txt.
* This binary form contains several tables. All indexes are to uint16_t
* units, and not to the bytes (uint8_t units). Addressing everything on
* 16-bit boundaries allows us to store more information with small index
* numbers, which are also 16-bit in size. The majority of the table (except
* the string table) are 16-bit numbers.
*
* First there is the size of the Table of Contents (TOC). The TOC
* entries contain the size of each section. In order to find the offset
* you just need to sum up the previous offsets.
*
* 1) This section contains a list of converters. This list contains indexes
* into the string table for the converter name. The index of this list is
* also used by other sections, which are mentioned later on.
*
* 2) This section contains a list of tags. This list contains indexes
* into the string table for the tag name. The index of this list is
* also used by other sections, which are mentioned later on.
*
* 3) This section contains a list of sorted unique aliases. This
* list contains indexes into the string table for the alias name. The
* index of this list is also used by other sections, like the 4th section.
* The index for the 3rd and 4th section is used to get the
* alias -> converter name mapping. Section 3 and 4 form a two column table.
*
* 4) This section contains a list of mapped converter names. Consider this
* as a table that maps the 3rd section to the 1st section. This list contains
* indexes into the 1st section. The index of this list is the same index in
* the 3rd section. There is also some extra information in the high bits of
* each converter index in this table. Currently it's only used to say that
* an alias mapped to this converter is ambiguous. See UCNV_CONVERTER_INDEX_MASK
* and UCNV_AMBIGUOUS_ALIAS_MAP_BIT for more information. This section is
* the predigested form of the 5th section so that an alias lookup can be fast.
*
* 5) This section contains a 2D array with indexes to the 6th section. This
* section is the full form of all alias mappings. The column index is the
* index into the converter list (column header). The row index is the index
* to tag list (row header). This 2D array is the top part a 3D array. The
* third dimension is in the 6th section.
*
* 6) This is blob of variable length arrays. Each array starts with a size,
* and is followed by indexes to alias names in the string table. This is
* the third dimension to the section 5. No other section should be referencing
* this section.
*
* 7) Reserved at this time (There is no information). This _usually_ has a
* size of 0. Future versions may add more information here.
*
* 8) This is the string table. All strings are indexed on an even address.
* There are two reasons for this. First many chip architectures locate strings
* faster on even address boundaries. Second, since all indexes are 16-bit
* numbers, this string table can be 128KB in size instead of 64KB when we
* only have strings starting on an even address.
*
*
* Here is the concept of section 5 and 6. It's a 3D cube. Each tag
* has a unique alias among all converters. That same alias can
* be mentioned in other standards on different converters,
* but only one alias per tag can be unique.
*
*
* Converter Names (Usually in TR22 form)
* -------------------------------------------.
* T / /|
* a / / |
* g / / |
* s / / |
* / / |
* ------------------------------------------/ |
* A | | |
* l | | |
* i | | /
* a | | /
* s | | /
* e | | /
* s | |/
* -------------------------------------------
*
*
*
* Here is what it really looks like. It's like swiss cheese.
* There are holes. Some converters aren't recognized by
* a standard, or they are really old converters that the
* standard doesn't recognize anymore.
*
* Converter Names (Usually in TR22 form)
* -------------------------------------------.
* T /##########################################/|
* a / # # /#
* g / # ## ## ### # ### ### ### #/
* s / # ##### #### ## ## #/#
* / ### # # ## # # # ### # # #/##
* ------------------------------------------/# #
* A |### # # ## # # # ### # # #|# #
* l |# # # # # ## # #|# #
* i |# # # # # # #|#
* a |# #|#
* s | #|#
* e
* s
*
*/
/**
* Used by the UEnumeration API
*/
typedef struct UAliasContext {
uint32_t listOffset;
uint32_t listIdx;
} UAliasContext;
static const char DATA_NAME[] = "cnvalias";
static const char DATA_TYPE[] = "icu";
static UDataMemory *gAliasData=NULL;
static const uint16_t *gConverterList = NULL;
static const uint16_t *gTagList = NULL;
static const uint16_t *gAliasList = NULL;
static const uint16_t *gUntaggedConvArray = NULL;
static const uint16_t *gTaggedAliasArray = NULL;
static const uint16_t *gTaggedAliasLists = NULL;
static const uint16_t *gStringTable = NULL;
static uint32_t gConverterListSize;
static uint32_t gTagListSize;
static uint32_t gAliasListSize;
static uint32_t gUntaggedConvArraySize;
static uint32_t gTaggedAliasArraySize;
static uint32_t gTaggedAliasListsSize;
static uint32_t gStringTableSize;
static const char **gAvailableConverters = NULL;
static uint16_t gAvailableConverterCount = 0;
static char gDefaultConverterNameBuffer[UCNV_MAX_CONVERTER_NAME_LENGTH + 1]; /* +1 for NULL */
static const char *gDefaultConverterName = NULL;
#define GET_STRING(idx) (const char *)(gStringTable + (idx))
static UBool U_CALLCONV
isAcceptable(void *context,
const char *type, const char *name,
const UDataInfo *pInfo) {
return (UBool)(
pInfo->size>=20 &&
pInfo->isBigEndian==U_IS_BIG_ENDIAN &&
pInfo->charsetFamily==U_CHARSET_FAMILY &&
pInfo->dataFormat[0]==0x43 && /* dataFormat="CvAl" */
pInfo->dataFormat[1]==0x76 &&
pInfo->dataFormat[2]==0x41 &&
pInfo->dataFormat[3]==0x6c &&
pInfo->formatVersion[0]==3);
}
static UBool
haveAliasData(UErrorCode *pErrorCode) {
if(pErrorCode==NULL || U_FAILURE(*pErrorCode)) {
return FALSE;
}
/* load converter alias data from file if necessary */
if(gAliasData==NULL) {
UDataMemory *data = NULL;
const uint16_t *table = NULL;
uint32_t tableStart;
uint32_t currOffset;
uint32_t reservedSize1;
data = udata_openChoice(NULL, DATA_TYPE, DATA_NAME, isAcceptable, NULL, pErrorCode);
if(U_FAILURE(*pErrorCode)) {
return FALSE;
}
table = (const uint16_t *)udata_getMemory(data);
tableStart = ((const uint32_t *)(table))[0];
if (tableStart < 8) {
*pErrorCode = U_INVALID_FORMAT_ERROR;
udata_close(data);
return FALSE;
}
umtx_lock(NULL);
if(gAliasData==NULL) {
gAliasData = data;
data=NULL;
gConverterListSize = ((const uint32_t *)(table))[1];
gTagListSize = ((const uint32_t *)(table))[2];
gAliasListSize = ((const uint32_t *)(table))[3];
gUntaggedConvArraySize = ((const uint32_t *)(table))[4];
gTaggedAliasArraySize = ((const uint32_t *)(table))[5];
gTaggedAliasListsSize = ((const uint32_t *)(table))[6];
reservedSize1 = ((const uint32_t *)(table))[7]; /* reserved */
gStringTableSize = ((const uint32_t *)(table))[8];
currOffset = tableStart * (sizeof(uint32_t)/sizeof(uint16_t)) + (sizeof(uint32_t)/sizeof(uint16_t));
gConverterList = table + currOffset;
currOffset += gConverterListSize;
gTagList = table + currOffset;
currOffset += gTagListSize;
gAliasList = table + currOffset;
currOffset += gAliasListSize;
gUntaggedConvArray = table + currOffset;
currOffset += gUntaggedConvArraySize;
gTaggedAliasArray = table + currOffset;
/* aliasLists is a 1's based array, but it has a padding character */
currOffset += gTaggedAliasArraySize;
gTaggedAliasLists = table + currOffset;
currOffset += gTaggedAliasListsSize;
/* reserved */
currOffset += reservedSize1;
gStringTable = table + currOffset;
}
umtx_unlock(NULL);
/* if a different thread set it first, then close the extra data */
if(data!=NULL) {
udata_close(data); /* NULL if it was set correctly */
}
}
return TRUE;
}
static U_INLINE UBool
isAlias(const char *alias, UErrorCode *pErrorCode) {
if(alias==NULL) {
*pErrorCode=U_ILLEGAL_ARGUMENT_ERROR;
return FALSE;
} else if(*alias==0) {
return FALSE;
} else {
return TRUE;
}
}
UBool
ucnv_io_cleanup()
{
if (gAliasData) {
udata_close(gAliasData);
gAliasData = NULL;
}
ucnv_io_flushAvailableConverterCache();
gConverterListSize = 0;
gTagListSize = 0;
gAliasListSize = 0;
gUntaggedConvArraySize = 0;
gTaggedAliasArraySize = 0;
gTaggedAliasListsSize = 0;
gStringTableSize = 0;
gConverterList = NULL;
gTagList = NULL;
gAliasList = NULL;
gUntaggedConvArray = NULL;
gTaggedAliasArray = NULL;
gTaggedAliasLists = NULL;
gStringTable = NULL;
gDefaultConverterName = NULL;
gDefaultConverterNameBuffer[0] = 0;
return TRUE; /* Everything was cleaned up */
}
static uint32_t getTagNumber(const char *tagname) {
if (gTagList) {
uint32_t tagNum;
for (tagNum = 0; tagNum < gTagListSize; tagNum++) {
if (!uprv_stricmp(GET_STRING(gTagList[tagNum]), tagname)) {
return tagNum;
}
}
}
return UINT32_MAX;
}
/* @see ucnv_compareNames */
U_CFUNC char * U_EXPORT2
ucnv_io_stripForCompare(char *dst, const char *name) {
char c1 = *name;
char *dstItr = dst;
while (c1) {
/* Ignore delimiters '-', '_', and ' ' */
while ((c1 = *name) == '-' || c1 == '_' || c1 == ' ') {
++name;
}
/* lowercase for case-insensitive comparison */
*(dstItr++) = uprv_tolower(c1);
++name;
}
return dst;
}
/**
* Do a fuzzy compare of a two converter/alias names. The comparison
* is case-insensitive. It also ignores the characters '-', '_', and
* ' ' (dash, underscore, and space). Thus the strings "UTF-8",
* "utf_8", and "Utf 8" are exactly equivalent.
*
* This is a symmetrical (commutative) operation; order of arguments
* is insignificant. This is an important property for sorting the
* list (when the list is preprocessed into binary form) and for
* performing binary searches on it at run time.
*
* @param name1 a converter name or alias, zero-terminated
* @param name2 a converter name or alias, zero-terminated
* @return 0 if the names match, or a negative value if the name1
* lexically precedes name2, or a positive value if the name1
* lexically follows name2.
*
* @see ucnv_io_stripForCompare
*/
U_CAPI int U_EXPORT2
ucnv_compareNames(const char *name1, const char *name2) {
int rc;
char c1, c2;
for (;;) {
/* Ignore delimiters '-', '_', and ' ' */
while ((c1 = *name1) == '-' || c1 == '_' || c1 == ' ') {
++name1;
}
while ((c2 = *name2) == '-' || c2 == '_' || c2 == ' ') {
++name2;
}
/* If we reach the ends of both strings then they match */
if ((c1|c2)==0) {
return 0;
}
/* Case-insensitive comparison */
rc = (int)(unsigned char)uprv_tolower(c1) -
(int)(unsigned char)uprv_tolower(c2);
if (rc != 0) {
return rc;
}
++name1;
++name2;
}
}
/*
* search for an alias
* return the converter number index for gConverterList
*/
static U_INLINE uint32_t
findConverter(const char *alias, UErrorCode *pErrorCode) {
uint32_t mid, start, limit;
uint32_t lastMid;
int result;
/* do a binary search for the alias */
start = 0;
limit = gUntaggedConvArraySize;
mid = limit;
lastMid = UINT32_MAX;
for (;;) {
mid = (uint32_t)((start + limit) / 2);
if (lastMid == mid) { /* Have we moved? */
break; /* We haven't moved, and it wasn't found. */
}
lastMid = mid;
result = ucnv_compareNames(alias, GET_STRING(gAliasList[mid]));
if (result < 0) {
limit = mid;
} else if (result > 0) {
start = mid;
} else {
/* Since the gencnval tool folds duplicates into one entry,
* this alias in gAliasList is unique, but different standards
* may map an alias to different converters.
*/
if (gUntaggedConvArray[mid] & UCNV_AMBIGUOUS_ALIAS_MAP_BIT) {
*pErrorCode = U_AMBIGUOUS_ALIAS_WARNING;
}
return gUntaggedConvArray[mid] & UCNV_CONVERTER_INDEX_MASK;
}
}
return UINT32_MAX;
}
/*
* Is this alias in this list?
* alias and listOffset should be non-NULL.
*/
static U_INLINE UBool
isAliasInList(const char *alias, uint32_t listOffset) {
if (listOffset) {
uint32_t currAlias;
uint32_t listCount = gTaggedAliasLists[listOffset];
/* +1 to skip listCount */
const uint16_t *currList = gTaggedAliasLists + listOffset + 1;
for (currAlias = 0; currAlias < listCount; currAlias++) {
if (currList[currAlias]
&& ucnv_compareNames(alias, GET_STRING(currList[currAlias]))==0)
{
return TRUE;
}
}
}
return FALSE;
}
/*
* Search for an standard name of an alias (what is the default name
* that this standard uses?)
* return the listOffset for gTaggedAliasLists. If it's 0,
* the it couldn't be found, but the parameters are valid.
*/
static uint32_t
findTaggedAliasListsOffset(const char *alias, const char *standard, UErrorCode *pErrorCode) {
uint32_t idx;
uint32_t listOffset;
uint32_t convNum;
UErrorCode myErr = U_ZERO_ERROR;
uint32_t tagNum = getTagNumber(standard);
/* Make a quick guess. Hopefully they used a TR22 canonical alias. */
convNum = findConverter(alias, &myErr);
if (myErr != U_ZERO_ERROR) {
*pErrorCode = myErr;
}
if (tagNum < (gTagListSize - UCNV_NUM_HIDDEN_TAGS) && convNum < gConverterListSize) {
listOffset = gTaggedAliasArray[tagNum*gConverterListSize + convNum];
if (listOffset && gTaggedAliasLists[listOffset + 1]) {
return listOffset;
}
if (myErr == U_AMBIGUOUS_ALIAS_WARNING) {
/* Uh Oh! They used an ambiguous alias.
We have to search the whole swiss cheese starting
at the highest standard affinity.
This may take a while.
*/
for (idx = 0; idx < gTaggedAliasArraySize; idx++) {
listOffset = gTaggedAliasArray[idx];
if (listOffset && isAliasInList(alias, listOffset)) {
uint32_t currTagNum = idx/gConverterListSize;
uint32_t currConvNum = (idx - currTagNum*gConverterListSize);
uint32_t tempListOffset = gTaggedAliasArray[tagNum*gConverterListSize + currConvNum];
if (tempListOffset && gTaggedAliasLists[tempListOffset + 1]) {
return tempListOffset;
}
/* else keep on looking */
/* We could speed this up by starting on the next row
because an alias is unique per row, right now.
This would change if alias versioning appears. */
}
}
/* The standard doesn't know about the alias */
}
/* else no default name */
return 0;
}
/* else converter or tag not found */
return UINT32_MAX;
}
/* Return the canonical name */
static uint32_t
findTaggedConverterNum(const char *alias, const char *standard, UErrorCode *pErrorCode) {
uint32_t idx;
uint32_t listOffset;
uint32_t convNum;
UErrorCode myErr = U_ZERO_ERROR;
uint32_t tagNum = getTagNumber(standard);
/* Make a quick guess. Hopefully they used a TR22 canonical alias. */
convNum = findConverter(alias, &myErr);
if (myErr != U_ZERO_ERROR) {
*pErrorCode = myErr;
}
if (tagNum < (gTagListSize - UCNV_NUM_HIDDEN_TAGS) && convNum < gConverterListSize) {
listOffset = gTaggedAliasArray[tagNum*gConverterListSize + convNum];
if (listOffset && isAliasInList(alias, listOffset)) {
return convNum;
}
if (myErr == U_AMBIGUOUS_ALIAS_WARNING) {
/* Uh Oh! They used an ambiguous alias.
We have to search one slice of the swiss cheese.
We search only in the requested tag, not the whole thing.
This may take a while.
*/
uint32_t convStart = (tagNum)*gConverterListSize;
uint32_t convLimit = (tagNum+1)*gConverterListSize;
for (idx = convStart; idx < convLimit; idx++) {
listOffset = gTaggedAliasArray[idx];
if (listOffset && isAliasInList(alias, listOffset)) {
return idx-convStart;
}
}
/* The standard doesn't know about the alias */
}
/* else no canonical name */
}
/* else converter or tag not found */
return UINT32_MAX;
}
U_CFUNC const char *
ucnv_io_getConverterName(const char *alias, UErrorCode *pErrorCode) {
if(haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t convNum = findConverter(alias, pErrorCode);
if (convNum < gConverterListSize) {
return GET_STRING(gConverterList[convNum]);
}
/* else converter not found */
}
return NULL;
}
static int32_t U_CALLCONV
ucnv_io_countStandardAliases(UEnumeration *enumerator, UErrorCode *pErrorCode) {
int32_t value = 0;
UAliasContext *myContext = (UAliasContext *)(enumerator->context);
uint32_t listOffset = myContext->listOffset;
if (listOffset) {
value = gTaggedAliasLists[listOffset];
}
return value;
}
static const char* U_CALLCONV
ucnv_io_nextStandardAliases(UEnumeration *enumerator,
int32_t* resultLength,
UErrorCode *pErrorCode)
{
UAliasContext *myContext = (UAliasContext *)(enumerator->context);
uint32_t listOffset = myContext->listOffset;
if (listOffset) {
uint32_t listCount = gTaggedAliasLists[listOffset];
const uint16_t *currList = gTaggedAliasLists + listOffset + 1;
if (myContext->listIdx < listCount) {
const char *myStr = GET_STRING(currList[myContext->listIdx++]);
if (resultLength) {
*resultLength = uprv_strlen(myStr);
}
return myStr;
}
}
/* Either we accessed a zero length list, or we enumerated too far. */
*pErrorCode = U_INDEX_OUTOFBOUNDS_ERROR;
return NULL;
}
static void U_CALLCONV
ucnv_io_resetStandardAliases(UEnumeration *enumerator, UErrorCode *pErrorCode) {
((UAliasContext *)(enumerator->context))->listIdx = 0;
}
static void U_CALLCONV
ucnv_io_closeUEnumeration(UEnumeration *enumerator) {
uprv_free(enumerator->context);
uprv_free(enumerator);
}
/* Enumerate the aliases for the specified converter and standard tag */
static const UEnumeration gEnumAliases = {
NULL,
NULL,
ucnv_io_closeUEnumeration,
ucnv_io_countStandardAliases,
uenum_unextDefault,
ucnv_io_nextStandardAliases,
ucnv_io_resetStandardAliases
};
U_CAPI UEnumeration *
ucnv_openStandardNames(const char *convName,
const char *standard,
UErrorCode *pErrorCode)
{
UEnumeration *myEnum = NULL;
if (haveAliasData(pErrorCode) && isAlias(convName, pErrorCode)) {
uint32_t listOffset = findTaggedAliasListsOffset(convName, standard, pErrorCode);
/* When listOffset == 0, we want to acknowledge that the
converter name and standard are okay, but there
is nothing to enumerate. */
if (listOffset < gTaggedAliasListsSize) {
UAliasContext *myContext;
myEnum = uprv_malloc(sizeof(UEnumeration));
if (myEnum == NULL) {
*pErrorCode = U_MEMORY_ALLOCATION_ERROR;
return NULL;
}
uprv_memcpy(myEnum, &gEnumAliases, sizeof(UEnumeration));
myContext = uprv_malloc(sizeof(UAliasContext));
if (myContext == NULL) {
*pErrorCode = U_MEMORY_ALLOCATION_ERROR;
uprv_free(myEnum);
return NULL;
}
myContext->listOffset = listOffset;
myContext->listIdx = 0;
myEnum->context = myContext;
}
/* else converter or tag not found */
}
return myEnum;
}
U_CFUNC uint16_t
ucnv_io_countAliases(const char *alias, UErrorCode *pErrorCode) {
if(haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t convNum = findConverter(alias, pErrorCode);
if (convNum < gConverterListSize) {
/* tagListNum - 1 is the ALL tag */
int32_t listOffset = gTaggedAliasArray[(gTagListSize - 1)*gConverterListSize + convNum];
if (listOffset) {
return gTaggedAliasLists[listOffset];
}
/* else this shouldn't happen. internal program error */
}
/* else converter not found */
}
return 0;
}
U_CFUNC uint16_t
ucnv_io_getAliases(const char *alias, uint16_t start, const char **aliases, UErrorCode *pErrorCode) {
if(haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t currAlias;
uint32_t convNum = findConverter(alias, pErrorCode);
if (convNum < gConverterListSize) {
/* tagListNum - 1 is the ALL tag */
int32_t listOffset = gTaggedAliasArray[(gTagListSize - 1)*gConverterListSize + convNum];
if (listOffset) {
uint32_t listCount = gTaggedAliasLists[listOffset];
/* +1 to skip listCount */
const uint16_t *currList = gTaggedAliasLists + listOffset + 1;
for (currAlias = start; currAlias < listCount; currAlias++) {
aliases[currAlias] = GET_STRING(currList[currAlias]);
}
}
/* else this shouldn't happen. internal program error */
}
/* else converter not found */
}
return 0;
}
U_CFUNC const char *
ucnv_io_getAlias(const char *alias, uint16_t n, UErrorCode *pErrorCode) {
if(haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t convNum = findConverter(alias, pErrorCode);
if (convNum < gConverterListSize) {
/* tagListNum - 1 is the ALL tag */
int32_t listOffset = gTaggedAliasArray[(gTagListSize - 1)*gConverterListSize + convNum];
if (listOffset) {
uint32_t listCount = gTaggedAliasLists[listOffset];
/* +1 to skip listCount */
const uint16_t *currList = gTaggedAliasLists + listOffset + 1;
if (n < listCount) {
return GET_STRING(currList[n]);
}
*pErrorCode = U_INDEX_OUTOFBOUNDS_ERROR;
}
/* else this shouldn't happen. internal program error */
}
/* else converter not found */
}
return NULL;
}
U_CFUNC uint16_t
ucnv_io_countStandards(UErrorCode *pErrorCode) {
if (haveAliasData(pErrorCode)) {
/* Don't include the empty list */
return (uint16_t)(gTagListSize - UCNV_NUM_HIDDEN_TAGS);
}
return 0;
}
U_CAPI const char * U_EXPORT2
ucnv_getStandard(uint16_t n, UErrorCode *pErrorCode) {
if (haveAliasData(pErrorCode)) {
if (n < gTagListSize - UCNV_NUM_HIDDEN_TAGS) {
return GET_STRING(gTagList[n]);
}
*pErrorCode = U_INDEX_OUTOFBOUNDS_ERROR;
}
return NULL;
}
U_CAPI const char * U_EXPORT2
ucnv_getStandardName(const char *alias, const char *standard, UErrorCode *pErrorCode) {
if (haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t listOffset = findTaggedAliasListsOffset(alias, standard, pErrorCode);
if (0 < listOffset && listOffset < gTaggedAliasListsSize) {
const uint16_t *currList = gTaggedAliasLists + listOffset + 1;
/* Get the preferred name from this list */
if (currList[0]) {
return GET_STRING(currList[0]);
}
/* else someone screwed up the alias table. */
/* *pErrorCode = U_INVALID_FORMAT_ERROR */
}
}
return NULL;
}
U_CAPI const char * U_EXPORT2
ucnv_getCanonicalName(const char *alias, const char *standard, UErrorCode *pErrorCode) {
if (haveAliasData(pErrorCode) && isAlias(alias, pErrorCode)) {
uint32_t convNum = findTaggedConverterNum(alias, standard, pErrorCode);
if (convNum < gConverterListSize) {
return GET_STRING(gConverterList[convNum]);
}
}
return NULL;
}
void
ucnv_io_flushAvailableConverterCache() {
if (gAvailableConverters) {
umtx_lock(NULL);
gAvailableConverterCount = 0;
uprv_free((char **)gAvailableConverters);
gAvailableConverters = NULL;
umtx_unlock(NULL);
}
}
static UBool haveAvailableConverterList(UErrorCode *pErrorCode) {
if (gAvailableConverters == NULL) {
uint16_t idx;
uint16_t localConverterCount;
UErrorCode status;
const char *converterName;
const char **localConverterList;
if (!haveAliasData(pErrorCode)) {
return FALSE;
}
/* We can't have more than "*converterTable" converters to open */
localConverterList = (const char **) uprv_malloc(gConverterListSize * sizeof(char*));
if (!localConverterList) {
*pErrorCode = U_MEMORY_ALLOCATION_ERROR;
return FALSE;
}
localConverterCount = 0;
for (idx = 0; idx < gConverterListSize; idx++) {
status = U_ZERO_ERROR;
converterName = GET_STRING(gConverterList[idx]);
ucnv_close(ucnv_open(converterName, &status));
if (U_SUCCESS(status)) {
localConverterList[localConverterCount++] = converterName;
}
}
umtx_lock(NULL);
if (gAvailableConverters == NULL) {
gAvailableConverters = localConverterList;
gAvailableConverterCount = localConverterCount;
}
else {
uprv_free((char **)localConverterList);
}
umtx_unlock(NULL);
}
return TRUE;
}
U_CFUNC uint16_t
ucnv_io_countAvailableConverters(UErrorCode *pErrorCode) {
if (haveAvailableConverterList(pErrorCode)) {
return gAvailableConverterCount;
}
return 0;
}
U_CFUNC const char *
ucnv_io_getAvailableConverter(uint16_t n, UErrorCode *pErrorCode) {
if (haveAvailableConverterList(pErrorCode)) {
if (n < gAvailableConverterCount) {
return gAvailableConverters[n];
}
*pErrorCode = U_INDEX_OUTOFBOUNDS_ERROR;
}
return NULL;
}
static int32_t U_CALLCONV
ucnv_io_countAllConverters(UEnumeration *enumerator, UErrorCode *pErrorCode) {
return gConverterListSize;
}
static const char* U_CALLCONV
ucnv_io_nextAllConverters(UEnumeration *enumerator,
int32_t* resultLength,
UErrorCode *pErrorCode)
{
uint16_t *myContext = (uint16_t *)(enumerator->context);
if (*myContext < gConverterListSize) {
const char *myStr = GET_STRING(gConverterList[(*myContext)++]);
if (resultLength) {
*resultLength = uprv_strlen(myStr);
}
return myStr;
}
/* Either we accessed a zero length list, or we enumerated too far. */
*pErrorCode = U_INDEX_OUTOFBOUNDS_ERROR;
return NULL;
}
static void U_CALLCONV
ucnv_io_resetAllConverters(UEnumeration *enumerator, UErrorCode *pErrorCode) {
*((uint16_t *)(enumerator->context)) = 0;
}
static const UEnumeration gEnumAllConverters = {
NULL,
NULL,
ucnv_io_closeUEnumeration,
ucnv_io_countAllConverters,
uenum_unextDefault,
ucnv_io_nextAllConverters,
ucnv_io_resetAllConverters
};
U_CAPI UEnumeration * U_EXPORT2
ucnv_openAllNames(UErrorCode *pErrorCode) {
UEnumeration *myEnum = NULL;
if (haveAliasData(pErrorCode)) {
uint16_t *myContext;
myEnum = uprv_malloc(sizeof(UEnumeration));
if (myEnum == NULL) {
*pErrorCode = U_MEMORY_ALLOCATION_ERROR;
return NULL;
}
uprv_memcpy(myEnum, &gEnumAllConverters, sizeof(UEnumeration));
myContext = uprv_malloc(sizeof(uint16_t));
if (myContext == NULL) {
*pErrorCode = U_MEMORY_ALLOCATION_ERROR;
uprv_free(myEnum);
return NULL;
}
*myContext = 0;
myEnum->context = myContext;
}
return myEnum;
}
#ifdef ICU_UNICODECONVERTER_USE_DEPRECATES
U_CFUNC void
ucnv_io_fillAvailableConverters(const char **aliases, UErrorCode *pErrorCode) {
if (haveAvailableConverterList(pErrorCode)) {
uint16_t count = 0;
while (count < gAvailableConverterCount) {
*aliases++=gAvailableConverters[count++];
}
}
}
#endif
U_CFUNC uint16_t
ucnv_io_countAvailableAliases(UErrorCode *pErrorCode) {
if (haveAliasData(pErrorCode)) {
return (uint16_t)gAliasListSize;
}
return 0;
}
/* default converter name --------------------------------------------------- */
/*
* In order to be really thread-safe, the get function would have to take
* a buffer parameter and copy the current string inside a mutex block.
* This implementation only tries to be really thread-safe while
* setting the name.
* It assumes that setting a pointer is atomic.
*/
U_CFUNC const char *
ucnv_io_getDefaultConverterName() {
/* local variable to be thread-safe */
const char *name=gDefaultConverterName;
if(name==NULL) {
const char *codepage = uprv_getDefaultCodepage();
if(codepage!=NULL) {
UErrorCode errorCode=U_ZERO_ERROR;
name=ucnv_io_getConverterName(codepage, &errorCode);
if(U_FAILURE(errorCode) || name==NULL) {
name=codepage;
}
}
/* if the name is there, test it out */
if(name != NULL) {
UErrorCode errorCode = U_ZERO_ERROR;
UConverter *cnv = ucnv_open(name, &errorCode);
if(U_FAILURE(errorCode) || (cnv == NULL)) {
/* Panic time, let's use a fallback. */
#if (U_CHARSET_FAMILY == U_ASCII_FAMILY)
name = "US-ASCII";
/* there is no 'algorithmic' converter for EBCDIC */
#elif defined(OS390)
name = "ibm-1047" UCNV_SWAP_LFNL_OPTION_STRING;
#else
name = "ibm-37";
#endif
}
ucnv_close(cnv);
}
if(name != NULL) {
umtx_lock(NULL);
/* Did find a name. And it works.*/
gDefaultConverterName=name;
umtx_unlock(NULL);
}
}
return name;
}
U_CFUNC void
ucnv_io_setDefaultConverterName(const char *converterName) {
if(converterName==NULL) {
/* reset to the default codepage */
gDefaultConverterName=NULL;
} else {
UErrorCode errorCode=U_ZERO_ERROR;
const char *name=ucnv_io_getConverterName(converterName, &errorCode);
if(U_SUCCESS(errorCode) && name!=NULL) {
gDefaultConverterName=name;
} else {
/* do not set the name if the alias lookup failed and it is too long */
int32_t length=(int32_t)(uprv_strlen(converterName));
if(length<sizeof(gDefaultConverterNameBuffer)) {
/* it was not found as an alias, so copy it - accept an empty name */
UBool didLock;
if(gDefaultConverterName==gDefaultConverterNameBuffer) {
umtx_lock(NULL);
didLock=TRUE;
} else {
didLock=FALSE;
}
uprv_memcpy(gDefaultConverterNameBuffer, converterName, length);
gDefaultConverterNameBuffer[length]=0;
gDefaultConverterName=gDefaultConverterNameBuffer;
if(didLock) {
umtx_unlock(NULL);
}
}
}
}
}
/*
* Hey, Emacs, please set the following:
*
* Local Variables:
* indent-tabs-mode: nil
* End:
*
*/
| [
"(no author)@251d0590-4201-4cf1-90de-194747b24ca1"
] | (no author)@251d0590-4201-4cf1-90de-194747b24ca1 |
ba361480a60923e8bf397eeee0b7c322397e74ec | 16d043d7afc88455781d68c8be3cb12cb745ba63 | /cuda/mcuda/MCUDA/include/mcutil.h | 8cdd8bf54a6c1e68dd1c7b7ae52d1011963be455 | [] | no_license | peeyush113/backups | 6028951470cff8c85c7f2c622807fd246b16c936 | 0562e738184eaa7d96678177a6fb9fd2b972b48b | refs/heads/master | 2020-07-03T06:23:49.209996 | 2019-08-11T21:58:14 | 2019-08-11T21:58:14 | 201,818,797 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 824 | h | /*
* (c) 2008 The Board of Trustees of the University of Illinois.
*/
#ifndef MCUDA_UTILS
#define MCUDA_UTILS
#define CUT_SAFE_CALL(x) (x)
#define CUDA_SAFE_CALL(x) (x)
#define CUT_CHECK_ERROR(x)
#if defined(__cplusplus)
extern "C" {
#endif
void cutCreateTimer(unsigned int* timer);
void cutStartTimer(unsigned int timer);
void cutStopTimer(unsigned int timer);
float cutGetTimerValue(unsigned int timer);
void cutDeleteTimer(unsigned int timer);
void cudaMemcpy(void* dest, void* src, size_t size, int type);
void cudaMalloc(void** dest, size_t size);
void cudaFree(void* ptr);
void cudaMemcpyToSymbol(void* dst, void* src, size_t size, int type);
void cudaMemset(void* ptr, int i, size_t size);
void cudaThreadSynchronize();
//__inline__ int __umul24(int x, int y);
#if defined(__cplusplus)
}
#endif
#endif
| [
"peeyush113@gmail.com"
] | peeyush113@gmail.com |
0f790d0b4017aa79cabdc405681e557af2eaa88b | 71718b60860c68539175931114ec322a83a014d2 | /static/capstone/arch/AArch64/AArch64Disassembler.c | 22880efab5b9503b2eac15b13e1c9d470ce332fd | [
"BSD-3-Clause",
"NCSA",
"Apache-2.0"
] | permissive | killvxk/Janus | 466ba3c3f41a410ea5c0afd2c2810861eaeede8b | f51381227e20a0f00ad6356ecf07c8b752d8ec33 | refs/heads/master | 2020-04-23T19:02:33.162511 | 2019-02-14T21:06:04 | 2019-02-14T21:06:04 | 171,388,739 | 1 | 0 | Apache-2.0 | 2019-02-19T02:13:31 | 2019-02-19T02:13:30 | null | UTF-8 | C | false | false | 48,477 | c | //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the functions necessary to decode AArch64 instruction
// bitpatterns into MCInsts (with the help of TableGenerated information from
// the instruction definitions).
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef CAPSTONE_HAS_ARM64
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include "../../cs_priv.h"
#include "../../utils.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "AArch64BaseInfo.h"
#include "AArch64AddressingModes.h"
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
uint32_t insn, uint64_t Address,
void *Decoder);
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
uint32_t insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address,
void *Decoder);
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder);
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder);
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder);
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder);
static bool Check(DecodeStatus *Out, DecodeStatus In)
{
switch (In) {
default: // never reach
return true;
case MCDisassembler_Success:
// Out stays the same.
return true;
case MCDisassembler_SoftFail:
*Out = In;
return true;
case MCDisassembler_Fail:
*Out = In;
return false;
}
// llvm_unreachable("Invalid DecodeStatus!");
}
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int feature)
{
// enable all features
return (uint64_t)-1;
}
#define GET_SUBTARGETINFO_ENUM
#include "AArch64GenSubtargetInfo.inc"
#include "AArch64GenDisassemblerTables.inc"
#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "AArch64GenRegisterInfo.inc"
#define Success MCDisassembler_Success
#define Fail MCDisassembler_Fail
#define SoftFail MCDisassembler_SoftFail
static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
const uint8_t *code, size_t code_len,
uint16_t *Size,
uint64_t Address, MCRegisterInfo *MRI)
{
uint32_t insn;
DecodeStatus result;
size_t i;
if (code_len < 4) {
// not enough data
*Size = 0;
return MCDisassembler_Fail;
}
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
}
if (MODE_IS_BIG_ENDIAN(ud->mode))
insn = (code[3] << 0) | (code[2] << 8) |
(code[1] << 16) | ((uint32_t) code[0] << 24);
else
insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
// Calling the auto-generated decoder function.
result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0);
if (result != MCDisassembler_Fail) {
*Size = 4;
return result;
}
MCInst_clear(MI);
*Size = 0;
return MCDisassembler_Fail;
}
bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address, void *info)
{
DecodeStatus status = _getInstruction((cs_struct *)ud, instr,
code, code_len,
size,
address, (MCRegisterInfo *)info);
return status == MCDisassembler_Success;
}
static const unsigned FPR128DecoderTable[] = {
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
AArch64_Q30, AArch64_Q31
};
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = FPR128DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
if (RegNo > 15)
return Fail;
return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
}
static const unsigned FPR64DecoderTable[] = {
AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4,
AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9,
AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14,
AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19,
AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24,
AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29,
AArch64_D30, AArch64_D31
};
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = FPR64DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned FPR32DecoderTable[] = {
AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4,
AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9,
AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14,
AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19,
AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24,
AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29,
AArch64_S30, AArch64_S31
};
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = FPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned FPR16DecoderTable[] = {
AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4,
AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9,
AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14,
AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19,
AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24,
AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29,
AArch64_H30, AArch64_H31
};
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = FPR16DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned FPR8DecoderTable[] = {
AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4,
AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9,
AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14,
AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19,
AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24,
AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29,
AArch64_B30, AArch64_B31
};
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = FPR8DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned GPR64DecoderTable[] = {
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4,
AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9,
AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14,
AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19,
AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24,
AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP,
AArch64_LR, AArch64_XZR
};
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = GPR64DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = GPR64DecoderTable[RegNo];
if (Register == AArch64_XZR)
Register = AArch64_SP;
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned GPR32DecoderTable[] = {
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4,
AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9,
AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14,
AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19,
AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24,
AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29,
AArch64_W30, AArch64_WZR
};
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = GPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = GPR32DecoderTable[RegNo];
if (Register == AArch64_WZR)
Register = AArch64_WSP;
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned VectorDecoderTable[] = {
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
AArch64_Q30, AArch64_Q31
};
static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = VectorDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned QQDecoderTable[] = {
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4,
AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8,
AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12,
AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20,
AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24,
AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28,
AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0
};
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr, void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = QQDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned QQQDecoderTable[] = {
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4,
AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7,
AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10,
AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13,
AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19,
AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22,
AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25,
AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28,
AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31,
AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1
};
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr, void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = QQQDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned QQQQDecoderTable[] = {
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5,
AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8,
AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11,
AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14,
AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20,
AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23,
AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26,
AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29,
AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0,
AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2
};
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = QQQQDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned DDDecoderTable[] = {
AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4,
AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8,
AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12,
AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16,
AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20,
AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24,
AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28,
AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0
};
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr, void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = DDDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned DDDDecoderTable[] = {
AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4,
AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7,
AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10,
AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13,
AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16,
AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19,
AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22,
AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25,
AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28,
AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31,
AArch64_D30_D31_D0, AArch64_D31_D0_D1
};
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr, void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = DDDDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static const unsigned DDDDDecoderTable[] = {
AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5,
AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8,
AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11,
AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14,
AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17,
AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20,
AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23,
AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26,
AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29,
AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0,
AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2
};
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Addr,
void *Decoder)
{
unsigned Register;
if (RegNo > 31)
return Fail;
Register = DDDDDecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Register);
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder)
{
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
MCOperand_CreateImm0(Inst, 64 - Imm);
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder)
{
MCOperand_CreateImm0(Inst, 64 - Imm);
return Success;
}
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
int64_t ImmVal = Imm;
// Sign-extend 19-bit immediate.
if (ImmVal & (1 << (19 - 1)))
ImmVal |= ~((1LL << 19) - 1);
MCOperand_CreateImm0(Inst, ImmVal);
return Success;
}
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder)
{
MCOperand_CreateImm0(Inst, (Imm >> 1) & 1);
MCOperand_CreateImm0(Inst, Imm & 1);
return Success;
}
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
uint64_t Address, void *Decoder)
{
MCOperand_CreateImm0(Inst, Imm);
// Every system register in the encoding space is valid with the syntax
// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
return Success;
}
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
uint64_t Address,
void *Decoder)
{
MCOperand_CreateImm0(Inst, Imm);
return Success;
}
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address,
void *Decoder)
{
// This decoder exists to add the dummy Lane operand to the MCInst, which must
// be 1 in assembly but has no other real manifestation.
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
if (IsToVec) {
DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
} else {
DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
}
// Add the lane
MCOperand_CreateImm0(Inst, 1);
return Success;
}
static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm,
unsigned Add)
{
MCOperand_CreateImm0(Inst, Add - Imm);
return Success;
}
static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm,
unsigned Add)
{
MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1));
return Success;
}
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 64);
}
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
}
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 32);
}
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
}
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 16);
}
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
uint64_t Addr,
void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
}
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftRImm(Inst, Imm, 8);
}
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 64);
}
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 32);
}
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 16);
}
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
uint64_t Addr, void *Decoder)
{
return DecodeVecShiftLImm(Inst, Imm, 8);
}
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rm = fieldFromInstruction(insn, 16, 5);
unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
unsigned shift = (shiftHi << 6) | shiftLo;
switch (MCInst_getOpcode(Inst)) {
default:
return Fail;
case AArch64_ADDWrs:
case AArch64_ADDSWrs:
case AArch64_SUBWrs:
case AArch64_SUBSWrs:
// if shift == '11' then ReservedValue()
if (shiftHi == 0x3)
return Fail;
// Deliberate fallthrough
case AArch64_ANDWrs:
case AArch64_ANDSWrs:
case AArch64_BICWrs:
case AArch64_BICSWrs:
case AArch64_ORRWrs:
case AArch64_ORNWrs:
case AArch64_EORWrs:
case AArch64_EONWrs: {
// if sf == '0' and imm6<5> == '1' then ReservedValue()
if (shiftLo >> 5 == 1)
return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
case AArch64_ADDXrs:
case AArch64_ADDSXrs:
case AArch64_SUBXrs:
case AArch64_SUBSXrs:
// if shift == '11' then ReservedValue()
if (shiftHi == 0x3)
return Fail;
// Deliberate fallthrough
case AArch64_ANDXrs:
case AArch64_ANDSXrs:
case AArch64_BICXrs:
case AArch64_BICSXrs:
case AArch64_ORRXrs:
case AArch64_ORNXrs:
case AArch64_EORXrs:
case AArch64_EONXrs:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
MCOperand_CreateImm0(Inst, shift);
return Success;
}
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned imm = fieldFromInstruction(insn, 5, 16);
unsigned shift = fieldFromInstruction(insn, 21, 2);
shift <<= 4;
switch (MCInst_getOpcode(Inst)) {
default:
return Fail;
case AArch64_MOVZWi:
case AArch64_MOVNWi:
case AArch64_MOVKWi:
if (shift & (1U << 5))
return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
break;
case AArch64_MOVZXi:
case AArch64_MOVNXi:
case AArch64_MOVKXi:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
break;
}
if (MCInst_getOpcode(Inst) == AArch64_MOVKWi ||
MCInst_getOpcode(Inst) == AArch64_MOVKXi)
MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0));
MCOperand_CreateImm0(Inst, imm);
MCOperand_CreateImm0(Inst, shift);
return Success;
}
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned offset = fieldFromInstruction(insn, 10, 12);
switch (MCInst_getOpcode(Inst)) {
default:
return Fail;
case AArch64_PRFMui:
// Rt is an immediate in prefetch.
MCOperand_CreateImm0(Inst, Rt);
break;
case AArch64_STRBBui:
case AArch64_LDRBBui:
case AArch64_LDRSBWui:
case AArch64_STRHHui:
case AArch64_LDRHHui:
case AArch64_LDRSHWui:
case AArch64_STRWui:
case AArch64_LDRWui:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRSBXui:
case AArch64_LDRSHXui:
case AArch64_LDRSWui:
case AArch64_STRXui:
case AArch64_LDRXui:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRQui:
case AArch64_STRQui:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRDui:
case AArch64_STRDui:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRSui:
case AArch64_STRSui:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRHui:
case AArch64_STRHui:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDRBui:
case AArch64_STRBui:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break;
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
//if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
MCOperand_CreateImm0(Inst, offset);
return Success;
}
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
bool IsLoad;
bool IsIndexed;
bool IsFP;
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
int32_t offset = fieldFromInstruction(insn, 12, 9);
// offset is a 9-bit signed immediate, so sign extend it to
// fill the unsigned.
if (offset & (1 << (9 - 1)))
offset |= ~((1LL << 9) - 1);
// First operand is always the writeback to the address register, if needed.
switch (MCInst_getOpcode(Inst)) {
default:
break;
case AArch64_LDRSBWpre:
case AArch64_LDRSHWpre:
case AArch64_STRBBpre:
case AArch64_LDRBBpre:
case AArch64_STRHHpre:
case AArch64_LDRHHpre:
case AArch64_STRWpre:
case AArch64_LDRWpre:
case AArch64_LDRSBWpost:
case AArch64_LDRSHWpost:
case AArch64_STRBBpost:
case AArch64_LDRBBpost:
case AArch64_STRHHpost:
case AArch64_LDRHHpost:
case AArch64_STRWpost:
case AArch64_LDRWpost:
case AArch64_LDRSBXpre:
case AArch64_LDRSHXpre:
case AArch64_STRXpre:
case AArch64_LDRSWpre:
case AArch64_LDRXpre:
case AArch64_LDRSBXpost:
case AArch64_LDRSHXpost:
case AArch64_STRXpost:
case AArch64_LDRSWpost:
case AArch64_LDRXpost:
case AArch64_LDRQpre:
case AArch64_STRQpre:
case AArch64_LDRQpost:
case AArch64_STRQpost:
case AArch64_LDRDpre:
case AArch64_STRDpre:
case AArch64_LDRDpost:
case AArch64_STRDpost:
case AArch64_LDRSpre:
case AArch64_STRSpre:
case AArch64_LDRSpost:
case AArch64_STRSpost:
case AArch64_LDRHpre:
case AArch64_STRHpre:
case AArch64_LDRHpost:
case AArch64_STRHpost:
case AArch64_LDRBpre:
case AArch64_STRBpre:
case AArch64_LDRBpost:
case AArch64_STRBpost:
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
break;
}
switch (MCInst_getOpcode(Inst)) {
default:
return Fail;
case AArch64_PRFUMi:
// Rt is an immediate in prefetch.
MCOperand_CreateImm0(Inst, Rt);
break;
case AArch64_STURBBi:
case AArch64_LDURBBi:
case AArch64_LDURSBWi:
case AArch64_STURHHi:
case AArch64_LDURHHi:
case AArch64_LDURSHWi:
case AArch64_STURWi:
case AArch64_LDURWi:
case AArch64_LDTRSBWi:
case AArch64_LDTRSHWi:
case AArch64_STTRWi:
case AArch64_LDTRWi:
case AArch64_STTRHi:
case AArch64_LDTRHi:
case AArch64_LDTRBi:
case AArch64_STTRBi:
case AArch64_LDRSBWpre:
case AArch64_LDRSHWpre:
case AArch64_STRBBpre:
case AArch64_LDRBBpre:
case AArch64_STRHHpre:
case AArch64_LDRHHpre:
case AArch64_STRWpre:
case AArch64_LDRWpre:
case AArch64_LDRSBWpost:
case AArch64_LDRSHWpost:
case AArch64_STRBBpost:
case AArch64_LDRBBpost:
case AArch64_STRHHpost:
case AArch64_LDRHHpost:
case AArch64_STRWpost:
case AArch64_LDRWpost:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURSBXi:
case AArch64_LDURSHXi:
case AArch64_LDURSWi:
case AArch64_STURXi:
case AArch64_LDURXi:
case AArch64_LDTRSBXi:
case AArch64_LDTRSHXi:
case AArch64_LDTRSWi:
case AArch64_STTRXi:
case AArch64_LDTRXi:
case AArch64_LDRSBXpre:
case AArch64_LDRSHXpre:
case AArch64_STRXpre:
case AArch64_LDRSWpre:
case AArch64_LDRXpre:
case AArch64_LDRSBXpost:
case AArch64_LDRSHXpost:
case AArch64_STRXpost:
case AArch64_LDRSWpost:
case AArch64_LDRXpost:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURQi:
case AArch64_STURQi:
case AArch64_LDRQpre:
case AArch64_STRQpre:
case AArch64_LDRQpost:
case AArch64_STRQpost:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURDi:
case AArch64_STURDi:
case AArch64_LDRDpre:
case AArch64_STRDpre:
case AArch64_LDRDpost:
case AArch64_STRDpost:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURSi:
case AArch64_STURSi:
case AArch64_LDRSpre:
case AArch64_STRSpre:
case AArch64_LDRSpost:
case AArch64_STRSpost:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURHi:
case AArch64_STURHi:
case AArch64_LDRHpre:
case AArch64_STRHpre:
case AArch64_LDRHpost:
case AArch64_STRHpost:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_LDURBi:
case AArch64_STURBi:
case AArch64_LDRBpre:
case AArch64_STRBpre:
case AArch64_LDRBpost:
case AArch64_STRBpost:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break;
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
MCOperand_CreateImm0(Inst, offset);
IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
IsFP = fieldFromInstruction(insn, 26, 1) != 0;
// Cannot write back to a transfer register (but xzr != sp).
if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
return SoftFail;
return Success;
}
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
unsigned Rs = fieldFromInstruction(insn, 16, 5);
unsigned Opcode = MCInst_getOpcode(Inst);
switch (Opcode) {
default:
return Fail;
case AArch64_STLXRW:
case AArch64_STLXRB:
case AArch64_STLXRH:
case AArch64_STXRW:
case AArch64_STXRB:
case AArch64_STXRH:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
// FALLTHROUGH
case AArch64_LDARW:
case AArch64_LDARB:
case AArch64_LDARH:
case AArch64_LDAXRW:
case AArch64_LDAXRB:
case AArch64_LDAXRH:
case AArch64_LDXRW:
case AArch64_LDXRB:
case AArch64_LDXRH:
case AArch64_STLRW:
case AArch64_STLRB:
case AArch64_STLRH:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_STLXRX:
case AArch64_STXRX:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
// FALLTHROUGH
case AArch64_LDARX:
case AArch64_LDAXRX:
case AArch64_LDXRX:
case AArch64_STLRX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break;
case AArch64_STLXPW:
case AArch64_STXPW:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
// FALLTHROUGH
case AArch64_LDAXPW:
case AArch64_LDXPW:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break;
case AArch64_STLXPX:
case AArch64_STXPX:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
// FALLTHROUGH
case AArch64_LDAXPX:
case AArch64_LDXPX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break;
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
// You shouldn't load to the same register twice in an instruction...
if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW ||
Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) &&
Rt == Rt2)
return SoftFail;
return Success;
}
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
void *Decoder)
{
unsigned Rt = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
int32_t offset = fieldFromInstruction(insn, 15, 7);
bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
unsigned Opcode = MCInst_getOpcode(Inst);
bool NeedsDisjointWritebackTransfer = false;
// offset is a 7-bit signed immediate, so sign extend it to
// fill the unsigned.
if (offset & (1 << (7 - 1)))
offset |= ~((1LL << 7) - 1);
// First operand is always writeback of base register.
switch (Opcode) {
default:
break;
case AArch64_LDPXpost:
case AArch64_STPXpost:
case AArch64_LDPSWpost:
case AArch64_LDPXpre:
case AArch64_STPXpre:
case AArch64_LDPSWpre:
case AArch64_LDPWpost:
case AArch64_STPWpost:
case AArch64_LDPWpre:
case AArch64_STPWpre:
case AArch64_LDPQpost:
case AArch64_STPQpost:
case AArch64_LDPQpre:
case AArch64_STPQpre:
case AArch64_LDPDpost:
case AArch64_STPDpost:
case AArch64_LDPDpre:
case AArch64_STPDpre:
case AArch64_LDPSpost:
case AArch64_STPSpost:
case AArch64_LDPSpre:
case AArch64_STPSpre:
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
break;
}
switch (Opcode) {
default:
return Fail;
case AArch64_LDPXpost:
case AArch64_STPXpost:
case AArch64_LDPSWpost:
case AArch64_LDPXpre:
case AArch64_STPXpre:
case AArch64_LDPSWpre:
NeedsDisjointWritebackTransfer = true;
// Fallthrough
case AArch64_LDNPXi:
case AArch64_STNPXi:
case AArch64_LDPXi:
case AArch64_STPXi:
case AArch64_LDPSWi:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break;
case AArch64_LDPWpost:
case AArch64_STPWpost:
case AArch64_LDPWpre:
case AArch64_STPWpre:
NeedsDisjointWritebackTransfer = true;
// Fallthrough
case AArch64_LDNPWi:
case AArch64_STNPWi:
case AArch64_LDPWi:
case AArch64_STPWi:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break;
case AArch64_LDNPQi:
case AArch64_STNPQi:
case AArch64_LDPQpost:
case AArch64_STPQpost:
case AArch64_LDPQi:
case AArch64_STPQi:
case AArch64_LDPQpre:
case AArch64_STPQpre:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
break;
case AArch64_LDNPDi:
case AArch64_STNPDi:
case AArch64_LDPDpost:
case AArch64_STPDpost:
case AArch64_LDPDi:
case AArch64_STPDi:
case AArch64_LDPDpre:
case AArch64_STPDpre:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break;
case AArch64_LDNPSi:
case AArch64_STNPSi:
case AArch64_LDPSpost:
case AArch64_STPSpost:
case AArch64_LDPSi:
case AArch64_STPSi:
case AArch64_LDPSpre:
case AArch64_STPSpre:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break;
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
MCOperand_CreateImm0(Inst, offset);
// You shouldn't load to the same register twice in an instruction...
if (IsLoad && Rt == Rt2)
return SoftFail;
// ... or do any operation that writes-back to a transfer register. But note
// that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
return SoftFail;
return Success;
}
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rd, Rn, Rm;
unsigned extend = fieldFromInstruction(insn, 10, 6);
unsigned shift = extend & 0x7;
if (shift > 4)
return Fail;
Rd = fieldFromInstruction(insn, 0, 5);
Rn = fieldFromInstruction(insn, 5, 5);
Rm = fieldFromInstruction(insn, 16, 5);
switch (MCInst_getOpcode(Inst)) {
default:
return Fail;
case AArch64_ADDWrx:
case AArch64_SUBWrx:
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case AArch64_ADDSWrx:
case AArch64_SUBSWrx:
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case AArch64_ADDXrx:
case AArch64_SUBXrx:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case AArch64_ADDSXrx:
case AArch64_SUBSXrx:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break;
case AArch64_ADDXrx64:
case AArch64_SUBXrx64:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
case AArch64_SUBSXrx64:
case AArch64_ADDSXrx64:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break;
}
MCOperand_CreateImm0(Inst, extend);
return Success;
}
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Datasize = fieldFromInstruction(insn, 31, 1);
unsigned imm;
if (Datasize) {
if (MCInst_getOpcode(Inst) == AArch64_ANDSXri)
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 13);
if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
return Fail;
} else {
if (MCInst_getOpcode(Inst) == AArch64_ANDSWri)
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 12);
if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32))
return Fail;
}
MCOperand_CreateImm0(Inst, imm);
return Success;
}
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr,
void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5);
if (MCInst_getOpcode(Inst) == AArch64_MOVID)
DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
MCOperand_CreateImm0(Inst, imm);
switch (MCInst_getOpcode(Inst)) {
default:
break;
case AArch64_MOVIv4i16:
case AArch64_MOVIv8i16:
case AArch64_MVNIv4i16:
case AArch64_MVNIv8i16:
case AArch64_MOVIv2i32:
case AArch64_MOVIv4i32:
case AArch64_MVNIv2i32:
case AArch64_MVNIv4i32:
MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
break;
case AArch64_MOVIv2s_msl:
case AArch64_MOVIv4s_msl:
case AArch64_MVNIv2s_msl:
case AArch64_MVNIv4s_msl:
MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108);
break;
}
return Success;
}
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5);
// Tied operands added twice.
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
MCOperand_CreateImm0(Inst, imm);
MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
return Success;
}
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
uint64_t Addr, void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
int32_t imm = fieldFromInstruction(insn, 5, 19) << 2;
imm |= fieldFromInstruction(insn, 29, 2);
// Sign-extend the 21-bit immediate.
if (imm & (1 << (21 - 1)))
imm |= ~((1LL << 21) - 1);
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
//if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
MCOperand_CreateImm0(Inst, imm);
return Success;
}
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
uint64_t Addr, void *Decoder)
{
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Imm = fieldFromInstruction(insn, 10, 14);
unsigned S = fieldFromInstruction(insn, 29, 1);
unsigned Datasize = fieldFromInstruction(insn, 31, 1);
unsigned ShifterVal = (Imm >> 12) & 3;
unsigned ImmVal = Imm & 0xFFF;
if (ShifterVal != 0 && ShifterVal != 1)
return Fail;
if (Datasize) {
if (Rd == 31 && !S)
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
} else {
if (Rd == 31 && !S)
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
}
//if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
MCOperand_CreateImm0(Inst, ImmVal);
MCOperand_CreateImm0(Inst, 12 * ShifterVal);
return Success;
}
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
uint64_t Addr,
void *Decoder)
{
int32_t imm = fieldFromInstruction(insn, 0, 26);
// Sign-extend the 26-bit immediate.
if (imm & (1 << (26 - 1)))
imm |= ~((1LL << 26) - 1);
// if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
MCOperand_CreateImm0(Inst, imm);
return Success;
}
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
uint32_t op1 = fieldFromInstruction(insn, 16, 3);
uint32_t op2 = fieldFromInstruction(insn, 5, 3);
uint32_t crm = fieldFromInstruction(insn, 8, 4);
bool ValidNamed;
uint32_t pstate_field = (op1 << 3) | op2;
MCOperand_CreateImm0(Inst, pstate_field);
MCOperand_CreateImm0(Inst, crm);
A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed);
return ValidNamed ? Success : Fail;
}
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
uint64_t Addr, void *Decoder)
{
uint32_t Rt = fieldFromInstruction(insn, 0, 5);
uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
uint32_t dst = fieldFromInstruction(insn, 5, 14);
bit |= fieldFromInstruction(insn, 19, 5);
// Sign-extend 14-bit immediate.
if (dst & (1 << (14 - 1)))
dst |= ~((1LL << 14) - 1);
if (fieldFromInstruction(insn, 31, 1) == 0)
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
MCOperand_CreateImm0(Inst, bit);
//if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
MCOperand_CreateImm0(Inst, dst);
return Success;
}
void AArch64_init(MCRegisterInfo *MRI)
{
/*
InitMCRegisterInfo(AArch64RegDesc, 420,
RA, PC,
AArch64MCRegisterClasses, 43,
AArch64RegUnitRoots, 66, AArch64RegDiffLists,
AArch64RegStrings,
AArch64SubRegIdxLists, 53,
AArch64SubRegIdxRanges,
AArch64RegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
0, 0,
AArch64MCRegisterClasses, 43,
0, 0, AArch64RegDiffLists,
0,
AArch64SubRegIdxLists, 53,
0);
}
#endif
| [
"rkz20@cam.ac.uk"
] | rkz20@cam.ac.uk |
8bc702e071187dde4bc22221ffcf8524b87828b5 | 0641d87fac176bab11c613e64050330246569e5c | /branches/mishonok/regex-2009/source/tools/gennorm/store.c | ddd4f7fd8f9a9154ef78ab3364d9d3b81c0f5458 | [
"LicenseRef-scancode-unicode",
"ICU"
] | permissive | svn2github/libicu_full | ecf883cedfe024efa5aeda4c8527f227a9dbf100 | f1246dcb7fec5a23ebd6d36ff3515ff0395aeb29 | refs/heads/master | 2021-01-01T17:00:58.555108 | 2015-01-27T16:59:40 | 2015-01-27T16:59:40 | 9,308,333 | 0 | 2 | null | null | null | null | UTF-8 | C | false | false | 77,622 | c | /*
*******************************************************************************
*
* Copyright (C) 1999-2010, International Business Machines
* Corporation and others. All Rights Reserved.
*
*******************************************************************************
* file name: store.c
* encoding: US-ASCII
* tab size: 8 (not used)
* indentation:4
*
* created on: 2001may25
* created by: Markus W. Scherer
*
* Store Unicode normalization data in a memory-mappable file.
*/
#include <stdio.h>
#include <stdlib.h>
#include "unicode/utypes.h"
#include "unicode/uchar.h"
#include "unicode/ustring.h"
#include "cmemory.h"
#include "cstring.h"
#include "filestrm.h"
#include "unicode/udata.h"
#include "utrie.h"
#include "utrie2.h"
#include "unicode/uset.h"
#include "toolutil.h"
#include "unewdata.h"
#include "writesrc.h"
#include "unormimp.h"
#include "gennorm.h"
#define DO_DEBUG_OUT 0
#define LENGTHOF(array) (int32_t)(sizeof(array)/sizeof((array)[0]))
/*
* The new implementation of the normalization code loads its data from
* unorm.icu, which is generated with this gennorm tool.
* The format of that file is described in unormimp.h .
*/
/* file data ---------------------------------------------------------------- */
#if UCONFIG_NO_NORMALIZATION
/* dummy UDataInfo cf. udata.h */
static UDataInfo dataInfo = {
sizeof(UDataInfo),
0,
U_IS_BIG_ENDIAN,
U_CHARSET_FAMILY,
U_SIZEOF_UCHAR,
0,
{ 0, 0, 0, 0 }, /* dummy dataFormat */
{ 0, 0, 0, 0 }, /* dummy formatVersion */
{ 0, 0, 0, 0 } /* dummy dataVersion */
};
#else
/* UDataInfo cf. udata.h */
static UDataInfo dataInfo={
sizeof(UDataInfo),
0,
U_IS_BIG_ENDIAN,
U_CHARSET_FAMILY,
U_SIZEOF_UCHAR,
0,
{ 0x4e, 0x6f, 0x72, 0x6d }, /* dataFormat="Norm" */
{ 2, 3, UTRIE_SHIFT, UTRIE_INDEX_SHIFT }, /* formatVersion */
{ 3, 2, 0, 0 } /* dataVersion (Unicode version) */
};
extern void
setUnicodeVersion(const char *v) {
UVersionInfo version;
u_versionFromString(version, v);
uprv_memcpy(dataInfo.dataVersion, version, 4);
}
static int32_t indexes[_NORM_INDEX_TOP]={ 0 };
/* builder data ------------------------------------------------------------- */
/* modularization flags, see gennorm.h (default to "store everything") */
uint32_t gStoreFlags=0xffffffff;
typedef void EnumTrieFn(void *context, uint32_t code, Norm *norm);
static UNewTrie
*normTrie,
*norm32Trie,
*fcdTrie,
*auxTrie;
static UToolMemory *normMem, *utf32Mem, *extraMem, *combiningTriplesMem;
static Norm *norms;
#if GENNORM_OBSOLETE
/*
* set a flag for each code point that was seen in decompositions -
* avoid to decompose ones that have not been used before
*/
static uint32_t haveSeenFlags[256];
#endif
/* set of characters with NFD_QC=No (i.e., those with canonical decompositions) */
static USet *nfdQCNoSet;
/* see addCombiningCP() for details */
static uint32_t combiningCPs[2000];
/*
* after processCombining() this contains for each code point in combiningCPs[]
* the runtime combining index
*/
static uint16_t combiningIndexes[2000];
/* section limits for combiningCPs[], see addCombiningCP() */
static uint16_t combineFwdTop=0, combineBothTop=0, combineBackTop=0;
/**
* Structure for a triple of code points, stored in combiningTriplesMem.
* The lead and trail code points combine into the the combined one,
* i.e., there is a canonical decomposition of combined-> <lead, trail>.
*
* Before processCombining() is called, leadIndex and trailIndex are 0.
* After processCombining(), they contain the indexes of the lead and trail
* code point in the combiningCPs[] array.
* They are then sorted by leadIndex, then trailIndex.
* They are not sorted by code points.
*/
typedef struct CombiningTriple {
uint16_t leadIndex, trailIndex;
uint32_t lead, trail, combined;
} CombiningTriple;
/* 15b in the combining index -> <=0x8000 uint16_t values in the combining table */
static uint16_t combiningTable[0x8000];
static uint16_t combiningTableTop=0;
#define _NORM_MAX_SET_SEARCH_TABLE_LENGTH 0x4000
static uint16_t canonStartSets[_NORM_MAX_CANON_SETS+2*_NORM_MAX_SET_SEARCH_TABLE_LENGTH
+10000]; /* +10000 for exclusion sets */
static int32_t canonStartSetsTop=_NORM_SET_INDEX_TOP;
static int32_t canonSetsCount=0;
/* allocate and initialize a Norm unit */
static Norm *
allocNorm() {
/* allocate Norm */
Norm *p=(Norm *)utm_alloc(normMem);
/*
* The combiningIndex must not be initialized to 0 because 0 is the
* combiningIndex of the first forward-combining character.
*/
p->combiningIndex=0xffff;
return p;
}
extern void
init() {
uint16_t *p16;
normTrie = (UNewTrie *)uprv_malloc(sizeof(UNewTrie));
uprv_memset(normTrie, 0, sizeof(UNewTrie));
norm32Trie = (UNewTrie *)uprv_malloc(sizeof(UNewTrie));
uprv_memset(norm32Trie, 0, sizeof(UNewTrie));
fcdTrie = (UNewTrie *)uprv_malloc(sizeof(UNewTrie));
uprv_memset(fcdTrie, 0, sizeof(UNewTrie));
auxTrie = (UNewTrie *)uprv_malloc(sizeof(UNewTrie));
uprv_memset(auxTrie, 0, sizeof(UNewTrie));
/* initialize the two tries */
if(NULL==utrie_open(normTrie, NULL, 30000, 0, 0, FALSE)) {
fprintf(stderr, "error: failed to initialize tries\n");
exit(U_MEMORY_ALLOCATION_ERROR);
}
/* allocate Norm structures and reset the first one */
normMem=utm_open("gennorm normalization structs", 20000, 20000, sizeof(Norm));
norms=allocNorm();
/* allocate UTF-32 string memory */
utf32Mem=utm_open("gennorm UTF-32 strings", 30000, 30000, 4);
#if GENNORM_OBSOLETE
/* reset all "have seen" flags */
uprv_memset(haveSeenFlags, 0, sizeof(haveSeenFlags));
#endif
/* open an empty set */
nfdQCNoSet=uset_open(1, 0);
/* allocate extra data memory for UTF-16 decomposition strings and other values */
extraMem=utm_open("gennorm extra 16-bit memory", _NORM_EXTRA_INDEX_TOP, _NORM_EXTRA_INDEX_TOP, 2);
/* initialize the extraMem counter for the top of FNC strings */
p16=(uint16_t *)utm_alloc(extraMem);
*p16=1;
/* allocate temporary memory for combining triples */
combiningTriplesMem=utm_open("gennorm combining triples", 0x4000, 0x4000, sizeof(CombiningTriple));
/* set the minimum code points for no/maybe quick check values to the end of the BMP */
indexes[_NORM_INDEX_MIN_NFC_NO_MAYBE]=0xffff;
indexes[_NORM_INDEX_MIN_NFKC_NO_MAYBE]=0xffff;
indexes[_NORM_INDEX_MIN_NFD_NO_MAYBE]=0xffff;
indexes[_NORM_INDEX_MIN_NFKD_NO_MAYBE]=0xffff;
/* preset the indexes portion of canonStartSets */
uprv_memset(canonStartSets, 0, _NORM_SET_INDEX_TOP*2);
}
/*
* get or create a Norm unit;
* get or create the intermediate trie entries for it as well
*/
static Norm *
createNorm(uint32_t code) {
Norm *p;
uint32_t i;
i=utrie_get32(normTrie, (UChar32)code, NULL);
if(i!=0) {
p=norms+i;
} else {
/* allocate Norm */
p=allocNorm();
if(!utrie_set32(normTrie, (UChar32)code, (uint32_t)(p-norms))) {
fprintf(stderr, "error: too many normalization entries\n");
exit(U_BUFFER_OVERFLOW_ERROR);
}
}
return p;
}
/* get an existing Norm unit */
static Norm *
getNorm(uint32_t code) {
uint32_t i;
i=utrie_get32(normTrie, (UChar32)code, NULL);
if(i==0) {
return NULL;
}
return norms+i;
}
/* get the canonical combining class of a character */
static uint8_t
getCCFromCP(uint32_t code) {
Norm *norm=getNorm(code);
if(norm==NULL) {
return 0;
} else {
return norm->udataCC;
}
}
/*
* enumerate all code points with their Norm structs and call a function for each
* return the number of code points with data
*/
static uint32_t
enumTrie(EnumTrieFn *fn, void *context) {
uint32_t count, i;
UChar32 code;
UBool isInBlockZero;
count=0;
for(code=0; code<=0x10ffff;) {
i=utrie_get32(normTrie, code, &isInBlockZero);
if(isInBlockZero) {
code+=UTRIE_DATA_BLOCK_LENGTH;
} else {
if(i!=0) {
fn(context, (uint32_t)code, norms+i);
++count;
}
++code;
}
}
return count;
}
#if GENNORM_OBSOLETE
static void
setHaveSeenString(const uint32_t *s, int32_t length) {
uint32_t c;
while(length>0) {
c=*s++;
haveSeenFlags[(c>>5)&0xff]|=(1<<(c&0x1f));
--length;
}
}
#define HAVE_SEEN(c) (haveSeenFlags[((c)>>5)&0xff]&(1<<((c)&0x1f)))
#endif
/* handle combining data ---------------------------------------------------- */
/*
* Insert an entry into combiningCPs[] for the new code point code with its flags.
* The flags indicate if code combines forward, backward, or both.
*
* combiningCPs[] contains three sections:
* 1. code points that combine forward
* 2. code points that combine forward and backward
* 3. code points that combine backward
*
* Search for code in the entire array.
* If it is found and already is in the right section (old flags==new flags)
* then we are done.
* If it is found but the flags are different, then remove it,
* union the old and new flags, and reinsert it into its correct section.
* If it is not found, then just insert it.
*
* Within each section, the code points are not sorted.
*/
static void
addCombiningCP(uint32_t code, uint8_t flags) {
uint32_t newEntry;
uint16_t i;
newEntry=code|((uint32_t)flags<<24);
/* search for this code point */
for(i=0; i<combineBackTop; ++i) {
if(code==(combiningCPs[i]&0xffffff)) {
/* found it */
if(newEntry==combiningCPs[i]) {
return; /* no change */
}
/* combine the flags, remove the old entry from the old place, and insert the new one */
newEntry|=combiningCPs[i];
if(i!=--combineBackTop) {
uprv_memmove(combiningCPs+i, combiningCPs+i+1, (combineBackTop-i)*4);
}
if(i<combineBothTop) {
--combineBothTop;
}
if(i<combineFwdTop) {
--combineFwdTop;
}
break;
}
}
/* not found or modified, insert it */
if(combineBackTop>=sizeof(combiningCPs)/4) {
fprintf(stderr, "error: gennorm combining code points - trying to use more than %ld units\n",
(long)(sizeof(combiningCPs)/4));
exit(U_MEMORY_ALLOCATION_ERROR);
}
/* set i to the insertion point */
flags=(uint8_t)(newEntry>>24);
if(flags==1) {
i=combineFwdTop++;
++combineBothTop;
} else if(flags==3) {
i=combineBothTop++;
} else /* flags==2 */ {
i=combineBackTop;
}
/* move the following code points up one and insert newEntry at i */
if(i<combineBackTop) {
uprv_memmove(combiningCPs+i+1, combiningCPs+i, (combineBackTop-i)*4);
}
combiningCPs[i]=newEntry;
/* finally increment the total counter */
++combineBackTop;
}
/**
* Find the index in combiningCPs[] where code point code is stored.
* @param code code point to look for
* @param isLead is code a forward combining code point?
* @return index in combiningCPs[] where code is stored
*/
static uint16_t
findCombiningCP(uint32_t code, UBool isLead) {
uint16_t i, limit;
if(isLead) {
i=0;
limit=combineBothTop;
} else {
i=combineFwdTop;
limit=combineBackTop;
}
/* search for this code point */
for(; i<limit; ++i) {
if(code==(combiningCPs[i]&0xffffff)) {
/* found it */
return i;
}
}
/* not found */
return 0xffff;
}
#if GENNORM_OBSOLETE
static void
addCombiningTriple(uint32_t lead, uint32_t trail, uint32_t combined) {
CombiningTriple *triple;
if(DO_NOT_STORE(UGENNORM_STORE_COMPOSITION)) {
return;
}
/*
* set combiningFlags for the two code points
* do this after decomposition so that getNorm() above returns NULL
* if we do not have actual sub-decomposition data for the initial NFD here
*/
createNorm(lead)->combiningFlags|=1; /* combines forward */
createNorm(trail)->combiningFlags|=2; /* combines backward */
addCombiningCP(lead, 1);
addCombiningCP(trail, 2);
triple=(CombiningTriple *)utm_alloc(combiningTriplesMem);
triple->lead=lead;
triple->trail=trail;
triple->combined=combined;
}
#endif
static int
compareTriples(const void *l, const void *r) {
int diff;
diff=(int)((CombiningTriple *)l)->leadIndex-
(int)((CombiningTriple *)r)->leadIndex;
if(diff==0) {
diff=(int)((CombiningTriple *)l)->trailIndex-
(int)((CombiningTriple *)r)->trailIndex;
}
return diff;
}
static void
processCombining() {
CombiningTriple *triples;
uint16_t *p;
uint32_t combined;
uint16_t i, j, count, tableTop, finalIndex, combinesFwd;
triples=utm_getStart(combiningTriplesMem);
/* add lead and trail indexes to the triples for sorting */
count=(uint16_t)utm_countItems(combiningTriplesMem);
for(i=0; i<count; ++i) {
/* findCombiningCP() must always find the code point */
triples[i].leadIndex=findCombiningCP(triples[i].lead, TRUE);
triples[i].trailIndex=findCombiningCP(triples[i].trail, FALSE);
}
/* sort them by leadIndex, trailIndex */
qsort(triples, count, sizeof(CombiningTriple), compareTriples);
/* calculate final combining indexes and store them in the Norm entries */
tableTop=0;
j=0; /* triples counter */
/* first, combining indexes of fwd/both characters are indexes into the combiningTable */
for(i=0; i<combineBothTop; ++i) {
/* start a new table */
/* assign combining index */
createNorm(combiningCPs[i]&0xffffff)->combiningIndex=combiningIndexes[i]=tableTop;
/* calculate the length of the combining data for this lead code point in the combiningTable */
while(j<count && i==triples[j].leadIndex) {
/* count 2 to 3 16-bit units per composition entry (back-index, code point) */
combined=triples[j++].combined;
if(combined<=0x1fff) {
tableTop+=2;
} else {
tableTop+=3;
}
}
}
/* second, combining indexes of back-only characters are simply incremented from here to be unique */
finalIndex=tableTop;
for(; i<combineBackTop; ++i) {
createNorm(combiningCPs[i]&0xffffff)->combiningIndex=combiningIndexes[i]=finalIndex++;
}
/* it must be finalIndex<=0x8000 because bit 15 is used in combiningTable as an end-for-this-lead marker */
if(finalIndex>0x8000) {
fprintf(stderr, "error: gennorm combining table - trying to use %u units, more than the %ld units available\n",
tableTop, (long)(sizeof(combiningTable)/4));
exit(U_MEMORY_ALLOCATION_ERROR);
}
combiningTableTop=tableTop;
/* store the combining data in the combiningTable, with the final indexes from above */
p=combiningTable;
j=0; /* triples counter */
/*
* this is essentially the same loop as above, but
* it writes the table data instead of calculating and setting the final indexes;
* it is necessary to have two passes so that all the final indexes are known before
* they are written into the table
*/
for(i=0; i<combineBothTop; ++i) {
/* start a new table */
combined=0; /* avoid compiler warning */
/* store the combining data for this lead code point in the combiningTable */
while(j<count && i==triples[j].leadIndex) {
Norm *normPtr;
finalIndex=combiningIndexes[triples[j].trailIndex];
combined=triples[j++].combined;
normPtr = getNorm(combined);
if (normPtr == NULL) {
fprintf(stderr, "error: processCombining did not get expected result. combined=%d\n", combined);
exit(U_INTERNAL_PROGRAM_ERROR);
}
/* is combined a starter? (i.e., cc==0 && combines forward) */
combinesFwd=(uint16_t)((normPtr->combiningFlags&1)<<13);
*p++=finalIndex;
if(combined<=0x1fff) {
*p++=(uint16_t)(combinesFwd|combined);
} else if(combined<=0xffff) {
*p++=(uint16_t)(0x8000|combinesFwd);
*p++=(uint16_t)combined;
} else {
*p++=(uint16_t)(0xc000|combinesFwd|((combined-0x10000)>>10));
*p++=(uint16_t)(0xdc00|(combined&0x3ff));
}
}
/* set a marker on the last final trail index in this lead's table */
if(combined<=0x1fff) {
*(p-2)|=0x8000;
} else {
*(p-3)|=0x8000;
}
}
/* post condition: tableTop==(p-combiningTable) */
}
/* processing incoming normalization data ----------------------------------- */
#if GENNORM_OBSOLETE
/*
* Decompose Hangul syllables algorithmically and fill a pseudo-Norm struct.
* c must be a Hangul syllable code point.
*/
static void
getHangulDecomposition(uint32_t c, Norm *pHangulNorm, uint32_t hangulBuffer[3]) {
/* Hangul syllable: decompose algorithmically */
uint32_t c2;
uint8_t length;
uprv_memset(pHangulNorm, 0, sizeof(Norm));
c-=HANGUL_BASE;
c2=c%JAMO_T_COUNT;
c/=JAMO_T_COUNT;
if(c2>0) {
hangulBuffer[2]=JAMO_T_BASE+c2;
length=3;
} else {
hangulBuffer[2]=0;
length=2;
}
hangulBuffer[1]=JAMO_V_BASE+c%JAMO_V_COUNT;
hangulBuffer[0]=JAMO_L_BASE+c/JAMO_V_COUNT;
pHangulNorm->nfd=hangulBuffer;
pHangulNorm->lenNFD=length;
if(DO_STORE(UGENNORM_STORE_COMPAT)) {
pHangulNorm->nfkd=hangulBuffer;
pHangulNorm->lenNFKD=length;
}
}
#endif
/*
* decompose the one decomposition further, may generate two decompositions
* apply all previous characters' decompositions to this one
*/
static void
decompStoreNewNF(uint32_t code, Norm *norm) {
#if !GENNORM_OBSOLETE
/* always allocate the original string */
uint32_t *s32;
uint8_t length;
if((length=norm->lenNFD)!=0) {
s32=utm_allocN(utf32Mem, norm->lenNFD);
uprv_memcpy(s32, norm->nfd, norm->lenNFD*4);
norm->nfd=s32;
} else if((length=norm->lenNFKD)!=0) {
s32=utm_allocN(utf32Mem, norm->lenNFKD);
uprv_memcpy(s32, norm->nfkd, norm->lenNFKD*4);
norm->nfkd=s32;
}
#else
uint32_t nfd[40], nfkd[40], hangulBuffer[3];
Norm hangulNorm;
uint32_t *s32;
Norm *p;
uint32_t c;
int32_t i, length;
uint8_t lenNFD=0, lenNFKD=0;
UBool changedNFD=FALSE, changedNFKD=FALSE;
if((length=norm->lenNFD)!=0) {
/* always allocate the original string */
changedNFD=TRUE;
s32=norm->nfd;
} else if((length=norm->lenNFKD)!=0) {
/* always allocate the original string */
changedNFKD=TRUE;
s32=norm->nfkd;
} else {
/* no decomposition here, nothing to do */
return;
}
/* decompose each code point */
for(i=0; i<length; ++i) {
c=s32[i];
p=getNorm(c);
if(p==NULL) {
if(HANGUL_BASE<=c && c<(HANGUL_BASE+HANGUL_COUNT)) {
getHangulDecomposition(c, &hangulNorm, hangulBuffer);
p=&hangulNorm;
} else {
/* no data, no decomposition */
nfd[lenNFD++]=c;
nfkd[lenNFKD++]=c;
continue;
}
}
/* canonically decompose c */
if(changedNFD) {
if(p->lenNFD!=0) {
uprv_memcpy(nfd+lenNFD, p->nfd, p->lenNFD*4);
lenNFD+=p->lenNFD;
} else {
nfd[lenNFD++]=c;
}
}
/* compatibility-decompose c */
if(p->lenNFKD!=0) {
uprv_memcpy(nfkd+lenNFKD, p->nfkd, p->lenNFKD*4);
lenNFKD+=p->lenNFKD;
changedNFKD=TRUE;
} else if(p->lenNFD!=0) {
uprv_memcpy(nfkd+lenNFKD, p->nfd, p->lenNFD*4);
lenNFKD+=p->lenNFD;
/*
* not changedNFKD=TRUE;
* so that we do not store a new nfkd if there was no nfkd string before
* and we only see canonical decompositions
*/
} else {
nfkd[lenNFKD++]=c;
}
}
/* assume that norm->lenNFD==1 or ==2 */
if(norm->lenNFD==2 && !(norm->combiningFlags&0x80)) {
addCombiningTriple(s32[0], s32[1], code);
}
if(changedNFD) {
if(lenNFD!=0) {
s32=utm_allocN(utf32Mem, lenNFD);
uprv_memcpy(s32, nfd, lenNFD*4);
} else {
s32=NULL;
}
norm->lenNFD=lenNFD;
norm->nfd=s32;
setHaveSeenString(nfd, lenNFD);
}
if(changedNFKD) {
if(lenNFKD!=0) {
s32=utm_allocN(utf32Mem, lenNFKD);
uprv_memcpy(s32, nfkd, lenNFKD*4);
} else {
s32=NULL;
}
norm->lenNFKD=lenNFKD;
norm->nfkd=s32;
setHaveSeenString(nfkd, lenNFKD);
}
#endif
}
#if GENNORM_OBSOLETE
typedef struct DecompSingle {
uint32_t c;
Norm *norm;
} DecompSingle;
/*
* apply this one character's decompositions (there is at least one!) to
* all previous characters' decompositions to decompose them further
*/
static void
decompWithSingleFn(void *context, uint32_t code, Norm *norm) {
uint32_t nfd[40], nfkd[40];
uint32_t *s32;
DecompSingle *me=(DecompSingle *)context;
uint32_t c, myC;
int32_t i, length;
uint8_t lenNFD=0, lenNFKD=0, myLenNFD, myLenNFKD;
UBool changedNFD=FALSE, changedNFKD=FALSE;
/* get the new character's data */
myC=me->c;
myLenNFD=me->norm->lenNFD;
myLenNFKD=me->norm->lenNFKD;
/* assume that myC has at least one decomposition */
if((length=norm->lenNFD)!=0 && myLenNFD!=0) {
/* apply NFD(myC) to norm->nfd */
s32=norm->nfd;
for(i=0; i<length; ++i) {
c=s32[i];
if(c==myC) {
uprv_memcpy(nfd+lenNFD, me->norm->nfd, myLenNFD*4);
lenNFD+=myLenNFD;
changedNFD=TRUE;
} else {
nfd[lenNFD++]=c;
}
}
}
if((length=norm->lenNFKD)!=0) {
/* apply NFD(myC) and NFKD(myC) to norm->nfkd */
s32=norm->nfkd;
for(i=0; i<length; ++i) {
c=s32[i];
if(c==myC) {
if(myLenNFKD!=0) {
uprv_memcpy(nfkd+lenNFKD, me->norm->nfkd, myLenNFKD*4);
lenNFKD+=myLenNFKD;
} else /* assume myLenNFD!=0 */ {
uprv_memcpy(nfkd+lenNFKD, me->norm->nfd, myLenNFD*4);
lenNFKD+=myLenNFD;
}
changedNFKD=TRUE;
} else {
nfkd[lenNFKD++]=c;
}
}
} else if((length=norm->lenNFD)!=0 && myLenNFKD!=0) {
/* apply NFKD(myC) to norm->nfd, forming a new norm->nfkd */
s32=norm->nfd;
for(i=0; i<length; ++i) {
c=s32[i];
if(c==myC) {
uprv_memcpy(nfkd+lenNFKD, me->norm->nfkd, myLenNFKD*4);
lenNFKD+=myLenNFKD;
changedNFKD=TRUE;
} else {
nfkd[lenNFKD++]=c;
}
}
}
/* set the new decompositions, forget the old ones */
if(changedNFD) {
if(lenNFD!=0) {
if(lenNFD>norm->lenNFD) {
s32=utm_allocN(utf32Mem, lenNFD);
} else {
s32=norm->nfd;
}
uprv_memcpy(s32, nfd, lenNFD*4);
} else {
s32=NULL;
}
norm->lenNFD=lenNFD;
norm->nfd=s32;
}
if(changedNFKD) {
if(lenNFKD!=0) {
if(lenNFKD>norm->lenNFKD) {
s32=utm_allocN(utf32Mem, lenNFKD);
} else {
s32=norm->nfkd;
}
uprv_memcpy(s32, nfkd, lenNFKD*4);
} else {
s32=NULL;
}
norm->lenNFKD=lenNFKD;
norm->nfkd=s32;
}
}
#endif
/*
* process the data for one code point listed in UnicodeData;
* UnicodeData itself never maps a code point to both NFD and NFKD
*/
extern void
storeNorm(uint32_t code, Norm *norm) {
#if GENNORM_OBSOLETE
DecompSingle decompSingle;
#endif
Norm *p;
if(DO_NOT_STORE(UGENNORM_STORE_COMPAT)) {
/* ignore compatibility decomposition */
norm->lenNFKD=0;
}
/* copy existing derived normalization properties */
p=createNorm(code);
norm->qcFlags=p->qcFlags;
norm->combiningFlags=p->combiningFlags;
norm->fncIndex=p->fncIndex;
/* process the decomposition if there is one here */
if((norm->lenNFD|norm->lenNFKD)!=0) {
/* decompose this one decomposition further, may generate two decompositions */
decompStoreNewNF(code, norm);
#if GENNORM_OBSOLETE
/* has this code point been used in previous decompositions? */
if(HAVE_SEEN(code)) {
/* use this decomposition to decompose other decompositions further */
decompSingle.c=code;
decompSingle.norm=norm;
enumTrie(decompWithSingleFn, &decompSingle);
}
#endif
}
/* store the data */
uprv_memcpy(p, norm, sizeof(Norm));
}
extern void
setQCFlags(uint32_t code, uint8_t qcFlags) {
if(DO_NOT_STORE(UGENNORM_STORE_COMPAT)) {
/* ignore compatibility decomposition: unset the KC/KD flags */
qcFlags&=~(_NORM_QC_NFKC|_NORM_QC_NFKD);
/* set the KC/KD flags to the same values as the C/D flags */
qcFlags|=qcFlags<<1;
}
if(DO_NOT_STORE(UGENNORM_STORE_COMPOSITION)) {
/* ignore composition data: unset the C/KC flags */
qcFlags&=~(_NORM_QC_NFC|_NORM_QC_NFKC);
/* set the C/KC flags to the same values as the D/KD flags */
qcFlags|=qcFlags>>2;
}
createNorm(code)->qcFlags|=qcFlags;
/* adjust the minimum code point for quick check no/maybe */
if(code<0xffff) {
if((qcFlags&_NORM_QC_NFC) && (uint16_t)code<indexes[_NORM_INDEX_MIN_NFC_NO_MAYBE]) {
indexes[_NORM_INDEX_MIN_NFC_NO_MAYBE]=(uint16_t)code;
}
if((qcFlags&_NORM_QC_NFKC) && (uint16_t)code<indexes[_NORM_INDEX_MIN_NFKC_NO_MAYBE]) {
indexes[_NORM_INDEX_MIN_NFKC_NO_MAYBE]=(uint16_t)code;
}
if((qcFlags&_NORM_QC_NFD) && (uint16_t)code<indexes[_NORM_INDEX_MIN_NFD_NO_MAYBE]) {
indexes[_NORM_INDEX_MIN_NFD_NO_MAYBE]=(uint16_t)code;
}
if((qcFlags&_NORM_QC_NFKD) && (uint16_t)code<indexes[_NORM_INDEX_MIN_NFKD_NO_MAYBE]) {
indexes[_NORM_INDEX_MIN_NFKD_NO_MAYBE]=(uint16_t)code;
}
}
if(qcFlags&_NORM_QC_NFD) {
uset_add(nfdQCNoSet, (UChar32)code);
}
}
extern void
setCompositionExclusion(uint32_t code) {
if(DO_STORE(UGENNORM_STORE_COMPOSITION)) {
createNorm(code)->combiningFlags|=0x80;
}
}
static void
setHangulJamoSpecials() {
Norm *norm;
uint32_t c, hangul;
/*
* Hangul syllables are algorithmically decomposed into Jamos,
* and Jamos are algorithmically composed into Hangul syllables.
* The quick check flags are parsed, except for Hangul.
*/
/* set Jamo L specials */
hangul=0xac00;
for(c=0x1100; c<=0x1112; ++c) {
norm=createNorm(c);
norm->specialTag=_NORM_EXTRA_INDEX_TOP+_NORM_EXTRA_JAMO_L;
if(DO_STORE(UGENNORM_STORE_COMPOSITION)) {
norm->combiningFlags=1;
}
/* for each Jamo L create a set with its associated Hangul block */
norm->canonStart=uset_open(hangul, hangul+21*28-1);
hangul+=21*28;
}
/* set Jamo V specials */
for(c=0x1161; c<=0x1175; ++c) {
norm=createNorm(c);
norm->specialTag=_NORM_EXTRA_INDEX_TOP+_NORM_EXTRA_JAMO_V;
if(DO_STORE(UGENNORM_STORE_COMPOSITION)) {
norm->combiningFlags=2;
}
norm->unsafeStart=TRUE;
}
/* set Jamo T specials */
for(c=0x11a8; c<=0x11c2; ++c) {
norm=createNorm(c);
norm->specialTag=_NORM_EXTRA_INDEX_TOP+_NORM_EXTRA_JAMO_T;
if(DO_STORE(UGENNORM_STORE_COMPOSITION)) {
norm->combiningFlags=2;
}
norm->unsafeStart=TRUE;
}
/* set Hangul specials, precompacted */
norm=allocNorm();
norm->specialTag=_NORM_EXTRA_INDEX_TOP+_NORM_EXTRA_HANGUL;
if(DO_STORE(UGENNORM_STORE_COMPAT)) {
norm->qcFlags=_NORM_QC_NFD|_NORM_QC_NFKD;
} else {
norm->qcFlags=_NORM_QC_NFD;
}
if(!utrie_setRange32(normTrie, 0xac00, 0xd7a4, (uint32_t)(norm-norms), TRUE)) {
fprintf(stderr, "error: too many normalization entries (setting Hangul)\n");
exit(U_BUFFER_OVERFLOW_ERROR);
}
}
/*
* set FC-NFKC-Closure string
* s contains the closure string; s[0]==length, s[1..length] is the actual string
* may modify s[0]
*/
U_CFUNC void
setFNC(uint32_t c, UChar *s) {
uint16_t *p;
int32_t length, i, count;
UChar first;
if( DO_NOT_STORE(UGENNORM_STORE_COMPAT) ||
DO_NOT_STORE(UGENNORM_STORE_COMPOSITION) ||
DO_NOT_STORE(UGENNORM_STORE_AUX)
) {
return;
}
count=utm_countItems(extraMem);
length=s[0];
first=s[1];
/* try to overlay single-unit strings with existing ones */
if(length==1 && first<0xff00) {
p=utm_getStart(extraMem);
for(i=1; i<count; ++i) {
if(first==p[i]) {
break;
}
}
} else {
i=count;
}
/* append the new string if it cannot be overlayed with an old one */
if(i==count) {
if(count>_NORM_AUX_MAX_FNC) {
fprintf(stderr, "gennorm error: too many FNC strings\n");
exit(U_INDEX_OUTOFBOUNDS_ERROR);
}
/* prepend 0xffxx with xx==length */
s[0]=(uint16_t)(0xff00+length);
++length;
p=(uint16_t *)utm_allocN(extraMem, length);
uprv_memcpy(p, s, length*2);
/* update the top index in extraMem[0] */
count+=length;
((uint16_t *)utm_getStart(extraMem))[0]=(uint16_t)count;
}
/* store the index to the string */
createNorm(c)->fncIndex=i;
}
/* build runtime structures ------------------------------------------------- */
/* canonically reorder a UTF-32 string; return { leadCC, trailCC } */
static uint16_t
reorderString(uint32_t *s, int32_t length) {
uint8_t ccs[40];
uint32_t c;
int32_t i, j;
uint8_t cc, prevCC;
if(length<=0) {
return 0;
}
for(i=0; i<length; ++i) {
/* get the i-th code point and its combining class */
c=s[i];
cc=getCCFromCP(c);
if(cc!=0 && i!=0) {
/* it is a combining mark, see if it needs to be moved back */
j=i;
do {
prevCC=ccs[j-1];
if(prevCC<=cc) {
break; /* found the right place */
}
/* move the previous code point here and go back */
s[j]=s[j-1];
ccs[j]=prevCC;
} while(--j!=0);
s[j]=c;
ccs[j]=cc;
} else {
/* just store the combining class */
ccs[i]=cc;
}
}
return (uint16_t)(((uint16_t)ccs[0]<<8)|ccs[length-1]);
}
#if 0
static UBool combineAndQC[64]={ 0 };
#endif
/*
* canonically reorder the up to two decompositions
* and store the leading and trailing combining classes accordingly
*
* also process canonical decompositions for canonical closure
*/
static void
postParseFn(void *context, uint32_t code, Norm *norm) {
int32_t length;
/* canonically order the NFD */
length=norm->lenNFD;
if(length>0) {
norm->canonBothCCs=reorderString(norm->nfd, length);
}
/* canonically reorder the NFKD */
length=norm->lenNFKD;
if(length>0) {
norm->compatBothCCs=reorderString(norm->nfkd, length);
}
/* verify that code has a decomposition if and only if the quick check flags say "no" on NF(K)D */
if((norm->lenNFD!=0) != ((norm->qcFlags&_NORM_QC_NFD)!=0)) {
fprintf(stderr, "gennorm warning: U+%04lx has NFD[%d] but quick check 0x%02x\n", (long)code, norm->lenNFD, norm->qcFlags);
}
if(((norm->lenNFD|norm->lenNFKD)!=0) != ((norm->qcFlags&(_NORM_QC_NFD|_NORM_QC_NFKD))!=0)) {
fprintf(stderr, "gennorm warning: U+%04lx has NFD[%d] NFKD[%d] but quick check 0x%02x\n", (long)code, norm->lenNFD, norm->lenNFKD, norm->qcFlags);
}
/* see which combinations of combiningFlags and qcFlags are used for NFC/NFKC */
#if 0
combineAndQC[(norm->qcFlags&0x33)|((norm->combiningFlags&3)<<2)]=1;
#endif
if(norm->combiningFlags&1) {
if(norm->udataCC!=0) {
/* illegal - data-derivable composition exclusion */
fprintf(stderr, "gennorm warning: U+%04lx combines forward but udataCC==%u\n", (long)code, norm->udataCC);
}
}
if(norm->combiningFlags&2) {
if((norm->qcFlags&0x11)==0) {
fprintf(stderr, "gennorm warning: U+%04lx combines backward but qcNF?C==0\n", (long)code);
}
#if 0
/* occurs sometimes, this one is ok (therefore #if 0) - still here for documentation */
if(norm->udataCC==0) {
printf("U+%04lx combines backward but udataCC==0\n", (long)code);
}
#endif
}
if((norm->combiningFlags&3)==3 && beVerbose) {
printf("U+%04lx combines both ways\n", (long)code);
}
/*
* process canonical decompositions for canonical closure
*
* in each canonical decomposition:
* add the current character (code) to the set of canonical starters of its norm->nfd[0]
* set the "unsafe starter" flag for each norm->nfd[1..]
*/
length=norm->lenNFD;
if(length>0) {
Norm *otherNorm;
UChar32 c;
int32_t i;
/* nfd[0].canonStart.add(code) */
c=norm->nfd[0];
otherNorm=createNorm(c);
if(otherNorm->canonStart==NULL) {
otherNorm->canonStart=uset_open(code, code);
if(otherNorm->canonStart==NULL) {
fprintf(stderr, "gennorm error: out of memory in uset_open()\n");
exit(U_MEMORY_ALLOCATION_ERROR);
}
} else {
uset_add(otherNorm->canonStart, code);
if(!uset_contains(otherNorm->canonStart, code)) {
fprintf(stderr, "gennorm error: uset_add(setOf(U+%4x), U+%4x)\n", (int)c, (int)code);
exit(U_INTERNAL_PROGRAM_ERROR);
}
}
/* for(i=1..length-1) nfd[i].unsafeStart=TRUE */
for(i=1; i<length; ++i) {
createNorm(norm->nfd[i])->unsafeStart=TRUE;
}
}
}
static uint32_t
make32BitNorm(Norm *norm) {
UChar extra[100];
const Norm *other;
uint32_t word;
int32_t i, length, beforeZero=0, count, start;
/*
* Check for assumptions:
*
* Test that if a "true starter" (cc==0 && NF*C_YES) decomposes,
* then the decomposition also begins with a true starter.
*/
if(norm->udataCC==0) {
/* this is a starter */
if((norm->qcFlags&_NORM_QC_NFC)==0 && norm->lenNFD>0) {
/* a "true" NFC starter with a canonical decomposition */
if( norm->canonBothCCs>=0x100 || /* lead cc!=0 or */
((other=getNorm(norm->nfd[0]))!=NULL && (other->qcFlags&_NORM_QC_NFC)!=0) /* nfd[0] not NFC_YES */
) {
fprintf(stderr,
"error: true NFC starter canonical decomposition[%u] does not begin\n"
" with a true NFC starter: U+%04lx U+%04lx%s\n",
norm->lenNFD, (long)norm->nfd[0], (long)norm->nfd[1],
norm->lenNFD<=2 ? "" : " ...");
exit(U_INVALID_TABLE_FILE);
}
}
if((norm->qcFlags&_NORM_QC_NFKC)==0) {
if(norm->lenNFKD>0) {
/* a "true" NFKC starter with a compatibility decomposition */
if( norm->compatBothCCs>=0x100 || /* lead cc!=0 or */
((other=getNorm(norm->nfkd[0]))!=NULL && (other->qcFlags&_NORM_QC_NFKC)!=0) /* nfkd[0] not NFKC_YES */
) {
fprintf(stderr,
"error: true NFKC starter compatibility decomposition[%u] does not begin\n"
" with a true NFKC starter: U+%04lx U+%04lx%s\n",
norm->lenNFKD, (long)norm->nfkd[0], (long)norm->nfkd[1],
norm->lenNFKD<=2 ? "" : " ...");
exit(U_INVALID_TABLE_FILE);
}
} else if(norm->lenNFD>0) {
/* a "true" NFKC starter with only a canonical decomposition */
if( norm->canonBothCCs>=0x100 || /* lead cc!=0 or */
((other=getNorm(norm->nfd[0]))!=NULL && (other->qcFlags&_NORM_QC_NFKC)!=0) /* nfd[0] not NFKC_YES */
) {
fprintf(stderr,
"error: true NFKC starter canonical decomposition[%u] does not begin\n"
" with a true NFKC starter: U+%04lx U+%04lx%s\n",
norm->lenNFD, (long)norm->nfd[0], (long)norm->nfd[1],
norm->lenNFD<=2 ? "" : " ...");
exit(U_INVALID_TABLE_FILE);
}
}
}
}
/* reset the 32-bit word and set the quick check flags */
word=norm->qcFlags;
/* set the UnicodeData combining class */
word|=(uint32_t)norm->udataCC<<_NORM_CC_SHIFT;
/* set the combining flag and index */
if(norm->combiningFlags&3) {
word|=(uint32_t)(norm->combiningFlags&3)<<6;
}
/* set the combining index value into the extra data */
/* 0xffff: no combining index; 0..0x7fff: combining index */
if(norm->combiningIndex!=0xffff) {
extra[0]=norm->combiningIndex;
beforeZero=1;
}
count=beforeZero;
/* write the decompositions */
if((norm->lenNFD|norm->lenNFKD)!=0) {
extra[count++]=0; /* set the pieces when available, into extra[beforeZero] */
length=norm->lenNFD;
if(length>0) {
if(norm->canonBothCCs!=0) {
extra[beforeZero]|=0x80;
extra[count++]=norm->canonBothCCs;
}
start=count;
for(i=0; i<length; ++i) {
UTF_APPEND_CHAR_UNSAFE(extra, count, norm->nfd[i]);
}
extra[beforeZero]|=(UChar)(count-start); /* set the decomp length as the number of UTF-16 code units */
}
length=norm->lenNFKD;
if(length>0) {
if(norm->compatBothCCs!=0) {
extra[beforeZero]|=0x8000;
extra[count++]=norm->compatBothCCs;
}
start=count;
for(i=0; i<length; ++i) {
UTF_APPEND_CHAR_UNSAFE(extra, count, norm->nfkd[i]);
}
extra[beforeZero]|=(UChar)((count-start)<<8); /* set the decomp length as the number of UTF-16 code units */
}
}
/* allocate and copy the extra data */
if(count!=0) {
UChar *p;
if(norm->specialTag!=0) {
fprintf(stderr, "error: gennorm - illegal to have both extra data and a special tag (0x%x)\n", norm->specialTag);
exit(U_ILLEGAL_ARGUMENT_ERROR);
}
p=(UChar *)utm_allocN(extraMem, count);
uprv_memcpy(p, extra, count*2);
/* set the extra index, offset by beforeZero */
word|=(uint32_t)(beforeZero+(p-(UChar *)utm_getStart(extraMem)))<<_NORM_EXTRA_SHIFT;
} else if(norm->specialTag!=0) {
/* set a special tag instead of an extra index */
word|=(uint32_t)norm->specialTag<<_NORM_EXTRA_SHIFT;
}
return word;
}
/* turn all Norm structs into corresponding 32-bit norm values */
static void
makeAll32() {
uint32_t *pNormData;
uint32_t n;
int32_t i, normLength, count;
count=(int32_t)utm_countItems(normMem);
for(i=0; i<count; ++i) {
norms[i].value32=make32BitNorm(norms+i);
}
pNormData=utrie_getData(norm32Trie, &normLength);
count=0; /* count is now just used for debugging */
for(i=0; i<normLength; ++i) {
n=pNormData[i];
if(0!=(pNormData[i]=norms[n].value32)) {
++count;
}
}
}
/*
* extract all Norm.canonBothCCs into the FCD table
* set 32-bit values to use the common fold and compact functions
*/
static void
makeFCD() {
uint32_t *pFCDData;
uint32_t n;
int32_t i, count, fcdLength;
uint16_t bothCCs;
count=utm_countItems(normMem);
for(i=0; i<count; ++i) {
bothCCs=norms[i].canonBothCCs;
if(bothCCs==0) {
/* if there are no decomposition cc's then use the udataCC twice */
bothCCs=norms[i].udataCC;
bothCCs|=bothCCs<<8;
}
norms[i].value32=bothCCs;
}
pFCDData=utrie_getData(fcdTrie, &fcdLength);
for(i=0; i<fcdLength; ++i) {
n=pFCDData[i];
pFCDData[i]=norms[n].value32;
}
}
/**
* If the given set contains exactly one character, then return it.
* Otherwise return -1.
*/
static int32_t
usetContainsOne(const USet* set) {
if(uset_getItemCount(set)==1) {
/* there is a single item (a single range) */
UChar32 start, end;
UErrorCode ec=U_ZERO_ERROR;
int32_t len=uset_getItem(set, 0, &start, &end, NULL, 0, &ec);
if (len==0 && start==end) { /* a range (len==0) with a single code point */
return start;
}
}
return -1;
}
static void
makeCanonSetFn(void *context, uint32_t code, Norm *norm) {
if(norm->canonStart!=NULL && !uset_isEmpty(norm->canonStart)) {
uint16_t *table;
int32_t c, tableLength;
UErrorCode errorCode=U_ZERO_ERROR;
/* does the set contain exactly one code point? */
c=usetContainsOne(norm->canonStart);
/* add an entry to the BMP or supplementary search table */
if(code<=0xffff) {
table=canonStartSets+_NORM_MAX_CANON_SETS;
tableLength=canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH];
table[tableLength++]=(uint16_t)code;
if(c>=0 && c<=0xffff && (c&_NORM_CANON_SET_BMP_MASK)!=_NORM_CANON_SET_BMP_IS_INDEX) {
/* single-code point BMP result for BMP code point */
table[tableLength++]=(uint16_t)c;
} else {
table[tableLength++]=(uint16_t)(_NORM_CANON_SET_BMP_IS_INDEX|canonStartSetsTop);
c=-1;
}
canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH]=(uint16_t)tableLength;
} else {
table=canonStartSets+_NORM_MAX_CANON_SETS+_NORM_MAX_SET_SEARCH_TABLE_LENGTH;
tableLength=canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH];
table[tableLength++]=(uint16_t)(code>>16);
table[tableLength++]=(uint16_t)code;
if(c>=0) {
/* single-code point result for supplementary code point */
table[tableLength-2]|=(uint16_t)(0x8000|((c>>8)&0x1f00));
table[tableLength++]=(uint16_t)c;
} else {
table[tableLength++]=(uint16_t)canonStartSetsTop;
}
canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH]=(uint16_t)tableLength;
}
if(c<0) {
/* write a USerializedSet */
++canonSetsCount;
canonStartSetsTop+=
uset_serialize(norm->canonStart,
canonStartSets+canonStartSetsTop,
_NORM_MAX_CANON_SETS-canonStartSetsTop,
&errorCode);
}
canonStartSets[_NORM_SET_INDEX_CANON_SETS_LENGTH]=(uint16_t)canonStartSetsTop;
if(U_FAILURE(errorCode)) {
fprintf(stderr, "gennorm error: uset_serialize()->%s (canonStartSetsTop=%d)\n", u_errorName(errorCode), (int)canonStartSetsTop);
exit(errorCode);
}
if(tableLength>_NORM_MAX_SET_SEARCH_TABLE_LENGTH) {
fprintf(stderr, "gennorm error: search table for canonical starter sets too long\n");
exit(U_INDEX_OUTOFBOUNDS_ERROR);
}
}
}
/* for getSkippableFlags ---------------------------------------------------- */
/* combine the lead and trail code points; return <0 if they do not combine */
static int32_t
combine(uint32_t lead, uint32_t trail) {
CombiningTriple *triples;
uint32_t i, count;
/* search for all triples with c as lead code point */
triples=utm_getStart(combiningTriplesMem);
count=utm_countItems(combiningTriplesMem);
/* triples are not sorted by code point but for each lead CP there is one contiguous block */
for(i=0; i<count && lead!=triples[i].lead; ++i) {}
/* check each triple for this code point */
for(; i<count && lead==triples[i].lead; ++i) {
if(trail==triples[i].trail) {
return (int32_t)triples[i].combined;
}
}
return -1;
}
/*
* Starting from the canonical decomposition s[0..length[ of a single code point,
* is the code point c consumed in an NFC/FCC recomposition?
*
* No need to handle discontiguous composition because that would not consume some
* intermediate character, so would not compose back to the original character.
* See comments in canChangeWithFollowing().
*
* No need to compose beyond where c canonically orders because if it is consumed
* then the result differs from the original anyway.
*
* Possible optimization:
* - Verify that there are no cases of the same combining mark stacking twice.
* - return FALSE right away if c inserts after a copy of itself
* without attempting to recompose; will happen because each mark in
* the decomposition will be enumerated and passed in as c.
* More complicated and fragile though than it is already.
*
* markus 2002nov04
*/
static UBool
doesComposeConsume(const uint32_t *s, int32_t length, uint32_t c, uint8_t cc) {
int32_t starter, i;
/* ignore trailing characters where cc<prevCC */
while(length>1 && cc<getCCFromCP(s[length-1])) {
--length;
}
/* start consuming/combining from the beginning */
starter=(int32_t)s[0];
for(i=1; i<length; ++i) {
starter=combine((uint32_t)starter, s[i]);
if(starter<0) {
fprintf(stderr, "error: unable to consume normal decomposition in doesComposeConsume(<%04x, %04x, ...>[%d], U+%04x, %u)\n",
(int)s[0], (int)s[1], (int)length, (int)c, cc);
exit(U_INTERNAL_PROGRAM_ERROR);
}
}
/* try to combine/consume c, return TRUE if it is consumed */
return combine((uint32_t)starter, c)>=0;
}
/* does the starter s[0] combine forward with another char that is below trailCC? */
static UBool
canChangeWithFollowing(const uint32_t *s, int32_t length, uint8_t trailCC) {
if(trailCC<=1) {
/* no character will combine ahead of the trailing char of the decomposition */
return FALSE;
}
/*
* We are only checking skippable condition (f).
* Therefore, the original character does not have quick check flag NFC_NO (c),
* i.e., the decomposition recomposes completely back into the original code point.
* So s[0] must be a true starter with cc==0 and
* combining with following code points.
*
* Similarly, length==1 is not possible because that would be a singleton
* decomposition which is marked with NFC_NO and does not pass (c).
*
* Only a character with cc<trailCC can change the composition.
* Reason: A char with cc>=trailCC would order after decomposition s[],
* composition would consume all of the decomposition, and here we know that
* the original char passed check d), i.e., it does not combine forward,
* therefore does not combine with anything after the decomposition is consumed.
*
* Now see if there is a character that
* 1. combines backward
* 2. has cc<trailCC
* 3. is consumed in recomposition
*
* length==2 is simple:
*
* Characters that fulfill these conditions are exactly the ones that combine directly
* with the starter c==s[0] because there is no intervening character after
* reordering.
* We can just enumerate all chars with which c combines (they all pass 1. and 3.)
* and see if one has cc<trailCC (passes 2.).
*
* length>2 is a little harder:
*
* Since we will get different starters during recomposition, we need to
* enumerate each backward-combining character (1.)
* with cc<trailCC (2.) and
* see if it gets consumed in recomposition. (3.)
* No need to enumerate both-ways combining characters because they must have cc==0.
*/
if(length==2) {
/* enumerate all chars that combine with this one and check their cc */
CombiningTriple *triples;
uint32_t c, i, count;
uint8_t cc;
/* search for all triples with c as lead code point */
triples=utm_getStart(combiningTriplesMem);
count=utm_countItems(combiningTriplesMem);
c=s[0];
/* triples are not sorted by code point but for each lead CP there is one contiguous block */
for(i=0; i<count && c!=triples[i].lead; ++i) {}
/* check each triple for this code point */
for(; i<count && c==triples[i].lead; ++i) {
cc=getCCFromCP(triples[i].trail);
if(cc>0 && cc<trailCC) {
/* this trail code point combines with c and has cc<trailCC */
return TRUE;
}
}
} else {
/* enumerate all chars that combine backward */
uint32_t c2;
uint16_t i;
uint8_t cc;
for(i=combineBothTop; i<combineBackTop; ++i) {
c2=combiningCPs[i]&0xffffff;
cc=getCCFromCP(c2);
/* pass in length-1 because we already know that c2 will insert before the last character with trailCC */
if(cc>0 && cc<trailCC && doesComposeConsume(s, length-1, c2, cc)) {
return TRUE;
}
}
}
/* this decomposition is not modified by any appended character */
return FALSE;
}
/* see unormimp.h for details on NF*C Skippable flags */
static uint32_t
getSkippableFlags(const Norm *norm) {
/* ignore NF*D skippable properties because they are covered by norm32, test at runtime */
/* ignore Hangul, test those at runtime (LV Hangul are not skippable) */
if(norm->specialTag==_NORM_EXTRA_INDEX_TOP+_NORM_EXTRA_HANGUL) {
return 0;
}
/* ### TODO check other data generation functions whether they should & do ignore Hangul/Jamo specials */
/*
* Note:
* This function returns a non-zero flag only if (a)..(e) indicate skippable but (f) does not.
*
* This means that (a)..(e) must always be derived from the runtime norm32 value,
* and (f) be checked from the auxTrie if the character is skippable per (a)..(e),
* the form is NF*C and there is a canonical decomposition (NFD_NO).
*
* (a) unassigned code points get "not skippable"==false because they
* don't have a Norm struct so they won't get here
*/
/* (b) not skippable if cc!=0 */
if(norm->udataCC!=0) {
return 0; /* non-zero flag for (f) only */
}
/*
* not NFC_Skippable if
* (c) quick check flag == NO or
* (d) combines forward or
* (e) combines back or
* (f) can change if another character is added
*
* for (f):
* For NF*C: Get corresponding decomposition, get its last starter (cc==0),
* check its composition list,
* see if any of the second code points in the list
* has cc less than the trailCC of the decomposition.
*
* For FCC: Test at runtime if the decomposition has a trailCC>1
* -> there are characters with cc==1, they would order before the trail char
* and prevent contiguous combination with the trail char.
*/
if( (norm->qcFlags&(_NORM_QC_NFC&_NORM_QC_ANY_NO))!=0 ||
(norm->combiningFlags&3)!=0) {
return 0; /* non-zero flag for (f) only */
}
if(norm->lenNFD!=0 && canChangeWithFollowing(norm->nfd, norm->lenNFD, (uint8_t)norm->canonBothCCs)) {
return _NORM_AUX_NFC_SKIP_F_MASK;
}
return 0; /* skippable */
}
static void
makeAux() {
Norm *norm;
uint32_t *pData;
int32_t i, length;
pData=utrie_getData(auxTrie, &length);
for(i=0; i<length; ++i) {
norm=norms+pData[i];
/*
* 16-bit auxiliary normalization properties
* see unormimp.h
*/
pData[i]=
((uint32_t)(norm->combiningFlags&0x80)<<(_NORM_AUX_COMP_EX_SHIFT-7))|
(uint32_t)norm->fncIndex;
if(norm->unsafeStart || norm->udataCC!=0) {
pData[i]|=_NORM_AUX_UNSAFE_MASK;
}
pData[i]|=getSkippableFlags(norm);
}
}
/* folding value for normalization: just store the offset (16 bits) if there is any non-0 entry */
static uint32_t U_CALLCONV
getFoldedNormValue(UNewTrie *trie, UChar32 start, int32_t offset) {
uint32_t value, leadNorm32=0;
UChar32 limit;
UBool inBlockZero;
limit=start+0x400;
while(start<limit) {
value=utrie_get32(trie, start, &inBlockZero);
if(inBlockZero) {
start+=UTRIE_DATA_BLOCK_LENGTH;
} else {
if(value!=0) {
leadNorm32|=value;
}
++start;
}
}
/* turn multi-bit fields into the worst-case value */
if(leadNorm32&_NORM_CC_MASK) {
leadNorm32|=_NORM_CC_MASK;
}
/* clean up unnecessarily ored bit fields */
leadNorm32&=~((uint32_t)0xffffffff<<_NORM_EXTRA_SHIFT);
if(leadNorm32==0) {
/* nothing to do (only composition exclusions?) */
return 0;
}
/* add the extra surrogate index, offset by the BMP top, for the new stage 1 location */
leadNorm32|=(
(uint32_t)_NORM_EXTRA_INDEX_TOP+
(uint32_t)((offset-UTRIE_BMP_INDEX_LENGTH)>>UTRIE_SURROGATE_BLOCK_BITS)
)<<_NORM_EXTRA_SHIFT;
return leadNorm32;
}
/* folding value for FCD: use default function (just store the offset (16 bits) if there is any non-0 entry) */
/*
* folding value for auxiliary data:
* store the non-zero offset in bits 9..0 (FNC bits)
* if there is any non-0 entry;
* "or" [verb!] together data bits 15..10 of all of the 1024 supplementary code points
*/
static uint32_t U_CALLCONV
getFoldedAuxValue(UNewTrie *trie, UChar32 start, int32_t offset) {
uint32_t value, oredValues;
UChar32 limit;
UBool inBlockZero;
oredValues=0;
limit=start+0x400;
while(start<limit) {
value=utrie_get32(trie, start, &inBlockZero);
if(inBlockZero) {
start+=UTRIE_DATA_BLOCK_LENGTH;
} else {
oredValues|=value;
++start;
}
}
if(oredValues!=0) {
/* move the 10 significant offset bits into bits 9..0 */
offset>>=UTRIE_SURROGATE_BLOCK_BITS;
if(offset>_NORM_AUX_FNC_MASK) {
fprintf(stderr, "gennorm error: folding offset too large (auxTrie)\n");
exit(U_INDEX_OUTOFBOUNDS_ERROR);
}
return (uint32_t)offset|(oredValues&~_NORM_AUX_FNC_MASK);
} else {
return 0;
}
}
extern void
processData() {
#if 0
uint16_t i;
#endif
processCombining();
/* canonically reorder decompositions and assign combining classes for decompositions */
enumTrie(postParseFn, NULL);
#if 0
for(i=1; i<64; ++i) {
if(combineAndQC[i]) {
printf("combiningFlags==0x%02x qcFlags(NF?C)==0x%02x\n", (i&0xc)>>2, i&0x33);
}
}
#endif
/* add hangul/jamo specials */
setHangulJamoSpecials();
/* set this value; will be updated as makeCanonSetFn() adds sets (if there are any, see gStoreFlags) */
canonStartSets[_NORM_SET_INDEX_CANON_SETS_LENGTH]=(uint16_t)canonStartSetsTop;
/* store search tables and USerializedSets for canonical starters (after Hangul/Jamo specials!) */
if(DO_STORE(UGENNORM_STORE_AUX) && DO_STORE(UGENNORM_STORE_COMPOSITION)) {
enumTrie(makeCanonSetFn, NULL);
}
/* clone the normalization builder trie to make the final data tries */
if( NULL==utrie_clone(norm32Trie, normTrie, NULL, 0) ||
NULL==utrie_clone(fcdTrie, normTrie, NULL, 0) ||
NULL==utrie_clone(auxTrie, normTrie, NULL, 0)
) {
fprintf(stderr, "error: unable to clone the normalization trie\n");
exit(U_MEMORY_ALLOCATION_ERROR);
}
/* --- finalize data for quick checks & normalization --- */
/* turn the Norm structs (stage2, norms) into 32-bit data words */
makeAll32();
/* --- finalize data for FCD checks --- */
/* FCD data: take Norm.canonBothCCs and store them in the FCD table */
makeFCD();
/* --- finalize auxiliary normalization data --- */
makeAux();
if(beVerbose) {
#if 0
printf("number of stage 2 entries: %ld\n", stage2Mem->index);
printf("size of stage 1 (BMP) & 2 (uncompacted) + extra data: %ld bytes\n", _NORM_STAGE_1_BMP_COUNT*2+stage2Mem->index*4+extraMem->index*2);
#endif
printf("combining CPs tops: fwd %u both %u back %u\n", combineFwdTop, combineBothTop, combineBackTop);
printf("combining table count: %u\n", combiningTableTop);
}
}
/* is this a norm32 with a special index for a lead surrogate? */
static U_INLINE UBool
isNorm32LeadSurrogate(uint32_t norm32) {
return _NORM_MIN_SPECIAL<=norm32 && norm32<_NORM_SURROGATES_TOP;
}
/* normTrie: 32-bit trie result may contain a special extraData index with the folding offset */
static int32_t U_CALLCONV
getFoldingNormOffset(uint32_t norm32) {
if(isNorm32LeadSurrogate(norm32)) {
return
UTRIE_BMP_INDEX_LENGTH+
(((int32_t)norm32>>(_NORM_EXTRA_SHIFT-UTRIE_SURROGATE_BLOCK_BITS))&
(0x3ff<<UTRIE_SURROGATE_BLOCK_BITS));
} else {
return 0;
}
}
/* auxTrie: the folding offset is in bits 9..0 of the 16-bit trie result */
static int32_t U_CALLCONV
getFoldingAuxOffset(uint32_t data) {
return (int32_t)(data&_NORM_AUX_FNC_MASK)<<UTRIE_SURROGATE_BLOCK_BITS;
}
#endif /* #if !UCONFIG_NO_NORMALIZATION */
static void
writeAllCC(FILE *f) {
uint32_t i;
UChar32 prevCode, code;
uint8_t prevCC, cc;
UBool isInBlockZero;
fprintf(f, "# Canonical_Combining_Class (ccc) values\n");
prevCode=0;
prevCC=0;
#if !UCONFIG_NO_NORMALIZATION
for(code=0; code<=0x110000;) {
if(code==0x110000) {
cc=0;
} else {
i=utrie_get32(normTrie, code, &isInBlockZero);
if(i==0 || isInBlockZero) {
cc=0;
} else {
cc=norms[i].udataCC;
}
}
if(prevCC!=cc) {
if(prevCC!=0) {
uint32_t lastCode=code-1;
if(prevCode==lastCode) {
fprintf(f, "%04lX:%d\n", (long)lastCode, prevCC);
} else {
fprintf(f, "%04lX..%04lX:%d\n",
(long)prevCode, (long)lastCode, prevCC);
}
}
prevCode=code;
prevCC=cc;
}
if(isInBlockZero) {
code+=UTRIE_DATA_BLOCK_LENGTH;
} else {
++code;
}
}
#endif /* UCONFIG_NO_NORMALIZATION */
}
#if !UCONFIG_NO_NORMALIZATION
static UBool
hasMapping(uint32_t code) {
Norm *norm=norms+utrie_get32(normTrie, code, NULL);
return norm->lenNFD!=0 || norm->lenNFKD!=0;
}
static UBool
hasOneWayMapping(uint32_t code, UBool withCompat) {
for(;;) {
Norm *norm=norms+utrie_get32(normTrie, code, NULL);
uint8_t length;
if((length=norm->lenNFD)!=0) {
/*
* The canonical decomposition is a one-way mapping if
* - it does not map to exactly two code points
* - the code has ccc!=0
* - the code has the Composition_Exclusion property
* - its starter has a one-way mapping (loop for this)
* - its non-starter decomposes
*/
if( length!=2 ||
norm->udataCC!=0 ||
norm->combiningFlags&0x80 ||
hasMapping(norm->nfd[1])
) {
return TRUE;
}
code=norm->nfd[0]; /* continue */
} else if(withCompat && norm->lenNFKD!=0) {
return TRUE;
} else {
return FALSE;
}
}
}
#endif /* !UCONFIG_NO_NORMALIZATION */
static void
writeAllMappings(FILE *f, UBool withCompat) {
uint32_t i, code;
UBool isInBlockZero;
if(withCompat) {
fprintf(f, "\n# Canonical and compatibility decomposition mappings\n");
} else {
fprintf(f, "\n# Canonical decomposition mappings\n");
}
#if !UCONFIG_NO_NORMALIZATION
for(code=0; code<=0x10ffff;) {
i=utrie_get32(normTrie, code, &isInBlockZero);
if(isInBlockZero) {
code+=UTRIE_DATA_BLOCK_LENGTH;
} else {
if(i!=0) {
uint32_t *s32;
uint8_t length;
char separator;
if((length=norms[i].lenNFD)!=0) {
s32=norms[i].nfd;
separator= hasOneWayMapping(code, withCompat) ? '>' : '=';
} else if(withCompat && (length=norms[i].lenNFKD)!=0) {
s32=norms[i].nfkd;
separator='>';
}
if(length!=0) {
uint8_t j;
fprintf(f, "%04lX%c", (long)code, separator);
for(j=0; j<length; ++j) {
if(j!=0) {
fputc(' ', f);
}
fprintf(f, "%04lX", (long)s32[j]);
}
fputc('\n', f);
}
}
++code;
}
}
#endif /* !UCONFIG_NO_NORMALIZATION */
}
static void
writeNorm2TextFile(const char *path, const char *filename, UBool withCompat) {
FILE *f=usrc_createTextData(path, filename);
if(f==NULL) {
exit(U_FILE_ACCESS_ERROR);
}
writeAllCC(f);
writeAllMappings(f, withCompat);
fclose(f);
}
extern void
writeNorm2(const char *dataDir) {
writeNorm2TextFile(dataDir, "nfc.txt", FALSE);
writeNorm2TextFile(dataDir, "nfkc.txt", TRUE);
}
extern void
generateData(const char *dataDir, UBool csource) {
static uint8_t normTrieBlock[100000], fcdTrieBlock[100000], auxTrieBlock[100000];
UNewDataMemory *pData;
UErrorCode errorCode=U_ZERO_ERROR;
int32_t size, dataLength;
#if UCONFIG_NO_NORMALIZATION
size=0;
#else
U_STRING_DECL(nxCJKCompatPattern, "[:Ideographic:]", 15);
U_STRING_DECL(nxUnicode32Pattern, "[:^Age=3.2:]", 12);
USet *set;
int32_t normTrieSize, fcdTrieSize, auxTrieSize;
normTrieSize=utrie_serialize(norm32Trie, normTrieBlock, sizeof(normTrieBlock), getFoldedNormValue, FALSE, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: utrie_serialize(normalization properties) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
if(DO_STORE(UGENNORM_STORE_FCD)) {
fcdTrieSize=utrie_serialize(fcdTrie, fcdTrieBlock, sizeof(fcdTrieBlock), NULL, TRUE, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: utrie_serialize(FCD data) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
} else {
fcdTrieSize=0;
}
if(DO_STORE(UGENNORM_STORE_AUX)) {
auxTrieSize=utrie_serialize(auxTrie, auxTrieBlock, sizeof(auxTrieBlock), getFoldedAuxValue, TRUE, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: utrie_serialize(auxiliary data) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
} else {
auxTrieSize=0;
}
/* move the parts of canonStartSets[] together into a contiguous block */
if( canonStartSetsTop<_NORM_MAX_CANON_SETS &&
canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH]!=0
) {
uprv_memmove(canonStartSets+canonStartSetsTop,
canonStartSets+_NORM_MAX_CANON_SETS,
canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH]*2);
}
canonStartSetsTop+=canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH];
if( canonStartSetsTop<(_NORM_MAX_CANON_SETS+_NORM_MAX_SET_SEARCH_TABLE_LENGTH) &&
canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH]!=0
) {
uprv_memmove(canonStartSets+canonStartSetsTop,
canonStartSets+_NORM_MAX_CANON_SETS+_NORM_MAX_SET_SEARCH_TABLE_LENGTH,
canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH]*2);
}
canonStartSetsTop+=canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH];
/* create the normalization exclusion sets */
/*
* nxCJKCompatPattern should be [[:Ideographic:]&[:NFD_QC=No:]]
* but we cannot use NFD_QC from the pattern because that would require
* unorm.icu which we are just going to generate.
* Therefore we have manually collected nfdQCNoSet and intersect Ideographic
* with that.
*/
U_STRING_INIT(nxCJKCompatPattern, "[:Ideographic:]", 15);
U_STRING_INIT(nxUnicode32Pattern, "[:^Age=3.2:]", 12);
canonStartSets[_NORM_SET_INDEX_NX_CJK_COMPAT_OFFSET]=canonStartSetsTop;
set=uset_openPattern(nxCJKCompatPattern, -1, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: uset_openPattern([:Ideographic:]&[:NFD_QC=No:]) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
uset_retainAll(set, nfdQCNoSet);
if(DO_NOT_STORE(UGENNORM_STORE_EXCLUSIONS)) {
uset_clear(set);
}
canonStartSetsTop+=uset_serialize(set, canonStartSets+canonStartSetsTop, LENGTHOF(canonStartSets)-canonStartSetsTop, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: uset_serialize([:Ideographic:]&[:NFD_QC=No:]) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
uset_close(set);
canonStartSets[_NORM_SET_INDEX_NX_UNICODE32_OFFSET]=canonStartSetsTop;
set=uset_openPattern(nxUnicode32Pattern, -1, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: uset_openPattern([:^Age=3.2:]) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
if(DO_NOT_STORE(UGENNORM_STORE_EXCLUSIONS)) {
uset_clear(set);
}
canonStartSetsTop+=uset_serialize(set, canonStartSets+canonStartSetsTop, LENGTHOF(canonStartSets)-canonStartSetsTop, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "error: uset_serialize([:^Age=3.2:]) failed, %s\n", u_errorName(errorCode));
exit(errorCode);
}
uset_close(set);
canonStartSets[_NORM_SET_INDEX_NX_RESERVED_OFFSET]=canonStartSetsTop;
/* make sure that the FCD trie is 4-aligned */
if((utm_countItems(extraMem)+combiningTableTop)&1) {
combiningTable[combiningTableTop++]=0x1234; /* add one 16-bit word for an even number */
}
/* pad canonStartSets to 4-alignment, too */
if(canonStartSetsTop&1) {
canonStartSets[canonStartSetsTop++]=0x1235;
}
size=
_NORM_INDEX_TOP*4+
normTrieSize+
utm_countItems(extraMem)*2+
combiningTableTop*2+
fcdTrieSize+
auxTrieSize+
canonStartSetsTop*2;
if(beVerbose) {
printf("size of normalization trie %5u bytes\n", (int)normTrieSize);
printf("size of 16-bit extra memory %5u UChars/uint16_t\n", (int)utm_countItems(extraMem));
printf(" of that: FC_NFKC_Closure size %5u UChars/uint16_t\n", ((uint16_t *)utm_getStart(extraMem))[0]);
printf("size of combining table %5u uint16_t\n", combiningTableTop);
printf("size of FCD trie %5u bytes\n", (int)fcdTrieSize);
printf("size of auxiliary trie %5u bytes\n", (int)auxTrieSize);
printf("size of canonStartSets[] %5u uint16_t\n", (int)canonStartSetsTop);
printf(" number of indexes %5u uint16_t\n", _NORM_SET_INDEX_TOP);
printf(" size of sets %5u uint16_t\n", canonStartSets[_NORM_SET_INDEX_CANON_SETS_LENGTH]-_NORM_SET_INDEX_TOP);
printf(" number of sets %5d\n", (int)canonSetsCount);
printf(" size of BMP search table %5u uint16_t\n", canonStartSets[_NORM_SET_INDEX_CANON_BMP_TABLE_LENGTH]);
printf(" size of supplementary search table %5u uint16_t\n", canonStartSets[_NORM_SET_INDEX_CANON_SUPP_TABLE_LENGTH]);
printf(" length of exclusion sets %5u uint16_t\n", canonStartSets[_NORM_SET_INDEX_NX_RESERVED_OFFSET]-canonStartSets[_NORM_SET_INDEX_NX_CJK_COMPAT_OFFSET]);
printf("size of " U_ICUDATA_NAME "_" DATA_NAME "." DATA_TYPE " contents: %ld bytes\n", (long)size);
}
indexes[_NORM_INDEX_TRIE_SIZE]=normTrieSize;
indexes[_NORM_INDEX_UCHAR_COUNT]=(uint16_t)utm_countItems(extraMem);
indexes[_NORM_INDEX_COMBINE_DATA_COUNT]=combiningTableTop;
indexes[_NORM_INDEX_COMBINE_FWD_COUNT]=combineFwdTop;
indexes[_NORM_INDEX_COMBINE_BOTH_COUNT]=(uint16_t)(combineBothTop-combineFwdTop);
indexes[_NORM_INDEX_COMBINE_BACK_COUNT]=(uint16_t)(combineBackTop-combineBothTop);
/* the quick check minimum code points are already set */
indexes[_NORM_INDEX_FCD_TRIE_SIZE]=fcdTrieSize;
indexes[_NORM_INDEX_AUX_TRIE_SIZE]=auxTrieSize;
indexes[_NORM_INDEX_CANON_SET_COUNT]=canonStartSetsTop;
#endif
if(csource) {
#if UCONFIG_NO_NORMALIZATION
/* no csource for dummy mode..? */
fprintf(stderr, "gennorm error: UCONFIG_NO_NORMALIZATION is on in csource mode.\n");
exit(1);
#else
/* write .c file for hardcoded data */
UTrie normRuntimeTrie={ NULL }, fcdRuntimeTrie={ NULL }, auxRuntimeTrie={ NULL };
UTrie2 *normRuntimeTrie2, *fcdRuntimeTrie2=NULL, *auxRuntimeTrie2=NULL;
FILE *f;
utrie_unserialize(&normRuntimeTrie, normTrieBlock, normTrieSize, &errorCode);
normRuntimeTrie.getFoldingOffset=getFoldingNormOffset;
if(fcdTrieSize>0) {
utrie_unserialize(&fcdRuntimeTrie, fcdTrieBlock, fcdTrieSize, &errorCode);
}
if(auxTrieSize>0) {
utrie_unserialize(&auxRuntimeTrie, auxTrieBlock, auxTrieSize, &errorCode);
auxRuntimeTrie.getFoldingOffset=getFoldingAuxOffset;
}
if(U_FAILURE(errorCode)) {
fprintf(
stderr,
"gennorm error: failed to utrie_unserialize() one of the tries - %s\n",
u_errorName(errorCode));
exit(errorCode);
}
/* use UTrie2 */
normRuntimeTrie2=utrie2_fromUTrie(&normRuntimeTrie, 0, &errorCode);
if(fcdTrieSize>0) {
fcdRuntimeTrie2=utrie2_fromUTrie(&fcdRuntimeTrie, 0, &errorCode);
}
if(auxTrieSize>0) {
auxRuntimeTrie2=utrie2_fromUTrie(&auxRuntimeTrie, 0, &errorCode);
}
if(U_FAILURE(errorCode)) {
fprintf(
stderr,
"gennorm error: utrie2_fromUTrie() failed - %s\n",
u_errorName(errorCode));
exit(errorCode);
}
if(auxTrieSize>0) {
/* delete lead surrogate code unit values */
UChar lead;
auxRuntimeTrie2=utrie2_cloneAsThawed(auxRuntimeTrie2, &errorCode);
for(lead=0xd800; lead<0xdc00; ++lead) {
utrie2_set32ForLeadSurrogateCodeUnit(auxRuntimeTrie2, lead, auxRuntimeTrie2->initialValue, &errorCode);
}
utrie2_freeze(auxRuntimeTrie2, UTRIE2_16_VALUE_BITS, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(
stderr,
"gennorm error: deleting lead surrogate code unit values failed - %s\n",
u_errorName(errorCode));
exit(errorCode);
}
}
f=usrc_create(dataDir, "unorm_props_data.c");
if(f!=NULL) {
/* unused
usrc_writeArray(f,
"static const UVersionInfo formatVersion={ ",
dataInfo.formatVersion, 8, 4,
" };\n\n");
*/
usrc_writeArray(f,
"static const UVersionInfo dataVersion={ ",
dataInfo.dataVersion, 8, 4,
" };\n\n");
usrc_writeArray(f,
"static const int32_t indexes[_NORM_INDEX_TOP]={\n",
indexes, 32, _NORM_INDEX_TOP,
"\n};\n\n");
usrc_writeUTrie2Arrays(f,
"static const uint16_t normTrie_index[%ld]={\n",
"static const uint32_t normTrie_data32[%ld]={\n",
normRuntimeTrie2,
"\n};\n\n");
usrc_writeUTrie2Struct(f,
"static const UTrie2 normTrie={\n",
normRuntimeTrie2, "normTrie_index", "normTrie_data32",
"};\n\n");
usrc_writeArray(f,
"static const uint16_t extraData[%ld]={\n",
utm_getStart(extraMem), 16, utm_countItems(extraMem),
"\n};\n\n");
usrc_writeArray(f,
"static const uint16_t combiningTable[%ld]={\n",
combiningTable, 16, combiningTableTop,
"\n};\n\n");
if(fcdTrieSize>0) {
usrc_writeUTrie2Arrays(f,
"static const uint16_t fcdTrie_index[%ld]={\n", NULL,
fcdRuntimeTrie2,
"\n};\n\n");
usrc_writeUTrie2Struct(f,
"static const UTrie2 fcdTrie={\n",
fcdRuntimeTrie2, "fcdTrie_index", NULL,
"};\n\n");
} else {
fputs( "static const UTrie2 fcdTrie={ NULL };\n\n", f);
}
if(auxTrieSize>0) {
usrc_writeUTrie2Arrays(f,
"static const uint16_t auxTrie_index[%ld]={\n", NULL,
auxRuntimeTrie2,
"\n};\n\n");
usrc_writeUTrie2Struct(f,
"static const UTrie2 auxTrie={\n",
auxRuntimeTrie2, "auxTrie_index", NULL,
"};\n\n");
} else {
fputs( "static const UTrie2 auxTrie={ NULL };\n\n", f);
}
usrc_writeArray(f,
"static const uint16_t canonStartSets[%ld]={\n",
canonStartSets, 16, canonStartSetsTop,
"\n};\n\n");
fclose(f);
}
utrie2_close(normRuntimeTrie2);
utrie2_close(fcdRuntimeTrie2);
utrie2_close(auxRuntimeTrie2);
#endif
} else {
/* write the data */
pData=udata_create(dataDir, DATA_TYPE, DATA_NAME, &dataInfo,
haveCopyright ? U_COPYRIGHT_STRING : NULL, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "gennorm: unable to create the output file, error %d\n", errorCode);
exit(errorCode);
}
#if !UCONFIG_NO_NORMALIZATION
udata_writeBlock(pData, indexes, sizeof(indexes));
udata_writeBlock(pData, normTrieBlock, normTrieSize);
udata_writeBlock(pData, utm_getStart(extraMem), utm_countItems(extraMem)*2);
udata_writeBlock(pData, combiningTable, combiningTableTop*2);
udata_writeBlock(pData, fcdTrieBlock, fcdTrieSize);
udata_writeBlock(pData, auxTrieBlock, auxTrieSize);
udata_writeBlock(pData, canonStartSets, canonStartSetsTop*2);
#endif
/* finish up */
dataLength=udata_finish(pData, &errorCode);
if(U_FAILURE(errorCode)) {
fprintf(stderr, "gennorm: error %d writing the output file\n", errorCode);
exit(errorCode);
}
if(dataLength!=size) {
fprintf(stderr, "gennorm error: data length %ld != calculated size %ld\n",
(long)dataLength, (long)size);
exit(U_INTERNAL_PROGRAM_ERROR);
}
}
}
#if !UCONFIG_NO_NORMALIZATION
extern void
cleanUpData(void) {
int32_t i, count;
count=utm_countItems(normMem);
for(i=0; i<count; ++i) {
uset_close(norms[i].canonStart);
}
utm_close(normMem);
utm_close(utf32Mem);
utm_close(extraMem);
utm_close(combiningTriplesMem);
utrie_close(normTrie);
utrie_close(norm32Trie);
utrie_close(fcdTrie);
utrie_close(auxTrie);
uset_close(nfdQCNoSet);
uprv_free(normTrie);
uprv_free(norm32Trie);
uprv_free(fcdTrie);
uprv_free(auxTrie);
}
#endif /* #if !UCONFIG_NO_NORMALIZATION */
/*
* Hey, Emacs, please set the following:
*
* Local Variables:
* indent-tabs-mode: nil
* End:
*
*/
| [
"mishonok@251d0590-4201-4cf1-90de-194747b24ca1"
] | mishonok@251d0590-4201-4cf1-90de-194747b24ca1 |
a926a07ba4801a3f103d1690a857a151f2886e3e | b338c820570064317e21a648ba2e5608474cb248 | /MPC_Code/Core7/app/MPC_LATENCY/LED_GREEN/src_5/cpu_5.c | 2b125c9232bcb8b774e05b424ce8c3e41ebc29f0 | [] | no_license | PallAxelSigurdsson/MPC-Platform | 39580574288625e08407e6b8414bff2dd15e9f97 | dfa3888657dae50a709c2aaefc60b946d80eae21 | refs/heads/main | 2023-06-21T14:35:01.251394 | 2021-07-22T15:23:39 | 2021-07-22T15:23:39 | 379,680,374 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 11,595 | c | /* DESCRIPTION:
* This code measures and reports the latencies of all functions
* relating to the green LED peripheral.
*/
#include "system.h"
#include "MPC.h" // The library holding all MPC OS commands.
#include "INFO.h" // Information about the whole multicore system (central system.h)
#include <sys/alt_irq.h>
#include "altera_avalon_timer_regs.h"
#include "altera_avalon_performance_counter.h"
alt_u8 COUNTER8 = 0;
alt_u32 INDEX = 0;
alt_u32 TIMER = 0;
alt_u32 ITERATIONS = 10000;
alt_u32 TIMER_MIN = 1000000;
alt_u32 TIMER_MAX = 0;
alt_u32 MEASURED_MIN = 1000000;
alt_u32 MEASURED_MAX = 0;
alt_u32 PERF_OVERHEAD = 16;
int main()
{
printf("\033c");
printf("CORE %u\n",CPU_5);
MPC_initialize_fifos(CPU_5, 12, 1);
MPC_receive_from_CPU(CPU_4, CPU_5);
printf("\n\n-------- WRITE SINGLE GREEN LED --------\n\n");
printf("\nWrite Single Green LED - Immediate\n\n");
alt_irq_context CONTEXT;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(0);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 0 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 0 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(1);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 1 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 1 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(2);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 2 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 2 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(3);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 3 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 3 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(4);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 4 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 4 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(5);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 5 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 5 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(6);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 6 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 6 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(7);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 7 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 7 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
printf("\nWRITE GREEN LED MIN: %u\n",MEASURED_MIN);
printf("WRITE GREEN LED MAX: %u\n",MEASURED_MAX);
MEASURED_MIN = 1000000;
MEASURED_MAX = 0;
printf("\nWrite Single Green LED - alt_u8\n\n");
for(COUNTER8 = 0; COUNTER8 < 8; COUNTER8++){
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_single_green_LED(COUNTER8);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED %u MIN: %u\n",COUNTER8,TIMER_MIN);
printf("WRITE GREEN LED %u MAX: %u\n",COUNTER8,TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
}
printf("\nWRITE GREEN LED MIN: %u\n",MEASURED_MIN);
printf("WRITE GREEN LED MAX: %u\n",MEASURED_MAX);
MEASURED_MIN = 1000000;
MEASURED_MAX = 0;
//NEXT TEST
printf("\n\n-------- WRITE MASK GREEN LED --------\n\n");
printf("\nWrite Mask Green LED - Immediate\n\n");
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_mask_green_LED(0xFF);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("WRITE GREEN LED 0 MIN: %u\n",TIMER_MIN);
printf("WRITE GREEN LED 0 MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
printf("\nWrite Mask Green LED - alt_u8\n\n");
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_write_mask_green_LED(COUNTER8);
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
alt_irq_enable_all(CONTEXT);
printf("WRITE MASK GREEN LED MIN: %u\n",TIMER_MIN);
printf("WRITE MASK GREEN LED MAX: %u\n",TIMER_MAX);
TIMER_MIN = 1000000;
TIMER_MAX = 0;
//NEXT TEST
printf("\n\n-------- RESET GREEN LED --------\n\n");
printf("\nReset Green LED - No Argument\n\n");
CONTEXT = alt_irq_disable_all();
for(INDEX = 0; INDEX < ITERATIONS; INDEX++){
PERF_RESET(PERFORMANCE_COUNTER_5_BASE);
PERF_START_MEASURING(PERFORMANCE_COUNTER_5_BASE);
PERF_BEGIN(PERFORMANCE_COUNTER_5_BASE,1);
MPC_reset_green_leds();
PERF_END(PERFORMANCE_COUNTER_5_BASE,1);
PERF_STOP_MEASURING(PERFORMANCE_COUNTER_5_BASE);
TIMER = perf_get_section_time(PERFORMANCE_COUNTER_5_BASE, 1)-PERF_OVERHEAD;
if(TIMER < TIMER_MIN){
TIMER_MIN = TIMER;
}
if(TIMER > TIMER_MAX){
TIMER_MAX = TIMER;
}
}
if(TIMER_MIN < MEASURED_MIN){
MEASURED_MIN = TIMER_MIN;
}
if(TIMER_MAX > MEASURED_MAX){
MEASURED_MAX = TIMER_MAX;
}
alt_irq_enable_all(CONTEXT);
printf("RESET GREEN LED 0 MIN: %u\n",TIMER_MIN);
printf("RESET GREEN LED 0 MAX: %u\n",TIMER_MAX);
MPC_send_to_CPU(CPU_5, CPU_6 , 10);
return 0;
}
| [
"pas17@hi.is"
] | pas17@hi.is |
75a068aa58a3ef475775c6f87473af013fcbe347 | 52263c795ed5b18f235347509839d66d2f015ff3 | /lexer.c | fec078a380af9f27120d39783dc7ba8ed3c1dc2c | [] | no_license | Schamnad/CS-F342-Compilers | c213fa0af7a8ee9c75d6c693ee411b8c79d8b147 | 800d4f017a784474d39e0e2d138b355a95079d7d | refs/heads/master | 2021-01-10T15:34:26.444017 | 2016-03-19T12:29:08 | 2016-03-19T12:29:57 | 54,264,031 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,767 | c | /*
COMPILER PROJECT-2015
Batch Number: 11
2011B2A7744P Sanjeed Schamnad
2011A7PS479P Shiva Manne
*/
#include<stdio.h>
#include<string.h>
#include<stdlib.h>
#if ! defined _l_H
#define _l_H 1
#include"lexer.h"
#endif
int DFA_table[STATE_SIZE][ALPHABET_SIZE];
terminal *FINAL[STATE_SIZE];
char temp_val[MAXSTRLEN]; //STORING THE LEXEME
int LINE_NUMBER=0;
// Lexical Analysis Variables
char PREVLOOKAHEAD='\0';
char mainBuffer[BUFFER_SIZE];
int BUFFER_POS=0;
int moreBuffer=0;
int PRESENT_STATE=0;
int LOOKAHEAD_INDEX=0;
int REPEAT_COUNTER_FUNID=0,REPEAT_COUNTER_ID=0;
int ERROR_NUMBER=0;
int val_pos=0;
BOOLEAN readMore=1;
BOOLEAN FINAL_STATE=false;
// end
void init()
{
int i=0, j=0;
for(i=0;i<STATE_SIZE;i++)
{
for(j=0; j<ALPHABET_SIZE; j++)
{
DFA_table[i][j]=-1;
}
FINAL[i]=NULL;
}
}
int getIndex(char ch)
{
if(ch<='9' && ch>='0')
return ch-'0';
else if(ch>='A' && ch<='Z')
return ch-'A'+10;
else if(ch>='a' && ch<='z')
return ch-'a'+10+26;
else if(ch==' ' || ch== '\n' || ch== '\t')
return 62;
else if(ch=='!')
return 63;
else if(ch=='#')
return 64;
else if(ch=='&')
return 65;
else if(ch>='(' && ch<='/')
return ch-'('+10+26+26+4;
else if(ch>=':' && ch <='>')
return ch-':'+10+26+26+4+8;
else if(ch=='@')
return 79;
else if(ch=='[')
return 80;
else if(ch==']')
return 81;
else if(ch=='_')
return 82;
else if(ch=='~')
return 83;
else if(ch=='%')
return 84;
else
return -1;
}
int populate_DFA_table(FILE *dfaFile)
{
init();
int stateNum=0, i=0, transNum=0;
fscanf(dfaFile, "%d", &stateNum);
int stateCount=stateNum;
int startIndex=-1, endIndex=-1,finalState=-1, presentState=-1;
char inputChar;
char temp;
int terminalNum=-1;
while(stateNum--)
{
fscanf(dfaFile, "%d", &presentState);
if(presentState==-1)
{
fscanf(dfaFile, "%c", &temp);
continue;
}
fscanf(dfaFile, "%d", &transNum);
if(transNum!=-1)
{
while(transNum--)
{
fscanf(dfaFile, "\n%c ", &inputChar);
fscanf(dfaFile, "%d", &finalState);
if(inputChar=='?') //ALL ALPHABETS
{
startIndex = getIndex('A');
endIndex = getIndex('z');
}
else if(inputChar == '|') //NUMBERS
{
startIndex= getIndex('0'); //moreBuffer= BUFFER_POS;
endIndex = getIndex('9');
}
else if(inputChar == '$') //SYMBOLS
{
startIndex=getIndex(' ');
endIndex= getIndex('~');
}
else if(inputChar == '"') //WHITESPACE
{
startIndex=getIndex(' ');
endIndex= getIndex(' ');
}
else if(inputChar == '^') //a-z
{
startIndex=getIndex('a');
endIndex= getIndex('z');
}
else if(inputChar == 125)// ALL CHAR // 125 = ascii(})
{
startIndex=getIndex('0');
endIndex= getIndex('~');
}
else
{
startIndex = endIndex = getIndex(inputChar);
}
for(i=startIndex; i<=endIndex; i++)
{
if(i!=-1)
{
DFA_table[presentState][i]=finalState;
}
else
{
printf("\nERROR: UNKNOWN SYMBOL: %c\n in DFA file\n", inputChar);
exit(0);
}
}
}
}
else //for final states
{
FINAL[presentState]=(terminal*)malloc(sizeof(terminal));
fscanf(dfaFile, "%d", &terminalNum);
*FINAL[presentState]=terminalNum;
}
}
/* for(i=0; i<=STATE_SIZE; i++)*/
/* {*/
/* if(FINAL[i]!=NULL)*/
/* //if(*FINAL[i]==true)*/
/* printf("%d\n",i);*/
/* }*/
}
tokenInfo getNextToken()
{
char lookahead;
int table_val, index1;
int cpy1=0;
tokenInfo Next_token;
readMore=0;
FINAL_STATE=false;
while( mainBuffer[BUFFER_POS]!='\0' )
{
if(moreBuffer == BUFFER_SIZE-2 && PREVLOOKAHEAD!=' ' && PREVLOOKAHEAD!='\n')
{
lookahead=PREVLOOKAHEAD;
BUFFER_POS--;
moreBuffer=0;
}
else
lookahead=mainBuffer[BUFFER_POS];
index1=getIndex(lookahead);
if(index1!=-1)
table_val=DFA_table[PRESENT_STATE][index1];
else
table_val=-1;
if(table_val!=-1)
{
PRESENT_STATE=table_val;
if(PRESENT_STATE==26 || PRESENT_STATE==25)
{
REPEAT_COUNTER_FUNID=0;
REPEAT_COUNTER_ID++;
if(REPEAT_COUNTER_ID<4)
REPEAT_COUNTER_ID=strlen(temp_val);
if(REPEAT_COUNTER_ID>21)
{
PRESENT_STATE=ERROR_STATE;
ERROR_NUMBER=5;
}
}
else if (PRESENT_STATE==17)
{
REPEAT_COUNTER_ID=0;
if(REPEAT_COUNTER_FUNID<6)
REPEAT_COUNTER_FUNID=strlen(temp_val);
REPEAT_COUNTER_FUNID++;
if(REPEAT_COUNTER_FUNID>30)
{
PRESENT_STATE=ERROR_STATE;
ERROR_NUMBER=6;
}
}
else{
REPEAT_COUNTER_ID=0;
REPEAT_COUNTER_FUNID=0;
}
}
else
{
PRESENT_STATE=ERROR_STATE;
temp_val[val_pos]='\0';
if(index1==-1)ERROR_NUMBER=2;
else
ERROR_NUMBER=3;
}
int *ret;
if(FINAL[PRESENT_STATE] != NULL)
{
temp_val[val_pos]='\0';
if(ERROR_NUMBER==5)
{
printf("ERROR_1: Length of Identifier %s at line %d is too long\n", temp_val, LINE_NUMBER+1);
ERROR_NUMBER=0;
}
else if(ERROR_NUMBER==6)
{
printf("ERROR_1: Length of Functional Identifier %s at line %d is too long\n", temp_val, LINE_NUMBER+1);
ERROR_NUMBER=0;
}
else if(ERROR_NUMBER==2)
{
printf("ERROR_2: Unknown Symbol %s at line %d\n", temp_val, LINE_NUMBER+1);
ERROR_NUMBER=0;
}
else if(ERROR_NUMBER==3)
{
printf("ERROR_3: Unknown pattern %s at line %d\n", temp_val, LINE_NUMBER+1);
ERROR_NUMBER=0;
}
moreBuffer= BUFFER_POS;
Next_token.name = *(FINAL[PRESENT_STATE]);
strcpy(Next_token.value, temp_val);
Next_token.index=-1;
Next_token.lineNumber=LINE_NUMBER+1;
val_pos=0;
int loop_k=0;
for(loop_k=0; loop_k<MAXSTRLEN; loop_k++)
temp_val[loop_k]='\0';
FINAL_STATE=true;
PRESENT_STATE=0;
if(moreBuffer== BUFFER_SIZE-2)
PREVLOOKAHEAD=lookahead;
return Next_token;
}
else
if(lookahead=='\n' && PREVLOOKAHEAD!='\n')
LINE_NUMBER++;
if( getIndex(lookahead)!=62 )
temp_val[val_pos++]=lookahead;
BUFFER_POS++;
FINAL_STATE=false;
}
readMore=1;
}
tokenInfo getStream(FILE *instream)
{
int res1=-1;
int begin=0;
tokenInfo next_token_read, prev_token_read;
if(readMore==1)
{
res1=fread(mainBuffer, 1, BUFFER_SIZE-1, instream);
mainBuffer[res1]='\0';
}
while(res1!=0)
{
prev_token_read = next_token_read;
next_token_read = getNextToken();
if(next_token_read.index==-9)
return next_token_read;
if(BUFFER_POS==BUFFER_SIZE-2 || readMore==1)
{
res1=fread(mainBuffer, 1, BUFFER_SIZE-1, instream);
BUFFER_POS=0;
readMore=0;
mainBuffer[res1]='\0';
}
next_token_read.index=-1;
if(FINAL_STATE==true)
return next_token_read;
}
terminal last=$;
tokenInfo last1;
last1.index=-1;
last1.name=last;
strcpy(last1.value,"$");
// fprintf(token_stream, "%d\n", last);
// fclose(token_stream);
printf("\n");
return last1;
}
void removeComments(char * filename)
{
char * cleaned_file,newFile[10000];
char str[200];
FILE* fp=fopen(filename,"r");
if(!fp) return (void)NULL;
while(fgets(str,sizeof(str),fp) != NULL)
{
strcat(newFile,str);
}
FILE *comments_rem=fopen("noComments.txt", "w");
int i=0, j=0, flag=0;
int *ret=0;
cleaned_file=(char*)malloc(sizeof(char));
while(i<strlen(newFile))
{
if(flag==0)
{
if(newFile[i] =='%')
{
flag=1;
i++;
continue;
}
else
{
ret=realloc(cleaned_file, (j+1)*sizeof(char));
cleaned_file[j++]=newFile[i];
i++;
}
}
else
{
if(newFile[i] =='\n')
{
ret=realloc(cleaned_file, (j+1)*sizeof(char));
cleaned_file[j++]='\n';
flag=0;
i++;
}
else
i++;
}
}
ret=realloc(cleaned_file, (j+1)*sizeof(char));
cleaned_file[j]='\0';
fprintf(comments_rem, "%s\n\n", cleaned_file);
fclose(comments_rem);
}
| [
"sanjeed063@gmail.com"
] | sanjeed063@gmail.com |
27483e95e33a7a0a65d86e3ddd64b89c65bebd6a | 07dd5c7172837398c88a0ff134c446a7dda942ab | /src/fvDVM/fvDVM/fvDVM.C | 081c0cda5723845288dabbe50f5e46c07380c4fc | [
"MIT"
] | permissive | tcfdwqq/dugksFoam | 3e5c0bb92023530c06d72a55801f72bb2f983805 | 2c8be0649482c50900729a51540d66ca27c4668f | refs/heads/master | 2020-03-16T21:38:18.644267 | 2017-05-21T09:03:17 | 2017-05-21T09:03:17 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 36,219 | c | /*---------------------------------------------------------------------------*\
========= |
\\ / F ield | OpenFOAM: The Open Source CFD Toolbox
\\ / O peration |
\\ / A nd | Copyright (C) 2011-2013 OpenFOAM Foundation
\\/ M anipulation |
-------------------------------------------------------------------------------
License
This file is part of OpenFOAM.
OpenFOAM is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
OpenFOAM is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with OpenFOAM. If not, see <http://www.gnu.org/licenses/>.
\*---------------------------------------------------------------------------*/
#include <mpi.h>
#include "fvDVM.H"
#include "constants.H"
#include "fvm.H"
#include "calculatedMaxwellFvPatchField.H"
#include "symmetryModFvPatchField.H"
#include "pressureInFvPatchField.H"
#include "pressureOutFvPatchField.H"
#include "scalarIOList.H"
#include "fieldMPIreducer.H"
using namespace Foam::constant;
using namespace Foam::constant::mathematical;
// * * * * * * * * * * * * * * Static Data Members * * * * * * * * * * * * * //
namespace Foam
{
defineTypeNameAndDebug(fvDVM, 0);
}
// * * * * * * * * * * * * * Private Member Functions * * * * * * * * * * * //
void Foam::fvDVM::setDVgrid
(
scalarField& weights,
scalarField& Xis,
scalar xiMin,
scalar xiMax,
label nXi
)
{
// Read from file ./constant/Xis and ./constant/weights
scalarIOList xiList
(
IOobject
(
"Xis",
time_.time().constant(),
mesh_,
IOobject::MUST_READ,
IOobject::NO_WRITE
)
);
scalarIOList weightList
(
IOobject
(
"weights",
time_.time().constant(),
mesh_,
IOobject::MUST_READ,
IOobject::NO_WRITE
)
);
// Check
if (
xiList.size() != nXi
|| weightList.size() != nXi
)
{
WarningIn("setDVgrid")
<< "Num of discreteVelocity not consistent" << endl;
std::exit(-1);
}
if (
xiList[0] != xiMin
|| xiList[nXi-1] != xiMax)
{
WarningIn("setDVgrid")
<< "xi not consistant" <<endl;
std::exit(-1);
}
for (label i = 0; i < nXi ; i++)
{
weights[i] = weightList[i];
Xis[i] = xiList[i];
}
}
void Foam::fvDVM::initialiseDV()
{
scalarField weights1D(nXiPerDim_);
scalarField Xis(nXiPerDim_);
//get discrete velocity points and weights
setDVgrid
(
weights1D,
Xis,
xiMin_.value(),
xiMax_.value(),
nXiPerDim_
);
scalarField weightsGlobal;
vectorField XisGlobal;
labelField symmXtgID;
labelField symmYtgID;
labelField symmZtgID;
if (mesh_.nSolutionD() == 3) //3D(X & Y & Z)
{
nXiX_ = nXiY_ = nXiZ_ = nXiPerDim_;
nXi_ = nXiX_*nXiY_*nXiZ_;
weightsGlobal.setSize(nXi_);
XisGlobal.setSize(nXi_);
symmXtgID.setSize(nXi_);
symmYtgID.setSize(nXi_);
symmZtgID.setSize(nXi_);
label i = 0;
for (label iz = 0; iz < nXiZ_; iz++)
{
for (label iy = 0; iy < nXiY_; iy++)
{
for (label ix = 0; ix < nXiZ_; ix++)
{
scalar weight = weights1D[iz]*weights1D[iy]*weights1D[ix];
vector xi(Xis[ix], Xis[iy], Xis[iz]);
weightsGlobal[i] = weight;
XisGlobal[i] = xi;
symmXtgID[i] = iz*nXiY_*nXiX_ + iy*nXiX_ + (nXiX_ - ix -1);
symmYtgID[i] = iz*nXiY_*nXiX_ + (nXiY_ - iy - 1)*nXiX_ + ix;
symmZtgID[i] = (nXiZ_ - iz -1)*nXiY_*nXiX_ + iy*nXiX_ + ix;
i++;
}
}
}
}
else
{
if (mesh_.nSolutionD() == 2) //2D (X & Y)
{
nXiX_ = nXiY_ = nXiPerDim_;
nXiZ_ = 1;
nXi_ = nXiX_*nXiY_*nXiZ_;
weightsGlobal.setSize(nXi_);
XisGlobal.setSize(nXi_);
symmXtgID.setSize(nXi_);
symmYtgID.setSize(nXi_);
symmZtgID.setSize(nXi_);
label i = 0;
for (label iy = 0; iy < nXiY_; iy++)
{
for (label ix = 0; ix < nXiX_; ix++)
{
scalar weight = weights1D[iy]*weights1D[ix]*1;
vector xi(Xis[ix], Xis[iy], 0.0);
weightsGlobal[i] = weight;
XisGlobal[i] = xi;
symmXtgID[i] = iy*nXiX_ + (nXiX_ - ix -1);
symmYtgID[i] = (nXiY_ - iy - 1)*nXiX_ + ix;
symmZtgID[i] = 0;
i++;
}
}
}
else //1D (X)
{
nXiX_ = nXiPerDim_;
nXiY_ = nXiZ_ = 1;
nXi_ = nXiX_*nXiY_*nXiZ_;
weightsGlobal.setSize(nXi_);
XisGlobal.setSize(nXi_);
symmXtgID.setSize(nXi_);
symmYtgID.setSize(nXi_);
symmZtgID.setSize(nXi_);
label i = 0;
for (label ix = 0; ix < nXiX_; ix++)
{
scalar weight = weights1D[ix]*1*1;
vector xi(Xis[ix], 0.0, 0.0);
weightsGlobal[i] = weight;
XisGlobal[i] = xi;
symmXtgID[i] = (nXiX_ - ix -1);
symmYtgID[i] = 0;
symmZtgID[i] = 0;
i++;
}
}
}
if(mpiReducer_.rank() == 0)
{
Info<< "fvDVM : Allocated " << XisGlobal.size()
<< " discrete velocities" << endl;
}
label nA = nXi_ / mpiReducer_.nproc();
label nB = nXi_ - nA*mpiReducer_.nproc();
label nXiPart = nA + (label)(mpiReducer_.rank() < nB);
DV_.setSize(nXiPart);
if(mpiReducer_.rank() == 0)
{
Info << "nproc " << mpiReducer_.nproc() << endl;
Info << "nXisPart " << nXiPart << endl;
}
label chunk = 0;
label gid = 0;
forAll(DV_, i)
{
gid = chunk + mpiReducer_.rank();
DV_.set
(
i,
new discreteVelocity
(
*this,
mesh_,
time_,
weightsGlobal[gid],
dimensionedVector( "xi", dimLength/dimTime, XisGlobal[gid]),
i,
symmXtgID[gid],
symmYtgID[gid],
symmZtgID[gid]
)
);
chunk += mpiReducer_.nproc();
}
}
void Foam::fvDVM::setCalculatedMaxwellRhoBC()
{
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
forAll(rhoBCs, patchi)
{
if (rhoBCs[patchi].type() == "calculatedMaxwell")
{
const vectorField& SfPatch = mesh_.Sf().boundaryField()[patchi];
calculatedMaxwellFvPatchField<scalar>& rhoPatch =
refCast<calculatedMaxwellFvPatchField<scalar> >(rhoBCs[patchi]);
const vectorField& Upatch = Uvol_.boundaryField()[patchi];
const scalarField& Tpatch = Tvol_.boundaryField()[patchi];
forAll(rhoPatch, facei)
{
vector faceSf = SfPatch[facei];
rhoPatch.inComingByRho()[facei] = 0; // set to zero
forAll(DV_, dvi) // add one by one
{
vector xi = DV_[dvi].xi().value();
scalar weight = DV_[dvi].weight();
if ( (xi & faceSf) < 0) //inComing
{
rhoPatch.inComingByRho()[facei] +=
- weight*(xi & faceSf)
*DV_[dvi].equilibriumMaxwellByRho
(
Upatch[facei],
Tpatch[facei]
);
}
}
}
if(args_.optionFound("dvParallel"))
mpiReducer_.reduceField(rhoPatch.inComingByRho());
}
}
}
void Foam::fvDVM::setSymmetryModRhoBC()
{
//prepare the container (set size) to store all DF on the patchi
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
forAll(rhoBCs, patchi)
{
label ps = rhoBCs[patchi].size();
if (rhoBCs[patchi].type() == "symmetryMod")
{
symmetryModFvPatchField<scalar>& rhoPatch =
refCast<symmetryModFvPatchField<scalar> >(rhoBCs[patchi]);
rhoPatch.dfContainer().setSize(ps*nXi_*2); //*2 means g and h
}
}
}
void Foam::fvDVM::updateGHbarPvol()
{
forAll(DV_, DVid)
DV_[DVid].updateGHbarPvol();
}
void Foam::fvDVM::updateGHbarSurf()
{
forAll(DV_, DVid)
DV_[DVid].updateGHbarSurf();
}
void Foam::fvDVM::updateMaxwellWallRho()
{
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
forAll(rhoBCs, patchi)
{
if (rhoBCs[patchi].type() == "calculatedMaxwell")
{
calculatedMaxwellFvPatchField<scalar>& rhoPatch =
refCast<calculatedMaxwellFvPatchField<scalar> >(rhoBCs[patchi]);
if(args_.optionFound("dvParallel"))
mpiReducer_.reduceField(rhoPatch.outGoing());
}
}
rhoVol_.correctBoundaryConditions();
}
void Foam::fvDVM::updateGHbarSurfMaxwellWallIn()
{
forAll(DV_, DVid)
DV_[DVid].updateGHbarSurfMaxwellWallIn();
}
void Foam::fvDVM::updateGHbarSurfSymmetryIn()
{
//1. copy all DV's g/h to rho patch's dfContainer
//2. MPI_Allgather the rho patch's dfContainer
//if(args_.optionFound("dvParallel"))
//{
label rank = mpiReducer_.rank();
label nproc = mpiReducer_.nproc();
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
forAll(rhoBCs, patchi)
{
label ps = rhoBCs[patchi].size();
if (rhoBCs[patchi].type() == "symmetryMod")
{
symmetryModFvPatchField<scalar>& rhoPatch =
refCast<symmetryModFvPatchField<scalar> >(rhoBCs[patchi]);
//compose the recvcout and displacement array
labelField recvc(nproc);
labelField displ(nproc);
label chunck = nXi_/nproc;
label left = nXi_%nproc;
forAll(recvc, i)
{
recvc[i] = 2*ps*(chunck + (i<left)) ;
if(i<=left)
displ[i] = i*2*ps*(chunck + 1); // (i<=nXi_%nproc)
else
displ[i] = 2*ps*(left*(chunck +1) + (i-left)*(chunck));
}
// check 12*28+15 dv's g
label did = 1709;
label pp = did%nproc;
label lid = did/nproc;
//if(rank==pp)
//{
//Info << "processing by rank " << rank << endl;
//Info << "12*28+15 outging g " << DV_[lid].gSurf()[0] << endl;
//Info << "12*28+15 outging xi " << DV_[lid].xi() <<endl;
//Info << "12*28+15 outging at boundary " << DV_[lid].gSurf().boundaryField()[patchi][0] << endl;
//}
// memcpy each dv's g/h to rho
forAll(DV_, DVid)
{
//label shift = (nXi_ / nproc * rank + DVid)*2*ps;
label shift = displ[rank] + DVid*2*ps;
memcpy( (rhoPatch.dfContainer().data() + shift),
DV_[DVid].gSurf().boundaryField()[patchi].cdata(), ps*sizeof(scalar));
memcpy( (rhoPatch.dfContainer().data() + shift + ps),
DV_[DVid].hSurf().boundaryField()[patchi].cdata(), ps*sizeof(scalar));
}
// check
//if(rank == pp)
//Info << "dv gid 1709's g = " <<rhoPatch.dfContainer()[displ[pp]+lid*2*ps+32]<< endl;;
//Allgather
MPI_Allgatherv(
//rhoPatch.dfContainer().data() + displ[rank],//2*ps*nXI_/nproc*rank, //send*
MPI_IN_PLACE,
2*ps*DV_.size(), //(how many DV i processed) * 2 * patch size
MPI_DOUBLE,
rhoPatch.dfContainer().data(),
recvc.data(),
displ.data(),
MPI_DOUBLE,
MPI_COMM_WORLD
);
}
}
forAll(DV_, DVid)
DV_[DVid].updateGHbarSurfSymmetryIn();
}
void Foam::fvDVM::updateMacroSurf()
{
// Init to zero before add one DV by one DV
rhoSurf_ = dimensionedScalar("0", rhoSurf_.dimensions(), 0);
Usurf_ = dimensionedVector("0", Usurf_.dimensions(), vector(0, 0, 0));
Tsurf_ = dimensionedScalar("0", Tsurf_.dimensions(), 0);
qSurf_ = dimensionedVector("0", qSurf_.dimensions(), vector(0, 0, 0));
stressSurf_ = dimensionedTensor
(
"0",
stressSurf_.dimensions(),
pTraits<tensor>::zero
);
//if(Pstream::parRun())
//{
//Pout << "My proc NO " << Pstream::myProcNo() << endl;
//if(Pstream::myProcNo() == 1)
//Pout << "g[78] at proc 1 interface" << DV_[100].gSurf().boundaryField()[mesh_.boundaryMesh().findPatchID("procBoundary1to0")][0] << endl;
//if(Pstream::myProcNo() == 0)
//Pout << "g[78] at proc 0 interface" << DV_[100].gSurf().boundaryField()[mesh_.boundaryMesh().findPatchID("procBoundary0to1")][0] << endl;
//}else
//{
//Info << "g[78] at 50 th interface" << DV_[100].gSurf()[49] << endl;
//}
// Conserved variable, now zero as the prime variable
// has been set to zero
surfaceVectorField rhoUsurf = rhoSurf_*Usurf_;
surfaceScalarField rhoEsurf = rhoSurf_*magSqr(Usurf_);
forAll(DV_, dvi)
{
discreteVelocity& dv = DV_[dvi];
rhoSurf_ += dXiCellSize_*dv.weight()*dv.gSurf();
rhoUsurf += dXiCellSize_*dv.weight()*dv.gSurf()*dv.xi();
rhoEsurf += 0.5*dXiCellSize_*dv.weight()
*(
dv.gSurf()*magSqr(dv.xi())
+ dv.hSurf()
);
}
if(args_.optionFound("dvParallel"))
{
mpiReducer_.reduceField(rhoSurf_);
mpiReducer_.reduceField(rhoUsurf);
mpiReducer_.reduceField(rhoEsurf);
}
//- get Prim. from Consv.
Usurf_ = rhoUsurf/rhoSurf_;
Tsurf_ = (rhoEsurf - 0.5*rhoSurf_*magSqr(Usurf_))/((KInner_ + 3)/2.0*R_*rhoSurf_);
tauSurf_ = updateTau(Tsurf_, rhoSurf_);
//- peculiar vel.
surfaceVectorField c = Usurf_;
//-get part heat flux
forAll(DV_, dvi)
{
discreteVelocity& dv = DV_[dvi];
c = dv.xi() - Usurf_;
qSurf_ += 0.5*dXiCellSize_*dv.weight()*c
*(
magSqr(c)*dv.gSurf()
+ dv.hSurf()
);
//- stressSurf is useless as we never update cell macro by macro flux
//- Comment out it as it is expansive
//stressSurf_ +=
//dXiCellSize_*dv.weight()*dv.gSurf()*c*c;
}
//- Get global heat flux, via MPI_Allreuce
if(args_.optionFound("dvParallel"))
mpiReducer_.reduceField(qSurf_);
//- correction for bar to original
qSurf_ = 2.0*tauSurf_/(2.0*tauSurf_ + 0.5*time_.deltaT()*Pr_)*qSurf_;
//- stress at surf is not used, as we dont't update macro in cell by macro flux at surface
//stressSurf_ =
//2.0*tauSurf_/(2.0*tauSurf_ + 0.5*time_.deltaT())*stressSurf_;
//- heat flux at wall is specially defined. as it ignores the velocity and temperature slip
//- NOTE: To be changed as it is part macro, but it will not affect the innner fields, so we change it later
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
qWall_ = dimensionedVector("0", qWall_.dimensions(), vector(0, 0, 0));
stressWall_ = dimensionedTensor
(
"0",
stressWall_.dimensions(),
pTraits<tensor>::zero
);
forAll(rhoBCs, patchi)
{
if (rhoBCs[patchi].type() == "calculatedMaxwell")
{
fvPatchField<vector>& qPatch = qWall_.boundaryField()[patchi];
fvPatchField<vector>& Upatch = Uvol_.boundaryField()[patchi];
fvPatchField<tensor>& stressPatch = stressWall_.boundaryField()[patchi];
//- tau at surface use the tau at slip temperature as it is.
fvsPatchField<scalar>& tauPatch = tauSurf_.boundaryField()[patchi];
forAll(qPatch, facei)
{
forAll(DV_, dvi)
{
scalar dXiCellSize = dXiCellSize_.value();
discreteVelocity& dv = DV_[dvi];
vector xi = dv.xi().value();
vector c = xi - Upatch[facei];
qPatch[facei] += 0.5*dXiCellSize*dv.weight()*c //sometimes wall moves, then c != \xi
*(
magSqr(c)*dv.gSurf().boundaryField()[patchi][facei]
+ dv.hSurf().boundaryField()[patchi][facei]
);
stressPatch[facei] +=
dXiCellSize*dv.weight()*dv.gSurf().boundaryField()[patchi][facei]*xi*xi;
}
qPatch[facei] = 2.0*tauPatch[facei]/(2.0*tauPatch[facei] + 0.5*time_.deltaT().value()*Pr_)*qPatch[facei];
stressPatch[facei] =
2.0*tauPatch[facei]/(2.0*tauPatch[facei] + 0.5*time_.deltaT().value())*stressPatch[facei];
}
if(args_.optionFound("dvParallel"))
{
mpiReducer_.reduceField(qPatch);
mpiReducer_.reduceField(stressPatch);
}
}
}
}
void Foam::fvDVM::updateGHsurf()
{
forAll(DV_, DVid)
DV_[DVid].updateGHsurf();
}
void Foam::fvDVM::updateGHtildeVol()
{
forAll(DV_, DVid)
DV_[DVid].updateGHtildeVol();
}
void Foam::fvDVM::updateMacroVol()
{
//- Old macros, used only if we update using macro fluxes.
volVectorField rhoUvol = rhoVol_*Uvol_;
volScalarField rhoEvol = rhoVol_*(magSqr(Uvol_) + (KInner_ + 3)/2.0*R_*Tvol_);
qVol_ = dimensionedVector("0", qVol_.dimensions(), vector(0, 0, 0));
if(macroFlux_ == "no") // update cell macro by moment from DF
{
//- init to zeros
rhoVol_ = dimensionedScalar("0", rhoVol_.dimensions(), 0);
rhoUvol = dimensionedVector("0", rhoUvol.dimensions(), vector(0, 0, 0));
rhoEvol = dimensionedScalar("0", rhoEvol.dimensions(), 0);
//- get part macro
forAll(DV_, dvi)
{
discreteVelocity& dv = DV_[dvi];
rhoVol_ += dXiCellSize_*dv.weight()*dv.gTildeVol();
rhoUvol += dXiCellSize_*dv.weight()*dv.gTildeVol()*dv.xi();
rhoEvol += 0.5*dXiCellSize_*dv.weight()
*(
magSqr(dv.xi())*dv.gTildeVol()
+ dv.hTildeVol()
);
}
//- get global macro via MPI_Allreduce
if(args_.optionFound("dvParallel"))
{
mpiReducer_.reduceField(rhoVol_);
mpiReducer_.reduceField(rhoUvol);
mpiReducer_.reduceField(rhoEvol);
}
}
else // update by macro flux
{
const labelUList& owner = mesh_.owner();
const labelUList& neighbour = mesh_.neighbour();
const vectorField Sf = mesh_.Sf();
const scalarField V = mesh_.V();
const scalar dt = time_.deltaTValue();
// internal faces
forAll(owner, facei)
{
const label own = owner[facei];
const label nei = neighbour[facei];
rhoVol_[own] -= (rhoSurf_[facei]*Usurf_[facei]&Sf[facei])*dt/V[own];
rhoVol_[nei] += (rhoSurf_[facei]*Usurf_[facei]&Sf[facei])*dt/V[nei];
rhoUvol[own] -= (rhoSurf_[facei]*Usurf_[facei]*Usurf_[facei]
+ stressSurf_[facei])&Sf[facei]*dt/V[own];
rhoUvol[nei] += (rhoSurf_[facei]*Usurf_[facei]*Usurf_[facei]
+ stressSurf_[facei])&Sf[facei]*dt/V[nei];
scalar rhoEsurf =
rhoSurf_[facei]
*(magSqr(Usurf_[facei]) + (KInner_ + 3)/2.0*R_.value()*Tsurf_[facei]);
rhoEvol[own] -= (rhoEsurf*Usurf_[facei] + qSurf_[facei])
&Sf[facei]*dt/V[own];
rhoEvol[nei] += (rhoEsurf*Usurf_[facei] + qSurf_[facei])
&Sf[facei]*dt/V[nei];
}
// boundary faces
forAll(rhoSurf_.boundaryField(), patchi)
{
const fvsPatchField<scalar>& rhoSurfPatch =
rhoSurf_.boundaryField()[patchi];
const fvsPatchField<vector>& UsurfPatch =
Usurf_.boundaryField()[patchi];
const fvsPatchField<scalar>& TsurfPatch =
Tsurf_.boundaryField()[patchi];
const fvsPatchField<tensor>& stressSurfPatch =
stressSurf_.boundaryField()[patchi];
const fvsPatchField<vector>& qSurfPatch =
qSurf_.boundaryField()[patchi];
const fvsPatchField<vector>& SfPatch =
mesh_.Sf().boundaryField()[patchi];
const labelUList& pOwner = mesh_.boundary()[patchi].faceCells();
forAll(pOwner, pFacei)
{
const label own = pOwner[pFacei];
rhoVol_[own] -= (rhoSurfPatch[pFacei]*UsurfPatch[pFacei]
&SfPatch[pFacei])*dt/V[own];
rhoUvol[own] -= (rhoSurfPatch[pFacei]*UsurfPatch[pFacei]*UsurfPatch[pFacei]
+ stressSurfPatch[pFacei])&Sf[pFacei]*dt/V[own];
scalar rhoEsurf =
rhoSurfPatch[pFacei]
*(magSqr(UsurfPatch[pFacei]) + (KInner_ + 3)/2.0*R_.value()*TsurfPatch[pFacei]);
rhoEvol[own] -= (rhoEsurf*UsurfPatch[pFacei] + qSurfPatch[pFacei])
&SfPatch[pFacei]*dt/V[own];
}
}
}
//- get Prim. from Consv.
Uvol_ = rhoUvol/rhoVol_;
Tvol_ = (rhoEvol - 0.5*rhoVol_*magSqr(Uvol_))/((KInner_ + 3)/2.0*R_*rhoVol_);
//- Correct the macro field boundary conition
Uvol_.correctBoundaryConditions();
Tvol_.correctBoundaryConditions();
//- Note for maxwell wall, the operation here update
//- the boundary rho field but it's meaningless.
//- The vol macro field's boundary field is meanless!
//rhoVol_.correctBoundaryConditions();
//- update tau
tauVol_ = updateTau(Tvol_, rhoVol_);
//- peculiar vel.
volVectorField c = Uvol_;
//-get part heat flux
forAll(DV_, dvi)
{
discreteVelocity& dv = DV_[dvi];
c = dv.xi() - Uvol_;
qVol_ += 0.5*dXiCellSize_*dv.weight()*c
*(
magSqr(c)*dv.gTildeVol()
+ dv.hTildeVol()
);
}
//- get global heat flux via MPI_Allreduce
if(args_.optionFound("dvParallel"))
mpiReducer_.reduceField(qVol_);
//- correction for bar to original
qVol_ = 2.0*tauVol_/(2.0*tauVol_ + time_.deltaT()*Pr_)*qVol_;
}
void Foam::fvDVM::updatePressureInOutBC()
{
// for pressureIn and pressureOut BC, the boundary value of Uvol(in/out) and Tvol(in/out) should be updated here!
// boundary faces
GeometricField<scalar, fvPatchField, volMesh>::GeometricBoundaryField&
rhoBCs = rhoVol_.boundaryField();
forAll(rhoBCs, patchi)
{
if (rhoBCs[patchi].type() == "pressureIn")
{
const fvsPatchField<vector>& SfPatch = mesh_.Sf().boundaryField()[patchi];
const fvsPatchField<scalar>& magSfPatch = mesh_.magSf().boundaryField()[patchi];
pressureInFvPatchField<scalar>& rhoPatch =
refCast<pressureInFvPatchField<scalar> >(rhoBCs[patchi]);
fvPatchField<vector>& Upatch = Uvol_.boundaryField()[patchi];
const fvPatchField<scalar>& Tpatch = Tvol_.boundaryField()[patchi];
const scalar pressureIn = rhoPatch.pressureIn();
// now changed rho and U patch
const labelUList& pOwner = mesh_.boundary()[patchi].faceCells();
forAll(rhoPatch, facei)
{
const scalar Tin = Tpatch[facei];
// change density
rhoPatch[facei] = pressureIn/R_.value()/Tin; // Accturally not changed at all :p
// inner boundary cell data state data
label own = pOwner[facei];
vector Ui = Uvol_[own];
scalar Ti = Tvol_[own];
scalar rhoi = rhoVol_[own];
scalar ai = sqrt(R_.value() * Ti * (KInner_ + 5)/(KInner_ + 3)); // sos
// change normal velocity component based on the characteristics
vector norm = SfPatch[facei]/magSfPatch[facei]; // boundary face normal vector
scalar Un = Ui & norm; // normal component
scalar UnIn = Un + (pressureIn - rhoi * R_.value() * Ti)/rhoi/ai; // change normal component
Upatch[facei] = UnIn * norm + (Ui - Un * norm); // tangential component not changed.
}
}
else if(rhoBCs[patchi].type() == "pressureOut")
{
const fvsPatchField<vector>& SfPatch = mesh_.Sf().boundaryField()[patchi];
const fvsPatchField<scalar>& magSfPatch = mesh_.magSf().boundaryField()[patchi];
pressureOutFvPatchField<scalar>& rhoPatch =
refCast<pressureOutFvPatchField<scalar> >(rhoBCs[patchi]);
fvPatchField<vector>& Upatch = Uvol_.boundaryField()[patchi];
fvPatchField<scalar>& Tpatch = Tvol_.boundaryField()[patchi];
const scalar pressureOut = rhoPatch.pressureOut();
// now changed rho and U patch
const labelUList& pOwner = mesh_.boundary()[patchi].faceCells();
forAll(rhoPatch, facei)
{
// inner cell data state data
label own = pOwner[facei];
vector Ui = Uvol_[own];
scalar Ti = Tvol_[own];
scalar rhoi = rhoVol_[own];
scalar ai = sqrt(R_.value() * Ti * (KInner_ + 5)/(KInner_ + 3)); // sos
// change outlet density
rhoPatch[facei] = rhoi + (pressureOut - rhoi * R_.value() * Ti)/ai/ai; // Accturally not changed at all :p
Tpatch[facei] = pressureOut/(R_.value() * rhoi);
// change normal velocity component based on the characteristics
vector norm = SfPatch[facei]/magSfPatch[facei]; // boundary face normal vector
scalar Un = Ui & norm; // normal component
scalar UnIn = Un + ( rhoi * R_.value() * Ti - pressureOut)/rhoi/ai; // change normal component
Upatch[facei] = UnIn * norm + (Ui - Un * norm); // tangential component not changed.
}
}
}
}
template<template<class> class PatchType, class GeoMesh>
Foam::tmp<Foam::GeometricField<scalar, PatchType, GeoMesh> >
Foam::fvDVM::updateTau
(
const GeometricField<scalar, PatchType, GeoMesh>& T,
const GeometricField<scalar, PatchType, GeoMesh>& rho
)
{
tmp<GeometricField<scalar, PatchType, GeoMesh> > tTau
(
new GeometricField<scalar, PatchType, GeoMesh>
(
IOobject
(
"tau",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedScalar( "0", dimTime, 0)
)
);
GeometricField<scalar, PatchType, GeoMesh>& tau = tTau();
tau = muRef_*exp(omega_*log(T/Tref_))/rho/T/R_;
return tTau;
}
void Foam::fvDVM::writeDF(label cellId)
{
std::ostringstream convert;
convert << cellId;
scalarIOList df
(
IOobject
(
"DF"+convert.str(),
time_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
)
);
//set size of df
df.setSize(nXi_);
scalarList dfPart(DV_.size());
//put cellId's DF to dfPart
forAll(dfPart, dfi)
dfPart[dfi] = DV_[dfi].gTildeVol()[cellId];
label nproc = mpiReducer_.nproc();
//gather
//tmp list for recv
scalarList dfRcv(nXi_);
//Compose displc and recvc
labelField recvc(nproc);
labelField displ(nproc);
label chunck = nXi_/nproc;
label left = nXi_%nproc;
forAll(recvc, i)
{
recvc[i] = chunck + (i<left) ;
if(i<=left)
displ[i] = i*(chunck + 1); // (i<=nXi_%nproc)
else
displ[i] = left*(chunck +1) + (i-left)*(chunck);
}
MPI_Gatherv(dfPart.cdata(), dfPart.size(), MPI_DOUBLE,
dfRcv.data(), recvc.cdata(), displ.cdata(),
MPI_DOUBLE, 0, MPI_COMM_WORLD);
//reposition
if(mpiReducer_.rank() == 0)
{
forAll(df, i)
{
label p = i%nproc;
label ldi = i/nproc;
df[i] = dfRcv[displ[p]+ldi];
}
df.write();
}
}
// * * * * * * * * * * * * * * * * Constructors * * * * * * * * * * * * * * //
Foam::fvDVM::fvDVM
(
volScalarField& rho,
volVectorField& U,
volScalarField& T,
int* argc,
char*** argv,
Foam::argList& args
)
:
IOdictionary
(
IOobject
(
"DVMProperties",
T.time().constant(),
T.mesh(),
IOobject::MUST_READ,
IOobject::NO_WRITE
)
),
mesh_(rho.mesh()),
time_(rho.time()),
rhoVol_(rho),
Uvol_(U),
Tvol_(T),
args_(args),
fvDVMparas_(subOrEmptyDict("fvDVMparas")),
gasProperties_(subOrEmptyDict("gasProperties")),
nXiPerDim_(readLabel(fvDVMparas_.lookup("nDV"))),
xiMax_(fvDVMparas_.lookup("xiMax")),
xiMin_(fvDVMparas_.lookup("xiMin")),
dXi_((xiMax_-xiMin_)/(nXiPerDim_ - 1)),
dXiCellSize_
(
"dXiCellSize",
pow(dimLength/dimTime, 3),
scalar(1.0)
),
macroFlux_(fvDVMparas_.lookupOrDefault("macroFlux", word("no"))),
//res_(fvDVMparas_.lookupOrDefault("res", 1.0e-12)),
//checkSteps_(fvDVMparas_.lookupOrDefault("checkSteps", 100)),
R_(gasProperties_.lookup("R")),
omega_(readScalar(gasProperties_.lookup("omega"))),
Tref_(gasProperties_.lookup("Tref")),
muRef_(gasProperties_.lookup("muRef")),
Pr_(readScalar(gasProperties_.lookup("Pr"))),
KInner_((gasProperties_.lookupOrDefault("KInner", 0))),
mpiReducer_(args, argc, argv), // args comes from setRootCase.H in dugksFoam.C;
DV_(0),
rhoSurf_
(
IOobject
(
"rhoSurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedScalar( "0", rho.dimensions(), 0)
),
Tsurf_
(
IOobject
(
"Tsurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedScalar( "0", T.dimensions(), 0)
),
Usurf_
(
IOobject
(
"Usurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedVector( "0", U.dimensions(), vector(0,0,0))
),
qSurf_
(
IOobject
(
"qSurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
),
mesh_,
dimensionedVector( "0", dimMass/pow(dimTime,3), vector(0,0,0))
),
stressSurf_
(
IOobject
(
"stressSurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
),
mesh_,
dimensionedTensor("0", dimensionSet(1,-1,-2,0,0,0,0), pTraits<tensor>::zero)
),
qVol_
(
IOobject
(
"q",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
),
mesh_,
dimensionedVector( "0", dimMass/pow(dimTime,3), vector(0,0,0))
),
tauVol_
(
IOobject
(
"tauVol",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedScalar( "0", dimTime, 0)
),
tauSurf_
(
IOobject
(
"tauSurf",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::NO_WRITE
),
mesh_,
dimensionedScalar( "0", dimTime, 0)
),
qWall_
(
IOobject
(
"qWall",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
),
mesh_,
dimensionedVector( "0", dimMass/pow(dimTime,3), vector(0,0,0))
),
stressWall_
(
IOobject
(
"stressWall",
mesh_.time().timeName(),
mesh_,
IOobject::NO_READ,
IOobject::AUTO_WRITE
),
mesh_,
dimensionedTensor("0", dimensionSet(1,-1,-2,0,0,0,0), pTraits<tensor>::zero)
)
{
initialiseDV();
setCalculatedMaxwellRhoBC();
setSymmetryModRhoBC();
// set initial rho in pressureIn/Out BC
updatePressureInOutBC();
tauVol_ = updateTau(Tvol_, rhoVol_); //calculate the tau at cell when init
Usurf_ = fvc::interpolate(Uvol_, "linear"); // for first time Dt calculation.
}
// * * * * * * * * * * * * * * * * Destructor * * * * * * * * * * * * * * * //
Foam::fvDVM::~fvDVM()
{
}
// * * * * * * * * * * * * * * * Member Functions * * * * * * * * * * * * * //
void Foam::fvDVM::evolution()
{
//Info << "Begin evolution" << endl;
updateGHbarPvol();
//Info << "Done updateGHbarPvol " << endl;
updateGHbarSurf();
//Info << "Done updateGHbarSurf " << endl;
updateMaxwellWallRho();
//Info << "Done updateMaxwellWallRho " << endl;
updateGHbarSurfMaxwellWallIn();
//Info << "Done updateGHbarSurfMaxwellWallIn " << endl;
updateGHbarSurfSymmetryIn();
//Info << "Done updateGHbarSurfSymmetryIn " << endl;
updateMacroSurf();
//Info << "Done updateMacroSurf " << endl;
updateGHsurf();
//Info << "Done updateGHsurf " << endl;
updateGHtildeVol();
//Info << "Done updateGHtildeVol " << endl;
updateMacroVol();
//
updatePressureInOutBC();
}
void Foam::fvDVM::getCoNum(scalar& maxCoNum, scalar& meanCoNum)
{
scalar dt = time_.deltaTValue();
scalarField UbyDx =
mesh_.surfaceInterpolation::deltaCoeffs()
*(mag(Usurf_) + sqrt(scalar(mesh_.nSolutionD()))*xiMax_);
maxCoNum = gMax(UbyDx)*dt;
meanCoNum = gSum(UbyDx)/UbyDx.size()*dt;
}
const fieldMPIreducer& Foam::fvDVM::mpiReducer() const
{
return mpiReducer_;
}
// ************************************************************************* //
| [
"zhulianhua121@gmail.com"
] | zhulianhua121@gmail.com |
464f9c8ad4c8b8fa80e3424c3459001557e13bd7 | 7d4176c878e8be73ffaa38c236f1a76528706c9f | /src/sys/scsi/scsi_tape.h | cc6f8570f734c7ead4a4c2438f583cf35b0b93e4 | [] | no_license | roytam1/mirbsd-cvs | c06ea23d2b106658f9903fe65d351c480b72e72c | 2a6f84cbc58f6ff22e1eeb7804df68d34c2b0a5c | refs/heads/master | 2020-04-14T15:47:25.324452 | 2019-01-01T19:38:30 | 2019-01-01T19:38:30 | 163,906,352 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 8,599 | h | /* $OpenBSD: scsi_tape.h,v 1.7 1998/01/07 17:28:38 deraadt Exp $ */
/* $NetBSD: scsi_tape.h,v 1.9 1996/05/24 02:04:47 thorpej Exp $ */
/*
* Copyright (c) 1994 Charles Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Charles Hannum.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Originally written by Julian Elischer (julian@tfs.com)
* for TRW Financial Systems.
*
* TRW Financial Systems, in accordance with their agreement with Carnegie
* Mellon University, makes this software available to CMU to distribute
* or use in any manner that they see fit as long as this message is kept with
* the software. For this reason TFS also grants any other persons or
* organisations permission to use or modify this software.
*
* TFS supplies this software to be publicly redistributed
* on the understanding that TFS is not responsible for the correct
* functioning of this software in any circumstances.
*
* Ported to run under 386BSD by Julian Elischer (julian@tfs.com) Sept 1992
*/
/*
* SCSI tape interface description
*/
#ifndef _SCSI_TAPE_H_
#define _SCSI_TAPE_H_ 1
/*
* SCSI command formats
*/
#define READ 0x08
#define WRITE 0x0a
struct scsi_rw_tape {
u_int8_t opcode;
u_int8_t byte2;
#define SRW_FIXED 0x01
u_int8_t len[3];
u_int8_t control;
};
#define SPACE 0x11
struct scsi_space {
u_int8_t opcode;
u_int8_t byte2;
#define SS_CODE 0x03
#define SP_BLKS 0x00
#define SP_FILEMARKS 0x01
#define SP_SEQ_FILEMARKS 0x02
#define SP_EOM 0x03
u_int8_t number[3];
u_int8_t control;
};
#define WRITE_FILEMARKS 0x10
struct scsi_write_filemarks {
u_int8_t opcode;
u_int8_t byte2;
u_int8_t number[3];
u_int8_t control;
};
#define REWIND 0x01
struct scsi_rewind {
u_int8_t opcode;
u_int8_t byte2;
#define SR_IMMED 0x01
u_int8_t unused[3];
u_int8_t control;
};
#define LOAD 0x1b
struct scsi_load {
u_int8_t opcode;
u_int8_t byte2;
#define SL_IMMED 0x01
u_int8_t unused[2];
u_int8_t how;
#define LD_UNLOAD 0x00
#define LD_LOAD 0x01
#define LD_RETENSION 0x02
u_int8_t control;
};
#define ERASE 0x19
struct scsi_erase {
u_int8_t opcode;
u_int8_t byte2;
#define SE_LONG 0x01
#define SE_IMMED 0x02
u_int8_t unused[3];
u_int8_t control;
};
#define READ_BLOCK_LIMITS 0x05
struct scsi_block_limits {
u_int8_t opcode;
u_int8_t byte2;
u_int8_t unused[3];
u_int8_t control;
};
struct scsi_block_limits_data {
u_int8_t reserved;
u_int8_t max_length[3]; /* Most significant */
u_int8_t min_length[2]; /* Most significant */
};
/* See SCSI-II spec 9.3.3.1 */
struct scsi_tape_dev_conf_page {
u_int8_t pagecode; /* 0x10 */
u_int8_t pagelength; /* 0x0e */
u_int8_t byte2;
#define SMT_CAP 0x40 /* change active partition */
#define SMT_CAF 0x20 /* change active format */
#define SMT_AFMASK 0x1f /* active format mask */
u_int8_t active_partition;
u_int8_t wb_full_ratio;
u_int8_t rb_empty_ratio;
u_int8_t wrdelay_time[2];
u_int8_t byte8;
#define SMT_DBR 0x80 /* data buffer recovery */
#define SMT_BIS 0x40 /* block identifiers supported */
#define SMT_RSMK 0x20 /* report setmarks */
#define SMT_AVC 0x10 /* automatic velocity control */
#define SMT_SOCF_MASK 0xc0 /* stop on consecutive formats */
#define SMT_RBO 0x20 /* recover buffer order */
#define SMT_REW 0x10 /* report early warning */
u_int8_t gap_size;
u_int8_t byte10;
#define SMT_EODDEFINED 0xe0 /* EOD defined */
#define SMT_EEG 0x10 /* enable EOD generation */
#define SMT_SEW 0x80 /* synchronize at early warning */
u_int8_t ew_bufsize[3];
u_int8_t sel_comp_alg;
#define SMT_COMP_NONE 0x00
#define SMT_COMP_DEFAULT 0x01
u_int8_t reserved;
};
/* defines for the device specific byte in the mode select/sense header */
#define SMH_DSP_SPEED 0x0F
#define SMH_DSP_BUFF_MODE 0x70
#define SMH_DSP_BUFF_MODE_OFF 0x00
#define SMH_DSP_BUFF_MODE_ON 0x10
#define SMH_DSP_BUFF_MODE_MLTI 0x20
#define SMH_DSP_WRITE_PROT 0x80
/* A special for the CIPHER ST150S(old drive) */
struct block_desc_cipher {
u_int8_t density;
u_int8_t nblocks[3];
u_int8_t reserved;
u_int8_t blklen[3];
u_int8_t other;
#define ST150_SEC 0x01 /* soft error count */
#define SR150_AUI 0x02 /* autoload inhibit */
};
/**********************************************************************
from the scsi2 spec
Value Tracks Density(bpi) Code Type Reference Note
0x1 9 800 NRZI R X3.22-1983 2
0x2 9 1600 PE R X3.39-1986 2
0x3 9 6250 GCR R X3.54-1986 2
0x5 4/9 8000 GCR C X3.136-1986 1
0x6 9 3200 PE R X3.157-1987 2
0x7 4 6400 IMFM C X3.116-1986 1
0x8 4 8000 GCR CS X3.158-1986 1
0x9 18 37871 GCR C X3B5/87-099 2
0xA 22 6667 MFM C X3B5/86-199 1
0xB 4 1600 PE C X3.56-1986 1
0xC 24 12690 GCR C HI-TC1 1,5
0xD 24 25380 GCR C HI-TC2 1,5
0xF 15 10000 GCR C QIC-120 1,5
0x10 18 10000 GCR C QIC-150 1,5
0x11 26 16000 GCR C QIC-320(525?) 1,5
0x12 30 51667 RLL C QIC-1350 1,5
0x13 1 61000 DDS CS X3B5/88-185A 4
0x14 1 43245 RLL CS X3.202-1991 4
0x15 1 45434 RLL CS ECMA TC17 4
0x16 48 10000 MFM C X3.193-1990 1
0x17 48 42500 MFM C X3B5/91-174 1
0x45 73 67733 RLL C QIC3095
where Code means:
NRZI Non Return to Zero, change on ones
GCR Group Code Recording
PE Phase Encoded
IMFM Inverted Modified Frequency Modulation
MFM Modified Frequency Modulation
DDS Dat Data Storage
RLL Run Length Encoding
where Type means:
R Reel-to-Reel
C Cartridge
CS cassette
where Notes means:
1 Serial Recorded
2 Parallel Recorded
3 Old format know as QIC-11
4 Helical Scan
5 Not ANSI standard, rather industry standard.
********************************************************************/
#define HALFINCH_800 0x01
#define HALFINCH_1600 0x02
#define HALFINCH_6250 0x03
#define QIC_11 0x04 /* from Archive 150S Theory of Op. XXX */
#define QIC_24 0x05 /* may be bad, works for CIPHER ST150S XXX */
#define QIC_120 0x0f
#define QIC_150 0x10
#define QIC_320 0x11
#define QIC_525 0x11
#define QIC_1320 0x12
#define DDS 0x13
#define DAT_1 0x13
#define QIC_3080 0x29
#define QIC_3095 0x45
#endif /* _SCSI_TAPE_H_ */
| [
""
] | |
fa90a9be276534b8750417059f04e76bc0db3cb2 | 74ca0502be3ea74703928bfa458e87a4335866f9 | /isode-8.0/paradise/others/quipu/uips/de/util.c | e8574aeb4b7e2cc984ba20779de4869e8694701c | [
"Apache-2.0"
] | permissive | Kampbell/ISODE | a80682dab1ee293a2711a687fc10660aae546933 | affd47713e792f7797150f237b10764577e5e067 | refs/heads/master | 2021-01-10T15:56:44.788906 | 2016-02-18T10:48:55 | 2016-02-18T10:48:55 | 52,000,870 | 8 | 0 | null | null | null | null | UTF-8 | C | false | false | 9,369 | c | /* template.c - your comments here */
#ifndef lint
static char *rcsid = "$Header: /xtel/isode/isode/others/quipu/uips/de/RCS/util.c,v 9.1 1992/08/25 15:50:26 isode Exp $";
#endif
/*
* $Header: /xtel/isode/isode/others/quipu/uips/de/RCS/util.c,v 9.1 1992/08/25 15:50:26 isode Exp $
*
*
* $Log: util.c,v $
* Revision 9.1 1992/08/25 15:50:26 isode
* PARADISE release
*
* Revision 8.1 1991/09/13 14:36:41 isode
* PARADISE Upgrade release
*
* Revision 8.0 91/07/17 13:18:50 isode
* Release 7.0
*
*
*/
/*
* NOTICE
*
* Acquisition, use, and distribution of this module and related
* materials are subject to the restrictions of a license agreement.
* Consult the Preface in the User's Manual for the full terms of
* this agreement.
*
*/
#include <signal.h>
#include "config.h"
#include "demanifest.h"
#include "destrings.h"
#include "types.h"
#include "util.h"
#include "namelist.h"
#include "cnamelist.h"
#include "quipu/util.h"
#include "quipu/ds_search.h"
#include "logger.h"
#include "query.h"
extern struct query qinfo[];
extern LLog *de_log;
extern int limitProblem;
extern int notAllReached;
extern int localAlarmTime;
extern int remoteAlarmTime;
extern char origDefaultCo[], origDefaultOrg[];
extern int deLogLevel;
extern int alarmCount;
extern int bindTimeout;
void onint1();
void clearDots();
extern int dots;
extern int dotsPrinted;
int
listlen(lp)
struct namelist * lp;
{
int len;
for (len = 0; lp != NULLLIST; lp = lp->next, len++) {};
return len;
}
unsigned int
alarmLen() {
if ((lexequ(qinfo[ORG].entered, origDefaultOrg) == 0) &&
(lexequ(qinfo[COUNTRY].entered, origDefaultCo) == 0))
return localAlarmTime;
else
return remoteAlarmTime;
}
void initAlarm() {
void onalarm();
(void) signal(SIGALRM, (VFP) onalarm);
dots = alarmLen() / 2;
dotsPrinted = 0;
(void) alarm(2);
}
void
alarmCleanUp() {
(void) signal(SIGALRM, SIG_IGN);
(void) alarm(0);
if (dotsPrinted > 0) {
if (dotsPrinted < dots)
clearDots();
else
(void) printf("\n\n");
dotsPrinted = 0;
}
}
void
clearDots() {
int i, len;
len = strlen(SEARCHMESS) + dotsPrinted;
for (i = 0; i < len; i++)
(void)printf("\b \b");
}
void
handleTimeout() {
de_unbind();
(void) signal(SIGALRM, SIG_IGN);
}
void startUnbindTimer() {
void handleTimeout();
(void) signal(SIGALRM, (VFP) handleTimeout);
(void) alarm((unsigned)bindTimeout);
}
void stopUnbindTimer() {
(void) signal(SIGALRM, SIG_IGN);
(void) alarm(0);
}
char *
copy_string(string)
char *string;
{
char *new_string;
if (string == NULLCP) return NULLCP;
new_string = (char *) smalloc((strlen(string) + 1));
(void) strcpy(new_string, string);
return new_string;
}
static PS ps = NULLPS;
char *dn2pstr (dn)
DN dn;
{
char *cp;
if (ps == NULL
&& ((ps = ps_alloc (str_open)) == NULLPS)
|| str_setup (ps, NULLCP, BUFSIZ, 0) == NOTOK) {
if (ps)
ps_free (ps), ps = NULLPS;
return NULLCP;
}
dn_print (ps, dn, RDNOUT);
ps_print (ps, " ");
*--ps -> ps_ptr = NULL, ps -> ps_cnt++;
cp = ps -> ps_base;
ps -> ps_base = NULL, ps -> ps_cnt = 0;
ps -> ps_ptr = NULL, ps -> ps_bufsiz = 0;
return cp;
}
char *rdn2pstr (rdn)
RDN rdn;
{
char *cp;
if (ps == NULL
&& ((ps = ps_alloc (str_open)) == NULLPS)
|| str_setup (ps, NULLCP, BUFSIZ, 0) == NOTOK) {
if (ps)
ps_free (ps), ps = NULLPS;
return NULLCP;
}
rdn_print (ps, rdn, RDNOUT);
ps_print (ps, " ");
*--ps -> ps_ptr = NULL, ps -> ps_cnt++;
cp = ps -> ps_base;
ps -> ps_base = NULL, ps -> ps_cnt = 0;
ps -> ps_ptr = NULL, ps -> ps_bufsiz = 0;
return cp;
}
/* determine wildcard type of already validated string */
int starstring(istr, ostr1, ostr2)
char * istr, ** ostr1, ** ostr2;
{
char * lastcp, *cp;
lastcp = istr + strlen(istr) - 1;
if ((*istr != '*') && (*lastcp == '*')) {
*lastcp = '\0';
*ostr1 = istr;
return LEADSUBSTR;
} else if ((*istr == '*') && (*lastcp != '*')) {
*ostr1 = istr + 1;
return TRAILSUBSTR;
} else if ((*istr == '*') && (*lastcp == '*')) {
*lastcp = '\0';
*ostr1 = istr + 1;
return ANYSUBSTR;
} else { /* must be of the form foo*bar */
*ostr1 = istr;
cp = index(istr, '*');
*cp = '\0';
*ostr2 = cp + 1;
return LEADANDTRAIL;
}
}
/* print last component of a dn string - optionally indented by type */
void printLastComponent(indent, dnstr, objectType, printNumber)
int indent;
char * dnstr;
int objectType;
int printNumber;
{
char * cp1, * cp2, * savestring;
if (strcmp(dnstr, "root") == 0)
return;
savestring = copy_string(dnstr);
cp1 = lastComponent(savestring, objectType);
if (cp1 == NULLCP) {
savestring = copy_string("Entry with no name!");
cp2 = savestring;
} else {
if (objectType == COUNTRY)
cp2 = mapCoName(cp1);
else
cp2 = cp1;
}
if (indent == INDENTON) {
switch (objectType) {
case COUNTRY:
break;
case LOCALITY:
pageprint(" ");
break;
case ORG:
pageprint(" ");
break;
case ORGUNIT:
pageprint(" ");
break;
case PERSON:
pageprint(" ");
break;
default:
(void) fprintf(stderr, "WOT's THIS? ");
break;
}
}
if (printNumber != 0)
pageprint("%3d ", printNumber);
pageprint("%s\n", cp2);
free(cp1);
free(savestring);
}
char *
lastComponent(dnstr, objectType)
char * dnstr;
int objectType;
{
char * cp, * cp2, *cp3, * savestring;
int gotmatch;
if (dnstr == NULLCP)
return NULLCP;
if (*dnstr == '\0')
return NULLCP;
savestring = copy_string(dnstr);
cp = cp3 = rindex(savestring, '@');
if (cp == NULLCP)
cp = dnstr;
else
cp++;
for (;;) {
gotmatch = FALSE;
switch (objectType) {
case PERSON:
if (strncmp(cp, SHORT_CN, strlen(SHORT_CN)) == 0) {
cp += strlen(SHORT_CN) + 1;
gotmatch = TRUE;
}
break;
case ORGUNIT:
if (strncmp(cp, SHORT_OU, strlen(SHORT_OU)) == 0) {
cp += strlen(SHORT_OU) + 1;
gotmatch = TRUE;
}
break;
case ORG:
if (strncmp(cp, SHORT_ORG, strlen(SHORT_ORG)) == 0) {
cp += strlen(SHORT_ORG) + 1;
gotmatch = TRUE;
}
break;
case LOCALITY:
if (strncmp(cp, SHORT_LOC, strlen(SHORT_LOC)) == 0) {
cp += strlen(SHORT_LOC) + 1;
gotmatch = TRUE;
}
break;
case COUNTRY:
if (strncmp(cp, SHORT_CO, strlen(SHORT_CO)) == 0) {
cp += strlen(SHORT_CO) + 1;
gotmatch = TRUE;
} else if (strncmp(cp, SHORT_LOC, strlen(SHORT_LOC)) == 0) {
cp += strlen(SHORT_LOC) + 1;
gotmatch = TRUE;
}
break;
}
cp2 = index(cp, '%');
if (gotmatch == TRUE) {
if (cp2 != NULLCP)
*cp2 = '\0';
break;
} else {
if (cp2 != NULLCP)
cp = cp2 + 1;
else
break;
}
}
if (gotmatch == FALSE) {
cp = index(cp3, '%');
if (cp != NULLCP)
*cp = '\0';
cp = index(cp3, '=') + 1;
}
cp = copy_string(cp);
free (savestring);
return cp;
}
char *
removeLastRDN(dnstr)
char * dnstr;
{
char * cp, * cp2;
cp = copy_string(dnstr);
if ((cp2 = rindex(cp, '@')) == NULLCP)
return NULLCP;
else
*cp2 = '\0';
return cp;
}
char *
lastRDN(dnstr)
char * dnstr;
{
char * cp;
cp = rindex(dnstr, '@');
if (cp == NULLCP)
return dnstr;
/* return NULLCP; */
else
return (++cp);
}
void
clearProblemFlags() {
limitProblem = notAllReached = FALSE;
}
void
setProblemFlags(sresult)
struct ds_search_result sresult;
{
if ((sresult.CSR_limitproblem == LSR_SIZELIMITEXCEEDED) ||
(sresult.CSR_limitproblem == LSR_ADMINSIZEEXCEEDED))
limitProblem = TRUE;
if ((sresult.CSR_cr != NULLCONTINUATIONREF) ||
(sresult.CSR_limitproblem == LSR_TIMELIMITEXCEEDED))
notAllReached = TRUE;
}
showAnyProblems(str)
char * str;
{
if (limitProblem == TRUE) {
pageprint("\nA limit has been imposed by the managers of the data which prevents the \n");
pageprint("listing of all the entries in the Directory beyond this point. Try and\n");
if (strcmp(str, "*") == 0) {
pageprint("guess the name of the entry you want. The directory may find the entry\n");
pageprint("even if you don't get the name exactly right.\n");
} else
pageprint("specify the query more precisely.\n");
pageprint("Please refer to the ?matching help screen for more details.\n");
} else {
if (notAllReached == TRUE) {
pageprint("\nIt was not possible to search all the parts of the Directory necessary\n");
pageprint("to complete this search - part of the database is currently inaccessible.\n");
pageprint("There may thus be more results than those displayed.\n\n");
}
}
}
void
logSearchSuccess(outcome, objecttype, string, searchNumber, noMatches)
char * outcome;
char * objecttype;
char * string;
int searchNumber;
int noMatches;
{
char filterNumberString[20];
if (deLogLevel > 1) {
if (searchNumber == 0)
(void) strcpy(filterNumberString, "explicit");
else
(void) sprintf(filterNumberString, "%d", searchNumber);
(void) ll_log (de_log, LLOG_NOTICE, NULLCP,
"searchOutcome:%s:%s:%s:%s:%d", objecttype,
outcome, string, filterNumberString, noMatches);
}
}
void logListSuccess(outcome, objecttype, noMatches)
char * outcome;
char * objecttype;
int noMatches;
{
if (deLogLevel > 1) {
(void) ll_log (de_log, LLOG_NOTICE, NULLCP,
"listOutcome:%s:%s:%d", objecttype, outcome, noMatches);
}
}
void logReadSuccess(outcome, objecttype)
char * outcome;
char * objecttype;
{
if (deLogLevel > 1) {
(void) ll_log (de_log, LLOG_NOTICE, NULLCP,
"readOutcome:%s:%s", objecttype, outcome);
}
}
| [
"zosrothko@orange.fr"
] | zosrothko@orange.fr |
c485ea22d20c2bbaa3e39fd15dda2604814719f4 | 18f5c6c7dad3df550ae1236913c4e9192087aa67 | /test/float32_unpack.c | 6c29d9a57566252c505adf300924b20ec417a2b7 | [
"MIT"
] | permissive | mohayonao/libvorbis.js | f51bd8ce934bcc076c1114762f7288557f535c30 | c53084b29549bc6e4a702fd4b21d4613655f77af | refs/heads/master | 2020-04-05T22:57:06.357833 | 2013-03-04T04:14:19 | 2013-03-04T04:14:19 | 8,370,164 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 870 | c | #include <stdio.h>
#include <math.h>
/* 32 bit float (not IEEE; nonnormalized mantissa +
biased exponent) : neeeeeee eeemmmmm mmmmmmmm mmmmmmmm
Why not IEEE? It's just not that important here. */
#define VQ_FEXP 10
#define VQ_FMAN 21
#define VQ_FEXP_BIAS 768 /* bias toward values smaller than 1. */
float _float32_unpack(long val){
double mant=val&0x1fffff;
int sign=val&0x80000000;
long exp =(val&0x7fe00000L)>>VQ_FMAN;
if(sign)mant= -mant;
return(ldexp(mant,exp-(VQ_FMAN-1)-VQ_FEXP_BIAS));
}
int main(void) {
long src[] = {
-535612621,
-535822336,
-537919488,
1610612736,
1609564160,
1611661312,
1611871027,
+2147483647,
-2147483648,
};
int size = sizeof(src) / sizeof(*src);
for (int i = 0; i < size; i++) {
printf("testpack(%ld, %f);\n", src[i], _float32_unpack(src[i]));
}
return 0;
}
| [
"mohayonao@gmail.com"
] | mohayonao@gmail.com |
a839321ef34ba3656785d8f38e30a6b5822a7c39 | df91a067ebe74199b0f8b8248ef3a3652e26b3ac | /src/libevent_test/hhdr.h | cd351ca10ee03bc7848319f827e146d590dd34ee | [] | no_license | xjp342023125/Code | 6aba3ca9122f07bc49417365153220a50d1f9fb5 | a6f6ae371fd157127b18b959c69ce0c2c76e6a22 | refs/heads/master | 2021-08-06T20:28:53.867527 | 2021-07-07T08:09:36 | 2021-07-07T08:09:36 | 79,343,868 | 5 | 2 | null | null | null | null | UTF-8 | C | false | false | 286 | h | #pragma pack(1)
#pragma warning(disable: 4200)
struct f_msg
{
int sum_len;
int nType;
char sz[];
};
struct up_log
{
char szpath[256];
char szname[100];
int len;
char sz[];
};
struct up_log_ret
{
int ret;
};
#pragma warning(default: 4200)
#pragma pack() | [
"qt00@qq.com"
] | qt00@qq.com |
5c4615af711d78749e7655860f7dee535986c2cd | 41f705c9892a3d339d72a546803340a6ab41af56 | /code/KEA128_BLDC_Sensorless/Sources/Peripherals/osc.c | b1c4882a295e2346587ec52aa7070c043563bc18 | [] | no_license | reyno123456/bldc_kea128 | edae81adb7c7977967739a9257a0250a4bb7551d | 3f25def01cb2149d1062a8aa90876b1466ab586d | refs/heads/master | 2021-08-27T20:22:10.757724 | 2017-11-28T07:12:08 | 2017-11-28T07:12:08 | 112,298,841 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,176 | c | /*******************************************************************************
*
* (c) Copyright 2014 Freescale Semiconductor
*
****************************************************************************//*!
*
* @file osc.c
*
* @author B06050
*
* @version 1.0.2.0
*
* @date Jul-3-2014
*
* @brief Oscillator SW module source file.
*
*******************************************************************************/
#include "osc.h"
/*******************************************************************************
* Global functions
*******************************************************************************/
/*******************************************************************************
*
* Function: void OSC_Init(void)
*
* Description: Initializes and enables Oscillator module:
* - Low-power mode
* - High frequency range of 4-24 MHz
*
*******************************************************************************/
void OSC_Init(void)
{
/* Enable OSC */
OSC_CR = 0x94;
/* Wait for OSC to be initialized */
while((OSC_CR & OSC_CR_OSCINIT_MASK) == 0)
{
}
}
| [
"reyno.wu@foxmail.com"
] | reyno.wu@foxmail.com |
020799e981d7775de3706e703051a5be75d66e8a | b77e54131dede28b3153d6c67f6c061ac739b7d7 | /bionic/libc/include/sys/linux-syscalls.h | 39fea219e1efdf3c0a9c25d2be4844346a18763b | [
"LicenseRef-scancode-warranty-disclaimer",
"SunPro",
"BSD-3-Clause",
"CMU-Mach",
"HPND",
"ISC",
"LicenseRef-scancode-other-permissive",
"LicenseRef-scancode-ibm-dhcp",
"BSD-2-Clause",
"Martin-Birgmeier"
] | permissive | JeffreyLau/JJWD-K8_icsCream | 2319be6b9b2abd5e9d4da1b5efe91a472539c6c2 | a9790f6edf973d9e6b102f9be89c7b7f883f1cb2 | refs/heads/master | 2021-01-19T11:37:22.502930 | 2013-06-27T06:05:01 | 2013-06-27T06:05:01 | 10,987,138 | 4 | 2 | null | null | null | null | UTF-8 | C | false | false | 19,501 | h | /* auto-generated by gensyscalls.py, do not touch */
#ifndef _BIONIC_LINUX_SYSCALLS_H_
#if !defined __ASM_ARM_UNISTD_H && !defined __ASM_I386_UNISTD_H
#if defined __arm__ && !defined __ARM_EABI__ && !defined __thumb__
# define __NR_SYSCALL_BASE 0x900000
#else
# define __NR_SYSCALL_BASE 0
#endif
#define __NR_exit (__NR_SYSCALL_BASE + 1)
#define __NR_fork (__NR_SYSCALL_BASE + 2)
#define __NR_clone (__NR_SYSCALL_BASE + 120)
#define __NR_execve (__NR_SYSCALL_BASE + 11)
#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
#define __NR_gettid (__NR_SYSCALL_BASE + 224)
#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
#define __NR_getppid (__NR_SYSCALL_BASE + 64)
#define __NR_setsid (__NR_SYSCALL_BASE + 66)
#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
#define __NR_brk (__NR_SYSCALL_BASE + 45)
#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
#define __NR_chroot (__NR_SYSCALL_BASE + 61)
#define __NR_prctl (__NR_SYSCALL_BASE + 172)
#define __NR_capget (__NR_SYSCALL_BASE + 184)
#define __NR_capset (__NR_SYSCALL_BASE + 185)
#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
#define __NR_acct (__NR_SYSCALL_BASE + 51)
#define __NR_read (__NR_SYSCALL_BASE + 3)
#define __NR_write (__NR_SYSCALL_BASE + 4)
#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
#define __NR_open (__NR_SYSCALL_BASE + 5)
#define __NR_close (__NR_SYSCALL_BASE + 6)
#define __NR_lseek (__NR_SYSCALL_BASE + 19)
#define __NR__llseek (__NR_SYSCALL_BASE + 140)
#define __NR_getpid (__NR_SYSCALL_BASE + 20)
#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
#define __NR_munmap (__NR_SYSCALL_BASE + 91)
#define __NR_mremap (__NR_SYSCALL_BASE + 163)
#define __NR_msync (__NR_SYSCALL_BASE + 144)
#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
#define __NR_mlock (__NR_SYSCALL_BASE + 150)
#define __NR_munlock (__NR_SYSCALL_BASE + 151)
#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
#define __NR_readv (__NR_SYSCALL_BASE + 145)
#define __NR_writev (__NR_SYSCALL_BASE + 146)
#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
#define __NR_flock (__NR_SYSCALL_BASE + 143)
#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
#define __NR_dup (__NR_SYSCALL_BASE + 41)
#define __NR_pipe (__NR_SYSCALL_BASE + 42)
#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
#define __NR__newselect (__NR_SYSCALL_BASE + 142)
#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
#define __NR_fsync (__NR_SYSCALL_BASE + 118)
#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
#define __NR_sync (__NR_SYSCALL_BASE + 36)
#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
#define __NR_link (__NR_SYSCALL_BASE + 9)
#define __NR_unlink (__NR_SYSCALL_BASE + 10)
#define __NR_chdir (__NR_SYSCALL_BASE + 12)
#define __NR_mknod (__NR_SYSCALL_BASE + 14)
#define __NR_chmod (__NR_SYSCALL_BASE + 15)
#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
#define __NR_mount (__NR_SYSCALL_BASE + 21)
#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
#define __NR_readlink (__NR_SYSCALL_BASE + 85)
#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
#define __NR_rename (__NR_SYSCALL_BASE + 38)
#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
#define __NR_access (__NR_SYSCALL_BASE + 33)
#define __NR_symlink (__NR_SYSCALL_BASE + 83)
#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
#define __NR_truncate (__NR_SYSCALL_BASE + 92)
#define __NR_pause (__NR_SYSCALL_BASE + 29)
#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
#define __NR_times (__NR_SYSCALL_BASE + 43)
#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
#define __NR_uname (__NR_SYSCALL_BASE + 122)
#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
#define __NR_umask (__NR_SYSCALL_BASE + 60)
#define __NR_reboot (__NR_SYSCALL_BASE + 88)
#define __NR_syslog (__NR_SYSCALL_BASE + 103)
#define __NR_init_module (__NR_SYSCALL_BASE + 128)
#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
#define __NR_syslog (__NR_SYSCALL_BASE + 103)
#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
#define __NR_personality (__NR_SYSCALL_BASE + 136)
#define __NR_futex (__NR_SYSCALL_BASE + 240)
#define __NR_poll (__NR_SYSCALL_BASE + 168)
#ifdef __arm__
#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
#define __NR_waitid (__NR_SYSCALL_BASE + 280)
#define __NR_vfork (__NR_SYSCALL_BASE + 190)
#define __NR_openat (__NR_SYSCALL_BASE + 322)
#define __NR_madvise (__NR_SYSCALL_BASE + 220)
#define __NR_mincore (__NR_SYSCALL_BASE + 219)
#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
#define __NR_renameat (__NR_SYSCALL_BASE + 329)
#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
#define __NR_utimes (__NR_SYSCALL_BASE + 269)
#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
#define __NR_socket (__NR_SYSCALL_BASE + 281)
#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
#define __NR_bind (__NR_SYSCALL_BASE + 282)
#define __NR_connect (__NR_SYSCALL_BASE + 283)
#define __NR_listen (__NR_SYSCALL_BASE + 284)
#define __NR_accept (__NR_SYSCALL_BASE + 285)
#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
#define __NR_sendto (__NR_SYSCALL_BASE + 290)
#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
#define __NR_ARM_set_tls (__NR_SYSCALL_BASE + 983045)
#define __NR_ARM_cacheflush (__NR_SYSCALL_BASE + 983042)
#define __NR_swapon (__NR_SYSCALL_BASE+ 87)
#define __NR_swapoff (__NR_SYSCALL_BASE+115)
#endif
#ifdef __i386__
#define __NR_exit_group (__NR_SYSCALL_BASE + 252)
#define __NR_waitpid (__NR_SYSCALL_BASE + 7)
#define __NR_waitid (__NR_SYSCALL_BASE + 284)
#define __NR_kill (__NR_SYSCALL_BASE + 37)
#define __NR_tkill (__NR_SYSCALL_BASE + 238)
#define __NR_set_thread_area (__NR_SYSCALL_BASE + 243)
#define __NR_openat (__NR_SYSCALL_BASE + 295)
#define __NR_madvise (__NR_SYSCALL_BASE + 219)
#define __NR_mincore (__NR_SYSCALL_BASE + 218)
#define __NR_pipe2 (__NR_SYSCALL_BASE + 331)
#define __NR_getdents64 (__NR_SYSCALL_BASE + 220)
#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 269)
#define __NR_fstatat64 (__NR_SYSCALL_BASE + 300)
#define __NR_mkdirat (__NR_SYSCALL_BASE + 296)
#define __NR_fchownat (__NR_SYSCALL_BASE + 298)
#define __NR_fchmodat (__NR_SYSCALL_BASE + 306)
#define __NR_renameat (__NR_SYSCALL_BASE + 302)
#define __NR_unlinkat (__NR_SYSCALL_BASE + 301)
#define __NR_statfs64 (__NR_SYSCALL_BASE + 268)
#define __NR_clock_gettime (__NR_SYSCALL_BASE + 265)
#define __NR_clock_settime (__NR_SYSCALL_BASE + 264)
#define __NR_clock_getres (__NR_SYSCALL_BASE + 266)
#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 267)
#define __NR_timer_create (__NR_SYSCALL_BASE + 259)
#define __NR_timer_settime (__NR_SYSCALL_BASE + 260)
#define __NR_timer_gettime (__NR_SYSCALL_BASE + 261)
#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 262)
#define __NR_timer_delete (__NR_SYSCALL_BASE + 263)
#define __NR_utimes (__NR_SYSCALL_BASE + 271)
#define __NR_utimensat (__NR_SYSCALL_BASE + 320)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_getcpu (__NR_SYSCALL_BASE + 318)
#define __NR_ioprio_set (__NR_SYSCALL_BASE + 289)
#define __NR_ioprio_get (__NR_SYSCALL_BASE + 290)
#define __NR_epoll_create (__NR_SYSCALL_BASE + 254)
#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 255)
#define __NR_epoll_wait (__NR_SYSCALL_BASE + 256)
#define __NR_inotify_init (__NR_SYSCALL_BASE + 291)
#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 292)
#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 293)
#define __NR_eventfd2 (__NR_SYSCALL_BASE + 328)
#endif
#if defined(__SH3__) || defined(__SH4__)
#define __NR_exit_group (__NR_SYSCALL_BASE + 252)
#define __NR_waitpid (__NR_SYSCALL_BASE + 7)
#define __NR_waitid (__NR_SYSCALL_BASE + 284)
#define __NR_kill (__NR_SYSCALL_BASE + 37)
#define __NR_tkill (__NR_SYSCALL_BASE + 238)
#define __NR_set_thread_area (__NR_SYSCALL_BASE + 243)
#define __NR_vfork (__NR_SYSCALL_BASE + 190)
#define __NR_openat (__NR_SYSCALL_BASE + 295)
#define __NR_madvise (__NR_SYSCALL_BASE + 219)
#define __NR_mincore (__NR_SYSCALL_BASE + 218)
#define __NR_pipe2 (__NR_SYSCALL_BASE + 331)
#define __NR_getdents64 (__NR_SYSCALL_BASE + 220)
#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 269)
#define __NR_fstatat64 (__NR_SYSCALL_BASE + 300)
#define __NR_mkdirat (__NR_SYSCALL_BASE + 296)
#define __NR_fchownat (__NR_SYSCALL_BASE + 298)
#define __NR_fchmodat (__NR_SYSCALL_BASE + 306)
#define __NR_renameat (__NR_SYSCALL_BASE + 302)
#define __NR_unlinkat (__NR_SYSCALL_BASE + 301)
#define __NR_statfs64 (__NR_SYSCALL_BASE + 268)
#define __NR_clock_gettime (__NR_SYSCALL_BASE + 265)
#define __NR_clock_settime (__NR_SYSCALL_BASE + 264)
#define __NR_clock_getres (__NR_SYSCALL_BASE + 266)
#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 267)
#define __NR_timer_create (__NR_SYSCALL_BASE + 259)
#define __NR_timer_settime (__NR_SYSCALL_BASE + 260)
#define __NR_timer_gettime (__NR_SYSCALL_BASE + 261)
#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 262)
#define __NR_timer_delete (__NR_SYSCALL_BASE + 263)
#define __NR_utimes (__NR_SYSCALL_BASE + 271)
#define __NR_utimensat (__NR_SYSCALL_BASE + 320)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
#define __NR_getcpu (__NR_SYSCALL_BASE + 318)
#define __NR_ioprio_set (__NR_SYSCALL_BASE + 288)
#define __NR_ioprio_get (__NR_SYSCALL_BASE + 289)
#define __NR_epoll_create (__NR_SYSCALL_BASE + 254)
#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 255)
#define __NR_epoll_wait (__NR_SYSCALL_BASE + 256)
#define __NR_inotify_init (__NR_SYSCALL_BASE + 290)
#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 291)
#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 292)
#define __NR_eventfd2 (__NR_SYSCALL_BASE + 328)
#endif
#endif
#endif /* _BIONIC_LINUX_SYSCALLS_H_ */
| [
"meto.jeffrey@gmail.com"
] | meto.jeffrey@gmail.com |
b0b1bff7442ffaf7c1d3b562d1b3e5a5d8293fe7 | 2a76e1899a814a2aa9bae18cc9bb9cc73372bba9 | /testing/icgen/random_verschillende_resoluties_N-GenIC/gadget3_64/subfind_cont.c | 4b761d5f8fdb1f112f1f46ea4f3e01da7d2193d2 | [
"Apache-2.0"
] | permissive | egpbos/egp | 588ab3d18eef2e9bdae60c571dd602924bab6932 | 5e82c2de9e6884795b4ee89f2b15ed5dde70388f | refs/heads/master | 2020-04-25T10:45:57.675997 | 2020-01-27T15:54:14 | 2020-01-27T15:54:14 | 172,720,830 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 10,389 | c | #include <mpi.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <gsl/gsl_math.h>
#include <sys/stat.h>
#include <sys/types.h>
#include "allvars.h"
#include "proto.h"
#ifdef SUBFIND
#include "fof.h"
#include "subfind.h"
/*! Structure for communication during the density computation. Holds data that is sent to other processors.
*/
static struct contamdata_in
{
MyDouble Pos[3];
MyFloat R200;
int NodeList[NODELISTLENGTH];
}
*ContamIn, *ContamGet;
static struct contamdata_out
{
double ContaminationMass;
int ContaminationLen;
}
*ContamResult, *ContamOut;
void subfind_contamination(void)
{
int i, j, ndone, ndone_flag, dummy, count;
int ngrp, sendTask, recvTask, place, nexport, nimport;
struct unbind_data *d;
d = (struct unbind_data *) mymalloc(NumPart * sizeof(struct unbind_data));
for(i = 0, count = 0; i < NumPart; i++)
#ifdef DENSITY_SPLIT_BY_TYPE
if(!((1 << P[i].Type) & (DENSITY_SPLIT_BY_TYPE)))
#else
if(!((1 << P[i].Type) & (FOF_PRIMARY_LINK_TYPES)))
#endif
d[count++].index = i;
force_treebuild(count, d); /* construct tree only with boundary particles */
myfree(d);
/* allocate buffers to arrange communication */
All.BunchSize =
(int) ((All.BufferSize * 1024 * 1024) / (sizeof(struct data_index) + sizeof(struct data_nodelist) +
sizeof(struct contamdata_in) + sizeof(struct contamdata_out) +
sizemax(sizeof(struct contamdata_in),
sizeof(struct contamdata_out))));
DataIndexTable = (struct data_index *) mymalloc(All.BunchSize * sizeof(struct data_index));
DataNodeList = (struct data_nodelist *) mymalloc(All.BunchSize * sizeof(struct data_nodelist));
/* we will repeat the whole thing for those groups where we didn't converge to a SO radius yet */
i = 0; /* begin with this index */
do
{
for(j = 0; j < NTask; j++)
{
Send_count[j] = 0;
Exportflag[j] = -1;
}
/* do local particles and prepare export list */
for(nexport = 0; i < Ngroups; i++)
{
if(Group[i].R_Mean200 > 0)
{
if(subfind_contamination_evaluate(i, 0, &nexport, Send_count) < 0)
break;
}
else
{
Group[i].ContaminationLen = 0;
Group[i].ContaminationMass = 0;
}
}
qsort(DataIndexTable, nexport, sizeof(struct data_index), data_index_compare);
MPI_Allgather(Send_count, NTask, MPI_INT, Sendcount_matrix, NTask, MPI_INT, MPI_COMM_WORLD);
for(j = 0, nimport = 0, Recv_offset[0] = 0, Send_offset[0] = 0; j < NTask; j++)
{
Recv_count[j] = Sendcount_matrix[j * NTask + ThisTask];
nimport += Recv_count[j];
if(j > 0)
{
Send_offset[j] = Send_offset[j - 1] + Send_count[j - 1];
Recv_offset[j] = Recv_offset[j - 1] + Recv_count[j - 1];
}
}
ContamGet = (struct contamdata_in *) mymalloc(nimport * sizeof(struct contamdata_in));
ContamIn = (struct contamdata_in *) mymalloc(nexport * sizeof(struct contamdata_in));
/* prepare particle data for export */
for(j = 0; j < nexport; j++)
{
place = DataIndexTable[j].Index;
ContamIn[j].Pos[0] = Group[place].Pos[0];
ContamIn[j].Pos[1] = Group[place].Pos[1];
ContamIn[j].Pos[2] = Group[place].Pos[2];
ContamIn[j].R200 = Group[place].R_Mean200;
memcpy(ContamIn[j].NodeList,
DataNodeList[DataIndexTable[j].IndexGet].NodeList, NODELISTLENGTH * sizeof(int));
}
/* exchange data */
for(ngrp = 1; ngrp < (1 << PTask); ngrp++)
{
sendTask = ThisTask;
recvTask = ThisTask ^ ngrp;
if(recvTask < NTask)
{
if(Send_count[recvTask] > 0 || Recv_count[recvTask] > 0)
{
/* get the data */
MPI_Sendrecv(&ContamIn[Send_offset[recvTask]],
Send_count[recvTask] * sizeof(struct contamdata_in), MPI_BYTE,
recvTask, TAG_DENS_A,
&ContamGet[Recv_offset[recvTask]],
Recv_count[recvTask] * sizeof(struct contamdata_in), MPI_BYTE,
recvTask, TAG_DENS_A, MPI_COMM_WORLD, MPI_STATUS_IGNORE);
}
}
}
myfree(ContamIn);
ContamResult = (struct contamdata_out *) mymalloc(nimport * sizeof(struct contamdata_out));
ContamOut = (struct contamdata_out *) mymalloc(nexport * sizeof(struct contamdata_out));
/* now do the locations that were sent to us */
for(j = 0; j < nimport; j++)
subfind_contamination_evaluate(j, 1, &dummy, &dummy);
if(i >= Ngroups)
ndone_flag = 1;
else
ndone_flag = 0;
MPI_Allreduce(&ndone_flag, &ndone, 1, MPI_INT, MPI_SUM, MPI_COMM_WORLD);
/* get the result */
for(ngrp = 1; ngrp < (1 << PTask); ngrp++)
{
sendTask = ThisTask;
recvTask = ThisTask ^ ngrp;
if(recvTask < NTask)
{
if(Send_count[recvTask] > 0 || Recv_count[recvTask] > 0)
{
/* send the results */
MPI_Sendrecv(&ContamResult[Recv_offset[recvTask]],
Recv_count[recvTask] * sizeof(struct contamdata_out),
MPI_BYTE, recvTask, TAG_DENS_B,
&ContamOut[Send_offset[recvTask]],
Send_count[recvTask] * sizeof(struct contamdata_out),
MPI_BYTE, recvTask, TAG_DENS_B, MPI_COMM_WORLD, MPI_STATUS_IGNORE);
}
}
}
/* add the result to the local particles */
for(j = 0; j < nexport; j++)
{
place = DataIndexTable[j].Index;
Group[place].ContaminationLen += ContamOut[j].ContaminationLen;
Group[place].ContaminationMass += ContamOut[j].ContaminationMass;
}
myfree(ContamOut);
myfree(ContamResult);
myfree(ContamGet);
}
while(ndone < NTask);
myfree(DataNodeList);
myfree(DataIndexTable);
}
/*! This function represents the core of the SPH density computation. The
* target particle may either be local, or reside in the communication
* buffer.
*/
int subfind_contamination_evaluate(int target, int mode, int *nexport, int *nsend_local)
{
int startnode, listindex = 0;
double h, mass, masssum;
int count, countsum;
MyDouble *pos;
masssum = 0;
countsum = 0;
if(mode == 0)
{
pos = Group[target].Pos;
h = Group[target].R_Mean200;
}
else
{
pos = ContamGet[target].Pos;
h = ContamGet[target].R200;
}
if(mode == 0)
{
startnode = All.MaxPart; /* root node */
}
else
{
startnode = ContamGet[target].NodeList[0];
startnode = Nodes[startnode].u.d.nextnode; /* open it */
}
while(startnode >= 0)
{
while(startnode >= 0)
{
count =
subfind_contamination_treefind(pos, h, target, &startnode, mode, nexport, nsend_local, &mass);
if(count < 0)
return -1;
masssum += mass;
countsum += count;
}
if(mode == 1)
{
listindex++;
if(listindex < NODELISTLENGTH)
{
startnode = ContamGet[target].NodeList[listindex];
if(startnode >= 0)
startnode = Nodes[startnode].u.d.nextnode; /* open it */
}
}
}
if(mode == 0)
{
Group[target].ContaminationMass = masssum;
Group[target].ContaminationLen = countsum;
}
else
{
ContamResult[target].ContaminationMass = masssum;
ContamResult[target].ContaminationLen = countsum;
}
return 0;
}
int subfind_contamination_treefind(MyDouble searchcenter[3], MyFloat hsml, int target, int *startnode,
int mode, int *nexport, int *nsend_local, double *Mass)
{
int no, p, task, nexport_save;
struct NODE *current;
double mass;
int count;
MyDouble dx, dy, dz, dist, r2;
#ifdef PERIODIC
MyDouble xtmp;
#endif
nexport_save = *nexport;
mass = 0;
count = 0;
no = *startnode;
while(no >= 0)
{
if(no < All.MaxPart) /* single particle */
{
p = no;
no = Nextnode[no];
dist = hsml;
dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]);
if(dz > dist)
continue;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
mass += P[p].Mass;
count++;
}
else
{
if(no >= All.MaxPart + MaxNodes) /* pseudo particle */
{
if(mode == 1)
endrun(12312);
if(mode == 0)
{
if(Exportflag[task = DomainTask[no - (All.MaxPart + MaxNodes)]] != target)
{
Exportflag[task] = target;
Exportnodecount[task] = NODELISTLENGTH;
}
if(Exportnodecount[task] == NODELISTLENGTH)
{
if(*nexport >= All.BunchSize)
{
*nexport = nexport_save;
if(nexport_save == 0)
endrun(13005); /* in this case, the buffer is too small to process even a single particle */
for(task = 0; task < NTask; task++)
nsend_local[task] = 0;
for(no = 0; no < nexport_save; no++)
nsend_local[DataIndexTable[no].Task]++;
return -1;
}
Exportnodecount[task] = 0;
Exportindex[task] = *nexport;
DataIndexTable[*nexport].Task = task;
DataIndexTable[*nexport].Index = target;
DataIndexTable[*nexport].IndexGet = *nexport;
*nexport = *nexport + 1;
nsend_local[task]++;
}
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]++] =
DomainNodeIndex[no - (All.MaxPart + MaxNodes)];
if(Exportnodecount[task] < NODELISTLENGTH)
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]] = -1;
}
no = Nextnode[no - MaxNodes];
continue;
}
current = &Nodes[no];
if(mode == 1)
{
if(current->u.d.bitflags & (1 << BITFLAG_TOPLEVEL)) /* we reached a top-level node again, which means that we are done with the branch */
{
*startnode = -1;
*Mass = mass;
return count;
}
}
no = current->u.d.sibling; /* in case the node can be discarded */
dist = hsml + 0.5 * current->len;;
dx = NGB_PERIODIC_LONG_X(current->center[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(current->center[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(current->center[2] - searchcenter[2]);
if(dz > dist)
continue;
/* now test against the minimal sphere enclosing everything */
dist += FACT1 * current->len;
if((r2 = (dx * dx + dy * dy + dz * dz)) > dist * dist)
continue;
no = current->u.d.nextnode; /* ok, we need to open the node */
}
}
*startnode = -1;
*Mass = mass;
return count;
}
#endif
| [
"pbos@astro.rug.nl"
] | pbos@astro.rug.nl |
47621517ba6449a5db63037d58bfd25a60cbbbea | dfede5776cd9aeb6a814d61a4179206af2578f4e | /RPI/OPSYS15F/notes/09-10-15/fd-open-redirect.c | 937341169f2cf7849a340daaa87258ec3dd753b0 | [] | no_license | chocolatemelt/misc | ecc4d5903565313519358f96c4d2e165c89444bd | e1044f3e0b3e14b16c03c51d3e82ced2c10a5f9f | refs/heads/master | 2021-06-23T20:43:53.226758 | 2017-08-27T20:56:36 | 2017-08-27T20:56:36 | 32,169,548 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 1,340 | c | /* fd-open-redirect.c */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
int main()
{
char name[80];
strcpy( name, "testfile.txt" );
/* name: "testfile.txt\0" */
/* ^^ */
/* the '\0' is a single character */
close( 1 ); /* close stdout */
int fd = open( name, O_WRONLY | O_CREAT | O_TRUNC );
if ( fd == -1 )
{
perror( "open() failed" );
return EXIT_FAILURE;
}
/* fd table (BEFORE open() call):
0 stdin
1
2 stderr
fd table (AFTER open() call):
0 stdin
1 testfile.txt (O_RDONLY)
2 stderr
*/
/* this line of output is buffered to go to fd 1,
which is testfile.txt */
printf( "fd for file %s is %d\n", name, fd );
/* the above line of output will not get to the file
unless the following fflush() call is made: */
fflush( NULL );
char buffer[81];
sprintf( buffer, "WRITING TO FD %d\n", fd );
int rc = write( fd, buffer, strlen( buffer ) );
printf( "write() returned %d\n", rc );
if ( rc == -1 )
{
perror( "write() failed" );
return EXIT_FAILURE;
}
close( fd ); /* remove entry 1 from the fd table */
return EXIT_SUCCESS;
}
| [
"kzhaaang@gmail.com"
] | kzhaaang@gmail.com |
7ec5d97f6807bd944959e7489c90e9300758713a | ed28e9fc5011bad460f134eb5fe344e18983d0e3 | /slprj/_cprj/m_EXjWXzdNbMLBy0VqWnKjsC.h | c8e4ad1c4fe609417ac22aa715f1a3a55df43123 | [] | no_license | seccortessa/sim_files_tesis | e2697a56533d40ebbaa344125a16fc5c2f62b0c4 | a1bb6904bb11b105b7c9523f192f98206a8ab799 | refs/heads/master | 2023-01-31T03:00:18.353259 | 2020-12-12T04:02:00 | 2020-12-12T04:02:00 | 298,026,509 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,117 | h | #ifndef __EXjWXzdNbMLBy0VqWnKjsC_h__
#define __EXjWXzdNbMLBy0VqWnKjsC_h__
/* Include files */
#include "simstruc.h"
#include "rtwtypes.h"
#include "multiword_types.h"
#include "slexec_vm_zc_functions.h"
#include "slexec_vm_simstruct_bridge.h"
#include "sl_sfcn_cov/sl_sfcn_cov_bridge.h"
/* Type Definitions */
#ifndef struct_tag_PMfBDzoakfdM9QAdfx2o6D
#define struct_tag_PMfBDzoakfdM9QAdfx2o6D
struct tag_PMfBDzoakfdM9QAdfx2o6D
{
uint32_T f1[8];
};
#endif /*struct_tag_PMfBDzoakfdM9QAdfx2o6D*/
#ifndef typedef_cell_wrap
#define typedef_cell_wrap
typedef struct tag_PMfBDzoakfdM9QAdfx2o6D cell_wrap;
#endif /*typedef_cell_wrap*/
#ifndef struct_tag_ypl2qxsMwxoAIyqbqeICFF
#define struct_tag_ypl2qxsMwxoAIyqbqeICFF
struct tag_ypl2qxsMwxoAIyqbqeICFF
{
int32_T isInitialized;
cell_wrap inputVarSize[1];
};
#endif /*struct_tag_ypl2qxsMwxoAIyqbqeICFF*/
#ifndef typedef_codertarget_internal_androidDataDisplay
#define typedef_codertarget_internal_androidDataDisplay
typedef struct tag_ypl2qxsMwxoAIyqbqeICFF
codertarget_internal_androidDataDisplay;
#endif /*typedef_codertarget_internal_androidDataDisplay*/
#ifndef struct_tag_AF9oIJqGDr0Kstxao4iUJE
#define struct_tag_AF9oIJqGDr0Kstxao4iUJE
struct tag_AF9oIJqGDr0Kstxao4iUJE
{
real_T f1[2];
};
#endif /*struct_tag_AF9oIJqGDr0Kstxao4iUJE*/
#ifndef typedef_b_cell_wrap
#define typedef_b_cell_wrap
typedef struct tag_AF9oIJqGDr0Kstxao4iUJE b_cell_wrap;
#endif /*typedef_b_cell_wrap*/
#ifndef struct_tag_R92EHBRJBtqsluQDZ25dkE
#define struct_tag_R92EHBRJBtqsluQDZ25dkE
struct tag_R92EHBRJBtqsluQDZ25dkE
{
char_T f1[7];
};
#endif /*struct_tag_R92EHBRJBtqsluQDZ25dkE*/
#ifndef typedef_c_cell_wrap
#define typedef_c_cell_wrap
typedef struct tag_R92EHBRJBtqsluQDZ25dkE c_cell_wrap;
#endif /*typedef_c_cell_wrap*/
#ifndef struct_tag_bum8ARtRRmNMdgv1XDJxMG
#define struct_tag_bum8ARtRRmNMdgv1XDJxMG
struct tag_bum8ARtRRmNMdgv1XDJxMG
{
char_T f1[4];
char_T f2[6];
char_T f3[6];
char_T f4[6];
char_T f5[8];
char_T f6[7];
char_T f7;
real_T f8;
};
#endif /*struct_tag_bum8ARtRRmNMdgv1XDJxMG*/
#ifndef typedef_cell
#define typedef_cell
typedef struct tag_bum8ARtRRmNMdgv1XDJxMG cell;
#endif /*typedef_cell*/
#ifndef struct_tag_JCMHh5upQJQLkLyj4IvLp
#define struct_tag_JCMHh5upQJQLkLyj4IvLp
struct tag_JCMHh5upQJQLkLyj4IvLp
{
char_T f1[6];
};
#endif /*struct_tag_JCMHh5upQJQLkLyj4IvLp*/
#ifndef typedef_d_cell_wrap
#define typedef_d_cell_wrap
typedef struct tag_JCMHh5upQJQLkLyj4IvLp d_cell_wrap;
#endif /*typedef_d_cell_wrap*/
#ifndef struct_tag_UX05GARjqsuR9QofOrwOSD
#define struct_tag_UX05GARjqsuR9QofOrwOSD
struct tag_UX05GARjqsuR9QofOrwOSD
{
char_T f1[27];
char_T f2[21];
char_T f3[26];
};
#endif /*struct_tag_UX05GARjqsuR9QofOrwOSD*/
#ifndef typedef_b_cell
#define typedef_b_cell
typedef struct tag_UX05GARjqsuR9QofOrwOSD b_cell;
#endif /*typedef_b_cell*/
#ifndef struct_tag_uo7PCp2pQzQ8uFrW43NfEH
#define struct_tag_uo7PCp2pQzQ8uFrW43NfEH
struct tag_uo7PCp2pQzQ8uFrW43NfEH
{
char_T f1[28];
char_T f2[22];
char_T f3[35];
char_T f4[26];
char_T f5[36];
char_T f6[39];
};
#endif /*struct_tag_uo7PCp2pQzQ8uFrW43NfEH*/
#ifndef typedef_c_cell
#define typedef_c_cell
typedef struct tag_uo7PCp2pQzQ8uFrW43NfEH c_cell;
#endif /*typedef_c_cell*/
#ifndef struct_tag_i3Yy1eMafhQ5Hb1YroYw5E
#define struct_tag_i3Yy1eMafhQ5Hb1YroYw5E
struct tag_i3Yy1eMafhQ5Hb1YroYw5E
{
b_cell_wrap _data;
};
#endif /*struct_tag_i3Yy1eMafhQ5Hb1YroYw5E*/
#ifndef typedef_s_i3Yy1eMafhQ5Hb1YroYw5E
#define typedef_s_i3Yy1eMafhQ5Hb1YroYw5E
typedef struct tag_i3Yy1eMafhQ5Hb1YroYw5E s_i3Yy1eMafhQ5Hb1YroYw5E;
#endif /*typedef_s_i3Yy1eMafhQ5Hb1YroYw5E*/
#ifndef struct_tag_DyxoIdtJXNTXJqriOfucUD
#define struct_tag_DyxoIdtJXNTXJqriOfucUD
struct tag_DyxoIdtJXNTXJqriOfucUD
{
c_cell_wrap _data;
};
#endif /*struct_tag_DyxoIdtJXNTXJqriOfucUD*/
#ifndef typedef_s_DyxoIdtJXNTXJqriOfucUD
#define typedef_s_DyxoIdtJXNTXJqriOfucUD
typedef struct tag_DyxoIdtJXNTXJqriOfucUD s_DyxoIdtJXNTXJqriOfucUD;
#endif /*typedef_s_DyxoIdtJXNTXJqriOfucUD*/
#ifndef struct_tag_pMw6X4fVVv2bXe1AOu48yC
#define struct_tag_pMw6X4fVVv2bXe1AOu48yC
struct tag_pMw6X4fVVv2bXe1AOu48yC
{
cell _data;
};
#endif /*struct_tag_pMw6X4fVVv2bXe1AOu48yC*/
#ifndef typedef_s_pMw6X4fVVv2bXe1AOu48yC
#define typedef_s_pMw6X4fVVv2bXe1AOu48yC
typedef struct tag_pMw6X4fVVv2bXe1AOu48yC s_pMw6X4fVVv2bXe1AOu48yC;
#endif /*typedef_s_pMw6X4fVVv2bXe1AOu48yC*/
#ifndef struct_tag_Y6XvlYTysWyABOiCRpJ3lH
#define struct_tag_Y6XvlYTysWyABOiCRpJ3lH
struct tag_Y6XvlYTysWyABOiCRpJ3lH
{
d_cell_wrap _data;
};
#endif /*struct_tag_Y6XvlYTysWyABOiCRpJ3lH*/
#ifndef typedef_s_Y6XvlYTysWyABOiCRpJ3lH
#define typedef_s_Y6XvlYTysWyABOiCRpJ3lH
typedef struct tag_Y6XvlYTysWyABOiCRpJ3lH s_Y6XvlYTysWyABOiCRpJ3lH;
#endif /*typedef_s_Y6XvlYTysWyABOiCRpJ3lH*/
#ifndef struct_tag_6khVZLlzg3270lst7fcoXG
#define struct_tag_6khVZLlzg3270lst7fcoXG
struct tag_6khVZLlzg3270lst7fcoXG
{
b_cell _data;
};
#endif /*struct_tag_6khVZLlzg3270lst7fcoXG*/
#ifndef typedef_s_6khVZLlzg3270lst7fcoXG
#define typedef_s_6khVZLlzg3270lst7fcoXG
typedef struct tag_6khVZLlzg3270lst7fcoXG s_6khVZLlzg3270lst7fcoXG;
#endif /*typedef_s_6khVZLlzg3270lst7fcoXG*/
#ifndef struct_tag_Q9exWnM4P2vFrlJou54v4D
#define struct_tag_Q9exWnM4P2vFrlJou54v4D
struct tag_Q9exWnM4P2vFrlJou54v4D
{
c_cell _data;
};
#endif /*struct_tag_Q9exWnM4P2vFrlJou54v4D*/
#ifndef typedef_s_Q9exWnM4P2vFrlJou54v4D
#define typedef_s_Q9exWnM4P2vFrlJou54v4D
typedef struct tag_Q9exWnM4P2vFrlJou54v4D s_Q9exWnM4P2vFrlJou54v4D;
#endif /*typedef_s_Q9exWnM4P2vFrlJou54v4D*/
#ifndef typedef_InstanceStruct_EXjWXzdNbMLBy0VqWnKjsC
#define typedef_InstanceStruct_EXjWXzdNbMLBy0VqWnKjsC
typedef struct {
SimStruct *S;
codertarget_internal_androidDataDisplay sysobj;
boolean_T sysobj_not_empty;
void *emlrtRootTLSGlobal;
real_T *u0;
} InstanceStruct_EXjWXzdNbMLBy0VqWnKjsC;
#endif /*typedef_InstanceStruct_EXjWXzdNbMLBy0VqWnKjsC*/
/* Named Constants */
/* Variable Declarations */
/* Variable Definitions */
/* Function Declarations */
/* Function Definitions */
extern void method_dispatcher_EXjWXzdNbMLBy0VqWnKjsC(SimStruct *S, int_T method,
void* data);
#endif
| [
"seccortessa@unal.edu.co"
] | seccortessa@unal.edu.co |
87281360205c4e8172a2170fe6b875c0fff8c74f | 4bda80208070befaa2719f0ae3379a2ac5179f20 | /02-linux-2.6.22-lab126/include/linux/usb/composite.h | 95efc89301f16824b17f6d3dedfcd4546e661c6b | [
"MIT"
] | permissive | nahtethan/dxg-display | c8123be88b018ca9cbd5d47c17a5c7b047822edf | 353d8c623042c2de78112d829c26a77378bc8e30 | refs/heads/master | 2021-07-26T16:06:05.524124 | 2020-06-05T16:11:00 | 2020-06-05T16:11:00 | 41,666,422 | 92 | 18 | null | 2016-11-22T03:58:15 | 2015-08-31T09:08:04 | C | UTF-8 | C | false | false | 16,016 | h | /*
* composite.h -- framework for usb gadgets which are composite devices
*
* Copyright (C) 2006-2008 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __LINUX_USB_COMPOSITE_H
#define __LINUX_USB_COMPOSITE_H
/*
* This framework is an optional layer on top of the USB Gadget interface,
* making it easier to build (a) Composite devices, supporting multiple
* functions within any single configuration, and (b) Multi-configuration
* devices, also supporting multiple functions but without necessarily
* having more than one function per configuration.
*
* Example: a device with a single configuration supporting both network
* link and mass storage functions is a composite device. Those functions
* might alternatively be packaged in individual configurations, but in
* the composite model the host can use both functions at the same time.
*/
#include <linux/usb/ch9.h>
#include <linux/usb_gadget.h>
/*
* USB function drivers should return USB_GADGET_DELAYED_STATUS if they
* wish to delay the data/status stages of the control transfer till they
* are ready. The control transfer will then be kept from completing till
* all the function drivers that requested for USB_GADGET_DELAYED_STAUS
* invoke usb_composite_setup_continue().
*/
#define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */
struct usb_configuration;
/**
* struct usb_function - describes one function of a configuration
* @name: For diagnostics, identifies the function.
* @strings: tables of strings, keyed by identifiers assigned during bind()
* and by language IDs provided in control requests
* @descriptors: Table of full (or low) speed descriptors, using interface and
* string identifiers assigned during @bind(). If this pointer is null,
* the function will not be available at full speed (or at low speed).
* @hs_descriptors: Table of high speed descriptors, using interface and
* string identifiers assigned during @bind(). If this pointer is null,
* the function will not be available at high speed.
* @config: assigned when @usb_add_function() is called; this is the
* configuration with which this function is associated.
* @bind: Before the gadget can register, all of its functions bind() to the
* available resources including string and interface identifiers used
* in interface or class descriptors; endpoints; I/O buffers; and so on.
* @unbind: Reverses @bind; called as a side effect of unregistering the
* driver which added this function.
* @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may
* initialize usb_ep.driver data at this time (when it is used).
* Note that setting an interface to its current altsetting resets
* interface state, and that all interfaces have a disabled state.
* @get_alt: Returns the active altsetting. If this is not provided,
* then only altsetting zero is supported.
* @disable: (REQUIRED) Indicates the function should be disabled. Reasons
* include host resetting or reconfiguring the gadget, and disconnection.
* @setup: Used for interface-specific control requests.
* @suspend: Notifies functions when the host stops sending USB traffic.
* @resume: Notifies functions when the host restarts USB traffic.
*
* A single USB function uses one or more interfaces, and should in most
* cases support operation at both full and high speeds. Each function is
* associated by @usb_add_function() with a one configuration; that function
* causes @bind() to be called so resources can be allocated as part of
* setting up a gadget driver. Those resources include endpoints, which
* should be allocated using @usb_ep_autoconfig().
*
* To support dual speed operation, a function driver provides descriptors
* for both high and full speed operation. Except in rare cases that don't
* involve bulk endpoints, each speed needs different endpoint descriptors.
*
* Function drivers choose their own strategies for managing instance data.
* The simplest strategy just declares it "static', which means the function
* can only be activated once. If the function needs to be exposed in more
* than one configuration at a given speed, it needs to support multiple
* usb_function structures (one for each configuration).
*
* A more complex strategy might encapsulate a @usb_function structure inside
* a driver-specific instance structure to allows multiple activations. An
* example of multiple activations might be a CDC ACM function that supports
* two or more distinct instances within the same configuration, providing
* several independent logical data links to a USB host.
*/
struct usb_function {
const char *name;
struct usb_gadget_strings **strings;
struct usb_descriptor_header **descriptors;
struct usb_descriptor_header **hs_descriptors;
struct usb_configuration *config;
/* REVISIT: bind() functions can be marked __init, which
* makes trouble for section mismatch analysis. See if
* we can't restructure things to avoid mismatching.
* Related: unbind() may kfree() but bind() won't...
*/
/* configuration management: bind/unbind */
int (*bind)(struct usb_configuration *,
struct usb_function *);
void (*unbind)(struct usb_configuration *,
struct usb_function *);
/* runtime state management */
int (*set_alt)(struct usb_function *,
unsigned interface, unsigned alt);
int (*get_alt)(struct usb_function *,
unsigned interface);
void (*disable)(struct usb_function *);
int (*setup)(struct usb_function *,
const struct usb_ctrlrequest *);
void (*suspend)(struct usb_function *);
void (*resume)(struct usb_function *);
/* private: */
/* internals */
struct list_head list;
DECLARE_BITMAP(endpoints, 32);
};
int usb_add_function(struct usb_configuration *, struct usb_function *);
int usb_function_deactivate(struct usb_function *);
int usb_function_activate(struct usb_function *);
int usb_interface_id(struct usb_configuration *, struct usb_function *);
/**
* ep_choose - select descriptor endpoint at current device speed
* @g: gadget, connected and running at some speed
* @hs: descriptor to use for high speed operation
* @fs: descriptor to use for full or low speed operation
*/
static inline struct usb_endpoint_descriptor *
ep_choose(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
struct usb_endpoint_descriptor *fs)
{
if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
return hs;
return fs;
}
#define MAX_CONFIG_INTERFACES 16 /* arbitrary; max 255 */
/**
* struct usb_configuration - represents one gadget configuration
* @label: For diagnostics, describes the configuration.
* @strings: Tables of strings, keyed by identifiers assigned during @bind()
* and by language IDs provided in control requests.
* @descriptors: Table of descriptors preceding all function descriptors.
* Examples include OTG and vendor-specific descriptors.
* @unbind: Reverses @bind; called as a side effect of unregistering the
* driver which added this configuration.
* @setup: Used to delegate control requests that aren't handled by standard
* device infrastructure or directed at a specific interface.
* @bConfigurationValue: Copied into configuration descriptor.
* @iConfiguration: Copied into configuration descriptor.
* @bmAttributes: Copied into configuration descriptor.
* @bMaxPower: Copied into configuration descriptor.
* @cdev: assigned by @usb_add_config() before calling @bind(); this is
* the device associated with this configuration.
*
* Configurations are building blocks for gadget drivers structured around
* function drivers. Simple USB gadgets require only one function and one
* configuration, and handle dual-speed hardware by always providing the same
* functionality. Slightly more complex gadgets may have more than one
* single-function configuration at a given speed; or have configurations
* that only work at one speed.
*
* Composite devices are, by definition, ones with configurations which
* include more than one function.
*
* The lifecycle of a usb_configuration includes allocation, initialization
* of the fields described above, and calling @usb_add_config() to set up
* internal data and bind it to a specific device. The configuration's
* @bind() method is then used to initialize all the functions and then
* call @usb_add_function() for them.
*
* Those functions would normally be independent of each other, but that's
* not mandatory. CDC WMC devices are an example where functions often
* depend on other functions, with some functions subsidiary to others.
* Such interdependency may be managed in any way, so long as all of the
* descriptors complete by the time the composite driver returns from
* its bind() routine.
*/
struct usb_configuration {
const char *label;
struct usb_gadget_strings **strings;
const struct usb_descriptor_header **descriptors;
/* REVISIT: bind() functions can be marked __init, which
* makes trouble for section mismatch analysis. See if
* we can't restructure things to avoid mismatching...
*/
/* configuration management: unbind/setup */
void (*unbind)(struct usb_configuration *);
int (*setup)(struct usb_configuration *,
const struct usb_ctrlrequest *);
/* fields in the config descriptor */
u8 bConfigurationValue;
u8 iConfiguration;
u8 bmAttributes;
u8 bMaxPower;
struct usb_composite_dev *cdev;
/* private: */
/* internals */
struct list_head list;
struct list_head functions;
u8 next_interface_id;
unsigned highspeed:1;
unsigned fullspeed:1;
struct usb_function *interface[MAX_CONFIG_INTERFACES];
};
int usb_add_config(struct usb_composite_dev *,
struct usb_configuration *,
int (*)(struct usb_configuration *));
int usb_remove_config(struct usb_composite_dev *,
struct usb_configuration *);
/**
* struct usb_composite_driver - groups configurations into a gadget
* @name: For diagnostics, identifies the driver.
* @iProduct: Used as iProduct override if @dev->iProduct is not set.
* If NULL value of @name is taken.
* @iManufacturer: Used as iManufacturer override if @dev->iManufacturer is
* not set. If NULL a default "<system> <release> with <udc>" value
* will be used.
* @dev: Template descriptor for the device, including default device
* identifiers.
* @strings: tables of strings, keyed by identifiers assigned during bind()
* and language IDs provided in control requests
* @needs_serial: set to 1 if the gadget needs userspace to provide
* a serial number. If one is not provided, warning will be printed.
* @unbind: Reverses bind; called as a side effect of unregistering
* this driver.
* @disconnect: optional driver disconnect method
* @suspend: Notifies when the host stops sending USB traffic,
* after function notifications
* @resume: Notifies configuration when the host restarts USB traffic,
* before function notifications
*
* Devices default to reporting self powered operation. Devices which rely
* on bus powered operation should report this in their @bind() method.
*
* Before returning from bind, various fields in the template descriptor
* may be overridden. These include the idVendor/idProduct/bcdDevice values
* normally to bind the appropriate host side driver, and the three strings
* (iManufacturer, iProduct, iSerialNumber) normally used to provide user
* meaningful device identifiers. (The strings will not be defined unless
* they are defined in @dev and @strings.) The correct ep0 maxpacket size
* is also reported, as defined by the underlying controller driver.
*/
struct usb_composite_driver {
const char *name;
const char *iProduct;
const char *iManufacturer;
const struct usb_device_descriptor *dev;
struct usb_gadget_strings **strings;
unsigned needs_serial:1;
int (*unbind)(struct usb_composite_dev *);
void (*disconnect)(struct usb_composite_dev *);
/* global suspend hooks */
void (*suspend)(struct usb_composite_dev *);
void (*resume)(struct usb_composite_dev *);
};
extern int usb_composite_probe(struct usb_composite_driver *driver,
int (*bind)(struct usb_composite_dev *cdev));
extern void usb_composite_unregister(struct usb_composite_driver *driver);
extern void usb_composite_setup_continue(struct usb_composite_dev *cdev);
/**
* struct usb_composite_device - represents one composite usb gadget
* @gadget: read-only, abstracts the gadget's usb peripheral controller
* @req: used for control responses; buffer is pre-allocated
* @bufsiz: size of buffer pre-allocated in @req
* @config: the currently active configuration
*
* One of these devices is allocated and initialized before the
* associated device driver's bind() is called.
*
* OPEN ISSUE: it appears that some WUSB devices will need to be
* built by combining a normal (wired) gadget with a wireless one.
* This revision of the gadget framework should probably try to make
* sure doing that won't hurt too much.
*
* One notion for how to handle Wireless USB devices involves:
* (a) a second gadget here, discovery mechanism TBD, but likely
* needing separate "register/unregister WUSB gadget" calls;
* (b) updates to usb_gadget to include flags "is it wireless",
* "is it wired", plus (presumably in a wrapper structure)
* bandgroup and PHY info;
* (c) presumably a wireless_ep wrapping a usb_ep, and reporting
* wireless-specific parameters like maxburst and maxsequence;
* (d) configurations that are specific to wireless links;
* (e) function drivers that understand wireless configs and will
* support wireless for (additional) function instances;
* (f) a function to support association setup (like CBAF), not
* necessarily requiring a wireless adapter;
* (g) composite device setup that can create one or more wireless
* configs, including appropriate association setup support;
* (h) more, TBD.
*/
struct usb_composite_dev {
struct usb_gadget *gadget;
struct usb_request *req;
unsigned bufsiz;
struct usb_configuration *config;
/* private: */
/* internals */
unsigned int suspended:1;
struct usb_device_descriptor desc;
struct list_head configs;
struct usb_composite_driver *driver;
u8 next_string_id;
u8 manufacturer_override;
u8 product_override;
u8 serial_override;
/* the gadget driver won't enable the data pullup
* while the deactivation count is nonzero.
*/
unsigned deactivations;
/* the composite driver won't complete the control transfer's
* data/status stages till delayed_status is zero.
*/
int delayed_status;
/* protects deactivations and delayed_status counts*/
spinlock_t lock;
};
extern int usb_string_id(struct usb_composite_dev *c);
extern int usb_string_ids_tab(struct usb_composite_dev *c,
struct usb_string *str);
extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n);
/* messaging utils */
#define DBG(d, fmt, args...) \
dev_dbg(&(d)->gadget->dev , fmt , ## args)
#define VDBG(d, fmt, args...) \
dev_vdbg(&(d)->gadget->dev , fmt , ## args)
#define ERROR(d, fmt, args...) \
dev_err(&(d)->gadget->dev , fmt , ## args)
#define WARNING(d, fmt, args...) \
dev_warn(&(d)->gadget->dev , fmt , ## args)
#define INFO(d, fmt, args...) \
dev_info(&(d)->gadget->dev , fmt , ## args)
#endif /* __LINUX_USB_COMPOSITE_H */
| [
"181545689@qq.com"
] | 181545689@qq.com |
681eb4d8341dded445241d819855b4f7f7cb44d9 | 4c521d6be326ab8fe574e90c5023ecd95e4cfc15 | /main.c | 7a74ccc52eb6980aaf4b93ef35bb5e48cbfcd3c1 | [] | no_license | Mike-show/BonusProject | c4f3e84ef2a62294be6ce1c2b164233cb8db9ab7 | ae3b90d7db509023444e7814fa18f952e8cfc0f5 | refs/heads/master | 2023-04-14T06:28:13.116011 | 2021-05-02T15:04:46 | 2021-05-02T15:04:46 | 363,583,920 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 961 | c | #include "Wlan.h"
int main(void){
system(CMD);
int Count;
FILE *Data;
Data = fopen("wlan.txt", "r");
char Choice = '\0';
if(Data != NULL){
Count = WlanCount(Data);
printf("%d WLANs have been found!\n\n", Count);
const int SizeWlan = sizeof(struct ssid);
struct ssid *ssid_list;
ssid_list = (struct ssid *)calloc(Count, SizeWlan);
WlanAnalyse(Data, ssid_list, Count);
fclose(Data);
ResultPrint(ssid_list, Count);
do{
printf("Do you want to delete the record file? (Y/N): ");
scanf("%c", &Choice);
if (Choice == 'Y' || Choice == 'y'){
system("del /f wlan.txt");
printf("wlan.txt has been deleted.\n");
}
printf("Goodbye!\n");
} while (Choice != 'Y' && Choice != 'N' && Choice != 'y' && Choice != 'n');
}
else printf("Error, wlan.txt file doesn't exist!");
} | [
"e2002026@DESKTOP-N6DCJCN"
] | e2002026@DESKTOP-N6DCJCN |
68eeeb84c8d955af76bca65e578796fde7276871 | 4a7d20f21763809b9a061b95d1f308055f5a3fdf | /binarisation/bin_treshold.c | 052676fb3be42becbe987e51239967f5295b5c5c | [] | no_license | multun/OCRe | ecd6b1bd57de25a91d4eea75edaa706a3b6b553e | c83b0a39af5136aa34e6921df1974a0efffad081 | refs/heads/master | 2021-01-19T03:09:44.697167 | 2016-12-05T14:54:45 | 2016-12-05T14:54:45 | 67,486,305 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 609 | c | #include <stdlib.h>
#include "binarise.h"
#include "../bitmap/img.h"
void bw_img_treshold(unsigned char treshold, t_bw_img *img)
{
unsigned int width = img->width;
unsigned int height = img->height;
for(unsigned int x = 0; x < width; x++)
for(unsigned int y = 0; y < height; y++)
{
unsigned int offset = y * width + x;
img->pixels[offset] = (img->pixels[offset] > treshold) ? 255 : 0;
}
}
t_bw_img *bin_treshold(unsigned char treshold, const t_color_img *orig_img)
{
t_bw_img *bw_img = greyscale(intensity, orig_img);
bw_img_treshold(treshold, bw_img);
return bw_img;
}
| [
"victor.collod@epita.fr"
] | victor.collod@epita.fr |
1a84fd48db74e0b1d33acc91009783f1086d8965 | f363fdb9445d8dec088fb02c8faae8e23570a33e | /d/mingjiao/obj/bag.c | d9ad524752f60078e1e2a34f5de2050b84bd441a | [] | no_license | MudRen/zjmud | 0999a492ac0717911c047936ee2c696b3b5cb20a | c56a166380d74858d7b4f0ba2817478ccea6b83d | refs/heads/main | 2023-07-24T21:02:00.246591 | 2021-09-07T12:50:20 | 2021-09-07T12:50:20 | 403,973,627 | 1 | 1 | null | null | null | null | GB18030 | C | false | false | 1,051 | c | // bag.c
#include <ansi.h>
inherit ITEM;
void create()
{
set_name("油布包", ({ "bag", "bao" }));
set_weight(200);
if (clonep())
set_default_object(__FILE__);
else {
set("unit", "个");
set("long", "这是一个油布包裹。\n");
set("value", 500);
set("material", "cloth");
}
set("book_count", 0);
}
void init()
{
if (this_player() == environment())
{
add_action("do_open", "open");
add_action("do_open", "unpack");
add_action("do_open", "dakai");
}
}
int do_open(string arg)
{
object me, book;
object where;
if (! arg || ! id(arg))
return 0;
if (query("book_count") < 1)
{
write("油布包里面什么也没有了。\n");
return 1;
}
me = this_player();
where = environment(me);
message_vision("$N轻轻地把油布包来看时，里面原来是一本"
"薄薄的经书，只因油布包得紧密，虽长期藏"
"在猿腹之中，书页仍然完好无损。\n", me);
book = new("/clone/book/jiuyang-book");
book->move(file_name(where));
add("book_count", -1);
return 1;
}
| [
"i@oiuv.cn"
] | i@oiuv.cn |
ce3257df27c9ca159eb2b44594d23cce7b01e0f8 | 45a175e1a470bf15f4a2aa5b066250d6f8ec5327 | /embox/src/profiler/tracing/no_trace.c | e7ebc4585e357a421dbd9651566018fd80530d77 | [
"BSD-2-Clause"
] | permissive | Walkingmind/embox | 8315ee532d9e0a0ccd5e566bf4feac5ffe58d683 | 67cc5f73466e1a4c33891b946fc8e8217ce26ade | refs/heads/master | 2021-01-01T17:22:48.903024 | 2015-04-14T20:24:43 | 2015-04-14T20:24:43 | 35,509,406 | 2 | 0 | null | null | null | null | UTF-8 | C | false | false | 435 | c | /**
* @file
* @brief
*
* @author Anton Kozlov
* @date 29.04.2013
*/
#include <stddef.h>
#include <profiler/tracing/trace.h>
time64_t trace_block_diff(struct __trace_block *tb) {
return -1;
}
time64_t trace_block_get_time(struct __trace_block *tb) {
return -1;
}
int trace_point_get_value(struct __trace_point *tp) {
return -1;
}
struct __trace_point *trace_point_get_by_name(const char *name) {
return NULL;
}
| [
"drakon.mega@5c469cbc-2eb3-11df-bba7-995ec2794b1c"
] | drakon.mega@5c469cbc-2eb3-11df-bba7-995ec2794b1c |
600963bd956149f1b2ea3e070a958698980051e0 | 9fe295bccc24fff067921a69efeae8523323bc6d | /shoes/native/gtk/gtkeditline.c | c7a587ea97e275cbb91ce52b0362277cf2a0777b | [
"MIT"
] | permissive | val461/shoes3 | 9265c5c9a5dfee558abdacae23bc4bba3b84d740 | 323e544d91d53a43670cab474cee269a1aa1d0e6 | refs/heads/master | 2021-08-23T03:43:59.243535 | 2017-12-02T03:32:43 | 2017-12-02T03:32:43 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,769 | c | #include "shoes/app.h"
#include "shoes/ruby.h"
#include "shoes/config.h"
#include "shoes/world.h"
#include "shoes/native/native.h"
#include "shoes/types/native.h"
#include "shoes/internal.h"
#include "shoes/native/gtk/gtkentryalt.h"
#include "shoes/native/gtk/gtkeditline.h"
SHOES_CONTROL_REF shoes_native_edit_line(VALUE self, shoes_canvas *canvas, shoes_place *place, VALUE attr, char *msg) {
SHOES_CONTROL_REF ref = gtk_entry_alt_new();
if (RTEST(ATTR(attr, secret))) shoes_native_secrecy(ref);
if (!NIL_P(shoes_hash_get(attr, rb_intern("tooltip")))) {
gtk_widget_set_tooltip_text(GTK_WIDGET(ref), RSTRING_PTR(shoes_hash_get(attr, rb_intern("tooltip"))));
}
gtk_entry_set_text(GTK_ENTRY(ref), _(msg));
g_signal_connect(G_OBJECT(ref), "changed",
G_CALLBACK(shoes_widget_changed),
(gpointer)self);
// cjc: try to intercept \n bug 860 @ shoes4
g_signal_connect(G_OBJECT(ref), "activate",
G_CALLBACK(shoes_native_enterkey), // fix name?
(gpointer)self);
return ref;
}
VALUE shoes_native_edit_line_get_text(SHOES_CONTROL_REF ref) {
return rb_str_new2(gtk_entry_get_text(GTK_ENTRY(ref)));
}
void shoes_native_edit_line_set_text(SHOES_CONTROL_REF ref, char *msg) {
gtk_entry_set_text(GTK_ENTRY(ref), _(msg));
}
VALUE shoes_native_edit_line_cursor_to_end(SHOES_CONTROL_REF ref) {
gtk_editable_set_position(GTK_EDITABLE(ref), -1);
return Qnil;
}
void shoes_native_enterkey(GtkWidget *ref, gpointer data) {
VALUE self = (VALUE)data;
GET_STRUCT(control, self_t);
VALUE click = ATTR(self_t->attr, donekey);
if (!NIL_P(click)) {
shoes_safe_block(self_t->parent, click, rb_ary_new3(1, self));
}
} | [
"ian.trudel@gmail.com"
] | ian.trudel@gmail.com |
cc9fbe2e0c31cb370023e9c0c0501c0a296de073 | 9d9aca7551e69a2538fb47d001bbdc3eea8c3f08 | /src/utils/dynamic_string_utils.c | 95f853af9a6edeea6703c310cd9cace33771123f | [] | no_license | hugoBuissez/42sh | d226d09b36d5ec8d70358d54baee1969d42e07ca | ad85735ce87edbcaad102b5d68f54e738b309ff6 | refs/heads/master | 2023-03-30T12:24:33.448736 | 2021-03-29T19:19:16 | 2021-03-29T19:19:16 | 337,054,088 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 318 | c | #include <string.h>
#include "dynamic_string.h"
#include "dynamic_string_internals.h"
size_t string_len(struct d_string *string)
{
return string->len;
}
char *string_value(struct d_string *string)
{
return string->buf;
}
char *string_value_copy(struct d_string *string)
{
return strdup(string->buf);
}
| [
"hbuissez@gmail.com"
] | hbuissez@gmail.com |
f14c1817cd3baa4613c4c7510c4b367ba5a67976 | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/linux/drivers/media/usb/cx231xx/extr_cx231xx-i2c.c_cx231xx_i2c_mux_unregister.c | 2bb4865bfe7f8ebe5de35cbfb65d2c612f2ce254 | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 594 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
/* Type definitions */
struct cx231xx {int /*<<< orphan*/ muxc; } ;
/* Variables and functions */
int /*<<< orphan*/ i2c_mux_del_adapters (int /*<<< orphan*/ ) ;
void cx231xx_i2c_mux_unregister(struct cx231xx *dev)
{
i2c_mux_del_adapters(dev->muxc);
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
6768b81c1820aa74ee43e72bf88812a00df5642b | e5b45ef28d128f072e5cc318371731b0fbdd4399 | /DataStructure/Tree/BinaryTree/BinaryTree/LinkedQueue.c | dd4c2ddac6548ea823c1cf46c05ec72b2b660a17 | [] | no_license | KianaGX/test | 8e12550bef48f689d9d9abace0bd1efefe045586 | 15ba7dcd6cf114b6ca45a4f8442f08c202bfaff9 | refs/heads/master | 2022-12-08T08:00:03.152204 | 2020-08-29T15:42:56 | 2020-08-29T15:42:56 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,074 | c | #include "BinaryTree.h"
#include "LinkedQueue.h"
void QueueInit(Queue* q)
{
q->front = q->rear = NULL;
}
DataType QueueFront(Queue* q)
{
assert(q);
return q->front->val;
}
DataType QueueBack(Queue* q)
{
assert(q);
return q->rear->val;
}
int QueueEmpty(Queue* q)
{
return q->front ? 0 : 1;
}
int QueueSize(Queue* q)
{
assert(q);
QNode* cur = q->front;
int count = 0;
while (cur)
{
count++;
cur = cur->next;
}
return count;
}
void QueuePush(Queue* q, DataType val)
{
assert(q);
QNode* node = (QNode*)malloc(sizeof(QNode));
node->val = val;
node->next = NULL;
if (q->rear)
{
q->rear->next = node;
q->rear = node;
}
else
{
q->front = q->rear = node;
}
}
void QueuePop(Queue* q)
{
assert(q);
if (NULL == q->front->next)
{
free(q->front);
q->front = q->rear = NULL;
}
else
{
QNode* next = q->front->next;
free(q->front);
q->front = next;
}
}
void QueueDestroy(Queue* q)
{
assert(q);
QNode* cur = q->front;
while (cur)
{
QNode* next = cur->next;
free(cur);
cur = next;
}
q->front = q->rear = NULL;
}
| [
"756687451@qq.com"
] | 756687451@qq.com |
e5a21f57abe8367f9a69e7f833e06b6679247c80 | ddef162b2d614f63ab8361c880ca75533b04b32e | /demo.c | d9cd069743860f46e264c917396698e9cc017f4c | [] | no_license | air2013/libRockey | 9dac86fbc21603b2e0e008774d22bb65e2c792ef | f33739e76b89ba7be00cc675e60d1b703b69f0f0 | refs/heads/master | 2020-04-06T17:04:21.095548 | 2015-07-21T07:02:33 | 2015-07-21T07:02:33 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 685 | c | #include <stdio.h>
#include "utils.h"
#include "utpm_api.h"
int main() {
short pcrnum = 0x7;
char digest[] = {
0x22, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00,
0x00, 0x22, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00,
0x00, 0x07, 0xff, 0xff};
if (utpm_pcr_extend(pcrnum, digest) != 0) {
printf("pcr extend failed.\n");
return -1;
}
printf("pcr_extend: pcr %d is: \n", pcrnum);
printf_buffer(digest, 20);
char digest2[20];
if (utpm_pcr_read(pcrnum, digest2) != 0) {
printf("pcr read failed.\n");
return -1;
}
printf("pcr_read: pcr %d is: \n", pcrnum);
printf_buffer(digest2, 20);
return 0;
}
| [
"johnxn@foxmail.com"
] | johnxn@foxmail.com |
37028eb6a3e545223f7f85f697d317756dddee04 | 78a2c3aa40f73038cc34708719f2d047ce46a0cd | /lex.yy.c | 87890b813b8359e4bfa2eef8fa2019c47d5e4943 | [] | no_license | fareyduran/Compiler_1 | 78798f8b4e6284e96f4482b6b391f829649c9d66 | a74ee64513133914ee655abc84b304dc22c3e14a | refs/heads/master | 2022-11-15T12:21:23.762206 | 2016-02-28T20:48:11 | 2016-02-28T20:48:11 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 54,618 | c |
#line 3 "lex.yy.c"
#define YY_INT_ALIGNED short int
/* A lexical scanner generated by flex */
#define FLEX_SCANNER
#define YY_FLEX_MAJOR_VERSION 2
#define YY_FLEX_MINOR_VERSION 5
#define YY_FLEX_SUBMINOR_VERSION 35
#if YY_FLEX_SUBMINOR_VERSION > 0
#define FLEX_BETA
#endif
/* First, we deal with platform-specific or compiler-specific issues. */
/* begin standard C headers. */
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <stdlib.h>
/* end standard C headers. */
/* flex integer type definitions */
#ifndef FLEXINT_H
#define FLEXINT_H
/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
* if you want the limit (max/min) macros for int types.
*/
#ifndef __STDC_LIMIT_MACROS
#define __STDC_LIMIT_MACROS 1
#endif
#include <inttypes.h>
typedef int8_t flex_int8_t;
typedef uint8_t flex_uint8_t;
typedef int16_t flex_int16_t;
typedef uint16_t flex_uint16_t;
typedef int32_t flex_int32_t;
typedef uint32_t flex_uint32_t;
typedef uint64_t flex_uint64_t;
#else
typedef signed char flex_int8_t;
typedef short int flex_int16_t;
typedef int flex_int32_t;
typedef unsigned char flex_uint8_t;
typedef unsigned short int flex_uint16_t;
typedef unsigned int flex_uint32_t;
#endif /* ! C99 */
/* Limits of integral types. */
#ifndef INT8_MIN
#define INT8_MIN (-128)
#endif
#ifndef INT16_MIN
#define INT16_MIN (-32767-1)
#endif
#ifndef INT32_MIN
#define INT32_MIN (-2147483647-1)
#endif
#ifndef INT8_MAX
#define INT8_MAX (127)
#endif
#ifndef INT16_MAX
#define INT16_MAX (32767)
#endif
#ifndef INT32_MAX
#define INT32_MAX (2147483647)
#endif
#ifndef UINT8_MAX
#define UINT8_MAX (255U)
#endif
#ifndef UINT16_MAX
#define UINT16_MAX (65535U)
#endif
#ifndef UINT32_MAX
#define UINT32_MAX (4294967295U)
#endif
#endif /* ! FLEXINT_H */
#ifdef __cplusplus
/* The "const" storage-class-modifier is valid. */
#define YY_USE_CONST
#else /* ! __cplusplus */
/* C99 requires __STDC__ to be defined as 1. */
#if defined (__STDC__)
#define YY_USE_CONST
#endif /* defined (__STDC__) */
#endif /* ! __cplusplus */
#ifdef YY_USE_CONST
#define yyconst const
#else
#define yyconst
#endif
/* Returned upon end-of-file. */
#define YY_NULL 0
/* Promotes a possibly negative, possibly signed char to an unsigned
* integer for use as an array index. If the signed char is negative,
* we want to instead treat it as an 8-bit unsigned char, hence the
* double cast.
*/
#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
/* Enter a start condition. This macro really ought to take a parameter,
* but we do it the disgusting crufty way forced on us by the ()-less
* definition of BEGIN.
*/
#define BEGIN (yy_start) = 1 + 2 *
/* Translate the current start state into a value that can be later handed
* to BEGIN to return to the state. The YYSTATE alias is for lex
* compatibility.
*/
#define YY_START (((yy_start) - 1) / 2)
#define YYSTATE YY_START
/* Action number for EOF rule of a given start state. */
#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
/* Special action meaning "start processing a new file". */
#define YY_NEW_FILE yyrestart(yyin )
#define YY_END_OF_BUFFER_CHAR 0
/* Size of default input buffer. */
#ifndef YY_BUF_SIZE
#define YY_BUF_SIZE 16384
#endif
/* The state buf must be large enough to hold one state per character in the main buffer.
*/
#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
#ifndef YY_TYPEDEF_YY_BUFFER_STATE
#define YY_TYPEDEF_YY_BUFFER_STATE
typedef struct yy_buffer_state *YY_BUFFER_STATE;
#endif
#ifndef YY_TYPEDEF_YY_SIZE_T
#define YY_TYPEDEF_YY_SIZE_T
typedef size_t yy_size_t;
#endif
extern yy_size_t yyleng;
extern FILE *yyin, *yyout;
#define EOB_ACT_CONTINUE_SCAN 0
#define EOB_ACT_END_OF_FILE 1
#define EOB_ACT_LAST_MATCH 2
#define YY_LESS_LINENO(n)
/* Return all but the first "n" matched characters back to the input stream. */
#define yyless(n) \
do \
{ \
/* Undo effects of setting up yytext. */ \
int yyless_macro_arg = (n); \
YY_LESS_LINENO(yyless_macro_arg);\
*yy_cp = (yy_hold_char); \
YY_RESTORE_YY_MORE_OFFSET \
(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
YY_DO_BEFORE_ACTION; /* set up yytext again */ \
} \
while ( 0 )
#define unput(c) yyunput( c, (yytext_ptr) )
#ifndef YY_STRUCT_YY_BUFFER_STATE
#define YY_STRUCT_YY_BUFFER_STATE
struct yy_buffer_state
{
FILE *yy_input_file;
char *yy_ch_buf; /* input buffer */
char *yy_buf_pos; /* current position in input buffer */
/* Size of input buffer in bytes, not including room for EOB
* characters.
*/
yy_size_t yy_buf_size;
/* Number of characters read into yy_ch_buf, not including EOB
* characters.
*/
yy_size_t yy_n_chars;
/* Whether we "own" the buffer - i.e., we know we created it,
* and can realloc() it to grow it, and should free() it to
* delete it.
*/
int yy_is_our_buffer;
/* Whether this is an "interactive" input source; if so, and
* if we're using stdio for input, then we want to use getc()
* instead of fread(), to make sure we stop fetching input after
* each newline.
*/
int yy_is_interactive;
/* Whether we're considered to be at the beginning of a line.
* If so, '^' rules will be active on the next match, otherwise
* not.
*/
int yy_at_bol;
int yy_bs_lineno; /**< The line count. */
int yy_bs_column; /**< The column count. */
/* Whether to try to fill the input buffer when we reach the
* end of it.
*/
int yy_fill_buffer;
int yy_buffer_status;
#define YY_BUFFER_NEW 0
#define YY_BUFFER_NORMAL 1
/* When an EOF's been seen but there's still some text to process
* then we mark the buffer as YY_EOF_PENDING, to indicate that we
* shouldn't try reading from the input source any more. We might
* still have a bunch of tokens to match, though, because of
* possible backing-up.
*
* When we actually see the EOF, we change the status to "new"
* (via yyrestart()), so that the user can continue scanning by
* just pointing yyin at a new input file.
*/
#define YY_BUFFER_EOF_PENDING 2
};
#endif /* !YY_STRUCT_YY_BUFFER_STATE */
/* Stack of input buffers. */
static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
/* We provide macros for accessing buffer states in case in the
* future we want to put the buffer states in a more general
* "scanner state".
*
* Returns the top of the stack, or NULL.
*/
#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
? (yy_buffer_stack)[(yy_buffer_stack_top)] \
: NULL)
/* Same as previous macro, but useful when we know that the buffer stack is not
* NULL or when we need an lvalue. For internal use only.
*/
#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
/* yy_hold_char holds the character lost when yytext is formed. */
static char yy_hold_char;
static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */
yy_size_t yyleng;
/* Points to current character in buffer. */
static char *yy_c_buf_p = (char *) 0;
static int yy_init = 0; /* whether we need to initialize */
static int yy_start = 0; /* start state number */
/* Flag which is used to allow yywrap()'s to do buffer switches
* instead of setting up a fresh yyin. A bit of a hack ...
*/
static int yy_did_buffer_switch_on_eof;
void yyrestart (FILE *input_file );
void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer );
YY_BUFFER_STATE yy_create_buffer (FILE *file,int size );
void yy_delete_buffer (YY_BUFFER_STATE b );
void yy_flush_buffer (YY_BUFFER_STATE b );
void yypush_buffer_state (YY_BUFFER_STATE new_buffer );
void yypop_buffer_state (void );
static void yyensure_buffer_stack (void );
static void yy_load_buffer_state (void );
static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file );
#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size );
YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str );
YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,yy_size_t len );
void *yyalloc (yy_size_t );
void *yyrealloc (void *,yy_size_t );
void yyfree (void * );
#define yy_new_buffer yy_create_buffer
#define yy_set_interactive(is_interactive) \
{ \
if ( ! YY_CURRENT_BUFFER ){ \
yyensure_buffer_stack (); \
YY_CURRENT_BUFFER_LVALUE = \
yy_create_buffer(yyin,YY_BUF_SIZE ); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
}
#define yy_set_bol(at_bol) \
{ \
if ( ! YY_CURRENT_BUFFER ){\
yyensure_buffer_stack (); \
YY_CURRENT_BUFFER_LVALUE = \
yy_create_buffer(yyin,YY_BUF_SIZE ); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
}
#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
/* Begin user sect3 */
typedef unsigned char YY_CHAR;
FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
typedef int yy_state_type;
extern int yylineno;
int yylineno = 1;
extern char *yytext;
#define yytext_ptr yytext
static yy_state_type yy_get_previous_state (void );
static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
static int yy_get_next_buffer (void );
static void yy_fatal_error (yyconst char msg[] );
/* Done after the current pattern has been matched and before the
* corresponding action - sets up yytext.
*/
#define YY_DO_BEFORE_ACTION \
(yytext_ptr) = yy_bp; \
yyleng = (yy_size_t) (yy_cp - yy_bp); \
(yy_hold_char) = *yy_cp; \
*yy_cp = '\0'; \
(yy_c_buf_p) = yy_cp;
#define YY_NUM_RULES 16
#define YY_END_OF_BUFFER 17
/* This struct is not used in this scanner,
but its presence is necessary. */
struct yy_trans_info
{
flex_int32_t yy_verify;
flex_int32_t yy_nxt;
};
static yyconst flex_int16_t yy_accept[40] =
{ 0,
0, 0, 17, 16, 14, 15, 11, 9, 2, 10,
12, 1, 16, 2, 2, 2, 2, 2, 2, 0,
1, 13, 0, 6, 0, 3, 0, 0, 2, 0,
8, 0, 0, 0, 4, 0, 7, 5, 0
} ;
static yyconst flex_int32_t yy_ec[256] =
{ 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
3, 4, 5, 6, 7, 1, 8, 9, 10, 10,
10, 10, 10, 10, 10, 10, 10, 11, 1, 1,
12, 1, 1, 1, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
1, 1, 1, 1, 1, 1, 6, 13, 6, 14,
15, 16, 17, 18, 19, 6, 6, 20, 6, 21,
22, 6, 6, 6, 6, 23, 6, 6, 24, 6,
6, 6, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1
} ;
static yyconst flex_int32_t yy_meta[25] =
{ 0,
1, 1, 1, 1, 1, 2, 1, 1, 1, 1,
1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2
} ;
static yyconst flex_int16_t yy_base[41] =
{ 0,
0, 0, 62, 63, 63, 63, 63, 63, 16, 63,
63, 18, 49, 20, 22, 24, 27, 29, 31, 0,
41, 63, 43, 63, 45, 63, 43, 38, 43, 37,
63, 34, 34, 27, 63, 31, 63, 63, 63, 40
} ;
static yyconst flex_int16_t yy_def[41] =
{ 0,
39, 1, 39, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39, 39, 39, 40,
39, 39, 39, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39, 39, 0, 39
} ;
static yyconst flex_int16_t yy_nxt[88] =
{ 0,
4, 5, 6, 7, 8, 9, 10, 11, 4, 12,
13, 4, 14, 15, 16, 9, 9, 9, 17, 9,
9, 9, 18, 19, 20, 20, 21, 21, 20, 20,
20, 20, 20, 20, 23, 20, 20, 20, 20, 20,
20, 29, 26, 24, 25, 38, 27, 37, 28, 21,
21, 20, 20, 36, 35, 34, 33, 32, 31, 30,
22, 39, 3, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39
} ;
static yyconst flex_int16_t yy_chk[88] =
{ 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 9, 9, 12, 12, 14, 14,
15, 15, 16, 16, 14, 17, 17, 18, 18, 19,
19, 40, 17, 15, 16, 36, 18, 34, 19, 21,
21, 29, 29, 33, 32, 30, 28, 27, 25, 23,
13, 3, 39, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39, 39, 39, 39,
39, 39, 39, 39, 39, 39, 39
} ;
static yy_state_type yy_last_accepting_state;
static char *yy_last_accepting_cpos;
extern int yy_flex_debug;
int yy_flex_debug = 0;
/* The intent behind this definition is that it'll catch
* any uses of REJECT which flex missed.
*/
#define REJECT reject_used_but_not_detected
#define yymore() yymore_used_but_not_detected
#define YY_MORE_ADJ 0
#define YY_RESTORE_YY_MORE_OFFSET
char *yytext;
#line 1 "t3.lex"
/* Archivo con el reconocedor léxico para la calculadora */
#line 3 "t3.lex"
#include <stdlib.h>
#include <math.h>
#define NUMERO 15
#define IDE 1
#define IF 2
#define THEN 3
#define WHILE 4
#define DO 5
#define BEG 6
#define END 7
#define MAS 8
#define MENOS 9
#define POR 10
#define ENTRE 11
#define IGUAL 12
#define PABRE 13
#define PCIERRA 14
#define PUNTOYCOMA 16
int entero;
char * op;
char * id;
char * sc;
char * ig;
char * pa;
char * pc;
int res;
int tamanioCadena;
/* Se incluye el archivo generado por bison para tener las definiciones
de los tokens */
#line 515 "lex.yy.c"
#define INITIAL 0
#ifndef YY_NO_UNISTD_H
/* Special case for "unistd.h", since it is non-ANSI. We include it way
* down here because we want the user's section 1 to have been scanned first.
* The user has a chance to override it with an option.
*/
#include <unistd.h>
#endif
#ifndef YY_EXTRA_TYPE
#define YY_EXTRA_TYPE void *
#endif
static int yy_init_globals (void );
/* Accessor methods to globals.
These are made visible to non-reentrant scanners for convenience. */
int yylex_destroy (void );
int yyget_debug (void );
void yyset_debug (int debug_flag );
YY_EXTRA_TYPE yyget_extra (void );
void yyset_extra (YY_EXTRA_TYPE user_defined );
FILE *yyget_in (void );
void yyset_in (FILE * in_str );
FILE *yyget_out (void );
void yyset_out (FILE * out_str );
yy_size_t yyget_leng (void );
char *yyget_text (void );
int yyget_lineno (void );
void yyset_lineno (int line_number );
/* Macros after this point can all be overridden by user definitions in
* section 1.
*/
#ifndef YY_SKIP_YYWRAP
#ifdef __cplusplus
extern "C" int yywrap (void );
#else
extern int yywrap (void );
#endif
#endif
static void yyunput (int c,char *buf_ptr );
#ifndef yytext_ptr
static void yy_flex_strncpy (char *,yyconst char *,int );
#endif
#ifdef YY_NEED_STRLEN
static int yy_flex_strlen (yyconst char * );
#endif
#ifndef YY_NO_INPUT
#ifdef __cplusplus
static int yyinput (void );
#else
static int input (void );
#endif
#endif
/* Amount of stuff to slurp up with each read. */
#ifndef YY_READ_BUF_SIZE
#define YY_READ_BUF_SIZE 8192
#endif
/* Copy whatever the last rule matched to the standard output. */
#ifndef ECHO
/* This used to be an fputs(), but since the string might contain NUL's,
* we now use fwrite().
*/
#define ECHO fwrite( yytext, yyleng, 1, yyout )
#endif
/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
* is returned in "result".
*/
#ifndef YY_INPUT
#define YY_INPUT(buf,result,max_size) \
if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
{ \
int c = '*'; \
yy_size_t n; \
for ( n = 0; n < max_size && \
(c = getc( yyin )) != EOF && c != '\n'; ++n ) \
buf[n] = (char) c; \
if ( c == '\n' ) \
buf[n++] = (char) c; \
if ( c == EOF && ferror( yyin ) ) \
YY_FATAL_ERROR( "input in flex scanner failed" ); \
result = n; \
} \
else \
{ \
errno=0; \
while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
{ \
if( errno != EINTR) \
{ \
YY_FATAL_ERROR( "input in flex scanner failed" ); \
break; \
} \
errno=0; \
clearerr(yyin); \
} \
}\
\
#endif
/* No semi-colon after return; correct usage is to write "yyterminate();" -
* we don't want an extra ';' after the "return" because that will cause
* some compilers to complain about unreachable statements.
*/
#ifndef yyterminate
#define yyterminate() return YY_NULL
#endif
/* Number of entries by which start-condition stack grows. */
#ifndef YY_START_STACK_INCR
#define YY_START_STACK_INCR 25
#endif
/* Report a fatal error. */
#ifndef YY_FATAL_ERROR
#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
#endif
/* end tables serialization structures and prototypes */
/* Default declaration of generated scanner - a define so the user can
* easily add parameters.
*/
#ifndef YY_DECL
#define YY_DECL_IS_OURS 1
extern int yylex (void);
#define YY_DECL int yylex (void)
#endif /* !YY_DECL */
/* Code executed at the beginning of each rule, after yytext and yyleng
* have been set up.
*/
#ifndef YY_USER_ACTION
#define YY_USER_ACTION
#endif
/* Code executed at the end of each rule. */
#ifndef YY_BREAK
#define YY_BREAK break;
#endif
#define YY_RULE_SETUP \
YY_USER_ACTION
/** The main scanner function which does all the work.
*/
YY_DECL
{
register yy_state_type yy_current_state;
register char *yy_cp, *yy_bp;
register int yy_act;
#line 43 "t3.lex"
#line 700 "lex.yy.c"
if ( !(yy_init) )
{
(yy_init) = 1;
#ifdef YY_USER_INIT
YY_USER_INIT;
#endif
if ( ! (yy_start) )
(yy_start) = 1; /* first start state */
if ( ! yyin )
yyin = stdin;
if ( ! yyout )
yyout = stdout;
if ( ! YY_CURRENT_BUFFER ) {
yyensure_buffer_stack ();
YY_CURRENT_BUFFER_LVALUE =
yy_create_buffer(yyin,YY_BUF_SIZE );
}
yy_load_buffer_state( );
}
while ( 1 ) /* loops until end-of-file is reached */
{
yy_cp = (yy_c_buf_p);
/* Support of yytext. */
*yy_cp = (yy_hold_char);
/* yy_bp points to the position in yy_ch_buf of the start of
* the current run.
*/
yy_bp = yy_cp;
yy_current_state = (yy_start);
yy_match:
do
{
register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
if ( yy_accept[yy_current_state] )
{
(yy_last_accepting_state) = yy_current_state;
(yy_last_accepting_cpos) = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 40 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
++yy_cp;
}
while ( yy_base[yy_current_state] != 63 );
yy_find_action:
yy_act = yy_accept[yy_current_state];
if ( yy_act == 0 )
{ /* have to back up */
yy_cp = (yy_last_accepting_cpos);
yy_current_state = (yy_last_accepting_state);
yy_act = yy_accept[yy_current_state];
}
YY_DO_BEFORE_ACTION;
do_action: /* This label is used only to access EOF actions. */
switch ( yy_act )
{ /* beginning of action switch */
case 0: /* must back up */
/* undo the effects of YY_DO_BEFORE_ACTION */
*yy_cp = (yy_hold_char);
yy_cp = (yy_last_accepting_cpos);
yy_current_state = (yy_last_accepting_state);
goto yy_find_action;
case 1:
YY_RULE_SETUP
#line 45 "t3.lex"
{ entero = atoi(yytext); return NUMERO;} // Lo convertimos a número entero
YY_BREAK
case 2:
YY_RULE_SETUP
#line 46 "t3.lex"
{id = yytext; tamanioCadena++; return IDE;}
YY_BREAK
case 3:
YY_RULE_SETUP
#line 47 "t3.lex"
{sc = yytext; tamanioCadena++; return IF;}
YY_BREAK
case 4:
YY_RULE_SETUP
#line 48 "t3.lex"
{sc = yytext; tamanioCadena++; return THEN;}
YY_BREAK
case 5:
YY_RULE_SETUP
#line 49 "t3.lex"
{sc = yytext; tamanioCadena++; return WHILE;}
YY_BREAK
case 6:
YY_RULE_SETUP
#line 50 "t3.lex"
{sc = yytext; tamanioCadena++; return DO;}
YY_BREAK
case 7:
YY_RULE_SETUP
#line 51 "t3.lex"
{sc = yytext; tamanioCadena++; return BEG;}
YY_BREAK
case 8:
YY_RULE_SETUP
#line 52 "t3.lex"
{sc = yytext; tamanioCadena++; return END;}
YY_BREAK
case 9:
YY_RULE_SETUP
#line 53 "t3.lex"
{op = yytext; tamanioCadena++; return MAS;}
YY_BREAK
case 10:
YY_RULE_SETUP
#line 54 "t3.lex"
{op = yytext; tamanioCadena++; return MENOS;}
YY_BREAK
case 11:
YY_RULE_SETUP
#line 55 "t3.lex"
{op = yytext; tamanioCadena++; return POR;}
YY_BREAK
case 12:
YY_RULE_SETUP
#line 56 "t3.lex"
{op = yytext; tamanioCadena++; return ENTRE;}
YY_BREAK
case 13:
YY_RULE_SETUP
#line 57 "t3.lex"
{ig = yytext; tamanioCadena++; return IGUAL;}
YY_BREAK
case 14:
YY_RULE_SETUP
#line 58 "t3.lex"
{pa = yytext; tamanioCadena++; return PABRE;}
YY_BREAK
case 15:
YY_RULE_SETUP
#line 59 "t3.lex"
{pc = yytext; tamanioCadena++; return PCIERRA;}
YY_BREAK
case 16:
YY_RULE_SETUP
#line 60 "t3.lex"
ECHO;
YY_BREAK
#line 863 "lex.yy.c"
case YY_STATE_EOF(INITIAL):
yyterminate();
case YY_END_OF_BUFFER:
{
/* Amount of text matched not including the EOB char. */
int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
/* Undo the effects of YY_DO_BEFORE_ACTION. */
*yy_cp = (yy_hold_char);
YY_RESTORE_YY_MORE_OFFSET
if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
{
/* We're scanning a new file or input source. It's
* possible that this happened because the user
* just pointed yyin at a new source and called
* yylex(). If so, then we have to assure
* consistency between YY_CURRENT_BUFFER and our
* globals. Here is the right place to do so, because
* this is the first action (other than possibly a
* back-up) that will match for the new input source.
*/
(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
}
/* Note that here we test for yy_c_buf_p "<=" to the position
* of the first EOB in the buffer, since yy_c_buf_p will
* already have been incremented past the NUL character
* (since all states make transitions on EOB to the
* end-of-buffer state). Contrast this with the test
* in input().
*/
if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
{ /* This was really a NUL. */
yy_state_type yy_next_state;
(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
yy_current_state = yy_get_previous_state( );
/* Okay, we're now positioned to make the NUL
* transition. We couldn't have
* yy_get_previous_state() go ahead and do it
* for us because it doesn't know how to deal
* with the possibility of jamming (and we don't
* want to build jamming into it because then it
* will run more slowly).
*/
yy_next_state = yy_try_NUL_trans( yy_current_state );
yy_bp = (yytext_ptr) + YY_MORE_ADJ;
if ( yy_next_state )
{
/* Consume the NUL. */
yy_cp = ++(yy_c_buf_p);
yy_current_state = yy_next_state;
goto yy_match;
}
else
{
yy_cp = (yy_c_buf_p);
goto yy_find_action;
}
}
else switch ( yy_get_next_buffer( ) )
{
case EOB_ACT_END_OF_FILE:
{
(yy_did_buffer_switch_on_eof) = 0;
if ( yywrap( ) )
{
/* Note: because we've taken care in
* yy_get_next_buffer() to have set up
* yytext, we can now set up
* yy_c_buf_p so that if some total
* hoser (like flex itself) wants to
* call the scanner after we return the
* YY_NULL, it'll still work - another
* YY_NULL will get returned.
*/
(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
yy_act = YY_STATE_EOF(YY_START);
goto do_action;
}
else
{
if ( ! (yy_did_buffer_switch_on_eof) )
YY_NEW_FILE;
}
break;
}
case EOB_ACT_CONTINUE_SCAN:
(yy_c_buf_p) =
(yytext_ptr) + yy_amount_of_matched_text;
yy_current_state = yy_get_previous_state( );
yy_cp = (yy_c_buf_p);
yy_bp = (yytext_ptr) + YY_MORE_ADJ;
goto yy_match;
case EOB_ACT_LAST_MATCH:
(yy_c_buf_p) =
&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
yy_current_state = yy_get_previous_state( );
yy_cp = (yy_c_buf_p);
yy_bp = (yytext_ptr) + YY_MORE_ADJ;
goto yy_find_action;
}
break;
}
default:
YY_FATAL_ERROR(
"fatal flex scanner internal error--no action found" );
} /* end of action switch */
} /* end of scanning one token */
} /* end of yylex */
/* yy_get_next_buffer - try to read in a new buffer
*
* Returns a code representing an action:
* EOB_ACT_LAST_MATCH -
* EOB_ACT_CONTINUE_SCAN - continue scanning from current position
* EOB_ACT_END_OF_FILE - end of file
*/
static int yy_get_next_buffer (void)
{
register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
register char *source = (yytext_ptr);
register int number_to_move, i;
int ret_val;
if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
YY_FATAL_ERROR(
"fatal flex scanner internal error--end of buffer missed" );
if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
{ /* Don't try to fill the buffer, so this is an EOF. */
if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
{
/* We matched a single character, the EOB, so
* treat this as a final EOF.
*/
return EOB_ACT_END_OF_FILE;
}
else
{
/* We matched some text prior to the EOB, first
* process it.
*/
return EOB_ACT_LAST_MATCH;
}
}
/* Try to read more data. */
/* First move last chars to start of buffer. */
number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
for ( i = 0; i < number_to_move; ++i )
*(dest++) = *(source++);
if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
/* don't do the read, it's not guaranteed to return an EOF,
* just force an EOF
*/
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
else
{
yy_size_t num_to_read =
YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
while ( num_to_read <= 0 )
{ /* Not enough room in the buffer - grow it. */
/* just a shorter name for the current buffer */
YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
int yy_c_buf_p_offset =
(int) ((yy_c_buf_p) - b->yy_ch_buf);
if ( b->yy_is_our_buffer )
{
yy_size_t new_size = b->yy_buf_size * 2;
if ( new_size <= 0 )
b->yy_buf_size += b->yy_buf_size / 8;
else
b->yy_buf_size *= 2;
b->yy_ch_buf = (char *)
/* Include room in for 2 EOB chars. */
yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
}
else
/* Can't grow it, we don't own it. */
b->yy_ch_buf = 0;
if ( ! b->yy_ch_buf )
YY_FATAL_ERROR(
"fatal error - scanner input buffer overflow" );
(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
number_to_move - 1;
}
if ( num_to_read > YY_READ_BUF_SIZE )
num_to_read = YY_READ_BUF_SIZE;
/* Read in more data. */
YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
(yy_n_chars), num_to_read );
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
}
if ( (yy_n_chars) == 0 )
{
if ( number_to_move == YY_MORE_ADJ )
{
ret_val = EOB_ACT_END_OF_FILE;
yyrestart(yyin );
}
else
{
ret_val = EOB_ACT_LAST_MATCH;
YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
YY_BUFFER_EOF_PENDING;
}
}
else
ret_val = EOB_ACT_CONTINUE_SCAN;
if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
/* Extend the array by 50%, plus the number we really need. */
yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size );
if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
}
(yy_n_chars) += number_to_move;
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
return ret_val;
}
/* yy_get_previous_state - get the state just before the EOB char was reached */
static yy_state_type yy_get_previous_state (void)
{
register yy_state_type yy_current_state;
register char *yy_cp;
yy_current_state = (yy_start);
for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
{
register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
if ( yy_accept[yy_current_state] )
{
(yy_last_accepting_state) = yy_current_state;
(yy_last_accepting_cpos) = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 40 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
}
return yy_current_state;
}
/* yy_try_NUL_trans - try to make a transition on the NUL character
*
* synopsis
* next_state = yy_try_NUL_trans( current_state );
*/
static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
{
register int yy_is_jam;
register char *yy_cp = (yy_c_buf_p);
register YY_CHAR yy_c = 1;
if ( yy_accept[yy_current_state] )
{
(yy_last_accepting_state) = yy_current_state;
(yy_last_accepting_cpos) = yy_cp;
}
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
if ( yy_current_state >= 40 )
yy_c = yy_meta[(unsigned int) yy_c];
}
yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
yy_is_jam = (yy_current_state == 39);
return yy_is_jam ? 0 : yy_current_state;
}
static void yyunput (int c, register char * yy_bp )
{
register char *yy_cp;
yy_cp = (yy_c_buf_p);
/* undo effects of setting up yytext */
*yy_cp = (yy_hold_char);
if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
{ /* need to shift things up to make room */
/* +2 for EOB chars. */
register yy_size_t number_to_move = (yy_n_chars) + 2;
register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
register char *source =
&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
*--dest = *--source;
yy_cp += (int) (dest - source);
yy_bp += (int) (dest - source);
YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
YY_FATAL_ERROR( "flex scanner push-back overflow" );
}
*--yy_cp = (char) c;
(yytext_ptr) = yy_bp;
(yy_hold_char) = *yy_cp;
(yy_c_buf_p) = yy_cp;
}
#ifndef YY_NO_INPUT
#ifdef __cplusplus
static int yyinput (void)
#else
static int input (void)
#endif
{
int c;
*(yy_c_buf_p) = (yy_hold_char);
if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
{
/* yy_c_buf_p now points to the character we want to return.
* If this occurs *before* the EOB characters, then it's a
* valid NUL; if not, then we've hit the end of the buffer.
*/
if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
/* This was really a NUL. */
*(yy_c_buf_p) = '\0';
else
{ /* need more input */
yy_size_t offset = (yy_c_buf_p) - (yytext_ptr);
++(yy_c_buf_p);
switch ( yy_get_next_buffer( ) )
{
case EOB_ACT_LAST_MATCH:
/* This happens because yy_g_n_b()
* sees that we've accumulated a
* token and flags that we need to
* try matching the token before
* proceeding. But for input(),
* there's no matching to consider.
* So convert the EOB_ACT_LAST_MATCH
* to EOB_ACT_END_OF_FILE.
*/
/* Reset buffer status. */
yyrestart(yyin );
/*FALLTHROUGH*/
case EOB_ACT_END_OF_FILE:
{
if ( yywrap( ) )
return 0;
if ( ! (yy_did_buffer_switch_on_eof) )
YY_NEW_FILE;
#ifdef __cplusplus
return yyinput();
#else
return input();
#endif
}
case EOB_ACT_CONTINUE_SCAN:
(yy_c_buf_p) = (yytext_ptr) + offset;
break;
}
}
}
c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
*(yy_c_buf_p) = '\0'; /* preserve yytext */
(yy_hold_char) = *++(yy_c_buf_p);
return c;
}
#endif /* ifndef YY_NO_INPUT */
/** Immediately switch to a different input stream.
* @param input_file A readable stream.
*
* @note This function does not reset the start condition to @c INITIAL .
*/
void yyrestart (FILE * input_file )
{
if ( ! YY_CURRENT_BUFFER ){
yyensure_buffer_stack ();
YY_CURRENT_BUFFER_LVALUE =
yy_create_buffer(yyin,YY_BUF_SIZE );
}
yy_init_buffer(YY_CURRENT_BUFFER,input_file );
yy_load_buffer_state( );
}
/** Switch to a different input buffer.
* @param new_buffer The new input buffer.
*
*/
void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer )
{
/* TODO. We should be able to replace this entire function body
* with
* yypop_buffer_state();
* yypush_buffer_state(new_buffer);
*/
yyensure_buffer_stack ();
if ( YY_CURRENT_BUFFER == new_buffer )
return;
if ( YY_CURRENT_BUFFER )
{
/* Flush out information for old buffer. */
*(yy_c_buf_p) = (yy_hold_char);
YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
}
YY_CURRENT_BUFFER_LVALUE = new_buffer;
yy_load_buffer_state( );
/* We don't actually know whether we did this switch during
* EOF (yywrap()) processing, but the only time this flag
* is looked at is after yywrap() is called, so it's safe
* to go ahead and always set it.
*/
(yy_did_buffer_switch_on_eof) = 1;
}
static void yy_load_buffer_state (void)
{
(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
(yy_hold_char) = *(yy_c_buf_p);
}
/** Allocate and initialize an input buffer state.
* @param file A readable stream.
* @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
*
* @return the allocated buffer state.
*/
YY_BUFFER_STATE yy_create_buffer (FILE * file, int size )
{
YY_BUFFER_STATE b;
b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
b->yy_buf_size = size;
/* yy_ch_buf has to be 2 characters longer than the size given because
* we need to put in 2 end-of-buffer characters.
*/
b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 );
if ( ! b->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
b->yy_is_our_buffer = 1;
yy_init_buffer(b,file );
return b;
}
/** Destroy the buffer.
* @param b a buffer created with yy_create_buffer()
*
*/
void yy_delete_buffer (YY_BUFFER_STATE b )
{
if ( ! b )
return;
if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
if ( b->yy_is_our_buffer )
yyfree((void *) b->yy_ch_buf );
yyfree((void *) b );
}
#ifndef __cplusplus
extern int isatty (int );
#endif /* __cplusplus */
/* Initializes or reinitializes a buffer.
* This function is sometimes called more than once on the same buffer,
* such as during a yyrestart() or at EOF.
*/
static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file )
{
int oerrno = errno;
yy_flush_buffer(b );
b->yy_input_file = file;
b->yy_fill_buffer = 1;
/* If b is the current buffer, then yy_init_buffer was _probably_
* called from yyrestart() or through yy_get_next_buffer.
* In that case, we don't want to reset the lineno or column.
*/
if (b != YY_CURRENT_BUFFER){
b->yy_bs_lineno = 1;
b->yy_bs_column = 0;
}
b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
errno = oerrno;
}
/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
* @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
*
*/
void yy_flush_buffer (YY_BUFFER_STATE b )
{
if ( ! b )
return;
b->yy_n_chars = 0;
/* We always need two end-of-buffer characters. The first causes
* a transition to the end-of-buffer state. The second causes
* a jam in that state.
*/
b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
b->yy_buf_pos = &b->yy_ch_buf[0];
b->yy_at_bol = 1;
b->yy_buffer_status = YY_BUFFER_NEW;
if ( b == YY_CURRENT_BUFFER )
yy_load_buffer_state( );
}
/** Pushes the new state onto the stack. The new state becomes
* the current state. This function will allocate the stack
* if necessary.
* @param new_buffer The new state.
*
*/
void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
{
if (new_buffer == NULL)
return;
yyensure_buffer_stack();
/* This block is copied from yy_switch_to_buffer. */
if ( YY_CURRENT_BUFFER )
{
/* Flush out information for old buffer. */
*(yy_c_buf_p) = (yy_hold_char);
YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
}
/* Only push if top exists. Otherwise, replace top. */
if (YY_CURRENT_BUFFER)
(yy_buffer_stack_top)++;
YY_CURRENT_BUFFER_LVALUE = new_buffer;
/* copied from yy_switch_to_buffer. */
yy_load_buffer_state( );
(yy_did_buffer_switch_on_eof) = 1;
}
/** Removes and deletes the top of the stack, if present.
* The next element becomes the new top.
*
*/
void yypop_buffer_state (void)
{
if (!YY_CURRENT_BUFFER)
return;
yy_delete_buffer(YY_CURRENT_BUFFER );
YY_CURRENT_BUFFER_LVALUE = NULL;
if ((yy_buffer_stack_top) > 0)
--(yy_buffer_stack_top);
if (YY_CURRENT_BUFFER) {
yy_load_buffer_state( );
(yy_did_buffer_switch_on_eof) = 1;
}
}
/* Allocates the stack if it does not exist.
* Guarantees space for at least one push.
*/
static void yyensure_buffer_stack (void)
{
yy_size_t num_to_alloc;
if (!(yy_buffer_stack)) {
/* First allocation is just for 2 elements, since we don't know if this
* scanner will even need a stack. We use 2 instead of 1 to avoid an
* immediate realloc on the next call.
*/
num_to_alloc = 1;
(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
(num_to_alloc * sizeof(struct yy_buffer_state*)
);
if ( ! (yy_buffer_stack) )
YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
(yy_buffer_stack_max) = num_to_alloc;
(yy_buffer_stack_top) = 0;
return;
}
if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
/* Increase the buffer to prepare for a possible push. */
int grow_size = 8 /* arbitrary grow size */;
num_to_alloc = (yy_buffer_stack_max) + grow_size;
(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
((yy_buffer_stack),
num_to_alloc * sizeof(struct yy_buffer_state*)
);
if ( ! (yy_buffer_stack) )
YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" );
/* zero only the new slots.*/
memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
(yy_buffer_stack_max) = num_to_alloc;
}
}
/** Setup the input buffer state to scan directly from a user-specified character buffer.
* @param base the character buffer
* @param size the size in bytes of the character buffer
*
* @return the newly allocated buffer state object.
*/
YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size )
{
YY_BUFFER_STATE b;
if ( size < 2 ||
base[size-2] != YY_END_OF_BUFFER_CHAR ||
base[size-1] != YY_END_OF_BUFFER_CHAR )
/* They forgot to leave room for the EOB's. */
return 0;
b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
b->yy_buf_pos = b->yy_ch_buf = base;
b->yy_is_our_buffer = 0;
b->yy_input_file = 0;
b->yy_n_chars = b->yy_buf_size;
b->yy_is_interactive = 0;
b->yy_at_bol = 1;
b->yy_fill_buffer = 0;
b->yy_buffer_status = YY_BUFFER_NEW;
yy_switch_to_buffer(b );
return b;
}
/** Setup the input buffer state to scan a string. The next call to yylex() will
* scan from a @e copy of @a str.
* @param yystr a NUL-terminated string to scan
*
* @return the newly allocated buffer state object.
* @note If you want to scan bytes that may contain NUL values, then use
* yy_scan_bytes() instead.
*/
YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
{
return yy_scan_bytes(yystr,strlen(yystr) );
}
/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
* scan from a @e copy of @a bytes.
* @param bytes the byte buffer to scan
* @param len the number of bytes in the buffer pointed to by @a bytes.
*
* @return the newly allocated buffer state object.
*/
YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len )
{
YY_BUFFER_STATE b;
char *buf;
yy_size_t n, i;
/* Get memory for full buffer, including space for trailing EOB's. */
n = _yybytes_len + 2;
buf = (char *) yyalloc(n );
if ( ! buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
for ( i = 0; i < _yybytes_len; ++i )
buf[i] = yybytes[i];
buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
b = yy_scan_buffer(buf,n );
if ( ! b )
YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
/* It's okay to grow etc. this buffer, and we should throw it
* away when we're done.
*/
b->yy_is_our_buffer = 1;
return b;
}
#ifndef YY_EXIT_FAILURE
#define YY_EXIT_FAILURE 2
#endif
static void yy_fatal_error (yyconst char* msg )
{
(void) fprintf( stderr, "%s\n", msg );
exit( YY_EXIT_FAILURE );
}
/* Redefine yyless() so it works in section 3 code. */
#undef yyless
#define yyless(n) \
do \
{ \
/* Undo effects of setting up yytext. */ \
int yyless_macro_arg = (n); \
YY_LESS_LINENO(yyless_macro_arg);\
yytext[yyleng] = (yy_hold_char); \
(yy_c_buf_p) = yytext + yyless_macro_arg; \
(yy_hold_char) = *(yy_c_buf_p); \
*(yy_c_buf_p) = '\0'; \
yyleng = yyless_macro_arg; \
} \
while ( 0 )
/* Accessor methods (get/set functions) to struct members. */
/** Get the current line number.
*
*/
int yyget_lineno (void)
{
return yylineno;
}
/** Get the input stream.
*
*/
FILE *yyget_in (void)
{
return yyin;
}
/** Get the output stream.
*
*/
FILE *yyget_out (void)
{
return yyout;
}
/** Get the length of the current token.
*
*/
yy_size_t yyget_leng (void)
{
return yyleng;
}
/** Get the current token.
*
*/
char *yyget_text (void)
{
return yytext;
}
/** Set the current line number.
* @param line_number
*
*/
void yyset_lineno (int line_number )
{
yylineno = line_number;
}
/** Set the input stream. This does not discard the current
* input buffer.
* @param in_str A readable stream.
*
* @see yy_switch_to_buffer
*/
void yyset_in (FILE * in_str )
{
yyin = in_str ;
}
void yyset_out (FILE * out_str )
{
yyout = out_str ;
}
int yyget_debug (void)
{
return yy_flex_debug;
}
void yyset_debug (int bdebug )
{
yy_flex_debug = bdebug ;
}
static int yy_init_globals (void)
{
/* Initialization is the same as for the non-reentrant scanner.
* This function is called from yylex_destroy(), so don't allocate here.
*/
(yy_buffer_stack) = 0;
(yy_buffer_stack_top) = 0;
(yy_buffer_stack_max) = 0;
(yy_c_buf_p) = (char *) 0;
(yy_init) = 0;
(yy_start) = 0;
/* Defined in main.c */
#ifdef YY_STDINIT
yyin = stdin;
yyout = stdout;
#else
yyin = (FILE *) 0;
yyout = (FILE *) 0;
#endif
/* For future reference: Set errno on error, since we are called by
* yylex_init()
*/
return 0;
}
/* yylex_destroy is for both reentrant and non-reentrant scanners. */
int yylex_destroy (void)
{
/* Pop the buffer stack, destroying each element. */
while(YY_CURRENT_BUFFER){
yy_delete_buffer(YY_CURRENT_BUFFER );
YY_CURRENT_BUFFER_LVALUE = NULL;
yypop_buffer_state();
}
/* Destroy the stack itself. */
yyfree((yy_buffer_stack) );
(yy_buffer_stack) = NULL;
/* Reset the globals. This is important in a non-reentrant scanner so the next time
* yylex() is called, initialization will occur. */
yy_init_globals( );
return 0;
}
/*
* Internal utility routines.
*/
#ifndef yytext_ptr
static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
{
register int i;
for ( i = 0; i < n; ++i )
s1[i] = s2[i];
}
#endif
#ifdef YY_NEED_STRLEN
static int yy_flex_strlen (yyconst char * s )
{
register int n;
for ( n = 0; s[n]; ++n )
;
return n;
}
#endif
void *yyalloc (yy_size_t size )
{
return (void *) malloc( size );
}
void *yyrealloc (void * ptr, yy_size_t size )
{
/* The cast to (char *) in the following accommodates both
* implementations that use char* generic pointers, and those
* that use void* generic pointers. It works with the latter
* because both ANSI C and C++ allow castless assignment from
* any pointer type to void*, and deal with argument conversions
* as though doing an assignment.
*/
return (void *) realloc( (char *) ptr, size );
}
void yyfree (void * ptr )
{
free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
}
#define YYTABLES_NAME "yytables"
#line 60 "t3.lex"
int stmt(int val); //funcion recibe el valor y lo que es
int expr();
int exprP();
int term();
int termP();
int factor();
int stmt_lst();
int opt_stmts();
int main(){
int resultado = 0; //variable que me indica si es aceptado o no
res = yylex(); //leo caracter
if(res == IDE){ // si lo que leo es un ID
resultado = stmt(res); // llamo a stmt y guardo el resultado
}else if(res == IF){ // si es un IF
resultado = stmt(res); //llamo a stmt y guardo el resultado
}else if(res == WHILE){ //si es un WHILE
resultado = stmt(res); //llamo a stmt y guardo el resultado
}else if(res == BEG){ // si es BEGIN
resultado = stmt(res); //llamo a stmt y guardo el resultado
}
if(resultado == 0){ // si el resultado obtenido de cualquiera de los if anterior es 0 no se acepta
printf("NO ES ACEPTADO\n");
}else if(resultado == 1){ //si el resultado obtenido de los if anteriores es 1 se acepta el lenguaje
printf("SI ES ACEPTADO\n");
}
return resultado; //termino el programa
}
int stmt(int val){ //stmt recibe una cadena de lo que dice lo que se lee y el valor que representa lo que se lee
int resultado = 0; //variable que me indica si se acepta
int val2 = val;
if(val2 == IDE){ //si el resor que se recibe corresponde a IDE
res = yylex(); //me muevo dos espacios en busqueda de :=
res = yylex();
if(res == IGUAL){ //si lo que encuentro es := entonces vamos bien y el siguiente debe ser un expr
resultado = expr(); //llamo a expr para que analice el siguiente dato a leer y guardo el resultado
}else{ //si no encuentro un := entonces el lenguaje NO es aceptado
resultado = 0;
}
}else if(val2 == IF){ // si el valor leeido de entrada es IF
res = yylex(); // leo el siguiente elemento
resultado = expr(); // checo si es una expr
if(resultado == 1){ // si si es expr
if(res == THEN){ // checo que el siguiente resultado sea THEN
res = yylex(); // si si leeo el siguiente elemento
if((resultado = stmt(res)) == 1){ // y checo si es un stmt
resultado = 1; // si si todo esta bien regresa 1
}else {
resultado = 0; // si no regresa 0
}
}else{
resultado = 0;
}
}
}else if(val2 == WHILE){ //si el valor leeido es WHILE
res = yylex(); //leeo el siguiente elemento
resultado = expr(); //checo si es una expr
if(resultado == 1){ // si si
if(res == DO){ // checo que el siguiente elemento sea un DO
res = yylex(); // si si leeo lo que sigue
if((resultado = stmt(res)) == 1){ // checo que sea una stmt
resultado = 1; // regreso 1 si es una stmt
}else{
resultado = 0; // sino regreso 0
}
}else{
resultado = 0; // si el siguiente elemento no es DO regreso 0
}
}
}else if(val2 == BEG){ // if el valor leido es BEG
res = yylex(); // leeo otro elemento
if(res != 0){ // si no esta vacio entonces
resultado = opt_stmts(); // checo que es una stmt o una lista de stmt
if(resultado == 1){ // si esta correcto todo
res = yylex(); // leeo el siguiente caracter
if(res == END){ // si el siguiente caracter es un end regreso 1
resultado = 1;
}
}
}else{ // si es vacio entonces regreso 0
resultado = 0;
}
}
return resultado;
}
int expr(){ // expr es un metodo que analisa el siguiente dato a leer
int resultado = 0;
res = yylex(); //leeo el siguiente elemento
if((resultado = term()) == 1){ // se le manda a term para que analice que es y se guarda el resultado
resultado = exprP(); //si existe un term entonces se pasa a exprP para analizar lo que sigue a ese termino
}
return resultado; //se regresa un resultado
}
int exprP(){ //
int resultado = 0; //variable resultado
if(res == MAS){ // si lo leeido es un mas
res = yylex(); // leeo el siguiente elemento
if((resultado = term()) == 1){ // checo que sea un term si si
resultado = exprP(); // checo que ya no haya mas expreciones signo termino (+ 3) que agregar
}
}else if(res == MENOS){ // si lo leeido es un menos
res = yylex(); // checo el siguiente caracter
if((resultado = term()) == 1){ // checo que sea un termino
resultado = exprP(); // si si es un term entonces checo que no haya mas expreciones signo termino (- 3) que agregar
}else{ // si el lo leeido no es un term regreso 0
resultado = 0;
}
}else if(res == 0 || res == 1 || res == 15){ // si no es ni un mas ni un menos entonces
res = yylex();
res = yylex();
resultado = 1;
}else if(res == THEN){ // si leeo un THEN entonces regreso 1
return 1;
}
else if(res == DO){ // si leeo un DO entonces regreso 1
return 1;
}
else{ // si leeo cualquier cosa que no sea lo anterior regreso 0
resultado = 0;
}
return resultado; // regreso el resultado
}
int term(){ // metodo que checa si es un factor (id, numero, ( ) ) y sus posbiles concatenaciones
int resultado = 0;
if((resultado = factor()) == 1){ // checo que lo que leeo sea un factor si es asi checa si hay mas elementos
resultado = termP();
}
return resultado;
}
int termP(){ // termp analiza si hay mas elementos en lac adena que pertenescan al factor como una multiplicacion o una divicion
int val;
val = res;
int resultado = 0;
res = yylex(); // checo el siguiente elemento
if(res == POR){ // si es un por
res = yylex(); // leeo el siguiente elemento
if((resultado = factor()) == 1){ // checo que ele elemento leeido sea un numero o un id
resultado = termP(); // checo que no haya mas elemento que multiplicar o dividir
}
}else if(res == ENTRE){ // si es un entre
res = yylex(); // leeo el siguiente elemento
if((resultado = factor()) == 1){ // checo si es un numero o un id
resultado = termP(); // si si es entonces checo que no haya mas elementos que multiplicar o dividir
}
}else if(res == 0 || res == MAS || res == MENOS){ // si lo leeido es un 0 o un mas o un menos entonces regreso 1
resultado = 1;
}else if(res == 1 || res == 15){ // si es un id o un numero regreso 1
resultado = 1;
}else if(res == THEN){ // si lo leeido es then entonces regreso 1
return 1;
}else if(res == DO){ // si lo leeido es DO entonces regreso 1
return 1;
}else {
return 0;
}
return resultado;
}
int factor(){ // checa que lo que se leea sea un numero un id o un parentesis que abre o cierra
int resultado = 0;
if( res == PABRE){ // si es un PABRE entonces checa que lo que siga sea una exprecion y tenga un PCIERRA
resultado = expr();
res = yylex();
if (res == PCIERRA && resultado == 1){ // si si es una expresion y tiene un PCIERRA entonces regresa 1
return 1;
}
}else if(res == IDE){ // checa si es un ID
resultado = 1;
}else if(res == NUMERO){ //checa si es un NUMERO
resultado = 1;
}
return resultado;
}
int opt_stmts(){ //
int resultado = 0;
if (res != 0){
resultado = stmt_lst();
}else{
resultado = 0;
}
return resultado;
}
int stmt_lst(){
int resultado = 0;
resultado = stmt(res);
if(resultado == 1){
res = yylex();
if(res == PUNTOYCOMA){
resultado = stmt_lst();
}else if(res == 0 || res == END){
resultado = 1;
}else {
resultado = 0;
}
}else{
resultado = 0;
}
return resultado;
}
| [
"farey.duran@gmail.com"
] | farey.duran@gmail.com |
c18d87f406735461c406d258422dc7c13a81cc7b | 6ef6213d2fa39d1d0ab7e2373d882b9d263e8c6d | /ti_components/cg_tools/linux/ti-cgt-c6000_8.2.4/lib/src/atanhf.c | a0b09e661b1dfb93f3df7bfa946fc04c4f2b651b | [] | no_license | Zhangh2018/PROCESSOR_SDK_VISION_03_06_00_00 | 9c380d3167b156a11a8f21814e94ac5550cddc87 | 05c72de5d031006c7565d4234abd53670a926acd | refs/heads/master | 2021-10-16T13:43:05.313842 | 2019-02-11T09:10:44 | 2019-02-11T09:10:44 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,955 | c | /****************************************************************************/
/* atanhf.c v8.2.4 */
/* */
/* Copyright (c) 1997-2018 Texas Instruments Incorporated */
/* http://www.ti.com/ */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in */
/* the documentation and/or other materials provided with the */
/* distribution. */
/* */
/* Neither the name of Texas Instruments Incorporated nor the names */
/* of its contributors may be used to endorse or promote products */
/* derived from this software without specific prior written */
/* permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* */
/****************************************************************************/
#include "float_config.h"
#include "reald.h"
_CODE_ACCESS float atanhf(float x)
{
#include "atanhf_i.h"
}
| [
"yukichen@otobrite.com"
] | yukichen@otobrite.com |
7621f686f4f137181a8477b3f7270dd9ce2e0214 | 20673ba95c7aae14500531d3bb909ec3a10f2553 | /src/renderer.c | f8917f4913913cbba246544337a0608ee7d427e8 | [] | no_license | NaviRice/renderer | 514bd73791d91af8d8be057aea9986c470e0d6ca | 9e138968a3b588e36da2623395495a1b17e9527f | refs/heads/master | 2021-09-12T19:24:51.640404 | 2018-04-20T03:33:30 | 2018-04-20T03:33:30 | 110,404,707 | 1 | 0 | null | 2017-12-02T22:10:26 | 2017-11-12T04:28:52 | C | UTF-8 | C | false | false | 2,944 | c | //Sys includes
//local includes
#include "globaldefs.h"
#include "renderer.h"
//#include "glmanager.h"
#include "glfwmanager.h" //init
#include "glmanager.h" //init
#include "cvarmanager.h"
#include "matrixlib.h"
#include "entitymanager.h" //init
#include "contextmanager.h"
#include "headclient.h"
#include "naviclient.h"
#include "navmanager.h"
#include "gamecodemanager.h"
extern double glfwGetTime(void);
int shutitdown(){
printf("Shutting down\n");
gl_shutdown();
glfw_shutdown();
entity_shutdown();
cvar_shutdown();
//todo
return FALSE;
}
cvarcallback_t CVAR_test_callbacks[] = {cvar_print, 0};
cvar_t CVAR_test = {CVAR_SAVEABLE, "test", "testing help text", "53.5"};
int main(int argc, char *argv[]){
if(!cvar_init()){printf("Unable to init cvar\n"); shutitdown(); return 1;}
cvar_register(&CVAR_test);
cvar_t *ctest = cvar_findByNameRPOINT("test");
cvar_print(ctest);
CVAR_test.onchanges = CVAR_test_callbacks;
cvar_set("test", "127.1 101.0 53.2222");
cvar_unregister(ctest->myid);
// if(!entity_init()){printf("Unable to init entity\n"); shutitdown(); return 4;}
if(!glfw_init(800, 600, 24,1)){printf("Unable to init glfw\n"); shutitdown(); return 2;}
if(!gl_init()){printf("Unable to init gl\n"); shutitdown(); return 3;}
if(!gamecode_init()){printf("Unable to init gamecode\n"); shutitdown(); return 4;}
//todo move to gamecode but whatever
naviclient_init();
headclient_init();
nav_init();
double t, to;
to=glfwGetTime();
double timesincelastfpsupdate = 0.0;
int framecount = 0;
double accum = 0.0;
while(TRUE){ //temp
t = glfwGetTime();
double delta = t-to;
to = t;
timesincelastfpsupdate+=delta;
if(timesincelastfpsupdate > 5.0){
printf("%f fps: %i frames in %f seconds: %f ms per frame\n", (float)framecount/(float)timesincelastfpsupdate, framecount,
timesincelastfpsupdate, 1000.0*(float)timesincelastfpsupdate / (float) framecount);
framecount = 0;
timesincelastfpsupdate = 0;
}
framecount++;
accum += delta;
//grab most recent head
glfw_checkEvent();
//todo figure out if thise should be reordered
headclient_update(t);
naviclient_update(t);
// if(t > 1.0){
// t = 1.0;
// accum = 0.0;
// }
// t = 7.0;
while(accum * 1000.0 > GCTIMESTEP){
gamecode_tick();
accum -= (double)GCTIMESTEP/1000.0;
}
// headclient_update();
#ifdef USENEWRENDERER
context_switch(0);
gl_setupFirstbounceForRender(t);
gl_setupWorldForRender(t);
gl_setupDebugForRender(t);
gl_renderFirstbounce(t);
gl_renderScreen(t);
glfw_swapBuffers();
context_switch(1);
gl_renderDebug(t);
glfw_swapBuffers();
#else
//todo recalc viewport stuff here
context_switch(0);
gl_renderWorld(t);
gl_renderFirstbounce(t);
gl_renderFrame(t);
glfw_swapBuffers();
context_switch(1);
//todo move to context 1 once i verify that it worky
gl_renderDebug(t);
glfw_swapBuffers();
#endif
}
shutitdown();
return FALSE;
}
| [
"roboman2444@gmail.com"
] | roboman2444@gmail.com |
14f2918893608dcbda814d000ec27731854b2efb | 976f5e0b583c3f3a87a142187b9a2b2a5ae9cf6f | /source/linux/drivers/media/usb/gspca/extr_stk1135.c_stk1135_camera_disable.c | e22540920d879d43fd93bf2f3e8ff9b920e0cf26 | [] | no_license | isabella232/AnghaBench | 7ba90823cf8c0dd25a803d1688500eec91d1cf4e | 9a5f60cdc907a0475090eef45e5be43392c25132 | refs/heads/master | 2023-04-20T09:05:33.024569 | 2021-05-07T18:36:26 | 2021-05-07T18:36:26 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,635 | c | #define NULL ((void*)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t; typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1
/* Forward declarations */
/* Type definitions */
struct gspca_dev {int dummy; } ;
/* Variables and functions */
scalar_t__ STK1135_REG_CIEPO ;
scalar_t__ STK1135_REG_GCTRL ;
scalar_t__ STK1135_REG_SCTRL ;
scalar_t__ STK1135_REG_SENSO ;
scalar_t__ STK1135_REG_TMGEN ;
int /*<<< orphan*/ reg_w (struct gspca_dev*,scalar_t__,int) ;
int /*<<< orphan*/ reg_w_mask (struct gspca_dev*,scalar_t__,int,int) ;
int /*<<< orphan*/ sensor_write_mask (struct gspca_dev*,int,int,int) ;
__attribute__((used)) static void stk1135_camera_disable(struct gspca_dev *gspca_dev)
{
/* set capture end Y position to 0 */
reg_w(gspca_dev, STK1135_REG_CIEPO + 2, 0x00);
reg_w(gspca_dev, STK1135_REG_CIEPO + 3, 0x00);
/* disable capture */
reg_w_mask(gspca_dev, STK1135_REG_SCTRL, 0x00, 0x80);
/* enable sensor standby and diasble chip enable */
sensor_write_mask(gspca_dev, 0x00d, 0x0004, 0x000c);
/* disable PLL */
reg_w_mask(gspca_dev, STK1135_REG_SENSO + 2, 0x00, 0x01);
/* disable timing generator */
reg_w(gspca_dev, STK1135_REG_TMGEN, 0x00);
/* enable STOP clock */
reg_w(gspca_dev, STK1135_REG_SENSO + 1, 0x20);
/* disable CLKOUT for sensor */
reg_w(gspca_dev, STK1135_REG_SENSO, 0x00);
/* disable sensor (GPIO5) and enable GPIO0,3,6 (?) - sensor standby? */
reg_w(gspca_dev, STK1135_REG_GCTRL, 0x49);
} | [
"brenocfg@gmail.com"
] | brenocfg@gmail.com |
9dce21efba513ad9bc87f118731c4b5cb914e606 | 9d107a4d6451b6d352ed434fc3fa1bdec3c5791c | /sqlite/splitsource/mem1.c | ed3ff250d8fd0c5cff5fa6c7237784fc2cd619e5 | [] | no_license | HarrtTong/Bitcoin-History | d50c7476452fe4f1fa6c6634eb37b10c5f7db67a | ef06995188b4ccb3126d56710ada272c278169f8 | refs/heads/master | 2020-05-23T01:08:02.873643 | 2014-05-15T00:57:17 | 2014-05-15T00:57:17 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,885 | c | /*
** 2007 August 14
**
** The author disclaims copyright to this source code. In place of
** a legal notice, here is a blessing:
**
** May you do good and not evil.
** May you find forgiveness for yourself and forgive others.
** May you share freely, never taking more than you give.
**
*************************************************************************
**
** This file contains low-level memory allocation drivers for when
** SQLite will use the standard C-library malloc/realloc/free interface
** to obtain the memory it needs.
**
** This file contains implementations of the low-level memory allocation
** routines specified in the sqlite3_mem_methods object.
**
** $Id: mem1.c,v 1.26 2008/09/01 18:34:20 danielk1977 Exp $
*/
#include "sqliteInt.h"
/*
** This version of the memory allocator is the default. It is
** used when no other memory allocator is specified using compile-time
** macros.
*/
#ifdef SQLITE_SYSTEM_MALLOC
/*
** Like malloc(), but remember the size of the allocation
** so that we can find it later using sqlite3MemSize().
**
** For this low-level routine, we are guaranteed that nByte>0 because
** cases of nByte<=0 will be intercepted and dealt with by higher level
** routines.
*/
static void *sqlite3MemMalloc(int nByte){
sqlite3_int64 *p;
assert( nByte>0 );
nByte = (nByte+7)&~7;
p = malloc( nByte+8 );
if( p ){
p[0] = nByte;
p++;
}
return (void *)p;
}
/*
** Like free() but works for allocations obtained from sqlite3MemMalloc()
** or sqlite3MemRealloc().
**
** For this low-level routine, we already know that pPrior!=0 since
** cases where pPrior==0 will have been intecepted and dealt with
** by higher-level routines.
*/
static void sqlite3MemFree(void *pPrior){
sqlite3_int64 *p = (sqlite3_int64*)pPrior;
assert( pPrior!=0 );
p--;
free(p);
}
/*
** Like realloc(). Resize an allocation previously obtained from
** sqlite3MemMalloc().
**
** For this low-level interface, we know that pPrior!=0. Cases where
** pPrior==0 while have been intercepted by higher-level routine and
** redirected to xMalloc. Similarly, we know that nByte>0 becauses
** cases where nByte<=0 will have been intercepted by higher-level
** routines and redirected to xFree.
*/
static void *sqlite3MemRealloc(void *pPrior, int nByte){
sqlite3_int64 *p = (sqlite3_int64*)pPrior;
assert( pPrior!=0 && nByte>0 );
nByte = (nByte+7)&~7;
p = (sqlite3_int64*)pPrior;
p--;
p = realloc(p, nByte+8 );
if( p ){
p[0] = nByte;
p++;
}
return (void*)p;
}
/*
** Report the allocated size of a prior return from xMalloc()
** or xRealloc().
*/
static int sqlite3MemSize(void *pPrior){
sqlite3_int64 *p;
if( pPrior==0 ) return 0;
p = (sqlite3_int64*)pPrior;
p--;
return p[0];
}
/*
** Round up a request size to the next valid allocation size.
*/
static int sqlite3MemRoundup(int n){
return (n+7) & ~7;
}
/*
** Initialize this module.
*/
static int sqlite3MemInit(void *NotUsed){
return SQLITE_OK;
}
/*
** Deinitialize this module.
*/
static void sqlite3MemShutdown(void *NotUsed){
return;
}
const sqlite3_mem_methods *sqlite3MemGetDefault(void){
static const sqlite3_mem_methods defaultMethods = {
sqlite3MemMalloc,
sqlite3MemFree,
sqlite3MemRealloc,
sqlite3MemSize,
sqlite3MemRoundup,
sqlite3MemInit,
sqlite3MemShutdown,
0
};
return &defaultMethods;
}
/*
** This routine is the only routine in this file with external linkage.
**
** Populate the low-level memory allocation function pointers in
** sqlite3GlobalConfig.m with pointers to the routines in this file.
*/
void sqlite3MemSetDefault(void){
sqlite3_config(SQLITE_CONFIG_MALLOC, sqlite3MemGetDefault());
}
#endif /* SQLITE_SYSTEM_MALLOC */
| [
"shenjian74@gmail.com"
] | shenjian74@gmail.com |
8fab794a02d9e03f26cae2099f7e1fa7bbec0e54 | 5d52c6480d1321dea2d15b5ee46685bde993f95a | /kelley_pohl/chapter_6/find_roots/fct.c | 373e4d8c2ac45c78757cf0dd5f07f8c4999e3a09 | [] | no_license | rdp84/c-exercises | 7c8bcb52cb97f2c5c81f137fdd739f20812406d1 | 3f8e44a99e473232a145b3247f27b66f04fa599b | refs/heads/master | 2023-08-07T15:33:59.525680 | 2022-09-22T16:28:36 | 2022-09-22T16:28:36 | 119,397,230 | 0 | 0 | null | 2022-09-22T16:28:37 | 2018-01-29T14:59:48 | C | UTF-8 | C | false | false | 110 | c | #include "find_root.h"
dbl f(dbl x)
{
return ((x * x * x * x * x) - (7.0 * x) - 3.0); /* x^5 - 7x - 3 */
}
| [
"pearson.bobby@gmail.com"
] | pearson.bobby@gmail.com |
6621666254780f0d4a09de1d73cd8bd50daa40f7 | 039f44329601436936848a79f0d817983f74a04b | /psptest/output/qt4/psptest/tools_align.h | f49bcfe957c8802420973c83f2eafad7f3fa2599 | [] | no_license | priyanshu-sekhar/GenApp | 52e98bfa56213f48de912de368d4a974055758bc | e881f8aa478a7af0351c2ae3175e30b8f62e8e67 | refs/heads/master | 2016-09-06T17:05:05.575066 | 2015-08-23T18:22:33 | 2015-08-23T18:22:33 | 37,317,585 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 8,685 | h | void psptest::module_load_tools_align()
{
delete_widgets_layouts( panel1_sub_widgets, panel1_sub_layouts );
panel1_widget_map.clear();
panel1_inputs.clear();
panel1_outputs.clear();
panel1_map_input.clear();
panel1_is_input.clear();
current_module_id = "align";
{
QLabel * lbl = new QLabel( "", this );
lbl->setMaximumHeight( 12 );
lbl->show();
gl_panel1->addWidget( lbl, 1, 0 );
panel1_sub_widgets.push_back( lbl );
}
QGridLayout * gl = new QGridLayout( 0 ); //, 1, 1, 3, 3 );
{
QLabel * lbl = new QLabel( "", this );
lbl->setMaximumHeight( 12 );
lbl->show();
gl->addWidget( lbl, 0, 2 );
panel1_sub_widgets.push_back( lbl );
}
int ppos = 0; // the base position in the gl_sub_panel
{
QLabel * lbl = new QLabel( "Align value 1 ", this );
lbl->setMaximumHeight( 22 );
lbl->show();
gl->addWidget( lbl, ppos, 0 );
panel1_sub_widgets.push_back( lbl );
QLineEdit * le = new QLineEdit( this );
le->setMaximumHeight( 22 );
// le->setPalette( *palette_le );
le->setValidator( new QDoubleValidator( le ) );
((QDoubleValidator*)le->validator())->setDecimals( 8 );
le->setText( QString( "%1" ).arg( 0 ) );
((QDoubleValidator*)le->validator())->setBottom( 0 );
((QDoubleValidator*)le->validator())->setTop( 1e+50 );
le->show();
gl->addWidget( le, ppos, 1 );
panel1_sub_widgets.push_back( le );
QString id = "align:input1";
global_data_types[ id ] = "le";
panel1_widget_map[ id ] = le;
panel1_inputs.push_back( id );
save_default_value( id );
ppos++;
}
{
QLabel * lbl = new QLabel( "Align value 2 ", this );
lbl->setMaximumHeight( 22 );
lbl->show();
gl->addWidget( lbl, ppos, 0 );
panel1_sub_widgets.push_back( lbl );
QLineEdit * le = new QLineEdit( this );
le->setMaximumHeight( 22 );
// le->setPalette( *palette_le );
le->setValidator( new QIntValidator( le ) );
le->setText( QString( "%1" ).arg( 1 ) );
((QIntValidator*)le->validator())->setBottom( -10 );
((QIntValidator*)le->validator())->setTop( 10 );
le->show();
gl->addWidget( le, ppos, 1 );
panel1_sub_widgets.push_back( le );
QString id = "align:input2";
global_data_types[ id ] = "le";
panel1_widget_map[ id ] = le;
panel1_inputs.push_back( id );
save_default_value( id );
ppos++;
}
{
mQLabel * lbl = new mQLabel( "Align value 3 ", this );
lbl->setMaximumHeight( 22 );
lbl->show();
gl->addWidget( lbl, ppos, 0 );
panel1_sub_widgets.push_back( lbl );
QCheckBox * cb = new QCheckBox( this );
cb->setMaximumHeight( 22 );
// cb->setPalette( *palette_cb );
cb->setChecked( true );
cb->show();
gl->addWidget( cb, ppos, 1 );
panel1_sub_widgets.push_back( cb );
connect( lbl, SIGNAL( pressed() ), cb, SLOT( toggle() ) );
QString id = "align:input3";
global_data_types[ id ] = "cb";
panel1_widget_map[ id ] = cb;
panel1_inputs.push_back( id );
save_default_value( id );
ppos++;
}
QHBoxLayout * hbl = new QHBoxLayout( 0 );
{
mQPushButton * pb = new mQPushButton( this );
pb->setText( "Submit" );
pb->setMaximumHeight( 22 );
pb->show();
connect( pb, SIGNAL( clicked() ), SLOT( module_submit_tools_align() ) );
hbl->addWidget( pb );
hbl->addSpacing( 3 );
panel1_sub_widgets.push_back( pb );
}
{
mQPushButton * pb = new mQPushButton( this );
pb->setText( "Reset to default values" );
pb->setMaximumHeight( 22 );
pb->show();
connect( pb, SIGNAL( clicked() ), SLOT(module_reset_tools_align() ) );
hbl->addWidget( pb );
panel1_sub_widgets.push_back( pb );
}
gl->addLayout( hbl, ppos, 0, 1, 2 );
panel1_sub_layouts.push_back( hbl );
ppos++;
{
QLabel * lbl = new QLabel( "", this );
// lbl->setPalette( *palette_lbl_error );
lbl->show();
gl->addWidget( lbl, ppos, 0, 1, 2 );
panel1_sub_widgets.push_back( lbl );
QString id = "align:_errorMessages";
global_data_types[ id ] = "lbl";
panel1_widget_map[ id ] = lbl;
panel1_inputs.push_back( id );
save_default_value( id );
}
ppos++;
{
QLabel * lbl = new QLabel( "Output value 1 ", this );
lbl->setMaximumHeight( 22 );
lbl->show();
gl->addWidget( lbl, ppos, 0 );
panel1_sub_widgets.push_back( lbl );
QLineEdit * le = new QLineEdit( this );
le->setMaximumHeight( 22 );
// le->setPalette( *palette_le );
le->setReadOnly( true );
le->show();
gl->addWidget( le, ppos, 1 );
panel1_sub_widgets.push_back( le );
QString id = "align:output1";
global_data_types[ id ] = "le";
panel1_widget_map[ id ] = le;
panel1_outputs.push_back( id );
save_default_value( id );
ppos++;
}
reset_last_values();
gl->setColumnStretch( 0, 0 );
gl->setColumnStretch( 1, 0 );
gl->setColumnStretch( 2, 1 );
gl_panel1->addLayout( gl, 2, 0, 1, 3 );
panel1_sub_layouts.push_back( gl );
for ( int i = 0; i < (int) panel1_inputs.size(); ++i )
{
panel1_is_input[ panel1_inputs[ i ] ] = true;
}
}
void psptest::module_reset_tools_align()
{
reset_default_values();
}
void psptest::module_submit_tools_align()
{
save_last_values();
reset_output_values( "default_value" );
// we should check if process already running
QString program = "/home/priyanshu-sekhar/airavata-sandbox/genapp-airavata-gsoc2015/GenApp-Priyanshu/psptest/bin/align";
QFileInfo qfi( program );
if ( !qfi.exists() || !qfi.isExecutable() || qfi.isDir() )
{
QString id = "align";
QString key = id + ":_errorMessages";
global_data[ key + ":last_value" ] = QVariant( "Unexpected results:\n error => command not found or not executable" );
if ( current_module_id == id &&
global_data_types.count( key ) )
{
reset_value( key, "last_value" );
}
return;
}
process_json[ "align" ] = "";
qDebug() << "process started";
string tprojId = createProject("user", "align");
char *projId = new char[tprojId.length() + 1];
strcpy(projId, tprojId.c_str());
QString tmp = input_to_json( "align" );
string tjson = tmp.toUtf8().constData();
char *json = new char[tjson.length() + 1];
strcpy(json, tjson.c_str());
Register* register_;
register_ = Register::getInstance();
string module = "align";
string experiment = "Experiment";
char* expName = new char[module.length() + experiment.length() + 1];
strcpy(expName,module.c_str());
strcat(expName,experiment.c_str());
string tappId = register_->getInterfaceId("Align");
char* appId = new char[tappId.length()+1];
strcpy(appId,tappId.c_str());
string texpId = createExperiment("user", expName , projId, appId, json);
char *expId = new char[texpId.length() + 1];
strcpy(expId, texpId.c_str());
launchExperiment(expId);
while((getExperimentStatus(expId))!=8){
cout << "status" << getExperimentStatus(expId) << endl;
if(getExperimentStatus(expId)==9)
{
cout << "Experiment Failed" << endl;
break;
}
unsigned int microseconds = 30000;
usleep(microseconds);
}
if(getExperimentStatus(expId)==8)
{
unsigned int microseconds = 500000;
usleep(microseconds);
string output = getExperimentOutput(expId);
QString qoutput = QString::fromStdString(output);
process_json[ "align" ] = qoutput;
qDebug() << "process_tools_align->finished()";
qDebug() << qoutput;
process_results( "align" );
}
if(getExperimentStatus(expId)==9)
exit(1);
}
void psptest::readyReadStandardOutput_tools_align()
{
process_json[ "align" ] += QString( process_tools_align->readAllStandardOutput() );
}
void psptest::readyReadStandardError_tools_align()
{
qDebug() << process_tools_align->readAllStandardError();
}
void psptest::error_tools_align( QProcess::ProcessError e )
{
qDebug() << "process_tools_align->error()" << e;
}
void psptest::finished_tools_align( int, QProcess::ExitStatus )
{
qDebug() << "process_tools_align->finished()";
readyReadStandardOutput_tools_align();
readyReadStandardError_tools_align();
disconnect( process_tools_align, 0, 0, 0 );
// post process data into output fields, add unexpected data etc
// delete process_tools_align;
// process_tools_align = (QProcess *) 0;
process_results( "align" );
}
| [
"pri.patra@gmail.com"
] | pri.patra@gmail.com |
9560b3da1e2b04962d88f6882a32ae35454a2387 | ba1bc65118e9d130ccb4ae96a29fafcc7fd27a54 | /src/VmCommon/src/fields.h | 5fb8a19b2617e591895cd9d45986dc3a097a59db | [] | no_license | ganyao114/j2me | 9497fb1345f6cecf35d8e5d50e10057a333204e2 | bcc1d7ea68f0764b726023431cd8cee2b9acbf0c | refs/heads/master | 2020-03-27T01:10:12.121310 | 2017-08-01T03:24:03 | 2017-08-01T03:24:03 | null | 0 | 0 | null | null | null | null | WINDOWS-1252 | C | false | false | 9,997 | h | /*
* Copyright © 2003 Sun Microsystems, Inc. All rights reserved.
* SUN PROPRIETARY/CONFIDENTIAL. Use is subject to license terms.
*
*/
/*=========================================================================
* SYSTEM: KVM
* SUBSYSTEM: Internal runtime structures
* FILE: fields.h
* OVERVIEW: Internal runtime structures for storing different kinds
* of fields (constants, variables, methods, interfaces).
* Tables of these fields are created every time a new class
* is loaded into the virtual machine.
* AUTHOR: Antero Taivalsaari, Sun Labs
* Edited by Doug Simon 11/1998
* Sheng Liang, Frank Yellin
*=======================================================================*/
/*=========================================================================
* COMMENTS:
* This file defines the VM-specific internal runtime structures
* needed for representing fields, methods and interfaces.
*=======================================================================*/
/*=========================================================================
* Include files
*=======================================================================*/
/*=========================================================================
* COMMENTS:
* FIELD is the basic structure that is used for representing
* information about instance variables, static variables, constants
* and static methods. It is used as a component in constant pool
* and instance variable tables stored in CLASS structures.
*
* Method tables use a slightly larger structure (METHOD)
* which is a logical subtype of FIELD.
*
* Note: to speed up stack frame generation at runtime, we calculate
* the number of parameters (argCount) and local variables (localCount)
* for each method in advance upon class loading.
*=======================================================================*/
/*=========================================================================
* IMPORTANT: If you change the order of any of the data elements
* in these data structures, make sure that the order matches
* with the corresponding data structures in 'rom.h'.
*=======================================================================*/
#include "global.h"
/* FIELD */
struct fieldStruct {
NameTypeKey nameTypeKey;
long accessFlags; /* Access indicators (public/private etc.) */
INSTANCE_CLASS ofClass; /* Backpointer to the class owning the field */
union {
long offset; /* for dynamic objects */
void *staticAddress; /* pointer to static. */
} u;
};
struct fieldTableStruct {
long length;
struct fieldStruct fields[1];
};
/* METHOD */
struct methodStruct {
NameTypeKey nameTypeKey;
union {
struct {
BYTE* code;
HANDLERTABLE handlers;
union {
STACKMAP pointerMap;
POINTERLIST verifierMap;
} stackMaps;
unsigned short codeLength;
unsigned short maxStack;
/* frameSize should be here, rather than in the generic part, */
/* but this gives us better packing of the bytes */
} java;
struct {
void (*code)(void);
void *info;
} native;
} u;
long accessFlags; /* Access indicators (public/private etc.) */
INSTANCE_CLASS ofClass; /* Backpointer to the class owning the field */
unsigned short frameSize; /* Method frame size (arguments+local vars) */
unsigned short argCount; /* Method argument (parameter) count */
};
struct methodTableStruct {
long length;
struct methodStruct methods[1];
};
/*=========================================================================
* COMMENTS:
* STACKMAPs are used internally by the KVM to store
* information that the runtime part of the classfile
* verifier can utilize to speed up verification.
* This information is also utilized by the exact
* garbage collector.
*=======================================================================*/
#define STACK_MAP_SHORT_ENTRY_FLAG 0x8000
#define STACK_MAP_ENTRY_COUNT_MASK 0x7FFF
#define STACK_MAP_SHORT_ENTRY_OFFSET_MASK 0xFFF
#define STACK_MAP_SHORT_ENTRY_MAX_OFFSET 0xFFF
#define STACK_MAP_SHORT_ENTRY_MAX_STACK_SIZE 0xF
struct stackMapStruct {
/* The high bit of nEntries is a flag indicating whether the structs are
* short entries or not.
* If this is a short entry
* The low 12 bits of offset are the actual offset
* The high 4 bits of offset are the operand stack size
* stackMapKey is a bitmap giving the live locals and operand
* stacks. ((char *)stackMapKey)[0] contains the low 8 bits and
* ((char *)stackMapKey)[1] contains the high 8 bits.
* If this isn't a short entry, then offset is the actual 16-bit offset.
* Stackmap key is an entry in the name table. The first byte of the
* entry is the stack size. The remaining bytes are a variable length
* bitmap.
*/
unsigned short nEntries;
struct stackMapEntryStruct {
unsigned short offset;
unsigned short stackMapKey;
} entries[1];
};
/*=========================================================================
* COMMENTS:
* The Java-level debugging interfaces need access to line number
* information. The following structures are used for storing
* that information.
*=======================================================================*/
#if ENABLE_JAVA_DEBUGGER
struct lineNumberStruct {
unsigned short start_pc;
unsigned short line_number;
};
struct lineNumberTableStruct {
unsigned short length;
struct lineNumberStruct lineNumber[1];
};
#endif /* ENABLE_JAVA_DEBUGGER */
/*=========================================================================
* Sizes of the data structures above
*=======================================================================*/
#define SIZEOF_FIELD StructSizeInCells(fieldStruct)
#define SIZEOF_METHOD StructSizeInCells(methodStruct)
#define SIZEOF_METHODTABLE(n) \
(StructSizeInCells(methodTableStruct) + (n - 1) * SIZEOF_METHOD)
#define SIZEOF_FIELDTABLE(n) \
(StructSizeInCells(fieldTableStruct) + (n - 1) * SIZEOF_FIELD)
/*=========================================================================
* Operations on field and method tables
*=======================================================================*/
FIELD lookupField(INSTANCE_CLASS thisClass, NameTypeKey key);
METHOD lookupMethod(CLASS thisClass, NameTypeKey key,
INSTANCE_CLASS currentClass);
METHOD lookupDynamicMethod(CLASS objectClass, METHOD declaredMethod);
METHOD getSpecialMethod(INSTANCE_CLASS thisClass, NameTypeKey key);
#if ENABLEPROFILING
int getMethodTableSize(METHODTABLE methodTable);
#else
# define getMethodTableSize(table) 0
#endif
/*=========================================================================
* Debugging and printing operations
*=======================================================================*/
#if INCLUDEDEBUGCODE
void printFieldTable(FIELDTABLE fieldTable);
void printMethodTable(METHODTABLE methodTable);
void printFieldName(FIELD fieldTable, LOGFILEPTR file);
void printMethodName(METHOD methodTable, LOGFILEPTR file);
#else
# define printFieldTable(x)
# define printMethodTable(y)
# define printFieldName(x, y)
# define printMethodName(x, y)
#endif
/*=========================================================================
* Iterators
*=======================================================================*/
#define FOR_EACH_METHOD(__var__, methodTable) { \
if (methodTable != NULL) { \
METHOD __first_method__ = methodTable->methods; \
METHOD __end_method__ = __first_method__ + methodTable->length; \
METHOD __var__; \
for (__var__ = __first_method__; __var__ < __end_method__; __var__++) {
#define END_FOR_EACH_METHOD } } }
#define FOR_EACH_FIELD(__var__, fieldTable) { \
if (fieldTable != NULL) { \
FIELD __first_field__ = fieldTable->fields; \
FIELD __end_field__ = __first_field__ + fieldTable->length; \
FIELD __var__; \
for (__var__ = __first_field__; __var__ < __end_field__; __var__++) {
#define END_FOR_EACH_FIELD } } }
/*=========================================================================
* Internal operations on signatures
*=======================================================================*/
#define methodName(method) \
(change_Key_to_Name((method)->nameTypeKey.nt.nameKey, NULL))
#define fieldName(field) \
(change_Key_to_Name((field)->nameTypeKey.nt.nameKey, NULL))
#define getMethodSignature(method) \
change_Key_to_MethodSignature((method)->nameTypeKey.nt.typeKey)
#define getFieldSignature(field) \
change_Key_to_FieldSignature((field)->nameTypeKey.nt.typeKey)
char *change_Key_to_FieldSignature(FieldTypeKey);
char *change_Key_to_FieldSignature_inBuffer(FieldTypeKey, char *result);
char *change_Key_to_MethodSignature(MethodTypeKey);
char *change_Key_to_MethodSignature_inBuffer(MethodTypeKey, char *result);
FieldTypeKey change_FieldSignature_to_Key(CONST_CHAR_HANDLE, int offset,
int length);
MethodTypeKey change_MethodSignature_to_Key(CONST_CHAR_HANDLE, int offset,
int length);
NameTypeKey getNameAndTypeKey(const char* name, const char* type);
#define FIELD_KEY_ARRAY_SHIFT 13
#define FIELD_KEY_MASK 0x1FFF
#define MAX_FIELD_KEY_ARRAY_DEPTH 7
| [
"wychenjiechen@jd.com"
] | wychenjiechen@jd.com |
ee62d5497141a31a4913593354dc6dbe71796b34 | 1c27b37dd3f961cf9911fd9e1e9166f61dc35a00 | /j/e/parse.c | ad1f636a282a756bf6b6dd93632a1289ad166787 | [
"MIT",
"LicenseRef-scancode-public-domain"
] | permissive | yosoyubik/urbit-2015 | 7d635bba9795dfc755aa1f54416092f16d142853 | 5b625d11d950c38e2c4d974f494508bf45738d43 | refs/heads/master | 2021-08-19T11:25:39.698165 | 2019-09-01T09:52:32 | 2019-09-01T09:52:32 | 205,657,485 | 0 | 0 | MIT | 2020-07-18T03:44:40 | 2019-09-01T09:51:06 | C | UTF-8 | C | false | false | 22,441 | c | /* j/5/parse.c
**
*/
#include "all.h"
static u3_noun
_slip(
u3_noun weq,
u3_noun naz)
{
u3_noun p_naz, q_naz;
u3x_cell(naz, &p_naz, &q_naz);
if ( 10 == weq ) {
return u3nc(u3x_good(
u3i_vint(u3k(p_naz))),
1);
} else {
return u3nc(u3k(p_naz),
u3x_good(
u3i_vint(u3k(q_naz))));
}
}
static u3_noun
_fail(
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
return u3nc(u3k(p_tub), u3_nul);
}
static u3_noun
_last(
u3_noun zyc,
u3_noun naz)
{
u3_noun p_zyc, q_zyc, p_naz, q_naz;
u3x_cell(zyc, &p_zyc, &q_zyc);
u3x_cell(naz, &p_naz, &q_naz);
if ( !_(u3a_is_cat(p_zyc)) || !_(u3a_is_cat(q_zyc)) ||
!_(u3a_is_cat(p_naz)) || !_(u3a_is_cat(q_naz)) )
{
return u3m_bail(c3__fail);
} else {
if ( p_zyc == p_naz ) {
return (q_zyc > q_naz) ? u3k(zyc) : u3k(naz);
}
else {
return (p_zyc > p_naz) ? u3k(zyc) : u3k(naz);
}
}
}
static u3_noun
_next(
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3_noun zac;
u3x_cell(tub, &p_tub, &q_tub);
if ( c3n == u3du(q_tub) ) {
return _fail(tub);
}
else {
u3_noun iq_tub = u3h(q_tub);
u3_noun tq_tub = u3t(q_tub);
zac = _slip(iq_tub, p_tub);
return u3nc
(zac,
u3nq(u3_nul,
u3k(iq_tub),
u3k(zac),
u3k(tq_tub)));
}
}
/* bend
*/
u3_noun
_cqe_bend_fun(u3_noun raq,
u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
} else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, yur;
u3_noun p_yit, q_yit;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
yur = _last(p_vex, p_yit);
if ( c3n == u3du(q_yit) ) {
ret = u3nc(yur, u3k(q_vex));
}
else {
u3_noun uq_yit = u3t(q_yit);
u3_noun puq_yit, quq_yit;
u3_noun vux;
u3x_cell(uq_yit, &puq_yit, &quq_yit);
vux = u3x_good
(u3n_slam_on
(u3k(raq),
u3nc(u3k(puq_vex),
u3k(puq_yit))));
if ( u3_nul == vux ) {
ret = u3nc(yur, u3k(q_vex));
}
else {
ret = u3nq(yur,
u3_nul,
u3k(u3t(vux)),
u3k(quq_yit));
u3z(vux);
}
}
u3z(yit);
return ret;
}
}
u3_noun
u3we_bend_fun(u3_noun cor)
{
u3_noun van, raq, vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex,
u3x_sam_3, &sab,
u3x_con, &van, 0)) ||
(u3_none == (raq = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_bend_fun(raq, vex, sab);
}
}
/* cold
*/
u3_noun
_cqe_cold_fun(
u3_noun cus,
u3_noun sef,
u3_noun tub)
{
u3_noun vex = u3x_good(u3n_slam_on(u3k(sef), u3k(tub)));
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return vex;
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun quq_vex;
u3_noun ret;
u3x_cell(uq_vex, 0, &quq_vex);
ret = u3nq(u3k(p_vex),
u3_nul,
u3k(cus),
u3k(quq_vex));
u3z(vex);
return ret;
}
}
u3_noun
u3we_cold_fun(
u3_noun cor)
{
u3_noun van, cus, sef, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(c3n == u3r_mean(van, u3x_sam_2, &cus, u3x_sam_3, &sef, 0)) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_cold_fun(cus, sef, tub);
}
}
/* cook
*/
u3_noun
_cqe_cook_fun(
u3_noun poq,
u3_noun sef,
u3_noun tub)
{
u3_noun vex = u3x_good(u3n_slam_on(u3k(sef), u3k(tub)));
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return vex;
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun wag;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
wag = u3x_good(u3n_slam_on(u3k(poq), u3k(puq_vex)));
ret = u3nq(u3k(p_vex),
u3_nul,
wag,
u3k(quq_vex));
u3z(vex);
return ret;
}
}
u3_noun
u3we_cook_fun(
u3_noun cor)
{
u3_noun van, poq, sef, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(c3n == u3r_mean(van, u3x_sam_2, &poq, u3x_sam_3, &sef, 0)) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_cook_fun(poq, sef, tub);
}
}
/* comp
*/
u3_noun
_cqe_comp_fun(
u3_noun raq,
u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
} else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, yur;
u3_noun p_yit, q_yit;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
yur = _last(p_vex, p_yit);
if ( c3n == u3du(q_yit) ) {
ret = u3nc(yur, u3k(q_yit));
}
else {
u3_noun uq_yit = u3t(q_yit);
u3_noun puq_yit, quq_yit;
u3x_cell(uq_yit, &puq_yit, &quq_yit);
ret = u3nq(yur,
u3_nul,
u3x_good
(
u3n_slam_on
(u3k(raq),
u3nc(u3k(puq_vex),
u3k(puq_yit)))),
u3k(quq_yit));
}
u3z(yit);
return ret;
}
}
u3_noun
u3we_comp_fun(
u3_noun cor)
{
u3_noun van, raq, vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex,
u3x_sam_3, &sab,
u3x_con, &van, 0)) ||
(u3_none == (raq = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_comp_fun(raq, vex, sab);
}
}
/* easy
*/
u3_noun
_cqe_easy_fun(
u3_noun huf,
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
return u3nq(u3k(p_tub),
u3_nul,
u3k(huf),
u3k(tub));
}
u3_noun
u3we_easy_fun(
u3_noun cor)
{
u3_noun van, huf, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(u3_none == (huf = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_easy_fun(huf, tub);
}
}
/* glue
*/
u3_noun
_cqe_glue_fun(
u3_noun bus,
u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, yur;
u3_noun p_yit, q_yit;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(bus), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
yur = _last(p_vex, p_yit);
if ( c3n == u3du(q_yit) ) {
ret = u3nc(yur, u3_nul);
}
else {
u3_noun uq_yit = u3t(q_yit);
u3_noun puq_yit, quq_yit;
u3_noun wam, p_wam, q_wam, goy;
u3x_cell(uq_yit, &puq_yit, &quq_yit);
wam = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_yit)));
u3x_cell(wam, &p_wam, &q_wam);
goy = _last(yur, p_wam);
u3z(yur);
if ( c3n == u3du(q_wam) ) {
ret = u3nc(goy, u3_nul);
} else {
u3_noun uq_wam = u3t(q_wam);
u3_noun puq_wam, quq_wam;
u3x_cell(uq_wam, &puq_wam, &quq_wam);
ret = u3nq(goy,
u3_nul,
u3nc(u3k(puq_vex),
u3k(puq_wam)),
u3k(quq_wam));
}
u3z(wam);
}
u3z(yit);
return ret;
}
}
u3_noun
u3we_glue_fun(
u3_noun cor)
{
u3_noun van, bus, vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex,
u3x_sam_3, &sab,
u3x_con, &van, 0)) ||
(u3_none == (bus = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_glue_fun(bus, vex, sab);
}
}
/* here
*/
u3_noun
_cqe_here_fun(
u3_noun hez,
u3_noun sef,
u3_noun tub)
{
u3_noun vex = u3x_good(u3n_slam_on(u3k(sef), u3k(tub)));
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return vex;
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun p_tub, q_tub;
u3_noun puq_vex, quq_vex, pquq_vex;
u3_noun gud, wag;
u3_noun ret;
u3x_cell(tub, &p_tub, &q_tub);
u3x_cell(uq_vex, &puq_vex, &quq_vex);
u3x_cell(quq_vex, &pquq_vex, 0);
gud = u3nc(
u3nc(u3k(p_tub),
u3k(pquq_vex)),
u3k(puq_vex));
wag = u3x_good(u3n_slam_on(u3k(hez), gud));
ret = u3nq(u3k(p_vex),
u3_nul,
wag,
u3k(quq_vex));
u3z(vex);
return ret;
}
}
u3_noun
u3we_here_fun(
u3_noun cor)
{
u3_noun van, hez, sef, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(c3n == u3r_mean(van, u3x_sam_2, &hez, u3x_sam_3, &sef, 0)) )
{
return u3m_bail(c3__fail);
}
else {
return _cqe_here_fun(hez, sef, tub);
}
}
/* just
*/
u3_noun
_cqe_just_fun(
u3_noun daf,
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
if ( c3n == u3du(q_tub) ) {
return _fail(tub);
}
else {
u3_noun iq_tub = u3h(q_tub);
if ( c3y == u3r_sing(daf, iq_tub) ) {
return _next(tub);
}
else return _fail(tub);
}
}
u3_noun
u3we_just_fun(
u3_noun cor)
{
u3_noun van, daf, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(u3_none == (daf = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_just_fun(daf, tub);
}
}
/* mask
*/
u3_noun
_cqe_mask_fun(
u3_noun bud,
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
if ( c3n == u3du(q_tub) ) {
return _fail(tub);
}
else {
u3_noun iq_tub = u3h(q_tub);
while ( c3y == u3du(bud) ) {
if ( c3y == u3r_sing(u3h(bud), iq_tub) ) {
return _next(tub);
}
bud = u3t(bud);
}
return _fail(tub);
}
}
u3_noun
u3we_mask_fun(
u3_noun cor)
{
u3_noun van, bud, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(u3_none == (bud = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_mask_fun(bud, tub);
}
}
/* pfix
*/
u3_noun
_cqe_pfix(
u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, p_yit, q_yit;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
ret = u3nc
(
_last(p_vex, p_yit),
u3k(q_yit));
u3z(yit);
return ret;
}
}
u3_noun
u3we_pfix(
u3_noun cor)
{
u3_noun vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex, u3x_sam_3, &sab, 0)) ) {
return u3m_bail(c3__exit);
} else {
return _cqe_pfix(vex, sab);
}
}
/* plug
*/
u3_noun
_cqe_plug(
u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, yur;
u3_noun p_yit, q_yit;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
yur = _last(p_vex, p_yit);
if ( c3n == u3du(q_yit) ) {
ret = u3nc(yur, u3k(q_yit));
}
else {
u3_noun uq_yit = u3t(q_yit);
u3_noun puq_yit, quq_yit;
u3x_cell(uq_yit, &puq_yit, &quq_yit);
ret = u3nq(yur,
u3_nul,
u3nc(u3k(puq_vex),
u3k(puq_yit)),
u3k(quq_yit));
}
u3z(yit);
return ret;
}
}
u3_noun
u3we_plug(
u3_noun cor)
{
u3_noun vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex, u3x_sam_3, &sab, 0)) ) {
return u3m_bail(c3__exit);
} else {
return _cqe_plug(vex, sab);
}
}
/* pose
*/
u3_noun
u3qe_pose(u3_noun vex,
u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3y == u3du(q_vex) ) {
return u3k(vex);
} else {
u3_noun roq = u3x_good(u3n_kick_on(u3k(sab)));
u3_noun p_roq, q_roq;
u3_noun ret;
u3x_cell(roq, &p_roq, &q_roq);
ret = u3nc
(
_last(p_vex, p_roq),
u3k(q_roq));
u3z(roq);
return ret;
}
}
u3_noun
u3we_pose(
u3_noun cor)
{
u3_noun vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex, u3x_sam_3, &sab, 0)) ) {
return u3m_bail(c3__exit);
} else {
return u3qe_pose(vex, sab);
}
}
/* sfix
*/
u3_noun
_cqe_sfix(u3_noun vex, u3_noun sab)
{
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return u3k(vex);
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun yit, p_yit, q_yit, yur;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
yit = u3x_good(u3n_slam_on(u3k(sab), u3k(quq_vex)));
u3x_cell(yit, &p_yit, &q_yit);
yur = _last(p_vex, p_yit);
if ( c3n == u3du(q_yit) ) {
ret = u3nc(yur, u3_nul);
}
else {
u3_noun uq_yit = u3t(q_yit);
u3_noun puq_yit, quq_yit;
u3x_cell(uq_yit, &puq_yit, &quq_yit);
ret = u3nq(yur,
u3_nul,
u3k(puq_vex),
u3k(quq_yit));
}
u3z(yit);
return ret;
}
}
u3_noun
u3we_sfix(u3_noun cor)
{
u3_noun vex, sab;
if ( (c3n == u3r_mean(cor, u3x_sam_2, &vex, u3x_sam_3, &sab, 0)) ) {
return u3m_bail(c3__exit);
} else {
return _cqe_sfix(vex, sab);
}
}
/* shim
*/
u3_noun
_cqe_shim_fun(u3_noun zep,
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
if ( c3n == u3du(q_tub) ) {
return _fail(tub);
}
else {
u3_noun p_zep, q_zep;
u3_noun iq_tub = u3h(q_tub);
u3x_cell(zep, &p_zep, &q_zep);
if ( _(u3a_is_cat(p_zep)) &&
_(u3a_is_cat(q_zep)) &&
_(u3a_is_cat(iq_tub)) )
{
if ( (iq_tub >= p_zep) && (iq_tub <= q_zep) ) {
return _next(tub);
}
else return _fail(tub);
}
else {
return u3m_bail(c3__fail);
}
}
}
u3_noun
u3we_shim_fun(
u3_noun cor)
{
u3_noun van, zep, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(u3_none == (zep = u3r_at(u3x_sam, van))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_shim_fun(zep, tub);
}
}
/* stag
*/
u3_noun
_cqe_stag_fun(
u3_noun gob,
u3_noun sef,
u3_noun tub)
{
u3_noun vex = u3x_good(u3n_slam_on(u3k(sef), u3k(tub)));
u3_noun p_vex, q_vex;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
return vex;
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun wag;
u3_noun ret;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
wag = u3nc(u3k(gob), u3k(puq_vex));
ret = u3nq(u3k(p_vex),
u3_nul,
wag,
u3k(quq_vex));
u3z(vex);
return ret;
}
}
u3_noun
u3we_stag_fun(
u3_noun cor)
{
u3_noun van, gob, sef, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(c3n == u3r_mean(van, u3x_sam_2, &gob, u3x_sam_3, &sef, 0)) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_stag_fun(gob, sef, tub);
}
}
/* stew
*/
static u3_noun
_stew_wor(
u3_noun ort,
u3_noun wan)
{
if ( !_(u3a_is_cat(ort)) ) {
return u3m_bail(c3__fail);
}
else {
if ( c3n == u3du(wan) ) {
if ( !_(u3a_is_cat(wan)) ) {
return u3m_bail(c3__fail);
}
else return (ort < wan) ? c3y : c3n;
}
else {
u3_noun h_wan = u3h(wan);
if ( !_(u3a_is_cat(h_wan)) ) {
return u3m_bail(c3__fail);
}
else return (ort < h_wan) ? c3y : c3n;
}
}
}
u3_noun
_cqe_stew_fun(
u3_noun hel,
u3_noun tub)
{
u3_noun p_tub, q_tub;
u3x_cell(tub, &p_tub, &q_tub);
if ( c3n == u3du(q_tub) ) {
return _fail(tub);
}
else {
u3_noun iq_tub = u3h(q_tub);
if ( !_(u3a_is_cat(iq_tub)) ) {
return u3m_bail(c3__fail);
}
else while ( 1 ) {
if ( c3n == u3du(hel) ) {
return _fail(tub);
}
else {
u3_noun n_hel, l_hel, r_hel;
u3_noun pn_hel, qn_hel;
c3_o bit_o;
u3x_trel(hel, &n_hel, &l_hel, &r_hel);
u3x_cell(n_hel, &pn_hel, &qn_hel);
if ( (c3n == u3du(pn_hel)) ) {
bit_o = __((iq_tub == pn_hel));
}
else {
u3_noun hpn_hel = u3h(pn_hel);
u3_noun tpn_hel = u3t(pn_hel);
if ( !_(u3a_is_cat(hpn_hel)) ||
!_(u3a_is_cat(tpn_hel)) ) {
return _fail(tub);
}
else bit_o = __((iq_tub >= hpn_hel) && (iq_tub <= tpn_hel));
}
if ( c3y == bit_o ) {
return u3x_good
(u3n_slam_on(u3k(qn_hel), u3k(tub)));
} else {
if ( c3y == _stew_wor(iq_tub, pn_hel) ) {
hel = l_hel;
}
else hel = r_hel;
}
}
}
}
}
u3_noun
u3we_stew_fun(
u3_noun cor)
{
u3_noun con, hel, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &con, 0)) ||
(u3_none == (hel = u3r_at(2, con))) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_stew_fun(hel, tub);
}
}
/* stir
*/
u3_noun
_cqe_stir_fun(u3_noun rud,
u3_noun raq,
u3_noun fel,
u3_noun tub)
{
u3_noun vex = u3x_good(u3n_slam_on(u3k(fel), u3k(tub)));
u3_noun p_vex, q_vex;
u3_noun ret;
u3x_cell(vex, &p_vex, &q_vex);
if ( c3n == u3du(q_vex) ) {
ret = u3nq(u3k(p_vex),
u3_nul,
u3k(rud),
u3k(tub));
}
else {
u3_noun uq_vex = u3t(q_vex);
u3_noun puq_vex, quq_vex;
u3_noun wag, p_wag, q_wag, uq_wag, puq_wag, quq_wag;
u3x_cell(uq_vex, &puq_vex, &quq_vex);
wag = _cqe_stir_fun(rud, raq, fel, quq_vex);
u3x_cell(wag, &p_wag, &q_wag);
if ( c3n == u3du(q_wag) ) {
return u3m_bail(c3__fail);
}
uq_wag = u3t(q_wag);
u3x_cell(uq_wag, &puq_wag, &quq_wag);
ret = u3nq
(_last(p_vex, p_wag),
u3_nul,
u3x_good(u3n_slam_on
(u3k(raq),
u3nc(u3k(puq_vex),
u3k(puq_wag)))),
u3k(quq_wag));
u3z(wag);
}
u3z(vex);
return ret;
}
u3_noun
u3we_stir_fun(u3_noun cor)
{
u3_noun van, rud, raq, fel, tub;
if ( (c3n == u3r_mean(cor, u3x_sam, &tub, u3x_con, &van, 0)) ||
(c3n == u3r_mean(van, u3x_sam_2, &rud,
u3x_sam_6, &raq,
u3x_sam_7, &fel,
0)) )
{
return u3m_bail(c3__fail);
} else {
return _cqe_stir_fun(rud, raq, fel, tub);
}
}
| [
"bellod.cisneros@gmail.com"
] | bellod.cisneros@gmail.com |
5e32e10be32899a6e0767aedb6ae270c348fecb1 | 388fcc80ed458742d476ad7ddc442b0f8f4df7a7 | /entropy.h | 619fd4aacc5d9ed4058376f22162238ba5ecdae3 | [] | no_license | akallin/1D_NLC_Dupliforked | 359dcc9d58392fe4d3c8de06bbe8a69a22974eb8 | 577544f82aa1916e2add2b945a23180158d3e1ce | refs/heads/master | 2021-01-23T06:35:33.881875 | 2012-08-27T00:28:59 | 2012-08-27T00:28:59 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 14,016 | h | //function to calculate the RDM and entropies for a 1d
#ifndef entropy_H
#define entropy_H
long double getEE( double alpha, vector< vector<long double> > SuperMat );
inline double TwoSiteEntropy(double h, double alpha)
{
double CommonEnt;
double DiffEnt;
double unLog;
CommonEnt = 0.5 + (1. + sqrt(1. + 4.*h*h))/(8.*h*h);
DiffEnt = h*sqrt(1.+2.*h*h+sqrt(1.+4.*h*h))/2./sqrt(2.0);
unLog = pow(CommonEnt + DiffEnt,alpha) + pow(abs(CommonEnt - DiffEnt),alpha);
// cout << CommonEnt << " " << DiffEnt << endl;
if(alpha==1.0){
// cout << CommonEnt - DiffEnt << endl;
return -(CommonEnt + DiffEnt)*log(CommonEnt + DiffEnt)
- abs(CommonEnt - DiffEnt)*log(abs(CommonEnt - DiffEnt));
}
else{
return (1./(1.-alpha))*log(unLog);
}
}
inline void Entropy1D(double alpha, Array<l_double,1>& eigs, Array<long double,1>& ents, double& mag)
{
// The dimension is number of eigenvalues
long int Dim = eigs.size();
// Get number of sites from the dimension
int Nsite = log2(Dim); //cout << "Nsite = " << Nsite << endl;
// The starting dimensions of region A and region B
int Adim=1;
int Bdim=Dim;
// A rectangular matrix containing the eigenvalues, used to get the RDM
Array<long double,2> SuperMat;
// The RDM (SuperMat squared) and RDM squared
Array<double,2> DM(Adim,Adim);
Array<double,2> DMsq(Adim,Adim);
// Some temp variables
long double temp2(0), temp3(0), temp4(0), temp5(0), temp6(0);
int a(0),b(0);
// Eigenvalues of the RDM get put in dd
vector<double> dd;
long double vN;
//Hardcoded to contain only 2 ents (though I may only do *one*!)
ents.resize(2,0);
ents = 0;
// Initializing some things
long double magnetization(0);
long double renyi(0);
l_double norm(0);
// measure the magnetization
for(int i=0; i<Dim; i++){
for (int sp=0; sp<Nsite; sp++){
temp3 += (i>>sp)&1;
}
magnetization += abs(temp3*2-Nsite)*eigs(i)*eigs(i);
norm += eigs(i)*eigs(i);
temp3=0;
}
// mag was passed by ref to the function, so this is what it returns
mag = magnetization;
magnetization = 0;
// Measure Renyi up to half the graph size
for(int Asite=1; Asite<(Nsite+2)/2; Asite++){
// Dimension of region A doubles (from last one) and B gets cut in half
Adim*=2;
Bdim/=2;
// sqrt of RDM gets the properdimensions and initialized
SuperMat.resize(Adim,Bdim);
SuperMat=0;
//More initialization
a=0;b=0;
temp3=0;
norm=0;
magnetization=0;
for(int i=0; i<Dim; i++){
// extractifying the region A and region B states
//b = (((a>>11)&31)<<2)+(((a>>7)&1)<<1)+((a>>3)&1);
//c = (((a>>8)&7)<<6)+(((a>>4)&7)<<3)+(a&7);
a = i&(Adim-1);
b = (i>>Asite)&(Bdim-1);
SuperMat(a,b) = eigs(i);
}
norm = 0;
DM.resize(Adim,Adim);
DM=0;
temp2=0;
//multiplying the supermat by its transpose to get the RDM
DM=0;
for(int i=0; i<Adim; i++){
for(int j=0; j<Adim; j++){
temp2=0;
for(int k=0; k<Bdim; k++){
temp2 += SuperMat(i,k)*SuperMat(j,k);
}
DM(i,j) = temp2;
}
}
//Diagonalizing the RDM
while(dd.size()>0){dd.erase(dd.begin());}
diagWithLapack_R(DM,dd);
renyi=0; vN=0; temp5=0;
for(int s=0;s<dd.size();s++){
if(dd[s]<0){dd[s]=0;}
temp5=log(dd[s]);
if(!(temp5>-1000000000)){temp5=0;}
vN+=-dd[s]*temp5;
if(abs(dd[s])<1e-15){dd[s]=0;}
renyi+=pow(dd[s],alpha);
}
if(alpha==1.0){temp6 = vN;}
else{temp6 = 1./(1.-alpha)*log(renyi);}
ents(1)+=temp6;
if(Asite<(Nsite+1)/2){ ents(1)+=temp6;}
//if(Asite<(Nsite+1)/2){ ents(0)+=vN; ents(1)+=-log(renyi);}// ents(1)+=renyi; }
//else{cout << "Asite:"<<Asite<<" Nsite:"<<Nsite<<endl;}
// cout <<" "<< setprecision(15) << -log(renyi) <<" "<< setprecision(15) << vN;
/*------Commenting out the other S_2 calculation because it's unnecessary---------
DM.resize(Adim,Adim);
DM=0;
temp2=0;
//multiplying the supermat by its transpose to get the RDM
DM=0;
for(int i=0; i<Adim; i++){
for(int j=0; j<Adim; j++){
temp2=0;
for(int k=0; k<Bdim; k++){
temp2 += SuperMat(i,k)*SuperMat(j,k);
}
DM(i,j) = temp2;
}
}
//Square the DM
DMsq.resize(Adim,Adim);
DMsq=0;
for(int i=0; i<Adim; i++){
for(int j=0; j<Adim; j++){
temp2=0;
for(int k=0; k<Adim; k++){
temp2 += DM(i,k)*DM(j,k);
}
DMsq(i,j) = temp2;
}
}
//cout << DMsq << endl;
renyi=0;
norm=0;
for(int s=0;s<Adim;s++){
norm += DM(s,s);
// cout << "Norm: " << norm << " ";
renyi += DMsq(s,s);
// cout << "Renyi: "<< renyi << endl;
}
---------------------------------------------------------------------*/
// cout << "Norm" << " " << setprecision(15) << norm << endl;
//cout << "Asites = " << Asite << " Renyi" << " " <<
// cout <<" "<< setprecision(15) << -log(renyi/norm) << endl;
// cout << endl;
}
//cout << endl;
}
inline void Entropy2D(double alpha, Array<l_double,1>& eigs, Array<long double,1>& ents, double& mag, vector< vector< int > >& RScoords)
{
// Get the graph dimensions from the realspace coordinates
int xMax = RScoords.size();
int yMax = RScoords[0].size();
// The dimension is number of eigenvalues
long int Dim = eigs.size();
// Get number of sites from the dimension
int Nsite = log2(Dim);
// -8-8-8-8- Measure the Magnetization!!! -8-8-8-8-
long double magnetization(0);
int itemp(0);
for(int i=0; i<Dim; i++){
for (int sp=0; sp<Nsite; sp++){
itemp += (i>>sp)&1;
}
magnetization += abs(itemp*2-Nsite)*eigs(i)*eigs(i);
itemp=0;
}
// mag was passed by ref to the function, so this is what it returns
mag = magnetization;
// -8-8-8-8- End of Magnetization -8-8-8-8-
// The dimensions of region A
int xSize(0), ySize(0), Adim(0), Bdim(0);
// A rectangular matrix containing the eigenvalues, used to get the RDM
vector< vector< long double > > SuperMat;
// Some temp variables;
int tempState(-1); // The current full basis state we're looking at
int tempSpin(-1); // The number of the spin that's currently being extracted
int spinState(-1); // The state of that spin
int aState(0), bState(0); // The basis states for reg A and B extracted from the full basis
long double tempEnt;
// make the entropy vector a nonzero size
ents.resize(2,0);
ents(0) = 0;
ents(1) = 0;
// ------ Line Terms!! ------
// -*-*-*- Horizontal -*-*-*-
xSize = xMax;
// Iterate over the horizontal cuts
for(int ySize=1; ySize<=yMax/2; ySize++){
// Get the dimensions of region A and B;
Adim = 1<<xSize*ySize;
Bdim = Dim/Adim;
// Initialize the matrix of eigenvalues
SuperMat.resize(Adim);
for(int q=0; q<Adim; q++){ SuperMat[q].resize(Bdim); }
// Loop over all the basis states
for(int i=0; i<Dim; i++){
// extractifying the region A and region B states
tempState = i;
// Loop over region A
aState=0; // Initialize the state in region A
for(int y=0; y<ySize; y++){
for(int x=0; x<xMax; x++){
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region A
aState += spinState;
// Shift the bits by 1 (for the next site)
aState = aState<<1;
}
}
// Unshift aState by 1 (because there was one extra)
aState = aState>>1;
// Loop over region B (note y starts at ySize)
bState=0; // Initialize the state in region B
for(int y=ySize; y<yMax; y++){
for(int x=0; x<xMax; x++){
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region B
bState += spinState;
// Shift the bits by 1 (for the next site)
bState = bState<<1;
}
}
// Unshift bState by 1 (because there was one extra)
bState = bState>>1;
SuperMat[aState][bState] = eigs(i);
}
// ------ GET ENTROPY!!! ------
tempEnt = (xMax-1)*getEE(alpha,SuperMat);
ents(0) += -tempEnt;
ents(1) += tempEnt;
if(ySize<(yMax+1)/2){ ents(0)+= -tempEnt; ents(1) += tempEnt;}
//cout << "Adim " << Adim << " Bdim " << Bdim << " Hent=" << getEE(alpha,SuperMat) <<endl;
// In the future we can just multiply all renyis by 2 except the middle one for an even system.
}
// -*-*-*- Vertical -*-*-*-
ySize = yMax;
// Iterate over the vectical cuts
for(int xSize=1; xSize<=xMax/2; xSize++){
// Get the dimensions of region A and B;
Adim = 1<<xSize*ySize;
Bdim = Dim/Adim;
// Initialize the matrix of eigenvalues
SuperMat.resize(Adim);
for(int q=0; q<Adim; q++){ SuperMat[q].resize(Bdim); }
// Loop over all the basis states
for(int i=0; i<Dim; i++){
// extractifying the region A and region B states
tempState = i;
// Loop over region A
aState=0; // Initialize the state in region A
for(int y=0; y<yMax; y++){
for(int x=0; x<xSize; x++){
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region A
aState += spinState;
// Shift the bits by 1 (for the next site)
aState = aState<<1;
}
}
// Unshift aState by 1 (because there was one extra)
aState = aState>>1;
// Loop over region B (note y starts at ySize)
bState=0; // Initialize the state in region B
for(int y=0; y<yMax; y++){
for(int x=xSize; x<xMax; x++){
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region B
bState += spinState;
// Shift the bits by 1 (for the next site)
bState = bState<<1;
}
}
// Unshift bState by 1 (because there was one extra)
bState = bState>>1;
SuperMat[aState][bState] = eigs(i);
}
// ------ GET ENTROPY!!! ------
tempEnt = -(yMax-1)*getEE(alpha,SuperMat);
ents(0) += tempEnt;
if(xSize<(xMax+1)/2){ ents(0)+=tempEnt; }
}
// -*-*-*-*-*- Corner Terms!! -*-*-*-*-*-
// Iterate over the corner cuts
for(int ySize=1; ySize<yMax; ySize++){
for(int xSize=1; xSize<xMax; xSize++){
// Get the dimensions of region A and B;
Adim = 1<<xSize*ySize;
Bdim = Dim/Adim;
// Initialize the matrix of eigenvalues
SuperMat.resize(Adim);
for(int q=0; q<Adim; q++){ SuperMat[q].resize(Bdim); }
// Loop over all the basis states
for(int i=0; i<Dim; i++){
// extractifying the region A and region B states
tempState = i;
// Loop over region A
aState=0; // Initialize the state in region A
for(int y=0; y<ySize; y++){
for(int x=0; x<xSize; x++){
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region A
aState += spinState;
// Shift the bits by 1 (for the next site)
aState = aState<<1;
}
}
// Unshift aState by 1 (because there was one extra)
aState = aState>>1;
// Loop over region B (loop over whole state, but do nothing when in region A)
bState=0; // Initialize the state in region B
for(int y=0; y<yMax; y++){
for(int x=0; x<xMax; x++){
if(y<ySize && x<xSize){ continue; }
// Figure out the spin number given the x,y coords
tempSpin = RScoords[x][y];
// Extract the state of tempSpin
spinState = ((tempState&(1<<tempSpin))>>tempSpin);
// Add the spin state to region B
bState += spinState;
// Shift the bits by 1 (for the next site)
bState = bState<<1;
}
}
// Unshift bState by 1 (because there was one extra)
bState = bState>>1;
SuperMat[aState][bState] = eigs(i);
}
// ------ GET ENTROPY!!! ------
ents(0) += 2*getEE(alpha, SuperMat);
}
}
}
long double getEE( double alpha, vector< vector<long double> > SuperMat ){
// The Density Matrix
Array <double,2> DM;
long double temp(0);
int Dim(0);
// Using SuperMat to get the density matrix
// If Adim > Bdim TRANSPOSE!!
if(SuperMat.size()>SuperMat[0].size()){
Dim = SuperMat[0].size();
DM.resize(Dim,Dim);
for(int i=0; i<Dim; i++){
for(int j=0; j<Dim; j++){
temp=0;
for(int k=0; k<SuperMat.size(); k++){
temp += SuperMat[k][i]*SuperMat[k][j];
}
DM(i,j) = temp;
}
}
}
// Otherwise, use Adim
else{
Dim = SuperMat.size();
DM.resize(Dim,Dim);
for(int i=0; i<Dim; i++){
for(int j=0; j<Dim; j++){
temp=0;
for(int k=0; k<SuperMat[0].size(); k++){
temp += SuperMat[i][k]*SuperMat[j][k];
}
DM(i,j) = temp;
}
}
}
// Eigenvalues of the RDM get put in dd
vector<double> dd;
//Diagonalizing the RDM
while(dd.size()>0){dd.erase(dd.begin());}
diagWithLapack_R(DM,dd);
long double EE(0);
long double vN(0), renyi(0);
temp=0;
// Loop over the eigenvalues
for(int s=0; s<dd.size(); s++){
if(dd[s]<0){dd[s]=0;} // All eigs should be positive. If not it's rounding error.
// If dd[s] is a verrrrry small number, it's probably zero.
temp=log(dd[s]);
if(!(temp>-1000000000)){temp=0;}
vN += -dd[s]*temp;
// Same problem. If they're too small they get set to 0.
if(abs(dd[s])<1e-15){dd[s]=0;}
renyi+=pow(dd[s],alpha);
}
if(alpha==1.0){EE = vN;}
else{EE = 1./(1.-alpha)*log(renyi);}
return EE;
}
#endif
| [
"ann.kallin@gmail.com"
] | ann.kallin@gmail.com |
a26ba3b72daf183eb7addf304cae71177d489e9b | 4d69a6218dba8843dc0436d36042ba96d14b3352 | /Light OJ/1000 - Greetings from LightOJ.c | e2338c31987de67e7ff071fad74e721157590663 | [] | no_license | SaimorAlam/Competitive-Programming | f96887231eb645dceec303894a5219419b00764d | 1db383cbcc4e42f4522b4ec622b15f6deb93d124 | refs/heads/master | 2020-04-13T23:24:33.033027 | 2017-08-16T16:54:17 | 2017-08-16T16:54:17 | 51,823,956 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 276 | c | #include<stdio.h>
int main()
{
int a,b,n,i;
while((scanf("%d",&n))==1)
{
for(i=1;i<=n;i++)
{
scanf("%d %d",&a,&b);
if((a<=10)&&(b<=10))
printf("Case %d: %d\n",i,a+b);
}
break;
}
return 0;
}
| [
"saimoralam@gmail.com"
] | saimoralam@gmail.com |
32f9ac09c66b72625716729cdd9a49b242d4ebe4 | 2d618311750fbd45a026ce89d287edcc2ca6f53c | /20170926/quantityBreak.c | 9217fc3488c9be1b86478a46e3489c95b69e95e4 | [] | no_license | Suzyy/C_Practice | 257061e8f48180e274a77fff9a3a06964d46bbdf | b0faa3b63c502cc79f025185f39fda1da9f8932e | refs/heads/master | 2021-09-14T04:01:46.533591 | 2018-05-08T03:55:46 | 2018-05-08T03:55:46 | 116,067,356 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 922 | c | #include <stdio.h>
main(){
int quantity;
float price;
float discountRate;
float discountAmount;
float salesAmount;
printf("Please enter a quantity: ");
scanf("%d", &quantity);
printf("Please enter the price: ");
scanf("%f", &price);
if((quantity >= 1)&&(quantity <= 99)){
discountRate = 0.00;
}
else if((quantity >= 100)&&(quantity <= 499)){
discountRate = 0.05;
}
else if((quantity >= 500)&&(quantity <= 999)){
discountRate = 0.10;
}
else if(quantity >= 1000){
discountRate = 0.15;
}
discountAmount = (quantity*price) * discountRate;
salesAmount = (quantity*price) - discountAmount;
printf("\n\nSales Information\n");
printf("=================\n\n");
printf("Quantity : %d\n",quantity);
printf("Price : $%.2f\n",price);
printf("Discount Rate : %.2f\n",discountRate);
printf("Discount Amount : $%.2f\n",discountAmount);
printf("Sales Amount : $%.2f\n",salesAmount);
return 0;
}
| [
"Suzy@isujiui-MacBook-Pro.local"
] | Suzy@isujiui-MacBook-Pro.local |
1f6ca9d308a1aa2bb4a6be4aa14df4a1a9607136 | e6c65e2e354336a4bea5b6a4ccbccd3682915fe2 | /out-bin/py/google/fhir/models/run_locally.runfiles/com_google_fhir/external/pypi__tensorflow_1_12_0/tensorflow-1.12.0.data/purelib/tensorflow/include/external/jpeg/jconfig.h | 61baae07a09652646be5fcfbea69b1ab778cca4a | [
"Apache-2.0"
] | permissive | rasalt/fhir-datalab | c30ab773d84983dd04a37e9d0ddec8bf2824b8a4 | 3e329fc8b4226d3e3a4a7c23c306a86e7a9ea0de | refs/heads/master | 2021-10-09T05:51:04.593416 | 2018-12-21T18:11:03 | 2018-12-22T05:38:32 | 162,744,237 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 183 | h | /home/rkharwar/.cache/bazel/_bazel_rkharwar/0ddaa3627472ad9d1367a008236ce2f5/external/pypi__tensorflow_1_12_0/tensorflow-1.12.0.data/purelib/tensorflow/include/external/jpeg/jconfig.h | [
"ruchika.kharwar@gmail.com"
] | ruchika.kharwar@gmail.com |
7c260001e7619c7d5a65b1ee8bf67de8b4b4050a | 490d52f91632f073443a93da34cbace8fd9a0808 | /Compiler for OOP decaf (CISC672)/pp5/parser.h | c2f86f65bc3cda781318c9f6ca14cfae3ee0263a | [] | no_license | sychen41/Coursework-Projects | 8a3e15595d315b87595f1c2187bd94fb6b208629 | 9bade7261e0cbceb3f4a41bcfd62eec25b63714e | refs/heads/master | 2021-06-11T11:03:30.140264 | 2016-11-22T20:18:30 | 2016-11-22T20:18:30 | 72,362,903 | 1 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,293 | h | /* File: parser.h
* --------------
* This file provides constants and type definitions that will
* are used and/or exported by the yacc-generated parser.
*/
#ifndef _H_parser
#define _H_parser
// here we need to include things needed for the yylval union
// (types, classes, constants)
#include "scanner.h" // for MaxIdentLen
#include "list.h" // because we use all these types
#include "ast.h" // in the union, we need their declarations
#include "ast_type.h"
#include "ast_decl.h"
#include "ast_expr.h"
#include "ast_stmt.h"
// Next, we want to get the exported defines for the token codes and
// typedef for YYSTYPE and exported global variable yylval. These
// definitions are generated and written to the y.tab.h header file. But
// because that header does not have any protection against being
// re-included and those definitions are also present in the y.tab.c,
// we can get into trouble if we don't take precaution to not include if
// we are compiling y.tab.c, which we use the YYBISON symbol for.
// Managing C headers can be such a mess!
#ifndef YYBISON
#include "y.tab.h"
#endif
int yyparse(); // Defined in the generated y.tab.c file
void InitParser(); // Defined in parser.y
#endif
| [
"sychen@udel.edu"
] | sychen@udel.edu |
2ad1dab2671c5ab440f9cc78e71695268655b683 | 05c9e83414ffd72e9d2ff51a714f0152b8ad5d5d | /src/sys/arch/amd64/compile/MYKERNEL/opt_x86emu.h | 4621793b634a462d5bc879706283fd47db4071b7 | [] | no_license | marwadesouky96/GSoC-NetBSD | 52152a02acfcaa4bf722abf119c66187c7147c2d | 5e3be60a17e3194f11264e0be0474f301d2e8e5f | refs/heads/master | 2020-03-19T11:14:52.539500 | 2018-06-12T01:22:16 | 2018-06-12T01:22:16 | 136,442,332 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 248 | h | #define X86EMU 1
#ifdef _LOCORE
.ifndef _KERNEL_OPT_X86EMU
.global _KERNEL_OPT_X86EMU
.equiv _KERNEL_OPT_X86EMU,0x1
.endif
#else
__asm(" .ifndef _KERNEL_OPT_X86EMU\n .global _KERNEL_OPT_X86EMU\n .equiv _KERNEL_OPT_X86EMU,0x1\n .endif");
#endif
| [
"root@MDesouky.my.domain"
] | root@MDesouky.my.domain |
cbab29d22695a81d434d5741e0089be96736068d | 2fe4e069831dc13785d6d85d48ff5b3e7917e49a | /xdk-asf-3.x/common/services/clock/example1/sam4cp16b_sam4cp16bmb/gcc/asf.h | fe1596de474715ade310474ddf2b18c1d23d4095 | [] | no_license | nandojve/embedded | 2c349bf2dbffa1ef5e0fa80c60b7d9a7c589e554 | da9fb2810a06980821bd4736ae622a80de6025d3 | refs/heads/master | 2021-01-21T12:27:09.764365 | 2015-01-05T23:09:53 | 2015-01-05T23:09:53 | 18,577,491 | 4 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,808 | h | /**
* \file
*
* \brief Autogenerated API include file for the Atmel Software Framework (ASF)
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef ASF_H
#define ASF_H
/*
* This file includes all API header files for the selected drivers from ASF.
* Note: There might be duplicate includes required by more than one driver.
*
* The file is automatically generated and will be re-written when
* running the ASF driver selector tool. Any changes will be discarded.
*/
// From module: Common SAM compiler driver
#include <compiler.h>
#include <status_codes.h>
// From module: Generic board support
#include <board.h>
// From module: IOPORT - General purpose I/O service
#include <ioport.h>
// From module: Interrupt management - SAM implementation
#include <interrupt.h>
// From module: PMC - Power Management Controller
#include <pmc.h>
#include <sleep.h>
// From module: Part identification macros
#include <parts.h>
// From module: SAM4CP16BMB LED support enabled
#include <led.h>
// From module: SUPC - Supply Controller
#include <supc.h>
// From module: System Clock Control - SAM4CP implementation
#include <sysclk.h>
#endif // ASF_H
| [
"nandojve@gmail.com"
] | nandojve@gmail.com |
5fc47c9d9290980934e587720cc971034c9140ea | f0411dca68854abd95705fa73dd34839b3e0dde8 | /Example/Pods/Headers/Private/LJKeyBroadEventManager/LJKeyboardReloadToolBar.h | 0050b9fcfdcece8c072c5d05830806600a925645 | [
"MIT"
] | permissive | lijian096870/LJKeyBroadEventManager | b4868b1ac628cb1720873fe50a8d73b1dd0e245f | b386772178351fb4d893df51d238a5bbba621287 | refs/heads/master | 2020-07-08T05:42:04.570699 | 2020-06-10T07:40:20 | 2020-06-10T07:40:20 | 203,582,066 | 23 | 1 | null | null | null | null | UTF-8 | C | false | false | 80 | h | ../../../../../LJKeyBroadEventManager/Classes/KeyBroad/LJKeyboardReloadToolBar.h | [
"1358756992@qq.com"
] | 1358756992@qq.com |
9bf7c8daba76274879806ec7f51df892924de5ea | 91a882547e393d4c4946a6c2c99186b5f72122dd | /Source/XPSP1/NT/base/pnp/setupapi/devicon.c | f7fa35b67f8848ba8cb517c0752cb3ac869cde48 | [] | no_license | IAmAnubhavSaini/cryptoAlgorithm-nt5src | 94f9b46f101b983954ac6e453d0cf8d02aa76fc7 | d9e1cdeec650b9d6d3ce63f9f0abe50dabfaf9e2 | refs/heads/master | 2023-09-02T10:14:14.795579 | 2021-11-20T13:47:06 | 2021-11-20T13:47:06 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 57,547 | c | /*++
Copyright (c) 1993-2000 Microsoft Corporation
Module Name:
devicon.c
Abstract:
Device Installer routines dealing with retrieval/display of icons.
Author:
Lonny McMichael (lonnym) 28-Aug--1995
Notes:
You must include "basetyps.h" first.
--*/
#include "precomp.h"
#pragma hdrstop
#include <shellapi.h>
MINI_ICON_LIST GlobalMiniIconList;
/*++
Class-to-Icon conversion tables exist in two places. First, there
is the built-in one defined below that is based on a hard-wired
bitmap in the resource. The second is a linked list of CLASSICON
structures that is created every time a new class with an icon
comes along.
Check out resource\ilwinmsd.bmp to see the mini-icons. The icons
are referenced via their (zero-based) index (e.g., computer is 0,
chip is 1, display is 2, etc.). Today, the bitmap indexes look as follows:
0 - computer
1 - chip
2 - display
3 - network
4 - windows
5 - mouse
6 - keyboard
7 - phone
8 - sound
9 - drives
10 - plugs
11 - generic
12 - check
13 - uncheck
14 - printer
15 - nettrans
16 - netclient
17 - netservice
18 - unknown
19 - Fax machine
20 - greyed check
21 - dial up networking
22 - direct cable connection
23 - briefcase (filesync)
24 - Exchange
25 - partial check
26 - Generic folder / Accessories
27 - media (music)
28 - Quick View
29 - old MSN
30 - calculator
31 - FAT32 Converter
32 - Document Templates
33 - disk compression
34 - Games
35 - HyperTerminal
36 - package
37 - mspaint
38 - Screensavers
39 - WordPad
40 - Clipboard Viewer
41 - Accessibility Options
42 - backup
43 - Desktop Wallpaper
44 - Character Map
45 - Mouse Pointers
46 - Net Watcher
47 - phone dialer
48 - resource monitor
49 - Online User's Guide
50 - Multilanguage Support
51 - Audio Compression
52 - CD player
53 - Media Player
54 - WAV sounds
55 - Sample Sounds
56 - Video Compression
57 - Volume Control
58 - Musica sound scheme
59 - Jungle sound scheme
60 - Robotz sound scheme
61 - Utopia sound scheme
62 - Eudcedit
63 - Minesweeper
64 - Pinball
65 - Imaging
66 - Clock
67 - Infrared
68 - MS Wallet
69 - FrontPage Express (aka FrontPad)
70 - MS Agent
71 - Internet Tools
72 - NetShow Player
73 - Net Meeting
74 - DVD Player
75 - Freecell
76 - Athena / Outlook Express / Internet Mail and News
77 - Desktop Themes
78 - Baseball theme
79 - Dangerous Creatures theme
80 - Inside your Computer theme
81 - Jungle theme
82 - Leonardo da Vinci theme
83 - More Windows theme
84 - Mystery theme
85 - Nature theme
86 - Science theme
87 - Space theme
88 - Sports theme
89 - The 60's USA theme
90 - The Golden Era theme
91 - Travel theme
92 - Underwater theme
93 - Windows 95 theme
94 - Personal Web Server
95 - Real Audio
96 - Web Publisher / WebPost
97 - WaveTop
98 - WebTV
--*/
CONST INT UnknownClassMiniIconIndex = 11;
CONST CLASSICON MiniIconXlate[] = { {&GUID_DEVCLASS_COMPUTER, 0, NULL},
{&GUID_DEVCLASS_DISPLAY, 2, NULL},
{&GUID_DEVCLASS_MOUSE, 5, NULL},
{&GUID_DEVCLASS_KEYBOARD, 6, NULL},
{&GUID_DEVCLASS_FDC, 9, NULL},
{&GUID_DEVCLASS_HDC, 9, NULL},
{&GUID_DEVCLASS_PORTS, 10, NULL},
{&GUID_DEVCLASS_NET, 15, NULL},
{&GUID_DEVCLASS_SYSTEM, 0, NULL},
{&GUID_DEVCLASS_SOUND, 8, NULL},
{&GUID_DEVCLASS_PRINTER, 14, NULL},
{&GUID_DEVCLASS_MONITOR, 2, NULL},
{&GUID_DEVCLASS_NETTRANS, 3, NULL},
{&GUID_DEVCLASS_NETCLIENT, 16, NULL},
{&GUID_DEVCLASS_NETSERVICE, 17, NULL},
{&GUID_DEVCLASS_UNKNOWN, 18, NULL},
{&GUID_DEVCLASS_LEGACYDRIVER, 11, NULL},
{&GUID_DEVCLASS_MTD, 9, NULL}
};
#define MINIX 16
#define MINIY 16
#define RGB_WHITE (RGB(255, 255, 255))
#define RGB_BLACK (RGB(0, 0, 0))
#define RGB_TRANSPARENT (RGB(0, 128, 128))
// This should removed when WINVER defined >= 0x0500 for this project.
#ifndef NOMIRRORBITMAP
#ifdef UNICODE
#define NOMIRRORBITMAP (DWORD)0x80000000 /* Do not Mirror the bitmap in this call */
#else
#define NOMIRRORBITMAP (DWORD)0x0
#endif //UNICODE
#endif
//
// Private function prototypes.
//
INT
NewMiniIcon(
IN CONST GUID *ClassGuid,
IN HICON hIcon OPTIONAL
);
INT
WINAPI
SetupDiDrawMiniIcon(
IN HDC hdc,
IN RECT rc,
IN INT MiniIconIndex,
IN DWORD Flags
)
/*++
Routine Description:
This routine draws the specified mini-icon at the requested location.
Arguments:
hdc - Supplies the handle of the device context in which the mini-icon
will be drawn.
rc - Supplies the rectangle in the specified HDC to draw the icon in.
MiniIconIndex - The index of the mini-icon, as retrieved from
SetupDiLoadClassIcon or SetupDiGetClassBitmapIndex. The following are
pre-defined indices that may be used.
0 Computer
2 display
5 mouse
6 keyboard
9 fdc
9 hdc
10 ports
15 net
0 system
8 sound
14 printer
2 monitor
3 nettrans
16 netclient
17 netservice
18 unknown
Flags - Controls the drawing operation. The LOWORD contains the actual flags
defined as follows:
DMI_MASK - Draw the mini-icon's mask into HDC.
DMI_BKCOLOR - Use the system color index specified in the HIWORD of Flags
as the background color. If not specified, COLOR_WINDOW is used.
DMI_USERECT - If set, SetupDiDrawMiniIcon will use the supplied rect,
stretching the icon to fit as appropriate.
Return Value:
This function returns the offset from the left of rc where the string should
start.
Remarks:
By default, the icon will be centered vertically and butted against the left
corner of the specified rectangle.
--*/
{
HBITMAP hbmOld;
DWORD rgbBk, rgbText;
INT ret = 0;
if(!LockMiniIconList(&GlobalMiniIconList)) {
return 0;
}
CreateMiniIcons();
if(GlobalMiniIconList.hbmMiniImage) {
//
// Set the Foreground and background color for the
// conversion of the Mono Mask image
//
if(Flags & DMI_MASK) {
rgbBk = SetBkColor(hdc, RGB_WHITE);
} else {
rgbBk = SetBkColor(hdc,
GetSysColor(((int)(Flags & DMI_BKCOLOR
? HIWORD(Flags)
: COLOR_WINDOW)))
);
}
rgbText = SetTextColor(hdc, RGB_BLACK);
if(Flags & DMI_USERECT) {
//
// Copy the converted mask into the dest. The transparent
// areas will be drawn with the current window color.
//
hbmOld = SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniMask
);
StretchBlt(hdc,
rc.left,
rc.top,
rc.right - rc.left,
rc.bottom - rc.top,
GlobalMiniIconList.hdcMiniMem,
MINIX * MiniIconIndex,
0,
MINIX,
MINIY,
SRCCOPY | NOMIRRORBITMAP);
if(!(Flags & DMI_MASK)) {
//
// OR the image into the dest
//
SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniImage
);
StretchBlt(hdc,
rc.left,
rc.top,
rc.right - rc.left,
rc.bottom - rc.top,
GlobalMiniIconList.hdcMiniMem,
MINIX * MiniIconIndex,
0,
MINIX,
MINIY,
SRCPAINT | NOMIRRORBITMAP);
}
} else {
//
// Copy the converted mask into the dest. The transparent
// areas will be drawn with the current window color.
//
hbmOld = SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniMask
);
BitBlt(hdc,
rc.left,
rc.top + (rc.bottom - rc.top - MINIY)/2,
MINIX,
MINIY,
GlobalMiniIconList.hdcMiniMem,
MINIX * MiniIconIndex,
0,
SRCCOPY | NOMIRRORBITMAP
);
if(!(Flags & DMI_MASK)) {
//
// OR the image into the dest
//
SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniImage
);
BitBlt(hdc,
rc.left,
rc.top + (rc.bottom - rc.top - MINIY)/2,
MINIX,
MINIY,
GlobalMiniIconList.hdcMiniMem,
MINIX * MiniIconIndex,
0,
SRCPAINT | NOMIRRORBITMAP
);
}
}
SetBkColor(hdc, rgbBk);
SetTextColor(hdc, rgbText);
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmOld);
if(Flags & DMI_USERECT) {
ret = rc.right - rc.left + 2; // offset to string from left edge
} else {
ret = MINIX + 2; // offset to string from left edge
}
}
UnlockMiniIconList(&GlobalMiniIconList);
return ret;
}
BOOL
WINAPI
pSetupDiLoadClassIcon(
IN CONST GUID *ClassGuid,
OUT HICON *LargeIcon, OPTIONAL
OUT HICON *SmallIcon, OPTIONAL
OUT LPINT MiniIconIndex OPTIONAL
)
/*++
Routine Description:
This routine loads both the large and mini-icons for the specified class
Arguments:
ClassGuid - Supplies the GUID of the class for which the icon(s) should
be loaded.
LargeIcon - Optionally, supplies a pointer to a variable that will receive
a handle to the loaded large icon for the specified class. If this
parameter is not specified, the large icon will not be loaded.
SmallIcon - Optionally, supplies a pointer to a variable that will receive
a handle to the loaded small icon for the specified class. If this
parameter is not specified, the small icon will not be loaded.
MiniIconIndex - Optionally, supplies a pointer to a variable that will
receive the index of the mini-icon for the specified class. The
mini-icon is stored in the device installer's mini-icon cache.
Return Value:
If the function succeeds, the return value is TRUE.
If the function fails, the return value is FALSE. To get extended error
information, call GetLastError.
Remarks:
The icons of the class are either pre-defined, and loaded from the device
installer's internal cache, or they are loaded directly from the class
installer's executable. This function will query the registry value ICON in
the specified class's section. If this value is specified then it indicates
what mini icon to load. If the icon value is negative the absolute value
represents a predefined icon. See SetupDiDrawMiniIcon for a list of pre-defined
mini icons. If the icon value is positive it represents an icon in the class
installer's executable, and will be extracted (the number one is reserved).
This function also uses the INSTALLER value first and ENUMPROPPAGES value second
to determine what executable to extract the icon(s) from.
--*/
{
HKEY hk = INVALID_HANDLE_VALUE;
DWORD Err;
HICON hRetLargeIcon = NULL;
HICON hRetSmallIcon = NULL;
INT ClassIconIndex;
DWORD RegDataType, StringSize;
PTSTR EndPtr;
BOOL bGetMini = FALSE;
BOOL bDestroyLargeIcon = FALSE, bDestroySmallIcon = FALSE;
TCHAR TempString[MAX_PATH];
TCHAR FullPath[MAX_PATH];
UINT IconsExtracted;
if(!LockMiniIconList(&GlobalMiniIconList)) {
SetLastError(ERROR_CANT_LOAD_CLASS_ICON);
return FALSE;
}
try {
if(MiniIconIndex) {
*MiniIconIndex = -1;
}
if((hk = SetupDiOpenClassRegKey(ClassGuid, KEY_READ)) == INVALID_HANDLE_VALUE) {
goto clean0;
}
StringSize = sizeof(TempString);
Err = RegQueryValueEx(hk,
pszInsIcon,
NULL,
&RegDataType,
(PBYTE)TempString,
&StringSize
);
if((Err == ERROR_SUCCESS) && (RegDataType == REG_SZ) && (StringSize > sizeof(TCHAR))) {
if((ClassIconIndex = _tcstol(TempString, &EndPtr, 10)) == 1) {
//
// Positive values indicate that we should access an icon
// directly using its ID. Since ExtractIconEx uses negative
// values to indicate these IDs, and since the value -1 has
// a special meaning to that API, we must disallow a ClassIconIndex
// of +1.
//
goto clean1;
}
} else {
//
// Icon index not specified, so assume index is 0.
//
ClassIconIndex = 0;
}
if(MiniIconIndex) {
//
// If mini-icon is already around, then we're done with it.
//
if(!SetupDiGetClassBitmapIndex(ClassGuid, MiniIconIndex)) {
//
// mini-icon not around--set flag to show we didn't get it.
//
bGetMini = TRUE;
}
}
if(ClassIconIndex < 0) {
INT ClassIconIndexNeg = -ClassIconIndex;
//
// Icon index is negative. This means that this class is one
// of our special classes with icons in setupapi.dll
//
if(LargeIcon) {
hRetLargeIcon = LoadIcon(MyDllModuleHandle,
MAKEINTRESOURCE(ClassIconIndexNeg)
);
}
if(bGetMini || SmallIcon) {
//
// Retrieve the small icon as well. If the resource doesn't
// have a small icon then the big one will get smushed, but it's
// better than getting the default icon.
//
hRetSmallIcon = LoadImage(MyDllModuleHandle,
MAKEINTRESOURCE(ClassIconIndexNeg),
IMAGE_ICON,
MINIX,
MINIY,
0
);
if(hRetSmallIcon && bGetMini) {
*MiniIconIndex = NewMiniIcon(ClassGuid, hRetSmallIcon);
}
}
} else if(bGetMini || LargeIcon || SmallIcon) {
//
// Look for the binary containing the icon(s) first in the
// "Installer32" entry, and if not found, then in the "EnumPropPages32"
// entry.
//
lstrcpyn(FullPath, SystemDirectory, MAX_PATH);
StringSize = sizeof(TempString);
Err = RegQueryValueEx(hk,
pszInstaller32,
NULL,
&RegDataType,
(PBYTE)TempString,
&StringSize
);
if((Err != ERROR_SUCCESS) || (RegDataType != REG_SZ) ||
(StringSize < sizeof(TCHAR))) {
StringSize = sizeof(TempString);
Err = RegQueryValueEx(hk,
pszEnumPropPages32,
NULL,
&RegDataType,
(PBYTE)TempString,
&StringSize
);
if((Err != ERROR_SUCCESS) || (RegDataType != REG_SZ) ||
(StringSize < sizeof(TCHAR))) {
goto clean1;
}
}
//
// Remove function name, if present, from installer name.
//
for(EndPtr = TempString + ((StringSize / sizeof(TCHAR)) - 1);
EndPtr >= TempString;
EndPtr--) {
if(*EndPtr == TEXT(',')) {
*EndPtr = TEXT('\0');
break;
}
//
// If we hit a double-quote mark, we terminate the search.
//
if(*EndPtr == TEXT('\"')) {
break;
}
}
pSetupConcatenatePaths(FullPath, TempString, MAX_PATH, NULL);
IconsExtracted = ExtractIconEx(FullPath,
-ClassIconIndex,
LargeIcon ? &hRetLargeIcon : NULL,
(bGetMini || SmallIcon) ? &hRetSmallIcon : NULL,
1
);
if((IconsExtracted != (UINT)-1) && (IconsExtracted > 0)) {
if(hRetLargeIcon) {
bDestroyLargeIcon = TRUE;
}
if(hRetSmallIcon) {
*MiniIconIndex = NewMiniIcon(ClassGuid, hRetSmallIcon);
bDestroySmallIcon = TRUE;
}
}
}
clean1:
RegCloseKey(hk);
hk = INVALID_HANDLE_VALUE;
clean0:
//
// Assume success, unless we hit some really big problem below.
//
Err = NO_ERROR;
if(LargeIcon && !hRetLargeIcon) {
//
// We didn't retrieve a large icon, so use a default.
//
if(!(hRetLargeIcon = LoadIcon(MyDllModuleHandle, MAKEINTRESOURCE(ICON_DEFAULT)))) {
Err = GetLastError();
}
}
if (SmallIcon && !hRetSmallIcon) {
//
// We didn't retrieve a small icon, so use a default.
//
if (!(hRetSmallIcon = LoadImage(MyDllModuleHandle,
MAKEINTRESOURCE(ICON_DEFAULT),
IMAGE_ICON,
GetSystemMetrics(SM_CXSMICON),
GetSystemMetrics(SM_CYSMICON),
0
))) {
Err = GetLastError();
}
}
if(Err == NO_ERROR) {
if(LargeIcon) {
*LargeIcon = hRetLargeIcon;
}
if (SmallIcon) {
*SmallIcon = hRetSmallIcon;
}
if(MiniIconIndex && (*MiniIconIndex == -1)) {
SetupDiGetClassBitmapIndex(NULL, MiniIconIndex);
}
}
} except(EXCEPTION_EXECUTE_HANDLER) {
Err = ERROR_INVALID_PARAMETER;
if(hk != INVALID_HANDLE_VALUE) {
RegCloseKey(hk);
}
}
if(Err != NO_ERROR) {
if (bDestroyLargeIcon) {
DestroyIcon(hRetLargeIcon);
}
if (bDestroySmallIcon) {
DestroyIcon(hRetSmallIcon);
}
}
UnlockMiniIconList(&GlobalMiniIconList);
SetLastError(Err);
return (Err == NO_ERROR);
}
BOOL
WINAPI
SetupDiLoadClassIcon(
IN CONST GUID *ClassGuid,
OUT HICON *LargeIcon, OPTIONAL
OUT LPINT MiniIconIndex OPTIONAL
)
/*++
Routine Description:
This routine loads both the large and mini-icons for the specified class
Arguments:
ClassGuid - Supplies the GUID of the class for which the icon(s) should
be loaded.
LargeIcon - Optionally, supplies a pointer to a variable that will receive
a handle to the loaded large icon for the specified class. If this
parameter is not specified, the large icon will not be loaded.
MiniIconIndex - Optionally, supplies a pointer to a variable that will
receive the index of the mini-icon for the specified class. The
mini-icon is stored in the device installer's mini-icon cache.
Return Value:
If the function succeeds, the return value is TRUE.
If the function fails, the return value is FALSE. To get extended error
information, call GetLastError.
Remarks:
The icons of the class are either pre-defined, and loaded from the device
installer's internal cache, or they are loaded directly from the class
installer's executable. This function will query the registry value ICON in
the specified class's section. If this value is specified then it indicates
what mini icon to load. If the icon value is negative the absolute value
represents a predefined icon. See SetupDiDrawMiniIcon for a list of pre-defined
mini icons. If the icon value is positive it represents an icon in the class
installer's executable, and will be extracted (the number one is reserved).
This function also uses the INSTALLER value first and ENUMPROPPAGES value second
to determine what executable to extract the icon(s) from.
--*/
{
return (pSetupDiLoadClassIcon(ClassGuid,
LargeIcon,
NULL,
MiniIconIndex
));
}
BOOL
WINAPI
SetupDiGetClassBitmapIndex(
IN CONST GUID *ClassGuid, OPTIONAL
OUT PINT MiniIconIndex
)
/*++
Routine Description:
This routine retrieves the index of the mini-icon for the specified class.
Arguments:
ClassGuid - Optionally, supplies the GUID of the class to get the mini-icon
index for. If this parameter is not specified, the index of the 'unknown'
icon is returned.
MiniIconIndex - Supplies a pointer to a variable that receives the index of
the mini-icon for the specified class. This buffer is always filled in,
and receives the index of the unknown mini-icon if there is no mini-icon
for the specified class (i.e., the return value is FALSE).
Return Value:
If there was a mini-icon for the specified class, the return value is TRUE.
If there was not a mini-icon for the specified class, or if no class was
specified, the return value is FALSE (and GetLastError returns
ERROR_NO_DEVICE_CLASS_ICON). In this case, MiniIconIndex will contain the
index of the unknown mini-icon.
--*/
{
BOOL bRet = FALSE; // assume not found
int i;
PCLASSICON pci;
DWORD Err;
if(ClassGuid) {
//
// First check the built-in list.
//
for(i = 0; !bRet && (i < ARRAYSIZE(MiniIconXlate)); i++) {
if(IsEqualGUID(MiniIconXlate[i].ClassGuid, ClassGuid)) {
*MiniIconIndex = MiniIconXlate[i].MiniBitmapIndex;
bRet = TRUE;
}
}
//
// Next check the "new stuff" list to see if it's there.
//
if(!bRet && LockMiniIconList(&GlobalMiniIconList)) {
for(pci = GlobalMiniIconList.ClassIconList;
!bRet && pci;
pci = pci->Next) {
if(IsEqualGUID(pci->ClassGuid, ClassGuid)) {
*MiniIconIndex = pci->MiniBitmapIndex;
bRet = TRUE;
}
}
UnlockMiniIconList(&GlobalMiniIconList);
}
}
//
// If no match was found, snag the "unknown" class.
//
if(!bRet) {
*MiniIconIndex = UnknownClassMiniIconIndex;
Err = ERROR_NO_DEVICE_ICON;
} else {
Err = NO_ERROR;
}
SetLastError(Err);
return bRet;
}
BOOL
CreateMiniIcons(
VOID
)
/*++
Routine Description:
This routine loads the default bitmap of mini-icons and turns it into
the image/mask pair that will be the cornerstone of mini-icon management.
THIS FUNCTION ASSUMES THE MINI-ICON LOCK HAS ALREADY BEEN ACQUIRED!
Arguments:
None.
Return Value:
If the function succeeds, the return value is TRUE, otherwise it is FALSE.
--*/
{
HDC hdc, hdcMem;
HBITMAP hbmOld;
BITMAP bm;
BOOL bRet = FALSE; // assume failure
if(GlobalMiniIconList.hdcMiniMem) {
//
// Then the mini-icon list has already been built, so
// return success.
//
return TRUE;
}
hdc = GetDC(NULL);
if (!hdc) {
goto clean0;
}
GlobalMiniIconList.hdcMiniMem = CreateCompatibleDC(hdc);
ReleaseDC(NULL, hdc);
if(!GlobalMiniIconList.hdcMiniMem) {
goto clean0;
}
if(!(hdcMem = CreateCompatibleDC(GlobalMiniIconList.hdcMiniMem))) {
goto clean0;
}
if(!(GlobalMiniIconList.hbmMiniImage = LoadBitmap(MyDllModuleHandle,
MAKEINTRESOURCE(BMP_DRIVERTYPES)))) {
goto clean1;
}
GetObject(GlobalMiniIconList.hbmMiniImage, sizeof(bm), &bm);
if(!(GlobalMiniIconList.hbmMiniMask = CreateBitmap(bm.bmWidth,
bm.bmHeight,
1,
1,
NULL))) {
goto clean1;
}
hbmOld = SelectObject(hdcMem, GlobalMiniIconList.hbmMiniImage);
SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniMask
);
//
// make the mask. white where transparent, black where opaque
//
SetBkColor(hdcMem, RGB_TRANSPARENT);
BitBlt(GlobalMiniIconList.hdcMiniMem,
0,
0,
bm.bmWidth,
bm.bmHeight,
hdcMem,
0,
0,
SRCCOPY
);
//
// black-out all of the transparent parts of the image, in preparation
// for drawing.
//
SetBkColor(hdcMem, RGB_BLACK);
SetTextColor(hdcMem, RGB_WHITE);
BitBlt(hdcMem, 0, 0, bm.bmWidth, bm.bmHeight, GlobalMiniIconList.hdcMiniMem, 0, 0, SRCAND);
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmOld);
GlobalMiniIconList.NumClassImages = bm.bmWidth/MINIX;
bRet = TRUE;
SelectObject(hdcMem, hbmOld);
clean1:
DeleteObject(hdcMem);
clean0:
//
// If failure, clean up anything we might have built
//
if(!bRet) {
DestroyMiniIcons();
}
return bRet;
}
INT
NewMiniIcon(
IN CONST GUID *ClassGuid,
IN HICON hIcon OPTIONAL
)
/*++
Routine Description:
It's a new class, and we have a mini-icon for it, so let's add it
to the mini-icon database. First pull out the image and mask
bitmaps. Then add these to the mini-icon bitmap. If this all
works, add the new class to the list
THIS FUNCTION ASSUMES THE MINI-ICON LOCK HAS ALREADY BEEN ACQUIRED!
Arguments:
ClassGuid - Supplies a pointer to the class GUID for this mini-icon.
hIcon - Optionally, supplies a handle to the mini-icon to be added to
the database. If this parameter is not specified, then the index
for the "unknown class" icon will be returned.
Return Value:
Index for class (set to "unknown class" if error)
--*/
{
INT iBitmap = -1;
ICONINFO ii;
PCLASSICON pci = NULL;
if(hIcon && GetIconInfo(hIcon, &ii)) {
try {
if((iBitmap = pSetupAddMiniIconToList(ii.hbmColor, ii.hbmMask)) != -1) {
//
// Allocate an extra GUID's worth of memory, so we can store
// the class GUID in the same chunk of memory as the CLASSICON
// node.
//
if(pci = (PCLASSICON)MyMalloc(sizeof(CLASSICON) + sizeof(GUID))) {
CopyMemory((PBYTE)pci + sizeof(CLASSICON),
ClassGuid,
sizeof(GUID)
);
pci->ClassGuid = (LPGUID)((PBYTE)pci + sizeof(CLASSICON));
pci->MiniBitmapIndex = iBitmap;
pci->Next = GlobalMiniIconList.ClassIconList;
GlobalMiniIconList.ClassIconList = pci;
}
}
} except(EXCEPTION_EXECUTE_HANDLER) {
if(pci) {
MyFree(pci);
}
iBitmap = -1;
}
DeleteObject(ii.hbmColor);
DeleteObject(ii.hbmMask);
}
if(iBitmap == -1) {
SetupDiGetClassBitmapIndex(NULL, &iBitmap);
}
return iBitmap;
}
INT
pSetupAddMiniIconToList(
IN HBITMAP hbmImage,
IN HBITMAP hbmMask
)
/*++
Routine Description:
Given the image and mask bitmaps of a mini-icon, add these to the
mini-icon bitmap.
THIS FUNCTION ASSUMES THE MINI-ICON LOCK HAS ALREADY BEEN ACQUIRED!
Arguments:
hbmImage - Supplies the handle of the bitmap for the mini-icon.
hbmMask - Supplies the handle of the bitmap for the mini-icon's mask.
Return Value:
If success, returns the index of the added mini-icon.
If failure, returns -1.
--*/
{
HBITMAP hbmNewImage, hbmNewMask, hbmOld;
HDC hdcMem;
BITMAP bm;
INT iIcon = -1; // assume failure
if(!CreateMiniIcons()) {
goto AddIcon_Exit;
}
MYASSERT(GlobalMiniIconList.hdcMiniMem);
if(!(hdcMem = CreateCompatibleDC(GlobalMiniIconList.hdcMiniMem))) {
goto AddIcon_Exit;
}
//
// Create a New global Bitmap for the minis
//
hbmOld = SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniImage
);
if(!(hbmNewImage = CreateCompatibleBitmap(GlobalMiniIconList.hdcMiniMem,
MINIX * (GlobalMiniIconList.NumClassImages + 1),
MINIY))) {
goto AddIcon_Exit1;
}
//
// Copy the current Mini bitmap
//
SelectObject(hdcMem, hbmNewImage);
BitBlt(hdcMem,
0,
0,
MINIX * GlobalMiniIconList.NumClassImages,
MINIY,
GlobalMiniIconList.hdcMiniMem,
0,
0,
SRCCOPY
);
//
// Fit the New icon into ours. We need to stretch it to fit correctly.
//
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmImage);
GetObject(hbmImage, sizeof(bm), &bm);
StretchBlt(hdcMem,
MINIX * GlobalMiniIconList.NumClassImages,
0,
MINIX,
MINIY,
GlobalMiniIconList.hdcMiniMem,
0,
0,
bm.bmWidth,
bm.bmHeight,
SRCCOPY
);
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmOld);
DeleteObject(GlobalMiniIconList.hbmMiniImage);
GlobalMiniIconList.hbmMiniImage = hbmNewImage;
//
// Next, copy the mask.
//
hbmOld = SelectObject(GlobalMiniIconList.hdcMiniMem,
GlobalMiniIconList.hbmMiniMask
);
if(!(hbmNewMask = CreateBitmap(MINIX * (GlobalMiniIconList.NumClassImages + 1),
MINIY,
1,
1,
NULL))) {
goto AddIcon_Exit1;
}
SelectObject(hdcMem, hbmNewMask);
BitBlt(hdcMem,
0,
0,
MINIX * GlobalMiniIconList.NumClassImages,
MINIY,
GlobalMiniIconList.hdcMiniMem,
0,
0,
SRCCOPY
);
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmMask);
GetObject(hbmMask, sizeof(bm), &bm);
StretchBlt(hdcMem,
MINIX * GlobalMiniIconList.NumClassImages,
0,
MINIX,
MINIY,
GlobalMiniIconList.hdcMiniMem,
0,
0,
bm.bmWidth,
bm.bmHeight,
SRCCOPY
);
SelectObject(GlobalMiniIconList.hdcMiniMem, hbmOld);
DeleteObject(GlobalMiniIconList.hbmMiniMask);
GlobalMiniIconList.hbmMiniMask = hbmNewMask;
iIcon = GlobalMiniIconList.NumClassImages;
GlobalMiniIconList.NumClassImages++; // one more image on the table
AddIcon_Exit1:
DeleteDC(hdcMem);
AddIcon_Exit:
return iIcon;
}
VOID
DestroyMiniIcons(
VOID
)
/*++
Routine Description:
This routine destroys the mini-icon bitmaps, if they exist.
THIS FUNCTION ASSUMES THE MINI-ICON LOCK HAS ALREADY BEEN ACQUIRED!
Arguments:
None.
Return Value:
None.
--*/
{
PCLASSICON pci;
if(GlobalMiniIconList.hdcMiniMem) {
DeleteDC(GlobalMiniIconList.hdcMiniMem);
GlobalMiniIconList.hdcMiniMem = NULL;
}
if(GlobalMiniIconList.hbmMiniImage) {
DeleteObject(GlobalMiniIconList.hbmMiniImage);
GlobalMiniIconList.hbmMiniImage = NULL;
}
if(GlobalMiniIconList.hbmMiniMask) {
DeleteObject(GlobalMiniIconList.hbmMiniMask);
GlobalMiniIconList.hbmMiniMask = NULL;
}
GlobalMiniIconList.NumClassImages = 0;
//
// Free up any additional class icon guys that were created
//
while(GlobalMiniIconList.ClassIconList) {
pci = GlobalMiniIconList.ClassIconList;
GlobalMiniIconList.ClassIconList = pci->Next;
MyFree(pci);
}
}
BOOL
WINAPI
SetupDiGetClassImageList(
OUT PSP_CLASSIMAGELIST_DATA ClassImageListData
)
/*++
Routine Description:
See SetupDiGetClassImageListEx for details.
--*/
{
return SetupDiGetClassImageListEx(ClassImageListData, NULL, NULL);
}
#ifdef UNICODE
//
// ANSI version
//
BOOL
WINAPI
SetupDiGetClassImageListExA(
OUT PSP_CLASSIMAGELIST_DATA ClassImageListData,
IN PCSTR MachineName, OPTIONAL
IN PVOID Reserved
)
{
PCWSTR UnicodeMachineName;
DWORD rc;
BOOL b;
b = FALSE;
if(MachineName) {
rc = pSetupCaptureAndConvertAnsiArg(MachineName, &UnicodeMachineName);
} else {
UnicodeMachineName = NULL;
rc = NO_ERROR;
}
if(rc == NO_ERROR) {
b = SetupDiGetClassImageListExW(ClassImageListData, UnicodeMachineName, Reserved);
rc = GetLastError();
if(UnicodeMachineName) {
MyFree(UnicodeMachineName);
}
}
SetLastError(rc);
return b;
}
#else
//
// Unicode version
//
BOOL
WINAPI
SetupDiGetClassImageListExW(
OUT PSP_CLASSIMAGELIST_DATA ClassImageListData,
IN PCWSTR MachineName, OPTIONAL
IN PVOID Reserved
)
{
UNREFERENCED_PARAMETER(ClassImageListData);
UNREFERENCED_PARAMETER(MachineName);
UNREFERENCED_PARAMETER(Reserved);
SetLastError(ERROR_CALL_NOT_IMPLEMENTED);
return(FALSE);
}
#endif
BOOL
WINAPI
SetupDiGetClassImageListEx(
OUT PSP_CLASSIMAGELIST_DATA ClassImageListData,
IN PCTSTR MachineName, OPTIONAL
IN PVOID Reserved
)
/*++
Routine Description:
This routine builds an image list containing bitmaps for every installed class,
and returns a data structure containing the list.
Arguments:
ClassImageListData - Supplies the address of a SP_CLASSIMAGELIST_DATA structure
that will receive information regarding the class list (including a handle
to the image list). The cbSize field of this structure must be initialized
with the size of the structure (in bytes) before calling this routine, or the
API will fail.
MachineName - Optionally, specifies the name of the remote machine whose installed
classes are to be used in building the class image list. If this parameter is
not specified, the local machine is used.
NOTE: Presently, class-specific icons can only be displayed if the class is
also present on the local machine. Thus, if the remote machine has
class x, but class x is not installed locally, then the generic (unknown)
icon will be returned.
Reserved - Reserved for future use--must be NULL.
Return Value:
If the function succeeds, the return value is TRUE.
If the function fails, the return value is FALSE. To get extended error
information, call GetLastError.
Remarks:
The image list contained in structure filled in by this API should NOT be
destroyed by calling ImageList_Destroy. Instead, SetupDiDestroyClassImageList
should be called, for proper clean-up to occur.
--*/
{
DWORD Err = NO_ERROR;
int cxMiniIcon, cyMiniIcon;
int MiniIconIndex = 0, DefaultIndex = 0;
int GuidCount, i;
int iIcon, iIndex;
HDC hDC = NULL, hMemImageDC = NULL;
HBITMAP hbmMiniImage = NULL, hbmMiniMask = NULL, hbmOldImage = NULL;
RECT rc;
CONST GUID *pClassGuid = NULL;
BOOL bUseBitmap, ComputerClassFound = FALSE;
HICON hiLargeIcon = NULL, hiSmallIcon = NULL, hIcon = NULL;
HBRUSH hOldBrush;
PCLASSICON pci = NULL;
PCLASS_IMAGE_LIST ImageData = NULL;
BOOL DestroyLock = FALSE;
HIMAGELIST ImageList = NULL;
DWORD dwLayout = 0;
UINT ImageListFlags = 0;
//
// Make sure the caller didn't pass us anything in the Reserved parameter.
//
if(Reserved) {
SetLastError(ERROR_INVALID_PARAMETER);
return FALSE;
}
try {
if(ClassImageListData->cbSize != sizeof(SP_CLASSIMAGELIST_DATA)) {
Err = ERROR_INVALID_USER_BUFFER;
goto clean0;
}
//
// Allocate and initialize the image list, including setting up the
// synchronization lock. Destroy it when done.
//
if(ImageData = MyMalloc(sizeof(CLASS_IMAGE_LIST))) {
ZeroMemory(ImageData, sizeof(CLASS_IMAGE_LIST));
} else {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
if(InitializeSynchronizedAccess(&ImageData->Lock)) {
DestroyLock = TRUE;
}
//
// Build the class image list. Create an Image List with no mask,
// 1 image, and a growth factor of 1.
//
cxMiniIcon = GetSystemMetrics(SM_CXSMICON);
cyMiniIcon = GetSystemMetrics(SM_CYSMICON);
ImageListFlags = ILC_MASK;
//
// Check which color depth we are running in. Set the ILC_COLOR32
// imagelist create flag if we are running at greate than 8bit (256)
// color depth.
//
hDC = GetDC(NULL);
if (hDC) {
if (GetDeviceCaps(hDC, BITSPIXEL) > 8) {
ImageListFlags |= ILC_COLOR32;
}
ReleaseDC(NULL, hDC);
hDC = NULL;
}
#ifdef UNICODE
//
// If we are running on an RTL build then we need to set the ILC_MIRROR
// flag when calling ImageList_Create to un-mirror the icons. By
// default the icons are mirrored.
//
if (GetProcessDefaultLayout(&dwLayout) &&
(dwLayout & LAYOUT_RTL)) {
ImageListFlags |= ILC_MIRROR;
}
#endif
if(!(ImageList = ImageList_Create(cxMiniIcon,
cyMiniIcon,
ImageListFlags,
1,
1)))
{
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
ImageList_SetBkColor(ImageList, GetSysColor(COLOR_WINDOW));
//
// Create a DC to draw the mini icons into. This is needed
// for the system defined Minis
//
if(!(hDC = GetDC(HWND_DESKTOP)) ||
!(hMemImageDC = CreateCompatibleDC(hDC)))
{
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
//
// Create a bitmap to draw the icons on. Defer checking for creation
// of bitmap until afer freeing DC, so it only has to be done once.
//
hbmMiniImage = CreateCompatibleBitmap(hDC, cxMiniIcon, cyMiniIcon);
hbmMiniMask = CreateCompatibleBitmap(hDC, cxMiniIcon, cyMiniIcon);
ReleaseDC(HWND_DESKTOP, hDC);
hDC = NULL;
//
// Did the bitmap get created?
//
if (!hbmMiniImage || ! hbmMiniMask) {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
//
// Select our bitmap into the memory DC.
//
hbmOldImage = SelectObject(hMemImageDC, hbmMiniImage);
//
// Prepare to draw the mini icon onto the memory DC
//
rc.left = 0;
rc.top = 0;
rc.right = cxMiniIcon;
rc.bottom = cyMiniIcon;
//
// Get the Index of the Default mini icon.
//
SetupDiGetClassBitmapIndex(NULL, &DefaultIndex);
//
// Enumerate all classes, and for each class, draw its bitmap.
//
GuidCount = 32;
ImageData->ClassGuidList = (LPGUID)MyMalloc(sizeof(GUID) * GuidCount);
if (!SetupDiBuildClassInfoListEx(0,
ImageData->ClassGuidList,
GuidCount,
&GuidCount,
MachineName,
NULL)) {
if (GetLastError() == ERROR_INSUFFICIENT_BUFFER) {
//
// Realloc buffer and try again.
//
MyFree(ImageData->ClassGuidList);
if(!(ImageData->ClassGuidList = MyMalloc(sizeof(GUID) * GuidCount))) {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
if (!SetupDiBuildClassInfoListEx(0,
ImageData->ClassGuidList,
GuidCount,
&GuidCount,
MachineName,
NULL)) {
Err = GetLastError();
goto clean0;
}
} else {
Err = GetLastError();
goto clean0;
}
}
//
// Retrieve the icon for each class in the class list.
//
for (pClassGuid = ImageData->ClassGuidList, i = 0;
i < GuidCount;
pClassGuid++, i++) {
if (!pSetupDiLoadClassIcon(pClassGuid,
&hiLargeIcon,
&hiSmallIcon,
&MiniIconIndex)) {
Err = GetLastError();
goto clean0;
}
//
// If the returned Mini Icon index is not the Default one, then
// we use the MiniBitmap, since it is a pre-defined one in SETUPAPI.
// If the Mini is not pre-defined, and there is no Class Installer
// then we use the Mini, since it is a valid default. If there
// is no Mini, and there is a class installer, then we will use
// the Class installer's big Icon, and have the Image list crunch
// it for us.
//
bUseBitmap = FALSE;
if (DefaultIndex != MiniIconIndex) {
SetupDiDrawMiniIcon(hMemImageDC,
rc,
MiniIconIndex,
DMI_USERECT);
SelectObject(hMemImageDC, hbmMiniMask);
SetupDiDrawMiniIcon(hMemImageDC,
rc,
MiniIconIndex,
DMI_MASK | DMI_USERECT);
bUseBitmap = TRUE;
}
//
// Deselect the bitmap from our DC BEFORE calling ImageList
// functions.
//
SelectObject(hMemImageDC, hbmOldImage);
//
// Add the image. Allocate a new PCI.
//
if(!(pci = (PCLASSICON)MyMalloc(sizeof(CLASSICON)))) {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
if (hiSmallIcon) {
pci->MiniBitmapIndex = (UINT)ImageList_AddIcon(ImageList, hiSmallIcon);
} else if (bUseBitmap) {
pci->MiniBitmapIndex = (UINT)ImageList_Add(ImageList, hbmMiniImage, hbmMiniMask);
} else {
pci->MiniBitmapIndex = (UINT)ImageList_AddIcon(ImageList, hiLargeIcon);
}
if (hiLargeIcon) {
DestroyIcon(hiLargeIcon);
hiLargeIcon = NULL;
}
if (hiSmallIcon) {
DestroyIcon(hiSmallIcon);
hiSmallIcon = NULL;
}
if(pci->MiniBitmapIndex == (UINT)-1) {
Err = ERROR_NOT_ENOUGH_MEMORY;
MyFree(pci);
pci = NULL;
goto clean0;
}
pci->ClassGuid = pClassGuid;
//
// Link it in.
//
pci->Next = ImageData->ClassIconList;
ImageData->ClassIconList = pci;
//
// Reset pci to NULL so we won't try to free it later.
//
pci = NULL;
//
// Select our bitmap back for the next ICON.
//
SelectObject(hMemImageDC, hbmMiniImage);
if(IsEqualGUID(pClassGuid, &GUID_DEVCLASS_UNKNOWN)) {
ImageData->UnknownImageIndex = i;
}
//
// Check to see if we've encountered the computer class. This used
// to be a special pseudo-class used solely by DevMgr to retrieve
// the icon for the root of the device tree. Now, we use this class
// for specifying the 'drivers' for the computer itself (i.e., the
// HALs and the appropriate versions of files that are different for
// MP vs. UP.
//
// We should encounter this class GUID, but if we don't, then we
// want to maintain the old behavior of adding this in manually
// later on.
//
if(!ComputerClassFound && IsEqualGUID(pClassGuid, &GUID_DEVCLASS_COMPUTER)) {
ComputerClassFound = TRUE;
}
}
if(!ComputerClassFound) {
//
// Special Case for the Internal Class "Computer"
//
if(!(pci = (PCLASSICON)MyMalloc(sizeof(CLASSICON)))) {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
pci->ClassGuid = &GUID_DEVCLASS_COMPUTER;
SelectObject(hMemImageDC, hbmMiniImage);
hOldBrush = SelectObject(hMemImageDC, GetSysColorBrush(COLOR_WINDOW));
PatBlt(hMemImageDC, 0, 0, cxMiniIcon, cyMiniIcon, PATCOPY);
SelectObject(hMemImageDC, hOldBrush);
SetupDiGetClassBitmapIndex((LPGUID)pci->ClassGuid, &MiniIconIndex);
SetupDiDrawMiniIcon(hMemImageDC,
rc,
MiniIconIndex,
DMI_USERECT);
SelectObject(hMemImageDC, hbmMiniMask);
SetupDiDrawMiniIcon(hMemImageDC,
rc,
MiniIconIndex,
DMI_MASK | DMI_USERECT);
//
// Deselect the bitmap from our DC BEFORE calling ImageList
// functions.
//
SelectObject(hMemImageDC, hbmOldImage);
pci->MiniBitmapIndex = ImageList_Add(ImageList, hbmMiniImage, hbmMiniMask);
if(pci->MiniBitmapIndex == (UINT)-1) {
Err = ERROR_NOT_ENOUGH_MEMORY;
MyFree(pci);
pci = NULL;
goto clean0;
}
//
// Link it in.
//
pci->Next = ImageData->ClassIconList;
ImageData->ClassIconList = pci;
//
// Reset pci to NULL so we won't try to free it later.
//
pci = NULL;
}
//
// Add the Overlay ICONs.
//
for (iIcon = IDI_CLASSICON_OVERLAYFIRST;
iIcon <= IDI_CLASSICON_OVERLAYLAST;
++iIcon) {
if(!(hIcon = LoadIcon(MyDllModuleHandle, MAKEINTRESOURCE(iIcon)))) {
Err = GetLastError();
goto clean0;
}
iIndex = ImageList_AddIcon(ImageList, hIcon);
if(iIndex == -1) {
Err = ERROR_NOT_ENOUGH_MEMORY;
goto clean0;
}
if(!ImageList_SetOverlayImage(ImageList, iIndex, iIcon - IDI_CLASSICON_OVERLAYFIRST + 1)) {
Err = ERROR_INVALID_DATA;
goto clean0;
}
}
//
// If we get to this point, then we've successfully constructed the entire
// image list, and associated CLASSICON nodes. Now, store this information
// in the caller's SP_CLASSIMAGELIST_DATA buffer.
//
ClassImageListData->Reserved = (ULONG_PTR)ImageData;
ClassImageListData->ImageList = ImageList;
clean0: ; // nothing to do.
} except(EXCEPTION_EXECUTE_HANDLER) {
Err = ERROR_INVALID_USER_BUFFER;
if(hDC) {
ReleaseDC(HWND_DESKTOP, hDC);
}
if(pci) {
MyFree(pci);
}
//
// Reference the following variables so the compiler will respect statement
// ordering w.r.t. assignment.
//
ImageData = ImageData;
DestroyLock = DestroyLock;
ImageList = ImageList;
}
if (hbmMiniImage) {
DeleteObject(hbmMiniImage);
}
if (hbmMiniMask) {
DeleteObject(hbmMiniMask);
}
if (hMemImageDC) {
DeleteDC(hMemImageDC);
}
if(Err != NO_ERROR) {
if(ImageData) {
if(DestroyLock) {
DestroySynchronizedAccess(&ImageData->Lock);
}
if(ImageData->ClassGuidList) {
MyFree(ImageData->ClassGuidList);
}
while(ImageData->ClassIconList) {
pci = ImageData->ClassIconList;
ImageData->ClassIconList = pci->Next;
MyFree(pci);
}
MyFree(ImageData);
}
if(ImageList) {
ImageList_Destroy(ImageList);
}
}
SetLastError(Err);
return (Err == NO_ERROR);
}
BOOL
WINAPI
SetupDiDestroyClassImageList(
IN PSP_CLASSIMAGELIST_DATA ClassImageListData
)
/*++
Routine Description:
This routine destroys a class image list built by a call to SetupDiGetClassImageList.
Arguments:
ClassImageListData - Supplies the address of a SP_CLASSIMAGELIST_DATA structure
containing the class image list to be destroyed.
Return Value:
If the function succeeds, the return value is TRUE.
If the function fails, the return value is FALSE. To get extended error
information, call GetLastError.
--*/
{
DWORD Err = NO_ERROR;
PCLASS_IMAGE_LIST ImageData = NULL;
PCLASSICON pci;
try {
if(ClassImageListData->cbSize != sizeof(SP_CLASSIMAGELIST_DATA)) {
Err = ERROR_INVALID_USER_BUFFER;
goto clean0;
}
if (ClassImageListData->Reserved == 0x0) {
Err = ERROR_INVALID_USER_BUFFER;
goto clean0;
}
ImageData = (PCLASS_IMAGE_LIST)ClassImageListData->Reserved;
if (!LockImageList(ImageData)) {
Err = ERROR_CANT_LOAD_CLASS_ICON;
goto clean0;
}
if (ClassImageListData->ImageList) {
ImageList_Destroy(ClassImageListData->ImageList);
}
if (ImageData->ClassGuidList) {
MyFree(ImageData->ClassGuidList);
}
while(ImageData->ClassIconList) {
pci = ImageData->ClassIconList;
ImageData->ClassIconList = pci->Next;
MyFree(pci);
}
DestroySynchronizedAccess(&ImageData->Lock);
MyFree(ImageData);
ClassImageListData->Reserved = 0;
clean0: ; // nothing to do.
} except(EXCEPTION_EXECUTE_HANDLER) {
Err = ERROR_INVALID_USER_BUFFER;
}
SetLastError(Err);
return (Err == NO_ERROR);
}
BOOL
WINAPI
SetupDiGetClassImageIndex(
IN PSP_CLASSIMAGELIST_DATA ClassImageListData,
IN CONST GUID *ClassGuid,
OUT PINT ImageIndex
)
/*++
Routine Description:
This routine retrieves the index within the class image list of a specified
class.
Arguments:
ClassImageListData - Supplies the address of a SP_CLASSIMAGELIST_DATA
structure containing the specified class's image.
ClassGuid - Supplies the address of the GUID for the class whose index is
to be retrieved.
ImageIndex - Supplies the address of a variable that receives the index of
the specified class's image within the class image list.
Return Value:
If the function succeeds, the return value is TRUE.
If the function fails, the return value is FALSE. To get extended error
information, call GetLastError.
--*/
{
DWORD Err = NO_ERROR;
BOOL bFound = FALSE, bLocked = FALSE;
PCLASS_IMAGE_LIST ImageData = NULL;
PCLASSICON pci;
try {
if(ClassImageListData->cbSize != sizeof(SP_CLASSIMAGELIST_DATA)) {
Err = ERROR_INVALID_USER_BUFFER;
goto clean0;
}
if (ClassImageListData->Reserved == 0x0) {
Err = ERROR_INVALID_USER_BUFFER;
goto clean0;
}
ImageData = (PCLASS_IMAGE_LIST)ClassImageListData->Reserved;
if (!LockImageList(ImageData)) {
Err = ERROR_CANT_LOAD_CLASS_ICON;
goto clean0;
}
bLocked = TRUE;
if (ClassGuid) {
//
// check the "new stuff" list to see if it's there
//
for (pci = ImageData->ClassIconList;
!bFound && pci;
pci = pci->Next) {
if(IsEqualGUID(pci->ClassGuid, ClassGuid)) {
*ImageIndex = pci->MiniBitmapIndex;
bFound = TRUE;
}
}
}
//
// if no match was found, snag the "unknown" class
//
if (!bFound) {
*ImageIndex = ImageData->UnknownImageIndex;
}
clean0: ; // nothing to do.
} except(EXCEPTION_EXECUTE_HANDLER) {
Err = ERROR_INVALID_USER_BUFFER;
}
if (bLocked && ImageData) {
UnlockImageList(ImageData);
}
SetLastError(Err);
return (Err == NO_ERROR);
}
| [
"support@cryptoalgo.cf"
] | support@cryptoalgo.cf |
fbe45d6df55bb99cea29fa60b928f53b44d510b8 | 287230b6695941701830dd513273d516c7235ba9 | /prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/lib/gcc/arm-linux-gnueabihf/6.3.1/plugin/include/tree-data-ref.h | d5efcbb537305987e190d1fe8787812e714f70be | [] | no_license | haohlliang/rv1126 | 8279c08ada9e29d8973c4c5532ca4515bd021454 | d8455921b05c19b47a2d7c8b682cd03e61789ee9 | refs/heads/master | 2023-08-10T05:56:01.779701 | 2021-06-27T14:30:42 | 2021-06-27T14:30:42 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 130 | h | version https://git-lfs.github.com/spec/v1
oid sha256:28400ff222a0035ae51d7c0889d18e69d55a3c895c82b03e044201c8295bf511
size 17091
| [
"geierconstantinabc@gmail.com"
] | geierconstantinabc@gmail.com |
27e510a7b3c18aec93f737171bf71ac1ef87bf19 | 86e708d6eea4b2be0a6f54667dcc08dac7ec3a37 | /os/lib/fork.c | ba45119a17f3c8f0dffe2d64b3a4380a5ed4032c | [] | no_license | aaandrewww/authcontrol | 0566acac31043e9c39d10ca3af1ddae0100a4563 | 98dc3249484fdc692bcba8e788f479121f7be808 | refs/heads/master | 2021-01-17T13:00:37.475296 | 2015-08-31T00:46:49 | 2015-08-31T00:46:49 | 41,648,058 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 5,337 | c | // implement fork from user space
#include <inc/string.h>
#include <inc/lib.h>
// PTE_COW marks copy-on-write page table entries.
// It is one of the bits explicitly allocated to user processes (PTE_AVAIL).
#define PTE_COW 0x800
static bool
is_mapped(uintptr_t va, pte_t *pte_store)
{
if ((vpd[PDX(va)] & PTE_P) && (vpt[PGNUM(va)] & PTE_P)) {
if (pte_store) *pte_store = vpt[PGNUM(va)];
return true;
} else {
return false;
}
}
//
// Custom page fault handler - if faulting page is copy-on-write,
// map in our own private writable copy and call resume(utf).
//
static void
pgfault(struct UTrapframe *utf)
{
void *addr = (void *) utf->utf_fault_va;
uint32_t err = utf->utf_err;
int r;
void *faultpage = (void *)ROUNDDOWN((uintptr_t)addr,PGSIZE);
pte_t pte;
// Check that the faulting access was (1) a write, and (2) to a
// copy-on-write page. If not, return 0.
// Hint: Use vpd and vpt.
// cprintf(">> in page fault handler!\n");
// Check fault was a write
if (!(err & 2)) return;
// cprintf(">> was a write!\n");
// Check that the page was COW
if ((r = is_mapped((uintptr_t)faultpage, &pte)) < 0) return;
if (!(pte & PTE_COW)) return;
// cprintf(">> was COW\n");
// Allocate a new page, map it at a temporary location (PFTEMP),
// copy the data from the old page to the new page, then move the new
// page to the old page's address.
// Hint:
// You should make three system calls.
// No need to explicitly delete the old page's mapping.
// LAB 4: Your code here.
if ((r = sys_page_alloc(0, PFTEMP, PTE_U | PTE_W)) < 0) panic("Couldn't allocate PFTEMP");
memcpy(PFTEMP,faultpage,PGSIZE);
if ((r = sys_page_map(0, PFTEMP, 0, faultpage, PTE_U | PTE_W)) < 0) panic("Couldn't remap faulted page");
if ((r = sys_page_unmap(0, PFTEMP)) < 0) panic("Couldn't unmap PFTEMP");
resume(utf);
}
//
// Map our virtual page pn (address pn*PGSIZE) into the target envid
// at the same virtual address. If the page is writable or copy-on-write,
// the new mapping must be created copy-on-write, and then our mapping must be
// marked copy-on-write as well. (Exercise: Why do we need to mark ours
// copy-on-write again if it was already copy-on-write at the beginning of
// this function?)
//
// Returns: 0 on success, < 0 on error.
// It is also OK to panic on error.
//
static int
duppage(envid_t envid, uintptr_t va)
{
int r;
pte_t pte;
pte_t perms;
if (is_mapped(va, &pte)) {
perms = pte & PTE_SYSCALL;
// pa is the physical address corresponding to va
if (pte & PTE_SHARE) {
if ((r = sys_page_map(0, (void *)va, envid, (void *)va, perms)) < 0) return r;
} else if ((pte & PTE_W) || (pte & PTE_COW)) {
// cprintf("[%08x] Duplicating W or COW page %p\n", thisenv->env_id, va);
perms = (perms & ~PTE_W) | PTE_COW;
if ((r = sys_page_map(0, (void *)va, envid, (void *)va, perms)) < 0) return r;
// Change perms to COW
if ((r = sys_page_map(0, (void *)va, 0, UTEMP, perms)) < 0) return r;
if ((r = sys_page_map(0, UTEMP, 0, (void *)va, perms)) < 0) return r;
if ((r = sys_page_unmap(0, UTEMP)) < 0) return r;
} else {
// cprintf("[%08x] Duplicating R page %p\n", thisenv->env_id, va);
if ((r = sys_page_map(0, (void *)va, envid, (void *)va, perms)) < 0) return r;
}
}
return 0;
}
//
// User-level fork with copy-on-write.
// Set up our page fault handler appropriately.
// Create a child.
// Copy our address space and page fault handler setup to the child.
// Then mark the child as runnable and return.
//
// Returns: child's envid to the parent, 0 to the child, < 0 on error.
// It is also OK to panic on error.
//
// Hint:
// Use vpd, vpt, and duppage.
// Remember to fix "thisenv" in the child process.
// Neither user exception stack should ever be marked copy-on-write,
// so you must allocate a new page for the child's user exception stack.
//
envid_t
fork(void)
{
int ret;
envid_t child;
// LAB 4: Your code here.
// 1. Install pgfault() as the page fault handler
add_pgfault_handler(pgfault);
// cprintf("pgfault handler %p\n", pgfault);
// 2. Allocate a child environment with sys_exofork()
if ((child = sys_exofork()) < 0) return child;
// cprintf("child [%08x]\n", child);
if (child == 0) {
// Fix thisenv and return 0
thisenv = &envs[ENVX(sys_getenvid())];
return 0;
}
// cprintf("Set up COW pages\n");
// 3. Set up COW pages
for (uintptr_t page = 0; page < UTOP; page += PGSIZE) {
if (page == UXSTACKTOP-PGSIZE) continue;
if (is_mapped(page,NULL)) {
if ((ret = duppage(child,page)) < 0) {
sys_env_destroy(child);
return ret;
}
}
}
// cprintf("Allocated exception stack at %p\n", UXSTACKTOP-PGSIZE);
// 4. Allocate exception stack
if ((ret = sys_page_alloc(child, (void *)(UXSTACKTOP-PGSIZE), PTE_U | PTE_W)) < 0) {
sys_env_destroy(child);
return ret;
}
// cprintf("Set up the page fault handler\n");
// 5. Set up the page fault handler in the child
if ((ret = sys_env_set_pgfault_upcall(child, (void *)thisenv->env_pgfault_upcall)) < 0) {
sys_env_destroy(child);
return ret;
}
// cprintf("Make the child runnable\n");
// 6. Mark the child runnable
if ((ret = sys_env_set_status(child, ENV_RUNNABLE)) < 0) {
sys_env_destroy(child);
return ret;
}
return child;
}
// Challenge!
int
sfork(void)
{
panic("sfork not implemented");
return -E_INVAL;
}
| [
"scott@thinkmoore.net"
] | scott@thinkmoore.net |
f392ac8e52f8f6f1b0a0a36745a5cac3f3d1a628 | 4a842c188112cf8de253b7163525513bc5f1067c | /reactingLagrangianQGDFoam/createClouds.H | 36296cffede84112693ec8b1f7d874b5c5426b35 | [] | no_license | eacfd/QGDsolver | c10c73dc91af66c94c1f0a6aa6eafa16e5806b48 | db06d5195804da242a2d00b3d0de2011276cac90 | refs/heads/jenkins/digitef-dev-1912 | 2023-03-16T15:08:12.472382 | 2020-05-21T13:18:45 | 2020-05-21T13:18:45 | 137,872,201 | 1 | 1 | null | 2023-03-03T13:43:48 | 2018-06-19T09:48:53 | C++ | UTF-8 | C | false | false | 160 | h | Info<< "\nConstructing reacting cloud" << endl;
basicReactingCloud parcels
(
"reactingCloud",
rho,
U,
g,
slgThermo
);
//
//END-OF-FILE
//
| [
"m.kraposhin@ispras.ru"
] | m.kraposhin@ispras.ru |
9070d4d2ca438ce282cb95cccdcefca3597a1794 | 335a3502b4d64b4d949e42c23e5c28fe51d253c7 | /tiny2313hacks-008-display-spi/main.c | 17c87088f75f070fac912227b6bc408acf200d4b | [] | no_license | st3fan/electronics | e8acbab7f55f2c7ec032f66d7b9ae40e5dd303e0 | 398f3188c420277673cadfa46d600a6beea3ba88 | refs/heads/master | 2020-04-01T16:40:29.052327 | 2011-04-21T04:00:41 | 2011-04-21T04:00:41 | 441,033 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 2,488 | c | // tiny2313-hacks-002-adc/main.c
#include <avr/interrupt.h>
#include <avr/io.h>
#include <util/delay.h>
void usart_setup()
{
UBRRH = 0;
UBRRL = 6;
UCSRA = 0;
UCSRB = (1 << TXEN);
UCSRC = (1 << UCSZ1) | (1 << UCSZ0);
}
void usart_tx(unsigned char c)
{
while ((UCSRA & (1 << UDRE)) == 0x00) {
// Do nothing
}
UDR = c;
}
void usart_tx_string(char* c)
{
while (*c) {
usart_tx(*c++);
}
}
void usart_tx_hex_uint8(uint8_t c)
{
static char digits[16] = { '0','1','2','3','4','5','6','7','8','9','a','b','c','d','e','f' };
usart_tx(digits[(c >> 4) & 0x0f]);
usart_tx(digits[(c >> 0) & 0x0f]);
}
void usart_tx_hex_uint16(uint16_t c)
{
usart_tx_hex_uint8((c >> 8) & 0x00ff);
usart_tx_hex_uint8((c >> 0) & 0x00ff);
}
//
#define SPI_PORT DDRB
#define SPI_CLK_PIN PB7
#define SPI_MISO_PIN PB6
#define SPI_MOSI_PIN PB5
#define DELAY 0
void spi_setup()
{
// Clock and Data Out are configured as output pins
SPI_PORT |= (1 << SPI_CLK_PIN) | (1 << SPI_MOSI_PIN);
}
void spi_write_bits(uint8_t b, uint8_t n)
{
while (n--) {
if (b & (1 << n)) {
PORTB |= (1 << SPI_MOSI_PIN);
} else {
PORTB &= ~(1 << SPI_MOSI_PIN);
}
PORTB |= (1 << SPI_CLK_PIN);
PORTB &= ~(1 << SPI_CLK_PIN);
}
}
uint16_t spi_read_bits(uint8_t n)
{
uint16_t v = 0;
for (int i = (n - 1); i >= 0; i--) {
if (PINB & (1 << SPI_MISO_PIN)) {
v |= (1 << i);
}
PORTB |= (1 << SPI_CLK_PIN);
PORTB &= ~(1 << SPI_CLK_PIN);
}
return v;
}
//
#define DISPLAY_DDR DDRB
#define DISPLAY_OUT PORTB
#define DISPLAY_PIN PB0
inline void display_select()
{
DISPLAY_OUT &= ~(1 << DISPLAY_PIN);
}
inline void display_deselect()
{
DISPLAY_OUT |= (1 << DISPLAY_PIN);
}
void display_setup()
{
DISPLAY_DDR |= (1 << DISPLAY_PIN);
}
void display_write(uint16_t value)
{
display_select();
{
spi_write_bits((uint8_t) (value >> 12) & 0x000f, 8);
spi_write_bits((uint8_t) (value >> 8) & 0x000f, 8);
spi_write_bits((uint8_t) (value >> 4) & 0x000f, 8);
spi_write_bits((uint8_t) (value >> 0) & 0x000f, 8);
}
display_deselect();
}
//
int main(void)
{
usart_setup();
spi_setup();
display_setup();
while (1) {
for (uint16_t i = 0; i <= 0xffff; i++) {
display_write(i);
_delay_ms(500);
}
}
return 0;
}
| [
"stefan@arentz.ca"
] | stefan@arentz.ca |
37fdefe38fec1a1a1cc3199a9b1d36abc1eea196 | db573dfca63e68963de9795a30e77534079385ce | /C-Program-Solve/string-cut.c | 8421572cfb40018fe1af2a5fa520ad80d2506f5c | [] | no_license | nibedika/C-Programming | 72cf4b1e5848f5edfb4f968c7ddfc246987e253a | 208a72d883c3da9adae17ec888f1bad7187fb6cb | refs/heads/master | 2022-12-25T02:23:19.321774 | 2020-09-12T22:23:30 | 2020-09-12T22:23:30 | 295,020,817 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 145 | c | #include<stdio.h>
#include<string.h>
int main()
{
char s1[10]="Nibedika";
char s2[10]=" Dhar";
strcat(s1,s2);
printf("%s",s1);
}
| [
"nibedikadhar1712@gmail.com"
] | nibedikadhar1712@gmail.com |
22d8c27df35e15fd5827d0a9e19caa737dced759 | 97aab27d4410969e589ae408b2724d0faa5039e2 | /CPU/SRCS/kos-1.2.0/kernel/arch/dreamcast/hardware/pvr/pvr_fog_tables.h | 702ee3a2648117851c2bfcf3a2078a85db2e3241 | [] | no_license | FutureWang123/dreamcast-docs | 82e4226cb1915f8772418373d5cb517713f858e2 | 58027aeb669a80aa783a6d2cdcd2d161fd50d359 | refs/heads/master | 2021-10-26T00:04:25.414629 | 2018-08-10T21:20:37 | 2018-08-10T21:20:37 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 7,909 | h | /* Kallistios 1.2.0
pvr_fog_tables.h
(C)2002 Paul Boese
Portions (C)1999-2001, Brian Paul
$Id: pvr_fog_tables.h,v 1.2 2002/02/17 03:43:16 axlen Exp $
*/
#ifndef __PVR_FOG_TABLES_H
#define __PVR_FOG_TABLES_H
/*
This table is used by the pvr_fog.c module to scale values for the PVR's
fog table. It can be used directly with each value multiplied by 255
to make perspectively correct table values for linear fog. The table does
not include the value of 1.0 which represents full visual occlusion.
*/
float inverse_w_depth[] = {
0.94118, 0.88889, 0.84211, 0.80000, 0.76190, 0.72727, 0.69565, 0.66667,
0.64000, 0.61538, 0.59259, 0.57143, 0.55172, 0.53333, 0.51613, 0.50000,
0.47059, 0.44444, 0.42105, 0.40000, 0.38095, 0.36364, 0.34783, 0.33333,
0.32000, 0.30769, 0.29630, 0.28571, 0.27586, 0.26667, 0.25806, 0.25000,
0.23529, 0.22222, 0.21053, 0.20000, 0.19048, 0.18182, 0.17391, 0.16667,
0.16000, 0.15385, 0.14815, 0.14286, 0.13793, 0.13333, 0.12903, 0.12500,
0.11765, 0.11111, 0.10526, 0.10000, 0.09524, 0.09091, 0.08696, 0.08333,
0.08000, 0.07692, 0.07407, 0.07143, 0.06897, 0.06667, 0.06452, 0.06250,
0.05882, 0.05556, 0.05263, 0.05000, 0.04762, 0.04545, 0.04348, 0.04167,
0.04000, 0.03846, 0.03704, 0.03571, 0.03448, 0.03333, 0.03226, 0.03125,
0.02941, 0.02778, 0.02632, 0.02500, 0.02381, 0.02273, 0.02174, 0.02083,
0.02000, 0.01923, 0.01852, 0.01786, 0.01724, 0.01667, 0.01613, 0.01562,
0.01471, 0.01389, 0.01316, 0.01250, 0.01190, 0.01136, 0.01087, 0.01042,
0.01000, 0.00962, 0.00926, 0.00893, 0.00862, 0.00833, 0.00806, 0.00781,
0.00735, 0.00694, 0.00658, 0.00625, 0.00595, 0.00568, 0.00543, 0.00521,
0.00500, 0.00481, 0.00463, 0.00446, 0.00431, 0.00417, 0.00403, 0.00391,
};
/* Code to generate the preceeding inverse_w_depth[] table
#include <stdio.h>
#include <math.h>
int main () {
int i, j;
float t;
printf("float inverse_w_depth[] = {\n\t");
for( i=1; i<=128; i++) {
j = i;
t = (pow(2.0, j>>4) * ((j&0xf)+16)/16.0f)/1.0f;
printf("%01.5f,%s", 1.0f/t, ((i)%8)?" ":"\n\t");
}
printf("\n};\n");
return 0;
}
*/
/*
* This is essentially the same table as above except each value has been
* multiplied by 259.999999. This table is used by the EXP and EXP2
* fog functions in pvr_fog.c. It just saves us one multiplcation per table
* entry.
*/
float inverse_w_depth260[] = {
244.706, 231.111, 218.947, 208.000, 198.095, 189.091, 180.870, 173.333,
166.400, 160.000, 154.074, 148.571, 143.448, 138.667, 134.194, 130.000,
122.353, 115.556, 109.474, 104.000, 99.048, 94.545, 90.435, 86.667,
83.200, 80.000, 77.037, 74.286, 71.724, 69.333, 67.097, 65.000,
61.176, 57.778, 54.737, 52.000, 49.524, 47.273, 45.217, 43.333,
41.600, 40.000, 38.519, 37.143, 35.862, 34.667, 33.548, 32.500,
30.588, 28.889, 27.368, 26.000, 24.762, 23.636, 22.609, 21.667,
20.800, 20.000, 19.259, 18.571, 17.931, 17.333, 16.774, 16.250,
15.294, 14.444, 13.684, 13.000, 12.381, 11.818, 11.304, 10.833,
10.400, 10.000, 9.630, 9.286, 8.966, 8.667, 8.387, 8.125,
7.647, 7.222, 6.842, 6.500, 6.190, 5.909, 5.652, 5.417,
5.200, 5.000, 4.815, 4.643, 4.483, 4.333, 4.194, 4.062,
3.824, 3.611, 3.421, 3.250, 3.095, 2.955, 2.826, 2.708,
2.600, 2.500, 2.407, 2.321, 2.241, 2.167, 2.097, 2.031,
1.912, 1.806, 1.711, 1.625, 1.548, 1.477, 1.413, 1.354,
1.300, 1.250, 1.204, 1.161, 1.121, 1.083, 1.048, 1.016,
};
/* Code to generate the preceeding inverse_w_depth260[] table
#include <stdio.h>
#include <math.h>
int main () {
int i, j;
float t;
printf("float inverse_w_depth260[] = {\n\t");
for( i=1; i<=128; i++) {
j = i;
t = (pow(2.0, j>>4) * ((j&0xf)+16)/16.0f)/259.999999f;
printf("%03.3f,%s", 1.0f/t, ((i)%8)?" ":"\n\t");
}
printf("\n};\n");
return 0;
}
*/
/* lookup table for the fast neg_exp function */
static float exp_table[] = {
1.00000000, 0.96169060, 0.92484879, 0.88941842,
0.85534531, 0.82257754, 0.79106510, 0.76075989,
0.73161560, 0.70358789, 0.67663383, 0.65071243,
0.62578398, 0.60181057, 0.57875562, 0.55658382,
0.53526145, 0.51475590, 0.49503589, 0.47607136,
0.45783335, 0.44029403, 0.42342663, 0.40720543,
0.39160562, 0.37660345, 0.36217600, 0.34830126,
0.33495805, 0.32212600, 0.30978554, 0.29791784,
0.28650481, 0.27552897, 0.26497361, 0.25482264,
0.24506053, 0.23567241, 0.22664395, 0.21796136,
0.20961139, 0.20158130, 0.19385885, 0.18643223,
0.17929012, 0.17242162, 0.16581626, 0.15946393,
0.15335497, 0.14748003, 0.14183016, 0.13639674,
0.13117145, 0.12614636, 0.12131377, 0.11666631,
0.11219689, 0.10789870, 0.10376516, 0.09978998,
0.09596708, 0.09229065, 0.08875505, 0.08535489,
0.08208500, 0.07894037, 0.07591622, 0.07300791,
0.07021102, 0.06752128, 0.06493458, 0.06244697,
0.06005467, 0.05775401, 0.05554149, 0.05341373,
0.05136748, 0.04939962, 0.04750715, 0.04568718,
0.04393693, 0.04225374, 0.04063502, 0.03907832,
0.03758125, 0.03614154, 0.03475698, 0.03342546,
0.03214495, 0.03091349, 0.02972922, 0.02859031,
0.02749503, 0.02644171, 0.02542875, 0.02445459,
0.02351775, 0.02261679, 0.02175036, 0.02091712,
0.02011579, 0.01934517, 0.01860407, 0.01789136,
0.01720595, 0.01654680, 0.01591290, 0.01530329,
0.01471703, 0.01415323, 0.01361103, 0.01308960,
0.01258814, 0.01210590, 0.01164213, 0.01119613,
0.01076721, 0.01035472, 0.00995804, 0.00957655,
0.00920968, 0.00885686, 0.00851756, 0.00819126,
0.00787746, 0.00757568, 0.00728546, 0.00700636,
0.00673795, 0.00647982, 0.00623158, 0.00599285,
0.00576327, 0.00554248, 0.00533015, 0.00512596,
0.00492959, 0.00474074, 0.00455912, 0.00438447,
0.00421650, 0.00405497, 0.00389962, 0.00375023,
0.00360656, 0.00346840, 0.00333553, 0.00320774,
0.00308486, 0.00296668, 0.00285303, 0.00274373,
0.00263862, 0.00253753, 0.00244032, 0.00234684,
0.00225693, 0.00217047, 0.00208732, 0.00200735,
0.00193045, 0.00185650, 0.00178538, 0.00171698,
0.00165120, 0.00158795, 0.00152711, 0.00146861,
0.00141235, 0.00135824, 0.00130621, 0.00125617,
0.00120805, 0.00116177, 0.00111726, 0.00107446,
0.00103330, 0.00099371, 0.00095564, 0.00091903,
0.00088383, 0.00084997, 0.00081741, 0.00078609,
0.00075598, 0.00072702, 0.00069916, 0.00067238,
0.00064662, 0.00062185, 0.00059803, 0.00057512,
0.00055308, 0.00053190, 0.00051152, 0.00049192,
0.00047308, 0.00045495, 0.00043753, 0.00042076,
0.00040465, 0.00038914, 0.00037424, 0.00035990,
0.00034611, 0.00033285, 0.00032010, 0.00030784,
0.00029604, 0.00028470, 0.00027380, 0.00026331,
0.00025322, 0.00024352, 0.00023419, 0.00022522,
0.00021659, 0.00020829, 0.00020031, 0.00019264,
0.00018526, 0.00017816, 0.00017134, 0.00016477,
0.00015846, 0.00015239, 0.00014655, 0.00014094,
0.00013554, 0.00013035, 0.00012535, 0.00012055,
0.00011593, 0.00011149, 0.00010722, 0.00010311,
0.00009916, 0.00009536, 0.00009171, 0.00008820,
0.00008482, 0.00008157, 0.00007844, 0.00007544,
0.00007255, 0.00006977, 0.00006710, 0.00006453,
0.00006205, 0.00005968, 0.00005739, 0.00005519,
0.00005308, 0.00005104, 0.00004909, 0.00004721,
};
/* code to generate the preceeding table
#include <stdio.h>
#include <math.h>
#define FOG_EXP_TABLE_SIZE 256
#define FOG_MAX (10.0)
#define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
int main () {
float value, f = 0.0F;
int i = 0;
printf("static float exp_table[FOG_EXP_TABLE_SIZE] = {\n\t");
for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
value = (float) exp(-f);
printf("%01.8f, %s", value, ((i+1)%4)?" ":"\n\t");
}
printf("\n};\n");
return 0;
}
*/
#endif
| [
"david.koch@9online.fr"
] | david.koch@9online.fr |
5a4facdc1485d9534e9a895ef9ca1e7720365ce9 | d1c4f9487dd0db03b1d118ee22c0bbfcac052547 | /aosp/external/libnfc-nci/halimpl/pn54x/utils/phNxpConfig.h | c6154f90a73e3ecb89be18fb2ff141f11a7e377b | [] | no_license | NXPNFCLinux/nxpnfc_android_kitkat | 441499bbf2d367d581606bd3bd7a5c307b8ef1a0 | a5ff49373e28faef06d70ff5e31a09b126e3a76a | refs/heads/master | 2020-12-26T04:49:10.403201 | 2020-10-14T08:29:15 | 2020-10-14T08:29:15 | 53,134,410 | 4 | 7 | null | null | null | null | UTF-8 | C | false | false | 3,651 | h | /******************************************************************************
*
* Copyright (C) 1999-2012 Broadcom Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
/******************************************************************************
*
* The original Work has been changed by NXP Semiconductors.
*
* Copyright (C) 2013-2014 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
int GetNxpStrValue(const char* name, char* p_value, unsigned long len);
int GetNxpNumValue(const char* name, void* p_value, unsigned long len);
int GetNxpByteArrayValue(const char* name, char* pValue,long bufflen, long *len);
void resetNxpConfig(void);
int isNxpConfigModified();
int updateNxpConfigTimestamp();
#ifdef __cplusplus
};
#endif
#define NAME_NXPLOG_EXTNS_LOGLEVEL "NXPLOG_EXTNS_LOGLEVEL"
#define NAME_NXPLOG_NCIHAL_LOGLEVEL "NXPLOG_NCIHAL_LOGLEVEL"
#define NAME_NXPLOG_NCIX_LOGLEVEL "NXPLOG_NCIX_LOGLEVEL"
#define NAME_NXPLOG_NCIR_LOGLEVEL "NXPLOG_NCIR_LOGLEVEL"
#define NAME_NXPLOG_FWDNLD_LOGLEVEL "NXPLOG_FWDNLD_LOGLEVEL"
#define NAME_NXPLOG_TML_LOGLEVEL "NXPLOG_TML_LOGLEVEL"
#define NAME_MIFARE_READER_ENABLE "MIFARE_READER_ENABLE"
#define NAME_FW_STORAGE "FW_STORAGE"
#define NAME_NXP_SYS_CLK_SRC_SEL "NXP_SYS_CLK_SRC_SEL"
#define NAME_NXP_SYS_CLK_FREQ_SEL "NXP_SYS_CLK_FREQ_SEL"
#define NAME_NXP_SYS_CLOCK_TO_CFG "NXP_SYS_CLOCK_TO_CFG"
#define NAME_NXP_ACT_PROP_EXTN "NXP_ACT_PROP_EXTN"
#define NAME_NXP_RF_CONF_BLK_1 "NXP_RF_CONF_BLK_1"
#define NAME_NXP_RF_CONF_BLK_2 "NXP_RF_CONF_BLK_2"
#define NAME_NXP_RF_CONF_BLK_3 "NXP_RF_CONF_BLK_3"
#define NAME_NXP_RF_CONF_BLK_4 "NXP_RF_CONF_BLK_4"
#define NAME_NXP_RF_CONF_BLK_5 "NXP_RF_CONF_BLK_5"
#define NAME_NXP_RF_CONF_BLK_6 "NXP_RF_CONF_BLK_6"
#define NAME_NXP_CORE_CONF_EXTN "NXP_CORE_CONF_EXTN"
#define NAME_NXP_CORE_CONF "NXP_CORE_CONF"
#define NAME_NXP_CORE_MFCKEY_SETTING "NXP_CORE_MFCKEY_SETTING"
#define NAME_NXP_CORE_STANDBY "NXP_CORE_STANDBY"
#define NAME_NXP_NFC_PROFILE_EXTN "NXP_NFC_PROFILE_EXTN"
#define NAME_NXP_SWP_FULL_PWR_ON "NXP_SWP_FULL_PWR_ON"
#define NAME_NXP_CORE_RF_FIELD "NXP_CORE_RF_FIELD"
#define NAME_NXP_NFC_MERGE_RF_PARAMS "NXP_NFC_MERGE_RF_PARAMS"
/* default configuration */
#define default_storage_location "/data/nfc"
#endif
| [
"jeremy.geslin@nxp.com"
] | jeremy.geslin@nxp.com |
807b71e373db16f33ff8e8e12c59211783de43bc | 6f0b0136f95c42fac9889497e9529fa911efb2b0 | /Software PWM/FR5994_softPWM/msp430fr599x_1.c | 4b069f659fe2726bf35cd4b87bb2d1546fdb4f53 | [] | no_license | RU09342/lab-4-timers-and-pwm-apranvoku | bcc1366264b202feabe37e412d3930a37967a699 | c3210d3318ab4aa879bcb51594bf7bc8c28d8149 | refs/heads/master | 2021-05-16T04:52:21.628795 | 2017-10-16T07:36:19 | 2017-10-16T07:36:19 | 106,218,615 | 0 | 1 | null | null | null | null | UTF-8 | C | false | false | 2,782 | c | //******************************************************************************
// Ardit Pranvoku Collab with Thai Nghiem
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
#include <Math.h>
volatile unsigned int j;
int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode
// to activate previously configured port settings
P1DIR |= BIT0; // Set P1.0 to output direction
P1OUT &= ~BIT0; // Switch LED off
P1DIR |=BIT1; //set Port 1.1 output ---LED
P1OUT &= ~BIT1; //Clear P1.1
P5DIR &= ~BIT5; // Set P5.5 as input
P5OUT |= BIT5; // Configure P5.5 for Pull-Up
P5REN |= BIT5; // Enable Pull Up of P5.5
P5IE |= BIT5; //enable the interrupt on Port 5.5
P5IES &= ~BIT5; //set as falling edge
P5IFG &= ~(BIT5); //clear interrupt flag
TA0CTL = TASSEL_2 + MC_1 ; // SMCLK / Upmode
TA0CCTL1 = (CCIE); //CCTL1 Compare/Capture Interrupt Enable
TA0CCTL0 = (CCIE); //CCTL1 Compare/Capture Interrupt Enable
TA0CCR0 = 1000-1; // PWM Frequency 10 kHz
TA0CCR1 = 500; // 50% Duty Cycle
__bis_SR_register(GIE);
while(1)
{
if((P5IN & BIT5))
P1OUT &= ~BIT1; //Clear P1.1
}
}
#pragma vector=PORT5_VECTOR
__interrupt void PORT5_IRS(void)
{
P5IE &= ~BIT5; //Port 5 interrupt enable is turned off
__delay_cycles(1000); //Debounce
P5IE |= BIT5; //Port 1 interrupt enable is turned back on
P1OUT |= BIT1; //Sets P1.1
if(TA0CCR1 >= 1000) // If the brightness is at 100%
{
TA0CCR0 = 0; // Reset CCR0
TA0CCR1 = 0;// Reset CCR1
TA0CCR0 = 1000; // Set CCR0 back to 10 kHz
}
else if (TA0CCR1 < 1000){ // If the brightness is <= than 90%
TA0CCR0 = 0; // Reset CCR0
TA0CCR1 += 100; // Add 10%
TA0CCR0 = 1000;// Set CCR0 back to 10 kHz
}
P5IFG &= ~BIT5; //Clear flag
}
//Timer A interrupt vectors
#pragma vector=TIMER0_A1_VECTOR
__interrupt void Timer0_A1_ISR (void)
{
if(TA0CCR1 != 1000)
{
P1OUT &= ~(BIT0); //turns off red led
}
TA0CCTL1 &= ~BIT0; //clears flag
}
#pragma vector=TIMER0_A0_VECTOR
__interrupt void Timer0_A0_ISR (void)
{
if(TA0CCR1 != 0){
P1OUT |= (BIT0); //turns on red led
}
TA0CCTL0 &= ~BIT0; //clears flag
}
| [
"pranvoku.ardit@gmail.com"
] | pranvoku.ardit@gmail.com |
5d4546911e9385b658c14f2b489d5bc24cc2dc97 | 50a950d167bc213a23af6efc3122463687b316f8 | /CRC32.h | b08c47e763d079bb89ec4e2947deecc697925209 | [] | no_license | aqwapengwan/HW5 | 9e88cdd12c999ebe53ebbd13210e9d098c46df5d | 9490c8615ea2506e87436bd1cc70a9efb4866b03 | refs/heads/master | 2020-04-09T00:37:21.508247 | 2018-12-04T17:14:30 | 2018-12-04T17:14:30 | 159,874,774 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 72 | h | uint32_t crc32(const uint8_t *block, uint32_t blockSize, uint32_t crc);
| [
"35090728+aqwapengwan@users.noreply.github.com"
] | 35090728+aqwapengwan@users.noreply.github.com |
e77c3a29079f0438c6b0f9c279e6c3cf29bc7dc1 | 957c488487158d509f6b1d490e56129bbc5e0645 | /programs/wolfportal/src/ft_rot_pos.c | 8457386ba24df45f9bd5903b0c3ea9baa177831f | [] | no_license | sclolus/Turbofish | 4412d94dff5aef99e1d453413a13f5375e2d4f4d | 972e470f4144b62ce90765f32666d5c3b16d68d1 | refs/heads/master | 2022-06-21T04:01:25.338170 | 2019-12-05T17:36:09 | 2019-12-05T17:37:28 | 263,923,507 | 9 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,386 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* ft_rot_pos.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: vcombey <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2017/04/25 21:15:56 by vcombey #+# #+# */
/* Updated: 2017/04/26 14:36:40 by vcombey ### ########.fr */
/* */
/* ************************************************************************** */
#include "wolf.h"
void ft_swap_double_pos(t_double_pos *a)
{
double tmp;
tmp = a->y;
a->y = a->x;
a->x = tmp;
}
void ft_rev_rot_int(t_int_pos *a)
{
int tmp;
tmp = a->y;
a->y = -a->x;
a->x = tmp;
}
void ft_rev_rot_double(t_double_pos *a)
{
double tmp;
tmp = a->y;
a->y = -a->x;
a->x = tmp;
}
void ft_rot_int(t_int_pos *a)
{
int tmp;
tmp = -a->y;
a->y = a->x;
a->x = tmp;
}
void ft_rot_double(t_double_pos *a)
{
double tmp;
tmp = -a->y;
a->y = a->x;
a->x = tmp;
}
| [
"bmickael@student.42.fr"
] | bmickael@student.42.fr |
f477796c4a2e7931a4d55df395de9f6d16cf5bda | 8c7edcd53b018b91b79dd67ecc2129b0dcf749fd | /fgcp_frideg.c | fd1ed186991696b2095f680c56e42605e40d66c0 | [] | no_license | lineCode/jingdong_mcu | f19f44728f90e22bb5dea0d46199c1f235a88f6e | 835f3adf556ead1d5d86de65a2797b9c85a9f884 | refs/heads/master | 2021-08-07T11:11:23.530542 | 2017-11-08T03:27:43 | 2017-11-08T03:27:43 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,420 | c | /*++
Copyright (c) 2016 Wisky. All Rights Reserved.
Revision History:
2016-03-11 Created by Fibo Lu
--*/
#include "r_cg_macrodriver.h"
#include "r_cg_port.h"
#include "r_cg_userdefine.h"
#include "r_cg_serial.h"
#include "utility.h"
#include "sensor_adc.h"
#include "r_cg_timer.h"
#include "fgcp.h"
#include "signal_control.h"
#include "angle_as5600.h"
#include "uart_manager.h"
DOOR_STATE gDoorState;
static unsigned short gCloseDoorTick;
static FGCP_STATE_MACHINE gFridgeFGCPStateMachine;
static unsigned short gFridgeFGCPTestCount = 0;
static void closeDoor(unsigned char correctStartAngleRaw)
{
setDoorStatePin(0);
gDoorState = DOOR_STATE_CLOSED;
if (correctStartAngleRaw)
{
doorCalibratorSetCloseSignal();
}
gCloseDoorTick = getTickCount();
}
static void openDoor()
{
gDoorState = DOOR_STATE_OPEN;
setDoorStatePin(1);
sendWakeupSignal();
}
static void doorStateMachine()
{
switch (gDoorState)
{
case DOOR_STATE_CLOSED:
if ((gAS5600StartAngleRaw != INVALID_ANGLE_RAW) && gAS5600Degree > 300)
{
openDoor();
}
break;
case DOOR_STATE_OPEN:
if ((gAS5600StartAngleRaw != INVALID_ANGLE_RAW) && gAS5600Degree < 30)
{
closeDoor(0);
}
break;
/*
case DOOR_STATE_IS_CLOSED:
if (overTickCount(gCloseDoorTick, 3000))
{
as5600CloseDoorSignal();
gDoorState = DOOR_STATE_CLOSED;
fgcpReportNeed(FGCP_REPORT_NEED_FLAG_0X78);
}
break;
*/
}
}
DOOR_STATE getDoorState()
{
return gDoorState;
}
static unsigned short g_openCount;
static unsigned short g_closeCount;
static void fridgeFGCPMessageProcess()
{
if (gFridgeFGCPStateMachine.mData.mHeader.mMessageType == 0x04 \
&& gFridgeFGCPStateMachine.mData.mHeader.mData0 == 0x00)
{
if (gFridgeFGCPStateMachine.mData.mHeader.mData1 & 0x01)
{
g_openCount++;
openDoor();
}
else
{
g_closeCount++;
closeDoor(1);
}
}
if ((getFgcpType() != FGCP_TYPE_MIDEA) && (gFridgeFGCPStateMachine.mJdBufferBytes == 0))
{
gFridgeFGCPStateMachine.mJdBufferBytes = fgcpJDConverter(gFridgeFGCPStateMachine.mData.mBuffer, gFridgeFGCPStateMachine.mJdBuffer);
}
}
void fridgeFGCPAnalysis(unsigned char *buf, unsigned char len)
{
unsigned char i;
gFridgeFGCPStateMachine.mWatchDogTickSecond = getTickCount();
for (i = 0; i < len; i++)
FGCPStateMachine(&gFridgeFGCPStateMachine, buf[i]);
if (gFridgeFGCPStateMachine.mState == FGCP_STATE_RX_END)
{
if (FGCPMessageCheck(gFridgeFGCPStateMachine.mData.mBuffer) == MD_OK)
{
fridgeFGCPMessageProcess();
}
gFridgeFGCPStateMachine.mState = FGCP_STATE_IDLE;
}
}
void fgcpFridegInit()
{
gFridgeFGCPStateMachine.mState = FGCP_STATE_IDLE;
gFridgeFGCPStateMachine.mWatchDogTickSecond = 0;
gDoorState = DOOR_STATE_CLOSED;
gCloseDoorTick = 0;
g_openCount = 0;
g_closeCount = 0;
}
void fgcpFridegRun()
{
if (gFridgeFGCPStateMachine.mJdBufferBytes)
{
if (androidUartSend(gFridgeFGCPStateMachine.mJdBuffer, \
gFridgeFGCPStateMachine.mJdBufferBytes, 0) == MD_OK)
{
gFridgeFGCPStateMachine.mJdBufferBytes = 0;
}
}
if (overTickCount(gFridgeFGCPStateMachine.mWatchDogTickSecond, 50))
{
gFridgeFGCPStateMachine.mWatchDogTickSecond = getTickCount();
gFridgeFGCPStateMachine.mState = FGCP_STATE_IDLE;
}
doorStateMachine();
}
| [
"luxiujun@wisky.com.cn"
] | luxiujun@wisky.com.cn |
761525b9ee0f88bbcb35f4897d573cf8e1a631e5 | 99bdb3251fecee538e0630f15f6574054dfc1468 | /bsp/allwinner/libraries/sunxi-hal/hal/source/g2d_rcq/simple_idr.c | 3e9970816c9130c1ace7241c4491ba65f658fe9f | [
"Apache-2.0",
"Zlib",
"LicenseRef-scancode-proprietary-license",
"MIT",
"BSD-3-Clause",
"X11",
"BSD-4-Clause-UC",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | RT-Thread/rt-thread | 03a7c52c2aeb1b06a544143b0e803d72f47d1ece | 3602f891211904a27dcbd51e5ba72fefce7326b2 | refs/heads/master | 2023-09-01T04:10:20.295801 | 2023-08-31T16:20:55 | 2023-08-31T16:20:55 | 7,408,108 | 9,599 | 5,805 | Apache-2.0 | 2023-09-14T13:37:26 | 2013-01-02T14:49:21 | C | UTF-8 | C | false | false | 8,199 | c | /*
* simple_idr.c
*
* Copyright (c) 2007-2019 Allwinnertech Co., Ltd.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
//not apply it in the IRQ, a simple idr from linux
#include <stdio.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "g2d_bsp.h"
#include "simple_idr.h"
static struct id_layer** find_empty_slot(struct id_layer *up_layer, int *id_index)
{
//first right empty 0~31
int i = 0, start = 0, id = 0;
for (i = 0; i < IDR_SIZE/32; i++)
if(up_layer->bitmap[i] != IDR32_MASK)
break;
if (i == IDR_SIZE/32) {
*id_index = NO_ID;
return NULL;
}
if (up_layer->bitmap[i] == 0)
goto cal;
id = ~up_layer->bitmap[i];
// 0~31 bit
if (!(id&0x0000ffff)) {
start +=16;
id >>= 16;
}
if (!(id&0x00ff)) {
start += 8;
id >>= 8;
}
if (!(id&0x0f)) {
start += 4;
id >>= 4;
}
if (!(id&0x3)) {
start += 2;
id >>= 2;
}
if (!(id&0x1)) {
start += 1;
id >>= 1;
}
cal:
*id_index = i*32+start;
return &up_layer->layer[*id_index];
}
int id_alloc(struct id_dir *dir, void *value)
{
int id = NO_ID, id_index = NO_ID;
int i = 0;
int curr_lvl;
struct id_layer **cur = NULL, *tmp = NULL;
if (dir == NULL || dir->status == -1)
return NO_ID;
hal_sem_wait(dir->lock);
if (dir->status == -1)
goto out;
dir->status = 1;
if (dir->lu_cache[0] != NULL) {
tmp = dir->lu_cache[0];
id = dir->lu_id;
cur = find_empty_slot(tmp, &id_index);
id = (id&(~0xff)) + id_index;
}else{
//add a new top
if (dir->top == NULL || find_empty_slot(dir->top, &id_index) == NULL) {
if (dir->top && dir->cur_max_level > 2) {
G2D_INFO_MSG("a full idr,we only support 32bit\n");
goto out;
}
tmp = (struct id_layer*)hal_malloc(sizeof(struct id_layer));
memset(tmp, 0, sizeof(struct id_layer));
tmp->layer[0] = dir->top;
tmp->bitmap[0] = 0x01;//0 is NO_ID
tmp->num_layer = 1;
dir->cur_max_level++;
dir->top = tmp;
if (dir->head) {
dir->head->pre = tmp;
}
tmp->next = dir->head;
}
curr_lvl = dir->cur_max_level;
for (cur= &dir->top; *cur != NULL; id <<= 8, id += id_index, curr_lvl--) {
tmp = *cur;
dir->lu_cache[curr_lvl] = tmp;
cur = find_empty_slot(tmp, &id_index);
if (curr_lvl > 0 && *cur == NULL) {
//add a new child idr
*cur = (struct id_layer*)hal_malloc(sizeof(struct id_layer));
if (*cur == NULL) {
G2D_INFO_MSG("atomic alloc idr mem err.\n");
goto out;
}
memset(*cur, 0, sizeof(struct id_layer));
tmp->num_layer++;
(*cur)->next = dir->head;
(*cur)->pre = NULL;
dir->head = *cur;
}
}
}
dir->lu_id = id;
*cur = (struct id_layer*)value;
tmp->bitmap[id_index/32] |= 1 << (id_index%32);
tmp->num_layer++;
if (tmp->num_layer == IDR_SIZE) {
dir->lu_cache[0] = NULL;
for (i = 1; dir->lu_cache[i] != NULL && i < dir->cur_max_level; i++) {
id_index = (id>>(8*i)) & 0xff;
dir->lu_cache[i]->bitmap[id_index/32] |= 1 << (id_index%32);
if (find_empty_slot(dir->lu_cache[i], &id_index) != NULL) {
break;
}
}
}
dir->status = 0;
out:
hal_sem_post(dir->lock);
// printf("id_alloc:%d == %08x\n",id, value);
return id;
}
void id_free(struct id_dir *dir, int id)
{
struct id_layer* lu[4] = {NULL, NULL, NULL, NULL};
int i = 0, id_index = 0;
if (id>>((dir->cur_max_level+1)*8) || id == NO_ID
|| dir->top == NULL || dir->status == -1) {
G2D_INFO_MSG("give a err id:%d, max:%ld\n", id, (1ul << ((dir->cur_max_level+1)* 8)) - 1);
return;
}
hal_sem_wait(dir->lock);
if (dir->status == -1)
goto out;
dir->status = 1;
lu[dir->cur_max_level] = dir->top;
for (i = dir->cur_max_level; i > 0; ) {
id_index = (id>>(i*8)) & 0xff;
i--;
lu[i] = lu[i+1]->layer[id_index];
}
id_index = id&0xff;
lu[0]->layer[id_index] = NULL;
lu[0]->num_layer--;
lu[0]->bitmap[id_index/32] &= ~(1<<(id_index % 32));
for (i = 1; i <= dir->cur_max_level; i++) {
id_index = (id>>(i*8)) & 0xff;
lu[i]->bitmap[id_index/32] &= ~(1<<(id_index % 32));
if (lu[i-1]->num_layer == 0) {
//top will not empty due to NO_ID, least 1 top layer.
if (lu[i]->layer[id_index]->next != NULL)
lu[i]->layer[id_index]->next->pre = lu[i]->layer[id_index]->pre;
if (lu[i]->layer[id_index]->pre != NULL)
lu[i]->layer[id_index]->pre->next = lu[i]->layer[id_index]->next;
else
dir->head = lu[i]->layer[id_index]->next;
free(lu[i]->layer[id_index]);
lu[i]->layer[id_index] = NULL;
lu[i]->num_layer--;
}
}
//deal_top:
while (dir->top->num_layer == 1 && dir->cur_max_level > 0
&& dir->top->layer[0] != NULL && dir->top->bitmap[0]^0x01) {
lu[0] = dir->top;
dir->top = lu[0]->layer[0];
if (lu[0]->next != NULL)
lu[0]->next->pre = lu[0]->pre;
if (lu[0]->pre != NULL)
lu[0]->pre->next = lu[0]->next;
else
dir->head = lu[0]->next;
free(lu[0]);
dir->cur_max_level--;
}
dir->status = 0;
out:
hal_sem_post(dir->lock);
//printf("leave id_free: %d \n", id);
}
void* id_get(struct id_dir *dir, int id)
{
int id_index, i;
struct id_layer *lu = NULL;
if (dir == NULL || dir->top == NULL || dir->status == -1 || id == NO_ID)
return NULL;
//the atomic area , but not happen
if (id>>((dir->cur_max_level+1)*8))
return NULL;
hal_sem_wait(dir->lock);
if (dir->status == -1)
goto out;
dir->status = 1;
lu = dir->top;
for (i = dir->cur_max_level; i >= 0; i--) {
id_index = (id>>(i*8)) & 0xff;
lu = lu->layer[id_index];
if (lu == NULL) {
G2D_INFO_MSG("give a err id:%d\n", id);
goto out;
}
}
dir->status = 0;
out:
hal_sem_post(dir->lock);
//printf("got id:%d=%08x\n",id,lu);
return (void*)lu;
}
struct id_dir* id_creat(void)
{
struct id_dir* idr;
int i;
idr = (struct id_dir*)hal_malloc(sizeof(struct id_dir));
if(idr == NULL) {
G2D_INFO_MSG("malloc idr err.\n");
return NULL;
}
memset(idr, 0, sizeof(struct id_dir));
idr->cur_max_level = -1;
idr->lock = hal_sem_create(1);
for(i = 0; i < 4; i++)
idr->lu_cache[i] = NULL;
idr->lu_id = 0;
idr->head = NULL;
idr->top = (struct id_layer*)hal_malloc(sizeof(struct id_layer));
if (idr->top == NULL) {
G2D_INFO_MSG("malloc id_layer err.\n");
goto out;
}
memset(idr->top, 0, sizeof(struct id_layer));
idr->top->bitmap[0] = 0x01; //0 is NO_ID
idr->top->num_layer = 1;
idr->cur_max_level = 0;
idr->head = idr->top;
idr->lu_cache[0] = idr->top;
out:
return idr;
}
void id_destroyed(struct id_dir *dir)
{
struct id_layer* free_id_layer;
hal_sem_wait(dir->lock);
dir->status = -1;
hal_sem_post(dir->lock);
while(dir->head != NULL) {
free_id_layer = dir->head;
dir->head = free_id_layer->next;
free(free_id_layer);
}
free(dir);
}
| [
"noreply@github.com"
] | RT-Thread.noreply@github.com |
2103c96b595c45feda2791208eb255e2a5bcb97c | 76a3d8485ecfe4d9ee51ffa5862946f3223bfa1a | /module/rdpComposite.h | 08fd7da95dc74d144e9b0a812eae8656ee549d98 | [
"MIT-open-group",
"X11"
] | permissive | neutrinolabs/xorgxrdp | 59ab958a60ae1b2af98bc6cd481ee36c57de8ce7 | bf49ee19f8478bd37920da3ea45e2f285b4c9997 | refs/heads/devel | 2023-09-06T05:58:07.907521 | 2023-05-29T13:08:07 | 2023-05-29T13:08:07 | 24,623,762 | 397 | 128 | NOASSERTION | 2023-09-09T23:13:42 | 2014-09-30T03:55:45 | C | UTF-8 | C | false | false | 1,295 | h | /*
Copyright 2005-2017 Jay Sorg
Permission to use, copy, modify, distribute, and sell this software and its
documentation for any purpose is hereby granted without fee, provided that
the above copyright notice appear in all copies and that both that
copyright notice and this permission notice appear in supporting
documentation.
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
composite(alpha blending) calls
*/
#ifndef _RDPCOMPOSITE_H
#define _RDPCOMPOSITE_H
#include <xorg-server.h>
#include <xorgVersion.h>
#include <xf86.h>
extern _X_EXPORT void
rdpComposite(CARD8 op, PicturePtr pSrc, PicturePtr pMask, PicturePtr pDst,
INT16 xSrc, INT16 ySrc, INT16 xMask, INT16 yMask, INT16 xDst,
INT16 yDst, CARD16 width, CARD16 height);
#endif
| [
"jay.sorg@gmail.com"
] | jay.sorg@gmail.com |
df1f1cf5dfe2cbb1aebf279e1868762543ed7c90 | fa32e1579b76c6e6e14001f10143ceeadea5aa72 | /station/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c | cc7b95100284adb8f22a5cb546508d53e99776c7 | [
"MIT",
"BSD-3-Clause",
"LicenseRef-scancode-st-bsd-restricted"
] | permissive | tigercosmos/bus-iot | 0e155cb0a36a63969b1576f65865f913aa3098ec | a08427e41b33b9102c3dcc79f27599ad9b56b750 | refs/heads/master | 2021-01-19T15:17:18.752546 | 2020-03-09T04:04:59 | 2020-03-09T04:04:59 | 100,954,785 | 1 | 2 | MIT | 2020-03-09T04:05:00 | 2017-08-21T13:25:13 | C | UTF-8 | C | false | false | 68,580 | c | /**
* @file
* Dynamic Host Configuration Protocol client
*
*/
/*
* Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
* Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
* The Swedish Institute of Computer Science and Adam Dunkels
* are specifically granted permission to redistribute this
* source code.
*
* Author: Leon Woestenberg <leon.woestenberg@gmx.net>
*
* This is a DHCP client for the lwIP TCP/IP stack. It aims to conform
* with RFC 2131 and RFC 2132.
*
* TODO:
* - Support for interfaces other than Ethernet (SLIP, PPP, ...)
*
* Please coordinate changes and requests with Leon Woestenberg
* <leon.woestenberg@gmx.net>
*
* Integration with your code:
*
* In lwip/dhcp.h
* #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute)
* #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer)
*
* Then have your application call dhcp_coarse_tmr() and
* dhcp_fine_tmr() on the defined intervals.
*
* dhcp_start(struct netif *netif);
* starts a DHCP client instance which configures the interface by
* obtaining an IP address lease and maintaining it.
*
* Use dhcp_release(netif) to end the lease and use dhcp_stop(netif)
* to remove the DHCP client.
*
*/
#include "lwip/opt.h"
#if LWIP_IPV4 && LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
#include "lwip/stats.h"
#include "lwip/mem.h"
#include "lwip/udp.h"
#include "lwip/ip_addr.h"
#include "lwip/netif.h"
#include "lwip/def.h"
#include "lwip/dhcp.h"
#include "lwip/autoip.h"
#include "lwip/dns.h"
#include "netif/etharp.h"
#include <string.h>
/** DHCP_CREATE_RAND_XID: if this is set to 1, the xid is created using
* LWIP_RAND() (this overrides DHCP_GLOBAL_XID)
*/
#ifndef DHCP_CREATE_RAND_XID
#define DHCP_CREATE_RAND_XID 1
#endif
/** Default for DHCP_GLOBAL_XID is 0xABCD0000
* This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g.
* #define DHCP_GLOBAL_XID_HEADER "stdlib.h"
* #define DHCP_GLOBAL_XID rand()
*/
#ifdef DHCP_GLOBAL_XID_HEADER
#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */
#endif
/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU
* MTU is checked to be big enough in dhcp_start */
#define DHCP_MAX_MSG_LEN(netif) (netif->mtu)
#define DHCP_MAX_MSG_LEN_MIN_REQUIRED 576
/** Minimum length for reply before packet is parsed */
#define DHCP_MIN_REPLY_LEN 44
#define REBOOT_TRIES 2
/** Option handling: options are parsed in dhcp_parse_reply
* and saved in an array where other functions can load them from.
* This might be moved into the struct dhcp (not necessarily since
* lwIP is single-threaded and the array is only used while in recv
* callback). */
#define DHCP_OPTION_IDX_OVERLOAD 0
#define DHCP_OPTION_IDX_MSG_TYPE 1
#define DHCP_OPTION_IDX_SERVER_ID 2
#define DHCP_OPTION_IDX_LEASE_TIME 3
#define DHCP_OPTION_IDX_T1 4
#define DHCP_OPTION_IDX_T2 5
#define DHCP_OPTION_IDX_SUBNET_MASK 6
#define DHCP_OPTION_IDX_ROUTER 7
#define DHCP_OPTION_IDX_DNS_SERVER 8
#if LWIP_DHCP_GET_NTP_SRV
#define DHCP_OPTION_IDX_NTP_SERVER (DHCP_OPTION_IDX_DNS_SERVER + DNS_MAX_SERVERS)
#define DHCP_OPTION_IDX_MAX (DHCP_OPTION_IDX_NTP_SERVER + LWIP_DHCP_MAX_NTP_SERVERS)
#else /* LWIP_DHCP_GET_NTP_SRV */
#define DHCP_OPTION_IDX_MAX (DHCP_OPTION_IDX_DNS_SERVER + DNS_MAX_SERVERS)
#endif /* LWIP_DHCP_GET_NTP_SRV */
/** Holds the decoded option values, only valid while in dhcp_recv.
@todo: move this into struct dhcp? */
u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX];
/** Holds a flag which option was received and is contained in dhcp_rx_options_val,
only valid while in dhcp_recv.
@todo: move this into struct dhcp? */
u8_t dhcp_rx_options_given[DHCP_OPTION_IDX_MAX];
static u8_t dhcp_discover_select_options[] = {
DHCP_OPTION_SUBNET_MASK,
DHCP_OPTION_ROUTER,
DHCP_OPTION_BROADCAST,
DHCP_OPTION_DNS_SERVER
#if LWIP_DHCP_GET_NTP_SRV
, DHCP_OPTION_NTP
#endif /* LWIP_DHCP_GET_NTP_SRV */
};
#ifdef DHCP_GLOBAL_XID
static u32_t xid;
static u8_t xid_initialised;
#endif /* DHCP_GLOBAL_XID */
#define dhcp_option_given(dhcp, idx) (dhcp_rx_options_given[idx] != 0)
#define dhcp_got_option(dhcp, idx) (dhcp_rx_options_given[idx] = 1)
#define dhcp_clear_option(dhcp, idx) (dhcp_rx_options_given[idx] = 0)
#define dhcp_clear_all_options(dhcp) (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given)))
#define dhcp_get_option_value(dhcp, idx) (dhcp_rx_options_val[idx])
#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val))
/* DHCP client state machine functions */
static err_t dhcp_discover(struct netif *netif);
static err_t dhcp_select(struct netif *netif);
static void dhcp_bind(struct netif *netif);
#if DHCP_DOES_ARP_CHECK
static err_t dhcp_decline(struct netif *netif);
#endif /* DHCP_DOES_ARP_CHECK */
static err_t dhcp_rebind(struct netif *netif);
static err_t dhcp_reboot(struct netif *netif);
static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state);
/* receive, unfold, parse and free incoming messages */
static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
/* set the DHCP timers */
static void dhcp_timeout(struct netif *netif);
static void dhcp_t1_timeout(struct netif *netif);
static void dhcp_t2_timeout(struct netif *netif);
/* build outgoing messages */
/* create a DHCP message, fill in common headers */
static err_t dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type);
/* free a DHCP request */
static void dhcp_delete_msg(struct dhcp *dhcp);
/* add a DHCP option (type, then length in bytes) */
static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len);
/* add option values */
static void dhcp_option_byte(struct dhcp *dhcp, u8_t value);
static void dhcp_option_short(struct dhcp *dhcp, u16_t value);
static void dhcp_option_long(struct dhcp *dhcp, u32_t value);
#if LWIP_NETIF_HOSTNAME
static void dhcp_option_hostname(struct dhcp *dhcp, struct netif *netif);
#endif /* LWIP_NETIF_HOSTNAME */
/* always add the DHCP options trailer to end and pad */
static void dhcp_option_trailer(struct dhcp *dhcp);
/**
* Back-off the DHCP client (because of a received NAK response).
*
* Back-off the DHCP client because of a received NAK. Receiving a
* NAK means the client asked for something non-sensible, for
* example when it tries to renew a lease obtained on another network.
*
* We clear any existing set IP address and restart DHCP negotiation
* afresh (as per RFC2131 3.2.3).
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_nak(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
(void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* remove IP address from interface (must no longer be used, as per RFC2131) */
netif_set_addr(netif, IP4_ADDR_ANY, IP4_ADDR_ANY, IP4_ADDR_ANY);
/* Change to a defined state */
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
/* We can immediately restart discovery */
dhcp_discover(netif);
}
#if DHCP_DOES_ARP_CHECK
/**
* Checks if the offered IP address is already in use.
*
* It does so by sending an ARP request for the offered address and
* entering CHECKING state. If no ARP reply is received within a small
* interval, the address is assumed to be free for use by us.
*
* @param netif the netif under DHCP control
*/
static void
dhcp_check(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
(s16_t)netif->name[1]));
dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
/* create an ARP query for the offered IP address, expecting that no host
responds, as the IP address should not be in use. */
result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
if (result != ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
msecs = 500;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
}
#endif /* DHCP_DOES_ARP_CHECK */
/**
* Remember the configuration offered by a DHCP server.
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_offer(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
(void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* obtain the server address */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
ip_addr_set_ip4_u32(&dhcp->server_ip_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
/* remember offered address */
ip4_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_select(netif);
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void*)netif));
}
}
/**
* Select a DHCP server offer out of all offers.
*
* Simply select the first offer received.
*
* @param netif the netif under DHCP control
* @return lwIP specific error (see error.h)
*/
static err_t
dhcp_select(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
u16_t msecs;
u8_t i;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
/* MUST request the offered IP address */
dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, sizeof(dhcp_discover_select_options));
for (i = 0; i < sizeof(dhcp_discover_select_options); i++) {
dhcp_option_byte(dhcp, dhcp_discover_select_options[i]);
}
#if LWIP_NETIF_HOSTNAME
dhcp_option_hostname(dhcp, netif);
#endif /* LWIP_NETIF_HOSTNAME */
dhcp_option_trailer(dhcp);
/* shrink the pbuf to the actual content length */
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
/* send broadcast to any DHCP server */
udp_sendto_if_src(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP_ADDR_ANY);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
/**
* The DHCP timer that checks for lease renewal/rebind timeouts.
*/
void
dhcp_coarse_tmr(void)
{
struct netif *netif = netif_list;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
/* iterate through all network interfaces */
while (netif != NULL) {
/* only act on DHCP configured interfaces */
struct dhcp* dhcp = netif->dhcp;
if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
/* compare lease time to expire timeout */
if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
/* this clients' lease time has expired */
dhcp_release(netif);
dhcp_discover(netif);
/* timer is active (non zero), and triggers (zeroes) now? */
} else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
/* this clients' rebind timeout triggered */
dhcp_t2_timeout(netif);
/* timer is active (non zero), and triggers (zeroes) now */
} else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
/* this clients' renewal timeout triggered */
dhcp_t1_timeout(netif);
}
}
/* proceed to next netif */
netif = netif->next;
}
}
/**
* DHCP transaction timeout handling
*
* A DHCP server is expected to respond within a short period of time.
* This timer checks whether an outstanding DHCP request is timed out.
*/
void
dhcp_fine_tmr(void)
{
struct netif *netif = netif_list;
/* loop through netif's */
while (netif != NULL) {
/* only act on DHCP configured interfaces */
if (netif->dhcp != NULL) {
/* timer is active (non zero), and is about to trigger now */
if (netif->dhcp->request_timeout > 1) {
netif->dhcp->request_timeout--;
}
else if (netif->dhcp->request_timeout == 1) {
netif->dhcp->request_timeout--;
/* { netif->dhcp->request_timeout == 0 } */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
/* this client's request timeout triggered */
dhcp_timeout(netif);
}
}
/* proceed to next network interface */
netif = netif->next;
}
}
/**
* A DHCP negotiation transaction, or ARP request, has timed out.
*
* The timer that was started with the DHCP or ARP request has
* timed out, indicating no response was received in time.
*
* @param netif the netif under DHCP control
*/
static void
dhcp_timeout(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
/* back-off period has passed, or server selection timed out */
if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
dhcp_discover(netif);
/* receiving the requested lease timed out */
} else if (dhcp->state == DHCP_STATE_REQUESTING) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n"));
if (dhcp->tries <= 5) {
dhcp_select(netif);
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n"));
dhcp_release(netif);
dhcp_discover(netif);
}
#if DHCP_DOES_ARP_CHECK
/* received no ARP reply for the offered address (which is good) */
} else if (dhcp->state == DHCP_STATE_CHECKING) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n"));
if (dhcp->tries <= 1) {
dhcp_check(netif);
/* no ARP replies on the offered address,
looks like the IP address is indeed free */
} else {
/* bind the interface to the offered address */
dhcp_bind(netif);
}
#endif /* DHCP_DOES_ARP_CHECK */
} else if (dhcp->state == DHCP_STATE_REBOOTING) {
if (dhcp->tries < REBOOT_TRIES) {
dhcp_reboot(netif);
} else {
dhcp_discover(netif);
}
}
}
/**
* The renewal period has timed out.
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t1_timeout(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
(dhcp->state == DHCP_STATE_RENEWING)) {
/* just retry to renew - note that the rebind timer (t2) will
* eventually time-out if renew tries fail. */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t1_timeout(): must renew\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
dhcp_renew(netif);
/* Calculate next timeout */
if (((netif->dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS))
{
netif->dhcp->t1_renew_time = ((netif->dhcp->t2_timeout - dhcp->lease_used) / 2);
}
}
}
/**
* The rebind period has timed out.
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t2_timeout(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
/* just retry to rebind */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t2_timeout(): must rebind\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
dhcp_rebind(netif);
/* Calculate next timeout */
if (((netif->dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS))
{
netif->dhcp->t2_rebind_time = ((netif->dhcp->t0_timeout - dhcp->lease_used) / 2);
}
}
}
/**
* Handle a DHCP ACK packet
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_ack(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
#if LWIP_DNS || LWIP_DHCP_GET_NTP_SRV
u8_t n;
#endif /* LWIP_DNS || LWIP_DHCP_GET_NTP_SRV */
#if LWIP_DHCP_GET_NTP_SRV
ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
#endif
/* clear options we might not get from the ACK */
ip4_addr_set_zero(&dhcp->offered_sn_mask);
ip4_addr_set_zero(&dhcp->offered_gw_addr);
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* lease time given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
/* remember offered lease time */
dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
/* remember given renewal period */
dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
} else {
/* calculate safe periods for renewal */
dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
/* remember given rebind period */
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
} else {
/* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
}
/* (y)our internet address */
ip4_addr_copy(dhcp->offered_ip_addr, dhcp->msg_in->yiaddr);
#if LWIP_DHCP_BOOTP_FILE
/* copy boot server address,
boot file name copied in dhcp_parse_reply if not overloaded */
ip_addr_copy(dhcp->offered_si_addr, dhcp->msg_in->siaddr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* subnet mask given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
/* remember given subnet mask */
ip4_addr_set_u32(&dhcp->offered_sn_mask, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
dhcp->subnet_mask_given = 1;
} else {
dhcp->subnet_mask_given = 0;
}
/* gateway router */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
ip4_addr_set_u32(&dhcp->offered_gw_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
}
#if LWIP_DHCP_GET_NTP_SRV
/* NTP servers */
for (n = 0; (n < LWIP_DHCP_MAX_NTP_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n); n++) {
ip4_addr_set_u32(&ntp_server_addrs[n], htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n)));
}
dhcp_set_ntp_servers(n, ntp_server_addrs);
#endif /* LWIP_DHCP_GET_NTP_SRV */
#if LWIP_DNS
/* DNS servers */
for (n = 0; (n < DNS_MAX_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) {
ip_addr_t dns_addr;
ip_addr_set_ip4_u32(&dns_addr, htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
dns_setserver(n, &dns_addr);
}
#endif /* LWIP_DNS */
}
/** Set a statically allocated struct dhcp to work with.
* Using this prevents dhcp_start to allocate it using mem_malloc.
*
* @param netif the netif for which to set the struct dhcp
* @param dhcp (uninitialised) dhcp struct allocated by the application
*/
void
dhcp_set_struct(struct netif *netif, struct dhcp *dhcp)
{
LWIP_ASSERT("netif != NULL", netif != NULL);
LWIP_ASSERT("dhcp != NULL", dhcp != NULL);
LWIP_ASSERT("netif already has a struct dhcp set", netif->dhcp == NULL);
/* clear data structure */
memset(dhcp, 0, sizeof(struct dhcp));
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
netif->dhcp = dhcp;
}
/** Removes a struct dhcp from a netif.
*
* ATTENTION: Only use this when not using dhcp_set_struct() to allocate the
* struct dhcp since the memory is passed back to the heap.
*
* @param netif the netif from which to remove the struct dhcp
*/
void dhcp_cleanup(struct netif *netif)
{
LWIP_ASSERT("netif != NULL", netif != NULL);
if (netif->dhcp != NULL) {
mem_free(netif->dhcp);
netif->dhcp = NULL;
}
}
/**
* Start DHCP negotiation for a network interface.
*
* If no DHCP client instance was attached to this interface,
* a new client is created first. If a DHCP client instance
* was already present, it restarts negotiation.
*
* @param netif The lwIP network interface
* @return lwIP error code
* - ERR_OK - No error
* - ERR_MEM - Out of memory
*/
err_t
dhcp_start(struct netif *netif)
{
struct dhcp *dhcp;
err_t result;
LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* check hwtype of the netif */
if ((netif->flags & NETIF_FLAG_ETHARP) == 0) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): No ETHARP netif\n"));
return ERR_ARG;
}
/* check MTU of the netif */
if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
return ERR_MEM;
}
/* no DHCP client attached yet? */
if (dhcp == NULL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting new DHCP client\n"));
dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
if (dhcp == NULL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
return ERR_MEM;
}
/* store this dhcp client in the netif */
netif->dhcp = dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
/* already has DHCP client attached */
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
if (dhcp->pcb != NULL) {
udp_remove(dhcp->pcb);
}
LWIP_ASSERT("pbuf p_out wasn't freed", dhcp->p_out == NULL);
LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL );
}
/* clear data structure */
memset(dhcp, 0, sizeof(struct dhcp));
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
/* allocate UDP PCB */
dhcp->pcb = udp_new();
if (dhcp->pcb == NULL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not obtain pcb\n"));
return ERR_MEM;
}
ip_set_option(dhcp->pcb, SOF_BROADCAST);
/* set up local and remote port for the pcb */
udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT);
/* set up the recv callback and argument */
udp_recv(dhcp->pcb, dhcp_recv, netif);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
#if LWIP_DHCP_CHECK_LINK_UP
if (!netif_is_link_up(netif)) {
/* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
dhcp_set_state(dhcp, DHCP_STATE_INIT);
return ERR_OK;
}
#endif /* LWIP_DHCP_CHECK_LINK_UP */
/* (re)start the DHCP negotiation */
result = dhcp_discover(netif);
if (result != ERR_OK) {
/* free resources allocated above */
dhcp_stop(netif);
return ERR_MEM;
}
return result;
}
/**
* Inform a DHCP server of our manual configuration.
*
* This informs DHCP servers of our fixed IP address configuration
* by sending an INFORM message. It does not involve DHCP address
* configuration, it is just here to be nice to the network.
*
* @param netif The lwIP network interface
*/
void
dhcp_inform(struct netif *netif)
{
struct dhcp dhcp;
err_t result = ERR_OK;
struct udp_pcb *pcb;
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
memset(&dhcp, 0, sizeof(struct dhcp));
dhcp_set_state(&dhcp, DHCP_STATE_INFORMING);
if ((netif->dhcp != NULL) && (netif->dhcp->pcb != NULL)) {
/* re-use existing pcb */
pcb = netif->dhcp->pcb;
} else {
pcb = udp_new();
if (pcb == NULL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform(): could not obtain pcb"));
return;
}
dhcp.pcb = pcb;
ip_set_option(dhcp.pcb, SOF_BROADCAST);
udp_bind(dhcp.pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_inform(): created new udp pcb\n"));
}
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, &dhcp, DHCP_INFORM);
if (result == ERR_OK) {
dhcp_option(&dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(&dhcp, DHCP_MAX_MSG_LEN(netif));
dhcp_option_trailer(&dhcp);
pbuf_realloc(dhcp.p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp.options_out_len);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n"));
udp_sendto_if(pcb, dhcp.p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
dhcp_delete_msg(&dhcp);
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n"));
}
if (dhcp.pcb != NULL) {
/* otherwise, the existing pcb was used */
udp_remove(dhcp.pcb);
}
}
/** Handle a possible change in the network configuration.
*
* This enters the REBOOTING state to verify that the currently bound
* address is still valid.
*/
void
dhcp_network_changed(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
if (!dhcp)
return;
switch (dhcp->state) {
case DHCP_STATE_REBINDING:
case DHCP_STATE_RENEWING:
case DHCP_STATE_BOUND:
case DHCP_STATE_REBOOTING:
dhcp->tries = 0;
dhcp_reboot(netif);
break;
case DHCP_STATE_OFF:
/* stay off */
break;
default:
/* INIT/REQUESTING/CHECKING/BACKING_OFF restart with new 'rid' because the
state changes, SELECTING: continue with current 'rid' as we stay in the
same state */
#if LWIP_DHCP_AUTOIP_COOP
if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
/* ensure we start with short timeouts, even if already discovering */
dhcp->tries = 0;
dhcp_discover(netif);
break;
}
}
#if DHCP_DOES_ARP_CHECK
/**
* Match an ARP reply with the offered IP address.
*
* @param netif the network interface on which the reply was received
* @param addr The IP address we received a reply from
*/
void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
{
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
/* is a DHCP client doing an ARP check? */
if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_STATE_CHECKING)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
ip4_addr_get_u32(addr)));
/* did a host respond with the address we
were offered by the DHCP server? */
if (ip4_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) {
/* we will not accept the offered address */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
dhcp_decline(netif);
}
}
}
/**
* Decline an offered lease.
*
* Tell the DHCP server we do not accept the offered address.
* One reason to decline the lease is when we find out the address
* is already in use by another host (through ARP).
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_decline(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result = ERR_OK;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_DECLINE);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_option_trailer(dhcp);
/* resize pbuf to reflect true size of options */
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
/* per section 4.4.4, broadcast DECLINE messages */
udp_sendto_if_src(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP_ADDR_ANY);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_decline: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
msecs = 10*1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
#endif /* DHCP_DOES_ARP_CHECK */
/**
* Start the DHCP process, discover a DHCP server.
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_discover(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result = ERR_OK;
u16_t msecs;
u8_t i;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
ip4_addr_set_any(&dhcp->offered_ip_addr);
dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER);
if (result == ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, sizeof(dhcp_discover_select_options));
for (i = 0; i < sizeof(dhcp_discover_select_options); i++) {
dhcp_option_byte(dhcp, dhcp_discover_select_options[i]);
}
dhcp_option_trailer(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: realloc()ing\n"));
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n"));
udp_sendto_if_src(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif, IP_ADDR_ANY);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
#if LWIP_DHCP_AUTOIP_COOP
if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
autoip_start(netif);
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
msecs = (dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
/**
* Bind the interface to the offered IP address.
*
* @param netif network interface to bind to the offered address
*/
static void
dhcp_bind(struct netif *netif)
{
u32_t timeout;
struct dhcp *dhcp;
ip4_addr_t sn_mask, gw_addr;
LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
dhcp = netif->dhcp;
LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* reset time used of lease */
dhcp->lease_used = 0;
if (dhcp->offered_t0_lease != 0xffffffffUL) {
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
if (timeout > 0xffff) {
timeout = 0xffff;
}
dhcp->t0_timeout = (u16_t)timeout;
if (dhcp->t0_timeout == 0) {
dhcp->t0_timeout = 1;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease*1000));
}
/* temporary DHCP lease? */
if (dhcp->offered_t1_renew != 0xffffffffUL) {
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
if (timeout > 0xffff) {
timeout = 0xffff;
}
dhcp->t1_timeout = (u16_t)timeout;
if (dhcp->t1_timeout == 0) {
dhcp->t1_timeout = 1;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000));
dhcp->t1_renew_time = dhcp->t1_timeout;
}
/* set renewal period timer */
if (dhcp->offered_t2_rebind != 0xffffffffUL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
if (timeout > 0xffff) {
timeout = 0xffff;
}
dhcp->t2_timeout = (u16_t)timeout;
if (dhcp->t2_timeout == 0) {
dhcp->t2_timeout = 1;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000));
dhcp->t2_rebind_time = dhcp->t2_timeout;
}
/* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
dhcp->t1_timeout = 0;
}
if (dhcp->subnet_mask_given) {
/* copy offered network mask */
ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
} else {
/* subnet mask not given, choose a safe subnet mask given the network class */
u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
if (first_octet <= 127) {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
} else if (first_octet >= 192) {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
} else {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
}
}
ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
/* gateway address not given? */
if (ip4_addr_isany_val(gw_addr)) {
/* copy network address */
ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
/* use first host address on network as gateway */
ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
}
#if LWIP_DHCP_AUTOIP_COOP
if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
/* interface is used by routing now that an address is set */
/* netif is now bound to DHCP leased address */
dhcp_set_state(dhcp, DHCP_STATE_BOUND);
}
/**
* Renew an existing DHCP lease at the involved DHCP server.
*
* @param netif network interface which must renew its lease
*/
err_t
dhcp_renew(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
#if LWIP_NETIF_HOSTNAME
dhcp_option_hostname(dhcp, netif);
#endif /* LWIP_NETIF_HOSTNAME */
/* append DHCP message trailer */
dhcp_option_trailer(dhcp);
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
udp_sendto_if(dhcp->pcb, dhcp->p_out, &dhcp->server_ip_addr, DHCP_SERVER_PORT, netif);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
/* back-off on retries, but to a maximum of 20 seconds */
msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
/**
* Rebind with a DHCP server for an existing DHCP lease.
*
* @param netif network interface which must rebind with a DHCP server
*/
static err_t
dhcp_rebind(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(dhcp, DHCP_MAX_MSG_LEN(netif));
#if LWIP_NETIF_HOSTNAME
dhcp_option_hostname(dhcp, netif);
#endif /* LWIP_NETIF_HOSTNAME */
dhcp_option_trailer(dhcp);
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
/* broadcast to server */
udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
/**
* Enter REBOOTING state to verify an existing lease
*
* @param netif network interface which must reboot
*/
static err_t
dhcp_reboot(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_REQUEST);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
dhcp_option_short(dhcp, 576);
dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4);
dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_option_trailer(dhcp);
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
/* broadcast to server */
udp_sendto_if(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT, netif);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
dhcp->tries++;
}
msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000;
dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
return result;
}
/**
* Release a DHCP lease.
*
* @param netif network interface which must release its lease
*/
err_t
dhcp_release(struct netif *netif)
{
struct dhcp *dhcp = netif->dhcp;
err_t result;
ip_addr_t server_ip_addr;
u8_t is_dhcp_supplied_address;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release()\n"));
if (dhcp == NULL) {
return ERR_ARG;
}
ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
is_dhcp_supplied_address = dhcp_supplied_address(netif);
/* idle DHCP client */
dhcp_set_state(dhcp, DHCP_STATE_OFF);
/* clean old DHCP offer */
ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
ip4_addr_set_zero(&dhcp->offered_ip_addr);
ip4_addr_set_zero(&dhcp->offered_sn_mask);
ip4_addr_set_zero(&dhcp->offered_gw_addr);
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
if (!is_dhcp_supplied_address) {
/* don't issue release message when address is not dhcp-assigned */
return ERR_OK;
}
/* create and initialize the DHCP message header */
result = dhcp_create_msg(netif, dhcp, DHCP_RELEASE);
if (result == ERR_OK) {
dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4);
dhcp_option_long(dhcp, ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
dhcp_option_trailer(dhcp);
pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len);
udp_sendto_if(dhcp->pcb, dhcp->p_out, &server_ip_addr, DHCP_SERVER_PORT, netif);
dhcp_delete_msg(dhcp);
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_STATE_OFF\n"));
} else {
/* sending release failed, but that's not a problem since the correct behaviour of dhcp does not rely on release */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
}
/* remove IP address from interface (prevents routing from selecting this interface) */
netif_set_addr(netif, IP4_ADDR_ANY, IP4_ADDR_ANY, IP4_ADDR_ANY);
return result;
}
/**
* Remove the DHCP client from the interface.
*
* @param netif The network interface to stop DHCP on
*/
void
dhcp_stop(struct netif *netif)
{
struct dhcp *dhcp;
LWIP_ERROR("dhcp_stop: netif != NULL", (netif != NULL), return;);
dhcp = netif->dhcp;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_stop()\n"));
/* netif is DHCP configured? */
if (dhcp != NULL) {
#if LWIP_DHCP_AUTOIP_COOP
if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) {
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
if (dhcp->pcb != NULL) {
udp_remove(dhcp->pcb);
dhcp->pcb = NULL;
}
LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL);
dhcp_set_state(dhcp, DHCP_STATE_OFF);
}
}
/*
* Set the DHCP state of a DHCP client.
*
* If the state changed, reset the number of tries.
*/
static void
dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
{
if (new_state != dhcp->state) {
dhcp->state = new_state;
dhcp->tries = 0;
dhcp->request_timeout = 0;
}
}
/*
* Concatenate an option type and length field to the outgoing
* DHCP message.
*
*/
static void
dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len)
{
LWIP_ASSERT("dhcp_option: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
dhcp->msg_out->options[dhcp->options_out_len++] = option_type;
dhcp->msg_out->options[dhcp->options_out_len++] = option_len;
}
/*
* Concatenate a single byte to the outgoing DHCP message.
*
*/
static void
dhcp_option_byte(struct dhcp *dhcp, u8_t value)
{
LWIP_ASSERT("dhcp_option_byte: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN);
dhcp->msg_out->options[dhcp->options_out_len++] = value;
}
static void
dhcp_option_short(struct dhcp *dhcp, u16_t value)
{
LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2U <= DHCP_OPTIONS_LEN);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t) (value & 0x00ffU);
}
static void
dhcp_option_long(struct dhcp *dhcp, u32_t value)
{
LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4U <= DHCP_OPTIONS_LEN);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
dhcp->msg_out->options[dhcp->options_out_len++] = (u8_t)((value & 0x000000ffUL));
}
#if LWIP_NETIF_HOSTNAME
static void
dhcp_option_hostname(struct dhcp *dhcp, struct netif *netif)
{
if (netif->hostname != NULL) {
size_t namelen = strlen(netif->hostname);
if (namelen > 0) {
u8_t len;
const char *p = netif->hostname;
/* Shrink len to available bytes (need 2 bytes for OPTION_HOSTNAME
and 1 byte for trailer) */
size_t available = DHCP_OPTIONS_LEN - dhcp->options_out_len - 3;
LWIP_ASSERT("DHCP: hostname is too long!", namelen <= available);
len = LWIP_MIN(namelen, available);
dhcp_option(dhcp, DHCP_OPTION_HOSTNAME, len);
while (len--) {
dhcp_option_byte(dhcp, *p++);
}
}
}
}
#endif /* LWIP_NETIF_HOSTNAME */
/**
* Extract the DHCP message and the DHCP options.
*
* Extract the DHCP message and the DHCP options, each into a contiguous
* piece of memory. As a DHCP message is variable sized by its options,
* and also allows overriding some fields for options, the easy approach
* is to first unfold the options into a contiguous piece of memory, and
* use that further on.
*
*/
static err_t
dhcp_parse_reply(struct dhcp *dhcp, struct pbuf *p)
{
u8_t *options;
u16_t offset;
u16_t offset_max;
u16_t options_idx;
u16_t options_idx_max;
struct pbuf *q;
int parse_file_as_options = 0;
int parse_sname_as_options = 0;
/* clear received options */
dhcp_clear_all_options(dhcp);
/* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
if (p->len < DHCP_SNAME_OFS) {
return ERR_BUF;
}
dhcp->msg_in = (struct dhcp_msg *)p->payload;
#if LWIP_DHCP_BOOTP_FILE
/* clear boot file name */
dhcp->boot_file_name[0] = 0;
#endif /* LWIP_DHCP_BOOTP_FILE */
/* parse options */
/* start with options field */
options_idx = DHCP_OPTIONS_OFS;
/* parse options to the end of the received packet */
options_idx_max = p->tot_len;
again:
q = p;
while ((q != NULL) && (options_idx >= q->len)) {
options_idx -= q->len;
options_idx_max -= q->len;
q = q->next;
}
if (q == NULL) {
return ERR_BUF;
}
offset = options_idx;
offset_max = options_idx_max;
options = (u8_t*)q->payload;
/* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
while ((q != NULL) && (options[offset] != DHCP_OPTION_END) && (offset < offset_max)) {
u8_t op = options[offset];
u8_t len;
u8_t decode_len = 0;
int decode_idx = -1;
u16_t val_offset = offset + 2;
/* len byte might be in the next pbuf */
if (offset + 1 < q->len) {
len = options[offset + 1];
} else {
len = (q->next != NULL ? ((u8_t*)q->next->payload)[0] : 0);
}
/* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
decode_len = len;
switch(op) {
/* case(DHCP_OPTION_END): handled above */
case(DHCP_OPTION_PAD):
/* special option: no len encoded */
decode_len = len = 0;
/* will be increased below */
offset--;
break;
case(DHCP_OPTION_SUBNET_MASK):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
break;
case(DHCP_OPTION_ROUTER):
decode_len = 4; /* only copy the first given router */
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_ROUTER;
break;
case(DHCP_OPTION_DNS_SERVER):
/* special case: there might be more than one server */
LWIP_ERROR("len % 4 == 0", len % 4 == 0, return ERR_VAL;);
/* limit number of DNS servers */
decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS);
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
break;
case(DHCP_OPTION_LEASE_TIME):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
break;
#if LWIP_DHCP_GET_NTP_SRV
case(DHCP_OPTION_NTP):
/* special case: there might be more than one server */
LWIP_ERROR("len % 4 == 0", len % 4 == 0, return ERR_VAL;);
/* limit number of NTP servers */
decode_len = LWIP_MIN(len, 4 * LWIP_DHCP_MAX_NTP_SERVERS);
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
break;
#endif /* LWIP_DHCP_GET_NTP_SRV*/
case(DHCP_OPTION_OVERLOAD):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_OVERLOAD;
break;
case(DHCP_OPTION_MESSAGE_TYPE):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
break;
case(DHCP_OPTION_SERVER_ID):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_SERVER_ID;
break;
case(DHCP_OPTION_T1):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_T1;
break;
case(DHCP_OPTION_T2):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_T2;
break;
default:
decode_len = 0;
LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", op));
break;
}
offset += len + 2;
if (decode_len > 0) {
u32_t value = 0;
u16_t copy_len;
decode_next:
LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
if (!dhcp_option_given(dhcp, decode_idx)) {
copy_len = LWIP_MIN(decode_len, 4);
pbuf_copy_partial(q, &value, copy_len, val_offset);
if (decode_len > 4) {
/* decode more than one u32_t */
LWIP_ERROR("decode_len % 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
dhcp_got_option(dhcp, decode_idx);
dhcp_set_option_value(dhcp, decode_idx, htonl(value));
decode_len -= 4;
val_offset += 4;
decode_idx++;
goto decode_next;
} else if (decode_len == 4) {
value = ntohl(value);
} else {
LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
value = ((u8_t*)&value)[0];
}
dhcp_got_option(dhcp, decode_idx);
dhcp_set_option_value(dhcp, decode_idx, value);
}
}
if (offset >= q->len) {
offset -= q->len;
offset_max -= q->len;
if ((offset < offset_max) && offset_max) {
q = q->next;
LWIP_ASSERT("next pbuf was null", q);
options = (u8_t*)q->payload;
} else {
/* We've run out of bytes, probably no end marker. Don't proceed. */
break;
}
}
}
/* is this an overloaded message? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
if (overload == DHCP_OVERLOAD_FILE) {
parse_file_as_options = 1;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME) {
parse_sname_as_options = 1;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
parse_sname_as_options = 1;
parse_file_as_options = 1;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
}
#if LWIP_DHCP_BOOTP_FILE
if (!parse_file_as_options) {
/* only do this for ACK messages */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) &&
(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK))
/* copy bootp file name, don't care for sname (server hostname) */
pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS);
/* make sure the string is really NULL-terminated */
dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
}
#endif /* LWIP_DHCP_BOOTP_FILE */
}
if (parse_file_as_options) {
/* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
parse_file_as_options = 0;
options_idx = DHCP_FILE_OFS;
options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
goto again;
} else if (parse_sname_as_options) {
parse_sname_as_options = 0;
options_idx = DHCP_SNAME_OFS;
options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
goto again;
}
return ERR_OK;
}
/**
* If an incoming DHCP message is in response to us, then trigger the state machine
*/
static void
dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
{
struct netif *netif = (struct netif *)arg;
struct dhcp *dhcp = netif->dhcp;
struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
u8_t msg_type;
u8_t i;
#if LWIP_IPV6
LWIP_ASSERT("invalid server address type", !IP_IS_V6(addr));
#endif /* LWIP_IPV6 */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p,
ip4_addr1_16(ip_2_ip4(addr)), ip4_addr2_16(ip_2_ip4(addr)), ip4_addr3_16(ip_2_ip4(addr)), ip4_addr4_16(ip_2_ip4(addr)), port));
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len));
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len));
/* prevent warnings about unused arguments */
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(addr);
LWIP_UNUSED_ARG(port);
LWIP_ASSERT("reply wasn't freed", dhcp->msg_in == NULL);
if (p->len < DHCP_MIN_REPLY_LEN) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
goto free_pbuf_and_return;
}
if (reply_msg->op != DHCP_BOOTREPLY) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
goto free_pbuf_and_return;
}
/* iterate through hardware address and match against DHCP message */
for (i = 0; i < netif->hwaddr_len && i < NETIF_MAX_HWADDR_LEN && i < DHCP_CHADDR_LEN; i++) {
if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n",
(u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
goto free_pbuf_and_return;
}
}
/* match transaction ID against what we expected */
if (ntohl(reply_msg->xid) != dhcp->xid) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n",ntohl(reply_msg->xid),dhcp->xid));
goto free_pbuf_and_return;
}
/* option fields could be unfold? */
if (dhcp_parse_reply(dhcp, p) != ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("problem unfolding DHCP message - too short on memory?\n"));
goto free_pbuf_and_return;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
/* obtain pointer to DHCP message type */
if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
goto free_pbuf_and_return;
}
/* read DHCP message type */
msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
/* message type is DHCP ACK? */
if (msg_type == DHCP_ACK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
/* in requesting state? */
if (dhcp->state == DHCP_STATE_REQUESTING) {
dhcp_handle_ack(netif);
#if DHCP_DOES_ARP_CHECK
/* check if the acknowledged lease address is already in use */
dhcp_check(netif);
#else
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
#endif
}
/* already bound to the given lease address? */
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
(dhcp->state == DHCP_STATE_RENEWING)) {
dhcp_bind(netif);
}
}
/* received a DHCP_NAK in appropriate state? */
else if ((msg_type == DHCP_NAK) &&
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
dhcp_handle_nak(netif);
}
/* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
dhcp->request_timeout = 0;
/* remember offered lease */
dhcp_handle_offer(netif);
}
free_pbuf_and_return:
dhcp->msg_in = NULL;
pbuf_free(p);
}
/**
* Create a DHCP request, fill in common headers
*
* @param netif the netif under DHCP control
* @param dhcp dhcp control struct
* @param message_type message type of the request
*/
static err_t
dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type)
{
u16_t i;
#ifndef DHCP_GLOBAL_XID
/** default global transaction identifier starting value (easy to match
* with a packet analyser). We simply increment for each new request.
* Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one
* at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
static u32_t xid;
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
static u32_t xid = 0xABCD0000;
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
#else
if (!xid_initialised) {
xid = DHCP_GLOBAL_XID;
xid_initialised = !xid_initialised;
}
#endif
LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return ERR_ARG;);
LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
LWIP_ASSERT("dhcp_create_msg: dhcp->p_out == NULL", dhcp->p_out == NULL);
LWIP_ASSERT("dhcp_create_msg: dhcp->msg_out == NULL", dhcp->msg_out == NULL);
dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
if (dhcp->p_out == NULL) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_create_msg(): could not allocate pbuf\n"));
return ERR_MEM;
}
LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
(dhcp->p_out->len >= sizeof(struct dhcp_msg)));
/* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
if (message_type != DHCP_REQUEST) {
/* reuse transaction identifier in retransmissions */
if (dhcp->tries == 0) {
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
xid = LWIP_RAND();
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
xid++;
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
}
dhcp->xid = xid;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
("transaction id xid(%"X32_F")\n", xid));
dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload;
dhcp->msg_out->op = DHCP_BOOTREQUEST;
/* TODO: make link layer independent */
dhcp->msg_out->htype = DHCP_HTYPE_ETH;
dhcp->msg_out->hlen = netif->hwaddr_len;
dhcp->msg_out->hops = 0;
dhcp->msg_out->xid = htonl(dhcp->xid);
dhcp->msg_out->secs = 0;
/* we don't need the broadcast flag since we can receive unicast traffic
before being fully configured! */
dhcp->msg_out->flags = 0;
ip4_addr_set_zero(&dhcp->msg_out->ciaddr);
/* set ciaddr to netif->ip_addr based on message_type and state */
if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
((dhcp->state== DHCP_STATE_RENEWING) || dhcp->state== DHCP_STATE_REBINDING))) {
ip4_addr_copy(dhcp->msg_out->ciaddr, *netif_ip4_addr(netif));
}
ip4_addr_set_zero(&dhcp->msg_out->yiaddr);
ip4_addr_set_zero(&dhcp->msg_out->siaddr);
ip4_addr_set_zero(&dhcp->msg_out->giaddr);
for (i = 0; i < DHCP_CHADDR_LEN; i++) {
/* copy netif hardware address, pad with zeroes */
dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len && i < NETIF_MAX_HWADDR_LEN) ? netif->hwaddr[i] : 0/* pad byte*/;
}
for (i = 0; i < DHCP_SNAME_LEN; i++) {
dhcp->msg_out->sname[i] = 0;
}
for (i = 0; i < DHCP_FILE_LEN; i++) {
dhcp->msg_out->file[i] = 0;
}
dhcp->msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
dhcp->options_out_len = 0;
/* fill options field with an incrementing array (for debugging purposes) */
for (i = 0; i < DHCP_OPTIONS_LEN; i++) {
dhcp->msg_out->options[i] = (u8_t)i; /* for debugging only, no matter if truncated */
}
/* Add option MESSAGE_TYPE */
dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
dhcp_option_byte(dhcp, message_type);
return ERR_OK;
}
/**
* Free previously allocated memory used to send a DHCP request.
*
* @param dhcp the dhcp struct to free the request from
*/
static void
dhcp_delete_msg(struct dhcp *dhcp)
{
LWIP_ERROR("dhcp_delete_msg: dhcp != NULL", (dhcp != NULL), return;);
LWIP_ASSERT("dhcp_delete_msg: dhcp->p_out != NULL", dhcp->p_out != NULL);
LWIP_ASSERT("dhcp_delete_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL);
if (dhcp->p_out != NULL) {
pbuf_free(dhcp->p_out);
}
dhcp->p_out = NULL;
dhcp->msg_out = NULL;
}
/**
* Add a DHCP message trailer
*
* Adds the END option to the DHCP message, and if
* necessary, up to three padding bytes.
*
* @param dhcp DHCP state structure
*/
static void
dhcp_option_trailer(struct dhcp *dhcp)
{
LWIP_ERROR("dhcp_option_trailer: dhcp != NULL", (dhcp != NULL), return;);
LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL);
LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN);
dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END;
/* packet is too small, or not 4 byte aligned? */
while (((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) &&
(dhcp->options_out_len < DHCP_OPTIONS_LEN)) {
/* add a fill/padding byte */
dhcp->msg_out->options[dhcp->options_out_len++] = 0;
}
}
/** check if DHCP supplied netif->ip_addr
*
* @param netif the netif to check
* @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
* 0 otherwise
*/
u8_t
dhcp_supplied_address(struct netif *netif)
{
if ((netif != NULL) && (netif->dhcp != NULL)) {
if ((netif->dhcp->state == DHCP_STATE_BOUND) ||
(netif->dhcp->state == DHCP_STATE_RENEWING)) {
return 1;
}
}
return 0;
}
#endif /* LWIP_IPV4 && LWIP_DHCP */
| [
"b04209032@ntu.edu.tw"
] | b04209032@ntu.edu.tw |
7b49f0479ee0b4d6218eb39802fbf7f15b2a4ab7 | 42af5cdbde2fa4ec4c6f34fbd74b01ea7973235e | /task_4/Task4.c | 0afbce385f903699a58c7612d5e98d14a4f9396c | [] | no_license | lyutov2208/3_sem | b85cd628165b506836fb273c51ef18c9a86d5839 | 8d75f8a188f20c93dd4a31221a09da3886b750a3 | refs/heads/master | 2020-09-20T12:56:18.482221 | 2019-12-20T22:33:59 | 2019-12-20T22:33:59 | 224,486,242 | 0 | 0 | null | 2019-11-27T17:45:26 | 2019-11-27T17:45:25 | null | UTF-8 | C | false | false | 2,127 | c | #include <pthread.h>
#include <stdio.h>
#include <stdlib.h>
#include <malloc.h>
#include <time.h>
struct rectangle
{
double a;
double b;
double count;
};
const long int amount = 5000000;
double S = 0; //
double func(double x)
{
return x*x;
}
void *calculate(void * annoy)
{
struct rectangle * limit = (struct rectangle *)annoy;
int i;
long int hit = 0;
double x, y, dx, M=0;
dx = (double)(limit->b - limit->a)/limit->count;
for(i=0; i <= limit->count; i++)
{
if(func(limit->a+dx*i)>M)
M = func(limit->a+dx*i);
}
struct drand48_data data;
srand48_r (rand(), &data);
for(i=0; i < limit->count; i++)
{
double r1, r2;
drand48_r(data, &r1);
drand48_r(data, &r2);
x = limit->a + (double)(limit->b - limit->a)*r1;
y = (double)M*r2;
if(y<func(x))
hit++;
}
S += (limit->b - limit->a)*M*((double)hit/limit->count);
return NULL;
}
int main()
{
int n, i, result;
double lk, rk, dl;
printf("Amount of threads?\n");
scanf("%d", &n);
printf("Left end of section?\n");
scanf("%lf", &lk);
printf("Right end of section?\n");
scanf("%lf", &rk);
pthread_t * thid = (pthread_t *)malloc(n*sizeof(pthread_t ));
struct rectangle * rects = (struct rectangle *)malloc(n*sizeof(struct rectangle));
dl = (double)(rk-lk)/n;
for(i = 0; i<n; i++)
{
rects[i].a = lk + dl*i;
rects[i].b = rects[i].a + dl;
rects[i].count = amount / n;
}
clock_t start = clock();
for( i = 0; i<n; i++)
{
result = pthread_create( thid + i, (pthread_attr_t *)NULL, calculate, rects + i);
if(result != 0){
printf ("Error on thread create, return value = %d\n", result);
exit(-1);
}
}
for( i = 0; i<n; i++)
{
pthread_join(thid[i], (void **)NULL);
}
printf("Time: %.3f ms\n", 1000*((double)clock()-start)/((double)CLOCKS_PER_SEC));
printf("Square is %lf\n", S);
free(thid);
free(rects);
return 0;
}
| [
"noreply@github.com"
] | lyutov2208.noreply@github.com |
43ac4beeb1062cc7cac811fc05db35764ed8bc64 | 468613e278d19408e70ee9c38762c1e054642513 | /FiBY_base/Anarchy/ngb.c | e1e0294a9f663b2aa7b1d17496cd0fa4065ce56b | [] | no_license | bpfm/FiBYHydroAdaption | dae121180b083f3a7b84201ca78bb76bbe05eddb | 54075e0319fa5645f608db5ac644f22eb9e94baa | refs/heads/master | 2021-08-28T06:16:50.880891 | 2017-12-11T10:50:36 | 2017-12-11T10:50:36 | 113,340,516 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 16,999 | c | #include <mpi.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <time.h>
#include "allvars.h"
#include "proto.h"
/*! \file ngb.c
* \brief neighbour search by means of the tree
*
* This file contains routines for neighbour finding. We use the
* gravity-tree and a range-searching technique to find neighbours.
*/
/*! This routine finds all neighbours `j' that can interact with the
* particle `i' in the communication buffer.
*
* Note that an interaction can take place if
* \f$ r_{ij} < h_i \f$ OR if \f$ r_{ij} < h_j \f$.
*
* In the range-search this is taken into account, i.e. it is guaranteed that
* all particles are found that fulfil this condition, including the (more
* difficult) second part of it. For this purpose, each node knows the
* maximum h occuring among the particles it represents.
*/
int ngb_treefind_pairs(MyDouble searchcenter[3], MyFloat hsml, int target, int *startnode,
int mode, int *nexport, int *nsend_local)
{
int no, p, numngb, task, nexport_save;
MyDouble dist, dx, dy, dz, dmax1, dmax2;
struct NODE *current;
#ifdef PERIODIC
MyDouble xtmp;
#endif
nexport_save = *nexport;
numngb = 0;
no = *startnode;
while(no >= 0)
{
if(no < All.MaxPart) /* single particle */
{
p = no;
no = Nextnode[no];
if(P[p].Type > 0)
continue;
if(P[p].Ti_current != All.Ti_Current)
drift_particle(p, All.Ti_Current);
dist = DMAX(PPP[p].Hsml, hsml);
dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]);
if(dz > dist)
continue;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
Ngblist[numngb++] = p; /* Note: unlike in previous versions of the code, the buffer
can hold up to all particles */
}
else
{
if(no >= All.MaxPart + MaxNodes) /* pseudo particle */
{
if(mode == 1)
endrun(23131);
if(Exportflag[task = DomainTask[no - (All.MaxPart + MaxNodes)]] != target)
{
Exportflag[task] = target;
Exportnodecount[task] = NODELISTLENGTH;
}
if(Exportnodecount[task] == NODELISTLENGTH)
{
if(*nexport >= All.BunchSize)
{
*nexport = nexport_save;
if(nexport_save == 0)
endrun(13003); /* in this case, the buffer is too small to process even a single particle */
for(task = 0; task < NTask; task++)
nsend_local[task] = 0;
for(no = 0; no < nexport_save; no++)
nsend_local[DataIndexTable[no].Task]++;
return -1;
}
Exportnodecount[task] = 0;
Exportindex[task] = *nexport;
DataIndexTable[*nexport].Task = task;
DataIndexTable[*nexport].Index = target;
DataIndexTable[*nexport].IndexGet = *nexport;
*nexport = *nexport + 1;
nsend_local[task]++;
}
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]++] =
DomainNodeIndex[no - (All.MaxPart + MaxNodes)];
if(Exportnodecount[task] < NODELISTLENGTH)
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]] = -1;
no = Nextnode[no - MaxNodes];
continue;
}
current = &Nodes[no];
if(mode == 1)
{
if(current->u.d.bitflags & (1 << BITFLAG_TOPLEVEL)) /* we reached a top-level node again, which means that we are done with the branch */
{
*startnode = -1;
return numngb;
}
}
if(current->Ti_current != All.Ti_Current)
force_drift_node(no, All.Ti_Current);
dist = DMAX(Extnodes[no].hmax, hsml) + 0.5 * current->len;
no = current->u.d.sibling; /* in case the node can be discarded */
dx = NGB_PERIODIC_LONG_X(current->center[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(current->center[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(current->center[2] - searchcenter[2]);
if(dz > dist)
continue;
/* now test against the minimal sphere enclosing everything */
dist += FACT1 * current->len;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
no = current->u.d.nextnode; /* ok, we need to open the node */
}
}
*startnode = -1;
return numngb;
}
/*! This function returns neighbours with distance <= hsml and returns them in
* Ngblist. Actually, particles in a box of half side length hsml are
* returned, i.e. the reduction to a sphere still needs to be done in the
* calling routine.
*/
int ngb_treefind_variable(MyDouble searchcenter[3], MyFloat hsml, int target, int *startnode, int mode,
int *nexport, int *nsend_local)
{
int numngb, no, p, task, nexport_save;
struct NODE *current;
MyDouble dx, dy, dz, dist;
#ifdef PERIODIC
MyDouble xtmp;
#endif
nexport_save = *nexport;
numngb = 0;
no = *startnode;
while(no >= 0)
{
if(no < All.MaxPart) /* single particle */
{
p = no;
no = Nextnode[no];
if(P[p].Type > 0)
continue;
if(P[p].Ti_current != All.Ti_Current)
drift_particle(p, All.Ti_Current);
dist = hsml;
dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]);
if(dz > dist)
continue;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
Ngblist[numngb++] = p;
}
else
{
if(no >= All.MaxPart + MaxNodes) /* pseudo particle */
{
if(mode == 1)
endrun(12312);
if(target >= 0) /* if no target is given, export will not occur */
{
if(Exportflag[task = DomainTask[no - (All.MaxPart + MaxNodes)]] != target)
{
Exportflag[task] = target;
Exportnodecount[task] = NODELISTLENGTH;
}
if(Exportnodecount[task] == NODELISTLENGTH)
{
if(*nexport >= All.BunchSize)
{
*nexport = nexport_save;
if(nexport_save == 0)
endrun(13004); /* in this case, the buffer is too small to process even a single particle */
for(task = 0; task < NTask; task++)
nsend_local[task] = 0;
for(no = 0; no < nexport_save; no++)
nsend_local[DataIndexTable[no].Task]++;
return -1;
}
Exportnodecount[task] = 0;
Exportindex[task] = *nexport;
DataIndexTable[*nexport].Task = task;
DataIndexTable[*nexport].Index = target;
DataIndexTable[*nexport].IndexGet = *nexport;
*nexport = *nexport + 1;
nsend_local[task]++;
}
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]++] =
DomainNodeIndex[no - (All.MaxPart + MaxNodes)];
if(Exportnodecount[task] < NODELISTLENGTH)
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]] = -1;
}
no = Nextnode[no - MaxNodes];
continue;
}
current = &Nodes[no];
if(mode == 1)
{
if(current->u.d.bitflags & (1 << BITFLAG_TOPLEVEL)) /* we reached a top-level node again, which means that we are done with the branch */
{
*startnode = -1;
return numngb;
}
}
if(current->Ti_current != All.Ti_Current)
force_drift_node(no, All.Ti_Current);
no = current->u.d.sibling; /* in case the node can be discarded */
dist = hsml + 0.5 * current->len;;
dx = NGB_PERIODIC_LONG_X(current->center[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(current->center[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(current->center[2] - searchcenter[2]);
if(dz > dist)
continue;
/* now test against the minimal sphere enclosing everything */
dist += FACT1 * current->len;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
no = current->u.d.nextnode; /* ok, we need to open the node */
}
}
*startnode = -1;
return numngb;
}
/*! Allocates memory for the neighbour list buffer.
*/
void ngb_init(void)
{
}
/*! This function constructs the neighbour tree. To this end, we actually need
* to construct the gravitational tree, because we use it now for the
* neighbour search.
*/
void ngb_treebuild(void)
{
if(ThisTask == 0)
printf("Begin Ngb-tree construction.\n");
force_treebuild(NumPart, NULL);
if(ThisTask == 0)
printf("Ngb-Tree contruction finished \n");
}
#ifdef FOF
int ngb_treefind_fof_primary(MyDouble searchcenter[3], MyFloat hsml, int target, int *startnode, int mode,
int *nexport, int *nsend_local)
{
int numngb, no, p, task, nexport_save;
struct NODE *current;
MyDouble dx, dy, dz, dist, r2;
#define FACT2 0.86602540
#ifdef PERIODIC
MyDouble xtmp;
#endif
nexport_save = *nexport;
numngb = 0;
no = *startnode;
while(no >= 0)
{
if(no < All.MaxPart) /* single particle */
{
p = no;
no = Nextnode[no];
if(!((1 << P[p].Type) & (FOF_PRIMARY_LINK_TYPES)))
continue;
if(mode == 0)
continue;
dist = hsml;
dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]);
if(dz > dist)
continue;
if(dx * dx + dy * dy + dz * dz > dist * dist)
continue;
Ngblist[numngb++] = p;
}
else
{
if(no >= All.MaxPart + MaxNodes) /* pseudo particle */
{
if(mode == 1)
endrun(12312);
if(mode == 0)
{
if(Exportflag[task = DomainTask[no - (All.MaxPart + MaxNodes)]] != target)
{
Exportflag[task] = target;
Exportnodecount[task] = NODELISTLENGTH;
}
if(Exportnodecount[task] == NODELISTLENGTH)
{
if(*nexport >= All.BunchSize)
{
*nexport = nexport_save;
if(nexport_save == 0)
endrun(13005); /* in this case, the buffer is too small to process even a single particle */
for(task = 0; task < NTask; task++)
nsend_local[task] = 0;
for(no = 0; no < nexport_save; no++)
nsend_local[DataIndexTable[no].Task]++;
return -1;
}
Exportnodecount[task] = 0;
Exportindex[task] = *nexport;
DataIndexTable[*nexport].Task = task;
DataIndexTable[*nexport].Index = target;
DataIndexTable[*nexport].IndexGet = *nexport;
*nexport = *nexport + 1;
nsend_local[task]++;
}
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]++] =
DomainNodeIndex[no - (All.MaxPart + MaxNodes)];
if(Exportnodecount[task] < NODELISTLENGTH)
DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]] = -1;
}
if(mode == -1)
{
*nexport = 1;
}
no = Nextnode[no - MaxNodes];
continue;
}
current = &Nodes[no];
if(mode == 1)
{
if(current->u.d.bitflags & (1 << BITFLAG_TOPLEVEL)) /* we reached a top-level node again, which means that we are done with the branch */
{
*startnode = -1;
return numngb;
}
}
no = current->u.d.sibling; /* in case the node can be discarded */
dist = hsml + 0.5 * current->len;;
dx = NGB_PERIODIC_LONG_X(current->center[0] - searchcenter[0]);
if(dx > dist)
continue;
dy = NGB_PERIODIC_LONG_Y(current->center[1] - searchcenter[1]);
if(dy > dist)
continue;
dz = NGB_PERIODIC_LONG_Z(current->center[2] - searchcenter[2]);
if(dz > dist)
continue;
/* now test against the minimal sphere enclosing everything */
dist += FACT1 * current->len;
if((r2 = (dx * dx + dy * dy + dz * dz)) > dist * dist)
continue;
if((current->u.d.bitflags & ((1 << BITFLAG_TOPLEVEL) + (1 << BITFLAG_DEPENDS_ON_LOCAL_MASS))) == 0) /* only use fully local nodes */
{
/* test whether the node is contained within the sphere */
dist = hsml - FACT2 * current->len;
if(dist > 0)
if(r2 < dist * dist)
{
if(current->u.d.bitflags & (1 << BITFLAG_INSIDE_LINKINGLENGTH)) /* already flagged */
{
/* sufficient to return only one particle inside this cell */
p = current->u.d.nextnode;
while(p >= 0)
{
if(p < All.MaxPart)
{
if(((1 << P[p].Type) & (FOF_PRIMARY_LINK_TYPES)))
{
dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]);
dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]);
dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]);
if(dx * dx + dy * dy + dz * dz > hsml * hsml)
break;
Ngblist[numngb++] = p;
break;
}
p = Nextnode[p];
}
else if(p >= All.MaxPart + MaxNodes)
p = Nextnode[p - MaxNodes];
else
p = Nodes[p].u.d.nextnode;
}
continue;
}
else
{
/* flag it now */
current->u.d.bitflags |= (1 << BITFLAG_INSIDE_LINKINGLENGTH);
}
}
}
no = current->u.d.nextnode; /* ok, we need to open the node */
}
}
*startnode = -1;
return numngb;
}
#endif
/* int ngb_treefind_darkmatter(MyDouble searchcenter[3], MyFloat hsml, int target, int *startnode, int mode, */
/* int *nexport, int *nsend_local) */
/* { */
/* int numngb, no, p, task, nexport_save; */
/* struct NODE *current; */
/* MyDouble dx, dy, dz, dist; */
/* #ifdef PERIODIC */
/* MyDouble xtmp; */
/* #endif */
/* nexport_save = *nexport; */
/* numngb = 0; */
/* no = *startnode; */
/* while(no >= 0) */
/* { */
/* if(no < All.MaxPart) /\* single particle *\/ */
/* { */
/* p = no; */
/* no = Nextnode[no]; */
/* if(P[p].Type != 1) */
/* continue; */
/* if(P[p].Ti_current != All.Ti_Current) */
/* drift_particle(p, All.Ti_Current); */
/* dist = hsml; */
/* dx = NGB_PERIODIC_LONG_X(P[p].Pos[0] - searchcenter[0]); */
/* if(dx > dist) */
/* continue; */
/* dy = NGB_PERIODIC_LONG_Y(P[p].Pos[1] - searchcenter[1]); */
/* if(dy > dist) */
/* continue; */
/* dz = NGB_PERIODIC_LONG_Z(P[p].Pos[2] - searchcenter[2]); */
/* if(dz > dist) */
/* continue; */
/* if(dx * dx + dy * dy + dz * dz > dist * dist) */
/* continue; */
/* Ngblist[numngb++] = p; */
/* } */
/* else */
/* { */
/* if(no >= All.MaxPart + MaxNodes) /\* pseudo particle *\/ */
/* { */
/* if(mode == 1) */
/* endrun(12312); */
/* if(Exportflag[task = DomainTask[no - (All.MaxPart + MaxNodes)]] != target) */
/* { */
/* Exportflag[task] = target; */
/* Exportnodecount[task] = NODELISTLENGTH; */
/* } */
/* if(Exportnodecount[task] == NODELISTLENGTH) */
/* { */
/* if(*nexport >= All.BunchSize) */
/* { */
/* *nexport = nexport_save; */
/* if(nexport_save == 0) */
/* endrun(13005); /\* in this case, the buffer is too small to process even a single particle *\/ */
/* for(task = 0; task < NTask; task++) */
/* nsend_local[task] = 0; */
/* for(no = 0; no < nexport_save; no++) */
/* nsend_local[DataIndexTable[no].Task]++; */
/* return -1; */
/* } */
/* Exportnodecount[task] = 0; */
/* Exportindex[task] = *nexport; */
/* DataIndexTable[*nexport].Task = task; */
/* DataIndexTable[*nexport].Index = target; */
/* DataIndexTable[*nexport].IndexGet = *nexport; */
/* *nexport = *nexport + 1; */
/* nsend_local[task]++; */
/* } */
/* DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]++] = */
/* DomainNodeIndex[no - (All.MaxPart + MaxNodes)]; */
/* if(Exportnodecount[task] < NODELISTLENGTH) */
/* DataNodeList[Exportindex[task]].NodeList[Exportnodecount[task]] = -1; */
/* no = Nextnode[no - MaxNodes]; */
/* continue; */
/* } */
/* current = &Nodes[no]; */
/* if(mode == 1) */
/* { */
/* if(current->u.d.bitflags & (1 << BITFLAG_TOPLEVEL)) /\* we reached a top-level node again, which means that we are done with the branch *\/ */
/* { */
/* *startnode = -1; */
/* return numngb; */
/* } */
/* } */
/* if(current->Ti_current != All.Ti_Current) */
/* force_drift_node(no, All.Ti_Current); */
/* no = current->u.d.sibling; /\* in case the node can be discarded *\/ */
/* dist = hsml + 0.5 * current->len;; */
/* dx = NGB_PERIODIC_LONG_X(current->center[0] - searchcenter[0]); */
/* if(dx > dist) */
/* continue; */
/* dy = NGB_PERIODIC_LONG_Y(current->center[1] - searchcenter[1]); */
/* if(dy > dist) */
/* continue; */
/* dz = NGB_PERIODIC_LONG_Z(current->center[2] - searchcenter[2]); */
/* if(dz > dist) */
/* continue; */
/* /\* now test against the minimal sphere enclosing everything *\/ */
/* dist += FACT1 * current->len; */
/* if(dx * dx + dy * dy + dz * dz > dist * dist) */
/* continue; */
/* no = current->u.d.nextnode; /\* ok, we need to open the node *\/ */
/* } */
/* } */
/* *startnode = -1; */
/* return numngb; */
/* } */
| [
"morton@roe.ac.uk"
] | morton@roe.ac.uk |
5062a559c3c39cc6cec097fc575e89310242f320 | 485741c6f00d939c2a1bc5011d01f5666325b0dd | /uspace/include/types/packet.h | ca39790009255a36926c6a6d2f8e29b546a2f944 | [] | no_license | frankfanslc/ustack | f623881cb6d6327741969758fe2caedd329c68d6 | 7fb7296601c3f92827fa0ae8d24e41e4af71edf6 | refs/heads/master | 2022-02-12T12:03:59.888457 | 2016-10-09T22:09:22 | 2016-10-09T22:09:22 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 1,559 | h | /*
* types/packet.h
*
* Copyright (C) 2012-2013 Peng Jianzhang
*
* Author: Peng Jianzhang
* Email: pengjianzhang@gmail.com
* Time: 2013.2.11
* */
#ifndef _TYPES_PACKET_H
#define _TYPES_PACKET_H
#include "common/types.h"
#include "common/list.h"
#include "types/lf_queue.h"
struct packet
{
struct list_head next; /*link package tDo freelist ... */
u64 phys; /* physical address */
u16 len; /* data length */
u16 size; /* 2k */
u16 protocol_eth; /* protocol at ethhdr */
u8 protocol_ip; /* protocl at iphdr */
u8 family; /* AF_INET, AF_INET6 */
u8 adapter_idx; /* adapter recv this packagyee */
// u8 queue_idx; /* rx queue recv this package */
enum lfq_state lfq_state; /* lfq state */
int id; /* this packet is alloced to a process,ynot changed from init */
struct net_address saddr; /*src address ip:port */
struct net_address daddr; /*dst address ip:port */
int transport_header; /* offset of transport layer header */
int network_header; /* offset of network layer header */
int mac_header; /* offset of mac layer header */
};
struct packet_pool
{
__u64 num;
struct list_head list;
};
struct packet_zone
{
u64 start_all; /* packet memory address */
u64 phys_all; /* physical address of the total packet memory */
__u64 start; //package start
__u64 phys; //physical address of <start>
__u64 size;
__u64 packet_num;
__u16 packet_size; //2k
__u16 packet_offset; //packet info offset from packet data head
int id;
struct packet_pool free_packet_pool;
};
#endif
| [
"pengjianzhang@gmail.com"
] | pengjianzhang@gmail.com |
bc391a76950e58da462fdcc7103ca785e7c12cee | f24bbc3aea1f4926e681d8a1736116d462ec0841 | /ext/leevel/bootstrap/kernel.zep.c | 4b34ed87489ec24c47dbde3aa16591bb07096631 | [
"MIT"
] | permissive | xubingyue/leevel | 61573299eaf23ea0c02ae77dc230d581090f6c75 | 16237d4dc23e5db134ce7e3b08cb5e2ff9c4e123 | refs/heads/master | 2020-04-05T11:05:50.120373 | 2018-11-07T19:12:21 | 2018-11-07T19:12:21 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | true | 11,020 | c |
#ifdef HAVE_CONFIG_H
#include "../../ext_config.h"
#endif
#include <php.h>
#include "../../php_ext.h"
#include "../../ext.h"
#include <Zend/zend_operators.h>
#include <Zend/zend_exceptions.h>
#include <Zend/zend_interfaces.h>
#include "kernel/main.h"
#include "kernel/object.h"
#include "kernel/memory.h"
#include "kernel/fcall.h"
#include "kernel/array.h"
#include "kernel/operators.h"
/**
* 内核执行
*
* @author Xiangmin Liu <635750556@qq.com>
*
* @since 2016.11.18
*
* @version 1.0
*/
ZEPHIR_INIT_CLASS(Leevel_Bootstrap_Kernel) {
ZEPHIR_REGISTER_CLASS(Leevel\\Bootstrap, Kernel, leevel, bootstrap_kernel, leevel_bootstrap_kernel_method_entry, ZEND_ACC_EXPLICIT_ABSTRACT_CLASS);
/**
* 项目
*
* @var \Leevel\Kernel\IProject
*/
zend_declare_property_null(leevel_bootstrap_kernel_ce, SL("project"), ZEND_ACC_PROTECTED TSRMLS_CC);
/**
* 路由
*
* @var \Leevel\Router\IRouter
*/
zend_declare_property_null(leevel_bootstrap_kernel_ce, SL("router"), ZEND_ACC_PROTECTED TSRMLS_CC);
/**
* 项目初始化执行
*
* @var array
*/
zend_declare_property_null(leevel_bootstrap_kernel_ce, SL("bootstraps"), ZEND_ACC_PROTECTED TSRMLS_CC);
leevel_bootstrap_kernel_ce->create_object = zephir_init_properties_Leevel_Bootstrap_Kernel;
zend_class_implements(leevel_bootstrap_kernel_ce TSRMLS_CC, 1, leevel_kernel_ikernel_ce);
return SUCCESS;
}
/**
* 构造函数
*
* @param \Leevel\Kernel\IProject $project
* @param \Leevel\Router\IRouter $router
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, __construct) {
zval *project, project_sub, *router, router_sub;
zval *this_ptr = getThis();
ZVAL_UNDEF(&project_sub);
ZVAL_UNDEF(&router_sub);
zephir_fetch_params(0, 2, 0, &project, &router);
zephir_update_property_zval(this_ptr, SL("project"), project);
zephir_update_property_zval(this_ptr, SL("router"), router);
}
/**
* 响应 HTTP 请求
*
* @param \Leevel\Http\IRequest $request
* @return \Leevel\Http\IResponse
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, handle) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub, response, e, fatalException, _0, _1$$6, _2$$6, _3$$6, _4$$6, _5$$6, _6$$6;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&response);
ZVAL_UNDEF(&e);
ZVAL_UNDEF(&fatalException);
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_1$$6);
ZVAL_UNDEF(&_2$$6);
ZVAL_UNDEF(&_3$$6);
ZVAL_UNDEF(&_4$$6);
ZVAL_UNDEF(&_5$$6);
ZVAL_UNDEF(&_6$$6);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 1, 0, &request);
/* try_start_1: */
ZEPHIR_CALL_METHOD(NULL, this_ptr, "registerbaseservice", NULL, 0, request);
zephir_check_call_status_or_jump(try_end_1);
ZEPHIR_CALL_METHOD(NULL, this_ptr, "bootstrap", NULL, 0);
zephir_check_call_status_or_jump(try_end_1);
ZEPHIR_CALL_METHOD(&response, this_ptr, "getresponsewithrequest", NULL, 0, request);
zephir_check_call_status_or_jump(try_end_1);
ZEPHIR_CALL_METHOD(NULL, this_ptr, "middlewareterminate", NULL, 0, request, &response);
zephir_check_call_status_or_jump(try_end_1);
try_end_1:
if (EG(exception)) {
ZEPHIR_INIT_VAR(&_0);
ZVAL_OBJ(&_0, EG(exception));
Z_ADDREF_P(&_0);
if (zephir_instance_of_ev(&_0, zend_exception_get_default(TSRMLS_C) TSRMLS_CC)) {
zend_clear_exception(TSRMLS_C);
ZEPHIR_CPY_WRT(&e, &_0);
ZEPHIR_CALL_METHOD(NULL, this_ptr, "reportexception", NULL, 0, &e);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&response, this_ptr, "renderexception", NULL, 0, request, &e);
zephir_check_call_status();
} else {
if (zephir_is_instance_of(&_0, SL("Throwable") TSRMLS_CC)) {
zend_clear_exception(TSRMLS_C);
ZEPHIR_CPY_WRT(&e, &_0);
ZEPHIR_INIT_VAR(&fatalException);
object_init_ex(&fatalException, zephir_get_internal_ce(SL("errorexception")));
ZEPHIR_CALL_METHOD(&_1$$6, &e, "getmessage", NULL, 0);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&_2$$6, &e, "getcode", NULL, 0);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&_3$$6, &e, "getfile", NULL, 0);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&_4$$6, &e, "getline", NULL, 0);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&_5$$6, &e, "getprevious", NULL, 0);
zephir_check_call_status();
ZVAL_LONG(&_6$$6, 1);
ZEPHIR_CALL_METHOD(NULL, &fatalException, "__construct", NULL, 67, &_1$$6, &_2$$6, &_6$$6, &_3$$6, &_4$$6, &_5$$6);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(NULL, this_ptr, "reportexception", NULL, 0, &fatalException);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(&response, this_ptr, "renderexception", NULL, 0, request, &fatalException);
zephir_check_call_status();
}
}
}
RETURN_CCTOR(&response);
}
/**
* 返回运行处理器
*
* @return \Leevel\Bootstrap\Runtime\IRuntime
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, getRuntime) {
zval _0, _1;
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *this_ptr = getThis();
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_1);
ZEPHIR_MM_GROW();
zephir_read_property(&_0, this_ptr, SL("project"), PH_NOISY_CC | PH_READONLY);
ZEPHIR_INIT_VAR(&_1);
ZVAL_STRING(&_1, "Leevel\\Kernel\\IRuntime");
ZEPHIR_RETURN_CALL_METHOD(&_0, "make", NULL, 0, &_1);
zephir_check_call_status();
RETURN_MM();
}
/**
* 执行结束
*
* @param \Leevel\Http\IRequest $request
* @param \Leevel\Http\IResponse $response
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, terminate) {
zval *request, request_sub, *response, response_sub;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&response_sub);
zephir_fetch_params(0, 2, 0, &request, &response);
}
/**
* 返回项目
*
* @return \Leevel\Kernel\IProject
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, getProject) {
zval *this_ptr = getThis();
RETURN_MEMBER(getThis(), "project");
}
/**
* 注册基础服务
*
* @param \Leevel\Http\IRequest $request
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, registerBaseService) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub, _0, _1;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_1);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 1, 0, &request);
zephir_read_property(&_0, this_ptr, SL("project"), PH_NOISY_CC | PH_READONLY);
ZEPHIR_INIT_VAR(&_1);
ZVAL_STRING(&_1, "request");
ZEPHIR_CALL_METHOD(NULL, &_0, "instance", NULL, 0, &_1, request);
zephir_check_call_status();
ZEPHIR_MM_RESTORE();
}
/**
* 根据请求返回响应
*
* @param \Leevel\Http\IRequest $request
* @return \Leevel\Http\IResponse
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, getResponseWithRequest) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 1, 0, &request);
ZEPHIR_RETURN_CALL_METHOD(this_ptr, "dispatchrouter", NULL, 0, request);
zephir_check_call_status();
RETURN_MM();
}
/**
* 路由调度
*
* @param \Leevel\Http\IRequest $request
* @return \Leevel\Http\IResponse
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, dispatchRouter) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub, _0;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&_0);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 1, 0, &request);
zephir_read_property(&_0, this_ptr, SL("router"), PH_NOISY_CC | PH_READONLY);
ZEPHIR_RETURN_CALL_METHOD(&_0, "dispatch", NULL, 0, request);
zephir_check_call_status();
RETURN_MM();
}
/**
* 初始化
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, bootstrap) {
zval _0, _1;
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *this_ptr = getThis();
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_1);
ZEPHIR_MM_GROW();
zephir_read_property(&_0, this_ptr, SL("project"), PH_NOISY_CC | PH_READONLY);
zephir_read_property(&_1, this_ptr, SL("bootstraps"), PH_NOISY_CC | PH_READONLY);
ZEPHIR_CALL_METHOD(NULL, &_0, "bootstrap", NULL, 0, &_1);
zephir_check_call_status();
ZEPHIR_MM_RESTORE();
}
/**
* 上报错误
*
* @param \Exception $e
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, reportException) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *e, e_sub, _0;
zval *this_ptr = getThis();
ZVAL_UNDEF(&e_sub);
ZVAL_UNDEF(&_0);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 1, 0, &e);
ZEPHIR_CALL_METHOD(&_0, this_ptr, "getruntime", NULL, 0);
zephir_check_call_status();
ZEPHIR_CALL_METHOD(NULL, &_0, "report", NULL, 0, e);
zephir_check_call_status();
ZEPHIR_MM_RESTORE();
}
/**
* 渲染异常
*
* @param \Leevel\Http\IRequest $request
* @param \Exception $e
* @return \Leevel\Http\IResponse
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, renderException) {
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub, *e, e_sub, _0;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&e_sub);
ZVAL_UNDEF(&_0);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 2, 0, &request, &e);
ZEPHIR_CALL_METHOD(&_0, this_ptr, "getruntime", NULL, 0);
zephir_check_call_status();
ZEPHIR_RETURN_CALL_METHOD(&_0, "render", NULL, 0, request, e);
zephir_check_call_status();
RETURN_MM();
}
/**
* 中间件结束响应.
*
* @param \Leevel\Http\IRequest $request
* @param \Leevel\Http\IResponse $response
*/
PHP_METHOD(Leevel_Bootstrap_Kernel, middlewareTerminate) {
zval _1;
zend_long ZEPHIR_LAST_CALL_STATUS;
zval *request, request_sub, *response, response_sub, _0;
zval *this_ptr = getThis();
ZVAL_UNDEF(&request_sub);
ZVAL_UNDEF(&response_sub);
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_1);
ZEPHIR_MM_GROW();
zephir_fetch_params(1, 2, 0, &request, &response);
zephir_read_property(&_0, this_ptr, SL("router"), PH_NOISY_CC | PH_READONLY);
ZEPHIR_INIT_VAR(&_1);
zephir_create_array(&_1, 1, 0 TSRMLS_CC);
zephir_array_fast_append(&_1, response);
ZEPHIR_CALL_METHOD(NULL, &_0, "throughmiddleware", NULL, 0, request, &_1);
zephir_check_call_status();
ZEPHIR_MM_RESTORE();
}
zend_object *zephir_init_properties_Leevel_Bootstrap_Kernel(zend_class_entry *class_type TSRMLS_DC) {
zval _1$$3;
zval _0, _2$$3;
ZVAL_UNDEF(&_0);
ZVAL_UNDEF(&_2$$3);
ZVAL_UNDEF(&_1$$3);
ZEPHIR_MM_GROW();
{
zval local_this_ptr, *this_ptr = &local_this_ptr;
ZEPHIR_CREATE_OBJECT(this_ptr, class_type);
zephir_read_property(&_0, this_ptr, SL("bootstraps"), PH_NOISY_CC | PH_READONLY);
if (Z_TYPE_P(&_0) == IS_NULL) {
ZEPHIR_INIT_VAR(&_1$$3);
zephir_create_array(&_1$$3, 4, 0 TSRMLS_CC);
ZEPHIR_INIT_VAR(&_2$$3);
ZVAL_STRING(&_2$$3, "Leevel\\Bootstrap\\Bootstrap\\LoadOption");
zephir_array_fast_append(&_1$$3, &_2$$3);
ZEPHIR_INIT_NVAR(&_2$$3);
ZVAL_STRING(&_2$$3, "Leevel\\Bootstrap\\Bootstrap\\LoadI18n");
zephir_array_fast_append(&_1$$3, &_2$$3);
ZEPHIR_INIT_NVAR(&_2$$3);
ZVAL_STRING(&_2$$3, "Leevel\\Bootstrap\\Bootstrap\\RegisterRuntime");
zephir_array_fast_append(&_1$$3, &_2$$3);
ZEPHIR_INIT_NVAR(&_2$$3);
ZVAL_STRING(&_2$$3, "Leevel\\Bootstrap\\Bootstrap\\TraverseProvider");
zephir_array_fast_append(&_1$$3, &_2$$3);
zephir_update_property_zval(this_ptr, SL("bootstraps"), &_1$$3);
}
ZEPHIR_MM_RESTORE();
return Z_OBJ_P(this_ptr);
}
}
| [
"635750556@qq.com"
] | 635750556@qq.com |
881f48d29b26f15b0e01b124488856d112822010 | e1901c4a297b119e57c943c51c2a7e6859da9bb6 | /TUESDAY/troll.c | e65b6b97717e30503d60cbd4a1d4a29c39c5dd5a | [] | no_license | tiprata/GNL | a5fb141f33aa4a4106f8483c89091ed5e96c83ce | e38e1ff83a3d9a622e60138e14dc50e852541a08 | refs/heads/master | 2021-01-10T02:40:52.223545 | 2016-01-22T16:26:20 | 2016-01-22T16:26:20 | 47,983,450 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 3,955 | c | /* ************************************************************************** */
/* */
/* ::: :::::::: */
/* get_next_line.c :+: :+: :+: */
/* +:+ +:+ +:+ */
/* By: tiprata <marvin@42.fr> +#+ +:+ +#+ */
/* +#+#+#+#+#+ +#+ */
/* Created: 2016/01/10 19:40:34 by tiprata #+# #+# */
/* Updated: 2016/01/12 20:28:32 by tiprata ### ########.fr */
/* */
/* ************************************************************************** */
#include "get_next_line.h"
#include "./libft/libft.h"
char *ft_dupstrcat(char *s1, char *s2, int l)
{
int i;
int j;
char *str;
i = -1;
j = -1;
if (s1 == NULL)
s1 = ft_strdup("");
if (!(str = ft_memalloc(ft_strlen(s1) + l + 1)))
return (NULL);
while (s1[++i])
str[i] = s1[i];
while (s2[++j] && j < l)
str[i++] = s2[j];
str[i] = '\0';
free(s1);
s1 = NULL;
return (str);
}
//t_rest ft_read(t_rest st, )
/*int ft_static_exist(t_rest st, char **line, char *str)
{
int i;
i = 0;
str = ft_strchr(st.s, '\n');
if (str == NULL)
{
*line = ft_strdup(st.s);
return (2);
}
else
{
i = str - st.s;
*line = ft_strsub(st.s, 0, i);
st.s = ((&str[1]) != NULL) ? ft_strdup(&str[1]) : NULL;
// st.s = ((&str[1]) != NULL) ? ft_strdup(&str[1]) : NULL;
return (st.ret == 0 && st.s[0] == '\0' ? 0 : 1);
}
}*/
int ft_strdelete(char **s, char **str)
{
if (s)
ft_strdel(s);
if (str)
ft_strdel(str);
return (0);
}
int ft_static_exist(char **s, char **line, char **str, int ret)
{
int i;
i = 0;
// if (*s[0] == '\0')
// return (2);
*str = ft_strchr(*s, '\n');
if (*s[0] == '\n')
ft_greenstr("POK");
if (*str == NULL)
{
*line = ft_strdup(*s);
return (2);
}
else
{
i = *str - *s;
*line = ft_strsub(*s, 0, i);
return (ret == 0 && *s[0] == '\0' ? ft_strdelete(s, str) : 1);
}
}
int get_next_line(int const fd, char **line)
{
static t_rest st;
int i = 0;
int j = 0;
char *str = NULL;
st.tmp = NULL;
if (fd < 0 || line == NULL )
return (-1);
*line = NULL;
if (st.s)
{
if ((ft_static_exist(&st.s, line, &str, st.ret)) != 2)
return (st.ret == 0 && st.s[0] == '\0' ? 0 : 1);
}
else
/* str = ft_strchr(st.s, '\n');
if (str == NULL)
*line = ft_strdup(st.s);
else
{
i = str - st.s;
*line = ft_strsub(st.s, 0, i);
st.s = ((&str[1]) != NULL) ? ft_strdup(&str[1]) : NULL;
return (st.ret == 0 && st.s[0] == '\0' ? ft_strdelete(&st.s, &str) : 1);
}*/
while (j == 0)
{
if (!(st.tmp))
st.tmp = ft_memalloc(BUF_SIZE + 1);
st.ret = read(fd, st.tmp, BUF_SIZE);
if (st.ret == 0)
j = 1;
if (st.ret == -1)
return (-1);
st.tmp[st.ret + 1] = '\0';
str = ft_strchr(st.tmp, '\n');
if (str == NULL)
{
if (!(*line))
*line = ft_strdup(st.tmp);
else
*line = ft_dupstrcat(*line, st.tmp, ft_strlen(st.tmp));
ft_strdel(&st.tmp);
}
else
{
i = str - st.tmp;
*line = ft_dupstrcat(*line, st.tmp, i);
st.s = ft_strdup(&str[1]);
ft_strdel(&st.tmp);
return (st.ret == 0 ? ft_strdelete(&st.s, &str) : 1);
}
}
return (st.ret == 0 ? ft_strdelete(&st.s, &str) : 1);
}
int main(int ac, char **av)
{
int fd;
int ret;
char *line = NULL;
int i;
int stop;
stop = 0;
i = 0;
ret = 0;
if (ac > 1)
{
fd = open(av[1], O_RDONLY);
if (fd == -1)
{
ft_putstr("ALERT FD -1\n");
return (0);
}
while ((ret = get_next_line(fd, &line)))
{
//if (ret == 0)
//stop = 1;
ft_putstr(line);
ft_pinkchar('|');
ft_pinkchar('\n');
ft_strdel(&line);
}
get_next_line(fd, &line);
ft_putstr(line);
}
return (0);
}
| [
"tiprata@e3r10p23.42.fr"
] | tiprata@e3r10p23.42.fr |
a6f3c46dcbb7603eff99d0068f7e9e2e06da8c45 | 72c8ed81a3e997fa93559a3e00c6a0d43fdaa685 | /wsfont/spleen-16x32.c | d4e8635e86d22cc72b713ea1eac9ee681f64b01d | [
"BSD-2-Clause",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | AVykhovanets/spleen | ff0902f434955b0d65c98b159ff77fa98ff1ab87 | a356d2b16a52fa252f9135936348f02180ddd6aa | refs/heads/master | 2023-08-27T01:00:37.214009 | 2021-10-09T19:42:41 | 2021-10-09T19:42:41 | null | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 609 | c | /*
* Spleen 1.9.1
* Copyright (c) 2018-2021, Frederic Cambus
* https://www.cambus.net/
*
* Created: 2020-06-20
* Last Updated: 2020-07-08
*
* Spleen is released under the BSD 2-Clause license.
* See LICENSE file for details.
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <stdio.h>
#include <time.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wsfont/spleen16x32.h>
int
main(int argc, char *argv[])
{
size_t loop;
for (loop = 0; loop < 32 * 2 * 32; loop++)
printf("%c", 0);
for (loop = 0; loop < 224 * 2 * 32; loop++)
printf("%c", spleen16x32_data[loop]);
return 0;
}
| [
"fred@statdns.com"
] | fred@statdns.com |
122675c9fae2064117470a518f4493c674983c00 | 24d856d98c85a319d53be2768ccc176a50873fa3 | /linux-lts-quantal-3.5.0/net/mac80211/rc80211_minstrel_ht_debugfs.c | e788f76a1dfe5811fb81614a88fc08f139f37f00 | [
"GPL-1.0-or-later",
"Linux-syscall-note",
"GPL-2.0-only",
"BSD-2-Clause"
] | permissive | dozenow/shortcut | a4803b59c95e72a01d73bb30acaae45cf76b0367 | b140082a44c58f05af3495259c1beaaa9a63560b | refs/heads/jumpstart-php | 2020-06-29T11:41:05.842760 | 2019-03-28T17:28:56 | 2019-03-28T17:28:56 | 200,405,626 | 2 | 2 | BSD-2-Clause | 2019-08-03T19:45:44 | 2019-08-03T17:57:58 | C | UTF-8 | C | false | false | 3,366 | c | /*
* Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/netdevice.h>
#include <linux/types.h>
#include <linux/skbuff.h>
#include <linux/debugfs.h>
#include <linux/ieee80211.h>
#include <linux/export.h>
#include <net/mac80211.h>
#include "rc80211_minstrel.h"
#include "rc80211_minstrel_ht.h"
static int
minstrel_ht_stats_open(struct inode *inode, struct file *file)
{
struct minstrel_ht_sta_priv *msp = inode->i_private;
struct minstrel_ht_sta *mi = &msp->ht;
struct minstrel_debugfs_info *ms;
unsigned int i, j, tp, prob, eprob;
char *p;
int ret;
if (!msp->is_ht) {
inode->i_private = &msp->legacy;
ret = minstrel_stats_open(inode, file);
inode->i_private = msp;
return ret;
}
ms = kmalloc(sizeof(*ms) + 8192, GFP_KERNEL);
if (!ms)
return -ENOMEM;
file->private_data = ms;
p = ms->buf;
p += sprintf(p, "type rate throughput ewma prob this prob "
"this succ/attempt success attempts\n");
for (i = 0; i < MINSTREL_MAX_STREAMS * MINSTREL_STREAM_GROUPS; i++) {
char htmode = '2';
char gimode = 'L';
if (!mi->groups[i].supported)
continue;
if (minstrel_mcs_groups[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
htmode = '4';
if (minstrel_mcs_groups[i].flags & IEEE80211_TX_RC_SHORT_GI)
gimode = 'S';
for (j = 0; j < MCS_GROUP_RATES; j++) {
struct minstrel_rate_stats *mr = &mi->groups[i].rates[j];
int idx = i * MCS_GROUP_RATES + j;
if (!(mi->groups[i].supported & BIT(j)))
continue;
p += sprintf(p, "HT%c0/%cGI ", htmode, gimode);
*(p++) = (idx == mi->max_tp_rate) ? 'T' : ' ';
*(p++) = (idx == mi->max_tp_rate2) ? 't' : ' ';
*(p++) = (idx == mi->max_prob_rate) ? 'P' : ' ';
p += sprintf(p, "MCS%-2u", (minstrel_mcs_groups[i].streams - 1) *
MCS_GROUP_RATES + j);
tp = mr->cur_tp / 10;
prob = MINSTREL_TRUNC(mr->cur_prob * 1000);
eprob = MINSTREL_TRUNC(mr->probability * 1000);
p += sprintf(p, " %6u.%1u %6u.%1u %6u.%1u "
"%3u(%3u) %8llu %8llu\n",
tp / 10, tp % 10,
eprob / 10, eprob % 10,
prob / 10, prob % 10,
mr->last_success,
mr->last_attempts,
(unsigned long long)mr->succ_hist,
(unsigned long long)mr->att_hist);
}
}
p += sprintf(p, "\nTotal packet count:: ideal %d "
"lookaround %d\n",
max(0, (int) mi->total_packets - (int) mi->sample_packets),
mi->sample_packets);
p += sprintf(p, "Average A-MPDU length: %d.%d\n",
MINSTREL_TRUNC(mi->avg_ampdu_len),
MINSTREL_TRUNC(mi->avg_ampdu_len * 10) % 10);
ms->len = p - ms->buf;
return nonseekable_open(inode, file);
}
static const struct file_operations minstrel_ht_stat_fops = {
.owner = THIS_MODULE,
.open = minstrel_ht_stats_open,
.read = minstrel_stats_read,
.release = minstrel_stats_release,
.llseek = no_llseek,
};
void
minstrel_ht_add_sta_debugfs(void *priv, void *priv_sta, struct dentry *dir)
{
struct minstrel_ht_sta_priv *msp = priv_sta;
msp->dbg_stats = debugfs_create_file("rc_stats", S_IRUGO, dir, msp,
&minstrel_ht_stat_fops);
}
void
minstrel_ht_remove_sta_debugfs(void *priv, void *priv_sta)
{
struct minstrel_ht_sta_priv *msp = priv_sta;
debugfs_remove(msp->dbg_stats);
}
| [
"jflinn"
] | jflinn |
4f4d7acb58840aaa07fc5e3841d49c141f8c0ddb | 62ee3292c00562e718adc9ced13e8ba2d44548ec | /TouchSensor/TouchSensorFirmware/src/smc_gen/Config_CMT0/Config_CMT0.h | ff1f7f268dc007257ab1103c90b65453bd451d2e | [] | no_license | tamapochi1/DigitalViolin | 632b32f64f89e834346ede623141cae819744fae | a5f46f305b7ab205296587d07c080f8c38ca49e1 | refs/heads/master | 2020-03-27T04:38:47.322488 | 2019-01-19T14:51:40 | 2019-01-19T14:51:40 | 145,957,743 | 1 | 2 | null | null | null | null | UTF-8 | C | false | false | 3,728 | h | /***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2016, 2017 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : Config_CMT0.h
* Version : 1.2.0
* Device(s) : R5F51303AxFN
* Description : This file implements device driver for Config_CMT0.
* Creation Date: 2018-10-24
***********************************************************************************************************************/
#ifndef Config_CMT0_H
#define Config_CMT0_H
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_cmt.h"
/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/
/* Compare Match Constant Register (CMCOR) */
#define _03A9_CMT0_CMCOR_VALUE (0x03A9U)
/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/
/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_Config_CMT0_Create(void);
void R_Config_CMT0_Start(void);
void R_Config_CMT0_Stop(void);
void R_Config_CMT0_Create_UserInit(void);
/* Start user code for function. Do not edit comment generated here */
/* End user code. Do not edit comment generated here */
#endif
| [
"koyuki-2009@live.jp"
] | koyuki-2009@live.jp |
61de930522db9e126d92af8b24d55fb023d1f550 | 07a1d9be578281caf4f0f1a1093ff559336ec0a1 | /midi_defs.h | 4c7023eaaa9d7ab031008edfc4da03dc2946dc9d | [
"MIT"
] | permissive | andypayne/midi_defs | 6b3669f957e2d4a1945b62f472698c6dedb3c8b7 | aa050affaa9ae9a5bd9169e5d59dc806dbcec2d9 | refs/heads/master | 2023-02-02T10:03:07.513688 | 2020-12-17T14:23:53 | 2020-12-17T14:23:53 | 311,129,359 | 0 | 0 | null | 2020-12-17T14:23:55 | 2020-11-08T18:37:43 | C | UTF-8 | C | false | false | 2,209 | h | #ifndef MIDI_DEFS_H
#define MIDI_DEFS_H
#define maj_triad(root) { root, 4 + root, 3 + 4 + root }
#define min_triad(root) { root, 3 + root, 4 + 3 + root }
#define dim_triad(root) { root, 3 + root, 3 + 3 + root }
#define maj_7(root) { root, 4 + root, 4 + 7 + root }
#define min_7(root) { root, 3 + root, 3 + 7 + root }
#define dom_7(root) { root, 4 + root, 3 + 7 + root }
#define dim_7(root) { root, 3 + root, 3 + 6 + root }
struct MidiDefs {
static const int MIDI_HIGH = 127;
static const int MIDI_LOW = 0;
static const char* noteNames(const int num) {
static const char* noteNamesDef[] = {
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", // 20
"A0",
"A#0",
"B0",
"C1",
"C#1",
"D1",
"D#1",
"E1",
"F1",
"F#1",
"G1",
"G#1",
"A1",
"A#1",
"B1",
"C2",
"C#2",
"D2",
"D#2",
"E2",
"F2",
"F#2",
"G2",
"G#2",
"A2",
"A#2",
"B2",
"C3",
"C#3",
"D3",
"D#3",
"E3",
"F3",
"F#3",
"G3",
"G#3",
"A3",
"A#3",
"B3",
"C4", // 60
"C#4",
"D4",
"D#4",
"E4",
"F4",
"F#4",
"G4",
"G#4",
"A4",
"A#4",
"B4",
"C5",
"C#5",
"D5",
"D#5",
"E5",
"F5",
"F#5",
"G5",
"G#5",
"A5",
"A#5",
"B5",
"C6",
"C#6",
"D6",
"D#6",
"E6",
"F6",
"F#6",
"G6",
"G#6",
"A6",
"A#6",
"B6",
"C7",
"C#7",
"D7",
"D#7",
"E7",
"F7",
"F#7",
"G7",
"G#7",
"A7",
"A#7",
"B7",
"C8",
"C#8",
"D8",
"D#8",
"E8",
"F8",
"F#8",
"G8",
"G#8",
"A8",
"A#8",
"B8",
"C9",
"C#9",
"D9",
"D#9",
"E9",
"F9",
"F#9",
"G9"
};
return noteNamesDef[num];
}
};
#endif
| [
"apayne@gmail.com"
] | apayne@gmail.com |
16f31992795045b633936c516c09a4ade04a8e32 | c2022f6b679e53cbd566c0b7d0ef652279e75d27 | /clan/2562.c | 40d53e03c7818aebb31c97781426f13b572eb053 | [] | no_license | ggjae/Algorithm-CS | 4663589e4e4bdb79a5255634933864408b06dca2 | 5598e7121b1b54bdcdf2c779d68577d25cfa75e9 | refs/heads/master | 2023-08-22T08:09:25.718005 | 2021-10-22T11:43:15 | 2021-10-22T11:43:15 | 275,533,281 | 0 | 0 | null | null | null | null | UTF-8 | C | false | false | 267 | c | #include <stdio.h>
int main(){
int a[9];
int max = -1;
int tmp = 0;
for(int i=0;i<9;i++){
scanf("%d",&a[i]);
if(max < a[i]){
max = a[i];
tmp = i;
}
}
printf("%d\n",max);
printf("%d",tmp+1);
} | [
"ggjae_@daum.net"
] | ggjae_@daum.net |
2eecc4df5440318c299254a3b4be0a5dfca3ffad | 7a3652781006b595be9f3350faf0f4552178e366 | /include/externals.h | ec055565c9ccc19a2998ba44418228d64ddf5172 | [
"MIT"
] | permissive | dbucher97/unclutter-xfixes | d816668f19b2a7dd813b21c7fb1c5fb41b9c984a | 35d227daec0db68a3ee56794339631ae9bb517ac | refs/heads/master | 2020-03-27T13:51:54.425207 | 2018-12-17T13:08:20 | 2018-12-17T13:08:20 | 146,632,042 | 0 | 0 | MIT | 2018-08-29T17:02:11 | 2018-08-29T17:02:11 | null | UTF-8 | C | false | false | 248 | h | // vim:ts=4:sw=4:expandtab
#pragma once
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <err.h>
#include <ev.h>
#include <X11/Xlib.h>
#include <X11/extensions/XInput2.h>
#include <X11/extensions/Xfixes.h>
| [
"ingo.buerk@tngtech.com"
] | ingo.buerk@tngtech.com |
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