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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
2ee228ad592e3d64f3eaed1ef48444b3ecff36f8 | 1f2490f35c67976e27fd409c1a15356580c4d846 | /Lab2/SiraliDosya.h | 6a5b5aa9285abbc2bb56008e9018283a6a09fa2f | [] | no_license | serdarmutluu/Course-Work-File-Structures | b783a12c2f8fc43a8c486d3de3641a37fe633b72 | 28466cc99e89c75ed8d1a0e104ec4741984ee9ce | refs/heads/master | 2022-11-25T08:50:23.664903 | 2020-07-21T05:48:38 | 2020-07-21T05:48:38 | 281,305,429 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,501 | h | /*
* To change this license header, choose License Headers in Project Properties.
* To change this template file, choose Tools | Templates
* and open the template in the editor.
*/
/*
* File: SiraliDosya.h
* Author: serdarm99
*
* Created on 21 Mart 2020 Cumartesi, 14:39
*/
#ifndef SIRALIDOSYA_H
#define SIRALIDOSYA_H
#include "Araba.h"
#include <deque>
#endif /* SIRALIDOSYA_H */
class SiraliDosya {
private:
fstream dosya;
deque<int> boslarListesi;
public:
SiraliDosya(char* dosyaAdi) {
dosya.open(dosyaAdi, ios::out | ios::in | ios::bin);
}
~SiraliDosya() {
dosya.close();
}
void basaSar() {
dosya.clear();
dosya.flush();
}
int ismeGoreArama(char* arananIsim) {
char isim[50];
int rrn = 0;
while (!dosya.eof()) {
dosya.read(isim, sizeof (isim));
if (strcmp(isim, arananIsim) == 0) {
rrn = dosya.tellg();
rrn -= sizeof (isim);
rrn /= sizeof (Araba);
rrn += 1;
cout << rrn;
Araba *a = new Araba();
a->kaydiOku(dosya, rrn);
cout << a;
return 0;
} else if (isim[0] == '*') {
cout << "aranan isim dosyada bulunamamistir";
return -1;
}
dosya.seekg(94,ios::cur);
}
cout << "aranan isim dosyada bulunamamistir";
return -1;
}
};
| [
"noreply@github.com"
] | serdarmutluu.noreply@github.com |
d0cebcd18f3adedf128c6e3ece11454e9c898036 | 1e2de2812842ffdcbff9c5091e08d090b72e0973 | /Development/Editor/Core/ydbase/base/warcraft3/jass/nf_register.cpp | 9e7c21144a46324d694cae25fbcef120e931ee77 | [
"Apache-2.0"
] | permissive | shawwwn/YDWE | 2cd64f215368a50271e817c755dae99e154d74da | b83ffe041d9623409d9ffd951988e2b482d9cfc3 | refs/heads/master | 2020-05-29T11:37:16.480432 | 2014-06-26T07:34:32 | 2014-06-26T07:34:32 | 16,688,734 | 2 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 4,077 | cpp | #include <base/warcraft3/jass/nf_register.h>
#include <base/hook/iat.h>
#include <base/util/do_once.h>
#include <base/warcraft3/version.h>
#include <base/warcraft3/war3_searcher.h>
#include <base/hook/fp_call.h>
namespace base { namespace warcraft3 { namespace jass { namespace nf_register {
util::signal<void, uintptr_t> event_hook;
util::signal<void, void> event_add;
uintptr_t thread_id = 0;
uintptr_t stat = 0;
uintptr_t real_storm_alloc = 0;
uintptr_t real_tls_get_value = 0;
uintptr_t __stdcall fake_storm_alloc(uint32_t amount, const char* log_filename, uint32_t log_line, uint32_t default_value)
{
uintptr_t retval = std_call<uintptr_t>(real_storm_alloc, amount, log_filename, log_line, default_value);
if ((amount == 176)
&& (log_line == 668)
&& (default_value == 0)
&& (strcmp(log_filename, ".\\Jass.cpp") == 0))
{
stat = 1;
thread_id = ::GetCurrentThreadId();
}
else if (stat == 3)
{
if (thread_id == ::GetCurrentThreadId())
{
if ((amount == 140)
&& (log_line == 90)
&& (default_value == 0)
&& (strcmp(log_filename, ".\\Agile.cpp") == 0))
{
stat = 0;
event_hook(retval);
}
}
}
return retval;
}
uintptr_t __stdcall fake_storm_alloc_122(uint32_t amount, const char* log_filename, uint32_t log_line, uint32_t default_value)
{
uintptr_t retval = std_call<uintptr_t>(real_storm_alloc, amount, log_filename, log_line, default_value);
if ((amount == 176)
&& (log_line == 667)
&& (default_value == 0)
&& (strcmp(log_filename, ".\\Jass.cpp") == 0))
{
stat = 1;
thread_id = ::GetCurrentThreadId();
}
else if (stat == 3)
{
if (thread_id == ::GetCurrentThreadId())
{
if ((amount == 140)
&& (log_line == 90)
&& (default_value == 0)
&& (strcmp(log_filename, ".\\Agile.cpp") == 0))
{
stat = 0;
event_hook(retval);
}
}
}
return retval;
}
uintptr_t __stdcall fake_storm_alloc_120(uint32_t amount, const char* log_filename, uint32_t log_line, uint32_t default_value)
{
uintptr_t retval = std_call<uintptr_t>(real_storm_alloc, amount, log_filename, log_line, default_value);
if ((amount == 176)
&& (log_line == 667)
&& (default_value == 0)
&& (strcmp(log_filename, "E:\\Drive1\\temp\\buildwar3x\\engine\\source\\Jass2\\Jass.cpp") == 0))
{
stat = 1;
thread_id = ::GetCurrentThreadId();
}
else if (stat == 3)
{
if (thread_id == ::GetCurrentThreadId())
{
if ((amount == 140)
&& (log_line == 90)
&& (default_value == 0)
&& (strcmp(log_filename, "E:\\Drive1\\temp\\buildwar3x\\engine\\Source\\Agile\\Agile.cpp") == 0))
{
stat = 0;
event_hook(retval);
}
}
}
return retval;
}
uintptr_t __stdcall fake_tls_get_value(uint32_t tls_index)
{
if ((stat != 0) && (thread_id == ::GetCurrentThreadId()))
{
if (stat == 1)
{
stat = 2;
}
else if (stat == 2)
{
stat = 3;
event_add();
}
}
return std_call<uintptr_t>(real_tls_get_value, tls_index);
}
bool initialize()
{
DO_ONCE_NOTHREADSAFE()
{
if (get_war3_searcher().get_version() > version_123)
{
real_storm_alloc = hook::iat(L"Game.dll", "Storm.dll", (const char*)401, (uintptr_t)fake_storm_alloc);
real_tls_get_value = hook::iat(L"Game.dll", "Kernel32.dll", "TlsGetValue", (uintptr_t)fake_tls_get_value);
}
else if (get_war3_searcher().get_version() > version_121b)
{
real_storm_alloc = hook::iat(L"Game.dll", "Storm.dll", (const char*)401, (uintptr_t)fake_storm_alloc_122);
real_tls_get_value = hook::iat(L"Game.dll", "Kernel32.dll", "TlsGetValue", (uintptr_t)fake_tls_get_value);
}
else
{
real_storm_alloc = hook::iat(L"Game.dll", "Storm.dll", (const char*)401, (uintptr_t)fake_storm_alloc_120);
real_tls_get_value = hook::iat(L"War3.exe", "Kernel32.dll", "TlsGetValue", (uintptr_t)fake_tls_get_value);
}
return true;
}
return false;
}
}}}}
| [
"actboy168@gmail.com"
] | actboy168@gmail.com |
f6ad6613263d131c13b5334ffe671dda6a56d350 | f3f7cf4a65cc3c9354ad04d86b14e853d34f7c08 | /Module_07/ex00/main.cpp | 0fb831d5de093912d11ba4ca0676172023f2f512 | [] | no_license | hamanmax/Piscine_CPP | 4aadce72e3feee00e4ca274dd68a876da785f36d | 18d62d0f2a4ec4023b2f167d4e63504b90253259 | refs/heads/master | 2023-04-07T02:17:12.599736 | 2021-04-19T09:18:36 | 2021-04-19T09:18:36 | 348,053,922 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 719 | cpp | #include <iostream>
#include "whatever.hpp"
int main( void ) {
int a = 2,b = 3;
std::cout << "a = " << a << ", b = " << b << std::endl;
std::cout << "min( a, b ) = " << ::min( a, b ) << std::endl;
std::cout << "max( a, b ) = " << ::max( a, b ) << std::endl;
std::string c = "chaine1";
std::string d = "chaine2";
::swap(c, d);
std::cout << "c = " << c << ", d = " << d << std::endl;
std::cout << "min( c, d ) = " << ::min( c, d ) << std::endl;
std::cout << "max( c, d ) = " << ::max( c, d ) << std::endl;
// Awesome e(2),f(3);
// swap( e, f );
// if (e > f)
// std::cout << "swap work\n";
// if (min( e, f) == f)
// std::cout << "f is the min\n";
// if (max( e, f) != f)
// std::cout << "e is the max\n";
return 0;
} | [
"hamanmax@gmail.com"
] | hamanmax@gmail.com |
23fff603a699fa0509a3e4e1e6665896a636f26b | 0783a2cce7ec4cd57a13643505ff42bd790348a0 | /Listing 2.1.h | 7dbdb8638f06972e956ee16d5f0a4132129ec7d7 | [] | no_license | Ichihoshisuz/C-Concurrency-in-Action---Listing | 9dec09364b33ef0cf9cb798a06b321b6c61b195b | 73b1d428c804bc6c7a70aa9d3ea0902c220c8d97 | refs/heads/main | 2023-04-19T10:46:15.329959 | 2021-05-08T02:17:54 | 2021-05-08T02:17:54 | 360,388,151 | 0 | 0 | null | null | null | null | GB18030 | C++ | false | false | 472 | h | #pragma once
#include <thread>
class func
{
public:
func(int& i) :N(i) {}
void operator()();
void do_something(int& i) { ++i; };
private:
int& N;
};
// 不应该这么写。会出现 dangling reference ，即可能会重复访问已经销毁的变量。
void func::operator()()
{
for (unsigned j = 0; j < 100000000; ++j)
{
do_something(N);
}
}
void oops()
{
int some_local_state = 0;
func m(some_local_state);
std::thread m_thread(m);
m_thread.detach();
} | [
"81299558+Ichihoshisuz@users.noreply.github.com"
] | 81299558+Ichihoshisuz@users.noreply.github.com |
27b56ba8e6f11aac23f2320443793cc31a03953f | 45364deefe009a0df9e745a4dd4b680dcedea42b | /SDK/FSD_STE_StickyFlame_DamageBonus_parameters.hpp | 47d9ad0fef272e1be379af895b3de7e346dcc821 | [] | no_license | RussellJerome/DeepRockGalacticSDK | 5ae9b59c7324f2a97035f28545f92773526ed99e | f13d9d8879a645c3de89ad7dc6756f4a7a94607e | refs/heads/master | 2022-11-26T17:55:08.185666 | 2020-07-26T21:39:30 | 2020-07-26T21:39:30 | 277,796,048 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 375 | hpp | #pragma once
// DeepRockGalactic SDK
#ifdef _MSC_VER
#pragma pack(push, 0x8)
#endif
#include "FSD_STE_StickyFlame_DamageBonus_classes.hpp"
namespace SDK
{
//---------------------------------------------------------------------------
//Parameters
//---------------------------------------------------------------------------
}
#ifdef _MSC_VER
#pragma pack(pop)
#endif
| [
"darkmanvoo@gmail.com"
] | darkmanvoo@gmail.com |
e10d0e97a4a214b0fe9d8d89b429bc494e08545d | b60514dc246386144edb585eb7d9c0c92bd548de | /Maths for Games/Week 1/Matrix Transformation Demo/Transformation Matrix Demo/Transformation_Matrix_DemoApp.cpp | b362df9017217d4ddb5b04ee1cb3f5edcd61d663 | [
"MIT"
] | permissive | sammydeedge/AIE2018 | 9addce918bf010ae840cdf294ba4077ae5bdeff7 | b23ce54e4572df3c00ad8517498cd11c47a41df2 | refs/heads/master | 2020-03-31T19:41:40.338376 | 2018-10-22T23:17:39 | 2018-10-22T23:17:39 | 141,961,746 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 2,594 | cpp | #include "Transformation_Matrix_DemoApp.h"
#include "Texture.h"
#include "Font.h"
#include "Input.h"
#include "Sprite.h"
Transformation_Matrix_DemoApp::Transformation_Matrix_DemoApp() {
}
Transformation_Matrix_DemoApp::~Transformation_Matrix_DemoApp() {
}
bool Transformation_Matrix_DemoApp::startup() {
m_2dRenderer = new aie::Renderer2D();
// TODO: remember to change this when redistributing a build!
// the following path would be used instead: "./font/consolas.ttf"
m_font = new aie::Font("../bin/font/consolas.ttf", 32);
//Intialising Textures for the tank's body and barrel
m_tankbodyTexture = new aie::Texture("../bin/textures/tankRed.png");
m_tankbarrelTexture = new aie::Texture("../bin/textures/barrelRed.png");
//Creating sprite files for the body and barrel
m_tankbody = new sprite(m_tankbodyTexture, 100, 100, 180);
m_tankbarrel = new sprite(m_tankbarrelTexture, 100, 100, 180);
m_tankbody->addChild(m_tankbarrel);
m_tankbody->setPosition(getWindowWidth() / 2.0f, getWindowHeight() / 2.0f);
return true;
}
void Transformation_Matrix_DemoApp::shutdown() {
delete m_tankbarrel;
delete m_tankbody;
delete m_font;
delete m_2dRenderer;
}
void Transformation_Matrix_DemoApp::update(float deltaTime) {
// input example
aie::Input* input = aie::Input::getInstance();
// turns tank
if (input->isKeyDown(aie::INPUT_KEY_A))
{
m_tankbody->rotate(deltaTime);
}
if (input->isKeyDown(aie::INPUT_KEY_D))
{
m_tankbody->rotate(-deltaTime);
}
//move tank forward and backwards
float setspeed = 100;
float adj_speed = deltaTime * setspeed;
if (input->isKeyDown(aie::INPUT_KEY_W))
{
auto facing = m_tankbody->getLocalTransformColumnVector(1) * adj_speed;
m_tankbody->translate(facing.x, facing.y, deltaTime);
}
if (input->isKeyDown(aie::INPUT_KEY_S))
{
auto facing = m_tankbody->getLocalTransformColumnVector(1) * -adj_speed;
m_tankbody->translate(facing.x, facing.y, deltaTime);
}
// turns turrent
if (input->isKeyDown(aie::INPUT_KEY_LEFT))
{
m_tankbarrel->rotate(deltaTime);
}
if (input->isKeyDown(aie::INPUT_KEY_RIGHT))
{
m_tankbarrel->rotate(-deltaTime);
}
// exit the application
if (input->isKeyDown(aie::INPUT_KEY_ESCAPE))
quit();
}
void Transformation_Matrix_DemoApp::draw() {
// wipe the screen to the background colour
clearScreen();
// begin drawing sprites
m_2dRenderer->begin();
// draw your stuff here!
m_tankbody->draw(m_2dRenderer);
// output some text, uses the last used colour
m_2dRenderer->drawText(m_font, "Press ESC to quit", 0, 0);
// done drawing sprites
m_2dRenderer->end();
} | [
"sammydeedge@hotmail.com"
] | sammydeedge@hotmail.com |
89233abff337cf6fa48a35dfc181435445f74923 | 935927010571e2f820e70cead9a1fd471d88ea16 | /Practice CP ITB/Practice10/B - Xenia and Bit Operator.cpp | 2c090a68d06b43dd263e23a023a5026955b32f2a | [] | no_license | muhammadhasan01/cp | ebb0869b94c2a2ab9487861bd15a8e62083193ef | 3b0152b9621c81190dd1a96dde0eb80bff284268 | refs/heads/master | 2023-05-30T07:18:02.094877 | 2023-05-21T22:03:57 | 2023-05-21T22:03:57 | 196,739,005 | 6 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,289 | cpp | #include<bits/stdc++.h>
using namespace std;
struct st{
long long v; int h;
};
int n,m,k;
vector<st> tree;
void build(){
for(int i=k-1; i > 0; i--){
//cout << i << "\n";
if(tree[2*i].h & 1){
tree[i].v = tree[2*i].v|tree[2*i+1].v;
tree[i].h = tree[2*i].h+1;
//cout << i << " => " << tree[i].v << " => " << tree[2*i].v << " |\n";
}else{
tree[i].v = tree[2*i].v^tree[2*i+1].v;
tree[i].h = tree[2*i].h+1;
//cout << i << " => " << tree[i].v << " => " << tree[2*i].v << " ^\n";
}
}
}
long long update(int p, long long val){
for(tree[p+=k].v = val; p>1; p/=2){
//cout << p/2 << "\n";
if(tree[p].h&1){
tree[p/2].v = tree[p].v|tree[p^1].v;
}else{
tree[p/2].v = tree[p].v^tree[p^1].v;
}
}
//cout << "\n";
return tree[1].v;
}
int main(){
ios_base::sync_with_stdio(false);
cin.tie(NULL);
cout.tie(NULL);
cin >> n >> m;
k = pow(2,n);
tree.resize(2*k);
for(int i=0;i<k;i++){
cin >> tree[k+i].v;
tree[k+i].h = 1;
}
build();
while(m--){
int p; long long val;
cin >> p >> val;
cout << update(p-1,val) << "\n";
}
return 0;
}
| [
"39514247+muhammadhasan01@users.noreply.github.com"
] | 39514247+muhammadhasan01@users.noreply.github.com |
92106689bb805a434d46ab106ec7596eda2445d1 | a3a614b13d1361b655c40e38ae266d71c4ec7b74 | /src/RANSAC.cpp | ed657aa8ce4b68bdc977a1b287fe50cadd0db98e | [] | no_license | limitimil/CVHW_ImageStiting | c00ffe636cdd361152aff0983a039c04040d9dfd | 43694d26d2ec9ca248ce9dfe0f7ec01aa8bad946 | refs/heads/master | 2021-01-09T20:14:06.081231 | 2016-07-12T14:56:35 | 2016-07-12T14:56:35 | 63,166,966 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 4,364 | cpp | #include <cmath>
#include <cstdlib>
#include <limits>
#include <cassert>
#include <opencv2/imgproc.hpp>
#include "RANSAC.h"
#include "../DevTool/combination.h"
#include "../DevTool/utilCV.h"
#include "warp.h"
#include "scoreBoard.h"
using namespace cv;
using namespace std;
RANSAC::RANSAC() {}
RANSAC::RANSAC(vector<KeyPoint>* points): points(points){}
void RANSAC::myline(Mat& img){
utilCV UTIL(false);
combination c(n_num_combination_of_m,2,points->size());
UTIL.nameValue("szie",(int)points->size());
int best_c[2] = {0,0};
Mat best_model;
int max_inlier_count = 0;
Mat img_clone(img.clone());
for(c.init();!c.isLast();c.next()){
UTIL.MSG("loop start");
UTIL.nameValue("c[0]",c[0]);
UTIL.nameValue("c[1]",c[1]);
Mat model = make_model((*points)[c[0]],(*points)[c[1]]);
UTIL.showCVobj(model,"model");
int inlier_count=0;
for(int i=0;i<points->size();i++){
float dist = calc_distance(model, (*points)[i]);
assert (dist >= 0.0);
UTIL.nameValue("dist",(float)dist);
if(dist < thredshold) inlier_count ++;
}
UTIL.nameValue("inlier_count",inlier_count);
if(inlier_count > max_inlier_count){
max_inlier_count = inlier_count;
if(!best_model.empty())best_model.release();
best_model= model.clone();
memcpy(best_c,c.value_block,sizeof(int)*2);
}
}
line (img_clone,(*points)[best_c[0]].pt,(*points)[best_c[1]].pt,Scalar(0,0,0),1,1);
imshow("img with line", img_clone);
}
Mat RANSAC::make_model(const KeyPoint& p1, const KeyPoint& p2){
Mat result(2,1,CV_32FC1);
Mat Y(2,1,CV_32FC1);
Mat X_s(2,2,CV_32FC1);
Mat_<float> Y_ = Y,X_s_ = X_s;
Y_(0) = p1.pt.y;
Y_(1) = p2.pt.y;
X_s_(0,0) = p1.pt.x;
X_s_(1,0) = p2.pt.x;
X_s_(0,1) = X_s_(1,1) = 1.0;
result = X_s.inv() * Y;
return result;
}
float RANSAC::calc_distance(Mat& m,const KeyPoint& p){
assert(m.rows == 2);
utilCV UTIL(false);
float tmp = abs(p.pt.y - m.at<float>(0) * p.pt.x - m.at<float>(1));
UTIL.nameValue("tmp is",tmp);
UTIL.showCVobj(m,"obj");
return tmp / sqrt(1+m.at<float>(0)* m.at<float>(0));
}
float calc_min_dist(Point2f& p,KNN_set& knn,int kp){ // only for RANSAC::best_model
float min_dist = numeric_limits<float>::max();
for(int i=0;i<knn.the_K;i++){
float dist = norm(Mat(p),Mat(knn(kp,i).pt));
if(dist < min_dist){
min_dist = dist ;
}
}
return min_dist;
}
inline static int random_select(scoreBoard& sb,float r){
int pick;
if(r > 1.0) pick = rand() % sb.size();
else pick = rand() % int(sb.size() * r);
return sb.keys[pick];
}
inline static void updateScore(int key1,int key2,int key3,scoreBoard& sb,int inlier_count){
if(sb.values[key1] < inlier_count) sb.update(key1, inlier_count);
if(sb.values[key2] < inlier_count) sb.update(key2, inlier_count);
if(sb.values[key3] < inlier_count) sb.update(key3, inlier_count);
return;
}
inline static void updateAnealing(float& a){
const float ratio = 1.005; //equals to 100^(1/100)
a = a*ratio;
return;
}
Mat RANSAC::best_model(KNN_set& knn,const Mat& img1,const Mat& img2){
utilCV UTIL(true);
thredshold = 10;
//
combination c2(n_num_in_range_of_m,3,knn.the_K);
scoreBoard sb(knn.objectKeyPoint->size());
Mat imgResult;
Mat best_model;
int max_inlier_count = 0;
int inlier_count;
float anealing = 1;
const vector<KeyPoint>& oKP = *knn.objectKeyPoint;
do{
int key1,key2,key3;
float range = (101-anealing)/100;
key1 = random_select(sb,range);//
while(key2 = random_select(sb,range),key2 == key1)UTIL.MSG("duplicate");//
while(key3 = random_select(sb,range),key3 == key2 || key3 == key1)UTIL.MSG("duplicate");//
Mat C = make_constraints(oKP[key1],oKP[key2 ],oKP[key3 ]);
c2.init();
do{
Mat T = make_offset(
knn(key1 ,c2[0]),
knn(key2 ,c2[1]),
knn(key3 ,c2[2])
);
Mat R = C.inv() * T;
inlier_count = 0;
for(int i=0;i< knn.objectKeyPoint->size();i++){
Point2f point = do_mul(R,oKP[i].pt.x,oKP[i].pt.y);
float dist = calc_min_dist(point,knn,i);
if(dist < thredshold) inlier_count ++ ;
}
if(inlier_count > max_inlier_count){
max_inlier_count = inlier_count;
R.copyTo(best_model);
}
updateScore(key1,key2,key3,sb,inlier_count);//
c2.next();
if(inlier_count > 400 && !img1.empty() && !img2.empty()) {
//RecoveryShow_forward(img1,img2,R,imgResult);
}
}while(!c2.isLast());
updateAnealing(anealing);
UTIL.nameValue("anealing",anealing);
}while(anealing <= 100);
return best_model;
}
| [
"zlsh10340@gmail.com"
] | zlsh10340@gmail.com |
28f1d2f1a2d102b07cdb4386cbb6de84abfa469a | 63a8dc27f2f742d2c82b94ebaea8173df3a47462 | /Algorithms/Implementation/FindDigits.cpp | bf7084d264505430b2aff464b7e29e77c85b83e6 | [] | no_license | CristianD1/Hacker-Rank-Code | 014f86676b76209a984f2e284e2c315118cae3c4 | f95da82e97d5dffc3e26a244d79e70054fca4729 | refs/heads/master | 2021-01-18T23:20:33.176107 | 2016-06-09T12:34:04 | 2016-06-09T12:34:04 | 50,144,866 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 423 | cpp | #include <iostream>
int findDivisors(int in){
int tempIn = in;
int resCount = 0;
while(tempIn > 0){
int digit = tempIn % 10;
tempIn = tempIn / 10;
if(digit != 0 && in % digit == 0){
resCount ++;
}
}
return resCount;
}
int main(){
int t;
std::cin >> t;
for(int i = 0; i < t; i++){
int in;
std::cin >> in;
int divisors = findDivisors(in);
std::cout << divisors << std::endl;
}
return 0;
} | [
"cristian.david909@gmail.com"
] | cristian.david909@gmail.com |
084563631b42ed0cfdcf510807ac03cef80a79de | bcf7410e9dd665c8243f927c31c291a6dcf4a98b | /src/textures.hh | 3136161bea6eab214371f6fd17e2697d807d669f | [] | no_license | bhamrick/zzz | d234f6d9852015d2eda19591745bed2c026ed067 | 63e563062b3e370ce093d30982ab1a286ba55adf | refs/heads/master | 2016-09-05T23:21:43.374395 | 2011-04-02T06:18:15 | 2011-04-02T06:18:15 | 1,307,319 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 147 | hh | #ifndef TEXTURES_H
#define TEXTURES_H
void init_textures();
void use_player_texture();
void use_background_texture();
void end_texture();
#endif
| [
"brian.c.hamrick@gmail.com"
] | brian.c.hamrick@gmail.com |
37556deb027ab9269f36fc965aea36ffa2f74e59 | 3f38a77e31becc7afb482e57bc115f2860976b7c | /solution/3003.cpp | 8e0f782829bb3e2cf617ced9eb36775cba502bf3 | [] | no_license | gnujoow/acmicpc | 06f2c7b1381d8f5b2af8f39bd92b5baf100f6007 | 8f5f082e03bc432a2b9956a82eeabd2974234b43 | refs/heads/master | 2020-04-15T15:01:50.222670 | 2017-06-14T08:50:51 | 2017-06-14T08:50:51 | 54,367,287 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 176 | cpp | #include <cstdio>
const int chess[6] ={1,1,2,2,2,8};
int main(){
int temp;
for(int i = 0 ; i < 6 ; i++){
scanf("%d",&temp);
printf("%d ",chess[i]-temp);
}
return 0;
} | [
"gnujoow.kim@gmail.com"
] | gnujoow.kim@gmail.com |
bebc4a2ad78e1f2180afbefb056d80f533d310ec | b4f09794c97136834aaef49bcdfa789f13bc9949 | /src/llmq/quorums_dkgsessionmgr.cpp | 2077d3ce9064dc1dfac04dfe77788b5f36e25110 | [
"MIT"
] | permissive | bee-group/beenode | c878ca0be7669fc405f00abb277c9ee26477cfc8 | d27c39471bd960779f1b5dd09ad07295fe29d3e6 | refs/heads/master | 2023-07-07T05:28:26.736520 | 2023-07-04T16:48:45 | 2023-07-04T16:48:45 | 180,884,728 | 8 | 11 | MIT | 2020-04-07T07:09:03 | 2019-04-11T22:03:08 | C++ | UTF-8 | C++ | false | false | 9,368 | cpp | // Copyright (c) 2018-2019 The Beenode Core developers
// Distributed under the MIT/X11 software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include "quorums_dkgsessionmgr.h"
#include "quorums_blockprocessor.h"
#include "quorums_debug.h"
#include "quorums_init.h"
#include "quorums_utils.h"
#include "chainparams.h"
#include "net_processing.h"
#include "spork.h"
#include "validation.h"
namespace llmq
{
CDKGSessionManager* quorumDKGSessionManager;
static const std::string DB_VVEC = "qdkg_V";
static const std::string DB_SKCONTRIB = "qdkg_S";
CDKGSessionManager::CDKGSessionManager(CDBWrapper& _llmqDb, CBLSWorker& _blsWorker) :
llmqDb(_llmqDb),
blsWorker(_blsWorker)
{
}
CDKGSessionManager::~CDKGSessionManager()
{
}
void CDKGSessionManager::StartMessageHandlerPool()
{
for (const auto& qt : Params().GetConsensus().llmqs) {
dkgSessionHandlers.emplace(std::piecewise_construct,
std::forward_as_tuple(qt.first),
std::forward_as_tuple(qt.second, messageHandlerPool, blsWorker, *this));
}
messageHandlerPool.resize(2);
RenameThreadPool(messageHandlerPool, "beenode-q-msg");
}
void CDKGSessionManager::StopMessageHandlerPool()
{
messageHandlerPool.stop(true);
}
void CDKGSessionManager::UpdatedBlockTip(const CBlockIndex* pindexNew, bool fInitialDownload)
{
const auto& consensus = Params().GetConsensus();
CleanupCache();
if (fInitialDownload)
return;
if (!deterministicMNManager->IsDIP3Enforced(pindexNew->nHeight))
return;
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return;
for (auto& qt : dkgSessionHandlers) {
qt.second.UpdatedBlockTip(pindexNew);
}
}
void CDKGSessionManager::ProcessMessage(CNode* pfrom, const std::string& strCommand, CDataStream& vRecv, CConnman& connman)
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return;
if (strCommand != NetMsgType::QCONTRIB
&& strCommand != NetMsgType::QCOMPLAINT
&& strCommand != NetMsgType::QJUSTIFICATION
&& strCommand != NetMsgType::QPCOMMITMENT
&& strCommand != NetMsgType::QWATCH) {
return;
}
if (strCommand == NetMsgType::QWATCH) {
pfrom->qwatch = true;
return;
}
if (vRecv.size() < 1) {
LOCK(cs_main);
Misbehaving(pfrom->id, 100);
return;
}
// peek into the message and see which LLMQType it is. First byte of all messages is always the LLMQType
Consensus::LLMQType llmqType = (Consensus::LLMQType)*vRecv.begin();
if (!dkgSessionHandlers.count(llmqType)) {
LOCK(cs_main);
Misbehaving(pfrom->id, 100);
return;
}
dkgSessionHandlers.at(llmqType).ProcessMessage(pfrom, strCommand, vRecv, connman);
}
bool CDKGSessionManager::AlreadyHave(const CInv& inv) const
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return false;
for (const auto& p : dkgSessionHandlers) {
auto& dkgType = p.second;
if (dkgType.pendingContributions.HasSeen(inv.hash)
|| dkgType.pendingComplaints.HasSeen(inv.hash)
|| dkgType.pendingJustifications.HasSeen(inv.hash)
|| dkgType.pendingPrematureCommitments.HasSeen(inv.hash)) {
return true;
}
}
return false;
}
bool CDKGSessionManager::GetContribution(const uint256& hash, CDKGContribution& ret) const
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return false;
for (const auto& p : dkgSessionHandlers) {
auto& dkgType = p.second;
LOCK2(dkgType.cs, dkgType.curSession->invCs);
if (dkgType.phase < QuorumPhase_Initialized || dkgType.phase > QuorumPhase_Contribute) {
continue;
}
auto it = dkgType.curSession->contributions.find(hash);
if (it != dkgType.curSession->contributions.end()) {
ret = it->second;
return true;
}
}
return false;
}
bool CDKGSessionManager::GetComplaint(const uint256& hash, CDKGComplaint& ret) const
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return false;
for (const auto& p : dkgSessionHandlers) {
auto& dkgType = p.second;
LOCK2(dkgType.cs, dkgType.curSession->invCs);
if (dkgType.phase < QuorumPhase_Contribute || dkgType.phase > QuorumPhase_Complain) {
continue;
}
auto it = dkgType.curSession->complaints.find(hash);
if (it != dkgType.curSession->complaints.end()) {
ret = it->second;
return true;
}
}
return false;
}
bool CDKGSessionManager::GetJustification(const uint256& hash, CDKGJustification& ret) const
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return false;
for (const auto& p : dkgSessionHandlers) {
auto& dkgType = p.second;
LOCK2(dkgType.cs, dkgType.curSession->invCs);
if (dkgType.phase < QuorumPhase_Complain || dkgType.phase > QuorumPhase_Justify) {
continue;
}
auto it = dkgType.curSession->justifications.find(hash);
if (it != dkgType.curSession->justifications.end()) {
ret = it->second;
return true;
}
}
return false;
}
bool CDKGSessionManager::GetPrematureCommitment(const uint256& hash, CDKGPrematureCommitment& ret) const
{
if (!sporkManager.IsSporkActive(SPORK_17_QUORUM_DKG_ENABLED))
return false;
for (const auto& p : dkgSessionHandlers) {
auto& dkgType = p.second;
LOCK2(dkgType.cs, dkgType.curSession->invCs);
if (dkgType.phase < QuorumPhase_Justify || dkgType.phase > QuorumPhase_Commit) {
continue;
}
auto it = dkgType.curSession->prematureCommitments.find(hash);
if (it != dkgType.curSession->prematureCommitments.end() && dkgType.curSession->validCommitments.count(hash)) {
ret = it->second;
return true;
}
}
return false;
}
void CDKGSessionManager::WriteVerifiedVvecContribution(Consensus::LLMQType llmqType, const CBlockIndex* pindexQuorum, const uint256& proTxHash, const BLSVerificationVectorPtr& vvec)
{
llmqDb.Write(std::make_tuple(DB_VVEC, (uint8_t) llmqType, pindexQuorum->GetBlockHash(), proTxHash), *vvec);
}
void CDKGSessionManager::WriteVerifiedSkContribution(Consensus::LLMQType llmqType, const CBlockIndex* pindexQuorum, const uint256& proTxHash, const CBLSSecretKey& skContribution)
{
llmqDb.Write(std::make_tuple(DB_SKCONTRIB, (uint8_t) llmqType, pindexQuorum->GetBlockHash(), proTxHash), skContribution);
}
bool CDKGSessionManager::GetVerifiedContributions(Consensus::LLMQType llmqType, const CBlockIndex* pindexQuorum, const std::vector<bool>& validMembers, std::vector<uint16_t>& memberIndexesRet, std::vector<BLSVerificationVectorPtr>& vvecsRet, BLSSecretKeyVector& skContributionsRet)
{
auto members = CLLMQUtils::GetAllQuorumMembers(llmqType, pindexQuorum);
memberIndexesRet.clear();
vvecsRet.clear();
skContributionsRet.clear();
memberIndexesRet.reserve(members.size());
vvecsRet.reserve(members.size());
skContributionsRet.reserve(members.size());
for (size_t i = 0; i < members.size(); i++) {
if (validMembers[i]) {
BLSVerificationVectorPtr vvec;
CBLSSecretKey skContribution;
if (!GetVerifiedContribution(llmqType, pindexQuorum, members[i]->proTxHash, vvec, skContribution)) {
return false;
}
memberIndexesRet.emplace_back(i);
vvecsRet.emplace_back(vvec);
skContributionsRet.emplace_back(skContribution);
}
}
return true;
}
bool CDKGSessionManager::GetVerifiedContribution(Consensus::LLMQType llmqType, const CBlockIndex* pindexQuorum, const uint256& proTxHash, BLSVerificationVectorPtr& vvecRet, CBLSSecretKey& skContributionRet)
{
LOCK(contributionsCacheCs);
ContributionsCacheKey cacheKey = {llmqType, pindexQuorum->GetBlockHash(), proTxHash};
auto it = contributionsCache.find(cacheKey);
if (it != contributionsCache.end()) {
vvecRet = it->second.vvec;
skContributionRet = it->second.skContribution;
return true;
}
BLSVerificationVector vvec;
BLSVerificationVectorPtr vvecPtr;
CBLSSecretKey skContribution;
if (llmqDb.Read(std::make_tuple(DB_VVEC, (uint8_t) llmqType, pindexQuorum->GetBlockHash(), proTxHash), vvec)) {
vvecPtr = std::make_shared<BLSVerificationVector>(std::move(vvec));
}
llmqDb.Read(std::make_tuple(DB_SKCONTRIB, (uint8_t) llmqType, pindexQuorum->GetBlockHash(), proTxHash), skContribution);
it = contributionsCache.emplace(cacheKey, ContributionsCacheEntry{GetTimeMillis(), vvecPtr, skContribution}).first;
vvecRet = it->second.vvec;
skContributionRet = it->second.skContribution;
return true;
}
void CDKGSessionManager::CleanupCache()
{
LOCK(contributionsCacheCs);
auto curTime = GetTimeMillis();
for (auto it = contributionsCache.begin(); it != contributionsCache.end(); ) {
if (curTime - it->second.entryTime > MAX_CONTRIBUTION_CACHE_TIME) {
it = contributionsCache.erase(it);
} else {
++it;
}
}
}
}
| [
"you@example.com"
] | you@example.com |
ac820055f5e4930bbee3ebf27b09aeb95e3c236a | 160581b145f691b23c723f417c550619b416beca | /sfml/include/SFML/Window/Mouse.hpp | 5daa466623542860e466f2a0e8b9bf9fbad6db5e | [] | no_license | AntonGlomadov/LiDAR_main | df2fd6fa0cff4f1e2871a7e08ba75eddb3523200 | 879d244f84680c9ceba89cd5ba071e1ff7ded482 | refs/heads/master | 2021-01-16T09:18:38.222799 | 2020-02-15T21:15:23 | 2020-02-15T21:15:23 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 6,617 | hpp | ////////////////////////////////////////////////////////////
//
// SFML - Simple and Fast Multimedia Library
// Copyright (C) 2007-2018 Laurent Gomila (laurent@sfml-dev.org)
//
// This software is provided 'as-is', without any express or implied warranty.
// In no event will the authors be held liable for any damages arising from the use of this software.
//
// Permission is granted to anyone to use this software for any purpose,
// including commercial applications, and to alter it and redistribute it freely,
// subject to the following restrictions:
//
// 1. The origin of this software must not be misrepresented;
// you must not claim that you wrote the original software.
// If you use this software in a product, an acknowledgment
// in the product documentation would be appreciated but is not required.
//
// 2. Altered source versions must be plainly marked as such,
// and must not be misrepresented as being the original software.
//
// 3. This notice may not be removed or altered from any source distribution.
//
////////////////////////////////////////////////////////////
#ifndef SFML_MOUSE_HPP
#define SFML_MOUSE_HPP
////////////////////////////////////////////////////////////
// Headers
////////////////////////////////////////////////////////////
#include <SFML/Window/Export.hpp>
#include <SFML/System/Vector2.hpp>
namespace sf {
class Window;
////////////////////////////////////////////////////////////
/// \brief Give access to the real-time state of the mouse
///
////////////////////////////////////////////////////////////
class SFML_WINDOW_API Mouse {
public:
////////////////////////////////////////////////////////////
/// \brief Mouse buttons
///
////////////////////////////////////////////////////////////
enum Button {
Left, ///< The left mouse button
Right, ///< The right mouse button
Middle, ///< The middle (wheel) mouse button
XButton1, ///< The first extra mouse button
XButton2, ///< The second extra mouse button
ButtonCount ///< Keep last -- the total number of mouse buttons
};
////////////////////////////////////////////////////////////
/// \brief Mouse wheels
///
////////////////////////////////////////////////////////////
enum Wheel {
VerticalWheel, ///< The vertical mouse wheel
HorizontalWheel ///< The horizontal mouse wheel
};
////////////////////////////////////////////////////////////
/// \brief Check if a mouse button is pressed
///
/// \param button Button to check
///
/// \return True if the button is pressed, false otherwise
///
////////////////////////////////////////////////////////////
static bool isButtonPressed(Button button);
////////////////////////////////////////////////////////////
/// \brief Get the current position of the mouse in desktop coordinates
///
/// This function returns the global position of the mouse
/// cursor on the desktop.
///
/// \return Current position of the mouse
///
////////////////////////////////////////////////////////////
static Vector2i getPosition();
////////////////////////////////////////////////////////////
/// \brief Get the current position of the mouse in window coordinates
///
/// This function returns the current position of the mouse
/// cursor, relative to the given window.
///
/// \param relativeTo Reference window
///
/// \return Current position of the mouse
///
////////////////////////////////////////////////////////////
static Vector2i getPosition(const Window &relativeTo);
////////////////////////////////////////////////////////////
/// \brief Set the current position of the mouse in desktop coordinates
///
/// This function sets the global position of the mouse
/// cursor on the desktop.
///
/// \param position New position of the mouse
///
////////////////////////////////////////////////////////////
static void setPosition(const Vector2i &position);
////////////////////////////////////////////////////////////
/// \brief Set the current position of the mouse in window coordinates
///
/// This function sets the current position of the mouse
/// cursor, relative to the given window.
///
/// \param position New position of the mouse
/// \param relativeTo Reference window
///
////////////////////////////////////////////////////////////
static void setPosition(const Vector2i &position, const Window &relativeTo);
};
} // namespace sf
#endif // SFML_MOUSE_HPP
////////////////////////////////////////////////////////////
/// \class sf::Mouse
/// \ingroup window
///
/// sf::Mouse provides an interface to the state of the
/// mouse. It only contains static functions (a single
/// mouse is assumed), so it's not meant to be instantiated.
///
/// This class allows users to query the mouse state at any
/// time and directly, without having to deal with a window and
/// its events. Compared to the MouseMoved, MouseButtonPressed
/// and MouseButtonReleased events, sf::Mouse can retrieve the
/// state of the cursor and the buttons at any time
/// (you don't need to store and update a boolean on your side
/// in order to know if a button is pressed or released), and you
/// always get the real state of the mouse, even if it is
/// moved, pressed or released when your window is out of focus
/// and no event is triggered.
///
/// The setPosition and getPosition functions can be used to change
/// or retrieve the current position of the mouse pointer. There are
/// two versions: one that operates in global coordinates (relative
/// to the desktop) and one that operates in window coordinates
/// (relative to a specific window).
///
/// Usage example:
/// \code
/// if (sf::Mouse::isButtonPressed(sf::Mouse::Left))
/// {
/// // left click...
/// }
///
/// // get global mouse position
/// sf::Vector2i position = sf::Mouse::getPosition();
///
/// // set mouse position relative to a window
/// sf::Mouse::setPosition(sf::Vector2i(100, 200), window);
/// \endcode
///
/// \see sf::Joystick, sf::Keyboard, sf::Touch
///
////////////////////////////////////////////////////////////
| [
"maxxtereshko@gmail.com"
] | maxxtereshko@gmail.com |
6ef2f72cf00f369cc3eaa21c1bbfe2db9f1fb4ee | 7353b0ef98502e77295480525fd040e0216d087a | /snippets/0x07/sol_deerwoods.cpp | f44eb75ee43f0e102d39be2e42418fff4af21462 | [] | no_license | pblan/fha-cpp | df5428dc68f6ba009dea8a0a738dfec356c4a4d9 | 5008f54133cf4913f0ca558a3817b01b10d04494 | refs/heads/master | 2023-08-10T16:21:30.697211 | 2021-09-28T15:04:53 | 2021-09-28T15:04:53 | 302,557,502 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,931 | cpp | // author: a.voss@fh-aachen.de
#include <iostream>
using std::cout;
using std::endl;
using std::ostream;
template <typename T>
class nullable {
public:
typedef T value_type;
private:
value_type m_value;
bool m_isNull;
public:
nullable() : m_isNull(true) {}
nullable(const nullable& n) : m_value(n.m_value), m_isNull(n.m_isNull) {}
nullable(const value_type& value) : m_value(value), m_isNull(false) {}
bool operator!() const {
return !m_isNull;
}
void reset() {
m_isNull = true;
}
operator T() const {
return m_value;
}
nullable& operator+=(const nullable& n) {
if (!m_isNull)
m_value += n.m_value;
return *this;
}
friend ostream& operator<<(ostream& os, const nullable& n) {
if (!n)
os << n.m_value;
else
os << "NULL";
return os;
}
friend nullable operator+(const nullable& lhs, const nullable& rhs) {
nullable res{lhs};
return res+=rhs;
}
};
int main()
{
cout << endl << "--- " << __FILE__ << " ---" << endl << endl;
nullable<int> n0,n1(23),n2(n1);
cout << "01| n0:" << n0 << ", n1:" << n1 << ", n2:" << n2 << endl;
n0 = 0;
n1 = 1;
n2.reset();
cout << "02| n0:" << n0 << ", n1:" << n1 << ", n2:" << n2 << endl;
cout << "-----" << endl;
n0 += 10;
n1 += 10;
n2 += 10;
cout << "03| n0:" << n0 << ", n1:" << n1 << ", n2:" << n2 << endl;
cout << "04| !n0:" << !n0 << ", !n1:" << !n1 << ", !n2:" << !n2 << endl;
cout << "-----" << endl;
n0 = 0; n1 = 1; n2 = 2;
cout << "05| n0:" << n0 << ", n1:" << n1 << ", n2:" << n2
<< ", (int)n2:" << (int)n2 << endl;
cout << "06| n1+n2:" << n1+n2 << endl;
cout << endl << "--- " << __FILE__ << " ---" << endl << endl;
return 0;
}
| [
"patrick.blaneck@rwth-aachen.de"
] | patrick.blaneck@rwth-aachen.de |
e3b1d9e53a277165194a662fb696488975bdd845 | c8e6f194669663e0e2748dbc56a7172b9ea008f7 | /.localhistory/GUI/1472038091$MainForm.h | ffe679abbda968c4564a473a9033100eebf770e4 | [] | no_license | itreppert/GUI | 1922e781d804d17cb8008197fdbfa11576077618 | 9ca4ea0531eb45a4462a4d8278aec67f8c2705ef | refs/heads/master | 2020-04-17T20:29:10.965471 | 2016-09-06T13:18:01 | 2016-09-06T13:18:01 | 67,501,677 | 0 | 0 | null | null | null | null | ISO-8859-1 | C++ | false | false | 107,384 | h | #pragma once
#include "Test.h"
#include "TeilenDurch0Exception.h"
#include "BlinkinButton.h"
#include "DrawingPanel.h"
#include "RegexTextBox.h"
namespace GUI
{
using namespace System;
using namespace System::ComponentModel;
using namespace System::Collections;
using namespace System::Windows::Forms;
using namespace System::Data;
using namespace System::Drawing;
using namespace NLog;
/// <summary>
/// Zusammenfassung für MainForm
/// </summary>
public ref class MainForm : public System::Windows::Forms::Form
{
public:
MainForm(void)
{
logger->Info("ctor");
InitializeComponent();
initialiseComponents();
tabControl1->SelectTab(tabControl1->TabCount - 1);
step = 0;
richTextBox1->LoadFile("d:\\Dokument.rtf");
points = gcnew ArrayList;
points->Add(lastPoint);
}
protected:
/// <summary>
/// Verwendete Ressourcen bereinigen.
/// </summary>
~MainForm()
{
if (components)
{
delete components;
}
}
//Logger !!
private: static Logger^ logger = LogManager::GetCurrentClassLogger();
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel1;
private: System::Windows::Forms::TextBox^ textBox1;
private: System::Windows::Forms::Panel^ panel1;
private: System::Windows::Forms::Button^ cmdChangeFormColor;
private: System::Windows::Forms::TabControl^ tabControl1;
private: System::Windows::Forms::TabPage^ tabPage1;
private: System::Windows::Forms::TabPage^ tabPage2;
private: System::Windows::Forms::TabPage^ tabPage3;
private: System::Windows::Forms::Button^ btnChangeTab;
private: System::Windows::Forms::Panel^ panel2;
private: System::Windows::Forms::CheckBox^ checkBox1;
private: System::Windows::Forms::Button^ btnCheckbox;
private: System::Windows::Forms::RadioButton^ radioButton3;
private: System::Windows::Forms::RadioButton^ radioButton2;
private: System::Windows::Forms::RadioButton^ radioButton1;
private: System::Windows::Forms::GroupBox^ groupBox1;
private: System::Windows::Forms::Button^ btnRadioButton;
private: System::Windows::Forms::ComboBox^ cmbBlubb;
private: System::Windows::Forms::Button^ btnComboboxValue;
private: System::Windows::Forms::Button^ btnComboAddItem;
private: System::Windows::Forms::Button^ btnComboremoveItem;
private: System::Windows::Forms::Button^ btnComboInsert;
private: System::Windows::Forms::ListBox^ listBox1;
private: System::Windows::Forms::TextBox^ txtAnswers;
private: System::Windows::Forms::TextBox^ txtQuestions;
Test^ t;
int progress;
String^ antwort1;
String^ antwort2;
String^ antwort3;
String^ antwort4;
private: System::Windows::Forms::Button^ btnNextStep;
int step;
private: System::Windows::Forms::Button^ btnChangeFromAnotherClass;
private: System::Windows::Forms::MaskedTextBox^ maskedTextBox1;
private: System::Windows::Forms::NumericUpDown^ numericUpDown1;
private: System::Windows::Forms::Panel^ panel3;
private: System::Windows::Forms::PictureBox^ pictureBox1;
private: System::Windows::Forms::Button^ btnStartProgress;
private: System::Windows::Forms::ProgressBar^ progressBar1;
private: System::Windows::Forms::RichTextBox^ richTextBox1;
private: System::Windows::Forms::Timer^ timer1;
private: System::Windows::Forms::TrackBar^ trackBar1;
private: System::Windows::Forms::MenuStrip^ menuStrip1;
private: System::Windows::Forms::ToolStripMenuItem^ toolStripMenuItem1;
private: System::Windows::Forms::ToolStripMenuItem^ toolStripMenuItem2;
private: System::Windows::Forms::ToolStripSeparator^ toolStripSeparator1;
private: System::Windows::Forms::ToolStripMenuItem^ mnuSaveFileDialog;
private: System::Windows::Forms::ToolStripMenuItem^ toolStripMenuItem3;
private: System::Windows::Forms::OpenFileDialog^ openFileDialog1;
private: System::Windows::Forms::ToolStripMenuItem^ mnuFarben;
private: System::Windows::Forms::ColorDialog^ colorDialog1;
private: System::Windows::Forms::SaveFileDialog^ saveFileDialog1;
private: System::Windows::Forms::ToolStripMenuItem^ mnuSchriftart;
private: System::Windows::Forms::FontDialog^ fontDialog1;
private: System::Windows::Forms::ToolStripMenuItem^ mnuRichtextBox;
private: System::Windows::Forms::ToolStripMenuItem^ mnuFolderBrowser;
private: System::Windows::Forms::FolderBrowserDialog^ folderBrowserDialog1;
private: System::Windows::Forms::ContextMenuStrip^ contextMenuStrip1;
private: System::Windows::Forms::ToolStripMenuItem^ mnuClearText;
private: System::Windows::Forms::ToolStripMenuItem^ mnuOpen;
private: System::Windows::Forms::ToolStripMenuItem^ mnuSave;
private: System::Windows::Forms::DateTimePicker^ dateTimePicker1;
private: System::Windows::Forms::ToolStripMenuItem^ toolStripMenuItem4;
private: System::Windows::Forms::ToolStripMenuItem^ mnuButtonsHerstellen;
private: System::Windows::Forms::ToolStripMenuItem^ mnuListControls;
private: System::Windows::Forms::ToolStripMenuItem^ mnuTextBoxenHerstellen;
private: System::Windows::Forms::Button^ btnAddDoubles;
private: System::Windows::Forms::Label^ label1;
private: System::Windows::Forms::TextBox^ txtZweiteZahl;
private: System::Windows::Forms::TextBox^ txtErsteZahl;
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel2;
private: System::Windows::Forms::Panel^ panel4;
private: System::Windows::Forms::Button^ btnArrayList;
private: System::Windows::Forms::TextBox^ txtCollections;
private: System::Windows::Forms::Button^ btnQueue;
private: System::Windows::Forms::Button^ btnStack;
private: System::Windows::Forms::Button^ btnSortedList;
private: System::Windows::Forms::Button^ btnHashtable;
private: System::Windows::Forms::Button^ btnList;
private: System::Windows::Forms::Button^ btnArray;
private: System::Windows::Forms::Button^ btnBenchmark;
private: System::Windows::Forms::TabPage^ tabPage4;
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel3;
private: System::Windows::Forms::Panel^ pnlDrawing;
private: System::Windows::Forms::Panel^ pnlGraphics;
private: System::Windows::Forms::Button^ btnDrawLine;
private: System::Windows::Forms::Button^ btnTranslatePoints;
private: System::Windows::Forms::PictureBox^ pictureBox2;
private: System::Windows::Forms::Button^ btnDrawImage;
private: System::Windows::Forms::Button^ btnDrawHouse;
private: System::Windows::Forms::Button^ btnDivide;
private: System::Windows::Forms::TabPage^ tabPage5;
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel4;
private: System::Windows::Forms::TextBox^ textBox2;
private: System::Windows::Forms::Panel^ panel5;
private: BlinkinButton^ btnBlinkinButton;
private: System::Windows::Forms::Panel^ panel6;
private: DrawingPanel^ pnlHouse;
private: System::Windows::Forms::TabPage^ tabPage6;
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel5;
private: System::Windows::Forms::Panel^ panel8;
private: System::Windows::Forms::TextBox^ txtTreeView;
private: System::Windows::Forms::TreeView^ treeView1;
private: System::Windows::Forms::Panel^ panel7;
private: System::Windows::Forms::Button^ btnAddTreeNodeToTreeView;
private: System::Windows::Forms::Button^ btnRemoveTreeNOde;
private: System::Windows::Forms::Button^ btnReadDirectories;
private: System::Windows::Forms::Button^ btnRecursion;
private: System::Windows::Forms::Button^ btnRegex;
private: System::Windows::Forms::TextBox^ txtRegex;
private: System::Windows::Forms::TextBox^ txtRegexExpr;
private: RegexTextBox^ txtAutoRegexMatcher;
private: System::Windows::Forms::Button^ btnChangeRegexInRegexTextBox;
private: System::Windows::Forms::Button^ btnWalkTreeViewRecursive;
private: System::Windows::Forms::Button^ btnDriveInfo;
private: System::Windows::Forms::TabPage^ tabPage7;
private: System::Windows::Forms::TableLayoutPanel^ tableLayoutPanel6;
private: System::Windows::Forms::TreeView^ trvDirectories;
private: System::Windows::Forms::ListView^ lsvFiles;
private: System::Windows::Forms::ToolStripMenuItem^ mnuRefreshTreeView;
private: System::ComponentModel::IContainer^ components;
protected:
private:
/// <summary>
/// Erforderliche Designervariable.
/// </summary>
#pragma region Windows Form Designer generated code
/// <summary>
/// Erforderliche Methode für die Designerunterstützung.
/// Der Inhalt der Methode darf nicht mit dem Code-Editor geändert werden.
/// </summary>
void InitializeComponent(void)
{
this->components = (gcnew System::ComponentModel::Container());
System::ComponentModel::ComponentResourceManager^ resources = (gcnew System::ComponentModel::ComponentResourceManager(MainForm::typeid));
System::Windows::Forms::TreeNode^ treeNode1 = (gcnew System::Windows::Forms::TreeNode(L"Knoten7"));
System::Windows::Forms::TreeNode^ treeNode2 = (gcnew System::Windows::Forms::TreeNode(L"Knoten8"));
System::Windows::Forms::TreeNode^ treeNode3 = (gcnew System::Windows::Forms::TreeNode(L"Knoten9"));
System::Windows::Forms::TreeNode^ treeNode4 = (gcnew System::Windows::Forms::TreeNode(L"Knoten15"));
System::Windows::Forms::TreeNode^ treeNode5 = (gcnew System::Windows::Forms::TreeNode(L"Knoten16"));
System::Windows::Forms::TreeNode^ treeNode6 = (gcnew System::Windows::Forms::TreeNode(L"Knoten21"));
System::Windows::Forms::TreeNode^ treeNode7 = (gcnew System::Windows::Forms::TreeNode(L"Knoten22"));
System::Windows::Forms::TreeNode^ treeNode8 = (gcnew System::Windows::Forms::TreeNode(L"Knoten26"));
System::Windows::Forms::TreeNode^ treeNode9 = (gcnew System::Windows::Forms::TreeNode(L"Knoten27"));
System::Windows::Forms::TreeNode^ treeNode10 = (gcnew System::Windows::Forms::TreeNode(L"Knoten28"));
System::Windows::Forms::TreeNode^ treeNode11 = (gcnew System::Windows::Forms::TreeNode(L"Knoten29"));
System::Windows::Forms::TreeNode^ treeNode12 = (gcnew System::Windows::Forms::TreeNode(L"Knoten30"));
System::Windows::Forms::TreeNode^ treeNode13 = (gcnew System::Windows::Forms::TreeNode(L"Knoten31"));
System::Windows::Forms::TreeNode^ treeNode14 = (gcnew System::Windows::Forms::TreeNode(L"Knoten32"));
System::Windows::Forms::TreeNode^ treeNode15 = (gcnew System::Windows::Forms::TreeNode(L"Knoten33"));
System::Windows::Forms::TreeNode^ treeNode16 = (gcnew System::Windows::Forms::TreeNode(L"Knoten34"));
System::Windows::Forms::TreeNode^ treeNode17 = (gcnew System::Windows::Forms::TreeNode(L"Knoten23", gcnew cli::array< System::Windows::Forms::TreeNode^ >(9)
{
treeNode8,
treeNode9, treeNode10, treeNode11, treeNode12, treeNode13, treeNode14, treeNode15, treeNode16
}));
System::Windows::Forms::TreeNode^ treeNode18 = (gcnew System::Windows::Forms::TreeNode(L"Knoten24"));
System::Windows::Forms::TreeNode^ treeNode19 = (gcnew System::Windows::Forms::TreeNode(L"Knoten25"));
System::Windows::Forms::TreeNode^ treeNode20 = (gcnew System::Windows::Forms::TreeNode(L"Knoten17", gcnew cli::array< System::Windows::Forms::TreeNode^ >(5)
{
treeNode6,
treeNode7, treeNode17, treeNode18, treeNode19
}));
System::Windows::Forms::TreeNode^ treeNode21 = (gcnew System::Windows::Forms::TreeNode(L"Knoten18"));
System::Windows::Forms::TreeNode^ treeNode22 = (gcnew System::Windows::Forms::TreeNode(L"Knoten19"));
System::Windows::Forms::TreeNode^ treeNode23 = (gcnew System::Windows::Forms::TreeNode(L"Knoten20"));
System::Windows::Forms::TreeNode^ treeNode24 = (gcnew System::Windows::Forms::TreeNode(L"Knoten10", gcnew cli::array< System::Windows::Forms::TreeNode^ >(6)
{
treeNode4,
treeNode5, treeNode20, treeNode21, treeNode22, treeNode23
}));
System::Windows::Forms::TreeNode^ treeNode25 = (gcnew System::Windows::Forms::TreeNode(L"Knoten11"));
System::Windows::Forms::TreeNode^ treeNode26 = (gcnew System::Windows::Forms::TreeNode(L"Knoten12"));
System::Windows::Forms::TreeNode^ treeNode27 = (gcnew System::Windows::Forms::TreeNode(L"Knoten13"));
System::Windows::Forms::TreeNode^ treeNode28 = (gcnew System::Windows::Forms::TreeNode(L"Knoten14"));
System::Windows::Forms::TreeNode^ treeNode29 = (gcnew System::Windows::Forms::TreeNode(L"Knoten0", gcnew cli::array< System::Windows::Forms::TreeNode^ >(8)
{
treeNode1,
treeNode2, treeNode3, treeNode24, treeNode25, treeNode26, treeNode27, treeNode28
}));
this->tableLayoutPanel1 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->textBox1 = (gcnew System::Windows::Forms::TextBox());
this->contextMenuStrip1 = (gcnew System::Windows::Forms::ContextMenuStrip(this->components));
this->mnuClearText = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuOpen = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuSave = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->panel1 = (gcnew System::Windows::Forms::Panel());
this->btnStartProgress = (gcnew System::Windows::Forms::Button());
this->btnChangeFromAnotherClass = (gcnew System::Windows::Forms::Button());
this->btnComboInsert = (gcnew System::Windows::Forms::Button());
this->btnComboremoveItem = (gcnew System::Windows::Forms::Button());
this->btnComboAddItem = (gcnew System::Windows::Forms::Button());
this->btnComboboxValue = (gcnew System::Windows::Forms::Button());
this->btnRadioButton = (gcnew System::Windows::Forms::Button());
this->btnCheckbox = (gcnew System::Windows::Forms::Button());
this->btnChangeTab = (gcnew System::Windows::Forms::Button());
this->cmdChangeFormColor = (gcnew System::Windows::Forms::Button());
this->panel2 = (gcnew System::Windows::Forms::Panel());
this->dateTimePicker1 = (gcnew System::Windows::Forms::DateTimePicker());
this->trackBar1 = (gcnew System::Windows::Forms::TrackBar());
this->numericUpDown1 = (gcnew System::Windows::Forms::NumericUpDown());
this->maskedTextBox1 = (gcnew System::Windows::Forms::MaskedTextBox());
this->listBox1 = (gcnew System::Windows::Forms::ListBox());
this->cmbBlubb = (gcnew System::Windows::Forms::ComboBox());
this->groupBox1 = (gcnew System::Windows::Forms::GroupBox());
this->radioButton3 = (gcnew System::Windows::Forms::RadioButton());
this->radioButton2 = (gcnew System::Windows::Forms::RadioButton());
this->radioButton1 = (gcnew System::Windows::Forms::RadioButton());
this->checkBox1 = (gcnew System::Windows::Forms::CheckBox());
this->panel3 = (gcnew System::Windows::Forms::Panel());
this->btnDivide = (gcnew System::Windows::Forms::Button());
this->btnAddDoubles = (gcnew System::Windows::Forms::Button());
this->label1 = (gcnew System::Windows::Forms::Label());
this->txtZweiteZahl = (gcnew System::Windows::Forms::TextBox());
this->txtErsteZahl = (gcnew System::Windows::Forms::TextBox());
this->richTextBox1 = (gcnew System::Windows::Forms::RichTextBox());
this->progressBar1 = (gcnew System::Windows::Forms::ProgressBar());
this->pictureBox1 = (gcnew System::Windows::Forms::PictureBox());
this->tabControl1 = (gcnew System::Windows::Forms::TabControl());
this->tabPage1 = (gcnew System::Windows::Forms::TabPage());
this->tabPage2 = (gcnew System::Windows::Forms::TabPage());
this->tableLayoutPanel2 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->panel4 = (gcnew System::Windows::Forms::Panel());
this->btnBenchmark = (gcnew System::Windows::Forms::Button());
this->btnArray = (gcnew System::Windows::Forms::Button());
this->btnList = (gcnew System::Windows::Forms::Button());
this->btnHashtable = (gcnew System::Windows::Forms::Button());
this->btnSortedList = (gcnew System::Windows::Forms::Button());
this->btnStack = (gcnew System::Windows::Forms::Button());
this->btnQueue = (gcnew System::Windows::Forms::Button());
this->btnArrayList = (gcnew System::Windows::Forms::Button());
this->txtCollections = (gcnew System::Windows::Forms::TextBox());
this->tabPage3 = (gcnew System::Windows::Forms::TabPage());
this->txtAnswers = (gcnew System::Windows::Forms::TextBox());
this->txtQuestions = (gcnew System::Windows::Forms::TextBox());
this->btnNextStep = (gcnew System::Windows::Forms::Button());
this->tabPage4 = (gcnew System::Windows::Forms::TabPage());
this->tableLayoutPanel3 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->pnlDrawing = (gcnew System::Windows::Forms::Panel());
this->pictureBox2 = (gcnew System::Windows::Forms::PictureBox());
this->pnlGraphics = (gcnew System::Windows::Forms::Panel());
this->btnDrawHouse = (gcnew System::Windows::Forms::Button());
this->btnDrawImage = (gcnew System::Windows::Forms::Button());
this->btnTranslatePoints = (gcnew System::Windows::Forms::Button());
this->btnDrawLine = (gcnew System::Windows::Forms::Button());
this->tabPage5 = (gcnew System::Windows::Forms::TabPage());
this->tableLayoutPanel4 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->textBox2 = (gcnew System::Windows::Forms::TextBox());
this->panel5 = (gcnew System::Windows::Forms::Panel());
this->panel6 = (gcnew System::Windows::Forms::Panel());
this->tabPage6 = (gcnew System::Windows::Forms::TabPage());
this->tableLayoutPanel5 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->panel8 = (gcnew System::Windows::Forms::Panel());
this->btnChangeRegexInRegexTextBox = (gcnew System::Windows::Forms::Button());
this->txtRegexExpr = (gcnew System::Windows::Forms::TextBox());
this->txtRegex = (gcnew System::Windows::Forms::TextBox());
this->btnRegex = (gcnew System::Windows::Forms::Button());
this->txtTreeView = (gcnew System::Windows::Forms::TextBox());
this->treeView1 = (gcnew System::Windows::Forms::TreeView());
this->panel7 = (gcnew System::Windows::Forms::Panel());
this->btnDriveInfo = (gcnew System::Windows::Forms::Button());
this->btnWalkTreeViewRecursive = (gcnew System::Windows::Forms::Button());
this->btnRecursion = (gcnew System::Windows::Forms::Button());
this->btnReadDirectories = (gcnew System::Windows::Forms::Button());
this->btnRemoveTreeNOde = (gcnew System::Windows::Forms::Button());
this->btnAddTreeNodeToTreeView = (gcnew System::Windows::Forms::Button());
this->tabPage7 = (gcnew System::Windows::Forms::TabPage());
this->tableLayoutPanel6 = (gcnew System::Windows::Forms::TableLayoutPanel());
this->trvDirectories = (gcnew System::Windows::Forms::TreeView());
this->lsvFiles = (gcnew System::Windows::Forms::ListView());
this->timer1 = (gcnew System::Windows::Forms::Timer(this->components));
this->menuStrip1 = (gcnew System::Windows::Forms::MenuStrip());
this->toolStripMenuItem1 = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->toolStripMenuItem2 = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->toolStripSeparator1 = (gcnew System::Windows::Forms::ToolStripSeparator());
this->mnuSaveFileDialog = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuRichtextBox = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuFolderBrowser = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->toolStripMenuItem3 = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuFarben = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuSchriftart = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->toolStripMenuItem4 = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuButtonsHerstellen = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuListControls = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuTextBoxenHerstellen = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->mnuRefreshTreeView = (gcnew System::Windows::Forms::ToolStripMenuItem());
this->openFileDialog1 = (gcnew System::Windows::Forms::OpenFileDialog());
this->colorDialog1 = (gcnew System::Windows::Forms::ColorDialog());
this->saveFileDialog1 = (gcnew System::Windows::Forms::SaveFileDialog());
this->fontDialog1 = (gcnew System::Windows::Forms::FontDialog());
this->folderBrowserDialog1 = (gcnew System::Windows::Forms::FolderBrowserDialog());
this->tableLayoutPanel1->SuspendLayout();
this->contextMenuStrip1->SuspendLayout();
this->panel1->SuspendLayout();
this->panel2->SuspendLayout();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->trackBar1))->BeginInit();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->numericUpDown1))->BeginInit();
this->groupBox1->SuspendLayout();
this->panel3->SuspendLayout();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->pictureBox1))->BeginInit();
this->tabControl1->SuspendLayout();
this->tabPage1->SuspendLayout();
this->tabPage2->SuspendLayout();
this->tableLayoutPanel2->SuspendLayout();
this->panel4->SuspendLayout();
this->tabPage3->SuspendLayout();
this->tabPage4->SuspendLayout();
this->tableLayoutPanel3->SuspendLayout();
this->pnlDrawing->SuspendLayout();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->pictureBox2))->BeginInit();
this->pnlGraphics->SuspendLayout();
this->tabPage5->SuspendLayout();
this->tableLayoutPanel4->SuspendLayout();
this->tabPage6->SuspendLayout();
this->tableLayoutPanel5->SuspendLayout();
this->panel8->SuspendLayout();
this->panel7->SuspendLayout();
this->tabPage7->SuspendLayout();
this->tableLayoutPanel6->SuspendLayout();
this->menuStrip1->SuspendLayout();
this->SuspendLayout();
//
// tableLayoutPanel1
//
this->tableLayoutPanel1->ColumnCount = 2;
this->tableLayoutPanel1->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel1->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel1->Controls->Add(this->textBox1, 1, 0);
this->tableLayoutPanel1->Controls->Add(this->panel1, 0, 0);
this->tableLayoutPanel1->Controls->Add(this->panel2, 0, 1);
this->tableLayoutPanel1->Controls->Add(this->panel3, 1, 1);
this->tableLayoutPanel1->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel1->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel1->Name = L"tableLayoutPanel1";
this->tableLayoutPanel1->RowCount = 2;
this->tableLayoutPanel1->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 50)));
this->tableLayoutPanel1->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 50)));
this->tableLayoutPanel1->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel1->TabIndex = 3;
//
// textBox1
//
this->textBox1->ContextMenuStrip = this->contextMenuStrip1;
this->textBox1->Dock = System::Windows::Forms::DockStyle::Fill;
this->textBox1->Location = System::Drawing::Point(431, 3);
this->textBox1->Multiline = true;
this->textBox1->Name = L"textBox1";
this->textBox1->ScrollBars = System::Windows::Forms::ScrollBars::Both;
this->textBox1->Size = System::Drawing::Size(422, 282);
this->textBox1->TabIndex = 2;
//
// contextMenuStrip1
//
this->contextMenuStrip1->Items->AddRange(gcnew cli::array< System::Windows::Forms::ToolStripItem^ >(3)
{
this->mnuClearText,
this->mnuOpen, this->mnuSave
});
this->contextMenuStrip1->Name = L"contextMenuStrip1";
this->contextMenuStrip1->Size = System::Drawing::Size(160, 70);
//
// mnuClearText
//
this->mnuClearText->Name = L"mnuClearText";
this->mnuClearText->Size = System::Drawing::Size(159, 22);
this->mnuClearText->Text = L"TextBox löschen";
this->mnuClearText->Click += gcnew System::EventHandler(this, &MainForm::mnuClearText_Click);
//
// mnuOpen
//
this->mnuOpen->Name = L"mnuOpen";
this->mnuOpen->Size = System::Drawing::Size(159, 22);
this->mnuOpen->Text = L"Datei öffnen";
this->mnuOpen->Click += gcnew System::EventHandler(this, &MainForm::toolStripMenuItem2_Click);
//
// mnuSave
//
this->mnuSave->Name = L"mnuSave";
this->mnuSave->Size = System::Drawing::Size(159, 22);
this->mnuSave->Text = L"Speichern als";
this->mnuSave->Click += gcnew System::EventHandler(this, &MainForm::mnuSaveFileDialog_Click);
//
// panel1
//
this->panel1->Controls->Add(this->btnStartProgress);
this->panel1->Controls->Add(this->btnChangeFromAnotherClass);
this->panel1->Controls->Add(this->btnComboInsert);
this->panel1->Controls->Add(this->btnComboremoveItem);
this->panel1->Controls->Add(this->btnComboAddItem);
this->panel1->Controls->Add(this->btnComboboxValue);
this->panel1->Controls->Add(this->btnRadioButton);
this->panel1->Controls->Add(this->btnCheckbox);
this->panel1->Controls->Add(this->btnChangeTab);
this->panel1->Controls->Add(this->cmdChangeFormColor);
this->panel1->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel1->Location = System::Drawing::Point(3, 3);
this->panel1->Name = L"panel1";
this->panel1->Size = System::Drawing::Size(422, 282);
this->panel1->TabIndex = 1;
//
// btnStartProgress
//
this->btnStartProgress->Location = System::Drawing::Point(115, 32);
this->btnStartProgress->Name = L"btnStartProgress";
this->btnStartProgress->Size = System::Drawing::Size(109, 23);
this->btnStartProgress->TabIndex = 9;
this->btnStartProgress->Text = L"Start Progress";
this->btnStartProgress->UseVisualStyleBackColor = true;
this->btnStartProgress->Click += gcnew System::EventHandler(this, &MainForm::btnStartProgress_Click);
//
// btnChangeFromAnotherClass
//
this->btnChangeFromAnotherClass->Location = System::Drawing::Point(115, 3);
this->btnChangeFromAnotherClass->Name = L"btnChangeFromAnotherClass";
this->btnChangeFromAnotherClass->Size = System::Drawing::Size(109, 23);
this->btnChangeFromAnotherClass->TabIndex = 8;
this->btnChangeFromAnotherClass->Text = L"Class Fun";
this->btnChangeFromAnotherClass->UseVisualStyleBackColor = true;
this->btnChangeFromAnotherClass->Click += gcnew System::EventHandler(this, &MainForm::btnChangeFromAnotherClass_Click);
//
// btnComboInsert
//
this->btnComboInsert->Location = System::Drawing::Point(3, 178);
this->btnComboInsert->Name = L"btnComboInsert";
this->btnComboInsert->Size = System::Drawing::Size(109, 23);
this->btnComboInsert->TabIndex = 7;
this->btnComboInsert->Text = L"Combo insert Item";
this->btnComboInsert->UseVisualStyleBackColor = true;
this->btnComboInsert->Click += gcnew System::EventHandler(this, &MainForm::btnComboInsert_Click);
//
// btnComboremoveItem
//
this->btnComboremoveItem->Location = System::Drawing::Point(4, 207);
this->btnComboremoveItem->Name = L"btnComboremoveItem";
this->btnComboremoveItem->Size = System::Drawing::Size(109, 23);
this->btnComboremoveItem->TabIndex = 6;
this->btnComboremoveItem->Text = L"Combo remove Item";
this->btnComboremoveItem->UseVisualStyleBackColor = true;
this->btnComboremoveItem->Click += gcnew System::EventHandler(this, &MainForm::btnComboremoveItem_Click);
//
// btnComboAddItem
//
this->btnComboAddItem->Location = System::Drawing::Point(3, 149);
this->btnComboAddItem->Name = L"btnComboAddItem";
this->btnComboAddItem->Size = System::Drawing::Size(96, 23);
this->btnComboAddItem->TabIndex = 5;
this->btnComboAddItem->Text = L"Combo Add Item";
this->btnComboAddItem->UseVisualStyleBackColor = true;
this->btnComboAddItem->Click += gcnew System::EventHandler(this, &MainForm::btnComboAddItem_Click);
//
// btnComboboxValue
//
this->btnComboboxValue->Location = System::Drawing::Point(4, 120);
this->btnComboboxValue->Name = L"btnComboboxValue";
this->btnComboboxValue->Size = System::Drawing::Size(96, 23);
this->btnComboboxValue->TabIndex = 4;
this->btnComboboxValue->Text = L"Combo Value";
this->btnComboboxValue->UseVisualStyleBackColor = true;
this->btnComboboxValue->Click += gcnew System::EventHandler(this, &MainForm::btnComboboxValue_Click);
//
// btnRadioButton
//
this->btnRadioButton->Location = System::Drawing::Point(4, 91);
this->btnRadioButton->Name = L"btnRadioButton";
this->btnRadioButton->Size = System::Drawing::Size(96, 23);
this->btnRadioButton->TabIndex = 3;
this->btnRadioButton->Text = L"Radiobutton";
this->btnRadioButton->UseVisualStyleBackColor = true;
this->btnRadioButton->Click += gcnew System::EventHandler(this, &MainForm::btnRadioButton_Click);
//
// btnCheckbox
//
this->btnCheckbox->Location = System::Drawing::Point(4, 62);
this->btnCheckbox->Name = L"btnCheckbox";
this->btnCheckbox->Size = System::Drawing::Size(96, 23);
this->btnCheckbox->TabIndex = 2;
this->btnCheckbox->Text = L"Checkbox";
this->btnCheckbox->UseVisualStyleBackColor = true;
this->btnCheckbox->Click += gcnew System::EventHandler(this, &MainForm::btnCheckbox_Click);
//
// btnChangeTab
//
this->btnChangeTab->Location = System::Drawing::Point(3, 32);
this->btnChangeTab->Name = L"btnChangeTab";
this->btnChangeTab->Size = System::Drawing::Size(97, 23);
this->btnChangeTab->TabIndex = 1;
this->btnChangeTab->Text = L"Change Tab";
this->btnChangeTab->UseVisualStyleBackColor = true;
this->btnChangeTab->Click += gcnew System::EventHandler(this, &MainForm::btnChangeTab_Click);
//
// cmdChangeFormColor
//
this->cmdChangeFormColor->Location = System::Drawing::Point(3, 3);
this->cmdChangeFormColor->Name = L"cmdChangeFormColor";
this->cmdChangeFormColor->Size = System::Drawing::Size(97, 23);
this->cmdChangeFormColor->TabIndex = 0;
this->cmdChangeFormColor->Text = L"Change Color";
this->cmdChangeFormColor->UseVisualStyleBackColor = true;
this->cmdChangeFormColor->Click += gcnew System::EventHandler(this, &MainForm::cmdChangeFormColor_Click);
//
// panel2
//
this->panel2->Controls->Add(this->dateTimePicker1);
this->panel2->Controls->Add(this->trackBar1);
this->panel2->Controls->Add(this->numericUpDown1);
this->panel2->Controls->Add(this->maskedTextBox1);
this->panel2->Controls->Add(this->listBox1);
this->panel2->Controls->Add(this->cmbBlubb);
this->panel2->Controls->Add(this->groupBox1);
this->panel2->Controls->Add(this->checkBox1);
this->panel2->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel2->Location = System::Drawing::Point(3, 291);
this->panel2->Name = L"panel2";
this->panel2->Size = System::Drawing::Size(422, 282);
this->panel2->TabIndex = 3;
//
// dateTimePicker1
//
this->dateTimePicker1->Location = System::Drawing::Point(24, 205);
this->dateTimePicker1->Name = L"dateTimePicker1";
this->dateTimePicker1->Size = System::Drawing::Size(200, 20);
this->dateTimePicker1->TabIndex = 10;
this->dateTimePicker1->ValueChanged += gcnew System::EventHandler(this, &MainForm::dateTimePicker1_ValueChanged);
//
// trackBar1
//
this->trackBar1->Location = System::Drawing::Point(10, 158);
this->trackBar1->Name = L"trackBar1";
this->trackBar1->Size = System::Drawing::Size(104, 45);
this->trackBar1->TabIndex = 9;
this->trackBar1->Scroll += gcnew System::EventHandler(this, &MainForm::trackBar1_Scroll);
//
// numericUpDown1
//
this->numericUpDown1->Increment = System::Decimal(gcnew cli::array< System::Int32 >(4) { 2, 0, 0, 0 });
this->numericUpDown1->Location = System::Drawing::Point(191, 132);
this->numericUpDown1->Minimum = System::Decimal(gcnew cli::array< System::Int32 >(4) { 5, 0, 0, 0 });
this->numericUpDown1->Name = L"numericUpDown1";
this->numericUpDown1->Size = System::Drawing::Size(79, 20);
this->numericUpDown1->TabIndex = 8;
this->numericUpDown1->Value = System::Decimal(gcnew cli::array< System::Int32 >(4) { 5, 0, 0, 0 });
//
// maskedTextBox1
//
this->maskedTextBox1->Location = System::Drawing::Point(4, 131);
this->maskedTextBox1->Mask = L"00/00/0000 00:00";
this->maskedTextBox1->Name = L"maskedTextBox1";
this->maskedTextBox1->Size = System::Drawing::Size(172, 20);
this->maskedTextBox1->TabIndex = 7;
this->maskedTextBox1->ValidatingType = System::DateTime::typeid;
//
// listBox1
//
this->listBox1->FormattingEnabled = true;
this->listBox1->Items->AddRange(gcnew cli::array< System::Object^ >(4) { L"Bli", L"Bla", L"Blubb", L"Trallallaaaaaa" });
this->listBox1->Location = System::Drawing::Point(133, 30);
this->listBox1->Name = L"listBox1";
this->listBox1->SelectionMode = System::Windows::Forms::SelectionMode::MultiSimple;
this->listBox1->Size = System::Drawing::Size(137, 95);
this->listBox1->TabIndex = 6;
this->listBox1->SelectedIndexChanged += gcnew System::EventHandler(this, &MainForm::listBox1_SelectedIndexChanged);
//
// cmbBlubb
//
this->cmbBlubb->DropDownStyle = System::Windows::Forms::ComboBoxStyle::DropDownList;
this->cmbBlubb->FormattingEnabled = true;
this->cmbBlubb->Items->AddRange(gcnew cli::array< System::Object^ >(5) { L"Bli", L"Bla", L"Blubb", L"Trallalla", L"Whooop" });
this->cmbBlubb->Location = System::Drawing::Point(133, 3);
this->cmbBlubb->Name = L"cmbBlubb";
this->cmbBlubb->Size = System::Drawing::Size(137, 21);
this->cmbBlubb->TabIndex = 5;
this->cmbBlubb->SelectedIndexChanged += gcnew System::EventHandler(this, &MainForm::cmbBlubb_SelectedIndexChanged);
//
// groupBox1
//
this->groupBox1->Controls->Add(this->radioButton3);
this->groupBox1->Controls->Add(this->radioButton2);
this->groupBox1->Controls->Add(this->radioButton1);
this->groupBox1->Location = System::Drawing::Point(4, 26);
this->groupBox1->Name = L"groupBox1";
this->groupBox1->Size = System::Drawing::Size(113, 91);
this->groupBox1->TabIndex = 4;
this->groupBox1->TabStop = false;
this->groupBox1->Text = L"groupBox1";
//
// radioButton3
//
this->radioButton3->AutoSize = true;
this->radioButton3->Location = System::Drawing::Point(6, 65);
this->radioButton3->Name = L"radioButton3";
this->radioButton3->Size = System::Drawing::Size(85, 17);
this->radioButton3->TabIndex = 3;
this->radioButton3->TabStop = true;
this->radioButton3->Text = L"radioButton3";
this->radioButton3->UseVisualStyleBackColor = true;
//
// radioButton2
//
this->radioButton2->AutoSize = true;
this->radioButton2->Location = System::Drawing::Point(6, 42);
this->radioButton2->Name = L"radioButton2";
this->radioButton2->Size = System::Drawing::Size(85, 17);
this->radioButton2->TabIndex = 2;
this->radioButton2->TabStop = true;
this->radioButton2->Text = L"radioButton2";
this->radioButton2->UseVisualStyleBackColor = true;
//
// radioButton1
//
this->radioButton1->AutoSize = true;
this->radioButton1->Location = System::Drawing::Point(6, 19);
this->radioButton1->Name = L"radioButton1";
this->radioButton1->Size = System::Drawing::Size(85, 17);
this->radioButton1->TabIndex = 1;
this->radioButton1->TabStop = true;
this->radioButton1->Text = L"radioButton1";
this->radioButton1->UseVisualStyleBackColor = true;
//
// checkBox1
//
this->checkBox1->AutoSize = true;
this->checkBox1->Location = System::Drawing::Point(3, 3);
this->checkBox1->Name = L"checkBox1";
this->checkBox1->Size = System::Drawing::Size(80, 17);
this->checkBox1->TabIndex = 0;
this->checkBox1->Text = L"checkBox1";
this->checkBox1->UseVisualStyleBackColor = true;
this->checkBox1->CheckedChanged += gcnew System::EventHandler(this, &MainForm::checkBox1_CheckedChanged);
//
// panel3
//
this->panel3->Controls->Add(this->btnDivide);
this->panel3->Controls->Add(this->btnAddDoubles);
this->panel3->Controls->Add(this->label1);
this->panel3->Controls->Add(this->txtZweiteZahl);
this->panel3->Controls->Add(this->txtErsteZahl);
this->panel3->Controls->Add(this->richTextBox1);
this->panel3->Controls->Add(this->progressBar1);
this->panel3->Controls->Add(this->pictureBox1);
this->panel3->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel3->Location = System::Drawing::Point(431, 291);
this->panel3->Name = L"panel3";
this->panel3->Size = System::Drawing::Size(422, 282);
this->panel3->TabIndex = 4;
//
// btnDivide
//
this->btnDivide->Location = System::Drawing::Point(107, 196);
this->btnDivide->Name = L"btnDivide";
this->btnDivide->Size = System::Drawing::Size(30, 23);
this->btnDivide->TabIndex = 11;
this->btnDivide->Text = L"/";
this->btnDivide->UseVisualStyleBackColor = true;
this->btnDivide->Click += gcnew System::EventHandler(this, &MainForm::btnDivide_Click);
//
// btnAddDoubles
//
this->btnAddDoubles->Location = System::Drawing::Point(240, 167);
this->btnAddDoubles->Name = L"btnAddDoubles";
this->btnAddDoubles->Size = System::Drawing::Size(30, 23);
this->btnAddDoubles->TabIndex = 10;
this->btnAddDoubles->Text = L"=";
this->btnAddDoubles->UseVisualStyleBackColor = true;
this->btnAddDoubles->Click += gcnew System::EventHandler(this, &MainForm::btnAddDoubles_Click);
//
// label1
//
this->label1->AutoSize = true;
this->label1->Location = System::Drawing::Point(124, 173);
this->label1->Name = L"label1";
this->label1->Size = System::Drawing::Size(13, 13);
this->label1->TabIndex = 5;
this->label1->Text = L"+";
//
// txtZweiteZahl
//
this->txtZweiteZahl->Location = System::Drawing::Point(138, 170);
this->txtZweiteZahl->Name = L"txtZweiteZahl";
this->txtZweiteZahl->Size = System::Drawing::Size(100, 20);
this->txtZweiteZahl->TabIndex = 4;
//
// txtErsteZahl
//
this->txtErsteZahl->Location = System::Drawing::Point(18, 170);
this->txtErsteZahl->Name = L"txtErsteZahl";
this->txtErsteZahl->Size = System::Drawing::Size(100, 20);
this->txtErsteZahl->TabIndex = 3;
//
// richTextBox1
//
this->richTextBox1->Location = System::Drawing::Point(93, 29);
this->richTextBox1->Name = L"richTextBox1";
this->richTextBox1->Size = System::Drawing::Size(177, 88);
this->richTextBox1->TabIndex = 2;
this->richTextBox1->Text = L"";
//
// progressBar1
//
this->progressBar1->Location = System::Drawing::Point(93, 3);
this->progressBar1->Name = L"progressBar1";
this->progressBar1->Size = System::Drawing::Size(177, 14);
this->progressBar1->Style = System::Windows::Forms::ProgressBarStyle::Continuous;
this->progressBar1->TabIndex = 1;
this->progressBar1->Value = 40;
//
// pictureBox1
//
this->pictureBox1->Image = (cli::safe_cast<System::Drawing::Image^>(resources->GetObject(L"pictureBox1.Image")));
this->pictureBox1->Location = System::Drawing::Point(3, 3);
this->pictureBox1->Name = L"pictureBox1";
this->pictureBox1->Size = System::Drawing::Size(84, 82);
this->pictureBox1->SizeMode = System::Windows::Forms::PictureBoxSizeMode::StretchImage;
this->pictureBox1->TabIndex = 0;
this->pictureBox1->TabStop = false;
//
// tabControl1
//
this->tabControl1->Controls->Add(this->tabPage1);
this->tabControl1->Controls->Add(this->tabPage2);
this->tabControl1->Controls->Add(this->tabPage3);
this->tabControl1->Controls->Add(this->tabPage4);
this->tabControl1->Controls->Add(this->tabPage5);
this->tabControl1->Controls->Add(this->tabPage6);
this->tabControl1->Controls->Add(this->tabPage7);
this->tabControl1->Dock = System::Windows::Forms::DockStyle::Fill;
this->tabControl1->Location = System::Drawing::Point(0, 24);
this->tabControl1->Name = L"tabControl1";
this->tabControl1->SelectedIndex = 0;
this->tabControl1->Size = System::Drawing::Size(870, 608);
this->tabControl1->TabIndex = 4;
//
// tabPage1
//
this->tabPage1->Controls->Add(this->tableLayoutPanel1);
this->tabPage1->Location = System::Drawing::Point(4, 22);
this->tabPage1->Name = L"tabPage1";
this->tabPage1->Padding = System::Windows::Forms::Padding(3);
this->tabPage1->Size = System::Drawing::Size(862, 582);
this->tabPage1->TabIndex = 0;
this->tabPage1->Text = L"Basics";
this->tabPage1->UseVisualStyleBackColor = true;
//
// tabPage2
//
this->tabPage2->Controls->Add(this->tableLayoutPanel2);
this->tabPage2->Location = System::Drawing::Point(4, 22);
this->tabPage2->Name = L"tabPage2";
this->tabPage2->Padding = System::Windows::Forms::Padding(3);
this->tabPage2->Size = System::Drawing::Size(862, 582);
this->tabPage2->TabIndex = 1;
this->tabPage2->Text = L"Other";
this->tabPage2->UseVisualStyleBackColor = true;
//
// tableLayoutPanel2
//
this->tableLayoutPanel2->ColumnCount = 2;
this->tableLayoutPanel2->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel2->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel2->Controls->Add(this->panel4, 0, 0);
this->tableLayoutPanel2->Controls->Add(this->txtCollections, 1, 0);
this->tableLayoutPanel2->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel2->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel2->Name = L"tableLayoutPanel2";
this->tableLayoutPanel2->RowCount = 1;
this->tableLayoutPanel2->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 50)));
this->tableLayoutPanel2->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel2->TabIndex = 0;
//
// panel4
//
this->panel4->Controls->Add(this->btnBenchmark);
this->panel4->Controls->Add(this->btnArray);
this->panel4->Controls->Add(this->btnList);
this->panel4->Controls->Add(this->btnHashtable);
this->panel4->Controls->Add(this->btnSortedList);
this->panel4->Controls->Add(this->btnStack);
this->panel4->Controls->Add(this->btnQueue);
this->panel4->Controls->Add(this->btnArrayList);
this->panel4->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel4->Location = System::Drawing::Point(3, 3);
this->panel4->Name = L"panel4";
this->panel4->Size = System::Drawing::Size(422, 570);
this->panel4->TabIndex = 0;
//
// btnBenchmark
//
this->btnBenchmark->Location = System::Drawing::Point(4, 207);
this->btnBenchmark->Name = L"btnBenchmark";
this->btnBenchmark->Size = System::Drawing::Size(121, 23);
this->btnBenchmark->TabIndex = 8;
this->btnBenchmark->Text = L"Benchmark";
this->btnBenchmark->UseVisualStyleBackColor = true;
this->btnBenchmark->Click += gcnew System::EventHandler(this, &MainForm::btnBenchmark_Click);
//
// btnArray
//
this->btnArray->Location = System::Drawing::Point(4, 178);
this->btnArray->Name = L"btnArray";
this->btnArray->Size = System::Drawing::Size(121, 23);
this->btnArray->TabIndex = 7;
this->btnArray->Text = L"array";
this->btnArray->UseVisualStyleBackColor = true;
this->btnArray->Click += gcnew System::EventHandler(this, &MainForm::btnArray_Click);
//
// btnList
//
this->btnList->Location = System::Drawing::Point(4, 149);
this->btnList->Name = L"btnList";
this->btnList->Size = System::Drawing::Size(121, 23);
this->btnList->TabIndex = 6;
this->btnList->Text = L"List";
this->btnList->UseVisualStyleBackColor = true;
this->btnList->Click += gcnew System::EventHandler(this, &MainForm::btnList_Click);
//
// btnHashtable
//
this->btnHashtable->Location = System::Drawing::Point(4, 120);
this->btnHashtable->Name = L"btnHashtable";
this->btnHashtable->Size = System::Drawing::Size(121, 23);
this->btnHashtable->TabIndex = 4;
this->btnHashtable->Text = L"HashTable";
this->btnHashtable->UseVisualStyleBackColor = true;
this->btnHashtable->Click += gcnew System::EventHandler(this, &MainForm::btnHashtable_Click);
//
// btnSortedList
//
this->btnSortedList->Location = System::Drawing::Point(4, 91);
this->btnSortedList->Name = L"btnSortedList";
this->btnSortedList->Size = System::Drawing::Size(121, 23);
this->btnSortedList->TabIndex = 3;
this->btnSortedList->Text = L"SortedList";
this->btnSortedList->UseVisualStyleBackColor = true;
this->btnSortedList->Click += gcnew System::EventHandler(this, &MainForm::btnSortedList_Click);
//
// btnStack
//
this->btnStack->Location = System::Drawing::Point(4, 62);
this->btnStack->Name = L"btnStack";
this->btnStack->Size = System::Drawing::Size(121, 23);
this->btnStack->TabIndex = 2;
this->btnStack->Text = L"Stack";
this->btnStack->UseVisualStyleBackColor = true;
this->btnStack->Click += gcnew System::EventHandler(this, &MainForm::btnStack_Click);
//
// btnQueue
//
this->btnQueue->Location = System::Drawing::Point(4, 33);
this->btnQueue->Name = L"btnQueue";
this->btnQueue->Size = System::Drawing::Size(121, 23);
this->btnQueue->TabIndex = 1;
this->btnQueue->Text = L"Queue";
this->btnQueue->UseVisualStyleBackColor = true;
this->btnQueue->Click += gcnew System::EventHandler(this, &MainForm::btnQueue_Click);
//
// btnArrayList
//
this->btnArrayList->Location = System::Drawing::Point(4, 4);
this->btnArrayList->Name = L"btnArrayList";
this->btnArrayList->Size = System::Drawing::Size(121, 23);
this->btnArrayList->TabIndex = 0;
this->btnArrayList->Text = L"ArrayList";
this->btnArrayList->UseVisualStyleBackColor = true;
this->btnArrayList->Click += gcnew System::EventHandler(this, &MainForm::btnArrayList_Click);
//
// txtCollections
//
this->txtCollections->Dock = System::Windows::Forms::DockStyle::Fill;
this->txtCollections->Location = System::Drawing::Point(431, 3);
this->txtCollections->Multiline = true;
this->txtCollections->Name = L"txtCollections";
this->txtCollections->Size = System::Drawing::Size(422, 570);
this->txtCollections->TabIndex = 1;
//
// tabPage3
//
this->tabPage3->Controls->Add(this->txtAnswers);
this->tabPage3->Controls->Add(this->txtQuestions);
this->tabPage3->Controls->Add(this->btnNextStep);
this->tabPage3->Location = System::Drawing::Point(4, 22);
this->tabPage3->Name = L"tabPage3";
this->tabPage3->Padding = System::Windows::Forms::Padding(3);
this->tabPage3->Size = System::Drawing::Size(862, 582);
this->tabPage3->TabIndex = 2;
this->tabPage3->Text = L"Quiz";
this->tabPage3->UseVisualStyleBackColor = true;
//
// txtAnswers
//
this->txtAnswers->Location = System::Drawing::Point(288, 231);
this->txtAnswers->Multiline = true;
this->txtAnswers->Name = L"txtAnswers";
this->txtAnswers->Size = System::Drawing::Size(268, 203);
this->txtAnswers->TabIndex = 2;
//
// txtQuestions
//
this->txtQuestions->Location = System::Drawing::Point(288, 4);
this->txtQuestions->Multiline = true;
this->txtQuestions->Name = L"txtQuestions";
this->txtQuestions->Size = System::Drawing::Size(268, 203);
this->txtQuestions->TabIndex = 1;
//
// btnNextStep
//
this->btnNextStep->Location = System::Drawing::Point(7, 7);
this->btnNextStep->Name = L"btnNextStep";
this->btnNextStep->Size = System::Drawing::Size(75, 23);
this->btnNextStep->TabIndex = 0;
this->btnNextStep->Text = L"Next";
this->btnNextStep->UseVisualStyleBackColor = true;
this->btnNextStep->Click += gcnew System::EventHandler(this, &MainForm::btnNextStep_Click);
//
// tabPage4
//
this->tabPage4->Controls->Add(this->tableLayoutPanel3);
this->tabPage4->Location = System::Drawing::Point(4, 22);
this->tabPage4->Name = L"tabPage4";
this->tabPage4->Padding = System::Windows::Forms::Padding(3);
this->tabPage4->Size = System::Drawing::Size(862, 582);
this->tabPage4->TabIndex = 3;
this->tabPage4->Text = L"Graphics";
this->tabPage4->UseVisualStyleBackColor = true;
//
// tableLayoutPanel3
//
this->tableLayoutPanel3->ColumnCount = 2;
this->tableLayoutPanel3->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel3->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel3->Controls->Add(this->pnlDrawing, 1, 0);
this->tableLayoutPanel3->Controls->Add(this->pnlGraphics, 0, 0);
this->tableLayoutPanel3->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel3->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel3->Name = L"tableLayoutPanel3";
this->tableLayoutPanel3->RowCount = 1;
this->tableLayoutPanel3->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 50)));
this->tableLayoutPanel3->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel3->TabIndex = 0;
//
// pnlDrawing
//
this->pnlDrawing->BackColor = System::Drawing::Color::Gainsboro;
this->pnlDrawing->Controls->Add(this->pictureBox2);
this->pnlDrawing->Dock = System::Windows::Forms::DockStyle::Fill;
this->pnlDrawing->Location = System::Drawing::Point(431, 3);
this->pnlDrawing->Name = L"pnlDrawing";
this->pnlDrawing->Size = System::Drawing::Size(422, 570);
this->pnlDrawing->TabIndex = 0;
this->pnlDrawing->Click += gcnew System::EventHandler(this, &MainForm::pnlDrawing_Click);
//
// pictureBox2
//
this->pictureBox2->Dock = System::Windows::Forms::DockStyle::Fill;
this->pictureBox2->Image = (cli::safe_cast<System::Drawing::Image^>(resources->GetObject(L"pictureBox2.Image")));
this->pictureBox2->Location = System::Drawing::Point(0, 0);
this->pictureBox2->Name = L"pictureBox2";
this->pictureBox2->Size = System::Drawing::Size(422, 570);
this->pictureBox2->TabIndex = 0;
this->pictureBox2->TabStop = false;
this->pictureBox2->Click += gcnew System::EventHandler(this, &MainForm::pnlDrawing_Click);
this->pictureBox2->Paint += gcnew System::Windows::Forms::PaintEventHandler(this, &MainForm::pnlDrawing_Paint);
//
// pnlGraphics
//
this->pnlGraphics->Controls->Add(this->btnDrawHouse);
this->pnlGraphics->Controls->Add(this->btnDrawImage);
this->pnlGraphics->Controls->Add(this->btnTranslatePoints);
this->pnlGraphics->Controls->Add(this->btnDrawLine);
this->pnlGraphics->Dock = System::Windows::Forms::DockStyle::Fill;
this->pnlGraphics->Location = System::Drawing::Point(3, 3);
this->pnlGraphics->Name = L"pnlGraphics";
this->pnlGraphics->Size = System::Drawing::Size(422, 570);
this->pnlGraphics->TabIndex = 1;
//
// btnDrawHouse
//
this->btnDrawHouse->Location = System::Drawing::Point(3, 90);
this->btnDrawHouse->Name = L"btnDrawHouse";
this->btnDrawHouse->Size = System::Drawing::Size(75, 23);
this->btnDrawHouse->TabIndex = 3;
this->btnDrawHouse->Text = L"Draw House";
this->btnDrawHouse->UseVisualStyleBackColor = true;
this->btnDrawHouse->Click += gcnew System::EventHandler(this, &MainForm::btnDrawHouse_Click);
//
// btnDrawImage
//
this->btnDrawImage->Location = System::Drawing::Point(3, 61);
this->btnDrawImage->Name = L"btnDrawImage";
this->btnDrawImage->Size = System::Drawing::Size(75, 23);
this->btnDrawImage->TabIndex = 2;
this->btnDrawImage->Text = L"Draw Image";
this->btnDrawImage->UseVisualStyleBackColor = true;
this->btnDrawImage->Click += gcnew System::EventHandler(this, &MainForm::btnDrawImage_Click);
//
// btnTranslatePoints
//
this->btnTranslatePoints->Location = System::Drawing::Point(3, 32);
this->btnTranslatePoints->Name = L"btnTranslatePoints";
this->btnTranslatePoints->Size = System::Drawing::Size(75, 23);
this->btnTranslatePoints->TabIndex = 1;
this->btnTranslatePoints->Text = L"Zoom";
this->btnTranslatePoints->UseVisualStyleBackColor = true;
this->btnTranslatePoints->Click += gcnew System::EventHandler(this, &MainForm::btnTranslatePoints_Click);
//
// btnDrawLine
//
this->btnDrawLine->Location = System::Drawing::Point(3, 3);
this->btnDrawLine->Name = L"btnDrawLine";
this->btnDrawLine->Size = System::Drawing::Size(75, 23);
this->btnDrawLine->TabIndex = 0;
this->btnDrawLine->Text = L"Draw Line";
this->btnDrawLine->UseVisualStyleBackColor = true;
this->btnDrawLine->Click += gcnew System::EventHandler(this, &MainForm::btnDrawLine_Click);
//
// tabPage5
//
this->tabPage5->Controls->Add(this->tableLayoutPanel4);
this->tabPage5->Location = System::Drawing::Point(4, 22);
this->tabPage5->Name = L"tabPage5";
this->tabPage5->Padding = System::Windows::Forms::Padding(3);
this->tabPage5->Size = System::Drawing::Size(862, 582);
this->tabPage5->TabIndex = 4;
this->tabPage5->Text = L"Own Components";
this->tabPage5->UseVisualStyleBackColor = true;
//
// tableLayoutPanel4
//
this->tableLayoutPanel4->ColumnCount = 2;
this->tableLayoutPanel4->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel4->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel4->Controls->Add(this->textBox2, 1, 0);
this->tableLayoutPanel4->Controls->Add(this->panel5, 0, 0);
this->tableLayoutPanel4->Controls->Add(this->panel6, 0, 1);
this->tableLayoutPanel4->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel4->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel4->Name = L"tableLayoutPanel4";
this->tableLayoutPanel4->RowCount = 2;
this->tableLayoutPanel4->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 22.91667F)));
this->tableLayoutPanel4->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 77.08334F)));
this->tableLayoutPanel4->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel4->TabIndex = 0;
//
// textBox2
//
this->textBox2->Dock = System::Windows::Forms::DockStyle::Fill;
this->textBox2->Location = System::Drawing::Point(431, 3);
this->textBox2->Multiline = true;
this->textBox2->Name = L"textBox2";
this->textBox2->Size = System::Drawing::Size(422, 125);
this->textBox2->TabIndex = 0;
//
// panel5
//
this->panel5->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel5->Location = System::Drawing::Point(3, 3);
this->panel5->Name = L"panel5";
this->panel5->Size = System::Drawing::Size(422, 125);
this->panel5->TabIndex = 1;
//
// panel6
//
this->panel6->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel6->Location = System::Drawing::Point(3, 134);
this->panel6->Name = L"panel6";
this->panel6->Size = System::Drawing::Size(422, 439);
this->panel6->TabIndex = 2;
//
// tabPage6
//
this->tabPage6->Controls->Add(this->tableLayoutPanel5);
this->tabPage6->Location = System::Drawing::Point(4, 22);
this->tabPage6->Name = L"tabPage6";
this->tabPage6->Padding = System::Windows::Forms::Padding(3);
this->tabPage6->Size = System::Drawing::Size(862, 582);
this->tabPage6->TabIndex = 5;
this->tabPage6->Text = L"Trees";
this->tabPage6->UseVisualStyleBackColor = true;
//
// tableLayoutPanel5
//
this->tableLayoutPanel5->ColumnCount = 2;
this->tableLayoutPanel5->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel5->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50)));
this->tableLayoutPanel5->Controls->Add(this->panel8, 0, 1);
this->tableLayoutPanel5->Controls->Add(this->txtTreeView, 1, 0);
this->tableLayoutPanel5->Controls->Add(this->treeView1, 0, 0);
this->tableLayoutPanel5->Controls->Add(this->panel7, 1, 1);
this->tableLayoutPanel5->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel5->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel5->Name = L"tableLayoutPanel5";
this->tableLayoutPanel5->RowCount = 2;
this->tableLayoutPanel5->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 55.20833F)));
this->tableLayoutPanel5->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 44.79167F)));
this->tableLayoutPanel5->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel5->TabIndex = 1;
//
// panel8
//
this->panel8->Controls->Add(this->btnChangeRegexInRegexTextBox);
this->panel8->Controls->Add(this->txtRegexExpr);
this->panel8->Controls->Add(this->txtRegex);
this->panel8->Controls->Add(this->btnRegex);
this->panel8->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel8->Location = System::Drawing::Point(3, 320);
this->panel8->Name = L"panel8";
this->panel8->Size = System::Drawing::Size(422, 253);
this->panel8->TabIndex = 2;
//
// btnChangeRegexInRegexTextBox
//
this->btnChangeRegexInRegexTextBox->Location = System::Drawing::Point(3, 72);
this->btnChangeRegexInRegexTextBox->Name = L"btnChangeRegexInRegexTextBox";
this->btnChangeRegexInRegexTextBox->Size = System::Drawing::Size(103, 23);
this->btnChangeRegexInRegexTextBox->TabIndex = 4;
this->btnChangeRegexInRegexTextBox->Text = L"Change Regex";
this->btnChangeRegexInRegexTextBox->UseVisualStyleBackColor = true;
this->btnChangeRegexInRegexTextBox->Click += gcnew System::EventHandler(this, &MainForm::btnChangeRegexInRegexTextBox_Click);
//
// txtRegexExpr
//
this->txtRegexExpr->Location = System::Drawing::Point(3, 6);
this->txtRegexExpr->Name = L"txtRegexExpr";
this->txtRegexExpr->Size = System::Drawing::Size(416, 20);
this->txtRegexExpr->TabIndex = 6;
this->txtRegexExpr->Text = L"^([\\+][0-9]{1,3}[ \\.\\-])\?([\\(]{1}[0-9]{1,6}[\\)])\?([0-9 \\.\\-\\/]{3,20})((x|ext|exte"
L"nsion)[ ]\?[0-9]{1,4})\?$";
//
// txtRegex
//
this->txtRegex->Location = System::Drawing::Point(112, 43);
this->txtRegex->Name = L"txtRegex";
this->txtRegex->Size = System::Drawing::Size(307, 20);
this->txtRegex->TabIndex = 5;
this->txtRegex->Text = L"+49 (0) 123 456789";
//
// btnRegex
//
this->btnRegex->Location = System::Drawing::Point(3, 43);
this->btnRegex->Name = L"btnRegex";
this->btnRegex->Size = System::Drawing::Size(103, 23);
this->btnRegex->TabIndex = 4;
this->btnRegex->Text = L"Regex";
this->btnRegex->UseVisualStyleBackColor = true;
this->btnRegex->Click += gcnew System::EventHandler(this, &MainForm::btnRegex_Click);
//
// txtTreeView
//
this->txtTreeView->Dock = System::Windows::Forms::DockStyle::Fill;
this->txtTreeView->Location = System::Drawing::Point(431, 3);
this->txtTreeView->Multiline = true;
this->txtTreeView->Name = L"txtTreeView";
this->txtTreeView->Size = System::Drawing::Size(422, 311);
this->txtTreeView->TabIndex = 0;
//
// treeView1
//
this->treeView1->Dock = System::Windows::Forms::DockStyle::Fill;
this->treeView1->Location = System::Drawing::Point(3, 3);
this->treeView1->Name = L"treeView1";
treeNode1->Name = L"Knoten7";
treeNode1->Text = L"Knoten7";
treeNode2->Name = L"Knoten8";
treeNode2->Text = L"Knoten8";
treeNode3->Name = L"Knoten9";
treeNode3->Text = L"Knoten9";
treeNode4->Name = L"Knoten15";
treeNode4->Text = L"Knoten15";
treeNode5->Name = L"Knoten16";
treeNode5->Text = L"Knoten16";
treeNode6->Name = L"Knoten21";
treeNode6->Text = L"Knoten21";
treeNode7->Name = L"Knoten22";
treeNode7->Text = L"Knoten22";
treeNode8->Name = L"Knoten26";
treeNode8->Text = L"Knoten26";
treeNode9->Name = L"Knoten27";
treeNode9->Text = L"Knoten27";
treeNode10->Name = L"Knoten28";
treeNode10->Text = L"Knoten28";
treeNode11->Name = L"Knoten29";
treeNode11->Text = L"Knoten29";
treeNode12->Name = L"Knoten30";
treeNode12->Text = L"Knoten30";
treeNode13->Name = L"Knoten31";
treeNode13->Text = L"Knoten31";
treeNode14->Name = L"Knoten32";
treeNode14->Text = L"Knoten32";
treeNode15->Name = L"Knoten33";
treeNode15->Text = L"Knoten33";
treeNode16->Name = L"Knoten34";
treeNode16->Text = L"Knoten34";
treeNode17->Name = L"Knoten23";
treeNode17->Text = L"Knoten23";
treeNode18->Name = L"Knoten24";
treeNode18->Text = L"Knoten24";
treeNode19->Name = L"Knoten25";
treeNode19->Text = L"Knoten25";
treeNode20->Name = L"Knoten17";
treeNode20->Text = L"Knoten17";
treeNode21->Name = L"Knoten18";
treeNode21->Text = L"Knoten18";
treeNode22->Name = L"Knoten19";
treeNode22->Text = L"Knoten19";
treeNode23->Name = L"Knoten20";
treeNode23->Text = L"Knoten20";
treeNode24->Name = L"Knoten10";
treeNode24->Text = L"Knoten10";
treeNode25->Name = L"Knoten11";
treeNode25->Text = L"Knoten11";
treeNode26->Name = L"Knoten12";
treeNode26->Text = L"Knoten12";
treeNode27->Name = L"Knoten13";
treeNode27->Text = L"Knoten13";
treeNode28->Name = L"Knoten14";
treeNode28->Text = L"Knoten14";
treeNode29->Name = L"Knoten0";
treeNode29->Text = L"Knoten0";
this->treeView1->Nodes->AddRange(gcnew cli::array< System::Windows::Forms::TreeNode^ >(1) { treeNode29 });
this->treeView1->Size = System::Drawing::Size(422, 311);
this->treeView1->TabIndex = 3;
this->treeView1->AfterSelect += gcnew System::Windows::Forms::TreeViewEventHandler(this, &MainForm::treeView1_AfterSelect);
//
// panel7
//
this->panel7->Controls->Add(this->btnDriveInfo);
this->panel7->Controls->Add(this->btnWalkTreeViewRecursive);
this->panel7->Controls->Add(this->btnRecursion);
this->panel7->Controls->Add(this->btnReadDirectories);
this->panel7->Controls->Add(this->btnRemoveTreeNOde);
this->panel7->Controls->Add(this->btnAddTreeNodeToTreeView);
this->panel7->Dock = System::Windows::Forms::DockStyle::Fill;
this->panel7->Location = System::Drawing::Point(431, 320);
this->panel7->Name = L"panel7";
this->panel7->Size = System::Drawing::Size(422, 253);
this->panel7->TabIndex = 4;
//
// btnDriveInfo
//
this->btnDriveInfo->Location = System::Drawing::Point(3, 119);
this->btnDriveInfo->Name = L"btnDriveInfo";
this->btnDriveInfo->Size = System::Drawing::Size(103, 23);
this->btnDriveInfo->TabIndex = 5;
this->btnDriveInfo->Text = L"DriveInfo";
this->btnDriveInfo->UseVisualStyleBackColor = true;
this->btnDriveInfo->Click += gcnew System::EventHandler(this, &MainForm::btnDriveInfo_Click);
//
// btnWalkTreeViewRecursive
//
this->btnWalkTreeViewRecursive->Location = System::Drawing::Point(3, 72);
this->btnWalkTreeViewRecursive->Name = L"btnWalkTreeViewRecursive";
this->btnWalkTreeViewRecursive->Size = System::Drawing::Size(103, 23);
this->btnWalkTreeViewRecursive->TabIndex = 4;
this->btnWalkTreeViewRecursive->Text = L"Tree Recursive";
this->btnWalkTreeViewRecursive->UseVisualStyleBackColor = true;
this->btnWalkTreeViewRecursive->Click += gcnew System::EventHandler(this, &MainForm::btnWalkTreeViewRecursive_Click);
//
// btnRecursion
//
this->btnRecursion->Location = System::Drawing::Point(220, 3);
this->btnRecursion->Name = L"btnRecursion";
this->btnRecursion->Size = System::Drawing::Size(88, 23);
this->btnRecursion->TabIndex = 3;
this->btnRecursion->Text = L"recursion";
this->btnRecursion->UseVisualStyleBackColor = true;
this->btnRecursion->Click += gcnew System::EventHandler(this, &MainForm::btnRecursion_Click);
//
// btnReadDirectories
//
this->btnReadDirectories->Location = System::Drawing::Point(97, 32);
this->btnReadDirectories->Name = L"btnReadDirectories";
this->btnReadDirectories->Size = System::Drawing::Size(103, 23);
this->btnReadDirectories->TabIndex = 2;
this->btnReadDirectories->Text = L"Read Directrories";
this->btnReadDirectories->UseVisualStyleBackColor = true;
this->btnReadDirectories->Click += gcnew System::EventHandler(this, &MainForm::btnReadDirectories_Click);
//
// btnRemoveTreeNOde
//
this->btnRemoveTreeNOde->Location = System::Drawing::Point(97, 3);
this->btnRemoveTreeNOde->Name = L"btnRemoveTreeNOde";
this->btnRemoveTreeNOde->Size = System::Drawing::Size(117, 23);
this->btnRemoveTreeNOde->TabIndex = 1;
this->btnRemoveTreeNOde->Text = L"Remove TreeNode";
this->btnRemoveTreeNOde->UseVisualStyleBackColor = true;
this->btnRemoveTreeNOde->Click += gcnew System::EventHandler(this, &MainForm::btnRemoveTreeNOde_Click);
//
// btnAddTreeNodeToTreeView
//
this->btnAddTreeNodeToTreeView->Location = System::Drawing::Point(3, 3);
this->btnAddTreeNodeToTreeView->Name = L"btnAddTreeNodeToTreeView";
this->btnAddTreeNodeToTreeView->Size = System::Drawing::Size(88, 23);
this->btnAddTreeNodeToTreeView->TabIndex = 0;
this->btnAddTreeNodeToTreeView->Text = L"Add TreeNode";
this->btnAddTreeNodeToTreeView->UseVisualStyleBackColor = true;
this->btnAddTreeNodeToTreeView->Click += gcnew System::EventHandler(this, &MainForm::btnAddTreeNodeToTreeView_Click);
//
// tabPage7
//
this->tabPage7->Controls->Add(this->tableLayoutPanel6);
this->tabPage7->Location = System::Drawing::Point(4, 22);
this->tabPage7->Name = L"tabPage7";
this->tabPage7->Padding = System::Windows::Forms::Padding(3);
this->tabPage7->Size = System::Drawing::Size(862, 582);
this->tabPage7->TabIndex = 6;
this->tabPage7->Text = L"Explorer";
this->tabPage7->UseVisualStyleBackColor = true;
//
// tableLayoutPanel6
//
this->tableLayoutPanel6->ColumnCount = 2;
this->tableLayoutPanel6->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
49.41589F)));
this->tableLayoutPanel6->ColumnStyles->Add((gcnew System::Windows::Forms::ColumnStyle(System::Windows::Forms::SizeType::Percent,
50.58411F)));
this->tableLayoutPanel6->Controls->Add(this->trvDirectories, 0, 0);
this->tableLayoutPanel6->Controls->Add(this->lsvFiles, 1, 0);
this->tableLayoutPanel6->Dock = System::Windows::Forms::DockStyle::Fill;
this->tableLayoutPanel6->Location = System::Drawing::Point(3, 3);
this->tableLayoutPanel6->Name = L"tableLayoutPanel6";
this->tableLayoutPanel6->RowCount = 1;
this->tableLayoutPanel6->RowStyles->Add((gcnew System::Windows::Forms::RowStyle(System::Windows::Forms::SizeType::Percent, 50)));
this->tableLayoutPanel6->Size = System::Drawing::Size(856, 576);
this->tableLayoutPanel6->TabIndex = 0;
//
// trvDirectories
//
this->trvDirectories->Dock = System::Windows::Forms::DockStyle::Fill;
this->trvDirectories->Location = System::Drawing::Point(3, 3);
this->trvDirectories->Name = L"trvDirectories";
this->trvDirectories->Size = System::Drawing::Size(417, 570);
this->trvDirectories->TabIndex = 0;
this->trvDirectories->AfterSelect += gcnew System::Windows::Forms::TreeViewEventHandler(this, &MainForm::trvDirectories_AfterSelect);
//
// lsvFiles
//
this->lsvFiles->Dock = System::Windows::Forms::DockStyle::Fill;
this->lsvFiles->Location = System::Drawing::Point(426, 3);
this->lsvFiles->Name = L"lsvFiles";
this->lsvFiles->Size = System::Drawing::Size(427, 570);
this->lsvFiles->TabIndex = 1;
this->lsvFiles->UseCompatibleStateImageBehavior = false;
//
// timer1
//
this->timer1->Interval = 1000;
this->timer1->Tick += gcnew System::EventHandler(this, &MainForm::timer1_Tick);
//
// menuStrip1
//
this->menuStrip1->Items->AddRange(gcnew cli::array< System::Windows::Forms::ToolStripItem^ >(3)
{
this->toolStripMenuItem1,
this->toolStripMenuItem3, this->toolStripMenuItem4
});
this->menuStrip1->Location = System::Drawing::Point(0, 0);
this->menuStrip1->Name = L"menuStrip1";
this->menuStrip1->Size = System::Drawing::Size(870, 24);
this->menuStrip1->TabIndex = 5;
this->menuStrip1->Text = L"menuStrip1";
//
// toolStripMenuItem1
//
this->toolStripMenuItem1->DropDownItems->AddRange(gcnew cli::array< System::Windows::Forms::ToolStripItem^ >(5)
{
this->toolStripMenuItem2,
this->toolStripSeparator1, this->mnuSaveFileDialog, this->mnuRichtextBox, this->mnuFolderBrowser
});
this->toolStripMenuItem1->Name = L"toolStripMenuItem1";
this->toolStripMenuItem1->Size = System::Drawing::Size(46, 20);
this->toolStripMenuItem1->Text = L"Datei";
//
// toolStripMenuItem2
//
this->toolStripMenuItem2->Name = L"toolStripMenuItem2";
this->toolStripMenuItem2->Size = System::Drawing::Size(190, 22);
this->toolStripMenuItem2->Text = L"Öffnen";
this->toolStripMenuItem2->Click += gcnew System::EventHandler(this, &MainForm::toolStripMenuItem2_Click);
//
// toolStripSeparator1
//
this->toolStripSeparator1->Name = L"toolStripSeparator1";
this->toolStripSeparator1->Size = System::Drawing::Size(187, 6);
//
// mnuSaveFileDialog
//
this->mnuSaveFileDialog->Name = L"mnuSaveFileDialog";
this->mnuSaveFileDialog->Size = System::Drawing::Size(190, 22);
this->mnuSaveFileDialog->Text = L"Speichern";
this->mnuSaveFileDialog->Click += gcnew System::EventHandler(this, &MainForm::mnuSaveFileDialog_Click);
//
// mnuRichtextBox
//
this->mnuRichtextBox->Name = L"mnuRichtextBox";
this->mnuRichtextBox->Size = System::Drawing::Size(190, 22);
this->mnuRichtextBox->Text = L"Richtextbox Speichern";
this->mnuRichtextBox->Click += gcnew System::EventHandler(this, &MainForm::mnuRichtextBox_Click);
//
// mnuFolderBrowser
//
this->mnuFolderBrowser->Name = L"mnuFolderBrowser";
this->mnuFolderBrowser->Size = System::Drawing::Size(190, 22);
this->mnuFolderBrowser->Text = L"FolderBrowserDialog";
this->mnuFolderBrowser->Click += gcnew System::EventHandler(this, &MainForm::mnuFolderBrowser_Click);
//
// toolStripMenuItem3
//
this->toolStripMenuItem3->DropDownItems->AddRange(gcnew cli::array< System::Windows::Forms::ToolStripItem^ >(2)
{
this->mnuFarben,
this->mnuSchriftart
});
this->toolStripMenuItem3->Name = L"toolStripMenuItem3";
this->toolStripMenuItem3->Size = System::Drawing::Size(90, 20);
this->toolStripMenuItem3->Text = L"Einstellungen";
//
// mnuFarben
//
this->mnuFarben->Name = L"mnuFarben";
this->mnuFarben->Size = System::Drawing::Size(122, 22);
this->mnuFarben->Text = L"Farben";
this->mnuFarben->Click += gcnew System::EventHandler(this, &MainForm::mnuFarben_Click);
//
// mnuSchriftart
//
this->mnuSchriftart->Name = L"mnuSchriftart";
this->mnuSchriftart->Size = System::Drawing::Size(122, 22);
this->mnuSchriftart->Text = L"Schriftart";
this->mnuSchriftart->Click += gcnew System::EventHandler(this, &MainForm::mnuSchriftart_Click);
//
// toolStripMenuItem4
//
this->toolStripMenuItem4->DropDownItems->AddRange(gcnew cli::array< System::Windows::Forms::ToolStripItem^ >(4)
{
this->mnuButtonsHerstellen,
this->mnuListControls, this->mnuTextBoxenHerstellen, this->mnuRefreshTreeView
});
this->toolStripMenuItem4->Name = L"toolStripMenuItem4";
this->toolStripMenuItem4->Size = System::Drawing::Size(54, 20);
this->toolStripMenuItem4->Text = L"Debug";
//
// mnuButtonsHerstellen
//
this->mnuButtonsHerstellen->Name = L"mnuButtonsHerstellen";
this->mnuButtonsHerstellen->Size = System::Drawing::Size(198, 22);
this->mnuButtonsHerstellen->Text = L"Buttons herstellen";
this->mnuButtonsHerstellen->Click += gcnew System::EventHandler(this, &MainForm::mnuButtonsHerstellen_Click);
//
// mnuListControls
//
this->mnuListControls->Name = L"mnuListControls";
this->mnuListControls->Size = System::Drawing::Size(198, 22);
this->mnuListControls->Text = L"Liste Controls tabPage2";
this->mnuListControls->Click += gcnew System::EventHandler(this, &MainForm::mnuListControls_Click);
//
// mnuTextBoxenHerstellen
//
this->mnuTextBoxenHerstellen->Name = L"mnuTextBoxenHerstellen";
this->mnuTextBoxenHerstellen->Size = System::Drawing::Size(198, 22);
this->mnuTextBoxenHerstellen->Text = L"TextBoxen herstellen";
this->mnuTextBoxenHerstellen->Click += gcnew System::EventHandler(this, &MainForm::mnuTextBoxenHerstellen_Click);
//
// mnuRefreshTreeView
//
this->mnuRefreshTreeView->Name = L"mnuRefreshTreeView";
this->mnuRefreshTreeView->Size = System::Drawing::Size(198, 22);
this->mnuRefreshTreeView->Text = L"Refresh ExplorerTree";
this->mnuRefreshTreeView->Click += gcnew System::EventHandler(this, &MainForm::mnuRefreshTreeView_Click);
//
// openFileDialog1
//
this->openFileDialog1->FileName = L"openFileDialog1";
//
// fontDialog1
//
this->fontDialog1->ShowColor = true;
//
// MainForm
//
this->AutoScaleDimensions = System::Drawing::SizeF(6, 13);
this->AutoScaleMode = System::Windows::Forms::AutoScaleMode::Font;
this->ClientSize = System::Drawing::Size(870, 632);
this->Controls->Add(this->tabControl1);
this->Controls->Add(this->menuStrip1);
this->MainMenuStrip = this->menuStrip1;
this->Name = L"MainForm";
this->Text = L"MainForm";
this->tableLayoutPanel1->ResumeLayout(false);
this->tableLayoutPanel1->PerformLayout();
this->contextMenuStrip1->ResumeLayout(false);
this->panel1->ResumeLayout(false);
this->panel2->ResumeLayout(false);
this->panel2->PerformLayout();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->trackBar1))->EndInit();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->numericUpDown1))->EndInit();
this->groupBox1->ResumeLayout(false);
this->groupBox1->PerformLayout();
this->panel3->ResumeLayout(false);
this->panel3->PerformLayout();
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->pictureBox1))->EndInit();
this->tabControl1->ResumeLayout(false);
this->tabPage1->ResumeLayout(false);
this->tabPage2->ResumeLayout(false);
this->tableLayoutPanel2->ResumeLayout(false);
this->tableLayoutPanel2->PerformLayout();
this->panel4->ResumeLayout(false);
this->tabPage3->ResumeLayout(false);
this->tabPage3->PerformLayout();
this->tabPage4->ResumeLayout(false);
this->tableLayoutPanel3->ResumeLayout(false);
this->pnlDrawing->ResumeLayout(false);
(cli::safe_cast<System::ComponentModel::ISupportInitialize^>(this->pictureBox2))->EndInit();
this->pnlGraphics->ResumeLayout(false);
this->tabPage5->ResumeLayout(false);
this->tableLayoutPanel4->ResumeLayout(false);
this->tableLayoutPanel4->PerformLayout();
this->tabPage6->ResumeLayout(false);
this->tableLayoutPanel5->ResumeLayout(false);
this->tableLayoutPanel5->PerformLayout();
this->panel8->ResumeLayout(false);
this->panel8->PerformLayout();
this->panel7->ResumeLayout(false);
this->tabPage7->ResumeLayout(false);
this->tableLayoutPanel6->ResumeLayout(false);
this->menuStrip1->ResumeLayout(false);
this->menuStrip1->PerformLayout();
this->ResumeLayout(false);
this->PerformLayout();
}
#pragma endregion
void initialiseComponents()
{
this->btnBlinkinButton = gcnew BlinkinButton(250, System::Drawing::Color::Coral, System::Drawing::Color::CornflowerBlue);
//
// btnBlinkinButton
//
this->btnBlinkinButton->Location = System::Drawing::Point(3, 3);
this->btnBlinkinButton->Name = L"btnBlinkinButton";
this->btnBlinkinButton->Size = System::Drawing::Size(75, 23);
this->btnBlinkinButton->TabIndex = 0;
this->btnBlinkinButton->Text = L"button1";
this->btnBlinkinButton->UseVisualStyleBackColor = true;
this->btnBlinkinButton->Click += gcnew System::EventHandler(this, &GUI::MainForm::BlinkinButtonOnClick);
this->btnBlinkinButton->MouseHover += gcnew System::EventHandler(this, &GUI::MainForm::BlinkinButtonOnMouseHover);
this->panel5->Controls->Add(this->btnBlinkinButton);
this->pnlHouse = (gcnew DrawingPanel);
//
// pnlHouse
//
this->pnlHouse->Location = System::Drawing::Point(25, 25);
this->pnlHouse->Name = L"pnlHouse";
this->pnlHouse->Size = System::Drawing::Size(300, 300);
this->pnlHouse->TabIndex = 0;
this->panel6->Controls->Add(this->pnlHouse);
this->txtAutoRegexMatcher = (gcnew RegexTextBox);
//
// txtAutoRegexMatcher
//
this->txtAutoRegexMatcher->Location = System::Drawing::Point(3, 117);
this->txtAutoRegexMatcher->Name = L"txtAutoRegexMatcher";
this->txtAutoRegexMatcher->Size = System::Drawing::Size(307, 20);
this->txtAutoRegexMatcher->TabIndex = 7;
this->txtAutoRegexMatcher->Text = L"+49 (0) 123 456789";
this->panel8->Controls->Add(this->txtAutoRegexMatcher);
}
private: System::Void BlinkinButtonOnMouseHover(System::Object^ sender, System::EventArgs^ e)
{
logger->Debug("I got hovered from the form !!!");
}
private: System::Void BlinkinButtonOnClick(System::Object^ sender, System::EventArgs^ e)
{
this->btnBlinkinButton->changeConfig(125, Color::Yellow, Color::OrangeRed);
}
private: System::Void cmdChangeFormColor_Click(System::Object^ sender, System::EventArgs^ e)
{
cmdChangeFormColor->BackColor = System::Drawing::Color(Color::HotPink);
this->BackColor = System::Drawing::Color(Color::GreenYellow);
}
private: System::Void btnChangeTab_Click(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText(tabControl1->SelectedIndex.ToString());
tabControl1->SelectedIndex = 1;
tabControl1->SelectTab(1);
textBox1->AppendText(textBox1->GetType()->ToString());
}
private: System::Void btnCheckbox_Click(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText(checkBox1->Checked.ToString());
if (checkBox1->Checked)
{
System::Windows::Forms::DialogResult dR =
MessageBox::Show("Oh nooooo, I'm checked !\r\n", "Please click !", MessageBoxButtons::YesNoCancel, MessageBoxIcon::Warning);
if (dR == System::Windows::Forms::DialogResult::Cancel)
{
System::Diagnostics::Debug::WriteLine("User clicked cancel");
textBox1->AppendText("User cancelled the action !\r\n");
}
else if (dR == System::Windows::Forms::DialogResult::Yes)
{
System::Diagnostics::Debug::WriteLine("User clicked yes");
textBox1->AppendText("You're amazing !!\r\n");
}
else if (dR == System::Windows::Forms::DialogResult::No)
{
System::Diagnostics::Debug::WriteLine("User clicked no");
textBox1->AppendText("Whaaaaat ??!!\r\n");
}
}
else
{
MessageBox::Show("Pleaseeeeee check me !\r\n");
}
}
private: System::Void checkBox1_CheckedChanged(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText("You changed the checkBox1 to " + checkBox1->Checked.ToString() + "\r\n");
}
RadioButton^ gimmeActiveRadioButton()
{
if (radioButton1->Checked)
{
return radioButton1;
}
else if (radioButton2->Checked)
{
return radioButton2;
}
else if (radioButton3->Checked)
{
return radioButton3;
}
}
private: System::Void btnRadioButton_Click(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText("Radiobutton : " + gimmeActiveRadioButton()->Name);
}
private: System::Void btnComboboxValue_Click(System::Object^ sender, System::EventArgs^ e)
{
}
private: System::Void cmbBlubb_SelectedIndexChanged(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText(cmbBlubb->Text);
}
private: System::Void btnComboAddItem_Click(System::Object^ sender, System::EventArgs^ e)
{
cmbBlubb->Items->Add("WoW");
}
private: System::Void btnComboremoveItem_Click(System::Object^ sender, System::EventArgs^ e)
{
cmbBlubb->Items->RemoveAt(2);
}
private: System::Void btnComboInsert_Click(System::Object^ sender, System::EventArgs^ e)
{
cmbBlubb->Items->Insert(2, "Test");
}
private: System::Void listBox1_SelectedIndexChanged(System::Object^ sender, System::EventArgs^ e)
{
int selectedItemsCount = listBox1->SelectedItems->Count;
for (int i = 0;i < selectedItemsCount;i++)
{
textBox1->AppendText(listBox1->SelectedItems[i]->ToString() + "\r\n");
}
}
private: System::Void btnNextStep_Click(System::Object^ sender, System::EventArgs^ e)
{
if (step == 0)
{
txtQuestions->Clear();
txtQuestions->AppendText("Wie heisst Du ?\r\n");
txtAnswers->Clear();
}
else if (step == 1)
{
txtQuestions->AppendText("Du heisst also " + txtAnswers->Text + " !\r\n");
antwort1 = txtAnswers->Text;
txtQuestions->AppendText("Wie alt bist Du ?\r\n");
txtAnswers->Clear();
}
else if (step == 2)
{
txtQuestions->AppendText("Du bist also " + txtAnswers->Text + " alt !\r\n");
antwort2 = txtAnswers->Text;
txtQuestions->AppendText("Was ist Deine Lieblingsfarbe ?\r\n");
txtAnswers->Clear();
}
else if (step == 3)
{
txtQuestions->AppendText("Deine Lieblingsfarbe ist also " + txtAnswers->Text + " !\r\n");
antwort3 = txtAnswers->Text;
txtQuestions->AppendText("Danke für's Gespräch !\r\n");
txtAnswers->Clear();
}
step++;
}
private: System::Void btnChangeFromAnotherClass_Click(System::Object^ sender, System::EventArgs^ e)
{
t = gcnew Test();
//t->changeTextBoxText(this);
}
private: System::Void btnStartProgress_Click(System::Object^ sender, System::EventArgs^ e)
{
//for(int counter = 0;counter <=100 ;counter++){
// System::Threading::Thread::Sleep(500);
// progressBar1->Value = counter;
//}
progress = 0;
timer1->Enabled = true;
}
private: System::Void timer1_Tick(System::Object^ sender, System::EventArgs^ e)
{
if (progress <= 100)
{
progressBar1->Value = progress;
progress += 5;
}
else
{
timer1->Enabled = false;
}
}
private: System::Void trackBar1_Scroll(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText(trackBar1->Value + "\r\n");
}
private: System::Void toolStripMenuItem2_Click(System::Object^ sender, System::EventArgs^ e)
{
openFileDialog1->Filter
= "Solution Files|*.sln;*.vcxproj|Text Files|*.txt|Image Files(*.BMP;*.JPG;*.GIF)|*.BMP;*.JPG;*.GIF|All files (*.*)|*.*";
openFileDialog1->FilterIndex = 2;
openFileDialog1->InitialDirectory = "d:\\";
System::Windows::Forms::DialogResult dialogResult = openFileDialog1->ShowDialog();
if (dialogResult == System::Windows::Forms::DialogResult::OK)
{
if (openFileDialog1->Multiselect == true)
{
for each(String^ einFileName in openFileDialog1->FileNames)
{
textBox1->AppendText(einFileName + "\r\n");
}
}
else
{
textBox1->AppendText(openFileDialog1->FileName + "\r\n");
String^ inhaltDerDatei = System::IO::File::ReadAllText(openFileDialog1->FileName);
textBox1->AppendText(inhaltDerDatei);
}
}
else
{
textBox1->AppendText("Datei auswählen !\r\n");
}
}
private: System::Void mnuFarben_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Windows::Forms::DialogResult dialogResult = colorDialog1->ShowDialog();
if (dialogResult == System::Windows::Forms::DialogResult::OK)
{
textBox1->BackColor = colorDialog1->Color;
}
}
private: System::Void mnuSaveFileDialog_Click(System::Object^ sender, System::EventArgs^ e)
{
saveFileDialog1->Filter = "Solution Files|*.sln;*.vcxproj|Text Files|*.txt|Image Files(*.BMP;*.JPG;*.GIF)|*.BMP;*.JPG;*.GIF|All files (*.*)|*.*";
saveFileDialog1->FilterIndex = 2;
saveFileDialog1->InitialDirectory = "d:\\";
System::Windows::Forms::DialogResult dialogResult = saveFileDialog1->ShowDialog();
if (dialogResult == System::Windows::Forms::DialogResult::OK)
{
System::IO::File::WriteAllText(saveFileDialog1->FileName, textBox1->Text);
}
}
private: System::Void mnuSchriftart_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Windows::Forms::DialogResult dialogResult = fontDialog1->ShowDialog();
if (dialogResult == System::Windows::Forms::DialogResult::OK)
{
textBox1->Font = fontDialog1->Font;
textBox1->ForeColor = fontDialog1->Color;
}
}
private: System::Void mnuRichtextBox_Click(System::Object^ sender, System::EventArgs^ e)
{
richTextBox1->SaveFile("d:\\richtexttest.rtf");
}
private: System::Void mnuFolderBrowser_Click(System::Object^ sender, System::EventArgs^ e)
{
folderBrowserDialog1->ShowDialog();
}
private: System::Void mnuClearText_Click(System::Object^ sender, System::EventArgs^ e)
{
textBox1->Clear();
}
private: System::Void dateTimePicker1_ValueChanged(System::Object^ sender, System::EventArgs^ e)
{
DateTime t = dateTimePicker1->Value;
DateTime aktuelleZeit = DateTime::Now;
textBox1->AppendText(t.ToLongDateString() + "\n");
textBox1->AppendText(aktuelleZeit.ToLongTimeString() + "\n");
TimeSpan dauer(10, 10, 10, 10);
DateTime summe = t.Add(dauer);
}
private: System::Void mnuButtonsHerstellen_Click(System::Object^ sender, System::EventArgs^ e)
{
for (int counter = 0; counter < 10;counter++)
{
System::Windows::Forms::Button^ btnDynamicButton = gcnew System::Windows::Forms::Button;
btnDynamicButton->Location = System::Drawing::Point(0, 0 + 25 * counter);
btnDynamicButton->Name = L"btnDynamicButton" + counter;
btnDynamicButton->Size = System::Drawing::Size(109, 23);
btnDynamicButton->TabIndex = 8;
btnDynamicButton->Text = L"I'm dynamic " + counter;
btnDynamicButton->UseVisualStyleBackColor = true;
btnDynamicButton->Click += gcnew System::EventHandler(this, &MainForm::dynamicButtonsClick);
tabPage2->Controls->Add(btnDynamicButton);
}
}
private: System::Void mnuListControls_Click(System::Object^ sender, System::EventArgs^ e)
{
for each(Control^ control in tabPage2->Controls)
{
textBox1->AppendText(control->Name + "\n");
}
}
private: System::Void dynamicButtonsClick(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText("Dynamic Button clicked !\t" + ((Button^)sender)->Name + "\n");
if (((Button^)sender)->Name == "btnDynamicButton3")
{
MessageBox::Show("Du hast den richtigen Button gedrückt !");
}
}
private: System::Void mnuTextBoxenHerstellen_Click(System::Object^ sender, System::EventArgs^ e)
{
createTextBoxes();
}
void createTextBoxes()
{
for (int counter = 0;counter < 10;counter++)
{
TextBox^ dynamicTextBox = gcnew TextBox;
dynamicTextBox->Location = System::Drawing::Point(200, 0 + 25 * counter);
dynamicTextBox->Name = L"textBox" + counter;
dynamicTextBox->ScrollBars = System::Windows::Forms::ScrollBars::Both;
dynamicTextBox->TabIndex = 67;
dynamicTextBox->TextChanged += gcnew System::EventHandler(this, &MainForm::dynamicTextBoxesTextChanged);
tabPage2->Controls->Add(dynamicTextBox);
}
}
private: System::Void dynamicTextBoxesTextChanged(System::Object^ sender, System::EventArgs^ e)
{
textBox1->AppendText(((TextBox^)sender)->Name + " TextChanged : " + ((TextBox^)sender)->Text + "\n");
}
private: System::Void btnAddDoubles_Click(System::Object^ sender, System::EventArgs^ e)
{
double ersteZahl = Double::Parse(txtErsteZahl->Text);
double zweiteZahl = Double::Parse(txtZweiteZahl->Text);
double ergebnis = ersteZahl + zweiteZahl;
textBox1->AppendText(ergebnis.ToString("N2"));
}
private: System::Void btnArrayList_Click(System::Object^ sender, System::EventArgs^ e)
{
ArrayList^ listeVonElementen = gcnew ArrayList;
listeVonElementen->Add("Bli");
txtCollections->AppendText("\n:::" + listeVonElementen[0]->ToString() + "\n");
listeVonElementen->Add("Bla");
listeVonElementen->Add("Blubb");
listeVonElementen->Add("Yeah");
listeVonElementen->Add(this);
listeVonElementen->Add(3);
listeVonElementen->Add(gcnew Button);
listeVonElementen->Remove("Bli");
txtCollections->AppendText(listeVonElementen->IndexOf("Yeah").ToString());
listeVonElementen->Insert(3, "Blubbbbbb");
listeVonElementen->Reverse();
for each(Object^ o in listeVonElementen)
{
txtCollections->AppendText(o->GetType() + " | " + o->ToString() + "\r\n");
}
}
private: System::Void btnQueue_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Collections::Queue^ queue = gcnew System::Collections::Queue;
queue->Enqueue("1");
queue->Enqueue("3");
queue->Enqueue("2");
queue->Enqueue("4");
txtCollections->Text += queue->Count.ToString();
int count = queue->Count;
for (int counter = 1;counter <= count;counter++)
{
txtCollections->AppendText(queue->Dequeue()->ToString());
//NICHT rausnehmen, nur drauf schauen
//txtCollections->AppendText(queue->Peek()->ToString());
}
}
private: System::Void btnStack_Click(System::Object^ sender, System::EventArgs^ e)
{
Stack^ stack = gcnew Stack;
stack->Push("1");
//stack->Push(1);
//stack->Push(this);
stack->Push("2");
stack->Push("3");
stack->Push("4");
stack->Push("5");
int count = stack->Count;
for (int counter = 0;counter < count;counter++)
{
txtCollections->AppendText((String^)stack->Pop());
}
}
private: System::Void btnSortedList_Click(System::Object^ sender, System::EventArgs^ e)
{
SortedList^ sortedList = gcnew SortedList;
sortedList->Add(1, "Sieger");
//sortedList->Add(1, "Sieger"); -> Fehler, existiert schon
sortedList->Add(3, "Drittplatzierter");
sortedList->Add(2, "Zweiter Sieger");
for each(int key in sortedList->Keys)
{
txtCollections->AppendText(key + " | " + sortedList[key] + "\r\n");
}
SortedList^ sortedList1 = gcnew SortedList;
DateTime d = DateTime(1971, 12, 12);
sortedList1->Add(d, "Sieger3");
sortedList1->Add(DateTime(1970, 12, 12), "Sieger2");
sortedList1->Add(DateTime(1968, 12, 12), "Sieger1");
for each(DateTime key in sortedList1->Keys)
{
txtCollections->AppendText(key + " | " + sortedList1[key] + "\r\n");
}
}
private: System::Void btnHashtable_Click(System::Object^ sender, System::EventArgs^ e)
{
Hashtable^ openWith = gcnew Hashtable;
// Add some elements to the hash table. There are no
// duplicate keys, but some of the values are duplicates.
openWith->Add("txt", "notepad.exe");
//openWith->Add("txt", "notepad.exe"); -> Fehler
openWith->Add("bmp", "paint.exe");
openWith->Add("dib", "paint.exe");
openWith->Add("rtf", "wordpad.exe");
txtCollections->AppendText(openWith["txt"] + "\r\n");
openWith["rtf"] = "winword.exe";
//If the key "ht" doesn't exist, add entry to our Hashtable
if (!openWith->ContainsKey("ht"))
{
openWith->Add("ht", "hypertrm.exe");
}
for each(DictionaryEntry de in openWith)
{
txtCollections->AppendText(de.Key + " | " + de.Value + "\r\n");
}
}
private: System::Void btnList_Click(System::Object^ sender, System::EventArgs^ e)
{
//Fully qualified |Diamantoperator
System::Collections::Generic::List<String^>^ phrases = gcnew System::Collections::Generic::List<String^>();
phrases->Add("Text");
phrases->Add("Text1");
phrases->Add("Text2");
phrases->Add("Text3");
//phrases->Add(34);-> Fehler
for each(String^ oneElement in phrases)
{
txtCollections->AppendText(oneElement);
}
}
private: System::Void btnArray_Click(System::Object^ sender, System::EventArgs^ e)
{
array<String^>^ myArr = { L"The", L"quick", L"brown", L"fox",
L"jumps", L"over", L"the", L"lazy", L"dog" };
Array::Resize(myArr, myArr->Length + 5);
array<Byte>^ buffer = gcnew array<Byte>(1024);
ArrayList^ l = gcnew ArrayList(myArr);
l->AddRange(myArr);
array<String ^, 3> ^ my3DArray = gcnew array<String ^, 3>(3, 5, 6);
my3DArray[0, 0, 0] = "Bla";
ArrayList^ zeile = gcnew ArrayList;
ArrayList^ spalte = gcnew ArrayList;
spalte->Add(zeile);
((ArrayList^)spalte[0])[0] = "j";
}
private: System::Void btnBenchmark_Click(System::Object^ sender, System::EventArgs^ e)
{
int size = 10000000;
ArrayList^ numbers = gcnew ArrayList;
DateTime startTime = DateTime::Now;
for (int counter = 0; counter < size; counter++)
{
numbers->Add(counter);
}
DateTime endTime = DateTime::Now;
txtCollections->AppendText("\r\nCreation of 1M int in ArrayList :" + endTime.Subtract(startTime).TotalMilliseconds);
//////////////////////////////////////////////////////////
startTime = DateTime::Now;
array<int>^ intArray = gcnew array<int>(size);
for (int counter = 0; counter < size; counter++)
{
intArray[counter] = counter;
}
endTime = DateTime::Now;
txtCollections->AppendText("\r\nCreation of 1M int in array :" + endTime.Subtract(startTime).TotalMilliseconds);
//////////////////////////////////////////////////////////
startTime = DateTime::Now;
for (int counter = 0;counter < size;counter++)
{
int temp = (int)numbers[counter];
}
endTime = DateTime::Now;
txtCollections->AppendText("\r\nAccessing 1M int in ArrayList :" + endTime.Subtract(startTime).TotalMilliseconds);
//////////////////////////////////////////////////////////
startTime = DateTime::Now;
for (int counter = 0;counter < size;counter++)
{
int temp = intArray[counter];
}
endTime = DateTime::Now;
txtCollections->AppendText("\r\nAccessing 1M int in array :" + endTime.Subtract(startTime).TotalMilliseconds);
}
private: System::Void btnDrawLine_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Drawing::Graphics^ graphics = pictureBox2->CreateGraphics();
System::Drawing::Pen^ penRed = gcnew System::Drawing::Pen(Color::Red);
System::Drawing::Pen^ penBlue = gcnew System::Drawing::Pen(Color::Blue);
System::Drawing::Pen^ penGreen = gcnew System::Drawing::Pen(Color::Green);
System::Drawing::Brush^ brushYellow = gcnew System::Drawing::SolidBrush(Color::Yellow);
graphics->DrawLine(penRed, 0, 0, 100, 300);
graphics->DrawLine(penBlue, 100, 200, 0, 0);
graphics->DrawEllipse(penGreen, 20, 90, 40, 20);
graphics->FillRectangle(brushYellow, 70, 70, 30, 60);
}
System::Drawing::Point lastPoint = Point(0, 0);
ArrayList^ points;
private: System::Void pnlDrawing_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Drawing::Graphics^ graphics = pictureBox2->CreateGraphics();
System::Drawing::Pen^ penBlack = gcnew System::Drawing::Pen(Color::Black, 4);
// |Umrechnung |aktuelle Mouseposition Bildschirm
System::Drawing::Point actualPosition = pnlDrawing->PointToClient(this->Cursor->Position);
graphics->DrawLine(penBlack, lastPoint, actualPosition);
lastPoint = actualPosition;
points->Add(lastPoint);
System::Diagnostics::Debug::WriteLine(actualPosition.ToString());
}
private: System::Void pnlDrawing_Paint(System::Object^ sender, System::Windows::Forms::PaintEventArgs^ e)
{
drawLinesByPoints(e->Graphics);
}
void drawLinesByPoints(Graphics^ g)
{
System::Drawing::Pen^ penBlack = gcnew System::Drawing::Pen(Color::Black, 4);
int pointsCount = points->Count;
logger->Info("Amount of points in points :" + pointsCount);
for (int counter = 0; counter < pointsCount - 1;counter++)
{
logger->Debug((Point)points[counter]);
g->DrawLine(penBlack, (Point)points[counter], (Point)points[counter + 1]);
}
}
void translatePoints(int factor)
{
logger->Debug("factor =" + factor);
int pointsCount = points->Count;
logger->Info("Amount of points in points :" + pointsCount);
for (int counter = 0; counter < pointsCount - 1;counter++)
{
logger->Trace("old point:" + (Point)points[counter]);
Point newPoint = Point(((Point)points[counter]).X * factor, ((Point)points[counter]).Y * factor);
points[counter] = newPoint;
logger->Trace("new point:" + newPoint);
}
}
private: System::Void btnTranslatePoints_Click(System::Object^ sender, System::EventArgs^ e)
{
translatePoints(2);
pnlDrawing->CreateGraphics()->Clear(Color::Gainsboro);
pnlDrawing->Refresh();
}
private: System::Void btnDrawImage_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Drawing::Pen^ penBlack = gcnew System::Drawing::Pen(Color::Black, 4);
System::Drawing::Image^ image = Image::FromFile("d:\\spaghettimonster.jpg");
Graphics^ imageGraphics = Graphics::FromImage(image);
imageGraphics->DrawLine(penBlack, 0, 0, 200, 200);
Point ulCorner = Point(100, 0);
pnlGraphics->CreateGraphics()->DrawImage(image, ulCorner);
image->Save("d:\\spaghettimonster12.jpg");
}
private: System::Void btnDrawHouse_Click(System::Object^ sender, System::EventArgs^ e)
{
for (double counter = 0.1;counter < 1;counter += 0.1)
{
drawHouse(pnlGraphics->CreateGraphics(), 0 + 20 * counter, 0 + 20 * counter, counter, counter);
}
}
void drawHouse(Graphics^ graphics, int startPositionX, int startPositionY, double scaleFactorX, double scaleFactorY)
{
System::Drawing::Pen^ penBlue = gcnew System::Drawing::Pen(Color::Blue);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 0, 300, 0, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 0, 100, 200, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 200, 100, 200, 300, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 200, 300, 0, 300, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 0, 100, 100, 20, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 100, 20, 200, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 100, 20, 300, 20, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 300, 20, 400, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 400, 100, 200, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 400, 300, 400, 100, scaleFactorX, scaleFactorY);
drawSpecialLine(graphics, penBlue, startPositionX, startPositionY, 200, 300, 400, 300, scaleFactorX, scaleFactorY);
}
void drawSpecialLine(Graphics^ graphics, Pen^ pen, float startPositionX, float startPositionY, float x1, float y1, float x2, float y2, float scaleFactorX, float scaleFactorY)
{
graphics->DrawLine(pen, startPositionX + x1 * scaleFactorX, startPositionY + y1 * scaleFactorY, startPositionX + x2 * scaleFactorX, startPositionY + y2 * scaleFactorY);
}
private: System::Void btnDivide_Click(System::Object^ sender, System::EventArgs^ e)
{
double ersteZahl = double::Parse(txtErsteZahl->Text);
double zweiteZahl = double::Parse(txtZweiteZahl->Text);
try
{
divide(ersteZahl, zweiteZahl);
}
catch (TeilenDurch0Exception^ ex)
{
logger->Fatal(ex->Message);
logger->Fatal("Zähler war : " + ex->zaehler);
txtZweiteZahl->BackColor = Color::LightSalmon;
}
catch (Exception^ ex)
{
logger->Fatal(ex->Message);
}
finally{
//Aufräumarbeiten
}
}
private:
/// <summary>Divides two numbers (number1, number2) and returns the result as int
/// </summary>
/// <param name="number1">Is the numerator as <code>int</code></param>
/// <param name="number2">Is the denominator as <code>int</code></param>
/// <returns>The result of the division</returns>
/// <exception cref="Notepad.TeilenDurch0Exception">Thrown when number2 == 0</exception>
int divide(int number1, int number2)
{
if (number2 == 0)
{
TeilenDurch0Exception^ ex = gcnew TeilenDurch0Exception("Teilen durch 0 is nich !", number1);
throw ex;
}
return number1 / number2;
}
private: System::Void btnAddTreeNodeToTreeView_Click(System::Object^ sender, System::EventArgs^ e)
{
treeView1->ExpandAll();
TreeNode^ anotherNode = gcnew TreeNode("I'm amazingly dynamic!");
anotherNode->Name = "I'm amazingly dynamic!";
treeView1->Nodes[0]->Nodes->Add(anotherNode);
}
private: System::Void treeView1_AfterSelect(System::Object^ sender, System::Windows::Forms::TreeViewEventArgs^ e)
{
txtTreeView->AppendText(e->Node->Name + "\r\n");
txtTreeView->AppendText("Parent : " + e->Node->Parent + "\r\n");
e->Node->BackColor = Color::LightSalmon;
}
private: System::Void btnRemoveTreeNOde_Click(System::Object^ sender, System::EventArgs^ e)
{
if (treeView1->SelectedNode)
{
treeView1->Nodes->Remove(treeView1->SelectedNode);
}
}
private: System::Void btnReadDirectories_Click(System::Object^ sender, System::EventArgs^ e)
{
TreeNode^ root = gcnew TreeNode("d:\\");
for each(String^ oneDirectory in System::IO::Directory::GetDirectories("d:\\"))
{
TreeNode^ directoryNode = gcnew TreeNode(oneDirectory);
root->Nodes->Add(directoryNode);
}
treeView1->Nodes->Add(root);
}
int fakultaet(int n)
{
logger->Trace("Einsprung");
logger->Trace("n=" + n);
if (n == 1)
{
logger->Trace("Raussprung");
logger->Trace("n=" + n);
return 1;
}
int result = n*fakultaet(n - 1);
logger->Trace("result=" + result);
logger->Trace("Raussprung");
return result;
}
//Fakultät 5!
//5! = 5 * 4 * 3 * 2 * 1
private: System::Void btnRecursion_Click(System::Object^ sender, System::EventArgs^ e)
{
txtTreeView->AppendText(fakultaet(4).ToString());
}
private: System::Void btnRegex_Click(System::Object^ sender, System::EventArgs^ e)
{
System::Text::RegularExpressions::Regex^ regex
= gcnew System::Text::RegularExpressions::Regex(txtRegexExpr->Text);
if (regex->IsMatch(txtRegex->Text))
{
txtRegex->BackColor = Color::White;
}
else
{
txtRegex->BackColor = Color::LightSalmon;
}
}
private: System::Void btnChangeRegexInRegexTextBox_Click(System::Object^ sender, System::EventArgs^ e)
{
this->txtAutoRegexMatcher->reconfigure(txtRegexExpr->Text, Color::LightPink);
}
private: System::Void btnWalkTreeViewRecursive_Click(System::Object^ sender, System::EventArgs^ e)
{
showTreeNodes(treeView1->Nodes[0], 0);
}
//Rekursion
void showTreeNodes(TreeNode^ t, int level)
{
level++;
logger->Trace(level + " : " + t->Name);
for each(TreeNode^ tn in t->Nodes)
{
showTreeNodes(tn, level);
}
}
private: System::Void btnDriveInfo_Click(System::Object^ sender, System::EventArgs^ e)
{
for each(System::IO::DriveInfo^ d in System::IO::DriveInfo::GetDrives())
{
txtTreeView->AppendText(d->Name + "\r\n");
}
}
void addTreeNodeToTreeView(String^ nodeText)
{
TreeNode^ t = gcnew TreeNode(nodeText);
t->Text = nodeText;
trvDirectories->Nodes->Add(t);
}
private: System::Void mnuRefreshTreeView_Click(System::Object^ sender, System::EventArgs^ e)
{
for each(System::IO::DriveInfo^ d in System::IO::DriveInfo::GetDrives())
{
addTreeNodeToTreeView(d->Name);
logger->Trace(d->Name);
}
}
void addDirectoriesToDirectoryTreeNode(TreeNode^ directoryTreeNode)
{
try
{
String^ path = directoryTreeNode->Text;
for each(String^ directoryPath in System::IO::Directory::GetDirectories(path))
{
TreeNode^ dirNode1 = gcnew TreeNode(directoryPath);
dirNode1->Name = directoryPath;
directoryTreeNode->Nodes->Add(dirNode1);
logger->Trace("dirNode1->Name=" + dirNode1->Name);
if (tryToGetDirectories(dirNode1->Name))
{
for each(String^ directoryPath2 in System::IO::Directory::GetDirectories(dirNode1->Name))
{
TreeNode^ dirNode2 = gcnew TreeNode(directoryPath2);
dirNode1->Nodes->Add(dirNode2);
}
}
else
{
logger->Debug(dirNode1->Name + " problem !");
}
}
}
catch (Exception^ e)
{
logger->Fatal(e->Message);
}
}
bool tryToGetDirectories(String^ path)
{
try
{
System::IO::Directory::GetDirectories(path);
}
catch (Exception^e)
{
logger->Debug(e->Message);
return false;
}
return true;
}
private: System::Void trvDirectories_AfterSelect(System::Object^ sender, System::Windows::Forms::TreeViewEventArgs^ e)
{
if (e->Node->Tag)
{
logger->Trace("Node " + e->Node->Name + " already clicked !");
}
else
{
addDirectoriesToDirectoryTreeNode(e->Node);
e->Node->Tag = true;
}
}
};
}
| [
"Alfa-Dozent@SB-U03-001"
] | Alfa-Dozent@SB-U03-001 |
a33ec34f6af6b6cbbb64ff24bb9df3a9fad4a1ee | 60db84d8cb6a58bdb3fb8df8db954d9d66024137 | /android-cpp-sdk/platforms/android-4/android/widget/CursorAdapter.hpp | ec4974648113f4833f71700254a31f0c4b406568 | [
"BSL-1.0"
] | permissive | tpurtell/android-cpp-sdk | ba853335b3a5bd7e2b5c56dcb5a5be848da6550c | 8313bb88332c5476645d5850fe5fdee8998c2415 | refs/heads/master | 2021-01-10T20:46:37.322718 | 2012-07-17T22:06:16 | 2012-07-17T22:06:16 | 37,555,992 | 5 | 4 | null | null | null | null | UTF-8 | C++ | false | false | 15,748 | hpp | /*================================================================================
code generated by: java2cpp
author: Zoran Angelov, mailto://baldzar@gmail.com
class: android.widget.CursorAdapter
================================================================================*/
#ifndef J2CPP_INCLUDE_IMPLEMENTATION
#ifndef J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_DECL
#define J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_DECL
namespace j2cpp { namespace android { namespace view { class View; } } }
namespace j2cpp { namespace android { namespace view { class ViewGroup; } } }
namespace j2cpp { namespace android { namespace widget { class FilterQueryProvider; } } }
namespace j2cpp { namespace android { namespace widget { class SpinnerAdapter; } } }
namespace j2cpp { namespace android { namespace widget { class Filter; } } }
namespace j2cpp { namespace android { namespace widget { class Adapter; } } }
namespace j2cpp { namespace android { namespace widget { class Filterable; } } }
namespace j2cpp { namespace android { namespace widget { class ListAdapter; } } }
namespace j2cpp { namespace android { namespace widget { class BaseAdapter; } } }
namespace j2cpp { namespace android { namespace database { class Cursor; } } }
namespace j2cpp { namespace android { namespace content { class Context; } } }
namespace j2cpp { namespace java { namespace lang { class CharSequence; } } }
namespace j2cpp { namespace java { namespace lang { class Object; } } }
#include <android/content/Context.hpp>
#include <android/database/Cursor.hpp>
#include <android/view/View.hpp>
#include <android/view/ViewGroup.hpp>
#include <android/widget/Adapter.hpp>
#include <android/widget/BaseAdapter.hpp>
#include <android/widget/Filter.hpp>
#include <android/widget/FilterQueryProvider.hpp>
#include <android/widget/Filterable.hpp>
#include <android/widget/ListAdapter.hpp>
#include <android/widget/SpinnerAdapter.hpp>
#include <java/lang/CharSequence.hpp>
#include <java/lang/Object.hpp>
namespace j2cpp {
namespace android { namespace widget {
class CursorAdapter;
class CursorAdapter
: public object<CursorAdapter>
{
public:
J2CPP_DECLARE_CLASS
J2CPP_DECLARE_METHOD(0)
J2CPP_DECLARE_METHOD(1)
J2CPP_DECLARE_METHOD(2)
J2CPP_DECLARE_METHOD(3)
J2CPP_DECLARE_METHOD(4)
J2CPP_DECLARE_METHOD(5)
J2CPP_DECLARE_METHOD(6)
J2CPP_DECLARE_METHOD(7)
J2CPP_DECLARE_METHOD(8)
J2CPP_DECLARE_METHOD(9)
J2CPP_DECLARE_METHOD(10)
J2CPP_DECLARE_METHOD(11)
J2CPP_DECLARE_METHOD(12)
J2CPP_DECLARE_METHOD(13)
J2CPP_DECLARE_METHOD(14)
J2CPP_DECLARE_METHOD(15)
J2CPP_DECLARE_METHOD(16)
J2CPP_DECLARE_METHOD(17)
J2CPP_DECLARE_METHOD(18)
J2CPP_DECLARE_METHOD(19)
explicit CursorAdapter(jobject jobj)
: object<CursorAdapter>(jobj)
{
}
operator local_ref<android::widget::SpinnerAdapter>() const;
operator local_ref<android::widget::Adapter>() const;
operator local_ref<android::widget::Filterable>() const;
operator local_ref<android::widget::ListAdapter>() const;
operator local_ref<android::widget::BaseAdapter>() const;
operator local_ref<java::lang::Object>() const;
CursorAdapter(local_ref< android::content::Context > const&, local_ref< android::database::Cursor > const&);
CursorAdapter(local_ref< android::content::Context > const&, local_ref< android::database::Cursor > const&, jboolean);
local_ref< android::database::Cursor > getCursor();
jint getCount();
local_ref< java::lang::Object > getItem(jint);
jlong getItemId(jint);
jboolean hasStableIds();
local_ref< android::view::View > getView(jint, local_ref< android::view::View > const&, local_ref< android::view::ViewGroup > const&);
local_ref< android::view::View > getDropDownView(jint, local_ref< android::view::View > const&, local_ref< android::view::ViewGroup > const&);
local_ref< android::view::View > newView(local_ref< android::content::Context > const&, local_ref< android::database::Cursor > const&, local_ref< android::view::ViewGroup > const&);
local_ref< android::view::View > newDropDownView(local_ref< android::content::Context > const&, local_ref< android::database::Cursor > const&, local_ref< android::view::ViewGroup > const&);
void bindView(local_ref< android::view::View > const&, local_ref< android::content::Context > const&, local_ref< android::database::Cursor > const&);
void changeCursor(local_ref< android::database::Cursor > const&);
local_ref< java::lang::CharSequence > convertToString(local_ref< android::database::Cursor > const&);
local_ref< android::database::Cursor > runQueryOnBackgroundThread(local_ref< java::lang::CharSequence > const&);
local_ref< android::widget::Filter > getFilter();
local_ref< android::widget::FilterQueryProvider > getFilterQueryProvider();
void setFilterQueryProvider(local_ref< android::widget::FilterQueryProvider > const&);
}; //class CursorAdapter
} //namespace widget
} //namespace android
} //namespace j2cpp
#endif //J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_DECL
#else //J2CPP_INCLUDE_IMPLEMENTATION
#ifndef J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_IMPL
#define J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_IMPL
namespace j2cpp {
android::widget::CursorAdapter::operator local_ref<android::widget::SpinnerAdapter>() const
{
return local_ref<android::widget::SpinnerAdapter>(get_jobject());
}
android::widget::CursorAdapter::operator local_ref<android::widget::Adapter>() const
{
return local_ref<android::widget::Adapter>(get_jobject());
}
android::widget::CursorAdapter::operator local_ref<android::widget::Filterable>() const
{
return local_ref<android::widget::Filterable>(get_jobject());
}
android::widget::CursorAdapter::operator local_ref<android::widget::ListAdapter>() const
{
return local_ref<android::widget::ListAdapter>(get_jobject());
}
android::widget::CursorAdapter::operator local_ref<android::widget::BaseAdapter>() const
{
return local_ref<android::widget::BaseAdapter>(get_jobject());
}
android::widget::CursorAdapter::operator local_ref<java::lang::Object>() const
{
return local_ref<java::lang::Object>(get_jobject());
}
android::widget::CursorAdapter::CursorAdapter(local_ref< android::content::Context > const &a0, local_ref< android::database::Cursor > const &a1)
: object<android::widget::CursorAdapter>(
call_new_object<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(0),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(0)
>(a0, a1)
)
{
}
android::widget::CursorAdapter::CursorAdapter(local_ref< android::content::Context > const &a0, local_ref< android::database::Cursor > const &a1, jboolean a2)
: object<android::widget::CursorAdapter>(
call_new_object<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(1),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(1)
>(a0, a1, a2)
)
{
}
local_ref< android::database::Cursor > android::widget::CursorAdapter::getCursor()
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(3),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(3),
local_ref< android::database::Cursor >
>(get_jobject());
}
jint android::widget::CursorAdapter::getCount()
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(4),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(4),
jint
>(get_jobject());
}
local_ref< java::lang::Object > android::widget::CursorAdapter::getItem(jint a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(5),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(5),
local_ref< java::lang::Object >
>(get_jobject(), a0);
}
jlong android::widget::CursorAdapter::getItemId(jint a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(6),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(6),
jlong
>(get_jobject(), a0);
}
jboolean android::widget::CursorAdapter::hasStableIds()
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(7),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(7),
jboolean
>(get_jobject());
}
local_ref< android::view::View > android::widget::CursorAdapter::getView(jint a0, local_ref< android::view::View > const &a1, local_ref< android::view::ViewGroup > const &a2)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(8),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(8),
local_ref< android::view::View >
>(get_jobject(), a0, a1, a2);
}
local_ref< android::view::View > android::widget::CursorAdapter::getDropDownView(jint a0, local_ref< android::view::View > const &a1, local_ref< android::view::ViewGroup > const &a2)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(9),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(9),
local_ref< android::view::View >
>(get_jobject(), a0, a1, a2);
}
local_ref< android::view::View > android::widget::CursorAdapter::newView(local_ref< android::content::Context > const &a0, local_ref< android::database::Cursor > const &a1, local_ref< android::view::ViewGroup > const &a2)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(10),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(10),
local_ref< android::view::View >
>(get_jobject(), a0, a1, a2);
}
local_ref< android::view::View > android::widget::CursorAdapter::newDropDownView(local_ref< android::content::Context > const &a0, local_ref< android::database::Cursor > const &a1, local_ref< android::view::ViewGroup > const &a2)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(11),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(11),
local_ref< android::view::View >
>(get_jobject(), a0, a1, a2);
}
void android::widget::CursorAdapter::bindView(local_ref< android::view::View > const &a0, local_ref< android::content::Context > const &a1, local_ref< android::database::Cursor > const &a2)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(12),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(12),
void
>(get_jobject(), a0, a1, a2);
}
void android::widget::CursorAdapter::changeCursor(local_ref< android::database::Cursor > const &a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(13),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(13),
void
>(get_jobject(), a0);
}
local_ref< java::lang::CharSequence > android::widget::CursorAdapter::convertToString(local_ref< android::database::Cursor > const &a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(14),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(14),
local_ref< java::lang::CharSequence >
>(get_jobject(), a0);
}
local_ref< android::database::Cursor > android::widget::CursorAdapter::runQueryOnBackgroundThread(local_ref< java::lang::CharSequence > const &a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(15),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(15),
local_ref< android::database::Cursor >
>(get_jobject(), a0);
}
local_ref< android::widget::Filter > android::widget::CursorAdapter::getFilter()
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(16),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(16),
local_ref< android::widget::Filter >
>(get_jobject());
}
local_ref< android::widget::FilterQueryProvider > android::widget::CursorAdapter::getFilterQueryProvider()
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(17),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(17),
local_ref< android::widget::FilterQueryProvider >
>(get_jobject());
}
void android::widget::CursorAdapter::setFilterQueryProvider(local_ref< android::widget::FilterQueryProvider > const &a0)
{
return call_method<
android::widget::CursorAdapter::J2CPP_CLASS_NAME,
android::widget::CursorAdapter::J2CPP_METHOD_NAME(18),
android::widget::CursorAdapter::J2CPP_METHOD_SIGNATURE(18),
void
>(get_jobject(), a0);
}
J2CPP_DEFINE_CLASS(android::widget::CursorAdapter,"android/widget/CursorAdapter")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,0,"<init>","(Landroid/content/Context;Landroid/database/Cursor;)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,1,"<init>","(Landroid/content/Context;Landroid/database/Cursor;Z)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,2,"init","(Landroid/content/Context;Landroid/database/Cursor;Z)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,3,"getCursor","()Landroid/database/Cursor;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,4,"getCount","()I")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,5,"getItem","(I)Ljava/lang/Object;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,6,"getItemId","(I)J")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,7,"hasStableIds","()Z")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,8,"getView","(ILandroid/view/View;Landroid/view/ViewGroup;)Landroid/view/View;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,9,"getDropDownView","(ILandroid/view/View;Landroid/view/ViewGroup;)Landroid/view/View;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,10,"newView","(Landroid/content/Context;Landroid/database/Cursor;Landroid/view/ViewGroup;)Landroid/view/View;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,11,"newDropDownView","(Landroid/content/Context;Landroid/database/Cursor;Landroid/view/ViewGroup;)Landroid/view/View;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,12,"bindView","(Landroid/view/View;Landroid/content/Context;Landroid/database/Cursor;)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,13,"changeCursor","(Landroid/database/Cursor;)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,14,"convertToString","(Landroid/database/Cursor;)Ljava/lang/CharSequence;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,15,"runQueryOnBackgroundThread","(Ljava/lang/CharSequence;)Landroid/database/Cursor;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,16,"getFilter","()Landroid/widget/Filter;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,17,"getFilterQueryProvider","()Landroid/widget/FilterQueryProvider;")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,18,"setFilterQueryProvider","(Landroid/widget/FilterQueryProvider;)V")
J2CPP_DEFINE_METHOD(android::widget::CursorAdapter,19,"onContentChanged","()V")
} //namespace j2cpp
#endif //J2CPP_ANDROID_WIDGET_CURSORADAPTER_HPP_IMPL
#endif //J2CPP_INCLUDE_IMPLEMENTATION
| [
"baldzar@gmail.com"
] | baldzar@gmail.com |
e891b3fb55a2ac1dda44e1cfc50405c7c50b9061 | b22588340d7925b614a735bbbde1b351ad657ffc | /athena/Control/AthenaMonitoring/AthenaMonitoring/DQEventFlagFilterTool.h | e412a729a9a730d332041a96816ce017a0dbc844 | [] | no_license | rushioda/PIXELVALID_athena | 90befe12042c1249cbb3655dde1428bb9b9a42ce | 22df23187ef85e9c3120122c8375ea0e7d8ea440 | refs/heads/master | 2020-12-14T22:01:15.365949 | 2020-01-19T03:59:35 | 2020-01-19T03:59:35 | 234,836,993 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 908 | h | /*
Copyright (C) 2002-2017 CERN for the benefit of the ATLAS collaboration
*/
#ifndef DQEVENTFLAGFILTERTOOL_H
#define DQEVENTFLAGFILTERTOOL_H
#include "AthenaMonitoring/IDQFilterTool.h"
#include "AthenaBaseComps/AthAlgTool.h"
#include "GaudiKernel/StatusCode.h"
#include "GaudiKernel/ToolHandle.h"
// This filter tool only accepts events which do not fail DP event cleaning cuts
// @author Peter Onyisi <ponyisi@cern.ch>
class DQEventFlagFilterTool : public AthAlgTool, virtual public IDQFilterTool {
public:
DQEventFlagFilterTool(const std::string&,const std::string&,const IInterface*);
virtual ~DQEventFlagFilterTool () override;
virtual StatusCode initialize() override;
virtual bool accept() const override;
private:
bool m_alwaysReturnTrue;
bool m_invert;
bool m_doLAr;
bool m_doTile;
bool m_doSCT;
bool m_doCore;
};
#endif //DQEVENTFLAGFILTERTOOL_H
| [
"rushioda@lxplus754.cern.ch"
] | rushioda@lxplus754.cern.ch |
e73f92fadfd061cbeb83abc655aa8c4335c3a655 | fd57ede0ba18642a730cc862c9e9059ec463320b | /native/libs/gui/tests/FillBuffer.cpp | 7642d03eaaed18fb873202cd2977b2b07fce6451 | [
"LicenseRef-scancode-unicode",
"Apache-2.0"
] | permissive | kailaisi/android-29-framwork | a0c706fc104d62ea5951ca113f868021c6029cd2 | b7090eebdd77595e43b61294725b41310496ff04 | refs/heads/master | 2023-04-27T14:18:52.579620 | 2021-03-08T13:05:27 | 2021-03-08T13:05:27 | 254,380,637 | 1 | 1 | null | 2023-04-15T12:22:31 | 2020-04-09T13:35:49 | C++ | UTF-8 | C++ | false | false | 4,251 | cpp | /*
* Copyright 2013 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "FillBuffer.h"
#include <ui/GraphicBuffer.h>
#include <gtest/gtest.h>
namespace android {
void fillYV12Buffer(uint8_t* buf, int w, int h, int stride) {
const int blockWidth = w > 16 ? w / 16 : 1;
const int blockHeight = h > 16 ? h / 16 : 1;
const int yuvTexOffsetY = 0;
int yuvTexStrideY = stride;
int yuvTexOffsetV = yuvTexStrideY * h;
int yuvTexStrideV = (yuvTexStrideY/2 + 0xf) & ~0xf;
int yuvTexOffsetU = yuvTexOffsetV + yuvTexStrideV * h/2;
int yuvTexStrideU = yuvTexStrideV;
for (int x = 0; x < w; x++) {
for (int y = 0; y < h; y++) {
int parityX = (x / blockWidth) & 1;
int parityY = (y / blockHeight) & 1;
unsigned char intensity = (parityX ^ parityY) ? 63 : 191;
buf[yuvTexOffsetY + (y * yuvTexStrideY) + x] = intensity;
if (x < w / 2 && y < h / 2) {
buf[yuvTexOffsetU + (y * yuvTexStrideU) + x] = intensity;
if (x * 2 < w / 2 && y * 2 < h / 2) {
buf[yuvTexOffsetV + (y*2 * yuvTexStrideV) + x*2 + 0] =
buf[yuvTexOffsetV + (y*2 * yuvTexStrideV) + x*2 + 1] =
buf[yuvTexOffsetV + ((y*2+1) * yuvTexStrideV) + x*2 + 0] =
buf[yuvTexOffsetV + ((y*2+1) * yuvTexStrideV) + x*2 + 1] =
intensity;
}
}
}
}
}
void fillYV12BufferRect(uint8_t* buf, int w, int h, int stride,
const android_native_rect_t& rect) {
const int yuvTexOffsetY = 0;
int yuvTexStrideY = stride;
int yuvTexOffsetV = yuvTexStrideY * h;
int yuvTexStrideV = (yuvTexStrideY/2 + 0xf) & ~0xf;
int yuvTexOffsetU = yuvTexOffsetV + yuvTexStrideV * h/2;
int yuvTexStrideU = yuvTexStrideV;
for (int x = 0; x < w; x++) {
for (int y = 0; y < h; y++) {
bool inside = rect.left <= x && x < rect.right &&
rect.top <= y && y < rect.bottom;
buf[yuvTexOffsetY + (y * yuvTexStrideY) + x] = inside ? 240 : 64;
if (x < w / 2 && y < h / 2) {
bool inside = rect.left <= 2*x && 2*x < rect.right &&
rect.top <= 2*y && 2*y < rect.bottom;
buf[yuvTexOffsetU + (y * yuvTexStrideU) + x] = 16;
buf[yuvTexOffsetV + (y * yuvTexStrideV) + x] =
inside ? 16 : 255;
}
}
}
}
void fillRGBA8Buffer(uint8_t* buf, int w, int h, int stride) {
const size_t PIXEL_SIZE = 4;
for (int x = 0; x < w; x++) {
for (int y = 0; y < h; y++) {
off_t offset = (y * stride + x) * PIXEL_SIZE;
for (int c = 0; c < 4; c++) {
int parityX = (x / (1 << (c+2))) & 1;
int parityY = (y / (1 << (c+2))) & 1;
buf[offset + c] = (parityX ^ parityY) ? 231 : 35;
}
}
}
}
void produceOneRGBA8Frame(const sp<ANativeWindow>& anw) {
android_native_buffer_t* anb;
ASSERT_EQ(NO_ERROR, native_window_dequeue_buffer_and_wait(anw.get(),
&anb));
ASSERT_TRUE(anb != nullptr);
sp<GraphicBuffer> buf(GraphicBuffer::from(anb));
uint8_t* img = nullptr;
ASSERT_EQ(NO_ERROR, buf->lock(GRALLOC_USAGE_SW_WRITE_OFTEN,
(void**)(&img)));
fillRGBA8Buffer(img, buf->getWidth(), buf->getHeight(), buf->getStride());
ASSERT_EQ(NO_ERROR, buf->unlock());
ASSERT_EQ(NO_ERROR, anw->queueBuffer(anw.get(), buf->getNativeBuffer(),
-1));
}
} // namespace android
| [
"541018378@qq.com"
] | 541018378@qq.com |
4f7362bb0161bf7624ce919523ccdb50f33707dc | 97c3a0cdc0894e08d2afebbd1a6e86e3233312d2 | /data/cws/src/hitwall/src/simwallsensor.cpp | 2c93ca4a007de3161d2c33fb4e3a92498b40677c | [
"MIT",
"BSD-2-Clause"
] | permissive | elbaum/phys | 139c17d9e4a5ed257657be9e5a3b4c580c460448 | 6ac580323493a5c6bb6846d039ae51e9ed1ec8b6 | refs/heads/master | 2020-03-21T13:25:09.513340 | 2018-06-24T21:05:43 | 2018-06-24T21:05:43 | 138,604,505 | 0 | 0 | MIT | 2018-06-25T14:15:26 | 2018-06-25T14:15:26 | null | UTF-8 | C++ | false | false | 4,740 | cpp | #include <iostream>
#include "ros/ros.h"
#include "gazebo_msgs/ModelState.h"
#include "gazebo_msgs/GetModelState.h"
#include "gazebo_msgs/SpawnModel.h"
#include "nav_msgs/Odometry.h"
#include "std_msgs/Empty.h"
#include "geometry_msgs/Twist.h"
#include "tf/tf.h"
#include "tf/transform_broadcaster.h"
#include <tinyxml.h>
#include <gazebo/transport/transport.hh>
#include <gazebo/msgs/msgs.hh>
#include <gazebo/gazebo.hh>
bool KeepGoing = true;
bool ShouldMeasureInitialPosition = true;
float InitialPosition = 0;
float xpos;
float ypos;
float theta;
void subFunc(nav_msgs::Odometry eventMsg)
{
//raw data
xpos = eventMsg.pose.pose.position.x;
ypos = eventMsg.pose.pose.position.y;
theta = eventMsg.twist.twist.angular.z;
//std::cout << " \t x:" << xpos << "\t y: " << ypos << "\t theta: " << theta << "\n";
}
/////////////////////////////////////////////////
// Function is called everytime a message is received.
/*
void cb(ConstWorldStatisticsPtr &_msg)
{
// Dump the message contents to stdout.
std::cout << _msg->DebugString();
}
*/
int main(int argc, char **argv)
{
ros::init(argc, argv, "simwallsensor");
ros::NodeHandle SimwallsensorNode;
ros::Rate loop_rate(10);
//GAZEBO TOPIC SUBSCRIBER
/*
// Create our node for communication
gazebo::transport::NodePtr node(new gazebo::transport::Node());
node->Init();
// Listen to Gazebo world_stats topic
gazebo::transport::SubscriberPtr sub = node->Subscribe("/gazebo/default/hokuyo/link/laser/scan", cb);
// Busy wait loop...replace with your own code as needed.
while (true)
gazebo::common::Time::MSleep(10);
// Make sure to shut everything down.
gazebo::transport::fini();
*/
//SETUP CLIENT FOR MODEL STATE
ros::service::waitForService("/gazebo/get_model_state");
ros::ServiceClient getModelStateClient =
SimwallsensorNode.serviceClient<gazebo_msgs::GetModelState>("/gazebo/get_model_state");
gazebo_msgs::GetModelState getModelState;
getModelState.request.model_name = "mobile_base";
//SPAWN CUBES
ros::service::waitForService("/gazebo/spawn_sdf_model");
ros::ServiceClient spawnCubesClient =
SimwallsensorNode.serviceClient<gazebo_msgs::SpawnModel>("/gazebo/spawn_sdf_model");
//~/gazebo_models/nist_maze_wall_240/
gazebo_msgs::SpawnModel spawnModelSrv;
spawnModelSrv.request.model_name = "nist_maze_wall_240";
spawnModelSrv.request.model_xml = "nist_maze_wall_240";
spawnModelSrv.request.initial_pose.position.x = 1;
spawnModelSrv.request.initial_pose.position.y = 1;
spawnModelSrv.request.initial_pose.position.z = 0.5;
spawnCubesClient.call(spawnModelSrv);
/*
//FROM ROS spawnbox.cpp start
ros::service::waitForService("gazebo/spawn_sdf_model");
ros::ServiceClient spawn_model_client = SimwallsensorNode.serviceClient<gazebo_msgs::SpawnModel>("gazebo/spawn_sdf_model");
gazebo_msgs::SpawnModel spawn_model;
spawn_model.request.model_name = "box1";
// load sdf file
std::string urdf_filename = std::string("~/gazebo_models/nist_maze_wall_240/model.sdf");
ROS_DEBUG("loading file: %s",urdf_filename.c_str());
// read sdf / gazebo model xml from file
TiXmlDocument xml_in(urdf_filename);
xml_in.LoadFile();
std::ostringstream stream;
stream << xml_in;
spawn_model.request.model_xml = stream.str(); // load xml file
ROS_DEBUG("XML string: %s",stream.str().c_str());
spawn_model.request.robot_namespace = "";
geometry_msgs::Pose pose;
pose.position.x = pose.position.y = 0; pose.position.z = 1;
pose.orientation.w = 1.0; pose.orientation.x = pose.orientation.y = pose.orientation.z = 0;
spawn_model.request.initial_pose = pose;
spawn_model.request.reference_frame = "";
spawn_model_client.call(spawn_model);
//FROM ROS spawnbox.cpp end
*/
std::cout << "model out..\n";
ros::Publisher pubName = SimwallsensorNode.advertise<geometry_msgs::Twist>("/mobile_base/commands/velocity", 1000);
ros::Subscriber subName = SimwallsensorNode.subscribe("/odom", 100, subFunc);
while (ros::ok())
{
getModelStateClient.call(getModelState);
std::cout << getModelState.response.pose.position.x << "\t";
std::cout << getModelState.response.pose.position.y << "\t";
tf::Pose pose;
tf::poseMsgToTF(getModelState.response.pose, pose);
double yaw_angle = tf::getYaw(pose.getRotation());
//getModelState.response.pose.orientation.z
std::cout << yaw_angle << "\n";
if(KeepGoing == true){
geometry_msgs::Twist twistMsg;
twistMsg.linear.x=0.0;
twistMsg.linear.y=0.0;
twistMsg.linear.z=0.0;
twistMsg.angular.x=0.0;
twistMsg.angular.y=0.0;
twistMsg.angular.z=0.0;
pubName.publish(twistMsg);
} else {
std::cout << " Really Stopped!!!";
}
ros::spinOnce();
loop_rate.sleep();
}
}
| [
"jpwco@bitbucket.org"
] | jpwco@bitbucket.org |
2e9cc3076709646209c2d2b9af6683e25d6c2a84 | 4213fd574b08a9bc4c02de4fc5fddec53e99994a | /wecon_wtest/common/PERMZ.INC | 79a54192d2ad2dc162d1a283c5d9d8a4e50f4242 | [] | no_license | OPM/opm-tests | a5a76fa747b7076c65cb05b8a7536939344aaf9f | c92774e32de36d5a2309f1fdd8d9251ebe53fc6e | refs/heads/master | 2023-08-28T01:06:21.274269 | 2023-08-23T21:03:02 | 2023-08-23T21:03:02 | 121,263,124 | 21 | 70 | null | 2023-09-14T08:39:55 | 2018-02-12T15:22:07 | ECL | UTF-8 | C++ | false | false | 61,581 | inc | -- This reservoir simulation deck is made available under the Open Database
-- License: http://opendatacommons.org/licenses/odbl/1.0/. Any rights in
-- individual contents of the database are licensed under the Database Contents
-- License: http://opendatacommons.org/licenses/dbcl/1.0/
-- Copyright (C) 2015 SINTEF ICT, Applied Mathematics
-- Copyright (C) 2015 Statoil
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| [
"tor.harald.sandve@iris.no"
] | tor.harald.sandve@iris.no |
d374213e0a4b6b019a55c737e743286157090f12 | 3f7028cc89a79582266a19acbde0d6b066a568de | /tools/testdata/check_format/counter_from_string.cc | 07c1cdad54ef18bd22f3adffd1eaf879316368d9 | [
"Apache-2.0",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | envoyproxy/envoy | 882d3c7f316bf755889fb628bee514bb2f6f66f0 | 72f129d273fa32f49581db3abbaf4b62e3e3703c | refs/heads/main | 2023-08-31T09:20:01.278000 | 2023-08-31T08:58:36 | 2023-08-31T08:58:36 | 65,214,191 | 21,404 | 4,756 | Apache-2.0 | 2023-09-14T21:56:37 | 2016-08-08T15:07:24 | C++ | UTF-8 | C++ | false | false | 112 | cc | namespace Envoy {
void init(Stats::Scope& scope) {
scope.counterFromString("hello");
}
} // namespace Envoy
| [
"noreply@github.com"
] | envoyproxy.noreply@github.com |
c282e3138d41f3c8d8e0ca3f03d54bc7225d3546 | 68f4dcbed619df4c336dcc315a0ff793fee1dde4 | /ece250.h | 74b142de29a67ff0ca5a4fcd3c6ed13de99d60d5 | [] | no_license | EIivaras/ECE250Project4 | 2b3a762006e38e6dbe1b631faaca1f3f0422aea4 | 36250e0fc618494b32248d20a2336d48fd9fa2be | refs/heads/master | 2021-01-25T10:39:04.516364 | 2018-03-07T21:07:09 | 2018-03-07T21:07:09 | 123,366,520 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 16,368 | h | #ifndef ECE250
#define ECE250
#include <cstdlib>
#include <iostream>
/* #include <sstream> */
#include <iomanip>
#include <string>
#include <cstring>
#include <cmath>
#include <ctime>
#include "Exception.h"
/****************************************************************************
* **************************************************************************
* * You don't have to use the Tester classes to use this to manage your
* * memory. All you must do is include this file and then, if you ever
* * want to test if you have memory which is currently unallocated,
* * you may use ece250::allocation_table.summary();
* *
* * You must simply indicate that you want to start recording by
* * using ece250::alocation_table.summary();
* *
* **************************************************************************
****************************************************************************/
/****************************************************************************
* ece250
* Author: Douglas Wilhelm Harder
* Copyright (c) 2006-13 by Douglas Wilhelm Harder and Vajih Montaghami. All rights reserved.
*
* DO NOT EDIT THIS FILE
*
* This file is broken into two parts:
*
* 1. The first namespace ece250 is associated with tools used by the
* second part.
* 2. The second has globally overloaded new, delete, new[], and delete[].
*
* This tracks everything that deals with memory allocation (new and new[])
* and memory deallocation (delete and delete[]).
*
* Each time 'new' or 'new[]' is called, an appropriate entry is
* set in a hash table 'allocation_table'. The hash function of any address
* is the last log[2](array_size) bits.
*
* Each time that 'delete' or 'delete[]' is called, it is checked whether:
* 1. the memory was actually allocated,
* 2. the appropriate form of delete versus delete[] is being called, and
* 3. delete/delete[] has been called multiple times.
*
* The class also stores how much memory was allocated and how much was
* deallocated. The summary() function prints a summary indicating the
* difference. When this is called at the end of a test, the result must
* be zero (0).
*
* If there is a problem with either allocation or deallocation, two events
* occur: a warning is printed and an exception is thrown.
*
* Each throw is associated with a warning sent to the student through cout.
****************************************************************************/
namespace ece250 {
int memory_alloc_store;
const size_t PAD = 16;
class overflow {};
class invalid_deletion {};
class invalid_input {};
// Each time a student calls either new or new[], the
// information about the memory allocation is stored in
// an instance of this class
class Stopwatch {
private:
clock_t start_time;
float duration;
public:
Stopwatch() {
duration = 0;
}
void start() {
start_time = std::clock();
}
void stop() {
clock_t end_time = std::clock();
//this supposed to be milisecond
duration = ((float)end_time - start_time) / CLOCKS_PER_SEC;
}
float get_last_duration() const {
return duration;
}
};
class Allocation {
public:
void *address;
size_t size;
bool is_array;
bool deleted;
Allocation() :
address(0),
size(0),
is_array(false),
deleted(false) {
// Empty constructor
}
Allocation(void *a, size_t s, bool i) :
address(a),
size(s),
is_array(i),
deleted(false) {
// Empty constructor
}
};
int to_int(int *ptr) {
int result = *ptr;
if (result < 0) {
result = result + (1 << (sizeof(int) - 1));
}
return result >> 3;
}
// All instances of an allocation are stored in this chained hash table
class HashTable {
private:
int array_size;
Allocation *allocated;
int total_memory_alloc;
int total_memory_deleted;
bool record;
public:
// Initialize all of the addresses to 0
HashTable(int as) :
array_size(as),
total_memory_alloc(0),
total_memory_deleted(0),
record(false) {
allocated = new Allocation[array_size];
}
void reserve(int N) {
// N must be a power of 2
if ((N & ((~N) + 1)) != N) {
throw illegal_argument();
}
delete[] allocated;
array_size = N;
allocated = new Allocation[array_size];
}
int memory_alloc() const {
return total_memory_alloc - total_memory_deleted;
}
void memory_store() const {
memory_alloc_store = total_memory_alloc - total_memory_deleted;
}
void memory_change(int n) const {
int memory_alloc_diff = total_memory_alloc - total_memory_deleted - memory_alloc_store;
if (memory_alloc_diff != n) {
std::cout << "WARNING: expecting a change in memory allocation of "
<< n << " bytes, but the change was " << memory_alloc_diff
<< std::endl;
}
}
// Insert uses the last log[2]( array_size ) bits of the address as the hash function
// It finds an unallocated entry in the array and stores the information
// about the memory allocation in that entry, including:
// The amount of memory allocated,
// Whether new or new[] was used for the allocation, and
// The address of the allocated memory.
void insert(void *ptr, size_t size, bool is_array) {
if (!record) {
return;
}
// the hash function is the last log[2]( array_size ) bits
int hash = to_int(reinterpret_cast<int *>(&ptr)) & (array_size - 1);
for (int i = 0; i < array_size; ++i) {
// It may be possible that we are allocated the same memory
// location twice (if there are numerous allocations and
// deallocations of memory. Thus, the second check is necessary,
// otherwise it may introduce session dependant errors.
if (allocated[hash].address == 0 || allocated[hash].address == ptr) {
// Store the address, the amount of memory allocated,
// whether or not new[] was used, and set 'deleted' to false.
allocated[hash] = Allocation(ptr, size, is_array);
// Add the memory allocated to the total memory allocated.
total_memory_alloc += size;
return;
}
hash = (hash + 1) & (array_size - 1);
}
std::cout << "WARNING: allocating more memory than is allowed for this project" << std::endl;
throw overflow();
}
// Remove checks:
// If the given memory location was allocated in the first place, and
// If the appropriate form of delete was used, i.e., delete versus delete[], and
// If delete has already been called on this object
size_t remove(void *ptr, bool is_array) {
if (!record || ptr == 0) {
return 0;
}
// the hash function is the last log[2]( array_size ) bits
int hash = to_int(reinterpret_cast<int *>(&ptr)) & (array_size - 1);
// Continue searching until we've checked all bins
// or we find an empty bin.
for (int i = 0; i < array_size && allocated[hash].address != 0; ++i) {
if (allocated[hash].address == ptr) {
// First check if:
// 1. If the wrong delete was called (e.g., delete[] when new was
// used or delete when new[] was used).
// 2. If the memory has already been deallocated previously.
//
// If the deletion is successful, then:
// 1. Set the 'deleted' flag to 'true', and
// 2. Add the memory deallocated ot the total memory deallocated.
if (allocated[hash].is_array != is_array) {
if (allocated[hash].is_array) {
std::cout << "WARNING: use 'delete [] ptr;' to free memory allocated with 'ptr = new Class[array_size];'" << std::endl;
}
else {
std::cout << "WARNING: use 'delete ptr;' to free memory allocated with 'ptr = new Class(...);'" << std::endl;
}
throw invalid_deletion();
}
else if (allocated[hash].deleted) {
std::cout << "WARNING: calling delete twice on the same memory location: " << ptr << std::endl;
throw invalid_deletion();
}
allocated[hash].deleted = true;
total_memory_deleted += allocated[hash].size;
// zero the memory before it is deallocated
char *cptr = static_cast<char *>(ptr);
for (size_t j = 0; j < allocated[hash].size; ++j) {
cptr[j] = 0;
}
return allocated[hash].size;
}
hash = (hash + 1) & (array_size - 1);
}
// If we've gotten this far, this means that the address was
// never allocated, and therefore we are calling delete on
// something which should be deleted.
std::cout << "WARNING: deleting a pointer to which memory was never allocated: " << ptr << std::endl;
throw invalid_deletion();
}
// Print a difference between the memory allocated and the memory deallocated
void summary() {
std::cout << "Memory allocated minus memory deallocated: "
<< total_memory_alloc - total_memory_deleted << std::endl;
}
// Print the difference between total memory allocated and total memory deallocated.
void details() {
std::cout << "SUMMARY OF MEMORY ALLOCATION:" << std::endl;
std::cout << " Memory allocated: " << total_memory_alloc << std::endl;
std::cout << " Memory deallocated: " << total_memory_deleted << std::endl << std::endl;
std::cout << "INDIVIDUAL REPORT OF MEMORY ALLOCATION:" << std::endl;
std::cout << " Address Using Deleted Bytes " << std::endl;
for (int i = 0; i < array_size; ++i) {
if (allocated[i].address != 0) {
std::cout << " " << allocated[i].address
<< (allocated[i].is_array ? " new[] " : " new ")
<< (allocated[i].deleted ? "Y " : "N ")
<< std::setw(6)
<< allocated[i].size << std::endl;
}
}
}
// Start recording memory allocations
void start_recording() {
record = true;
}
// Stop recording memory allocations
void stop_recording() {
record = false;
}
bool is_recording() {
return record;
}
};
bool asymptotic_tester(double *array, int N, int k, bool ln) {
double *ratios = new double[N];
double *differences = new double[N - 1];
int M = 2;
for (int i = 0; i < N; ++i) {
ratios[i] = array[i] / (M*(ln ? std::log(static_cast<double>(M)) : 1.0));
M = M * (1 << k);
}
for (int i = 0; i < N - 1; ++i) {
differences[i] = ratios[i + 1] - ratios[i];
// std::cout << differences[i] << std::endl;
}
for (int i = 1; i < N - 1; ++i) {
if (!(differences[i] < 0)) {
if (differences[i] > differences[i - 1]) {
delete[] ratios;
delete[] differences;
return false;
}
}
}
delete[] ratios;
delete[] differences;
return true;
}
HashTable allocation_table(8192);
std::string history[1000];
int count = 0;
// Set the contents of the allocated memory to alternating 0s and 1s
// 'U' = 0b01010101
// Four bytes are therefore 0x55555555 or 1431655765
//
// Sixteen bytes before and after the requested memory are also allocated and initialized.
// ________________ ________________
// UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
void initialize_array_bounds(char *ptr, size_t size) {
std::memset(ptr, 'U', size);
}
// When the user returns memory, we must check that the padding is unchaged.
// ________________ ________________
// UUUUUUUUUUUUUUUUxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxUUUUUUUUUUUUUUUU
// We also check that the memory has been used--if allocated memory is left untouched,
// there was an unnecessary allocation of memory.
//
// Finally, we reset all the entries to 'U' to ensure that if the user attempts to
// access this memory again, an error will occur.
// ________________ ________________
// UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
void check_array_bounds(char *ptr, size_t size) {
for (size_t i = 0; i < PAD; ++i) {
if (ptr[i] != 'U') {
std::cout << "Memory before the array located at adderss "
<< static_cast<void *>(ptr + PAD) << " was overwritten" << std::endl;
throw out_of_range();
}
if (ptr[size - 1 - i] != 'U') {
std::cout << "Memory after the array located at adderss "
<< static_cast<void *>(ptr + PAD) << " was overwritten" << std::endl;
throw out_of_range();
}
}
bool used = false;
for (size_t i = 0; i < size - 2 * PAD; ++i) {
if (ptr[PAD + i] != 'U') {
used = true;
break;
}
}
if (!used) {
std::cout << "The memory allocated at adderss "
<< static_cast<void *>(ptr + PAD) << " was not used" << std::endl;
}
std::memset(ptr, 'U', size);
}
/* // Type input<Type>()
//
// Attempt to parse the input as if it is of the given Type
// - If it fails, it prints an error message and throws an exception
template <typename Type>
Type input() {
std::string s;
std::cin >> s;
std::stringstream ss( s );
Type n;
ss >> n;
if ( ss.fail() ) {
std::cerr << "Not expecting the input \"" << s << "\"" << std::endl;
throw invalid_input();
}
return n;
}
// bool input<bool>()
//
// This is a specialization of the input function for Boolean values
// - It will accept the strings 'true' and 'false' as well as 1 and 0
// - If it fails, it prints an error message and throws an exception
template <>
bool input<bool>() {
std::string s;
std::cin >> s;
std::stringstream ss( s );
if ( s == "true" ) {
return 1;
} else if ( s == "false" ) {
return 0;
} else {
bool n;
ss >> n;
if ( ss.fail() ) {
std::cerr << "Not expecting the input \"" << s << "\"" << std::endl;
throw invalid_input();
}
return n;
}
} */
}
/****************************************************************************
* new
* Author: Douglas Wilhelm Harder
* Overloads the global operator new
*
* Use malloc to perform the allocation.
* Insert the pointer returned by malloc into the hash table.
*
* The argument 'false' indicates that this is a call
* to new (versus a call to new[]).
*
* Return the pointer to the user.
****************************************************************************/
void *operator new(size_t size) throw(std::bad_alloc) {
void *ptr = malloc(size);
ece250::allocation_table.insert(ptr, size, false);
return static_cast<void *>(ptr);
}
/****************************************************************************
* delete
* Author: Douglas Wilhelm Harder
* Overloads the global operator delete
*
* Remove the pointer from the hash table (the entry is not truly removed,
* simply marked as removed).
*
* The argument 'false' indicates that this is a call
* to delete (versus a call to delete[]).
*
* Use free to perform the deallocation.
****************************************************************************/
void operator delete(void *ptr) throw () {
ece250::allocation_table.remove(ptr, false);
free(ptr);
}
/****************************************************************************
* new[]
* Author: Douglas Wilhelm Harder
* Overloads the global operator new[]
*
* Use malloc to perform the allocation.
* Insert the pointer returned by malloc into the hash table.
*
* The argument 'true' indicates that this is a call
* to new[] (versus a call to new).
*
* Return the pointer to the user.
****************************************************************************/
void *operator new[](size_t size) throw(std::bad_alloc) {
char *ptr = static_cast<char *>(malloc(size + 2 * ece250::PAD));
ece250::allocation_table.insert(static_cast<void *>(ptr + ece250::PAD), size, true);
ece250::initialize_array_bounds(ptr, size + 2 * ece250::PAD);
return static_cast<void *>(ptr + ece250::PAD);
}
/****************************************************************************
* delete[]
* Author: Douglas Wilhelm Harder
* Overloads the global operator delete[]
*
* Remove the pointer from the hash table (the entry is not truly removed,
* simply marked as removed).
*
* The argument 'true' indicates that this is a call
* to delete[] (versus a call to delete).
*
* Use free to perform the deallocation.
****************************************************************************/
void operator delete[](void *ptr) throw () {
size_t size = ece250::allocation_table.remove(ptr, true);
if (ece250::allocation_table.is_recording()) {
ece250::check_array_bounds(static_cast<char *>(ptr) - ece250::PAD, size + 2 * ece250::PAD);
}
free(static_cast<char *>(ptr) - ece250::PAD);
}
#endif
| [
"zach00182@gmail.com"
] | zach00182@gmail.com |
ce8c68130b903e15c4efe59fd9b2ad68c418a60e | 4bfef1b16438fcb5e59366e0ae37bf8be0cfeb3d | /CFA/5OSTAPANDGRASS.cpp | 56698e361f96557494128a1cd175660f24ac8cba | [] | no_license | RSHBSXN/CP | dec5df0b31d9dfff12d061711675c341c8df6398 | c00b6fd9ac1694fea144a5d507bd576f42ccfb91 | refs/heads/master | 2022-01-10T22:51:24.988519 | 2019-06-03T16:53:24 | 2019-06-03T16:53:24 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,049 | cpp | /*
Author: Rishabh Saxena
All the best!!
*/
#include <bits/stdc++.h>
using namespace std;
#define LL long long
#define XLL __int128
#define pii pair<int,int>
#define pll pair<LL,LL>
#define vi vector<int>
#define MATRIX vector<vector<int>>
#define MATRIXB vector<vector<bool>>
#define MATRIXC vector<vector<char>>
#define MATRIXLL vector<vector<LL>>
#define MATRIX3D vector<vector<vector<int>>>
#define MAX(A,B,C) max(A,max(B,C))
#define MIN(A,B,C) min(A,min(B,C))
#define FASTIO ios_base::sync_with_stdio(false);cin.tie(NULL)
int main(){
int n,k;
cin >> n >> k;
string s;
cin >> s;
int ind = s.find('G');
int indT = s.find('T');
bool canEat = true;
if(abs(indT - ind) % k != 0){
cout<<"NO\n";
}
else{
bool reachable = true;
int dir = (ind < indT)?1:-1;
for(int i=ind +(k * dir);i != indT;i += (k*dir)){
if(s[i] == '#'){
reachable = false;
break;
}
}
cout<<((reachable)?"YES":"NO")<<'\n';
}
}
| [
"noreply@github.com"
] | RSHBSXN.noreply@github.com |
ba43ba666a7389b8eb4e4c77aa86dbafa6213743 | ae1c2f2e5a25a267580989b573694fe0431d7be9 | /Instructors Stuff/QtExamples/5/mainwindow.cpp | 09cd0cf897e91e8dff82a7dfdc7f12347c72516f | [] | no_license | roburrq/Homework3 | b31c42fcd5fbd539726514afc2566ab7dc880c96 | f1486676f0499d3ec4b0286d1e1aa69ff34faee2 | refs/heads/master | 2022-11-14T04:34:36.040437 | 2020-07-05T15:14:36 | 2020-07-05T15:14:36 | 277,326,118 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,521 | cpp | #include "mainwindow.h"
#include "ui_mainwindow.h"
MainWindow::MainWindow(QWidget *parent) :
QMainWindow(parent),
ui(new Ui::MainWindow)
{
ui->setupUi(this);
connect(ui->m_exitButton, &QPushButton::clicked, this, &MainWindow::exit, Qt::DirectConnection);
connect(ui->m_startButton, &QPushButton::clicked, this, &MainWindow::startThread, Qt::DirectConnection);
connect(ui->m_stopButton, &QPushButton::clicked, this, &MainWindow::stopThread, Qt::DirectConnection);
}
MainWindow::~MainWindow()
{
delete ui;
}
void MainWindow::exit()
{
QApplication::exit();
}
void MainWindow::startThread()
{
m_pWorkerThread = new WorkerThread;
connect(m_pWorkerThread, &WorkerThread::ready, this, &MainWindow::showResults, Qt::QueuedConnection);
connect(m_pWorkerThread, &QThread::finished, m_pWorkerThread, &QObject::deleteLater);
connect(m_pWorkerThread, &WorkerThread::finished, this, &MainWindow::destroyThread);
connect(this, &MainWindow::stopSignal, m_pWorkerThread, &WorkerThread::stop, Qt::DirectConnection);
m_pWorkerThread->start();
ui->m_startButton->setEnabled(false);
ui->m_stopButton->setEnabled(true);
}
void MainWindow::stopThread()
{
emit stopSignal();
}
void MainWindow::destroyThread()
{
ui->m_startButton->setEnabled(true);
ui->m_stopButton->setEnabled(false);
}
void MainWindow::showResults(QString msg)
{
ui->m_resultLineEdit->clear();
ui->m_resultLineEdit->setText(msg);
}
| [
"noreply@github.com"
] | roburrq.noreply@github.com |
4b038bd64ee2385d643acdd474fe1ee04fd239a4 | 8c121b5c3dc564eb75f7cb8a1e881941d9792db9 | /old_contest/at_coder_abc183_C.cpp | 35fcb76c92e0c0091f435712b860af0148caaee1 | [] | no_license | kayaru28/programming_contest | 2f967a4479f5a1f2c30310c00c143e711445b12d | 40bb79adce823c19bbd988f77b515052c710ea42 | refs/heads/master | 2022-12-13T18:32:37.818967 | 2022-11-26T16:36:20 | 2022-11-26T16:36:20 | 147,929,424 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,899 | cpp | #include <iostream>
#include <stdio.h>
#include <algorithm>
#include <map>
#include <math.h>
using namespace std;
#include <vector>
#define rep(i,n) for (ll i = 0; i < (n) ; i++)
#define INF 1e9
#define llINF 1e18
#define base10_4 10000 //1e4
#define base10_5 100000 //1e5
#define base10_6 1000000 //1e6
#define base10_7 10000000 //1e7
#define base10_8 100000000 //1e8
#define base10_9 1000000000 //1e9
#define MOD 1000000007
#define pb push_back
#define ll long long
#define ld long double
#define ull unsigned long long
#define vint vector<int>
#define vll vector<ll>
//#include <stack>
//#include <queue>
// #include <iomanip>
// cout << fixed << setprecision(15) << y << endl;
string ans_Yes = "Yes";
string ans_No = "No";
string ans_yes = "yes";
string ans_no = "no";
ll A;
ll B;
ll C;
ll N;
ll M;
ll K;
ll ltmp;
string stmp;
double dtmp;
ll timer[10][10];
ll cnt = 0;
/*
max 448,000,000
map<string,ll> count_map;
count_map['0']=0;
for(auto x : count_map) {
string key = x.first;
ll value = x.second;
}
*/
void solver(map<ll,ll> visited,ll count, ll cost, ll from){
if(count == N){
if(from == 0){
if(cost == K) cnt++;
}
}else{
count++;
rep(to,N){
//cout << count << " : " << from << " -> " << to << " = " << visited[to] << endl;
if(visited[to]==0){
map<ll,ll> visited2;
visited2 = visited;
visited2[to]++;
ll tmpcost = cost + timer[from][to];
solver(visited2,count,tmpcost, to);
}
}
}
}
int main(){
ios::sync_with_stdio(false);
cin.tie(0);
cout.tie(0);
cin >> N;
cin >> K;
rep(ni,N){
rep(nii,N){
cin >> timer[ni][nii];
}
}
map<ll,ll> visited;
solver(visited,0,0,0);
cout << cnt << endl;
} | [
"istorytale090415@gmail.com"
] | istorytale090415@gmail.com |
ade35185dd9486e415707b14b75418ca75cccf16 | c3ea40ffec96954b955c5b1d67a05c991fbcf461 | /Server.cpp | f7b3eeb37f9b7f7a57696283797f165ad2ed4f4b | [] | no_license | msb217/File-Server | 32c8a97a8aff7b56a4271a97a6d8eadcb142f198 | a7df3500e62dbae6cdb2b8aea2afbc64ee8cd44b | refs/heads/master | 2021-08-28T17:23:14.639750 | 2017-12-12T22:50:14 | 2017-12-12T22:50:14 | 112,871,127 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 15,982 | cpp | #include <arpa/inet.h>
#include <errno.h>
#include <fcntl.h>
#include <netdb.h>
#include <netinet/in.h>
#include <openssl/md5.h>
#include <stddef.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include "support.h"
#include "Server.h"
#include <thread>
#include <mutex>
using namespace std;
mutex server_mtx;
void help(char *progname)
{
printf("Usage: %s [OPTIONS]\n", progname);
printf("Initiate a network file server\n");
printf(" -m enable multithreading mode\n");
printf(" -l number of entries in the LRU cache\n");
printf(" -p port on which to listen for connections\n");
}
void die(const char *msg1, char *msg2)
{
fprintf(stderr, "%s, %s\n", msg1, msg2);
exit(0);
}
/*
* open_server_socket() - Open a listening socket and return its file
* descriptor, or terminate the program
*/
int open_server_socket(int port)
{
int listenfd; /* the server's listening file descriptor */
struct sockaddr_in addrs; /* describes which clients we'll accept */
int optval = 1; /* for configuring the socket */
/* Create a socket descriptor */
if((listenfd = socket(AF_INET, SOCK_STREAM, 0)) < 0)
{
die("Error creating socket: ", strerror(errno));
}
/* Eliminates "Address already in use" error from bind. */
if(setsockopt(listenfd, SOL_SOCKET, SO_REUSEADDR, (const void *)&optval , sizeof(int)) < 0)
{
die("Error configuring socket: ", strerror(errno));
}
/* Listenfd will be an endpoint for all requests to the port from any IP
address */
bzero((char *) &addrs, sizeof(addrs));
addrs.sin_family = AF_INET;
addrs.sin_addr.s_addr = htonl(INADDR_ANY);
addrs.sin_port = htons((unsigned short)port);
if(bind(listenfd, (struct sockaddr *)&addrs, sizeof(addrs)) < 0)
{
die("Error in bind(): ", strerror(errno));
}
/* Make it a listening socket ready to accept connection requests */
if(listen(listenfd, 1024) < 0) // backlog of 1024
{
die("Error in listen(): ", strerror(errno));
}
return listenfd;
}
/*
* handle_requests() - given a listening file descriptor, continually wait
* for a request to come in, and when it arrives, pass it
* to service_function. Note that this is not a
* multi-threaded server.
*/
void handle_requests(int listenfd, void (*service_function)(int, int), int param, bool multithread)
{
while(1)
{
/* block until we get a connection */
struct sockaddr_in clientaddr;
memset(&clientaddr, 0, sizeof(sockaddr_in));
socklen_t clientlen = sizeof(clientaddr);
int connfd;
if((connfd = accept(listenfd, (struct sockaddr *)&clientaddr, &clientlen)) < 0)
{
die("Error in accept(): ", strerror(errno));
}
/* print some info about the connection */
struct hostent *hp;
hp = gethostbyaddr((const char *)&clientaddr.sin_addr.s_addr, sizeof(clientaddr.sin_addr.s_addr), AF_INET);
if(hp == NULL)
{
fprintf(stderr, "DNS error in gethostbyaddr() %d\n", h_errno);
exit(0);
}
char *haddrp = inet_ntoa(clientaddr.sin_addr);
printf("server connected to %s (%s)\n", hp->h_name, haddrp);
/* serve requests */
if(multithread){
if(!fork()){
service_function(connfd, param);
}
if(close(connfd) < 0){
die("Error in close(): ", strerror(errno));
}
}
else{
service_function(connfd, param);
/* clean up, await new connection */
if(close(connfd) < 0)
{
die("Error in close(): ", strerror(errno));
}
}
}
}
char* hash_MD5(char* file_contents){
unsigned char digest[MD5_DIGEST_LENGTH];
MD5_CTX mdContext;
MD5_Init(&mdContext);
MD5_Update(&mdContext, file_contents, strlen(file_contents));
MD5_Final (digest ,&mdContext);
char* hashed_string = (char *)malloc(2*MD5_DIGEST_LENGTH*sizeof(char));
bzero(hashed_string, MD5_DIGEST_LENGTH);
for(int i = 0; i < MD5_DIGEST_LENGTH; i++){
sprintf(&hashed_string[i*2], "%02x", digest[i]);
}
return hashed_string;
}
bool write_OK(int connfd, char* file_name){
server_mtx.lock();
int OK_response_size = 3 + strlen(file_name) + 1;
char OK_response[OK_response_size];
sprintf(OK_response, "OK %s\n", file_name);
if(write(connfd, OK_response, OK_response_size) < 0){
fprintf(stderr, "%s", "Error writing OK\n");
server_mtx.unlock();
return false;
}
server_mtx.unlock();
return true;
}
bool write_size(int connfd, long int file_size){
server_mtx.lock();
if(write(connfd, &file_size, sizeof(file_size)) < 0){
fprintf(stderr, "%s", "Error writing file size\n");
server_mtx.unlock();
return false;
}
server_mtx.unlock();
return true;
}
bool write_hash(int connfd, char* hashed_file){
server_mtx.lock();
if(write(connfd, hashed_file, 32) < 0){
fprintf(stderr, "%s", "Error writing file hash\n");
server_mtx.unlock();
return false;
}
server_mtx.unlock();
return true;
}
bool write_file(int connfd, char* file, long file_size){
server_mtx.lock();
if(write(connfd, file, file_size) < 0){
fprintf(stderr, "%s", "Error writing file contents\n");
server_mtx.unlock();
return false;
}
server_mtx.unlock();
return true;
}
long int read_file_size(FILE* file){
server_mtx.lock();
fseek(file, 0, SEEK_END);
long int file_size = ftell(file);
fseek(file, 0, SEEK_SET);
server_mtx.unlock();
return file_size;
}
bool get_cached(int connfd, char* file_name, char** LRU, char** LRU_file_names, long int* LRU_file_sizes, char** LRU_hashes, int lru_size, bool checksum){
for(int i = 0; i < lru_size; i++){
if(LRU_file_names[i]){
if(!strncmp(LRU_file_names[i], file_name, strlen(file_name))){
if(write_OK(connfd, file_name)){
if(write_size(connfd, LRU_file_sizes[i])){
if(checksum){
if(write_hash(connfd, LRU_hashes[i])){
if(write_file(connfd, LRU[i], LRU_file_sizes[i])){
printf("Cached\n");
return true;
}
}
}
else{
if(write_file(connfd, LRU[i], LRU_file_sizes[i])){
printf("Cached\n");
return true;
}
}
}
}
}
}
}
return false;
}
bool put_cached(char* file_name, char** LRU, char** LRU_file_names, long int* LRU_file_sizes,
char** LRU_hashes, int lru_size, bool checksum, long int file_size, char* hash,
char* file_buffer, FILE* file){
for(int i = 0; i < lru_size; i++){
if(LRU_file_names[i]){
if(!strncmp(LRU_file_names[i], file_name, strlen(file_name))){
if(file_size == LRU_file_sizes[i]){
if(checksum){
if(!strncmp(LRU_hashes[i], hash, strlen(LRU_hashes[i]))){
if(!strncmp(LRU[i], file_buffer, strlen(LRU[i]))){
printf("Cached\n");
return true;
}
else{
sprintf(LRU_file_names[i], "%s", (file_name));
LRU_file_sizes[i] = file_size;
LRU_hashes[i] = hash;
LRU[i] = file_buffer;
return true;
}
}
else{
sprintf(LRU_file_names[i], "%s", (file_name));
LRU_file_sizes[i] = file_size;
LRU_hashes[i] = hash;
LRU[i] = file_buffer;
return true;
}
}
else{
if(!strncmp(LRU[i], file_buffer, strlen(LRU[i]))){
printf("Cached\n");
return true;
}
else{
sprintf(LRU_file_names[i], "%s", (file_name));
LRU_file_sizes[i] = file_size;
LRU_hashes[i] = hash;
LRU[i] = file_buffer;
return true;
}
}
}
else{
sprintf(LRU_file_names[i], "%s", (file_name));
LRU_file_sizes[i] = file_size;
LRU_hashes[i] = hash;
LRU[i] = file_buffer;
return true;
}
}
}
}
return false;
}
/*
* file_server() - Read a request from a socket, satisfy the request, and
* then close the connection.
*/
void file_server(int connfd, int lru_size)
{
const int MAXLINE = 8192;
/* LRU Cache */
/*
Acts as a circular buffer
*/
static char **LRU = (char**)malloc(sizeof(char *)*lru_size);
static char **LRU_file_names = (char**)malloc(sizeof(char *)*lru_size);
static long int* LRU_file_sizes = (long int*)malloc(sizeof(long int)*lru_size);
static char** LRU_hashes = (char**)malloc(sizeof(char *)*lru_size);
static int lru_index = 0;
static bool lru_initialized = false;
static mutex cache_mtx;
if(!lru_initialized){
cache_mtx.lock();
for(int i = 0; i < lru_size; i++){
LRU[i] = (char*)malloc(MAXLINE * sizeof(char));
LRU_file_names[i] = (char*)malloc(MAXLINE * sizeof(char));
LRU_file_sizes[i] = 0;
LRU_hashes[i] = (char*)malloc(MAXLINE * sizeof(char));
}
lru_initialized = true;
cache_mtx.unlock();
}
/*
Read the request from the given socket
*/
char buf[MAXLINE];
bzero(buf, MAXLINE);
server_mtx.lock();
read(connfd, buf, sizeof(buf));
server_mtx.unlock();
if(!strncmp(buf, "GET ", 4)){
char* moving_buffer = buf;
moving_buffer+=4;
char* file_name = strtok(moving_buffer, "\n");
/*
If the file isn't cached the code within the loop is run - otherwise
refere to get_cached to see how the Server responds with the cached contents
*/
cache_mtx.lock();
if(!get_cached(connfd, file_name, LRU, LRU_file_names, LRU_file_sizes, LRU_hashes, lru_size, false)){
cache_mtx.unlock();
FILE* get_file = fopen(file_name, "rb");
if(get_file){
write_OK(connfd, file_name);
long int file_size = read_file_size(get_file);
char* file_buffer = (char*)malloc(sizeof(char)*file_size);
fread(file_buffer, file_size, 1, get_file);
char* hashed_file = hash_MD5(file_buffer);
write_size(connfd, file_size);
write_file(connfd, file_buffer, file_size);
/*
By allowing the lru_index to be incremnted prior to accessing the
cache itself, we allow other threads to simulataneously work on
the cache with the original thread
*/
if(lru_size > 0){
cache_mtx.lock();
int temp_index = lru_index;
lru_index++;
if(lru_index == lru_size){
*(&lru_index) = 0;
}
cache_mtx.unlock();
cache_mtx.lock();
sprintf(LRU_file_names[temp_index], "%s", (file_name));
LRU_file_sizes[temp_index] = file_size;
LRU_hashes[temp_index] = hashed_file;
LRU[temp_index] = file_buffer;
cache_mtx.unlock();
}
}
else{
fprintf(stderr, "GET - File not found %s\n", file_name);
}
fclose(get_file);
}
else{
cache_mtx.unlock();
}
}
else if (!strncmp(buf, "GETC ", 5)){
char* moving_buffer = buf;
moving_buffer+=5;
char* file_name = strtok(moving_buffer, "\n");
cache_mtx.lock();
if(!get_cached(connfd, file_name, LRU, LRU_file_names, LRU_file_sizes, LRU_hashes, lru_size, true)){
cache_mtx.unlock();
FILE* get_file = fopen(file_name, "rb");
if(get_file){
write_OK(connfd, file_name);
long int file_size = read_file_size(get_file);
char *file_buffer = (char*)malloc(sizeof(char)*file_size);
fread(file_buffer, file_size, 1, get_file);
char* hashed_file = hash_MD5(file_buffer);
write_size(connfd, file_size);
/*
Same as GET except for this function
*/
write_hash(connfd, hashed_file);
write_file(connfd, file_buffer, file_size);
if(lru_size > 0){
cache_mtx.lock();
int temp_index = lru_index;
lru_index++;
if(lru_index == lru_size){
*(&lru_index) = 0;
}
cache_mtx.unlock();
cache_mtx.lock();
sprintf(LRU_file_names[temp_index], "%s", (file_name));
LRU_file_sizes[temp_index] = file_size;
LRU_hashes[temp_index] = hashed_file;
LRU[temp_index] = file_buffer;
cache_mtx.unlock();
}
fclose(get_file);
}
else{
fprintf(stderr, "GETC - File not found %s\n", file_name);
}
}
else{
cache_mtx.unlock();
}
}
else if(!strncmp(buf, "PUT ", 4)){
server_mtx.lock();
char* moving_buffer = buf;
moving_buffer+=4;
char* file_name = strtok(moving_buffer, "\n");
FILE* put_file = fopen(file_name, "wb");
if(put_file){
moving_buffer += strlen(file_name) + 1;
char* file_size_string = strtok(moving_buffer, "\n");
long int file_size = atoi(file_size_string);
moving_buffer += strlen(file_size_string) + 1;
char* file_contents = (char*)malloc((file_size+1)*sizeof(char));
strncpy(file_contents, moving_buffer, file_size);
file_contents[file_size] = '\0';
char* hash = hash_MD5(file_contents);
fwrite(file_contents, file_size, 1, put_file);
cache_mtx.lock();
if(!put_cached(file_name, LRU, LRU_file_names, LRU_file_sizes, LRU_hashes,
lru_size, false, file_size, hash, file_contents, put_file)){
cache_mtx.unlock();
if(lru_size > 0){
cache_mtx.lock();
int temp_index = lru_index;
lru_index++;
if(lru_index == lru_size){
*(&lru_index) = 0;
}
cache_mtx.unlock();
cache_mtx.lock();
sprintf(LRU_file_names[temp_index], "%s", (file_name));
LRU_file_sizes[temp_index] = file_size;
LRU_hashes[temp_index] = hash;
LRU[temp_index] = file_contents;
cache_mtx.unlock();
}
}
else{
cache_mtx.unlock();
}
}
else{
perror("Error opening file for writing");
}
fclose(put_file);
server_mtx.unlock();
}
else if(!strncmp(buf, "PUTC ", 5)){
server_mtx.lock();
char* moving_buffer = buf;
moving_buffer+=5;
char* file_name = strtok(moving_buffer, "\n");
moving_buffer += strlen(file_name) + 1;
FILE* put_file = fopen(file_name, "wb");
if(put_file){
char* file_size_string = strtok(moving_buffer, "\n");
long int file_size = atoi(file_size_string);
moving_buffer += strlen(file_size_string) + 1;
char* MD5_digest = strtok(moving_buffer, "\n");
moving_buffer += 33;
char* file_contents = (char*)malloc((file_size+1)*sizeof(char));
strncpy(file_contents, moving_buffer, file_size);
file_contents[file_size] = '\0';
char* hash = hash_MD5(file_contents);
if(!strncmp(hash, MD5_digest, 32)){
fwrite(file_contents, file_size, 1, put_file);
cache_mtx.lock();
if(!put_cached(file_name, LRU, LRU_file_names, LRU_file_sizes, LRU_hashes,
lru_size, false, file_size, hash, file_contents, put_file)){
cache_mtx.unlock();
if(lru_size > 0){
cache_mtx.lock();
int temp_index = lru_index;
lru_index++;
if(lru_index == lru_size){
*(&lru_index) = 0;
}
cache_mtx.unlock();
cache_mtx.lock();
sprintf(LRU_file_names[temp_index], "%s", (file_name));
LRU_file_sizes[temp_index] = file_size;
LRU_hashes[temp_index] = hash;
LRU[temp_index] = file_contents;
cache_mtx.unlock();
}
}
else{
cache_mtx.unlock();
}
}
else{
perror("MD5 does not match");
}
fclose(put_file);
}
server_mtx.unlock();
}
else{
printf("Invalid Request");
}
}
/*
* main() - parse command line, create a socket, handle requests
*/
int main(int argc, char **argv)
{
/* for getopt */
long opt;
int lru_size = 10;
int port = 9000;
bool multithread = false;
check_team(argv[0]);
/* parse the command-line options. They are 'p' for port number, */
/* and 'l' for lru cache size, 'm' for multi-threaded. 'h' is also supported. */
while((opt = getopt(argc, argv, "hml:p:")) != -1)
{
switch(opt)
{
case 'h': help(argv[0]); break;
case 'l': lru_size = atoi(argv[0]); break;
case 'm': multithread = true; break;
case 'p': port = atoi(optarg); break;
}
}
/* open a socket, and start handling requests */
int fd = open_server_socket(port);
handle_requests(fd, file_server, lru_size, multithread);
exit(0);
}
| [
"msb217@lehigh.edu"
] | msb217@lehigh.edu |
230cc165fc85c9cfb1e046dd1eed3fdeae77043d | c9ea4b7d00be3092b91bf157026117bf2c7a77d7 | /字符串初步/P2375.cpp | 9dce4cf7050d04ce8b96936b18c5f40078497e02 | [] | no_license | Jerry-Terrasse/Programming | dc39db2259c028d45c58304e8f29b2116eef4bfd | a59a23259d34a14e38a7d4c8c4d6c2b87a91574c | refs/heads/master | 2020-04-12T08:31:48.429416 | 2019-04-20T00:32:55 | 2019-04-20T00:32:55 | 162,387,499 | 3 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 745 | cpp | #include<iostream>
#include "memory.h"
#include<cstring>
#define MAXL 1000010
#define p 1000000007
#define ll long long
using namespace std;
ll nx[MAXL],num[MAXL],n=0,ans=1,len=0;
char s[MAXL]="";
int main()
{
ll i=0,j=0,k=0;
ios::sync_with_stdio(0);
for(cin>>n;n--;)
{
memset(nx,0,sizeof(nx));
memset(num,0,sizeof(num));
memset(s,'\0',sizeof(s));
ans=1;
cin>>s;
len=strlen(s);
for(i=1,j=0;i<len;i++)
{
for(;j && s[i]!=s[j];j=nx[j-1]);
if(s[i]==s[j])
{
j++;
}
nx[i]=j;
for(k=j;k;k=nx[k-1])
{
if((k<<1)<=i+1)
{
num[i]++;
}
}
}
for(i=0;i<len;i++)
{
ans*=num[i]+1;
ans%=p;
}
cout<<ans<<endl;
}
return 0;
}
| [
"3305049949@qq.com"
] | 3305049949@qq.com |
047b8a9ee7d624eeb8f7372214cf935ee0b092ab | a27d9bc41f5eb391a24043b60926695e01e7ff4a | /Biggest_and_smallest_in_array_with_function.cpp | 7adc05afb703a78130bf32522109410f4294bf29 | [] | no_license | Yildirim-Habr/Cpp-code | 467d051a302432a4f25afe3aa1555d76850fad14 | 56ee19d7b18a4f1dbb6f2b5705e97485e9ba5e6e | refs/heads/master | 2021-01-02T09:18:40.293467 | 2017-11-18T09:50:51 | 2017-11-18T09:50:51 | 99,190,404 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 683 | cpp | #include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <iomanip>
#include <string>
#include <vector>
#include <ctype.h>
#include <algorithm>
using namespace std;
void getValue(){
int i, num;
float val, z, maxv, minv;
cout << "How many value ? ";
cin >> num;
float ar[num] = {};
z = 0;
for(i=0; i<num; i++){
cout << "Enter the " << i+1 << " value here = ";
cin >> val;
ar[i] = val;
maxv = max(val, maxv);
minv = min(val, minv);
}
cout << "The max value is " << maxv << endl;
cout << "The min value is " << minv << endl;
}
int main() {
getValue();
return 0;
}
| [
"noreply@github.com"
] | Yildirim-Habr.noreply@github.com |
387d5f1b889644702f26e2d4af4c22dbfd6e7677 | 989c31de263a91d93f39b6bfc050259367ee0fbb | /psol/include/net/instaweb/rewriter/public/test_rewrite_driver_factory.h | 5a2a41d5dcbdf3db0dbf82ae6ed1422a73fce3fa | [
"Apache-2.0"
] | permissive | vinothwindows47/ngx_pagespeed | a00f97935721847bdec7278bac37151a98dff70e | 85a36b8133a1dc8fbb24afecacfb0a2c05616605 | refs/heads/master | 2021-01-24T00:08:44.684277 | 2013-04-26T21:39:24 | 2013-04-26T21:39:24 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 8,146 | h | /*
* Copyright 2011 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// Author: jmarantz@google.com (Joshua Marantz)
#ifndef NET_INSTAWEB_REWRITER_PUBLIC_TEST_REWRITE_DRIVER_FACTORY_H_
#define NET_INSTAWEB_REWRITER_PUBLIC_TEST_REWRITE_DRIVER_FACTORY_H_
#include <vector>
#include "net/instaweb/rewriter/public/rewrite_driver_factory.h"
#include "net/instaweb/util/public/basictypes.h"
#include "net/instaweb/util/public/scoped_ptr.h"
#include "net/instaweb/util/public/simple_stats.h"
#include "net/instaweb/util/public/string.h"
#include "net/instaweb/util/public/string_util.h"
namespace net_instaweb {
class CountingUrlAsyncFetcher;
class DelayCache;
class FakeUrlAsyncFetcher;
class FileSystem;
class Hasher;
class HtmlFilter;
class LRUCache;
class MemFileSystem;
class MessageHandler;
class MockHasher;
class MockMessageHandler;
class MockScheduler;
class MockTimer;
class MockTimeCache;
class MockUrlFetcher;
class PropertyCache;
class ServerContext;
class RewriteDriver;
class RewriteFilter;
class RewriteOptions;
class Scheduler;
class ThreadsafeCache;
class Timer;
class UrlAsyncFetcher;
class UrlFetcher;
class UrlNamer;
class WaitUrlAsyncFetcher;
// RewriteDriverFactory implementation for use in tests, using mock time,
// mock fetchers, and a memory-based file system.
class TestRewriteDriverFactory : public RewriteDriverFactory {
public:
static const int64 kStartTimeMs; // Arbitrary time to start MockTimer.
static const char kUrlNamerScheme[]; // Env.var URL_NAMER_SCHEME
class CreateFilterCallback {
public:
CreateFilterCallback() {}
virtual ~CreateFilterCallback();
virtual HtmlFilter* Done(RewriteDriver* driver) = 0;
private:
DISALLOW_COPY_AND_ASSIGN(CreateFilterCallback);
};
class CreateRewriterCallback {
public:
CreateRewriterCallback() {}
virtual ~CreateRewriterCallback();
virtual RewriteFilter* Done(RewriteDriver* driver) = 0;
private:
DISALLOW_COPY_AND_ASSIGN(CreateRewriterCallback);
};
class PlatformSpecificConfigurationCallback {
public:
PlatformSpecificConfigurationCallback() {}
virtual ~PlatformSpecificConfigurationCallback();
virtual void Done(RewriteDriver* driver) = 0;
private:
DISALLOW_COPY_AND_ASSIGN(PlatformSpecificConfigurationCallback);
};
TestRewriteDriverFactory(const StringPiece& temp_dir,
MockUrlFetcher* mock_fetcher,
MockUrlFetcher* mock_distributed_fetcher);
virtual ~TestRewriteDriverFactory();
DelayCache* delay_cache() { return delay_cache_; }
LRUCache* lru_cache() { return lru_cache_.get(); }
MockTimer* mock_timer() { return mock_timer_; }
MockHasher* mock_hasher() { return mock_hasher_; }
MemFileSystem* mem_file_system() { return mem_file_system_; }
FakeUrlAsyncFetcher* mock_url_async_fetcher() {
return mock_url_async_fetcher_.get();
}
WaitUrlAsyncFetcher* wait_url_async_fetcher() {
return wait_url_async_fetcher_.get();
}
CountingUrlAsyncFetcher* counting_url_async_fetcher() {
return counting_url_async_fetcher_;
}
CountingUrlAsyncFetcher* counting_distributed_async_fetcher() {
return counting_distributed_async_fetcher_;
}
MockTimeCache* mock_time_cache() { return mock_time_cache_.get(); }
void SetupWaitFetcher();
void CallFetcherCallbacksForDriver(RewriteDriver* driver);
MockMessageHandler* mock_message_handler() { return mock_message_handler_; }
MockScheduler* mock_scheduler() { return mock_scheduler_; }
bool use_test_url_namer() const { return use_test_url_namer_; }
void SetUseTestUrlNamer(bool x);
// Does NOT take ownership of the callback.
void AddCreateFilterCallback(CreateFilterCallback* callback) {
filter_callback_vector_.push_back(callback);
}
void ClearFilterCallbackVector() {
filter_callback_vector_.clear();
}
// Does NOT take ownership of the callback.
void AddCreateRewriterCallback(CreateRewriterCallback* callback) {
rewriter_callback_vector_.push_back(callback);
}
void ClearRewriterCallbackVector() {
rewriter_callback_vector_.clear();
}
// By default this is false, but can be reset.
virtual bool UseBeaconResultsInFilters() const {
return use_beacon_results_in_filters_;
}
void set_use_beacon_results_in_filters(bool b) {
use_beacon_results_in_filters_ = b;
}
// Does NOT take ownership of the callback.
void AddPlatformSpecificConfigurationCallback(
PlatformSpecificConfigurationCallback* callback) {
platform_config_vector_.push_back(callback);
}
void ClearPlatformSpecificConfigurationCallback() {
platform_config_vector_.clear();
}
// Note that this disables ajax rewriting by default.
virtual RewriteOptions* NewRewriteOptions();
// Note that this enables html proxying.
virtual ServerContext* NewServerContext();
virtual bool IsDebugClient(const GoogleString& ip) const {
return ip == "127.0.0.1";
}
// Enable or disable adding the contents of rewriter_callback_vector_ within
// AddPlatformSpecificRewritePasses.
void set_add_platform_specific_decoding_passes(bool value) {
add_platform_specific_decoding_passes_ = value;
}
bool add_platform_specific_decoding_passes() const {
return add_platform_specific_decoding_passes_;
}
// Advances the mock scheduler by delta_ms.
void AdvanceTimeMs(int64 delta_ms);
// Sets up the cohort in the PropertyCache provided.
void SetupCohort(PropertyCache* cache, const GoogleString& cohort_name);
protected:
virtual Hasher* NewHasher();
virtual MessageHandler* DefaultHtmlParseMessageHandler();
virtual MessageHandler* DefaultMessageHandler();
virtual UrlFetcher* DefaultUrlFetcher();
virtual UrlAsyncFetcher* DefaultAsyncUrlFetcher();
virtual UrlAsyncFetcher* DefaultDistributedUrlFetcher();
virtual FileSystem* DefaultFileSystem();
virtual Timer* DefaultTimer();
virtual void SetupCaches(ServerContext* resource_manager);
virtual UrlNamer* DefaultUrlNamer();
virtual Scheduler* CreateScheduler();
virtual void AddPlatformSpecificDecodingPasses(RewriteDriver* driver);
virtual void AddPlatformSpecificRewritePasses(RewriteDriver* driver);
virtual void ApplyPlatformSpecificConfiguration(RewriteDriver* driver);
private:
MockTimer* mock_timer_; // owned by base class timer_.
MockScheduler* mock_scheduler_; // owned by RewriteDriverFactory::scheduler_.
DelayCache* delay_cache_;
scoped_ptr<ThreadsafeCache> threadsafe_cache_;
scoped_ptr<LRUCache> lru_cache_;
UrlFetcher* proxy_url_fetcher_;
MockUrlFetcher* mock_url_fetcher_;
MockUrlFetcher* mock_distributed_fetcher_;
scoped_ptr<FakeUrlAsyncFetcher> mock_url_async_fetcher_;
scoped_ptr<FakeUrlAsyncFetcher> mock_distributed_async_fetcher_;
CountingUrlAsyncFetcher* counting_url_async_fetcher_;
CountingUrlAsyncFetcher* counting_distributed_async_fetcher_;
scoped_ptr<WaitUrlAsyncFetcher> wait_url_async_fetcher_;
scoped_ptr<MockTimeCache> mock_time_cache_;
MemFileSystem* mem_file_system_; // owned by base class file_system_.
MockHasher* mock_hasher_;
SimpleStats simple_stats_;
MockMessageHandler* mock_message_handler_;
MockMessageHandler* mock_html_message_handler_;
bool use_beacon_results_in_filters_;
bool use_test_url_namer_;
bool add_platform_specific_decoding_passes_;
std::vector<CreateFilterCallback*> filter_callback_vector_;
std::vector<CreateRewriterCallback*> rewriter_callback_vector_;
std::vector<PlatformSpecificConfigurationCallback*> platform_config_vector_;
};
} // namespace net_instaweb
#endif // NET_INSTAWEB_REWRITER_PUBLIC_TEST_REWRITE_DRIVER_FACTORY_H_
| [
"jefftk@google.com"
] | jefftk@google.com |
633e758697d97417f1f104bb547e9e638d9c31f7 | a4161b9eb3de347b3b79cbcff7c146637001b13f | /sframe/conf/TableReader.h | 0f1e27865ef0867af972a0c95e26507c0753a22b | [] | no_license | hackerlank/sframe | 86fb94d2b7424e97cc6354d1332939af53daac49 | 315c604a1cc0efd0751239be5b042aeea46a547b | refs/heads/master | 2021-01-12T06:28:22.180760 | 2016-11-22T19:18:51 | 2016-11-22T19:18:51 | null | 0 | 0 | null | null | null | null | GB18030 | C++ | false | false | 4,657 | h |
#ifndef SFRAME_TABLE_READER_H
#define SFRAME_TABLE_READER_H
#include <assert.h>
#include <string>
#include <vector>
#include <list>
#include <set>
#include <unordered_set>
#include <map>
#include <unordered_map>
#include <memory>
#include "Table.h"
#include "ConfigStringParser.h"
#include "ConfigLoader.h"
#include "ConfigMeta.h"
namespace sframe {
class TableReader
{
public:
TableReader(sframe::Table & tbl) : _tbl(&tbl), _cur_row(0) {}
~TableReader() {}
sframe::Row * GetCurrentRow()
{
if (_cur_row >= _tbl->GetRowCount())
{
return nullptr;
}
return &(*_tbl)[_cur_row];
}
void Next()
{
if (_cur_row >= _tbl->GetRowCount())
{
return;
}
_cur_row++;
}
private:
sframe::Table * _tbl;
int32_t _cur_row;
};
template<typename T_Map>
inline bool Table_FillMap(TableReader & tbl, T_Map & obj)
{
while (true)
{
if (!tbl.GetCurrentRow())
{
break;
}
typename T_Map::mapped_type v;
if (!ConfigLoader::Load(tbl, v))
{
return false;
}
typename T_Map::key_type k = GetConfigObjKey<typename T_Map::key_type>(v);
if (!obj.insert(std::make_pair(k, v)).second)
{
return false;
}
tbl.Next();
}
return true;
}
template<typename T_Array>
inline bool Table_FillArray(TableReader & tbl, T_Array & obj)
{
while (true)
{
if (!tbl.GetCurrentRow())
{
break;
}
typename T_Array::value_type v;
if (!ConfigLoader::Load(tbl, v))
{
return false;
}
obj.push_back(v);
tbl.Next();
}
return true;
}
template<typename T_Set>
inline bool Table_FillSet(TableReader & tbl, T_Set & obj)
{
while (true)
{
if (!tbl.GetCurrentRow())
{
break;
}
typename T_Set::value_type v;
if (!ConfigLoader::Load(tbl, v))
{
return false;
}
obj.insert(v);
tbl.Next();
}
return true;
}
// 填充Table到unorder_map
template<typename T_Key, typename T_Val>
struct ObjectFiller<TableReader, std::unordered_map<T_Key, T_Val>>
{
static bool Fill(TableReader & tbl, std::unordered_map<T_Key, T_Val> & obj)
{
return Table_FillMap(tbl, obj);
}
};
// 填充Table到map
template<typename T_Key, typename T_Val>
struct ObjectFiller<TableReader, std::map<T_Key, T_Val>>
{
static bool Fill(TableReader & tbl, std::map<T_Key, T_Val> & obj)
{
return Table_FillMap(tbl, obj);
}
};
// 填充Table到set
template<typename T>
struct ObjectFiller<TableReader, std::set<T>>
{
static bool Fill(TableReader & tbl, std::set<T> & obj)
{
return Table_FillSet(tbl, obj);
}
};
// 填充Table到unordered_set
template<typename T>
struct ObjectFiller<TableReader, std::unordered_set<T>>
{
static bool Fill(TableReader & tbl, std::unordered_set<T> & obj)
{
return Table_FillSet(tbl, obj);
}
};
// 填充Table到vector
template<typename T>
struct ObjectFiller<TableReader, std::vector<T>>
{
static bool Fill(TableReader & tbl, std::vector<T> & obj)
{
return Table_FillArray(tbl, obj);
}
};
// 填充Table到list
template<typename T>
struct ObjectFiller<TableReader, std::list<T>>
{
static bool Fill(TableReader & tbl, std::list<T> & obj)
{
return Table_FillArray(tbl, obj);
}
};
// 填充Table到shared_ptr
template<typename T>
struct ObjectFiller<TableReader, std::shared_ptr<T>>
{
static bool Fill(TableReader & tbl, std::shared_ptr<T> & obj)
{
obj = std::make_shared<T>();
return ConfigLoader::Load(tbl, *(obj.get()));
}
};
// 填充表格字段
template<typename T>
inline bool Tbl_FillField(TableReader & reader, const char * field_name, T & obj, const T & default_value = T())
{
std::string * str = nullptr;
sframe::Row * r = reader.GetCurrentRow();
if (!r || (str = r->GetValue(field_name)) == nullptr)
{
obj = default_value;
return false;
}
ParseCaller::Parse(*str, obj);
return true;
}
// 填充表格字段
template<typename T>
inline bool Tbl_FillIndex(TableReader & reader, int32_t field_index, T & obj, const T & default_value = T())
{
std::string * str = nullptr;
sframe::Row * r = reader.GetCurrentRow();
if (!r || (str = r->GetValue(field_index, false)) == nullptr)
{
obj = default_value;
return false;
}
ParseCaller::Parse(*str, obj);
return true;
}
}
// 对象填充辅助宏
#define TBL_FILLFIELD(name) sframe::Tbl_FillField(reader, #name, this->name);
#define TBL_FILLFIELD_DEFAULT(name, defaultval) sframe::Tbl_FillField(reader, #name, this->name, defaultval)
#define TBL_FILLINDEX(index, name) sframe::Tbl_FillIndex(reader, (int)index, obj.name);
#define TBL_FILLINDEX_DEFAULT(index, name, defaultval) sframe::Tbl_FillIndex(reader, (int)index, this->name, defaultval)
#endif
| [
"353153763@qq.com"
] | 353153763@qq.com |
b17aa2ca47c8b22ee2a57f3ad1021321fbe8124b | a84edc307452519e101093c96861fe269b965be0 | /src/net.cpp | b28627dd1a2c3bce9eb2bc1c33505f17fe663b6b | [
"MIT"
] | permissive | zebbra2014/rublebit | d339ae3063b6b1b19c49da4eccfe946657a10406 | 39bb89fa7186a4782ae1d1856d17067f243c8f89 | refs/heads/master | 2021-01-17T17:20:30.606553 | 2015-11-12T08:12:55 | 2015-11-12T08:12:55 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 56,728 | cpp | // Copyright (c) 2009-2010 Satoshi Nakamoto
// Copyright (c) 2009-2014 The RubleBit developers
// Distributed under the MIT/X11 software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include "db.h"
#include "net.h"
#include "init.h"
#include "addrman.h"
#include "ui_interface.h"
#include "script.h"
#ifdef WIN32
#include <string.h>
#endif
#ifdef USE_UPNP
#include <miniupnpc/miniwget.h>
#include <miniupnpc/miniupnpc.h>
#include <miniupnpc/upnpcommands.h>
#include <miniupnpc/upnperrors.h>
#endif
// Dump addresses to peers.dat every 15 minutes (900s)
#define DUMP_ADDRESSES_INTERVAL 900
using namespace std;
using namespace boost;
static const int MAX_OUTBOUND_CONNECTIONS = 16;
bool OpenNetworkConnection(const CAddress& addrConnect, CSemaphoreGrant *grantOutbound = NULL, const char *strDest = NULL, bool fOneShot = false);
struct LocalServiceInfo {
int nScore;
int nPort;
};
//
// Global state variables
//
bool fDiscover = true;
uint64 nLocalServices = NODE_NETWORK;
static CCriticalSection cs_mapLocalHost;
static map<CNetAddr, LocalServiceInfo> mapLocalHost;
static bool vfReachable[NET_MAX] = {};
static bool vfLimited[NET_MAX] = {};
static CNode* pnodeLocalHost = NULL;
static CNode* pnodeSync = NULL;
uint64 nLocalHostNonce = 0;
static std::vector<SOCKET> vhListenSocket;
CAddrMan addrman;
int nMaxConnections = 125;
vector<CNode*> vNodes;
CCriticalSection cs_vNodes;
map<CInv, CDataStream> mapRelay;
deque<pair<int64, CInv> > vRelayExpiration;
CCriticalSection cs_mapRelay;
limitedmap<CInv, int64> mapAlreadyAskedFor(MAX_INV_SZ);
static deque<string> vOneShots;
CCriticalSection cs_vOneShots;
set<CNetAddr> setservAddNodeAddresses;
CCriticalSection cs_setservAddNodeAddresses;
vector<std::string> vAddedNodes;
CCriticalSection cs_vAddedNodes;
static CSemaphore *semOutbound = NULL;
void AddOneShot(string strDest)
{
LOCK(cs_vOneShots);
vOneShots.push_back(strDest);
}
unsigned short GetListenPort()
{
return (unsigned short)(GetArg("-port", GetDefaultPort()));
}
void CNode::PushGetBlocks(CBlockIndex* pindexBegin, uint256 hashEnd)
{
// Filter out duplicate requests
if (pindexBegin == pindexLastGetBlocksBegin && hashEnd == hashLastGetBlocksEnd)
return;
pindexLastGetBlocksBegin = pindexBegin;
hashLastGetBlocksEnd = hashEnd;
PushMessage("getblocks", CBlockLocator(pindexBegin), hashEnd);
}
// find 'best' local address for a particular peer
bool GetLocal(CService& addr, const CNetAddr *paddrPeer)
{
if (fNoListen)
return false;
int nBestScore = -1;
int nBestReachability = -1;
{
LOCK(cs_mapLocalHost);
for (map<CNetAddr, LocalServiceInfo>::iterator it = mapLocalHost.begin(); it != mapLocalHost.end(); it++)
{
int nScore = (*it).second.nScore;
int nReachability = (*it).first.GetReachabilityFrom(paddrPeer);
if (nReachability > nBestReachability || (nReachability == nBestReachability && nScore > nBestScore))
{
addr = CService((*it).first, (*it).second.nPort);
nBestReachability = nReachability;
nBestScore = nScore;
}
}
}
return nBestScore >= 0;
}
// get best local address for a particular peer as a CAddress
CAddress GetLocalAddress(const CNetAddr *paddrPeer)
{
CAddress ret(CService("0.0.0.0",0),0);
CService addr;
if (GetLocal(addr, paddrPeer))
{
ret = CAddress(addr);
ret.nServices = nLocalServices;
ret.nTime = GetAdjustedTime();
}
return ret;
}
bool RecvLine(SOCKET hSocket, string& strLine)
{
strLine = "";
loop
{
char c;
int nBytes = recv(hSocket, &c, 1, 0);
if (nBytes > 0)
{
if (c == '\n')
continue;
if (c == '\r')
return true;
strLine += c;
if (strLine.size() >= 9000)
return true;
}
else if (nBytes <= 0)
{
boost::this_thread::interruption_point();
if (nBytes < 0)
{
int nErr = WSAGetLastError();
if (nErr == WSAEMSGSIZE)
continue;
if (nErr == WSAEWOULDBLOCK || nErr == WSAEINTR || nErr == WSAEINPROGRESS)
{
MilliSleep(10);
continue;
}
}
if (!strLine.empty())
return true;
if (nBytes == 0)
{
// socket closed
printf("socket closed\n");
return false;
}
else
{
// socket error
int nErr = WSAGetLastError();
printf("recv failed: %d\n", nErr);
return false;
}
}
}
}
// used when scores of local addresses may have changed
// pushes better local address to peers
void static AdvertizeLocal()
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
{
if (pnode->fSuccessfullyConnected)
{
CAddress addrLocal = GetLocalAddress(&pnode->addr);
if (addrLocal.IsRoutable() && (CService)addrLocal != (CService)pnode->addrLocal)
{
pnode->PushAddress(addrLocal);
pnode->addrLocal = addrLocal;
}
}
}
}
void SetReachable(enum Network net, bool fFlag)
{
LOCK(cs_mapLocalHost);
vfReachable[net] = fFlag;
if (net == NET_IPV6 && fFlag)
vfReachable[NET_IPV4] = true;
}
// learn a new local address
bool AddLocal(const CService& addr, int nScore)
{
if (!addr.IsRoutable())
return false;
if (!fDiscover && nScore < LOCAL_MANUAL)
return false;
if (IsLimited(addr))
return false;
printf("AddLocal(%s,%i)\n", addr.ToString().c_str(), nScore);
{
LOCK(cs_mapLocalHost);
bool fAlready = mapLocalHost.count(addr) > 0;
LocalServiceInfo &info = mapLocalHost[addr];
if (!fAlready || nScore >= info.nScore) {
info.nScore = nScore + (fAlready ? 1 : 0);
info.nPort = addr.GetPort();
}
SetReachable(addr.GetNetwork());
}
AdvertizeLocal();
return true;
}
bool AddLocal(const CNetAddr &addr, int nScore)
{
return AddLocal(CService(addr, GetListenPort()), nScore);
}
/** Make a particular network entirely off-limits (no automatic connects to it) */
void SetLimited(enum Network net, bool fLimited)
{
if (net == NET_UNROUTABLE)
return;
LOCK(cs_mapLocalHost);
vfLimited[net] = fLimited;
}
bool IsLimited(enum Network net)
{
LOCK(cs_mapLocalHost);
return vfLimited[net];
}
bool IsLimited(const CNetAddr &addr)
{
return IsLimited(addr.GetNetwork());
}
/** vote for a local address */
bool SeenLocal(const CService& addr)
{
{
LOCK(cs_mapLocalHost);
if (mapLocalHost.count(addr) == 0)
return false;
mapLocalHost[addr].nScore++;
}
AdvertizeLocal();
return true;
}
/** check whether a given address is potentially local */
bool IsLocal(const CService& addr)
{
LOCK(cs_mapLocalHost);
return mapLocalHost.count(addr) > 0;
}
/** check whether a given address is in a network we can probably connect to */
bool IsReachable(const CNetAddr& addr)
{
LOCK(cs_mapLocalHost);
enum Network net = addr.GetNetwork();
return vfReachable[net] && !vfLimited[net];
}
bool GetMyExternalIP2(const CService& addrConnect, const char* pszGet, const char* pszKeyword, CNetAddr& ipRet)
{
SOCKET hSocket;
if (!ConnectSocket(addrConnect, hSocket))
return error("GetMyExternalIP() : connection to %s failed", addrConnect.ToString().c_str());
send(hSocket, pszGet, strlen(pszGet), MSG_NOSIGNAL);
string strLine;
while (RecvLine(hSocket, strLine))
{
if (strLine.empty()) // HTTP response is separated from headers by blank line
{
loop
{
if (!RecvLine(hSocket, strLine))
{
closesocket(hSocket);
return false;
}
if (pszKeyword == NULL)
break;
if (strLine.find(pszKeyword) != string::npos)
{
strLine = strLine.substr(strLine.find(pszKeyword) + strlen(pszKeyword));
break;
}
}
closesocket(hSocket);
if (strLine.find("<") != string::npos)
strLine = strLine.substr(0, strLine.find("<"));
strLine = strLine.substr(strspn(strLine.c_str(), " \t\n\r"));
while (strLine.size() > 0 && isspace(strLine[strLine.size()-1]))
strLine.resize(strLine.size()-1);
CService addr(strLine,0,true);
printf("GetMyExternalIP() received [%s] %s\n", strLine.c_str(), addr.ToString().c_str());
if (!addr.IsValid() || !addr.IsRoutable())
return false;
ipRet.SetIP(addr);
return true;
}
}
closesocket(hSocket);
return error("GetMyExternalIP() : connection closed");
}
bool GetMyExternalIP(CNetAddr& ipRet)
{
CService addrConnect;
const char* pszGet;
const char* pszKeyword;
for (int nLookup = 0; nLookup <= 1; nLookup++)
for (int nHost = 1; nHost <= 1; nHost++)
{
// We should be phasing out our use of sites like these. If we need
// replacements, we should ask for volunteers to put this simple
// php file on their web server that prints the client IP:
// <?php echo $_SERVER["REMOTE_ADDR"]; ?>
if (nHost == 1)
{
addrConnect = CService("91.198.22.70", 80); // checkip.dyndns.org
if (nLookup == 1)
{
CService addrIP("checkip.dyndns.org", 80, true);
if (addrIP.IsValid())
addrConnect = addrIP;
}
pszGet = "GET / HTTP/1.1\r\n"
"Host: checkip.dyndns.org\r\n"
"User-Agent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1)\r\n"
"Connection: close\r\n"
"\r\n";
pszKeyword = "Address:";
}
if (GetMyExternalIP2(addrConnect, pszGet, pszKeyword, ipRet))
return true;
}
return false;
}
void ThreadGetMyExternalIP(void* parg)
{
// Make this thread recognisable as the external IP detection thread
RenameThread("rublebit-ext-ip");
CNetAddr addrLocalHost;
if (GetMyExternalIP(addrLocalHost))
{
printf("GetMyExternalIP() returned %s\n", addrLocalHost.ToStringIP().c_str());
AddLocal(addrLocalHost, LOCAL_HTTP);
}
}
void AddressCurrentlyConnected(const CService& addr)
{
addrman.Connected(addr);
}
CNode* FindNode(const CNetAddr& ip)
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
if ((CNetAddr)pnode->addr == ip)
return (pnode);
return NULL;
}
CNode* FindNode(std::string addrName)
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
if (pnode->addrName == addrName)
return (pnode);
return NULL;
}
CNode* FindNode(const CService& addr)
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
if ((CService)pnode->addr == addr)
return (pnode);
return NULL;
}
CNode* ConnectNode(CAddress addrConnect, const char *pszDest)
{
if (pszDest == NULL) {
if (IsLocal(addrConnect))
return NULL;
// Look for an existing connection
CNode* pnode = FindNode((CService)addrConnect);
if (pnode)
{
pnode->AddRef();
return pnode;
}
}
/// debug print
printf("trying connection %s lastseen=%.1fhrs\n",
pszDest ? pszDest : addrConnect.ToString().c_str(),
pszDest ? 0 : (double)(GetAdjustedTime() - addrConnect.nTime)/3600.0);
// Connect
SOCKET hSocket;
if (pszDest ? ConnectSocketByName(addrConnect, hSocket, pszDest, GetDefaultPort()) : ConnectSocket(addrConnect, hSocket))
{
addrman.Attempt(addrConnect);
/// debug print
printf("connected %s\n", pszDest ? pszDest : addrConnect.ToString().c_str());
// Set to non-blocking
#ifdef WIN32
u_long nOne = 1;
if (ioctlsocket(hSocket, FIONBIO, &nOne) == SOCKET_ERROR)
printf("ConnectSocket() : ioctlsocket non-blocking setting failed, error %d\n", WSAGetLastError());
#else
if (fcntl(hSocket, F_SETFL, O_NONBLOCK) == SOCKET_ERROR)
printf("ConnectSocket() : fcntl non-blocking setting failed, error %d\n", errno);
#endif
// Add node
CNode* pnode = new CNode(hSocket, addrConnect, pszDest ? pszDest : "", false);
pnode->AddRef();
{
LOCK(cs_vNodes);
vNodes.push_back(pnode);
}
pnode->nTimeConnected = GetTime();
return pnode;
}
else
{
return NULL;
}
}
void CNode::CloseSocketDisconnect()
{
fDisconnect = true;
if (hSocket != INVALID_SOCKET)
{
printf("disconnecting node %s\n", addrName.c_str());
closesocket(hSocket);
hSocket = INVALID_SOCKET;
}
// in case this fails, we'll empty the recv buffer when the CNode is deleted
TRY_LOCK(cs_vRecvMsg, lockRecv);
if (lockRecv)
vRecvMsg.clear();
// if this was the sync node, we'll need a new one
if (this == pnodeSync)
pnodeSync = NULL;
}
void CNode::Cleanup()
{
}
void CNode::PushVersion()
{
/// when NTP implemented, change to just nTime = GetAdjustedTime()
int64 nTime = (fInbound ? GetAdjustedTime() : GetTime());
CAddress addrYou = (addr.IsRoutable() && !IsProxy(addr) ? addr : CAddress(CService("0.0.0.0",0)));
CAddress addrMe = GetLocalAddress(&addr);
RAND_bytes((unsigned char*)&nLocalHostNonce, sizeof(nLocalHostNonce));
printf("send version message: version %d, blocks=%d, us=%s, them=%s, peer=%s\n", PROTOCOL_VERSION, nBestHeight, addrMe.ToString().c_str(), addrYou.ToString().c_str(), addr.ToString().c_str());
PushMessage("version", PROTOCOL_VERSION, nLocalServices, nTime, addrYou, addrMe,
nLocalHostNonce, FormatSubVersion(CLIENT_NAME, CLIENT_VERSION, std::vector<string>()), nBestHeight);
}
std::map<CNetAddr, int64> CNode::setBanned;
CCriticalSection CNode::cs_setBanned;
void CNode::ClearBanned()
{
setBanned.clear();
}
bool CNode::IsBanned(CNetAddr ip)
{
bool fResult = false;
{
LOCK(cs_setBanned);
std::map<CNetAddr, int64>::iterator i = setBanned.find(ip);
if (i != setBanned.end())
{
int64 t = (*i).second;
if (GetTime() < t)
fResult = true;
}
}
return fResult;
}
bool CNode::Misbehaving(int howmuch)
{
if (addr.IsLocal())
{
printf("Warning: Local node %s misbehaving (delta: %d)!\n", addrName.c_str(), howmuch);
return false;
}
nMisbehavior += howmuch;
if (nMisbehavior >= GetArg("-banscore", 100))
{
int64 banTime = GetTime()+GetArg("-bantime", 60*60*24); // Default 24-hour ban
printf("Misbehaving: %s (%d -> %d) DISCONNECTING\n", addr.ToString().c_str(), nMisbehavior-howmuch, nMisbehavior);
{
LOCK(cs_setBanned);
if (setBanned[addr] < banTime)
setBanned[addr] = banTime;
}
CloseSocketDisconnect();
return true;
} else
printf("Misbehaving: %s (%d -> %d)\n", addr.ToString().c_str(), nMisbehavior-howmuch, nMisbehavior);
return false;
}
#undef X
#define X(name) stats.name = name
void CNode::copyStats(CNodeStats &stats)
{
X(nServices);
X(nLastSend);
X(nLastRecv);
X(nTimeConnected);
X(addrName);
X(nVersion);
X(cleanSubVer);
X(fInbound);
X(nStartingHeight);
X(nMisbehavior);
X(nSendBytes);
X(nRecvBytes);
X(nBlocksRequested);
stats.fSyncNode = (this == pnodeSync);
}
#undef X
// requires LOCK(cs_vRecvMsg)
bool CNode::ReceiveMsgBytes(const char *pch, unsigned int nBytes)
{
while (nBytes > 0) {
// get current incomplete message, or create a new one
if (vRecvMsg.empty() ||
vRecvMsg.back().complete())
vRecvMsg.push_back(CNetMessage(SER_NETWORK, nRecvVersion));
CNetMessage& msg = vRecvMsg.back();
// absorb network data
int handled;
if (!msg.in_data)
handled = msg.readHeader(pch, nBytes);
else
handled = msg.readData(pch, nBytes);
if (handled < 0)
return false;
pch += handled;
nBytes -= handled;
}
return true;
}
int CNetMessage::readHeader(const char *pch, unsigned int nBytes)
{
// copy data to temporary parsing buffer
unsigned int nRemaining = 24 - nHdrPos;
unsigned int nCopy = std::min(nRemaining, nBytes);
memcpy(&hdrbuf[nHdrPos], pch, nCopy);
nHdrPos += nCopy;
// if header incomplete, exit
if (nHdrPos < 24)
return nCopy;
// deserialize to CMessageHeader
try {
hdrbuf >> hdr;
}
catch (std::exception &e) {
return -1;
}
// reject messages larger than MAX_SIZE
if (hdr.nMessageSize > MAX_SIZE)
return -1;
// switch state to reading message data
in_data = true;
vRecv.resize(hdr.nMessageSize);
return nCopy;
}
int CNetMessage::readData(const char *pch, unsigned int nBytes)
{
unsigned int nRemaining = hdr.nMessageSize - nDataPos;
unsigned int nCopy = std::min(nRemaining, nBytes);
memcpy(&vRecv[nDataPos], pch, nCopy);
nDataPos += nCopy;
return nCopy;
}
// requires LOCK(cs_vSend)
void SocketSendData(CNode *pnode)
{
std::deque<CSerializeData>::iterator it = pnode->vSendMsg.begin();
while (it != pnode->vSendMsg.end()) {
const CSerializeData &data = *it;
assert(data.size() > pnode->nSendOffset);
int nBytes = send(pnode->hSocket, &data[pnode->nSendOffset], data.size() - pnode->nSendOffset, MSG_NOSIGNAL | MSG_DONTWAIT);
if (nBytes > 0) {
pnode->nLastSend = GetTime();
pnode->nSendBytes += nBytes;
pnode->nSendOffset += nBytes;
if (pnode->nSendOffset == data.size()) {
pnode->nSendOffset = 0;
pnode->nSendSize -= data.size();
it++;
} else {
// could not send full message; stop sending more
break;
}
} else {
if (nBytes < 0) {
// error
int nErr = WSAGetLastError();
if (nErr != WSAEWOULDBLOCK && nErr != WSAEMSGSIZE && nErr != WSAEINTR && nErr != WSAEINPROGRESS)
{
printf("socket send error %d\n", nErr);
pnode->CloseSocketDisconnect();
}
}
// couldn't send anything at all
break;
}
}
if (it == pnode->vSendMsg.end()) {
assert(pnode->nSendOffset == 0);
assert(pnode->nSendSize == 0);
}
pnode->vSendMsg.erase(pnode->vSendMsg.begin(), it);
}
static list<CNode*> vNodesDisconnected;
void ThreadSocketHandler()
{
unsigned int nPrevNodeCount = 0;
loop
{
//
// Disconnect nodes
//
{
LOCK(cs_vNodes);
// Disconnect unused nodes
vector<CNode*> vNodesCopy = vNodes;
BOOST_FOREACH(CNode* pnode, vNodesCopy)
{
if (pnode->fDisconnect ||
(pnode->GetRefCount() <= 0 && pnode->vRecvMsg.empty() && pnode->nSendSize == 0 && pnode->ssSend.empty()))
{
// remove from vNodes
vNodes.erase(remove(vNodes.begin(), vNodes.end(), pnode), vNodes.end());
// release outbound grant (if any)
pnode->grantOutbound.Release();
// close socket and cleanup
pnode->CloseSocketDisconnect();
pnode->Cleanup();
// hold in disconnected pool until all refs are released
if (pnode->fNetworkNode || pnode->fInbound)
pnode->Release();
vNodesDisconnected.push_back(pnode);
}
}
// Delete disconnected nodes
list<CNode*> vNodesDisconnectedCopy = vNodesDisconnected;
BOOST_FOREACH(CNode* pnode, vNodesDisconnectedCopy)
{
// wait until threads are done using it
if (pnode->GetRefCount() <= 0)
{
bool fDelete = false;
{
TRY_LOCK(pnode->cs_vSend, lockSend);
if (lockSend)
{
TRY_LOCK(pnode->cs_vRecvMsg, lockRecv);
if (lockRecv)
{
TRY_LOCK(pnode->cs_inventory, lockInv);
if (lockInv)
fDelete = true;
}
}
}
if (fDelete)
{
vNodesDisconnected.remove(pnode);
delete pnode;
}
}
}
}
if (vNodes.size() != nPrevNodeCount)
{
nPrevNodeCount = vNodes.size();
uiInterface.NotifyNumConnectionsChanged(vNodes.size());
}
//
// Find which sockets have data to receive
//
struct timeval timeout;
timeout.tv_sec = 0;
timeout.tv_usec = 50000; // frequency to poll pnode->vSend
fd_set fdsetRecv;
fd_set fdsetSend;
fd_set fdsetError;
FD_ZERO(&fdsetRecv);
FD_ZERO(&fdsetSend);
FD_ZERO(&fdsetError);
SOCKET hSocketMax = 0;
bool have_fds = false;
BOOST_FOREACH(SOCKET hListenSocket, vhListenSocket) {
FD_SET(hListenSocket, &fdsetRecv);
hSocketMax = max(hSocketMax, hListenSocket);
have_fds = true;
}
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
{
if (pnode->hSocket == INVALID_SOCKET)
continue;
FD_SET(pnode->hSocket, &fdsetError);
hSocketMax = max(hSocketMax, pnode->hSocket);
have_fds = true;
// Implement the following logic:
// * If there is data to send, select() for sending data. As this only
// happens when optimistic write failed, we choose to first drain the
// write buffer in this case before receiving more. This avoids
// needlessly queueing received data, if the remote peer is not themselves
// receiving data. This means properly utilizing TCP flow control signalling.
// * Otherwise, if there is no (complete) message in the receive buffer,
// or there is space left in the buffer, select() for receiving data.
// * (if neither of the above applies, there is certainly one message
// in the receiver buffer ready to be processed).
// Together, that means that at least one of the following is always possible,
// so we don't deadlock:
// * We send some data.
// * We wait for data to be received (and disconnect after timeout).
// * We process a message in the buffer (message handler thread).
{
TRY_LOCK(pnode->cs_vSend, lockSend);
if (lockSend && !pnode->vSendMsg.empty()) {
FD_SET(pnode->hSocket, &fdsetSend);
continue;
}
}
{
TRY_LOCK(pnode->cs_vRecvMsg, lockRecv);
if (lockRecv && (
pnode->vRecvMsg.empty() || !pnode->vRecvMsg.front().complete() ||
pnode->GetTotalRecvSize() <= ReceiveFloodSize()))
FD_SET(pnode->hSocket, &fdsetRecv);
}
}
}
int nSelect = select(have_fds ? hSocketMax + 1 : 0,
&fdsetRecv, &fdsetSend, &fdsetError, &timeout);
boost::this_thread::interruption_point();
if (nSelect == SOCKET_ERROR)
{
if (have_fds)
{
int nErr = WSAGetLastError();
printf("socket select error %d\n", nErr);
for (unsigned int i = 0; i <= hSocketMax; i++)
FD_SET(i, &fdsetRecv);
}
FD_ZERO(&fdsetSend);
FD_ZERO(&fdsetError);
MilliSleep(timeout.tv_usec/1000);
}
//
// Accept new connections
//
BOOST_FOREACH(SOCKET hListenSocket, vhListenSocket)
if (hListenSocket != INVALID_SOCKET && FD_ISSET(hListenSocket, &fdsetRecv))
{
#ifdef USE_IPV6
struct sockaddr_storage sockaddr;
#else
struct sockaddr sockaddr;
#endif
socklen_t len = sizeof(sockaddr);
SOCKET hSocket = accept(hListenSocket, (struct sockaddr*)&sockaddr, &len);
CAddress addr;
int nInbound = 0;
if (hSocket != INVALID_SOCKET)
if (!addr.SetSockAddr((const struct sockaddr*)&sockaddr))
printf("Warning: Unknown socket family\n");
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
if (pnode->fInbound)
nInbound++;
}
if (hSocket == INVALID_SOCKET)
{
int nErr = WSAGetLastError();
if (nErr != WSAEWOULDBLOCK)
printf("socket error accept failed: %d\n", nErr);
}
else if (nInbound >= nMaxConnections - MAX_OUTBOUND_CONNECTIONS)
{
{
LOCK(cs_setservAddNodeAddresses);
if (!setservAddNodeAddresses.count(addr))
closesocket(hSocket);
}
}
else if (CNode::IsBanned(addr))
{
printf("connection from %s dropped (banned)\n", addr.ToString().c_str());
closesocket(hSocket);
}
else
{
printf("accepted connection %s\n", addr.ToString().c_str());
CNode* pnode = new CNode(hSocket, addr, "", true);
pnode->AddRef();
{
LOCK(cs_vNodes);
vNodes.push_back(pnode);
}
}
}
//
// Service each socket
//
vector<CNode*> vNodesCopy;
{
LOCK(cs_vNodes);
vNodesCopy = vNodes;
BOOST_FOREACH(CNode* pnode, vNodesCopy)
pnode->AddRef();
}
BOOST_FOREACH(CNode* pnode, vNodesCopy)
{
boost::this_thread::interruption_point();
//
// Receive
//
if (pnode->hSocket == INVALID_SOCKET)
continue;
if (FD_ISSET(pnode->hSocket, &fdsetRecv) || FD_ISSET(pnode->hSocket, &fdsetError))
{
TRY_LOCK(pnode->cs_vRecvMsg, lockRecv);
if (lockRecv)
{
{
// typical socket buffer is 8K-64K
char pchBuf[0x10000];
int nBytes = recv(pnode->hSocket, pchBuf, sizeof(pchBuf), MSG_DONTWAIT);
if (nBytes > 0)
{
if (!pnode->ReceiveMsgBytes(pchBuf, nBytes))
pnode->CloseSocketDisconnect();
pnode->nLastRecv = GetTime();
pnode->nRecvBytes += nBytes;
}
else if (nBytes == 0)
{
// socket closed gracefully
if (!pnode->fDisconnect)
printf("socket closed\n");
pnode->CloseSocketDisconnect();
}
else if (nBytes < 0)
{
// error
int nErr = WSAGetLastError();
if (nErr != WSAEWOULDBLOCK && nErr != WSAEMSGSIZE && nErr != WSAEINTR && nErr != WSAEINPROGRESS)
{
if (!pnode->fDisconnect)
printf("socket recv error %d\n", nErr);
pnode->CloseSocketDisconnect();
}
}
}
}
}
//
// Send
//
if (pnode->hSocket == INVALID_SOCKET)
continue;
if (FD_ISSET(pnode->hSocket, &fdsetSend))
{
TRY_LOCK(pnode->cs_vSend, lockSend);
if (lockSend)
SocketSendData(pnode);
}
//
// Inactivity checking
//
if (pnode->vSendMsg.empty())
pnode->nLastSendEmpty = GetTime();
if (GetTime() - pnode->nTimeConnected > 60)
{
if (pnode->nLastRecv == 0 || pnode->nLastSend == 0)
{
printf("socket no message in first 60 seconds, %d %d\n", pnode->nLastRecv != 0, pnode->nLastSend != 0);
pnode->fDisconnect = true;
}
else if (GetTime() - pnode->nLastSend > 90*60 && GetTime() - pnode->nLastSendEmpty > 90*60)
{
printf("socket not sending\n");
pnode->fDisconnect = true;
}
else if (GetTime() - pnode->nLastRecv > 90*60)
{
printf("socket inactivity timeout\n");
pnode->fDisconnect = true;
}
}
}
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodesCopy)
pnode->Release();
}
MilliSleep(10);
}
}
#ifdef USE_UPNP
void ThreadMapPort()
{
std::string port = strprintf("%u", GetListenPort());
const char * multicastif = 0;
const char * minissdpdpath = 0;
struct UPNPDev * devlist = 0;
char lanaddr[64];
#ifndef UPNPDISCOVER_SUCCESS
/* miniupnpc 1.5 */
devlist = upnpDiscover(2000, multicastif, minissdpdpath, 0);
#else
/* miniupnpc 1.6 */
int error = 0;
devlist = upnpDiscover(2000, multicastif, minissdpdpath, 0, 0, &error);
#endif
struct UPNPUrls urls;
struct IGDdatas data;
int r;
r = UPNP_GetValidIGD(devlist, &urls, &data, lanaddr, sizeof(lanaddr));
if (r == 1)
{
if (fDiscover) {
char externalIPAddress[40];
r = UPNP_GetExternalIPAddress(urls.controlURL, data.first.servicetype, externalIPAddress);
if(r != UPNPCOMMAND_SUCCESS)
printf("UPnP: GetExternalIPAddress() returned %d\n", r);
else
{
if(externalIPAddress[0])
{
printf("UPnP: ExternalIPAddress = %s\n", externalIPAddress);
AddLocal(CNetAddr(externalIPAddress), LOCAL_UPNP);
}
else
printf("UPnP: GetExternalIPAddress failed.\n");
}
}
string strDesc = "RubleBit " + FormatFullVersion();
try {
loop {
#ifndef UPNPDISCOVER_SUCCESS
/* miniupnpc 1.5 */
r = UPNP_AddPortMapping(urls.controlURL, data.first.servicetype,
port.c_str(), port.c_str(), lanaddr, strDesc.c_str(), "TCP", 0);
#else
/* miniupnpc 1.6 */
r = UPNP_AddPortMapping(urls.controlURL, data.first.servicetype,
port.c_str(), port.c_str(), lanaddr, strDesc.c_str(), "TCP", 0, "0");
#endif
if(r!=UPNPCOMMAND_SUCCESS)
printf("AddPortMapping(%s, %s, %s) failed with code %d (%s)\n",
port.c_str(), port.c_str(), lanaddr, r, strupnperror(r));
else
printf("UPnP Port Mapping successful.\n");;
MilliSleep(20*60*1000); // Refresh every 20 minutes
}
}
catch (boost::thread_interrupted)
{
r = UPNP_DeletePortMapping(urls.controlURL, data.first.servicetype, port.c_str(), "TCP", 0);
printf("UPNP_DeletePortMapping() returned : %d\n", r);
freeUPNPDevlist(devlist); devlist = 0;
FreeUPNPUrls(&urls);
throw;
}
} else {
printf("No valid UPnP IGDs found\n");
freeUPNPDevlist(devlist); devlist = 0;
if (r != 0)
FreeUPNPUrls(&urls);
}
}
void MapPort(bool fUseUPnP)
{
static boost::thread* upnp_thread = NULL;
if (fUseUPnP)
{
if (upnp_thread) {
upnp_thread->interrupt();
upnp_thread->join();
delete upnp_thread;
}
upnp_thread = new boost::thread(boost::bind(&TraceThread<boost::function<void()> >, "upnp", &ThreadMapPort));
}
else if (upnp_thread) {
upnp_thread->interrupt();
upnp_thread->join();
delete upnp_thread;
upnp_thread = NULL;
}
}
#else
void MapPort(bool)
{
// Intentionally left blank.
}
#endif
// DNS seeds
// Each pair gives a source name and a seed name.
// The first name is used as information source for addrman.
// The second name should resolve to a list of seed addresses.
static const char *strMainNetDNSSeed[][2] = {
{"node.rublebit.info", "128.199.38.11"},
// {"seed5.rublebit.info", "128.199.38.11"},
{NULL, NULL}
};
static const char *strTestNetDNSSeed[][2] = {
{"xurious.com", "testnet-seed.ltc.xurious.com"},
{"wemine-testnet.com", "dnsseed.wemine-testnet.com"},
{NULL, NULL}
};
void ThreadDNSAddressSeed()
{
static const char *(*strDNSSeed)[2] = fTestNet ? strTestNetDNSSeed : strMainNetDNSSeed;
int found = 0;
printf("Loading addresses from DNS seeds (could take a while)\n");
for (unsigned int seed_idx = 0; strDNSSeed[seed_idx][0] != NULL; seed_idx++) {
if (HaveNameProxy()) {
AddOneShot(strDNSSeed[seed_idx][1]);
} else {
vector<CNetAddr> vaddr;
vector<CAddress> vAdd;
if (LookupHost(strDNSSeed[seed_idx][1], vaddr))
{
BOOST_FOREACH(CNetAddr& ip, vaddr)
{
int nOneDay = 24*3600;
CAddress addr = CAddress(CService(ip, GetDefaultPort()));
addr.nTime = GetTime() - 3*nOneDay - GetRand(4*nOneDay); // use a random age between 3 and 7 days old
vAdd.push_back(addr);
found++;
}
}
addrman.Add(vAdd, CNetAddr(strDNSSeed[seed_idx][0], true));
}
}
printf("%d addresses found from DNS seeds\n", found);
}
unsigned int pnSeed[] =
{
// 0x4423ff60, 0xfa57ec6d, 0xcde2fb65, 0x11093257, 0x4748cd5b, 0x720c03dd, 0x8c7b0905, 0xba8b2e48
// 0xBCA62DAE, 0xBCA65C80, 0x5F55370D, 0xB23EC3A1, 0x80C7260B, 0x34590359
};
void DumpAddresses()
{
int64 nStart = GetTimeMillis();
CAddrDB adb;
adb.Write(addrman);
printf("Flushed %d addresses to peers.dat %"PRI64d"ms\n",
addrman.size(), GetTimeMillis() - nStart);
}
void static ProcessOneShot()
{
string strDest;
{
LOCK(cs_vOneShots);
if (vOneShots.empty())
return;
strDest = vOneShots.front();
vOneShots.pop_front();
}
CAddress addr;
CSemaphoreGrant grant(*semOutbound, true);
if (grant) {
if (!OpenNetworkConnection(addr, &grant, strDest.c_str(), true))
AddOneShot(strDest);
}
}
void ThreadOpenConnections()
{
// Connect to specific addresses
if (mapArgs.count("-connect") && mapMultiArgs["-connect"].size() > 0)
{
for (int64 nLoop = 0;; nLoop++)
{
ProcessOneShot();
BOOST_FOREACH(string strAddr, mapMultiArgs["-connect"])
{
CAddress addr;
OpenNetworkConnection(addr, NULL, strAddr.c_str());
for (int i = 0; i < 10 && i < nLoop; i++)
{
MilliSleep(500);
}
}
MilliSleep(500);
}
}
// Initiate network connections
int64 nStart = GetTime();
loop
{
ProcessOneShot();
MilliSleep(500);
CSemaphoreGrant grant(*semOutbound);
boost::this_thread::interruption_point();
// Add seed nodes if IRC isn't working
if (addrman.size()==0 && (GetTime() - nStart > 60) && !fTestNet)
{
std::vector<CAddress> vAdd;
for (unsigned int i = 0; i < ARRAYLEN(pnSeed); i++)
{
// It'll only connect to one or two seed nodes because once it connects,
// it'll get a pile of addresses with newer timestamps.
// Seed nodes are given a random 'last seen time' of between one and two
// weeks ago.
const int64 nOneWeek = 7*24*60*60;
struct in_addr ip;
memcpy(&ip, &pnSeed[i], sizeof(ip));
CAddress addr(CService(ip, GetDefaultPort()));
addr.nTime = GetTime()-GetRand(nOneWeek)-nOneWeek;
vAdd.push_back(addr);
}
addrman.Add(vAdd, CNetAddr("127.0.0.1"));
}
//
// Choose an address to connect to based on most recently seen
//
CAddress addrConnect;
// Only connect out to one peer per network group (/16 for IPv4).
// Do this here so we don't have to critsect vNodes inside mapAddresses critsect.
int nOutbound = 0;
set<vector<unsigned char> > setConnected;
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes) {
if (!pnode->fInbound) {
setConnected.insert(pnode->addr.GetGroup());
nOutbound++;
}
}
}
int64 nANow = GetAdjustedTime();
int nTries = 0;
loop
{
// use an nUnkBias between 10 (no outgoing connections) and 90 (8 outgoing connections)
CAddress addr = addrman.Select(10 + min(nOutbound,8)*10);
// if we selected an invalid address, restart
if (!addr.IsValid() || setConnected.count(addr.GetGroup()) || IsLocal(addr))
break;
// If we didn't find an appropriate destination after trying 100 addresses fetched from addrman,
// stop this loop, and let the outer loop run again (which sleeps, adds seed nodes, recalculates
// already-connected network ranges, ...) before trying new addrman addresses.
nTries++;
if (nTries > 100)
break;
if (IsLimited(addr))
continue;
// only consider very recently tried nodes after 30 failed attempts
if (nANow - addr.nLastTry < 600 && nTries < 30)
continue;
// do not allow non-default ports, unless after 50 invalid addresses selected already
if (addr.GetPort() != GetDefaultPort() && nTries < 50)
continue;
addrConnect = addr;
break;
}
if (addrConnect.IsValid())
OpenNetworkConnection(addrConnect, &grant);
}
}
void ThreadOpenAddedConnections()
{
{
LOCK(cs_vAddedNodes);
vAddedNodes = mapMultiArgs["-addnode"];
}
if (HaveNameProxy()) {
while(true) {
list<string> lAddresses(0);
{
LOCK(cs_vAddedNodes);
BOOST_FOREACH(string& strAddNode, vAddedNodes)
lAddresses.push_back(strAddNode);
}
BOOST_FOREACH(string& strAddNode, lAddresses) {
CAddress addr;
CSemaphoreGrant grant(*semOutbound);
OpenNetworkConnection(addr, &grant, strAddNode.c_str());
MilliSleep(500);
}
MilliSleep(120000); // Retry every 2 minutes
}
}
for (unsigned int i = 0; true; i++)
{
list<string> lAddresses(0);
{
LOCK(cs_vAddedNodes);
BOOST_FOREACH(string& strAddNode, vAddedNodes)
lAddresses.push_back(strAddNode);
}
list<vector<CService> > lservAddressesToAdd(0);
BOOST_FOREACH(string& strAddNode, lAddresses)
{
vector<CService> vservNode(0);
if(Lookup(strAddNode.c_str(), vservNode, GetDefaultPort(), fNameLookup, 0))
{
lservAddressesToAdd.push_back(vservNode);
{
LOCK(cs_setservAddNodeAddresses);
BOOST_FOREACH(CService& serv, vservNode)
setservAddNodeAddresses.insert(serv);
}
}
}
// Attempt to connect to each IP for each addnode entry until at least one is successful per addnode entry
// (keeping in mind that addnode entries can have many IPs if fNameLookup)
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
for (list<vector<CService> >::iterator it = lservAddressesToAdd.begin(); it != lservAddressesToAdd.end(); it++)
BOOST_FOREACH(CService& addrNode, *(it))
if (pnode->addr == addrNode)
{
it = lservAddressesToAdd.erase(it);
it--;
break;
}
}
BOOST_FOREACH(vector<CService>& vserv, lservAddressesToAdd)
{
CSemaphoreGrant grant(*semOutbound);
OpenNetworkConnection(CAddress(vserv[i % vserv.size()]), &grant);
MilliSleep(500);
}
MilliSleep(120000); // Retry every 2 minutes
}
}
// if successful, this moves the passed grant to the constructed node
bool OpenNetworkConnection(const CAddress& addrConnect, CSemaphoreGrant *grantOutbound, const char *strDest, bool fOneShot)
{
//
// Initiate outbound network connection
//
boost::this_thread::interruption_point();
if (!strDest)
if (IsLocal(addrConnect) ||
FindNode((CNetAddr)addrConnect) || CNode::IsBanned(addrConnect) ||
FindNode(addrConnect.ToStringIPPort().c_str()))
return false;
if (strDest && FindNode(strDest))
return false;
CNode* pnode = ConnectNode(addrConnect, strDest);
boost::this_thread::interruption_point();
if (!pnode)
return false;
if (grantOutbound)
grantOutbound->MoveTo(pnode->grantOutbound);
pnode->fNetworkNode = true;
if (fOneShot)
pnode->fOneShot = true;
return true;
}
// for now, use a very simple selection metric: the node from which we received
// most recently
double static NodeSyncScore(const CNode *pnode) {
return -pnode->nLastRecv;
}
void static StartSync(const vector<CNode*> &vNodes) {
CNode *pnodeNewSync = NULL;
double dBestScore = 0;
// fImporting and fReindex are accessed out of cs_main here, but only
// as an optimization - they are checked again in SendMessages.
if (fImporting || fReindex)
return;
// Iterate over all nodes
BOOST_FOREACH(CNode* pnode, vNodes) {
// check preconditions for allowing a sync
if (!pnode->fClient && !pnode->fOneShot &&
!pnode->fDisconnect && pnode->fSuccessfullyConnected &&
(pnode->nStartingHeight > (nBestHeight - 144)) &&
(pnode->nVersion < NOBLKS_VERSION_START || pnode->nVersion >= NOBLKS_VERSION_END)) {
// if ok, compare node's score with the best so far
double dScore = NodeSyncScore(pnode);
if (pnodeNewSync == NULL || dScore > dBestScore) {
pnodeNewSync = pnode;
dBestScore = dScore;
}
}
}
// if a new sync candidate was found, start sync!
if (pnodeNewSync) {
pnodeNewSync->fStartSync = true;
pnodeSync = pnodeNewSync;
}
}
void ThreadMessageHandler()
{
SetThreadPriority(THREAD_PRIORITY_BELOW_NORMAL);
while (true)
{
bool fHaveSyncNode = false;
vector<CNode*> vNodesCopy;
{
LOCK(cs_vNodes);
vNodesCopy = vNodes;
BOOST_FOREACH(CNode* pnode, vNodesCopy) {
pnode->AddRef();
if (pnode == pnodeSync)
fHaveSyncNode = true;
}
}
if (!fHaveSyncNode)
StartSync(vNodesCopy);
// Poll the connected nodes for messages
CNode* pnodeTrickle = NULL;
if (!vNodesCopy.empty())
pnodeTrickle = vNodesCopy[GetRand(vNodesCopy.size())];
bool fSleep = true;
BOOST_FOREACH(CNode* pnode, vNodesCopy)
{
if (pnode->fDisconnect)
continue;
// Receive messages
{
TRY_LOCK(pnode->cs_vRecvMsg, lockRecv);
if (lockRecv)
{
if (!ProcessMessages(pnode))
pnode->CloseSocketDisconnect();
if (pnode->nSendSize < SendBufferSize())
{
if (!pnode->vRecvGetData.empty() || (!pnode->vRecvMsg.empty() && pnode->vRecvMsg[0].complete()))
{
fSleep = false;
}
}
}
}
boost::this_thread::interruption_point();
// Send messages
{
TRY_LOCK(pnode->cs_vSend, lockSend);
if (lockSend)
SendMessages(pnode, pnode == pnodeTrickle);
}
boost::this_thread::interruption_point();
}
{
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodesCopy)
pnode->Release();
}
if (fSleep)
MilliSleep(100);
}
}
bool BindListenPort(const CService &addrBind, string& strError)
{
strError = "";
int nOne = 1;
// Create socket for listening for incoming connections
#ifdef USE_IPV6
struct sockaddr_storage sockaddr;
#else
struct sockaddr sockaddr;
#endif
socklen_t len = sizeof(sockaddr);
if (!addrBind.GetSockAddr((struct sockaddr*)&sockaddr, &len))
{
strError = strprintf("Error: bind address family for %s not supported", addrBind.ToString().c_str());
printf("%s\n", strError.c_str());
return false;
}
SOCKET hListenSocket = socket(((struct sockaddr*)&sockaddr)->sa_family, SOCK_STREAM, IPPROTO_TCP);
if (hListenSocket == INVALID_SOCKET)
{
strError = strprintf("Error: Couldn't open socket for incoming connections (socket returned error %d)", WSAGetLastError());
printf("%s\n", strError.c_str());
return false;
}
#ifdef SO_NOSIGPIPE
// Different way of disabling SIGPIPE on BSD
setsockopt(hListenSocket, SOL_SOCKET, SO_NOSIGPIPE, (void*)&nOne, sizeof(int));
#endif
#ifndef WIN32
// Allow binding if the port is still in TIME_WAIT state after
// the program was closed and restarted. Not an issue on windows.
setsockopt(hListenSocket, SOL_SOCKET, SO_REUSEADDR, (void*)&nOne, sizeof(int));
#endif
#ifdef WIN32
// Set to non-blocking, incoming connections will also inherit this
if (ioctlsocket(hListenSocket, FIONBIO, (u_long*)&nOne) == SOCKET_ERROR)
#else
if (fcntl(hListenSocket, F_SETFL, O_NONBLOCK) == SOCKET_ERROR)
#endif
{
strError = strprintf("Error: Couldn't set properties on socket for incoming connections (error %d)", WSAGetLastError());
printf("%s\n", strError.c_str());
return false;
}
#ifdef USE_IPV6
// some systems don't have IPV6_V6ONLY but are always v6only; others do have the option
// and enable it by default or not. Try to enable it, if possible.
if (addrBind.IsIPv6()) {
#ifdef IPV6_V6ONLY
#ifdef WIN32
setsockopt(hListenSocket, IPPROTO_IPV6, IPV6_V6ONLY, (const char*)&nOne, sizeof(int));
#else
setsockopt(hListenSocket, IPPROTO_IPV6, IPV6_V6ONLY, (void*)&nOne, sizeof(int));
#endif
#endif
#ifdef WIN32
int nProtLevel = 10 /* PROTECTION_LEVEL_UNRESTRICTED */;
int nParameterId = 23 /* IPV6_PROTECTION_LEVEl */;
// this call is allowed to fail
setsockopt(hListenSocket, IPPROTO_IPV6, nParameterId, (const char*)&nProtLevel, sizeof(int));
#endif
}
#endif
if (::bind(hListenSocket, (struct sockaddr*)&sockaddr, len) == SOCKET_ERROR)
{
int nErr = WSAGetLastError();
if (nErr == WSAEADDRINUSE)
strError = strprintf(_("Unable to bind to %s on this computer. RubleBit is probably already running."), addrBind.ToString().c_str());
else
strError = strprintf(_("Unable to bind to %s on this computer (bind returned error %d, %s)"), addrBind.ToString().c_str(), nErr, strerror(nErr));
printf("%s\n", strError.c_str());
return false;
}
printf("Bound to %s\n", addrBind.ToString().c_str());
// Listen for incoming connections
if (listen(hListenSocket, SOMAXCONN) == SOCKET_ERROR)
{
strError = strprintf("Error: Listening for incoming connections failed (listen returned error %d)", WSAGetLastError());
printf("%s\n", strError.c_str());
return false;
}
vhListenSocket.push_back(hListenSocket);
if (addrBind.IsRoutable() && fDiscover)
AddLocal(addrBind, LOCAL_BIND);
return true;
}
void static Discover()
{
if (!fDiscover)
return;
#ifdef WIN32
// Get local host IP
char pszHostName[1000] = "";
if (gethostname(pszHostName, sizeof(pszHostName)) != SOCKET_ERROR)
{
vector<CNetAddr> vaddr;
if (LookupHost(pszHostName, vaddr))
{
BOOST_FOREACH (const CNetAddr &addr, vaddr)
{
AddLocal(addr, LOCAL_IF);
}
}
}
#else
// Get local host ip
struct ifaddrs* myaddrs;
if (getifaddrs(&myaddrs) == 0)
{
for (struct ifaddrs* ifa = myaddrs; ifa != NULL; ifa = ifa->ifa_next)
{
if (ifa->ifa_addr == NULL) continue;
if ((ifa->ifa_flags & IFF_UP) == 0) continue;
if (strcmp(ifa->ifa_name, "lo") == 0) continue;
if (strcmp(ifa->ifa_name, "lo0") == 0) continue;
if (ifa->ifa_addr->sa_family == AF_INET)
{
struct sockaddr_in* s4 = (struct sockaddr_in*)(ifa->ifa_addr);
CNetAddr addr(s4->sin_addr);
if (AddLocal(addr, LOCAL_IF))
printf("IPv4 %s: %s\n", ifa->ifa_name, addr.ToString().c_str());
}
#ifdef USE_IPV6
else if (ifa->ifa_addr->sa_family == AF_INET6)
{
struct sockaddr_in6* s6 = (struct sockaddr_in6*)(ifa->ifa_addr);
CNetAddr addr(s6->sin6_addr);
if (AddLocal(addr, LOCAL_IF))
printf("IPv6 %s: %s\n", ifa->ifa_name, addr.ToString().c_str());
}
#endif
}
freeifaddrs(myaddrs);
}
#endif
// Don't use external IPv4 discovery, when -onlynet="IPv6"
if (!IsLimited(NET_IPV4))
NewThread(ThreadGetMyExternalIP, NULL);
}
void StartNode(boost::thread_group& threadGroup)
{
if (semOutbound == NULL) {
// initialize semaphore
int nMaxOutbound = min(MAX_OUTBOUND_CONNECTIONS, nMaxConnections);
semOutbound = new CSemaphore(nMaxOutbound);
}
if (pnodeLocalHost == NULL)
pnodeLocalHost = new CNode(INVALID_SOCKET, CAddress(CService("127.0.0.1", 0), nLocalServices));
Discover();
//
// Start threads
//
if (!GetBoolArg("-dnsseed", true))
printf("DNS seeding disabled\n");
else
threadGroup.create_thread(boost::bind(&TraceThread<boost::function<void()> >, "dnsseed", &ThreadDNSAddressSeed));
#ifdef USE_UPNP
// Map ports with UPnP
MapPort(GetBoolArg("-upnp", USE_UPNP));
#endif
// Send and receive from sockets, accept connections
threadGroup.create_thread(boost::bind(&TraceThread<void (*)()>, "net", &ThreadSocketHandler));
// Initiate outbound connections from -addnode
threadGroup.create_thread(boost::bind(&TraceThread<void (*)()>, "addcon", &ThreadOpenAddedConnections));
// Initiate outbound connections
threadGroup.create_thread(boost::bind(&TraceThread<void (*)()>, "opencon", &ThreadOpenConnections));
// Process messages
threadGroup.create_thread(boost::bind(&TraceThread<void (*)()>, "msghand", &ThreadMessageHandler));
// Dump network addresses
threadGroup.create_thread(boost::bind(&LoopForever<void (*)()>, "dumpaddr", &DumpAddresses, DUMP_ADDRESSES_INTERVAL * 1000));
}
bool StopNode()
{
printf("StopNode()\n");
GenerateRubleBits(false, NULL);
MapPort(false);
nTransactionsUpdated++;
if (semOutbound)
for (int i=0; i<MAX_OUTBOUND_CONNECTIONS; i++)
semOutbound->post();
MilliSleep(50);
DumpAddresses();
return true;
}
class CNetCleanup
{
public:
CNetCleanup()
{
}
~CNetCleanup()
{
// Close sockets
BOOST_FOREACH(CNode* pnode, vNodes)
if (pnode->hSocket != INVALID_SOCKET)
closesocket(pnode->hSocket);
BOOST_FOREACH(SOCKET hListenSocket, vhListenSocket)
if (hListenSocket != INVALID_SOCKET)
if (closesocket(hListenSocket) == SOCKET_ERROR)
printf("closesocket(hListenSocket) failed with error %d\n", WSAGetLastError());
// clean up some globals (to help leak detection)
BOOST_FOREACH(CNode *pnode, vNodes)
delete pnode;
BOOST_FOREACH(CNode *pnode, vNodesDisconnected)
delete pnode;
vNodes.clear();
vNodesDisconnected.clear();
delete semOutbound;
semOutbound = NULL;
delete pnodeLocalHost;
pnodeLocalHost = NULL;
#ifdef WIN32
// Shutdown Windows Sockets
WSACleanup();
#endif
}
}
instance_of_cnetcleanup;
void RelayTransaction(const CTransaction& tx, const uint256& hash)
{
CDataStream ss(SER_NETWORK, PROTOCOL_VERSION);
ss.reserve(10000);
ss << tx;
RelayTransaction(tx, hash, ss);
}
void RelayTransaction(const CTransaction& tx, const uint256& hash, const CDataStream& ss)
{
CInv inv(MSG_TX, hash);
{
LOCK(cs_mapRelay);
// Expire old relay messages
while (!vRelayExpiration.empty() && vRelayExpiration.front().first < GetTime())
{
mapRelay.erase(vRelayExpiration.front().second);
vRelayExpiration.pop_front();
}
// Save original serialized message so newer versions are preserved
mapRelay.insert(std::make_pair(inv, ss));
vRelayExpiration.push_back(std::make_pair(GetTime() + 15 * 60, inv));
}
LOCK(cs_vNodes);
BOOST_FOREACH(CNode* pnode, vNodes)
{
if(!pnode->fRelayTxes)
continue;
LOCK(pnode->cs_filter);
if (pnode->pfilter)
{
if (pnode->pfilter->IsRelevantAndUpdate(tx, hash))
pnode->PushInventory(inv);
} else
pnode->PushInventory(inv);
}
}
| [
"root@poolcoin.pw"
] | root@poolcoin.pw |
f51be28603380741684e7a811ef8af073f4fcf7f | bed24ed6bd341da7818d7cfc988564a37bb9382d | /Synthetic/src/Synthetic/Events/LayerStack.h | 361911ab8b17813d9908e7c3b37e4b35744e5eb0 | [
"Apache-2.0"
] | permissive | qlurkin/synthetic | 6865aa3eaf9e29e5f0f531695af3cc362d0133d7 | 9bd50dc0048746304c611634bf16d9de27466f4b | refs/heads/master | 2023-01-03T22:01:55.388407 | 2020-10-20T11:43:27 | 2020-10-20T11:43:27 | 270,856,062 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 698 | h | #pragma once
#include "Synthetic/core.h"
#include "Layer.h"
namespace syn {
class LayerStack {
public:
LayerStack();
~LayerStack();
void pushLayer(Layer* layer);
void pushOverlay(Layer* overlay);
void popLayer(Layer* layer);
void popOverlay(Layer* overlay);
template<class T>
bool dispatch(T& event) {
bool res = false;
for(Layer* layer: layers) {
res = layer->dispatch(event);
if(res) break;
}
return res;
}
std::vector<Layer*>::iterator begin() { return layers.begin(); }
std::vector<Layer*>::iterator end() { return layers.end(); }
private:
std::vector<Layer*> layers;
std::vector<Layer*>::iterator layerInsert;
};
} | [
"qlurkin@gmail.com"
] | qlurkin@gmail.com |
a20c73321da73cc8d1d807984afea82cdb9c3f6c | 8e0da1edac91c82e9a0a6cd1d229ff41d0d7042a | /Math/Src/Vector2.cpp | 090cf9b8ebea2b8549285803e326d8c1c7fe37cf | [] | no_license | MaxFanning/CCGE | 813d4917cf417019fecd343411f913e2702b7172 | 810245edbf67301b3fd24365d98704cc23d17208 | refs/heads/master | 2021-04-27T21:04:01.601866 | 2018-02-21T20:32:55 | 2018-02-21T20:32:55 | 122,390,274 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 664 | cpp | #include "Precompiled.h"
#include "Vector2.h"
namespace CCGE {
namespace CMath {
Vector2 Vector2::XAxis()
{
return { 1.0f, 0.0f };
}
Vector2 Vector2::YAxis()
{
return { 0.0f, 1.0f };
}
Vector2 Vector2::Zero()
{
return { 0.0f, 0.0f };
}
Vector2 Vector2::One()
{
return { 0.0f, 0.0f };
}
Vector2 Vector2::operator/(float s) const
{
return { 0.0f, 0.0f };
}
Vector2& Vector2::operator+=(const Vector2& v)
{
//return { 0.0f, 0.0f };
}
Vector2& Vector2::operator-=(const Vector2& v)
{
//return { 0.0f, 0.0f };
}
Vector2& Vector2::operator*=(float s)
{
//return { 0.0f, 0.0f };
}
Vector2& Vector2::operator/=(float s)
{
//return { 0.0f, 0.0f };
}
}
} | [
"31266092+MaxFanning@users.noreply.github.com"
] | 31266092+MaxFanning@users.noreply.github.com |
7a68f40cbc26633c210e288cf1d9171ae61404f8 | 97aab27d4410969e589ae408b2724d0faa5039e2 | /SDK/EXES/INSTALL VISUAL 6 SDK/INPUT/6.0_980820/MSDN/VCPP/SMPL/MSDN98/98VSa/1036/SAMPLES/VC98/sdk/com/inole2/chap16/beeper6/beeper.h | d603171dc77226f3437041aeea1ec1fed8e7e611 | [] | no_license | FutureWang123/dreamcast-docs | 82e4226cb1915f8772418373d5cb517713f858e2 | 58027aeb669a80aa783a6d2cdcd2d161fd50d359 | refs/heads/master | 2021-10-26T00:04:25.414629 | 2018-08-10T21:20:37 | 2018-08-10T21:20:37 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 6,868 | h | /*
* BEEPER.H
* Beeper Object #6 with Property Pages Chapter 16
*
* Classes that implement the Beeper object for supporting
* property pages.
*
* Copyright (c)1993-1995 Microsoft Corporation, All Right Reserved
*
* Kraig Brockschmidt, Microsoft
* Internet : kraigb@microsoft.com
* Compuserve: >INTERNET:kraigb@microsoft.com
*/
#ifndef _BEEPER_H_
#define _BEEPER_H_
/*
* This #define tells <bookguid.h> to not define GUIDs that will
* be defined in MKTYPLIB-generated header files, like ibeeper.h.
*/
#define GUIDS_FROM_TYPELIB
#define INC_AUTOMATION
//CHAPTER16MOD
#define INC_CONTROLS
#define CHAPTER16
//End CHAPTER16MOD
#include <inole.h>
#include <malloc.h>
//This file is generated from MKTYPLIB
#include "ibeeper.h"
//Help context ID for exceptions
#define HID_SOUND_PROPERTY_LIMITATIONS 0x1E100
//English exception strings
#define IDS_0_MIN 16
#define IDS_0_EXCEPTIONSOURCE (IDS_0_MIN)
#define IDS_0_EXCEPTIONINVALIDSOUND (IDS_0_MIN+1)
//German exception strings
#define IDS_7_MIN 32
#define IDS_7_EXCEPTIONSOURCE (IDS_7_MIN)
#define IDS_7_EXCEPTIONINVALIDSOUND (IDS_7_MIN+1)
//Forward class declarations for friend statements
class CImpIDispatch;
typedef CImpIDispatch *PCImpIDispatch;
//CHAPTER16MOD
class CImpISpecifyPP;
typedef CImpISpecifyPP *PCImpISpecifyPP;
class CImpIConnPtCont;
typedef CImpIConnPtCont *PCImpIConnPtCont;
class CConnectionPoint;
typedef CConnectionPoint *PCConnectionPoint;
//Number of property pages we support
#define CPROPPAGES 1
//End CHAPTER16MOD
class CBeeper : public IBeeper
{
friend CImpIDispatch;
//CHAPTER16MOD
friend CImpISpecifyPP;
friend CImpIConnPtCont;
friend CConnectionPoint;
//End CHAPTER16MOD
protected:
ULONG m_cRef; //Object reference count
LPUNKNOWN m_pUnkOuter; //Controlling unknown
PFNDESTROYED m_pfnDestroy; //To call on closure
long m_lSound;
PCImpIDispatch m_pImpIDispatch; //Our IDispatch
//CHAPTER16MOD
PCImpISpecifyPP m_pImpISpecifyPP; //Our ISpecifyPropertyPages
PCImpIConnPtCont m_pImpIConnPtCont; //Our IConnectionPointContainer
IPropertyNotifySink *m_pIPropNotifySink; //Client's
PCConnectionPoint m_pConnPt; //Ours
//End CHAPTER16MOD
public:
CBeeper(LPUNKNOWN, PFNDESTROYED);
~CBeeper(void);
BOOL Init(void);
//Non-delegating object IUnknown
STDMETHODIMP QueryInterface(REFIID, PPVOID);
STDMETHODIMP_(ULONG) AddRef(void);
STDMETHODIMP_(ULONG) Release(void);
//IBeeper functions
STDMETHODIMP_(long) get_Sound(void);
STDMETHODIMP_(void) put_Sound(long);
STDMETHODIMP_(long) Beep(void);
};
typedef CBeeper *PCBeeper;
//DISPIDs for our dispinterface
enum
{
PROPERTY_SOUND=0,
METHOD_BEEP
};
/*
* IDispatch interface implementations for the Beeper.
*/
class CImpIDispatch : public IDispatch
{
public:
ULONG m_cRef; //For debugging
private:
PCBeeper m_pObj;
LPUNKNOWN m_pUnkOuter;
WORD m_wException;
ITypeInfo *m_pITINeutral; //Type information
ITypeInfo *m_pITIGerman;
public:
CImpIDispatch(PCBeeper, LPUNKNOWN);
~CImpIDispatch(void);
/*
* This function is called from CBeeper functions that
* are called from within DispInvoke to set an exception.
* This is because the CBeeper functions have no way to
* tell DispInvoke of such exceptions, so we have to
* tell our IDispatch::Invoke implementation directly.
*/
void Exception(WORD);
//IUnknown members that delegate to m_pUnkOuter.
STDMETHODIMP QueryInterface(REFIID, PPVOID);
STDMETHODIMP_(ULONG) AddRef(void);
STDMETHODIMP_(ULONG) Release(void);
//IDispatch members
STDMETHODIMP GetTypeInfoCount(UINT *);
STDMETHODIMP GetTypeInfo(UINT, LCID, ITypeInfo **);
STDMETHODIMP GetIDsOfNames(REFIID, OLECHAR **, UINT, LCID
, DISPID *);
STDMETHODIMP Invoke(DISPID, REFIID, LCID, WORD
, DISPPARAMS *, VARIANT *, EXCEPINFO *, UINT *);
};
//Exceptions we can throw from IDispatch::Invoke
enum
{
EXCEPTION_NONE=0,
EXCEPTION_INVALIDSOUND=1000
};
//Exception filling function for the EXCEPINFO structure.
HRESULT STDAPICALLTYPE FillException(EXCEPINFO *);
//CHAPTER16MOD
class CImpISpecifyPP : public ISpecifyPropertyPages
{
protected:
ULONG m_cRef; //Interface reference count
PCBeeper m_pObj; //Backpointer to the object
LPUNKNOWN m_pUnkOuter; //For delegation
public:
CImpISpecifyPP(PCBeeper, LPUNKNOWN);
~CImpISpecifyPP(void);
STDMETHODIMP QueryInterface(REFIID, LPVOID *);
STDMETHODIMP_(ULONG) AddRef(void);
STDMETHODIMP_(ULONG) Release(void);
STDMETHODIMP GetPages(CAUUID *);
};
//CONNPT.CPP
class CImpIConnPtCont : public IConnectionPointContainer
{
private:
ULONG m_cRef; //Interface ref count
PCBeeper m_pObj; //Backpointer to object
LPUNKNOWN m_pUnkOuter; //Controlling unknown
public:
CImpIConnPtCont(PCBeeper, LPUNKNOWN);
~CImpIConnPtCont(void);
//IUnknown members
STDMETHODIMP QueryInterface(REFIID, PPVOID);
STDMETHODIMP_(DWORD) AddRef(void);
STDMETHODIMP_(DWORD) Release(void);
//IConnectionPointContainer members
STDMETHODIMP EnumConnectionPoints(IEnumConnectionPoints **);
STDMETHODIMP FindConnectionPoint(REFIID, IConnectionPoint **);
};
//This object only supports one connection per point
#define CCONNMAX 1
#define ADVISEKEY 72388 //Arbitrary
class CConnectionPoint : public IConnectionPoint
{
private:
ULONG m_cRef; //Object reference count
PCBeeper m_pObj; //Containing object.
public:
CConnectionPoint(PCBeeper);
~CConnectionPoint(void);
//IUnknown members
STDMETHODIMP QueryInterface(REFIID, LPVOID *);
STDMETHODIMP_(ULONG) AddRef(void);
STDMETHODIMP_(ULONG) Release(void);
//IConnectionPoint members
STDMETHODIMP GetConnectionInterface(IID *);
STDMETHODIMP GetConnectionPointContainer
(IConnectionPointContainer **);
STDMETHODIMP Advise(LPUNKNOWN, DWORD *);
STDMETHODIMP Unadvise(DWORD);
STDMETHODIMP EnumConnections(IEnumConnections **);
};
//End CHAPTER16MOD
#endif //_BEEPER_H_
| [
"david.koch@9online.fr"
] | david.koch@9online.fr |
d7e3239207cfd7933ff10600cc731127da4a334c | 4e16586c4d70ad578899cf205dcb188383a751cb | /example/23.usb_device/USB_msd_sd/1.usb_msd_sd.cpp | 4a92f18a4f7ff53c6686b40c9fa14348350e009a | [] | no_license | bladrome/eBox_on_MQTT | 5ecb20a84f74267467ae09e74acac98a0d20d3c5 | b0e3129411cffdbe4b3b153ec6de795cc493887e | refs/heads/master | 2023-08-16T19:42:29.679799 | 2023-08-12T14:06:17 | 2023-08-12T14:06:17 | 87,694,771 | 0 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 897 | cpp | #include "ebox.h"
#include "usb_msd_sd.h"
/*
* Disk initilization
*/
int USBMSD_SD::disk_initialize() {
int ret;
ret = SD::init();
mass_memory_size = SD::get_capacity();
_status = 0;
return ret;
}
int USBMSD_SD::disk_write(const uint8_t* data, uint64_t block, uint8_t count) {
if(count == 1)
{
return(SD::write_single_block(block,data));
}
else
{
return(SD::write_multi_block(block,data,count));
}
}
int USBMSD_SD::disk_read(uint8_t* data, uint64_t block, uint8_t count){
if(count == 1)
{
return(SD::read_single_block(block,data));
}
else
{
return(SD::read_multi_block(block,data,count));
}
}
int USBMSD_SD::disk_status(){
return _status;
}
uint64_t USBMSD_SD::disk_size(){
return mass_memory_size;
}
uint64_t USBMSD_SD::disk_sectors(){
return mass_memory_size/512;
}
| [
"blackwhitedoggie@163.com"
] | blackwhitedoggie@163.com |
3c13945ef55796f5876a8a6b60bd522c8c825b2d | 0f4012d03230b59125ac3c618f9b5e5e61d4cc7d | /Cocos2d-x/svnserve/Encrypt.h | f2e7160c48a590e2830a16d390d00decd0a5ade5 | [] | no_license | daxingyou/SixCocos2d-xVC2012 | 80d0a8701dda25d8d97ad88b762aadd7e014c6ee | 536e5c44b08c965744cd12103d3fabd403051f19 | refs/heads/master | 2022-04-27T06:41:50.396490 | 2020-05-01T02:57:20 | 2020-05-01T02:57:20 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,829 | h | #ifndef ENCRYPT_HEAD_FILE
#define ENCRYPT_HEAD_FILE
//数组维数
#define CountArray(Array) (sizeof(Array)/sizeof(Array[0]))
//////////////////////////////////////////////////////////////////////////
//网狐32位MD5加密和20位异或加密解密
//MD5 加密类
class CMD5Encrypt
{
//函数定义
private:
//构造函数
CMD5Encrypt() {}
//功能函数
public:
//生成密文
static void EncryptData(const char* pszSrcData, char szMD5Result[33]);
};
//异或加密类
class CXOR6601Encrypt
{
//函数定义
private:
//构造函数
CXOR6601Encrypt() {}
//功能函数
public:
//生成密文
static unsigned short EncryptData(const char* pszSrcData, char* pszEncrypData, unsigned short wSize,int encrypt_key_len=5);
//解开密文
static unsigned short CrevasseData(const char* pszEncrypData, char* pszSrcData, unsigned short wSize,int encrypt_key_len=5);
};
//MD5 加密类
class CMD5
{
//变量定义
private:
unsigned long int state[4];
unsigned long int count[2];
unsigned char buffer[64];
unsigned char PADDING[64];
//函数定义
public:
//构造函数
CMD5() { MD5Init(); }
//功能函数
public:
//最终结果
void MD5Final(unsigned char digest[16]);
//设置数值
void MD5Update(unsigned char * input, unsigned int inputLen);
//内部函数
private:
//初始化
void MD5Init();
//置位函数
void MD5_memset(unsigned char * output, int value, unsigned int len);
//拷贝函数
void MD5_memcpy(unsigned char * output, unsigned char * input, unsigned int len);
//转换函数
void MD5Transform(unsigned long int state[4], unsigned char block[64]);
//编码函数
void Encode(unsigned char * output, unsigned long int * input, unsigned int len);
//解码函数
void Decode(unsigned long int *output, unsigned char * input, unsigned int len);
};
#endif | [
"hanxiaohua85@163.com"
] | hanxiaohua85@163.com |
a8fad6cec7f505db1cfacda8fada7c82787a21ab | 5178ebecc4458b360b7593e31353ab18e519953e | /include/npstat/nm/UniformAxis.hh | e63211fe5ae9c2b7ad83c6dc40ae24462675ad89 | [] | no_license | KanZhang23/Tmass | 9ee2baff245a1842e3ceaaa04eb8f5fb923faea9 | 6cf430a7a8e717874298d99977cb50c8943bb1b9 | refs/heads/master | 2022-01-10T10:51:49.627777 | 2019-06-12T14:53:17 | 2019-06-12T14:53:17 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 3,462 | hh | #ifndef NPSTAT_UNIFORMAXIS_HH_
#define NPSTAT_UNIFORMAXIS_HH_
/*!
// \file UniformAxis.hh
//
// \brief Uniformly spaced coordinate sets for use in constructing
// rectangular grids
//
// Author: I. Volobouev
//
// June 2012
*/
#include <vector>
#include <utility>
#include <string>
#include <iostream>
#include "geners/ClassId.hh"
namespace npstat {
/**
// This class contains the info needed to define an axis of a rectangular
// grid. The distance between grid points is uniform.
*/
class UniformAxis
{
public:
// The number of coordinates must be at least 2
UniformAxis(unsigned nCoords, double min, double max,
const char* label=0);
// Basic accessors
inline unsigned nCoords() const {return npt_;}
inline double min() const {return min_;}
inline double max() const {return max_;}
inline const std::string& label() const {return label_;}
inline bool usesLogSpace() const {return false;}
// The following function returns the grid interval number and
// the weight of the point at the left side of the interval.
// The weight will be set to 1 if the given coordinate coincides
// with the grid point and will decay to 0 linearly as the
// coordinate moves towards the next point on the right.
//
// The coordinates below the leftmost grid point are mapped
// into the 0th interval with weight 1. The coordinates above
// the rightmost grid point are mapped into the last interval
// with weight 0 for the left point (it is expected that weight 1
// will then be assigned to the right point).
std::pair<unsigned,double> getInterval(double coordinate) const;
// Similar function which calculates the weights including
// the points outside of the axis boundaries
std::pair<unsigned,double> linearInterval(double coordinate) const;
// Convenience methods
std::vector<double> coords() const;
double coordinate(unsigned i) const;
inline double length() const {return max_ - min_;}
inline bool isUniform() const {return true;}
inline unsigned nIntervals() const {return npt_ - 1;}
inline double intervalWidth(unsigned) const {return bw_;}
bool operator==(const UniformAxis& r) const;
inline bool operator!=(const UniformAxis& r) const
{return !(*this == r);}
// Closeness within tolerance
bool isClose(const UniformAxis& r, double tol) const;
// Modify the label
inline void setLabel(const char* newlabel)
{label_ = newlabel ? newlabel : "";}
// Methods related to I/O
inline gs::ClassId classId() const {return gs::ClassId(*this);}
bool write(std::ostream& of) const;
static inline const char* classname() {return "npstat::UniformAxis";}
static inline unsigned version() {return 1;}
static UniformAxis* read(const gs::ClassId& id, std::istream& in);
private:
double min_;
double max_;
double bw_;
std::string label_;
unsigned npt_;
#ifdef SWIG
public:
inline std::pair<double,double> range() const
{return std::pair<double,double>(min_, max_);}
#endif
inline UniformAxis() : min_(0.), max_(0.), bw_(0.), npt_(0) {}
};
}
#endif // NPSTAT_UNIFORMAXIS_HH_
| [
"kanzhang@fcdflnxgpvm01.fnal.gov"
] | kanzhang@fcdflnxgpvm01.fnal.gov |
a11506e53e436e56dee387d3e6b1a34a388d4e83 | 7d91170c0c6b7abb0784a8521755aefee650f7e3 | /HiUqoEL6NvhS2Js3/GRWOAr35s4aMD9fE.cpp | ee66ac6a58972fa4e81489435dd9adeed8a480bb | [] | no_license | urlib/usi35g | e577ca090fc4a60b68662d251370a7cd7cc2afe3 | 46562fa29da32e4b75d8f8fd88496e95a3937099 | refs/heads/master | 2021-04-08T04:02:59.860711 | 2020-04-15T04:22:45 | 2020-04-15T04:22:45 | 248,737,049 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 42,238 | cpp | 蹈𣤥北𞡑𢟳𩥭텴𢶴𤸌𗮾𡧴汃㻅𥆂𫒶橥𤎑ﹿဏ⮶惵᷀𪨷𥖧䇅𠯔🧨𛂆𦥾囆𔒍𪶝𬈸𮝧𡒘𖮍𧈆롞𡕊𧷇垶铀𨎵⺫暬𗎦𐔻ឃ𭉇𦛹휟ᔼ𭾍ⲿ𬅏𘓵𩐷蠬𗱬辶഼姴驖𝓠뗵𫒈𓇟𪶦𑆵𧶨𗈀𦭦ᶺ벣汋𝐫𗖛铭釡𮡛𧶖𤖏ﲖ𠻸𤺫≉🕈𫈦ٍ𪕖康䎌𨉂Ї𤠵𣕪隯𑴕𮟭𠒖㈝𤖣鍢𧒏ც𫸧ᔎ㻠ꨰ𦈴𑋌𨐏ﲐ𭫅븵껧𡞽𝡒酸𪻕𢡢뒟從𤖞㉮𬙯▧䬅𣠀𮈳Օ𓎈₥龔⅓𗓟鲇ᑡ𪶜𬗹䀦堥𠏣𐌳𢽞𦪠횹뛩𨔯𮨚仍𩥱𣫻𩹗𮡴𩚄𭶴𤚄𥋍钉𥾺𪄧桡ᴼ瘒𦝸𠍄🆕뀙𑵀𖹁䀝𡡤ﬦ靀䘋𡡥𪗝𪳴𭺐⼑펇𩈽𧙰Ò𩸦𛃃𘘁慃춗𘥯𝜴𩘟ᒍ𥹪𒓣𞠇𓋿ꆡ舸𬓜𒊹𪝕𢾦𣴒⛴𣻝𨲸𤁾좤👐轝𦖅𡺮ꀥᬂ𘕭󠆁𣘾ᙾ𝪯䟩𥅟⃔𥶸칱𠮏ၱ楇頋Ⓢ쮒𪂧𑀳𥜰Ꙋ𦤨ㄠ🟤𤋿𠚵䝬䅺㙧𠡑ꇘ𮚵⦭鲎𛇷𥰟𤱎𬄠雋𪎢𣮡𡢠𑩾𧕖𧱌𒎔想𡠱꺻𓏠𭟯𡴒ᄽ𬤖쒨𤝱𫃸𓀰𩁆驒𬨢𢣈𐑼𖠷𘆊䭟顡𢎮𝜑𦮏𩖼⊳𐎹𘠚ᘫ𑇟룘𔑜𫦔傹揌𬽂𓇼𤐸𭽛é𥐷욡쉡ϝ쟙륊𥥘𬱃ዒ겫𥈴뽟𢹵龩𠳄牍𑲅隚𥢭똃𨅡𪁹𖧻죽골ﲼ饘𣧨𤤏𢕑𤕎⑂ᆉ䱪𪁧𫟐🙆矞𮊙𛂐碹𤭏𩪓𖣴𗵙𐰙𢞢𬋩𤎻ᗫ𖥮𢧥𢹝蹖汐𫑺𑋠𠦄𧃮𡛶𘋴𣉁장𧭼𬳗𮇵釄𨼇𫩡𗈘𤬰𗉊貑𧤌祝𣦍㵀𣅪远䪟𘡲𢼡♀𪧰쁮绱𔔷𝪇𨥇𪣵𗟓ᦕ𦯛𥌞𥖯𬊲䃧钾𩑞湟𥵢𢨮𢎋𫖝𧤪쇝𦀓𥖐𪤣𠓀𝝘𠩎𡨒쬒鏒𪫿𝔍础汧鮷鞫𠒁𛈷𤚖绮𩭰𑵽넛쌼톨澰𢇺𫟊뎋揉𡏍죡𥪹刱𤣓𦖎左𝢘𤒢𠓈𠹤𨽌荓缝𡶅𥩆𝤅纉𭍠𪎰윈⼖蓋뇫𬘾𩳞𐦅𡛗𗴯𐄐𦾩𠂏踡陶🅊💹綟𬝣麻𦶄벬輶𤭮𨗠𮊌𮒻𓋊쬕瞌𘊷㑎𑃓𦟅𥱼𫓆䙥𮁢𨓟𘓝𒉛Ӗ𩓪뮽𮕒궔𬾏⺩𫵝𐢙𨃻布𬝠訢榠𗥆𮮞𔐞𦡯𬉍𦬁𗡵𡼿𫇬𢯎𠰑𩂉𣤮穊ﯩ𥙾𢳕瞥𡒂㌲⺎𘜃𒄟て𦍎𖧓𩁒ꧬ長𨣳𭵲𩇳𡅾𧒦𗨜푧斠𨚴𫏏៨줼烄ᑷ薻𭻶ꢙ𣺿𝀣犋Ღꆭ🨴𡴉𧃕ﲺ𓐗︄𥡡𗽒ꪸ𗫑뇚딛䂐𩐳钢𡑶𘔰𪎸𭽙搋櫽姶褥屄𥽗땂𪙥𮕾촰㖟𦻹鸀㯣𠦓𭝠𡺶𗪶𬝃𔔦𨑕𧄜𭽋ᒼ𡟒ⵞ𥕎𘚟𠼁맶𫊋셗痀ૡ𐃑𢼗𦻓杤镓ᮟ䱯𐮇𠥐龵薳쭮咇𭴦𫀆𬮜穄𗡩㍓纫螢𡗑𭥾𤵱Ѩ𞸵霗𬼌⥻𠝰颒𖠧퉒鰾𨚎𫥴汮犆𢘙뼏𡝵𣶻𦛩𪺭𒈭𪜗ᝢ𪒿𐠲𐀷𧢓銠𗑩󠅏𛄁𦸹𡎄春𖹠監Ҽ𣺲𡮡𫟬𓐚𭌙矙朒쫠🧇尗㚄𥞀됊𣚏啧𢐈躛𫴥𨚜𩼐𧍯羚잝𝠗𪬩稒𣋿雸┻媵쳪𩮸𦪨챕ᔍয়𢏀綧𬊦𐀸𨅄⃒䧰𤒉㮝𣤑켈儇𐌇끾𓂐𡏎𢇵篖𬺞𑑄童𩗙餡跗🗷𥓽庐𬡬𫞎蘭搳슉𗥪𫵃苢䳾𥏺𫺸楰𣵋🇱𬚚𖽪𗅱㦣呤𣙃⻔𫨃䒥喳𗰭㎼𩈞튆𢾏㣇𮊕𮦒𝅘惘𝜕𡊢𩂨𢠱ꘀ𑐫휁𥖄𫕙鿀𗟐𐝔ᷣ𢔡𨥼𩍄𑂪ꦔ𝈔䖱𗓭𪯳𝢙𨂆𬧶𐚃𥦐꽖ꨱ𔕺睇惿䐮㶒獚쀎𮖽㑳𣵲𦡕𠔻𑗁𩘗蛼퐀💓𭧞𑆐腛욚𡁭𨮤𩺀𒑤𨍳띚㣗𤼻𣀴𝀂쇾𧗤𭾛𔔢𑴀䘓𥟄퇼늝𥵪ヨ៴𣧘𬜔岖𘐧𦪼𫫓𘊜퉥𣳯팦𗼹𩩀𬎏󠇯箳𭊦魸𩄙𑃴胮泏剣𘆘襭泗捛💹𘨀𞢋紧𗗁𥮹톍⊀𩦺𫕟𦨞𬫐倘𝓒載𣔃🧙𭚧牠𩔴𦈥𛇋𣌃𧞕𩍛𠷂ེ𠽻𨒨𒂮𦍯𑌟𧪦ꖫ🂷剟乬𭑴𭫭ⴢ𧻥𭕈𬫅杅𓐬ꨖ䆍𨒙ﻛ鏮㘛𛋌㲇𪑋ᶚ𗽖𤞏🤠𤌈ꃑ𪉕𮍜퀀ᝤ𪢟䕇𪼔𭠡酱𑚸𧷟𬴻𢼃𫚙𑗈𧃳𑿒₂麼辪𠈕땓𥇱𡍔𣒘𬶃ꂄ敏ꄉ崚荻𫬡𠭆𡙊高𡭌𢹔俺裉𤬏佼ꩦṸ𤲢擌𛃃𡤋𪟗𪦪鐊𮨊■Ц𔘧郞𘃤🖍𣊞𝦹咹𩆾𣎇𪗔ㅽ⽝먕𨴳𗤍䫪𮡴ⱈ𣒭𒊝𡚿ޜ𤩧䞴幗悴𠚑𔗑銯𠠈胵𦛑🖽𓎓𫦥𩅚𤳑𩝃য়첌ꯨ𡿞䳨𮞈𮩉𐙖𮮘Ѳ픪𭃆𑊑𡵨𪴖𦈆謥塌좒𐳕𭇍눢妥𗵏喢𪋕䧹桥𡊍𪎼퓲𦵍㍷枬ὠ𥵝頂匥㈛𠅂䳇懃𔒘푥𥸩𐍨糷礆㊟𭁥𠲸𬸺𣇓𥡪䥤𢹿돥뛅纮嚖🥛𦓚🅁𪣡𪱅뀼𝖝𬙳✻練𗟢匞𧅮Ữ𡎩앥𥠹던⟹𢮍𝥒鎃𒄔𓐢𪖿𗮂𓇬湀뾾𬣶𨠪𭈖᨞𭶣𤡿𫾾勒𐓝㥼첵𡧒ⷖ𓍪ꀒ𡓜㨡汤𣱚𘖶𫹗毘䝭蠙鶭𝤘𣔯㠬𭥓█鸘𫀶ꗨ𑃁ꚗ⏿𡦻罸쟒𫉓𤺩𠊑𘍿̀𘜾𥶼絖뇽唏𠗑ඩ𑩶與𣁏遭攟峈𐝍⢴𥂞𥚮繸𝨴𒒐糪𝈚𠘾𐡭🃂𘨐ﾉ䭉𨊸𬆼𩩝鉎ʜ싿詿𝘦𨒔ⱹ𓌏𢙿𤐜🨐㮝뿣﮿㢹ꯥ𗥾𪮿ຝ𗜻𪬾𗊺임𤨱⪾𝀭𣆲𢭬𥧷𦃺ż𬌋𦙦ﮃ렃𡏼ॴᨭ혱󠆩𫎉껼Ⰽ𬛄𢄘𪱅𝄱𮉸𬤘𭒭꧅𤑟𬟷傡⍨𥪪𫞜緦㖵𡰹닶𒐌𗿈𡛽𪮰𡽙𩵗𭷿𨎇𨡷𢾃𧤢賮𥣞𛈫걗ꖊ蔆Ⴏ𭟅𪯐𩱈𥃩⬍踊𗱃𪿼성𐦇끩噉셃⥐𡌲𭈩첼𑄪𨢍𩁿𤨂馝𫻖铃炨섷𑪋𦗏𬢃𭁫𣥕𨽱𥝤绤ᩔ𥌲🅀𨏞𡧳𢍕𬪸潡𘃨𬝑ﭠ𗨝𗷲䕧곖𡽒ឞ𦠺ّ𘑄뾢⒵ﳙ𒌚】涙𫾅𒓡𮏛垱𫲡분𩪟𨻋𨽅蹝枉퍌𣕸𗾝樇𮄈챪𡧏𗤄𤐘𗊔區𨩾❲ꧢ㹸𫿟밻儏𢰃㉾𖨯졞𬑝𡉘禰𣬋椝𪤳즏𪵽騿🎧┸𘛾䛓潵庍𘣲랡𤥱𨮊𢞃떌𛁃┿𥫎꼉𧡪𥖮𭷯𬔦𫮫쐘Პ𞋿벮몂蜪ศ𪘞𦝱𝣚᳒𡡌섐ᷟ𑰌뗧𬡷ﱹ⚱𩯰鈜碹𫪭恡𘢓ꅘ𥆬𝤖𨃷睼𑓘𧇨層ᚡ輝𪂇𥱾𪑓́𐼓𖠒𮇓𬹩𨣶㟀倬𤲫𬴣𬻕𮘈𠗖𬤐𩶹𪨵𡔁걣𨫵𢿗𪕥ﶡꦾ䞷灦竓𧌿鞧𥓶𮞏𡞔ﰲ𑊈䆱獨𬱴𥃍𭦞𤏾𮚥𦼦𤝮䕀讁𦮼𘇭𦔠衋销𫝫餵𨇙𠅽𥁄讻𨏞戄𬫀𝚂𗛖𫲀糦𥉈𗿸𪭸곋𫒈𦼢䭓묈紡𤰵𞄜𝞘𫓯茿鋏𣟶🐱樇𗵱뽹𢰨𨏝𓉧𡿥𭲴𨖹𐝤瞋휴觤𨭪鈣𬥭甊𧅃𡿼𒊁𧴁蒾𧩬𪻫赔凑𥜜𡟛𫛂扗🛤𬻖ꢖ𠠄૦㛛ꊮꐆ䗹䶒ﶧ့鈳匟𦐖𪱲ベ𥜯𫷑𣨡𗓖𤖅ࡏ𧒲秝𭇐𣰏𠃔𬪊ா㐵⤯𐅴𤅌雧쬒𩛐ꂐᾮ𐔃𫴡𤱏𛃍訇𗝚𫱵𩬄𐫅𦂮쭷𩫐𛰍𣂧稆✹𮅠ؒ𣪍🂡𡙲읷ᡰ痎𐇬𦐌⽯拟𝜝趻𭩐𑱕葴䵲𭤮𢨊𩬤𩿶𨎔𐲔𮯋𮪤㈋🞵🧗𤱪𞸀𠐇뗋Ⴅ𤰏𢧈셲𐌆𗛃䚷𧳛鴀ⷾ䟙𑅘𥬅揝𣌩𠼵𝌣𛃩𪱤汄辷𪽉𧎩𧸫𛃇𤃻𩣯𘓒ꙟ饇쏒󠄑𢴬껶𛂮鉵𭲼⛭𠠝𣧕𦑯쮣𤝉𩵲𣓸𮜑𭭦𓉂𤷐𢵄𣐜𫿿ᯀ𡋜𭽊𭎳뤥첾𢞊𩐉陖𢙞𡿻𝀪𪹇跒𨍼𦤅𐬳솓𗟴𡝔𠙨ꈹ𮃍𖼾䧌𝠛𮫼䁴𪖤𣃆𗑣挄𬲮緳ࢼ梡𣂑枏斔剸𐨓哅𐠮𥇧𧶦𞲜喙𢝡𬙄𦓒𦧕𘔁𗰢ͱ𡖔꩟𢕟祡𧀄壋𭉒𭂭⽃옭𪧒𗬖𭈞𥖚볹𝃳𑙙ያ𗺡𛋀𡏗𠕋羐孰먆𭇵𬈨𨴦測𫼍𤭞ᕨ𩳙𨦿𤕈𢥋甞됃𦭓𦻫ᖽ𧔏𤅑̬ﰃ𣔓ំ𫽑𡃲𢂷뒻𬕝𡭋콇𦨙𬰜賋ៜ𠿜𠼵𝛊𨇹퍨↥㾓𦙂𘣁觨𮙶뉚𭪉𘣳瘗𢚦𩷿𢒏𪿫鵕𧯃㎵ጙ䚠嵅𘡐𭠏𩛖ϰ𝐁䊚쬠𬆕ꢤ𤀠𐡒𥑧𮇧𛃩𡆀𧯟𫖎𩇛𓉿퇍𞠦𭚁𪻥𩴂𥒖𠥿𥑋🧂𡽓𘛑𣭡𪫔霙𤔢𥺉𭐪𢺮䅏𤳺𧣫㗈𘂈口𭣌料𢌅𧁈𫠌睯𩂴𐑩𭏿닅𥡪鏅ោ𬟑𭢨윞褴촟璑𨡶蔛𦙫𥛁𣑫𥑴｡𡭮𭡰𡊇𓄙걓𪕣𮞎謁༰𤏒𗷪遣𓍔𢗜𡨕䝚𪋸陱𥆐梹𥛝𩯵𦗻𢊊𫃦𘕼鑷㢢Ⱓ𤆊䲘ዕ𒑋𬱧𗎫𨗙㛘ꛂ願ꮹབྷ𦠓⾩䯧𨤳🔐粃ᶣ鑈𨜚䔕퍃𢘡𠶴챩ᕧ𧰧𭄶𨙽ᇇ𠇝బ墉𨇨𠺗𬽈㡧𥺡𣄏賕ꘌ𩋲⁷𦗀ቸ𧕠蒈𭲀㭛𮋇𧑃䧴𩒹睺🀝𪖡뫽𦮙𬿩斃𢰰𪏜𤑆𦓨𩖜𡐰㈒𠨹𧲭𐆍㢐𤈣峘拥曷汛嘺簆એ擰ཽ𡹭𨏚臆𨧃ㆨ𫩯ꀭ𘖢𤅒땽繊怚𥤵𪆊ꣶ鸂𓁠㈬𤫅𭭱瑱뗄鶙탐䲖깷礣鯷냦𘈦𥎒גּ𫬣𬯚ꗮ𞲴Ჯ쟶娉𤹿쉌𬸲𠜢𔑜𑅚𗔹晚𢥇Ừ𣦪挘𘌑凪贱𔔟ᷳ㏷烥𝍀𤩦묋𮌦𢻥ֽ𫔫𦅍ꌄ𣢰𤏖喙𖧌𑜼聐ᣵ𦁂𩁳鴪𤪩𠭁롍෩魻𒒹‒𝦐띢𘃝𦲘𩪂揅匠𖼀𬀸𝡱糱𠀭좛𦁐𩶣䉐튖𣲑䫕䓈𭏞𩸯𘌫𡈻𮫟𬥘𦙿ﰪ𬑌𥏾𬯝𧨡𘠌ំ𧝐ᅤ𩿃᎐𢠲셨᷵ჱ癈𭯎⼀ꠡ𦅝➻𝛥𢚣𑣄𓊈𖾑ȏ缫穜䓿𪍓𫇤ꮽ𢒲ܜ𧒳䂯챈𢪗晜ᐐӶ𠪼ᐆ올䅤ﴲ쁒𩩭燊ޕ𒀎䰜𧝻𫟪鍉鋞𦤍䤯꛳𬰐𬰬槟혧𣦨𢨓𨪆𨙆𘘚𠇞𮋐䑎𗙘𠑆㐕㪊𥤡㶖ꁄ𣝰𥡍쬦ᵞ𡪚𒂌ꭊ𩥔𝜲𣻾㢾𗙖聯𬽚蚋ꝁ𡨘𝂇𦷧束𦘇𮍠䅗𩙐𩸉𑜆𨺄쿚𘢵𡻭涏𖫚鋒𛃤𫯳𔑩𗫕絔𝜟জ⤲𦪄㝦𢑊𐪁𪶯𦧑🎫𞋦𫵲𨵲𮝔𠥖輓𒈉𒎊蛚𣜓𖩉󠄨𩉝𦶎𭼖𪲒𪚪𩟜𬋟𐛖𤿑𡹗𗛵𘣧⟠𢝓햒櫹塻𩬤甡𩕟𫐣音맣袍𫴇𮮃ߣ厜𠎆𠎦余𐔊鬔┸𤞞췟쎒𭤡큵𧚛𫽪𩽠𧳭읲﹍𧬱𦨣𣊜𠠚𐋋𪥊瘱𡸍𥭊𠻊𝞆𥔃𮀢စ𭉛𗞺𪖪臨𐒶𩻈𩀿䅬ॡ鍧昳𨬡孵𢵫𣿆𦔯땧𬊔𗑐婢𢷤𠐖ﮧᖑ𮌺🍝咠𪺋𥳂淔ퟘ읟𝀓𪊰⩜□䗡🟃邪𢣙ꚙ𤼰𑦣𡔲𐹺𣤥湚𦹗경𪙽𐧫𖧿𥢣𦦊𞀎銽䥡維𑧓㕷䉐녵摷𠃳칕嶸ﯬ𠴖尰戉捵쑓🗄⑼鋓泭𒊊觷쭛𦷁폁𥶝𮑂𥊄瘸𭵪铋捂𖧩𫶚𬫹󠆨𣓓쿤ᢢ𤕬ߠ鶇𗞜ꋾ𘤲𥨺𦆅騀𠺓𭡗𓆍𪸃탱𑴥譟𨾏䦶𢃗𫐓𥵧𦕚𮓠࣯煰꓿𣴦𠅡𪊧𗯗魠𗝰ᦫ⌧뵜촼〝뻩˩𢱏ãỼ𥛫𭏌𫧏𭤎콊䕫懞땜뷤𤓨𗖃𧠮𨕳鉩搀欇맙ᚨᩨ侟𦏊ޞ𬍟𦕨秴𥗖涉𪏈쳇䋠덺𨣻㝿𥡍坼⽠䘤쩊뺏诜🃁𤤝첌𫓾𤠖𑠊齕𭺙𐬎𫣎꜉𗃽蜀֟𤠗𥯌𑩯𩷲𐅃𬕉𧵮𮃵𦂐₊𘫱抨𢛭𠌣𫗊糑𝣺𖤥푞𣳰㸝룄𖤼흹𝨁𬀞𗃲뿋𫆴𢆅ꗎ𠓆䮈첞𑣬𮟕䖢戭𤴷𮥣鑫𬳀𢬐𧍃𝒖𤕋𥵔祰撰趪𬃮꼞𢦷뛜熐🐱𢿠췾𥓐🔖𫮏𢾠ّ凟廿홭𣫀𧵆嬴羐뱪𤨷𮏗⯈䝝𖼎𛊶𐧗𛆒߅𩋞𗦤𗒸麽𦬐⫒덡𫉟𤳇𗵲莵沇𨆶뱃𮏆𩜢윩𐚗𠯕𫫜뎣𤯼𣼤𦦎ﱢ飼낈𧻩𣈸𭡼蒧愺𥊐궫𤽆Ì𥲖煕𫽛℀𘒅ꗣ仝𗰙𥠆𫢕崄𬛘𣡋𥄁𣖶ꅔ𭈺𬅯𦐛𭆹ꌿ𩞄잫𨾭苺𨇑䈁𤂯𬿋튵𡪠𫩅𣠃礯⭡쾺쯶𡞸⨭临𞠹𭆝씞暗ᖯ𨲈𦙫𤭏𦦲욱𭌭𥗚𠼆𤱆𤤎𤻓⟁𦇟𩥖𖬓𐊙좢𩽿侰𐓞𡏈繦妓憼𤼊𠉍𨞟𬵲𑀪𩧐𢸩𗖋𥂊꺒殿𪍣𩧤ም⚷𠻃灻Ⲉ𣂟鯉𠢸🌓𐜣𡅖𢺶ᙕ挹𪇳𓀙𫌑🝳𦣾롧껊됝𬐊軑뷔𐴓门㜊𨢟𡗐𗯍ᲅ쌁𣰸難됓𗃑⺓ⰻ𢩭𒎕党屃ꎦ𩟃谖𞥋𛋜𨅩ힺ𘉣𥨃𘏬𤨱ﭩ𪱋𮘷ȶ皶眆𫟃𮤛𤞧𩘘𭛝𪄍𘀒⺉𡑠𬰑鵰𥥷㡇䡊𫃴𪖂𪕜𫼣硩𒒜ܔﵜ𖭶獶𦂞𣢮惴䞠𝄿𐱅𐿪𦪟𨲔𨀀𦥺엙닠𥒽롾㌚뙺𓋔뭒𣩑꽐䂩𞄠𡤓萌𤩁읭遆𭛐掴𢺏𘃁𬩿𩅪ᴄ𨺸𨝭綆𣄜𦩕𠒺𨤌䷃ⳙ괹𦯺𡶺𩩕䐌칓𡢚뿡𤹶𞋇𥿾𗓠𠕥𫐵駣䶵𪳎𦬌𡄈餳𧄀搀𗮻㉁嫺𢉮𪊠𠓻𮮝𐭙𨊹㢨욹扴𭦆𮪲᳹𠷦徏𢷤㝏ࡂ廔𧐏𮘯ܡ腠𪫤𨪒ﲮ𥡋𪚲𥿌꧱홺㪴𤰘좬ՙ𧊌𢊂𤕺𑲥𧲝켇𤛿帊岚ㇹ⸘듗璈𝁌媃𭘚𠁹ꬮ𦢦𨻕籘쬊刄ꀂ嚭𐡼𑍬𝪇鮎倴𥻾𣜊𩕙𬬮캽𐌁𗂺𡛘꿪坄𣳤阊𠇫𗥛䙆琰䵎𨶙ဉ﮼𨜁𗸄𓊦𬜞뺟𣬗䛝𬋫𢈬㧢췆⮅𢔧ᅶ褹𢙏𗔰벿咗𮂇𪝽𖽹⨔𐙲𩖤𤮣𛈇𐘶𥒊𐡝𗝔𬙝𐘗𭐔튵𡢸孖ꕶ𛋓춼鵊𭸔𗴕鴗ࠪ𦵻𤱰䭗𣧌𪃒뉆坵𨠺𨡂燒𣿢锓𨷬𒂦𩝰𘟵㌕𣤰𮟪諉戭𪝐𐄀𣤶𗇅舧ʼ냐𮝷鶲𝘭𠫾𢣕띂닣𘟕𭼘퇢🟨𮡥ꈅ𧇕𗥑𗂫𐅀⨆刦𠫘𣔟𝖢𨔝𣬭𩱥們𘁼𡗖𧐻𘙋沔銇𮡽𧵄𥊌巸⨏𞢪굻𒑀𢻗𪊙떔𦂱𭥭謒𢨄𧑘𮙓㇖擱𐳾礧𒁺𨽑𤿐𬽈𫞨𧭦𦟢𢣫옶𫳋𡄱𦫯𞠯⇻𗴫悊ⷞ𐆍竽㬑蘤𣯐榽𣊆𢾑㙊遪𠃃𗞦𩣕󠆣ꊳꦅ热𓅙𦲢𩒥𪭫𬎭𩓫𘥹㞁탑𡮨💞𓐊鏎𦄥𘂉🝚쳁깳𧈞죭𖩧퉬𦹮𡏅᥎ﵗ𨠹𖣎콥繰뮆𮍎䊸𧾜쥤𖠊𬈷𝔍𭤆搤𫨭𭨊𢍺븁綘𭯽𝠞𢢊𫸐仑飼逈𢄣뵐𬪷쓠𛉠𐩯𩓰𪾈𦨌𦡾ᢼ䒺𐚾ﱾ胉ᬉ𪂔𣚶𣸢𤛻𢖟잳㬂𫳙탰𢱫𬘼ﻩ𗃓脇𔐃𦉅Ψ᳞𫊵𒀡̈𒈄𝕳𫢣֛𣍖跂𨳷㳀𝢶🚦𧑰𣈡칐𫊋𮮹𭗇𐹺🎕𪫳ꄏ핝ꍳ𐊙䵻𥠌蛢ꪅ𧝙𦓥𥗬𤙕𖤐𬋴𦣄𗴸𓏅忀𫌲戉𤇋𢷏𭍧𥎽䳋琒𦓠᧮𠼷𤾯𣦍振栱𗑤᧿ꎡ⬯𬠔𩁉𬀎Ⴝ𒒆𧬣𠵧♒𐔦黍篰嘚𢮫梀𒅥㸚𣑇𤾏阻饳𘞪𣸯𮊽𩇯𣓁㴥𒔟𣣤𧚈㻶𛅰ᧃ𑅱뎯𪽮𫩃잧𠋂𩵠𠌚𩻇𬶝𪮎넸𭗷ꊐ坠🨠𪶍𗞋⢈襎𬁚𥦍嗳𘡥𤴱罂𦺆㎻鴋𢈉唦ꛮ𤒂鶽𦯘콸檒薎顠🙄𣚧𬟆놵🖔𦪓𐨧暃𨪱잳ꔹ𢉅𥗠맂彘𝩪𬹩ꅛ딅𒓑秶𫱿븝ᛦ쌋ꀪ𗊑🇱𩄐𑗖𞱹𤿑㙔𦅑𮇭䨇駖㷁𩘍䣭𠈬𦼇֏󠆦嘐糔𓋰徐📦뀯𘥺隣垐毌🗈𩧢ᴅ𡢨𩚠𩦮𞥆窞ཧ褩㓫𤏲𤅬☴𠐖𣪗𪙔憎跎𒓱闙𡑝𫅬𦾊㫦𗧑𨮸𥿟롇𨿳𡐃땅쎭ᝨ𒔕ખ㶆칕✋쪙鏽愳𔕑𪧸𧷖𫻼𣅶뤉𤖬🂪𘩭𭾟𣩪遨𧗔𬛍컣碭腪짘옓𝃊イ𘧱𥠬𭩣Ɬ𢛱𢺉ᅍႝﮆ𧒪𣠪㧹𠏣䷻给䇏𤁫𧅺宑𨝸㋩𐃐𗰥珘𧦫䉵𮀢𡾤𣤶Х倨뽃㗴剓똻𝄽𗹕𫖄鯗𮪋᭵𑱬𗒔𖧩𫠬𥊢𔒭𭭅𬫤𤗗ᖳ㞕𠼅龦繖雉𬖶𝜽셗𗺑풴麋𐫖똄𫹭𮏻𢉬뉕𢭟𩐕뙧𫹙𝣭쏨𡦺📢𦼒𩾀騺𫢨𞋆勒𧿲𫈮똾䊰𤾖𡧧𤷗♗𥷖ﲪ뼫𓂇뜧𮍆𦳈줊郈鳞诙牴瞖𩗉㴣𝞙ư𣲊隲郱㹜䕑ಿ𧙖𦩏𖣖𥭡𥦹毕𥖊𧧖𘅊픋삏嬂𬮟nj𫅈枓𢧈𫡰ᗐᵒ𢕈𫷦𠚚𬖾𠯢묙𢈩𦓬𩩿𤶌휺☘𧪡᱂쩧𢭙㰑𪁮ô𞹮𑵓闫㎑롹틊𢻏𣰒뺆𠢶𧚺𝑇譡찅衫𤜐蕞ᬙඑ𢹴ࠗ𡔮禋鿬獘イ𪀵ﻆ𭮁🝈𥴢𩱘𥲭湾歶찛𪲇𭤜𡑴𢔊𗮓ﱟ𠪟𧭊典ᦧ𛈀𧼧𬚾𧖹𫲪𭐹ﶍ𭛏𢸺⚇ꭙ𧜇鷓𨌧𪻆𤇔𠢥𐊸𬰇𗾳𑒮𡐷𝪛犕𬥦𣫥⢠📊𑜨𝞧𐬁럞짡镬𗶑𖭵𖽰𮟘𡭒𬄆𧖌𡾘𭨳ⅩĔ𥜶𭪷镡𠬺𬻄𠲒炭毎鱦𝈠𫣰룏𥩈ਔ敔𨳃㒽𧪶첩蓇𧿕𪽪聝𫻲𝪢𮒉⏖𫢶𭙲𢸪𡷨틧𣄶𖧎퉐诜リ黻𗬙𮤹槹𥎾𫔡뵮𝐙˿𭛌𧧵眵虜𭹄𥲼𐔒𘧽𬶜睽稲𡏊𣀸𥘒𮅨騅㬥佑翊۷𓍍𮘥𡈰𫧰礱듡𘏳᪷𧸑𓆞𨳏𫴯惆쉕⧶𨚶𭼝𧣑𣶮𨪂𧿊౦𬽥蜦𣎅𡙼䇫𫥮繁𡋒𣧟襇𑁍𘣤내𢔃👤𘍅ጉ稜藈𐝇𛊴谶𑈐𞠇𒉯䈌𒒿酠𫃀𩓤㮋⦎䎍𭧴𖺍𫑵봊𨀹⇳𝚹䝮𩏵𭒂𣰣𑘘𛅦𥳤𦗩𭡴𧠃𡊦𢭨𤅠𡯶뤓쀼𨽵𡤢𣊓𩦐𦒮鍼𨟯ሣ𪑓𗱒谬邔𭦉𓅞𩷞𣊅𨁑𦣲㾔𧴃𨰢𡍣𞸲臭𪔂𐝧ꨲ뎇𒔜𗞷钛霾㓂膼ᄂ띂𭅂똽挆𔖰⑈膪⍞𥤏𗋲뢔𭞄䧸魲𦻲튢𑄴𥜯𪘞𡌣𦁭𧑊蓠𐡋鏗㨰雙🍗𑓐𝟷𪲳𢻉𝦤럾𨻕𣑕횩䋡펍𐧝መꙿ𩥟ӑ𣳄𩝍ﳮ绿𭟛𭿨Ⲏ𩡤ẋ𠭧𘠰𐌹薴𤑔𮍝𤬌𑱑𦙳𠼀𥪛쒷嵲셂🤕𧦥𠒰禞𫴏མ𢑱𣨏𨥻珴𨖿𭷇𝡰𒌊𗘟鬽𭆜𢷻𨕝ダ𤥋𨪝Ꮀ𮚃𒈱仍𥖄𧢀𝀿𨡙𬙖𐳀𝆎𩐽刉𤓝𤬫䇅텘ﮞꋰ𧌢벟𒃢𨽫搥⍇益㓃᩷𠎵蜝ᤩ𢄳㍬𥌦ᴫ잠𨇕췴𫦐𤟚絑𧩢狤㘉𬅚㩟杍ጱ𫱁𮙀쫞𠼲녦🏠︰𤇇ୱ𭝣𥶗𥀑𬽀骂宬𪌥𥻞𦵜𨂮︈帑⻇ℶ⚟𭠆𣰢𤧠얨駃𤪷늬儾滝𢑸遁𣙇𧬚𨶟𢂔𐼛ꏷ鴴翓𡋏攑ꧮ𠂻𢙃𫾲㴽䍤𠼰䎫𫓌𘓷𬪊𩟮𧂹𥛷𩎟獽𪢵㦰魘𢝖𪬼𭺜𡒧𨀻𨒻𫲜㞫𨢲ꮥ𩨟䋖𖧇𦁻𠄤懾𠲆𝛅𘉂쀵𬸈𩾶Ƶ瀍𘢢𑆝𩵬Љ𑰟ㅊ𨎳𬇤拓𦮻𗨶𤔾𭬺롌ꁸ荽直熇㟾𗺒𪢧𬿍𦂱궬𣱐𣹾ꫦ𦣍𬂄벒ڋ긍𡒫凂𥉢隔踼퐎𝒊𦎸誉㌢퐻𧌇𤺿𝂝𢟞𒀈𓅍흕謼𡚿⪳唾봮웂𡶨𤶑𮐞𦈹𐐞𭯲捚𭲂랽䞃䣩𫹦𐤹𪊖缍𗣫䚶𘋷𪦕𭵑拂𓌳虴䩁ᱪ飥𡪈𨛢𬤛𤬩𪥜𥁂𫸰꾒𗕱𭼀욨璽𩋇𐀓𛅵𬽺𑫁辩𝑆𨶎𝥑㌕尬洴𐎙𝍃𑿢櫬𛉌𫵴㷚𦶗𬊗𧠂𫌟𢲯㎨𡉪𮝺ꈡ𢭤𦷣𐣮▒𣮝𤴦𫢳𑪘𥉖𧜨䢜卦𥫆𢡭芑𐄁᭚𐰇𫌒縮𡌟𞱷𐡎𗠞츻𧝊𧟾𤡅𮏥毛𠔥𦺟𥱕𓏬孿𭴠𡉫𬟝𨲛𡆬𑍁𫈡𖨲ꭓᶆ𩫦⤝䆬曤㬍𡲧ꪕ𞢗𬾇𐅊𣡃𤆉𑵶𖤵ᄉዻ𭥙𔔤啛𮜂𪅴𗷉𢜈嶥𧖠홺𗞃䯒𣮛𮑀𧋫≸쯆𠞢𤐂⣢圅𝄬蘑䁣呹𧬓協𗦟𧷠𘫢𠐱𡣾🔵𫿒𤡗曫𭕠隆鱗𝥆𠋢𨬭𪕭𧃝𣍟𦉒⃚𔖇𦼁悭𢰜𡡥𑇈𢠂ಘ첿𢞵𭤸𧺻𢿽𦲺ằ뎮𥃻᧒฿ꆞ焅㸰𣚽⇿𨨾ẕ郉姝𭤴𪩋㖬𨘮ই𡉼䁊ꮫ𤅼襎㼍É𨏝𬥮ϝК𝑤𨍠𢠳𦺍𤰺𪿄𥳏ʟ鶩𪡴𧌋ണ𨉰𘝺컚𭁨𬧬顨ၯ󠄞鼶헝픩𦠎𡯇𣿸𥭢𓇐𐊹𮫩ȳ𪢁𩳲𪩀𝕚認缛𢲻璝𥋐分𧲜欷憕𡆦𥜏尦𤎍ᨿ𭯑𗌻퉔𪪺𤢕𤼎𫮏൛𠢀뼣ꤕ㆚⒱𫴁ⱬ𛇗𠀲𬕎𤙺𫓎𐌅𐲆ꥂ𣻠🅧⸝𭌇𐂏֝𢉄ꌴ𪙚쁤녍ꏙ㑃𭤺ൺ𣻑𩦱𪈪𠱢땉𫑵𧃾뤫🝙𤈰𡔶𐫥𞤂勺𥾸𪳜𠺬𢤭𮦹𥷧𥢒ʝ𭾓㹣𪙾㛃𧏈𨿞륧塂㷩蓡휀䮢厠𭾣뗥ಾ𢫈𞢞𫜩럎𬥐𫅬𥫭勩わ幎𩙥𦣫儅𥮺𦸛𖫚𐛼𦜔ࠀ𗈥⬍𥑻둴贞𐩣ሱ𨞚𐙞𬊶𧷝ーᐭ𡄏𣎎垆졷秉嫤𥤪𥂊𣍾ܥ𠑝𮪭𪲁𡼘艀리模𘨑უ𐂗跞𪸬𠵥𦐶훥𡫬𪁉㋹𨽄𩃹𐳂⧺𝘑♥𘡟𫒮𪘌𨀸謡𦤆괼𣋶𘉆𧆊춸𭥰獂נ𠐅𮬠𧡅𩦥഼𭌜𨻐珪イ𗱪夲䃤⺨𭆆𩳾𛇫㤱ⷤ🩌𮤵ᢴ𩮉묪𭒉䄄𦼍𪜭纛ꪺ𬅉𣀀𢫿𘃦𩍙𣬏𑀃쐍斾𦥑𡾊䠻𪍻𩠎𤟸𭀕𨤏믐則𦴫钾𝕤𢞀𡀊穛𭬐誇㨤𧗦𞡒𣶳𨲃⋉玸𝞓𭵕𤑾갢爱𩕟𗲓ꠎ숭䬺海㯕⧳遘𭂣𨕂𤀲𝓠𦄚洛쌸𦊪鷁ｔ𤑅𢸶𛊮﹖𡰮⓯𔖫蔖𡢐ꤸ𭝔眸𦧼𑑔𢶝𗹮쿪𗃈쟎𩬫骻𢤮𫴆𘠛뮔唪签瑿졳𐍧𡥼𥖭囹䰠넜쥗𩟟ⳳ贈啷𨒤𪔂𣙼𧖓ற𡽑𤓆ꮢ픷𢞰🁖𗎃𨵲ն㓅𞱿𖩀删𭰝캘𢾆𩓋𘋳𪇵𭺟︷䊙𦶬瘔렉ꃇ𩉴𦬿㢴𗗑𣒳蹏𡘌𣕕𝔥𞡕𤧮𪩂줳縛𧎡𣣝𮛍𫑽𠊴𬎆𢌱㗌𭃶𩞞玭𭢚𬼊𘫪䙙퓫𥛠𣓳觮𐕊艚地𭂸𝣁𦺰跭𠨂𨴺ィ肀𮒨𠞲𧎈𠜔능𠫲♌柇𦪭𘡈褨𨵼딷䱊値𪮀𒁽𢳳𗅝𗚒哝𨥲𢡝퀊融𠰶篑𬰾ꚻ牧𡐶ꏆꑣ𝋨䛳𝨵킕𫝉𮄭氣𪡂𣳨𠕊欄𣢈𖧌⢿킃聂𡞔𢝂钪坆磌𩗝𒋮𢁂朗𤔄䴆㋘𢡡𪔺媪抱𦁌⚴𗩧鬗롄𥽰ḣ𘀢𢷚𫣟𣅡㛰𣑤𦡖祤𨨥疪ⳮ𘃬𤴥𐜤蚁鼂𖬮꜏𨀪𬫬疯𣐹৷跮ꇫ쟭鄓𮇥𛄀𩳯𣈪Š𥒠䐨𝩘𩲺𤓛𨟭풰𧵂쉻ꣾ𦪇Ɽ溺𫉘𖧩𦁏㼔𑶓𥮠⪶𨢌惿𐽗𨸉𠎃叓鴷𩍏𢋩쳺𠔈𫞕梘𦍙Ο𢳹막䕖𣙣ﲎ뭔땏𩨻𮓤𨷚탚𩖎𮟉𩏽蚾笯𠜗𪼟𮛝𬌹慗𪺋翺ﶙ썈𪶂Ⱶ𠃱𡙄𥞨얈ᴦ𧮫𡙥𥠅⯡𤽰𮉲𡱮霡𤣲᩹═닠𖡍𣨍䴶𛆲𬝱𩆌끎ྞ𫡺𨁤𦊴⺢ᢔ𥏚𣇊𧵣𝂫𨯥𤜜際ᚔ滔𮕋𛲔𭩉𨎍𨲩𬧭涊𠡤𭅾𨟾냃띧𠂜⦳觻ರ𝑸𦡿𥱪㫥𗡂ᬹ𩈍マ𣐗榫腅𨯼𐔘𥁈𢯳캐蠭ᗏ𡞘𪝀ዉ𐔹𝆤㠠䎍𡋴𗺳𨘏𥪈툳៝诐쵞𠣹聘𬿯𤲓瓦𤙍颪𥜙𘃬𫮞䌷𩄒삣䓩𝛇𤔩嶧發𘠯봴✬嵸𭃬照𨑘ᘇ𘆍𛁡𐍲𢓏𥪽𧅝𭂁𡠊𬤦書招鮌핇낔𬱁䁚𩹋𩓖换𮟦𬃣Ⴊ𒉰䑌𧆫𢗒㽍𥶫𑁃𤠡ᾈ𘈟𠱏띠⯃걵𩫿𑅬設熷🕻𑓃㇀陽䉆ꓽ𥋁陭𦖑ퟕ𮜆ఢ𩔌𝨏劔𧋑Ꮝꌒ𢻙𑒼𭉢㬶𘛊𨥉𦍵𭚮𓊉𩆘纾ﴜ𩠫ࡀ籤𫍮𡼢땊ෞ𣬹𦿮𤸆𪴝𥡚𫟻銆菬𦓂𗣢𣅴𤍰쑨飏ᝪ𩢋𠑡𠲃𑈳𝚡𬘰𮝯ꫜ𫆘𠐾𠅵𝘸덫𠐌𠁜ڄ𬋨𛉍䘉𡄣𭋅ᓌ樏ṉ駤槞洼𡶕𢘖𣧦⇿𪛋𭬳𡪼Ň盘㠳𧾵晚𮣙𫆤𨒞깜𠞌𤑗랼瑀榼庫𣶱㞉𥆨𭧭ꑕ🝧𦬎豿𮭇紕𘎞懏𪍵𨤎䕝𦫙𪮅ឭ鱆䨃𣊛늱ꅭ𮄙脢𡠲ꌛテ𑆨𝢕𩈸𒂌惁𡂑ꂝ𘤍𪫏齋𦳼㜵椀篛桃𒎋⎎𧕕𮃲𦛌ꉬ𫷆봲𡾴㜳믇閇𤻜⢦軫瑱𥗖𝔘𩖼췎𪉗퓝𥘵𝣔𦑼𦬻𦙣㾻啇𭹚⃠𩚠𢯐ᆫ覈햺𮪺ζ村𩡭똪𢣈𤸅蓳𗮍䃳𨍙𥶝𬀂𭸠𥬘𠑻𩲌㋌⡧ᷰ𭂃䍠㜺𤱈䨐ᆄ𧌋𤡼⽡𤻷䶜𡦉𨶋噺𓁊墇ᣳ𡯖𐼿𬦤캭𡿰쬛𤹫𦝷𬆝𠝐鬃𩛽𨵒𢂎×𣶘𠙰᱓𞢊⎧覾閇嵢𮬬𨩐𔘙𘇌𗞫𨾐𨘫簤ꄳ𦐔𣅭𧧹༫𧱤𗵙ꎄᦿ뺢𢯞ઔ奁᧑冭𧶿ꃇ𢚸ퟀ秆𣹾껩美媊䅊쓒ʒ诏𠥼𦳪𡠌𗷣瑑ۑ賠鮽𩫫𗦢𮒻𢻲៚𬡔𫋶𛉠𓎍𧐬찳ꗯ𩁣𡏛ت땪𬝤㢲ഽ見땿𬇣ᝰᒀ𩧳𮤔ꊿ𮭀滤𞠼푥鎯濦𮍕𩡟𣰨𫸘𭲍㡠𬀲Ⅴ铛𢐏ᠸ𧹈ꂕ噺𛀑┮𤸯𦰧𤚼𨚿ֺ䍚𩯘🢡𧸄𫩜딆𨊘𧄘𗱴諕ॷ𩏎扷⮁𪀳砱𤀆𦟵鞣𘆸𣬺𗯊𑂧𨁐▲𗎄𢂗𠙀𧫆섀䈍熣𬸉𢒤𗍴쟤𞄍念𥡏𝁣炳𘤥鄔𥧞賿𦾵𣥝𠚡𨧈훂🏵𥥙龛𩚙𐐱𩱎𪼘叅䓆𬰒𘅢鵧𩀳𭊾𒂛𬒧𢀲𗡦𨅋㻓𧝬撁𮑽𡟱𠀛懶ࠕ𢿵ᑻ𭹤볁灣👻梆𤭳𧶗핹𗅫踸𣥚ࡣ𫉼㊗𭏭巃㘏𑘲𡸩𗡈썩𥍈콄捂𬒦𦫼𠕆쟙햢𨋨䥥𫐍𞺔㙏𣥹𧚀𡑕늽𭍶憶䌿𡤜𧓪났𨵅䇐ᅮ쵭𮊈歱㭘𐬡𦡲簅𪖪𑐄𧂃碵ꮑרּ䜇퐝뙽𦡌ﻜ𭢤𬳎ጒ𠞀𨊴𩿦饆뵈𡌐㳜𥘑𐘧𪄞𛄖ủ𥗚呝Ố𥫎𬸙浪䨥𫗛𩱰훈𫬪𮃔𣯃駂歸𤴜ᨺ䤚﨨𗽿𥖏𣆳킺錄𭐤𝪋ꄽ𫞜𥞋楡죄𧧤伵𠱑𘂟𑘭庿𮎘𘫯𬅕꧸𐡙𥕰𐅜𗭠𩭁𘩯𣝼ؗ햢𪥬슝𒌜𢐴𣵍𬯴떜𐳥𪹇🔆𪡞🗑𨐠䮿𑁒Ḿ𨀂辮𮥂𢋉𨍖𣆳𦦎𭾃𠘵𝆀𝖠𣙋𮍐索삌採𪛋𤜼읾𥥿𠈴𗮙𨫺𣲊𣣇篌𥸿🁚𡝽솯𤫇밚𣥻𫟅膢𩙮▧𪟢𣌧𪿋𥨊𮢔ƕ굵𠿭𭏲𠽹擅𬍷𦍯𝤽𥪹𝔮怍𤊹𧼰왬𢇓횛𢵧𪱜𨃴ʀ뜲𬛇蒢𫈖𝗦竊䮃췝𗑨䥆𐒻𬇏칕𥯤㞿𮧽𪂶𫸶𬟸왚🁲ﶂ쐦🨐𭇂饰軽㢳顠𨓓퐕𡞟𠍑𛋶䀳🂂𣗪𐫃𮐩🝀𩤀𦇩𑠥𒒰𠱂𓅯𐙓𘝎𢕑𥭎𤀽𓈪𑗒𬕝Ұ鵕𩛃𡭉𩴡𤣟𫰭𡿣𮛩킍𥒡𑠳𝩫𛋰𬗒𔖄𡜨𫙤𠵩ቛ𑲟⍎𥼁𑌐𨭫𣜋偙𫟂﮻🨓뽕𑫉𠼧𫳞𮑛䑠⛺𣫔𫷗줇𦿗侮責潻䤊횫𢊅鼰𞡦靛퇒壙𗸿𬉩ᦦ𗆑𑁟𭮌𨜴𤰎𭸱剿䞑𪊜⭅🜚𥕎𣸯咛𒁂𛆨봶槺𣃁猞僋𫰆岼𭿖𗠿롍𭹁北婀𢇫𣑇𨞼𪡺𩝂谎𭇘팂𡅷𭯗䦘𦿑𥵴𫀣𒔂뢡𐄘㫤퇵𩙴颫ۈ쟜䲟𫯻𢩖𪯠𠆈᭜𠖹𣡚𧳐ౙ𗸂𡦫邱煿ᲀᴤ𭈤𬔪𐋯𨶱𑨠𐦰翙𘩍ㆪ𠻿𢯒𩶽𐿣䚬𦔲緓븿𬬟𫰲ụ𧺁⏳𦤠𩹲𑣗𡾹𒈊𦁥𗏈﮼𨜏𡔛扐𢿠𫒁𭉕𤂊𣵡𡵤𓍵𮁾紟텕蝻🩅葚差綠𧿎빘峸欔𥑣𣚣𨰝𐃟𣤻药𨯓𧦐𬉄찣𡽱𮎘萚ꛗ𘉃𡣭𨺘𨎄칓𨩝＼𧷤텫𪺻콚𘛢𡻣藺좰湍𐚏𬜻𩨱𥡄𧵆╷𦾆𥿬𡻄𭨶䦑𡯑𢫯䊰ꅹ𫺃𝠾늓𢰒男쉘𛀽𤉻𠘻𘡸붠𗰊旮裻𬦓𗇀𭅩𠈓𢙡𓋪𤨛赦𗍚𣔮⢿𢯂𫉪춖🝐夎𫸻𐨪𫝛𧑢𪁒𐦎𓃰𠂵𣩹툛𘟑㜑돹㐍𩏭폑𫒆𧔖垄刻𨗼廐𥊑𭥚葵㳎𑘗֑𣚋𣙾⥾𡢥𦏸𓃌𫐛𩈨𭖃𞢄톋ꏿ┵诈㙠𑈠⾉𬥖🐋𣓷𤫌㒝𛁪𥮫𘀵鶡𤇉첨淄卹思𬃿嬸컹𬥏폿𛊪忹𪡱噫𤩤྇𭳚𐒐𑋳寷𐴃𪥬ꑶ焍𗎔𭱉𠸻㠱𡤥䪖䋃𪊻懲䔢᧗𫃏𤿯𡞴⠿𦮭卟ץ𢔌𩠃𢌎뷈𛆬𥁭𧭽𠯹ꗷ쒇𪏋𡏎🈴ꣳ듌𩲹𫕁𢕀缐܊𩵜抲𨀢퉯𗱼𦦏𥀪𮚣銊𩇠𞄰𑣗𠞍𥪈𮕁𢒿𧗙𥇠쌃💼𤮎𡵖𭱙𫻿𥛽ꀤ쌌尨적𤚬뛗幊𮝶듢𩀍꼊↫턟𢷉জ𥣁쵄𥈭ࢣ衩𦭁𗗁𧒻𗉌ﶇ國𪲦핧𢖕𪪷𣷉唢氏ᚏ𡰒𣮢ꄼ쀏𓅺𔗗꘧쒢𪈺𩰇茞𩼾喥ᮭ킪㑽𫹬𗕈𩖳陿ᚗ𭼡𤁪᷋ﺂ퐌蛖쮬𣮎𨣜𪙡𨧍뻓𭔤𮂱닽笥𧥿𢣎𣥣吵𨬍濲𠎇𩏾ᢰ𪱡𦖳𠑐𘝻틯県奚𪧏𪝰𤈓絈ԝ뚋䨋罵睉𝀏𩮑𪮨𘀌𬺔𣸄𡊓妰糧멮稉됫밇𧘥𤉯𧳙𤝄ꫪ奀㏊𮇇𘞏𝑀󠆃𗉫𫽊伭𨓭𥷺𡳨𩏒𥁈𩄶𗔖嗭𭦊𧍜𡁬𤎦𔔢拲뚁𠞉귅𠥱𪘯𫇥쐼𫒩𪏁𡳊௹𡜻𪸙𢯺𗮿🂥𡰽𪘄𐜬𔒺𨹜ୡ𣣷𡟜𩝼𧟨𪘳𬀑쫞ꗗ帞𩟆埾🟅𣚊𠣑禘𡨽㥟ﰲ謪𥌓졿葨𠄺𘉬気垔묂𢩍筥Ž𗺱𠉔𩼯𦉞𗃙𠓆𞄗𗵀𧓗𥯠𥆺𪘁腽𧂇𩎻𢱗𬈸𤈦𥽛섴𨼇𭾏昩𝟨𗻝𝪅Ჰ𬜠𭂲췓å⚕𤎍𡜝♑䤡䨼𡣕줷暜𠞤蘾伤𭤆접𩛡𤼼𐅬裌𮖏𩬲橺𦮗𣟞孅⸢냳𮒄𓄝𪕃𗥑𦉉⣐𓋜솆䒯𥕼皼𢙬𪱓𭞏𭠍울𡪺𦜦𗅹𣊳𡺚㋀𘅿𦗷꿶𧽄믘𘘕돰襵𡐗𣍿姶🠠𠓐𤉺⃟𮛭誒𨷂▣𐆕𠭯쨕𒒬귴𤺡𛋈ꍭ𥀮𨨕ꥯ襾𮧹宼𝟊ꃃ𣰋𥠛𘆋𣮹𝂡髱륭𗚧ⶨ🚫𗉙𧙞𠒠𠱰짟ᠻ𞺺䎵𮤡𪅖𑁆𥢹𠞌𡚔ቺ🨲󠆜𭙞냰㩺𠶲𐝈ﬞ𐩡魆𦿑𥄈𗻊㘱𖤈𡔴𬍜𤴋𝣁꯷醮𧞡螀𝁹𢷶ۮត⠩췺痱芬𞋳𖽲𬪟躳⏩𔖣𭔯𨠚𦌛澦𑠵𛇢梒𦲵䤟㺘𡵷🔁𬟭𭸬𑲇𪂁𗏠𨴹𓋯𫁹𬻋ꢎ獆筍㿧𬭑町粁ꕨ𢥙𗉓𐌞𦨎嘘䓥贷䆘𡳁𢀍볣𑇧𪋣𬫛鶘𭗞秈𪿿🜑𘑣𦤊𥝰𩔓𬎥🥍瓹𪺗𪄴𫮇𡇸軜嬪𣕬𡉡𠑈៴僺ﲀ𠎙𮆃𬝊鬧宗𠕣𤜵䎊㴐𪆦𐛕𩱜ɯ㔟𧘪𤰈恕𫬿𣎽⟝𫬯枽⨥𥱙𫌛㿻𭦬𢅺𮙳𗻸ﴮ𗞗𤫩ﭕ𤋛䙴𥽼ꪰ狎𭏴𤃴𞠐𢠚钊ﷷ뎷鰘𗆠𡊵𪑟툆𠱇𗨐踐𪘯།썓愶𬳎뉅뗪𦁎𫎐𐀛蠓𦣁𨄜쳯𭗶𩢏𠟎✠𒅖ꙕ薗覦𥡌𩦽켐𖢖ﮞ𒀓𝥳𢔛䓸￡𖬭𪚯┲ퟷ鴳𣏇𩨶𥂸꘩𡨭𑀰𘫨㊭𐒃坛𒄬𤀩𗿚𘗟㾨𧀈ƣ𩔵裈𑗂𫹍췹𑊽吏櫆옼🍫𦎢𢣁ﳅꪟ𫪨𐡞𥹟뢢𐽐𫏩稛𭴫労㽩𝔶𘦣𢉹𠺂ោ뼬镋尣𨿍𐫖𧥡𤮋᩶𬌤䉖𥔇𦐐𩂭𨥄𣷳ꠚ𥑭㾉緇梱𢮘ࣶ𑨰恞𛈨ὒꚣ煻猰𦘓𭒲𭻛𭍛𬒺䠵𥀙谍댿𠵴𓈶ꜟ𡼇첌𮀙𧟐𝄸磝𭎪🛴䮬鰺𭶆𦋤𢓃𩮧𤧺쭬람뙋𬆀喍䩴𬝖𡜪鉄𨙄𬞀𘀮ઝ睙𒍜㚝𣧆𦐪𡙷𛲗哪𭟏厊訸𤅷𒃂羁𮗦뿥𩏖냀܋𩊤𘠒𞡮𘉈ꑚ宭ഌ𤴻W𭁌𣎫𦤌𐏉𑲵𬨉偗셗𐍞𡁚𭮃짍䵷𤜐眝𡵲𡖴𭭣𨟊𠀨𭖗𣵓𠡬𫲿𢰮𦎵𧡐𒉼󠆾𩸉忁謒𩨾𪞋𩙿฿烞𦘃몶埈홈𫩇엁𝃲扵𥱋𣩩𡿫𬛚𥿒𨩃𦂃谀𐠊⹂𘠂𪪉≹𫓱𤺻𪵆𑐔𬈋縥𫛵𪵽𪈤糐綿𤞳ㆋ珽f숭𢢛𘌁𛁢𗅠锽뜰㼾𡺕𦖦𭌎𠥭烷Ꚃ𓐮𤽠𑓑𬇛腸犫𧶝䭎⫘𩐝𭹅𫅶𒍠𨼳𩦑𦇜𤯨쟧𤐁롭𨡾𠯮𖤼𠔠◖𫯞𤁐𓄋跌𢅤ݿ梏𗬎𡍲𦘚𧱹𧹼鐵𥙘𡤆𭷍𬦢귃枒𨣍ﭐ𥆘𪼛𥅡궑𢗷櫑襘𮍽𣠵Ṣ跘狮喴𪳋놜䛇𬁣𦽔𨽛謶𥇍𩦥ί𫡊摊𪣲𠸴縛𗫙烅𩁨𮖔𢿹🛨⸬𧪿蹍𦻊𧳨𣆟𡼦𤩷𥯰❑𥁱剰ꨙ贈𡋳𠓄덆𫃏萧𥪡𬛗𧖇瞊𩃛𪢖㯚쓋熗𥗖穥냍킸𣂙𪊈𘒳𘏙榐ᐊ牜〫𦳶𭩷𨈫넭𛆈𨐛𐫙𨄮𩡃𝩑䡭𨒖𧏒𩪁㳮ੈ𭜝㗿秎𓀵𥸉冄𠘉𔗼𥅶𗡧𥽉씗𒌐枌𐂜𧯟쓳𢴴𫋁𤌮𬘰𠑺졗𠁮𡟥𦳅쵢𘋜𢣼𩊐𢒀𬩸𢂂孼㨎𠸂𢨍鱧𩃔컑Λ閎㫗瞭摉𘁫𪲋唇匐ꬿ𓐘𢣏𮭳𦝱ቸ𧲍≵𧕩㊚䙿錒遡𥲙𣳙ꚩ礹𧗒ზ𬙠𨑋͈𢯩ኖ𠪄𢡐㽏𥊘𤰭𡼖𔓻⧦𝔃𭭽𡌇𬸚𑄧轻𪠯銂𤠬똅𬸼ﮢ𐦟𖽐𪊽剕𘨍᳴𬵤𣥻涄𦓭𒐶𤲽䲙𨨯𠽷𭀫𥠭𧕶𨄹ᨲ𠳎洛ᓝ𑅑ዾ🨖헎𒈁𡁅璵🄴𐦓𩠉𖠟踭𭤹𥼺𨠧渗𝢊郠쑳𪺆𣔲𠓼𤦵绅𨼎𗣱𡭰𛰉𭃘ই𫑱𫚩䣥㯘𨞒壷𡓱뒑윙𑿒𡇺𫎌呼텫𓆫늽𧼕浡𗫒𗗾譜👐𗈒𠦶𑵥𫈄ᩮ𩆰備쮛𭞥𮪬䔋徶鵄𭇮摈ﻄ𫥎𫸍𨫗𓁚𧻉𗳡嘙물䛠𮃯𝀊ij𨻑준롒𪄯𤥍徳𪐇𖥆𨉤𨧇𒒻𡳫🌭𫖁𘃌퀅𤌋韅濆𨥢◝𢧮憉ᑩ캑𗱜𩋩떜𢤌㎺งփ먗𩞁𑣘𗦎𥄜𨣠婣𝅧𬔅⩋𮅦䚭𦣪ꈜ𪣠雴𮒹늢𝜆𝀔𥔚𣓒𡬚𩦮𥢅𦙸Ꮫ𧤁𗺢𡔪袅𨭐𠭨왛𤠿踠🔪𗻤란㤶춥⥸𗐩➨𞡸̷䙄𣎞휇𔒃𐐡≨긟𧬙𫛴䐀𢞶ⰰ𪁕ඹ𩁿𖨁㴮𗟃𣣆𡞥㏶굛𥣣𗋚룚𥅳𣿀𭛉𬣕𠠘𘁐𢀈⠝臑𢣇𥼅𤷠쯰𦉁𐚹刳𔔎푼𠑪̾㶥ԛ𮪔𫙎𢔙𡶯𬦁𝕮𮆧㇠𬫓磣)𨇹𨈋𩏦𩛖䩁菐듕파헆𫲮苇𝅮𠶦Პ𢬻𝧯ⱘ𣲇针幩奖劷𝀝𑘚闠᎕仦쒍𝦏𢻰鳜𖡣ᦚ𔒤𭄟𞲎𓇱傁嵃Ⓚ𤳺𩏵叫𪫢𫠎𘕰𫊂𔔫勺ᤚ栥𖢪太𨺕𬂫ṭ螇庒젦퐱ᘞ𧑾𪸍睹𬚳𪺕딻𣼛𫟛𮁘⎭🁨𗄹絖𥗋𪁬ᓺ𪉑𤏞𤧛ꎋ𗬆𫝄楲𨥝깼𦸡𭱾𫺧닭鱡𢖃𠝇𘛥𬟤穞䀷닎ﱈ𭅵𭹰𧊩𢅱뭲𭆴퐻魌⫖ḛ𛊯𝐾엷𡶟𖧖𗊯亿𐳾𪦶𪺥𩢈펗𞄲𦙘렳𮬝𢴚𪽤𡌟𦾾𝨪𨷷ꃪ𢵟𭵳𫻲𪱃兓𨜬𭣿ꕝ𧁬⩜🆜𨎼𩕞𝃣𡘠㦈妲쨚৴𫨨𣒴璡ၧ𖦆컾𣝠𗵖鵎۟𤩶𩤃𩾏ᯌ𦑤籆𧛳𫺗🚩𫫡𣻀𪍰䈈𥉥轫𩚢𘏕㴠𢹚𦀾𝛺㖇𫡡𮣱𫪒ツ焢𧅌孝𣙞𥍠𠟺𥅕𖹔𫵩𗦄衣𩉑𡏅个顃𢄳伌𛰰𞡧𠼃𝀨𫞾ꤻ医췣𦧼䅞𤳛𦤃𣗡륚𧙮킋🞏𩌄𧐉꥟𦃒𬕃秣𐢬𧗄晦猵霾癩𥾀𪋅𮆃𡎝𧜇𬀮𣽿𝍧𩧣𠕹𞸛⦺𩑻𦠕崮𧾅垊𓇰𓂡𤌄𖢞𦫃㺈朡🗔ᱰ𗡜辞姍𬕚𫂮楦𩿛蕙𭳲𨅭泶彟𘃏𠥵죨𬋖Ỽ𐙩𬡿湶뉙礹𡾷嶄𑙖𞣐ᕦ𭦅𨖦㴆轧㹂𗡩𗯩𩇬𘧕𭅥瞰𪧸𣚑𠙦𪙎𠦉𬃡🦑𑈕浮𢶧썉𩪮衴ŗ𛱳笛𩛷鄔𩈅𬠎𫒩𣑞갹𐰕텺🩪𑀌𗎧ｚ쵙鍀𪬞ᇏ㪴𢟆ꮂ𑒻ᅆ𩐾𭲩𝠰𢪗棍🝌◐𝜅鄐𮐏𨕆賅𨁁𤒹᱈𠱗𠒰𩀤昢ꉓ𝓝𨛍𥔭䜋𬆑𡐨🄗𛀺讒馳𭅎𨇔𦳦𒑜𛂀𪬒份굼𩜚ꘟ𥿂려䍭乎᯼󠇡績𥕀椓𣑥𬁋𪘺뢘尰㐚ᔰ𩙝𨋲뺛ۂ😈殍𨧻𢥏𩗔錐𞲥髂𗼒丕魻𪸤𠽻𮤀涋ꋌǰ솽퍷𨧞픆𤖽겲𥝆䒡𔓚𨦷㪐௮𪳾ﹴ犋𠪊続砖ཹ𛁑윇𐳔㾛춑𨟬𥞂씺𧾢𑚋𬿐黸𡬋𥰷𦯪𭛾◰䵥𠕋矖𣃽𮡩篏𭕰𠕝ḑ𥻣𫐘䖸ॖ蹩𦕎阷揿𬇱塛쏀썣溢𥗺ᔩ옚𠂥𧴼𬵻𣣭𬵗ᾓ𨛙퍪⯔𔕭瞈𡃆𥗆ⴱ𠠥𪥘𧿙υ𝅔𮟤𦼐𧩈𬊅𪂀𘞢𑧖𗥅𖢑髾𨌜𩚶廪𦫻𦩊멶𧴢瀘𨲠ڞ䂥䡨𫁂𢕄🐫嵲𐎆𪵛ꞯ곻𩋝𫡿𘌂ꕊ𝇂𦯸𡚶𠪇ꢔ𪍙𤇸𮕿𬠅𢽺祈𨠝窸𐙳𢣈𫮎䢡𫢝𨕶𒒛𨑴𗾖𫑏၌簷똍賧꼊𐨌𐐏𭯃𮏺𣖸𬊃鯵㫤𑅓캳𢁦𘗋𠸬𑑙摯𮢷ﭩ줚꽟🂹𨸇𑿯𩈌𡙣𗉮𠕔𤾔䡲퇿娳鑮𥮇𨏔ꕨ𖨑𬂳𐧆爱䖱𗈦𫃉𣿈𡛻𘍒𢋲ㅟ𣫩ㅄ𭱑𝂙圠竝ꮇ柗𦖡ꯦ𢴂𡍖棅𑈺𫡄꜓榘𤧷𭻪ㅭ𩘎𖣄𘒰牥嗺𤅎𡜮觧𦺄𩩴쟣𥩳𫄅𤣈筡身𮨟🌈𧃒𦷧𪬟ᶉ圄𭡶𤕬𨴁𧫮𥁯ｯ𨞷𧻨𨧋𪦄𨤻␕𐔍먜𠃭𦲸𨤠㿊췽질𩝍𭨽𝢈禡尵𦙿▫𐫇𫕐𠁅鰉漸𡤃𗢪ꬰ쟳𦎔𬿕쫰瘬𤇋𠓋𬩹𪨔𬸗𭿚뤆ᓀ⣳𘝮槈𡊯㠄㣤朞🙥𬞄䐎燓𮡄숵ℏ韏Ȍ𘌭𭊊𘙒𪡦䗇軛勾𧀚댺𧡌𩽆𥓸𤝅𭘳𪤚𘈥ⴢ𝂗𠄍𗴴⡸ᆧ𪐞뷄崍Ҿ𣾻𨏾𣡹̒𠪉俯븲𫉀𝖪垹敿૭픡듀𡓿㑔䌳𦒶𮑕𡋻𢛴５ᛥ𮄓沦𘣞𫭐𡂛𢪩𪢬𠽽논𭻧痱𐒕🤡𢪾𝘷霉𢞀𬈢𩂿𢛈耗𥑼捆𮬁𢪮㬘𬁜𣗓𬳽𒎕㩖𨥍𥀅뺯𣞗㠣𛊻𪮻㮺쵬绱㷊،𪉝嚍𥋺𨇬סּ𭇎ﺊ𧋜𨾇𒋰𦩾𝞎𗁒𢹁⡺橩䉏𥪾𝁤𨩕𣁬𐁄ꉣᕰꛓ❧菐𬜔𘊫𥴈𢥭𦏚䟄𢭲𑄁𦻞ﱸ𬜎쩜𮗦䪍𥵛𘤌𨁱뚋󠇃𐂎𭘑⍋𛋍𫗷𮫈𮋦꽴𬱶𥾿낳𑐙碡𡃃㆘𦵚𗡜𢚧𩻐𠧈𗌝𤦊㌴𥰺𘊿烌𭿫ਂ𢓩崽𮨋𩰌𭭉𫳉𨨸咞𔕰緆𑚸䫑ꈱ𪇮𩂯𫴉瑼˕猆𥺖𧃦穅炾𭼺𥎼㶎𫈗𤖻ᡏ魏𠛃驣𪧝ꟿ롛𛊂뭩𒓊𡙭𧚾䙻䱂𗚎𪅟笖⢠쐞荛懑⭍𡎉놢𩍼刔𭡍ά𣅾冤𣵷𦛹띫襂𫇎𦮋蜞𠉘㢟艛鋐𪢬𘇚ꪱ㊠𭇇暬𘍐Იꕱ𪱱𔕓纖괚𧣆𢓒𪻯ﾸ㌃룳뒎𫾟𨕿䏱𪩒𐽃럐𫵢㡠𤊦🧍𛀜勸𝥮춖仆𤭍𣀾솀𭹅𧻟薔𤃣𫱤𢩿さց☐諭𡞢𧲪𠃍𣢫褸𓌴𡦸й鉐ꆈ𑱨𩁓𗞽👇𠸐𘦶ﵣ㬓𧖘𞸻泳𤜝𨟊𐭫𫒟𦙛𫟋𨱄ム𠐨𔔭𑌯𭻜釜𪦳𪏝𤛙찛𛄖쳨𫫂𧚰𑵁𦡫𦥄𭌓𫷲㊠禙ꍠ埲𩀱䂵𫎋쏍잋𢩔𐚠𬤺𪏏𡱐𬟨𦀷ꄅ𫦃𤏀㼫𩒿𗽑핐𢱗𬏞𘇈𬢞횻𑨯積ᆞ⭥𑪋𨘐𓆹𩘫𭖢吖𮝵퐇𪭉𑶦舽𠍚𩝏ⴗ𥗾𖩖𐛙付𥻹𗂽氓𓄕𪋼𘎒𪊢𮫶𤰐ｳ𘂧𩄚ﻓ쇫㢖🔣厙𩁇陁𫮊𠋜𑆢𓄣扭𪔈𥸻㏬𤅮𭠓郔𪆀𨱟𪄈伾Ⅷ䋔騾忘𫶂𫷥洞𤀚𣫧𑂄⨿깓舿𗽫洁ᶏ췣폸줾𮇷橥𥇖𖧗㊉唈ᚼ鍈𢡑𬞌𩖓ﭡ㵾嶫𗰢𨷓𠊹꯴ⱏ滻𭅫👤𮛒𘄖盉𡿣鏟𫙡𥩘𡣑𧘵𤭈虔Ｃ𪵛𓉰芋韁𦞏𩻦𨵉킲鑞𩫢𬉉𠇝丟𤲑鴢䬇ॻ𭲭𐧥𫲻𭵢𗀢𨙋䃮𣅄ᑢᐱ𡉟𮁼𝩺鐵𧽓㵧᠂𤌹𦜃𭛓𘗁榽𠞎ꃃ𓊂𫹔ᱠ笶𨮵𢄹🙯𦕾ꮧ𒃹㣱𦁰⺋𠍫🕉𮎿𔕼䙊𩐰𖣰騛ᬨ𥒥𮇏醥𗨭𦓋𤱕次ꋀ𨖤𫓐󠅐𥅳ﱋ𭓿𭏵𫯨𩗏𗰨띍凴❒敃𮚤𪠼ꢷ慊뒱엒懞𧍌剳𩛥𡙝𦏴ោ佡ू𬹼ᲈ𮡲㇖𤬤흊ﳆ䦙㦙萗𩔣㋌ᵇ𡌮돣硟𦿃𗨾𪉽⫞𤳩拚𬮬𩂤疨캏鵧㎰𮡜𝅉𢎅ʕ𘚐䨆𫴓𢯟𭹰𮦓𞅈竺𣖙𠚓𤘆𨦬㣦𫠌芶砜𖼇𦒧𧋬𫻞⦑𪍭𪪫㫡횩囮𒀜焷蟥𢩣실𣫤𮁃開𣔵𗁊🖰𢠳瀶𝘂ᡒ𘈄슍洂𧐉Ⴍ𮭉𐍖𣶞𪦑꺓𩵤𝤒𐛤𑲁픱𪦅🌣𤽢𒇟𨜐醱䪨𗈓𝣲𣈛찰𬓎𛊖뷂혧𦍔麱𢌕𥻊𣤃넼櫜ᄀ뛾㙪𨘉𧃅툕𐠪𭷼𔐰𬙶𦐇舊ﭒ𢙛𞺈𡁫뫁黃桟괷毣ﴟ𬏵饖𮜺𮙥𠂇𩲩𥟮𨉠💐𦔚捗𩚥𩽂瓬𓀣𫵠㥾𗶫𧥎碓𠐣𗘿啨竚𡷩𥈼𓋔𨬰𧝃𮌮㟿𨳛𘃦𪐈佚𨉋𩅓𦴒𭫃銂𦢳ᙕ𩶂墤𦣦𨈎Ⱉ𖠛ꍸ𩊱𖼂ꑙ𠮼🥝𨲹줁𤼟𮠌𭮒𧵰𗴤𘌜쥧𑖁﹃𡕺𨛋🎭𝁗𬜹⣣𤖴𒒎㿠톡𣥻𤿷𘏟蓻𣘆押휂鱆㎔᪣𡦫魺𛉘𥍯降𤈶𝨜𗳣𪊑ᬬ𣶻𐊴좁𡟈⨻𣜓𨊼况迻氘⎃𧋸𥎊𧡓쮧㝬ｮ𐓱𬹭𐫶涋🛰𨹱𡋣𬟘𣉮璩뫪轭雸𤞗㪳𒆸훡萟𘌡獍𩮿𢉦룎𣆖𔐟乞賅좿麻𠶚𝤞𠥜𮟂𧄾𤊮𫵬諾𣓕燎㬌𝓧镕𝑿𓊟𥚺𨾣𠙮㉫🂉픪𑒃🨜𪨪㬹𮚅𮐫凚𤔩挕㙔𗥞봆𥮻𡷤𗟫𧫛𗀑𡥝𪸢𝝠𧼊鼨ꎏ𘪛蜨𗙁𭓎𞡙𗠫𪊁䣓𢩝𥰎鼚婅⏹꠹𦳛𝨸干醶쮀ꖁ𨪷𦦃啝렜𡧔𧥤𥕊鞵𣎔𡷟ⳍ𫇰🏰戂౺𗈌𣄱𝢈𔒒𓆏𒐦𭂔𠑌𒋅𦚢닽𤭩𬒁𨩰♲𩷥𬨅𩾱䇝𩑂䤓驃𫱛𝥎ᣵ𮏚㢒饊ꊾ씳၂䔨虥𥝎𩲠𩱃𨕯⁍퀓𡪔𥸓𘧉𧄑𫬎⽭𝌧笈짅䔒𡠔𢕰藨以𢙓𥘘䷅𣅉𢼏ꘟᓨ𡗎𩜜𧨀掩𮄻꽐䦄徹挚썆𔒷锜퓹छ𭺌𐐗炎𪔏𗄔𐨃燚❘𮇼𛉴𨎾𥎆𛆶𝈯𩬸𥟇歅ܓ덂𗳴𗘔밾🢪𧹇𬘘𞄍댓𛁭霏𢲩𠇤𥴲𩕭隍䑷𨓑𖢗禆𨃖𩏜ਜ𩏲粶𦏬稶𗢷瀞ᔎ獔𩀩䚛𧼍툍𬛜𘊪⭼𥲇尛𠏼𬖝됔𘌧𗓩𥟖鼙𧇰庛𡕨䗘𣒄;𦐪𔙁쌫屩𠀬➹𪲳𮅄拵岧麼𧟕𗥌𐴖𥋛𨌶𧲠庰𑊡帳󠆼🞰꿰𢖝𐰂𥫹늑𭒐謷𠰟󠅈𪹏䨈᧿御뱋ꥱ𘔳幥𣃻筣𞸢𡿮먄𬱔ᲀ◊𗔤⦚鬫镂𢜹ㄞ𭭩䍱𠹍䛵𧓋菨𫘪𪼠뮼𮁁禘惻ྫྷ𤲅𣒠𒊉ଓ𮖜𧟦𓀠𩯽뤧𛃮⃝ꕨ阅𨬇慓𭷠́𘝁𑚤𬩤𠟖𦙩𠦶ƚ𨧌𠐇𮛕𧛉鷉⢽𬀴鮖ъ𬴻𡎦𘈇𝇙𥾣뱵䞻𠼎𖣷𭖐ꊘ𦣠𡔲팵𡍝派𠗒𡱟ɰ𡉠෬𧢉𭿎ꡡ岝𭯪𗩟𦃕𥊍悌𨨉𐅵𤝕𥦄𐅦𢛘ꃖ錧𧮍놌𪖵𮞑愠󠆿𧡾𨿠痍㐹뵑늟𒅫𝗕𦿈𐰸𗆌𫈽𫭃𭽯𬐦𧂡𘒮ꥬⲘ𨳏蝦𢷯🪓𐅉𝁓𩠧𨩬ײַ䊾𔕝⧿鶈則𗁣ᷓ穟䵋𩌹𨡀𢸑𡀠臭🁔𫏒啈𦘕挓𭋹𗛏𑗜𥞽深두𥹐𥨲𫳃𬊛냵𠶏ᐣ䊜姺𪇌잝춲𘗫𗼄篰𦥧𪪭햣𮪁肝⬔𖼝槩𬦦𮓀Ḃওᘚ䫗水𢪂𧐏𠆚𡪶𪙊市玜½薸𓎊𦝧𠫆୭𨗻℠𪘚𤔡熫𠭴𢔥𩂐𩤹𗣒䗫𞴣𬬿𨕟㠩𫶔ࡅṈ𧞕𒈽𑣏𤻷毰𢒑𘁴窝𒐿𤙠瞘𠪼짦𝌡𑇍𭗌𬊍杻𠯇ￖ𬸨ᰠ軕𣊾Ჯ𮉩𭈼𤘶錜”𝐦ఫ𫉻🠒绿烴玥𤳵𡜷⥻𢇿㝋𬾷𦘢𫊉𢦊🆐𐚡𫐉⁂𭓧𨁬⼤𦄃𘧱𣵩Ꮭ割𭴴𗤼輞頟ꉣ𧽓ꐚ︑෯𔑪潦𠨘撡𭾁𢖝𦓣𘉊놋𝜣沊𭀀𗩃𧉨𨠉吚𡯌🕦忈🌸𐢈偑瀄𮮖ྺ🤃쿸呧艊𪺓𤮲𤉝𭷪𣱿魰𥯍𬢙ᝍ𦶰𣒧𘖆𣧹𮓝𩁩𥱺𘑢𒉳𦛟얥Ǚ𣃉龨𑅙꽯𧮖｡𭾻𫷁𠾳𠺬𫃈컥𠧔ጺ枳䄴𘦼𢰽傽𡺭퉡𨷾혮⾳駷爵𣋎𢑌暧𪗅癐𡙬𢓱⌻篳롮𤸟濇𗴴𨖴𨯗𖢽㠹暎◃李𢿋𮭮矚꠲꽡𢞭𮍚𩺐𡫫𩈆𫒑❬𣆱𒆷簣𪆱𫃠𡎲𫒚𫇐삿֟𠴉౧𧱵𫤱⩈𑌈𠞽𠅨𦤿𢥻𫮂𫉈𝜐鹚翺𫿢屩𠑎𩡕đ𣫑추𝌜𧷻𐎣𭼜顶𑂜𬵔脖𣅾𮮪𨇊𗦁펜㌔𓏑𢤺쾋ꕃ㞣𭹃𤶇𮂼飄𝘁𗼵ᓱ𩪉䞈㰟႖𠙠蚀侵⡜컣惊趼𭈠缧𫲛𪘙⟞巩𨄇𬴞⾪𬒁㏁莂𘗎𗱎㳑𭜲𢊴𞸔𧻆𑅆𣊮𧉔⭛𫐞𦗛ⶍ鼫𬯰ձ𥹃𝘵솷𗊋🍸䧷큓𘝽֚𦉺𫭔𫣰씓𘀿𥐷兟🠀🥩𥛽𧩳⼬𧩾𒈔📕骣腊𥃪⧰𡎏𘢚𡆣🝬𠃘𠍮𮍹𤭧𫸒࠽𥑟擠𗹜辯𤫒𢆡𫦡𧶒𨇠閶𠼨Ț滒𬵇𐠏〷𠰲ᙾ𣘔쟟𢒲𗑙䖾𡄍硞諤𭡤볻𠔥𥏽𭟫𠷧𨖛數𤴷𗅾ؐ𩃶𮙄𝨭𦀪隿𤣼桽𭹟𦍅𠺧🧝넟𪳴鴗𨎕𡊒𗑬𠋠𦵿媜𥤏𝘐𐡍𘀎𘫛𥱀ꥋ𪤩𦱝𢚋𣇭䥽輵翏𢚘𧭃𧗅⢛𪤿즺𛲙ທ𗐔𪁖蕪䠋皪㵍🦪𤫼𘉅𠵪鐴𢢯𭻍𫣜憪𡘯⏀辴𪪐㴾𪏍𦕀𦶦𢽃⨌즡쀢𩬫🄑𝂒諴רּឆ𐿥䡬購㈌𧿇섮偞╔𗮻𤢯𠡦㋘አ㥋꺢㸐𒈰𢓍Ꮵᒳ𦏗떶𨕯𛰿䶣釩𥎑𬢢𛉮𦕲ड군՞㈂𤎸𠺋𣚣𘂘𑓐㶶鐷𨽟𗦼𢓊𓇘𫦁𢵠춘危楩𨽹𤁌ꖬ𬈇𥯞ᡸ𡰢𤔻鶔ְ틓𫃣𥱷곓𠇰𠑼𧛨❬𭠒𤯰殈쌽𥒴䥄𒎓╿𠦫𥸆磻賥擺ቦ𨏗𑰕凐𨦏𦔧𢑪𪽂𭼇ﶰ𦻥𔖕⾆𠞕𡞾𨂬蓛骘１ᙇ𩑯𨤿𨾗𫗯ഠ𨁜𬊫𩼞쪐𦕶𗑗𩴭𗃵𭏂𮊪𥴕💜𥧴𨅏Ṳ𦶉𨚱𥦉𬵀🙀𤷛饲🗯昡𢍛𤥲🌸圖籸𞄞𢟯𧽓𠌡𪤱죊𘦃콻뭜毪𗪨玅𛱴𢮍焀𦢳屗伭𢡉𡥑ๆ⤅𘉌𐨕𡫐𫴶㗰氟毴⩋公𗯦餚𭂓ꦶ咐跅𩿋𩦈ƺ賢𗡘蠎⟨𬍕𥅧𓍣讄贕𠉳踳𡸶𐑾𮄝䄆𖮊⟌𡶀𡡱𥱼𒇶及⬠𠂇𝃂תּ棤𫥮𬗒𘩋黊䊪跇𣈘𨬥𦳸𢉻𮏇𪇳𩆖𬿸𬦦𗂢唡🙷ｹᮭ𣹰𤂓𓄈⋫鐁𭼔頚𣶩𡵠᷻慪봜仩𨡝𭩽𧄟甄𥕿鉸ጵ𒊠𗌗𤪎㦔𘥤𠄔𨮖懓𫧃뉽𖩣𡳪𬷢晹𢫑烋𣹝𤏀𐅵洖𩻏𫝛썐뇱𥻎ፚ𧳾𡳏䀭𤻢д𢝤𓆪𤁲𡅿𤞺盛𮘕ꑁ𤮍鑝𘐁𭄛𖤲𡕅𓉯ﭩ陣ꑇ᷹·𐔲𑻯롟𭠍麌𠅝𢟨僻릝𞋇媒먋𭟩🛫꫱涢𥈊𮯄ⱕ𦊩𥾽ힲ𖺂茘𢫶㑣𑀰𬯕ࢽ𦣤旌晗𤟚伡𠓗Ꮸ🈮𬔼𦙈𬺑𠫿𧿺凄ⷭ𫱀∳𑆶읋齨𦰿𢮝헾𮨋𪾕𡵟𦗸꿡𪰞鍎焅𡩞𫷆𒐐䀟绍𪄾𪰋ݷ誟㖵𨮡𓃕𡷅𪩘𢌋𡙸啠𗝐㒨𦾜𥫠腒𣝗𣆠𧊛㾟𖠞묾Ꮚ路󠇢ꖆ𦨏𦚞㋍州征𬹷牽𦠄瀵ꔺ𠒮𢊛𠢩𘒄𩁷𗱑ಂ놱𫈇𥩆ﾍ𝞆🝋㡊𫓹𪳞庖𭤛𫈖⿐챾𠰵㗓𡦐𡐚𑧌𥑖霔颻📀𖺋𢩮𭋀ీ𘊃𧝈鸞𭋏𢭆𠄯𠟆𩺨ᚫ𮒴𗚵𧑾熓𐑂𭏯𫒙𬨸𢏛𪄲庞삕💫𨎊ډ𧐔𭭃𬠏𨨂𑫏𤹺둜𖠥𣏘𬞚텎𘋧𡡥🅀𠼶𢣛柝𬭯𮟂ꄒ𠰺⢓ꗳꇁ𦡙𐑄㪾𔒿꼼Ƕ𭐦𗒘捍𨷮𐚲𫪘𮨚㮠䫳𨻍𩄚𪚹ᔖ𝓇冯𪱁𧑗𨥴輭腪᛬𝡩Ὄ𩖇枥𫛸⩶۶𠂂Ἁ㉆㶕䁕𘎪蘠闦𨈑礊𫄹𩰑𡬩舙屼뙑𡕡𥆘╢𗁅𦴨𡨃퍂𦬘磥籦㜈𬥬𡬋Ἀ햻㏧먚꒹𨊄𩖉뗥𓁱𥆬𓉤𘇠⑱𖠾𩐽𣍐𠪚𗍃𨁾𠠇𧁙𤡾𤪞𩺀𦆱ꤻ𭍮𛀟𤧴⠠𤓰𪹙𧜭𣘩셚𤏎𗖀𒇻𫯍𨤺𢿏뮖⋽𘇪𥗉𬢿𤮺𤥽𭌅僵𡕢낯蕻ۿᕑノ𭻰𠼌𫁗𠘺𩻜ᚾ澳𫞨𭖱𥁵䖦砏𤠀菢𩓴𥬖䚷𞹏𥔝𨬨𛆃煠𨝱䴬𥃟𗥿𧍱㜬𦁎឴𬾓𗓒젢𠎗蠟︬𬢗噵댳𢍴ꡇ𭺶煠𫙫⛅ご𮉥𠦘𬻩ಃ슀Ⰹ𭟘𓏹骋𩉕揵𤔓𐂠𗹃𨟛⾸̓🅞𡷴Ყꂀ𐄇𣿏〒쨖ⲽ싃𓎪콳𗗠ꃨ𭴺𤹸⨍𮅁𣸙𑍢𘩭筃裬𣭩𔔢𫸹ቘ𑵄𨢴𤻿𤓄ꉬ裡쒁㘍𢒮𢐃𢓛㮏쒅𩕜𣡰뢬嶇륆𥱮⭥𭅗䍛𦸕𩊚𨽂𐫲꿌🤆𭘝𪻋𢷬𦼁𓏵痆𨸘𗫭𡛢𠈗𢊱𨜶뿻𪭶㣺풇𘙎𑛅ᣦ𡲎𥘕𦌛ྃ᠐圫𬭔쫙𣔳𨻲𡐏𓅷𥬮숔⒳🅡ꥰ焍췱𦾳閣𢨃𧹻ゲ砉♔픚𫓘╥𨪫𧔝⦼𦸸ﭟ🃜ᔎ镪𤹟샸𤄉🥔𣨶脾𥂔팶쥼笧𡶚𐂨𖣱ꈕ봐𤢹𢓳𤞋𩢹𭣣瞤𧂹𮡛𞢆𩳏𡽜𮭻ݷ𦔶𥯦⚾蕊妪𩥺銤𝁃럏𤱓𒈠𠪓ᣌﰭ⊂蓱𠚭𦏙𦺎ﲪ𨞈𮆥𗔠嘘益𬝶𥜙Ƨ𮠐𮗘𪩕𧏰︮𤎽𣗾𨳙𢦧쏵𧞺𣨵𢬒𩺳⩜𬶚𧷂茉趼𪥋ퟔ𗽧𗽙翫𮄷🙦𤊏棎𢨣𐿭𢟞녰𢈫𭍅𗫪𤼾𠶬ㅥ𘂘𣜨𢘗㑄֞画Ḏ𥔓𛆃𑄓𥧗𤤠𡴟𠧠𝔛𦆖𢠵飧𗧐𬺰𪘕𤝀𡚼𨜸𐃃𔒓𪁷딍Ӱ𠂊쏨🍁᩻𤷺૾օ苕栅𐃳૪𡪊𗥒裃𡵐䮲婢𥡤𡃵ᙫ𪋫憹䉠풽྾쐳𫷝𤀲𖦛煹𖣐⤕🦻豴𨴸𘆴𧛟祏𪕋쒔🛩爩礼춛𥈱큃殽𤛟뉧𐳱𢤛㵤𝛣𝚠∱㷐𤤲㰸庰셅𫯇𦜇蕷𢛅𛋴𧛇𮒵𐢩𣋴⺍𦮌𫒞𝂘織𬗿率𤖱쐚𨿥𥉬澃ඒ𢚬𡢹㤀𤤘܌康구硾뻫轀圮턧䆨𫷎𠲠𧐋焻𗣁ႇ𐹩네惭𗏨𨉲ኺ𮛯𝑪𐎤ᮽ驈흸䃫𪸺佀𠞓𠺌𩝚巈溄𣦔娓姑𩘩𗈼⋃ℒ𡷥쒯𢜙𣫁瞛𢄰㟁茰묶𝂫𑱁̅汝𠌆𓊩𮞯ֶ駄𧢛뒃𬩜𝥦𩋗ླྀ𑁓𖦝𩰈𢣊𝟅ⷭ𥘐푞𭊇𢞭𢀄𗎍獚홿𦜺촨ోᓎфꋠ𪎎𦡨𦬶㒟𞺡🢆璢𨙔𒔭ቭ隱𩣘𤭄𩧉븣揬𢹚햻᪬殭䒚𮍱𩽄亀Ỗ𡳐콄붃𬽅䴨ඞ𫼜𢾦𘕽䏐𑑇𮣹䴒𛀳𩢆𨿓أ𖬒𝛷𭁣𒇙ᦏ𩛒𪘹⽀𘐆𫚯ꉬ𪳔阻礗𘋑㉨𨶏𤪀쿭𘩛𠏇𗢈蒿艮𔗄𩺲𪗃𘍋工𣆭𪭸𦾷𪚈饐𬎰𝂦𨋭𑱼𪯅𫉷𬤌懲𩿉絞𫞴𑦣𥄜㌫𩾯椌𥲬𑨱幭獺𧧻שּׁ𨐯쳊𭥣𠆻𠳬𩆜釂鸘𨻪铮𫊷쾙😧𐐖𢏡咣𩯿𠡛噫苶㶈𡡆𡠛𠁉𦛲𤞌꾙𗺕𫑕ꧾ𢉗㢂聋۸𡚏𢦨𔗲㿦𝤊𨧯𢤔떩𘌻豞👜𭄮귨𤰮萑𢃯軳⡁𭫿𦁃붸𝍰𩘀𣦾𦩼𘕝𐪚꾿🚭㉄䷲῭폦𨞗𗚄豥㚟𬚈𡽊혾䀸𐀽𪌧乏𭼭𦔁ꏑ𢇠𭩽錪㽹𣳵秪ퟗ㵪𬉝𪵦𗈴𥹔𤣷ꂊ𩰫𨗤𦤂풲ꍰ⅘𪏃𥼋㚶迻𗰅𭪙갽𥊑𢍰𠜆␢𖫵𦧙ൠ㕂𤾀𥴎𘙊裏㲮𢹀禈𨘶ﺛ𧵐𨯌𦧀𦯐ᒲ𣦵𡷧𧇖𠰂𥁵𐲉ꥁ䴢삭𥇽𤧄亡禈ꠑ𝑃𭲝dž셝𑖢㝉𠤸ⷥ獺𠒪𫀜𤗋🆇𫶓䊪𛆜𒁎𦖈딢풚赓𡙷属痑𪺔𫖷𤂅𝝓𓊗ꏽ𗖘𠯳㹚𠴹💑𦸚𢧇㌡𘀽𒈆𥼃𤧶𨳖𤮋⸋𪌡疢熮𤀆𛋉掙𦰏𮁠䥩𭭅鷆菸𩽉ة𝔾𢸂𘧙⬘𭢈饢𩄜Ⴘ㽍ꁼ𢮔𧆕㰘𗙧𓍊甸㎎쐟𧌃𣢸𬶡𭜧𦤨㚶𥣈ꘟ굙힇𪥃㪪䁇隶𩵊𡅵鿋𦺿𗜇𨎥𥵬𡢭砘𗶆𗌠𭙠˿𡸆𫡝𫎦㩰𛇙迗݄𬹎𦘵鿦𗿠𡼼毣䫥𡢢㼻㪚𥙧𢁄𐬎痨ᄴ𡳠斱𩆶𠴘懇䯄嵭𭛬骱홅豖햡𩢑ᦷ𘢲𦲡𑖚𗼖䛔乃𪾹ꚁ𖧧䴭ࠫ𭲞𫝟寃𫊛𤆔ヅ𩃑₆𮡋𝓽𞤑匷⫚𫙈癧𬀵𔗿𫺲𭘴𣊨𝖶툼𧿣塇𣍠𡂼𖼕𧇷쬫𢏙𞋦𭏫𐨐椋𦄍쬺𫹣嗎𥮆壷𨬾𣥳𫊛𫝒𔑋媘峰𗶫𣚁🖞䙻𗌒拝螐钶ፎ𨠔ሠ퉀𦎳🏏㝱𥰿ܙ𮍏𥤪𬔊𤭙醋𪔉ᜀ兀ꪐ𣇿逆𨲚𢲲̸䈸𮃸𦌢𝄶晴Ʞ𮁻𧟪𭪞删𩹲𮆄秶𢷦舄劵מ𨴪玷䆽褿𝕬𮩰𩦜嫛份缐𗉉鬦𔓪𨽌𡠃𭨏𓊌𬟸𥻩值𦊔ﵱ𣙲𐂥𞴉𧏫툊𫄣𣢟𣬛𐒝𗱕냟𘇿𮭶𪨤𨲴襯鑬𨍩𣅛󠆲꘨粮嫳𡇭𐎐𬖓𘧃ᆴ楚𥟆㾖擂㉙𭰠嚘뎰𪛏𗍋𠔮鞿𩲆𒅵𡃟𥝆𑗅𔘨𠖩𬇫覻፰𪂳𬪙𦬵𩹢컕𢬉𗮈𑖹鸔㧙馶𘌅餣𧙠窫𣌲𨭨𛆒箃𠟂㨠敂𤢕䰬㫕𫆤䈂秛𡌾𗓌𢅬𪄨𦋤쳼𥎑𧒇ᨾ㡎嚥𡰪𨐭萘𐧉鷫𦒤𦎗𫕧蒄𡭍𗑃𐽓𫬈퐾𭉙𩸺𗅌箋𥽞𨾯𤊁𦑠𗵓蹮壃𠮉𝁗𩭴𩧣눲𨪮࠴𫆭𡞫ꂍ縒敯𧒳𘕃𫔒𐭅㬻꡶𭿉黉𣩤𪜖킎𮉕𬎲儅҄𪽺႔ꄖ𨧋熧㠾𫹬ﳧ𗔕쁟ﴽ環𔕰𢟹𡴽菎[𧷬𩃁笢𐘭骨㩗ゆ樶좄蕰𮮜ඩ𬮜맞락𣯢𖣫-𤸵𠷶🅺嗁𝇏𣧿🈁𒂾ℱ豐𩩰𬽌糼𨯇╗𦉎܋𘗳𪕌𮓺㗺𥅆킪𨼽𡒰𝕣𐤇瘃𘓏貼𡢫𠱡𡭏ǜ𭝯𩁴죥𮉳𫱬𦸠𧲠顨𝔚𬶨알𪒴纮졄𤗒酸粼𥏿箔𧼄𮑆𤇶𬥹ꐎ𗔜확𧞜🗋𗤫𨡌𠑼鈼𣨚𦲦逖𭳄🗵鞲ﮊ겘𨫩ꛨ𛁟𨚘𦽎ﶸ𭺊⇾𤢶𫽏덵ൢ絪𐠯𢬌𝀒𣬣𒌱𦼁𥓆𨓌𨹝𫔉諽𦙲𠛁𪒃놥絯䇿ⰲ⺛ꓮ厸𫍝𡚥𗳘𮅄𭟈헱𥧣▻촉鴻𝆝𖣖𠡄󠆟毳虙𤘵ʡᮠ𖹴템𘄣𡻨ꂉ𡎷😿𗺭𗘯𧂥먐恃㬙𗨂𦅭𭃃𢯆𧸜욛뚌𨇯𩒩𥳴𝄈𨐝㴚ﳶ𫹠𛈪𠟊蓀𖾀䤖𫐔𩪾鈫𝟒ꯊ彦𐊢𧗔姕鍠𦀎𦃐𐀑𧍸𮚧𤃁𣿔鑅🠣𗖠홲펜𑀣𢰝仠𬎶꼵촫𪈟𢞡𤌝𢶨ợ𭬔ᮿ𣤗𥨈𬞫콄𝞫醊𬵠폯𡥭𠐾㋸ቿ𭾖𡢎𩲞𣫑豍𨺒箵𫪧𗕢転𪹼 | [
"45290401+vmlankub@users.noreply.github.com"
] | 45290401+vmlankub@users.noreply.github.com |
be6b93eb898ea5b5c820ed8f45f191bc57b10022 | 781964e465e1d49b3cd44eb69a333474916d159b | /gr/gr1/utl/shader_param_data.cpp | 0efc0909e0a60ef378b0ea889276b8347921f5d7 | [] | no_license | aaalexandrov/Alex | 3742d25c6d30c80c7929631b394e1387028edc01 | 7c7aed6cb3e5897fe91cf324c79425042ba3488a | refs/heads/master | 2023-08-19T10:58:54.633930 | 2023-08-16T23:27:10 | 2023-08-16T23:27:10 | 3,391,809 | 2 | 0 | null | 2022-12-01T21:42:36 | 2012-02-08T21:55:15 | C++ | UTF-8 | C++ | false | false | 72 | cpp | #include "shader_param_data.h"
NAMESPACE_BEGIN(gr1)
NAMESPACE_END(gr1) | [
"greyalex2003@yahoo.com"
] | greyalex2003@yahoo.com |
8ecc8602a07457f89e198e59286c5e14ad62e4d5 | 0dca3325c194509a48d0c4056909175d6c29f7bc | /sas/include/alibabacloud/sas/model/DescribeDingTalkResult.h | e913dbe4002c7852464de98a3cf85ba68d5ba7e5 | [
"Apache-2.0"
] | permissive | dingshiyu/aliyun-openapi-cpp-sdk | 3eebd9149c2e6a2b835aba9d746ef9e6bef9ad62 | 4edd799a79f9b94330d5705bb0789105b6d0bb44 | refs/heads/master | 2023-07-31T10:11:20.446221 | 2021-09-26T10:08:42 | 2021-09-26T10:08:42 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,861 | h | /*
* Copyright 2009-2017 Alibaba Cloud All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ALIBABACLOUD_SAS_MODEL_DESCRIBEDINGTALKRESULT_H_
#define ALIBABACLOUD_SAS_MODEL_DESCRIBEDINGTALKRESULT_H_
#include <string>
#include <vector>
#include <utility>
#include <alibabacloud/core/ServiceResult.h>
#include <alibabacloud/sas/SasExport.h>
namespace AlibabaCloud
{
namespace Sas
{
namespace Model
{
class ALIBABACLOUD_SAS_EXPORT DescribeDingTalkResult : public ServiceResult
{
public:
struct PageInfo
{
int totalCount;
int pageSize;
int currentPage;
};
struct ActionListArr
{
int status;
std::string groupIdList;
std::string actionName;
long gmtCreate;
long gmtModified;
int id;
int intervalTime;
std::string url;
std::string configList;
std::string dingTalkLang;
long aliUid;
};
DescribeDingTalkResult();
explicit DescribeDingTalkResult(const std::string &payload);
~DescribeDingTalkResult();
PageInfo getPageInfo()const;
std::vector<ActionListArr> getActionList()const;
protected:
void parse(const std::string &payload);
private:
PageInfo pageInfo_;
std::vector<ActionListArr> actionList_;
};
}
}
}
#endif // !ALIBABACLOUD_SAS_MODEL_DESCRIBEDINGTALKRESULT_H_ | [
"13862149+AxiosCros@users.noreply.github.com"
] | 13862149+AxiosCros@users.noreply.github.com |
822848d09f226ca8d0ac440383491eba5bd97111 | dd3d11771fd5affedf06f9fcf174bc83a3f2b139 | /BotCore/DofusProtocol/QuestListMessage.cpp | 7476077e60a0198df201cd141beeae56c7279a22 | [] | no_license | Arkwell9112/arkwBot | d3f77ad3874e831594bd5712705983618e94f258 | 859f78dd5c777077b3005870800cb62eec1a9587 | refs/heads/master | 2023-03-17T12:45:07.560436 | 2021-03-16T11:22:35 | 2021-03-16T11:22:35 | 338,042,990 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 2,254 | cpp | #include "../ProtocolTypeManager.h"
#include "QuestListMessage.h"
void QuestListMessage::deserialize(ICustomDataInput &input) {
this->deserializeAs_QuestListMessage(input);
}
void QuestListMessage::deserializeAs_QuestListMessage(ICustomDataInput &input) {
unsigned int _val1 = 0;
unsigned int _val2 = 0;
unsigned int _id3 = 0;
QuestActiveInformations _item3;
unsigned int _val4 = 0;
unsigned int _finishedQuestsIdsLen = input.readUnsignedShort();
for (unsigned int _i1 = 0; _i1 < _finishedQuestsIdsLen; _i1++) {
_val1 = input.readVarUhShort();
this->finishedQuestsIds.push_back(_val1);
}
unsigned int _finishedQuestsCountsLen = input.readUnsignedShort();
for (unsigned int _i2 = 0; _i2 < _finishedQuestsCountsLen; _i2++) {
_val2 = input.readVarUhShort();
this->finishedQuestsCounts.push_back(_val2);
}
unsigned int _activeQuestsLen = input.readUnsignedShort();
for (unsigned int _i3 = 0; _i3 < _activeQuestsLen; _i3++) {
_id3 = input.readUnsignedShort();
_item3 = ProtocolTypeManager::getObject<QuestActiveInformations>(input, _id3);
this->activeQuests.push_back(_item3);
}
unsigned int _reinitDoneQuestsIdsLen = input.readUnsignedShort();
for (unsigned int _i4 = 0; _i4 < _reinitDoneQuestsIdsLen; _i4++) {
_val4 = input.readVarUhShort();
this->reinitDoneQuestsIds.push_back(_val4);
}
}
void QuestListMessage::_finishedQuestsIdsFunc(ICustomDataInput &input) {
unsigned int _val = input.readVarUhShort();
this->finishedQuestsIds.push_back(_val);
}
void QuestListMessage::_finishedQuestsCountsFunc(ICustomDataInput &input) {
unsigned int _val = input.readVarUhShort();
this->finishedQuestsCounts.push_back(_val);
}
void QuestListMessage::_activeQuestsFunc(ICustomDataInput &input) {
unsigned int _id = input.readUnsignedShort();
QuestActiveInformations _item = ProtocolTypeManager::getObject<QuestActiveInformations>(input, _id);
_item.deserialize(input);
this->activeQuests.push_back(_item);
}
void QuestListMessage::_reinitDoneQuestsIdsFunc(ICustomDataInput &input) {
unsigned int _val = input.readVarUhShort();
this->reinitDoneQuestsIds.push_back(_val);
}
| [
"arkwell9112@nowhere.com"
] | arkwell9112@nowhere.com |
12de0f42c0146fa9acf4ef6fb1f2e4aac7680c81 | 5e6910a3e9a20b15717a88fd38d200d962faedb6 | /Codeforces/Contests/CF1285/d.cpp | 7814a8e693cf071b8528239e1e586adc4580ce9f | [] | no_license | khaledsliti/CompetitiveProgramming | f1ae55556d744784365bcedf7a9aaef7024c5e75 | 635ef40fb76db5337d62dc140f38105595ccd714 | refs/heads/master | 2023-08-29T15:12:04.935894 | 2023-08-15T13:27:12 | 2023-08-15T13:27:12 | 171,742,989 | 3 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,111 | cpp | #include <bits/stdc++.h>
using namespace std;
#define pb push_back
#define mp make_pair
#define sz(x) ((int)(x).size())
#define all(x) (x).begin(), (x).end()
#define endl '\n'
const int N = 2e5 + 5;
struct node{
int ch[2];
node(){
ch[0] = ch[1] = -1;
}
};
int n;
vector<node> tr;
int dp[N * 32];
void insert(int a)
{
int cur = 0;
for(int i = 29 ; i >= 0 ; i--){
int c = (a >> i) & 1;
if(tr[cur].ch[c] == -1){
tr[cur].ch[c] = sz(tr);
tr.push_back(node());
}
cur = tr[cur].ch[c];
}
}
int solve(int cur, int lev)
{
int& r = dp[cur];
if(r != -1) return r;
r = 0;
if(tr[cur].ch[0] != -1 && tr[cur].ch[1] != -1){
r = (1 << lev) | min(solve(tr[cur].ch[0], lev - 1), solve(tr[cur].ch[1], lev - 1));
}else if(tr[cur].ch[0] != -1)
r = solve(tr[cur].ch[0], lev - 1);
else if(tr[cur].ch[1] != -1)
r = solve(tr[cur].ch[1], lev - 1);
return r;
}
int main()
{
scanf("%d", &n);
tr.pb(node());
for(int i = 0 ; i < n ; i++){
int a; scanf("%d", &a);
insert(a);
}
memset(dp, -1, sizeof dp);
cout << solve(0, 29) << endl;
return 0;
}
| [
"khaled.sliti@supcom.tn"
] | khaled.sliti@supcom.tn |
05b91f9856143a356bf6924fa524c6a7614af4af | 97eb17ce805e762982c1b09647ea3f251fa0ea0b | /HoeGame/include/hoe_app.h | 5c051fbc366a76f3e936d05652c1926dc0a72c65 | [] | no_license | HeimdallTeam/Hoe3D | 8ca6d434b298773abc3d8c324822df3b97f5d19a | 62c6547ee5751ca6da31fa5379c6a0b78bafe5bd | refs/heads/master | 2021-01-15T14:24:35.777027 | 2014-10-03T23:11:14 | 2014-10-03T23:11:14 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,688 | h |
/**
@file hoe_app.h
@date Oct 2004
@version $Revision: 1.11 $
@brief Hlavní aplikace
*/
#ifndef _HOE_GAME_APP_H_
#define _HOE_GAME_APP_H_
#include "hoe_vars.h"
#include "hoe_console.h"
#include "hoe_engine.h"
#include "hoe_fs.h"
#ifdef _WIN32
#include "hoe_win32.h"
#endif
#ifdef _LINUX
#include "hoe_linux.h"
#endif
#ifdef _MACOSX
#include "hoe_macosx.h"
#endif
BEGIN_HOEGAME
/**
* @brief Hlavní aplikace
*/
#ifdef _WIN32
class HoeApp : public HoeWin32
#endif
#ifdef _LINUX
class HoeApp : public HoeLinux
#endif
#ifdef _MACOSX
class HoeApp : public HoeMacOsX
#endif
{
protected:
HoeEngine m_engine;
Console * m_con;
HoeGame::FileSystem m_fs;
static CVar m_width;
static CVar m_height;
static CVar m_fullscreen;
const char * m_lastError;
virtual bool LoadEngine(int sdkver);
virtual bool Frame(float time);
virtual bool Frame();
public:
static CVar m_enginedll;
/**
* Kontruktor
* @param con Konzole hry
*/
HoeApp(HOE_INSTANCE,Console * con);
/** Destruktor */
virtual ~HoeApp();
virtual bool Init(const char * title, int sdkver);
virtual void Run();
virtual void OnSize(int width, int height);
virtual void OnPaint();
virtual const char * GetTitle();
static BaseConsole * GetConsole()
{
return GET_THIS(HoeApp)->m_con;
}
static IHoe3DEngine * GetEngine()
{
assert(HoeGame::GetHoeEngine());
return HoeGame::GetHoeEngine();
}
static FileSystem * GetFS()
{
return &(GET_THIS(HoeApp)->m_fs);
}
virtual void OnUpdate(float time);
void DestroyEngine();
};
END_HOEGAME
#endif // _HOE_GAME_APP_H_
| [
"gejza@gejza.net"
] | gejza@gejza.net |
cd7c9318415e081cd68d029a080a859be4347bd0 | 7b7c1d9dbb9d2da7be522ea3b858066d7c527845 | /Codeforces/1327B - Princesses and Princes.cpp | fa50c33e895b52f0f68568260b8cb9b512d80bfb | [] | no_license | cyyself/OILife | 97893cf7e1d3de61517b0ddd5e6a064700886667 | 9190e45c6a660bf2e1db6d08d84ddf26eccd85dc | refs/heads/master | 2021-06-03T10:02:33.627522 | 2021-04-17T09:27:49 | 2021-04-17T09:27:49 | 101,148,852 | 12 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 656 | cpp | #include <bits/stdc++.h>
using namespace std;
const int maxn = 1e5+5;
bool visl[maxn],visr[maxn];
int main() {
int T;
scanf("%d",&T);
while (T --) {
int n;
scanf("%d",&n);
for (int i=1;i<=n;i++) {
visl[i] = visr[i] = false;
}
int mt = 0;
for (int i=1;i<=n;i++) {
int k;
scanf("%d",&k);
for (int j=0;j<k;j++) {
int t;
scanf("%d",&t);
if (!visr[t] && !visl[i]) {
visr[t] = true;
visl[i] = true;
mt ++;
}
}
}
if (mt == n) printf("OPTIMAL\n");
else {
printf("IMPROVE\n");
int l = n , r = n;
while (visl[l]) l --;
while (visr[r]) r --;
printf("%d %d\n",l,r);
}
}
return 0;
}
| [
"noreply@github.com"
] | cyyself.noreply@github.com |
01205228e12cdc665985113bb57dab01ee348030 | 9f520bcbde8a70e14d5870fd9a88c0989a8fcd61 | /pitzDaily/176/phi | f7d3b01c614bafc64b902c1ce2ba547edeb0e870 | [] | no_license | asAmrita/adjoinShapOptimization | 6d47c89fb14d090941da706bd7c39004f515cfea | 079cbec87529be37f81cca3ea8b28c50b9ceb8c5 | refs/heads/master | 2020-08-06T21:32:45.429939 | 2019-10-06T09:58:20 | 2019-10-06T09:58:20 | 213,144,901 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 233,339 | /*--------------------------------*- C++ -*----------------------------------*\
| ========= | |
| \\ / F ield | OpenFOAM: The Open Source CFD Toolbox |
| \\ / O peration | Version: v1806 |
| \\ / A nd | Web: www.OpenFOAM.com |
| \\/ M anipulation | |
\*---------------------------------------------------------------------------*/
FoamFile
{
version 2.0;
format ascii;
class surfaceScalarField;
location "176";
object phi;
}
// * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * //
dimensions [0 3 -1 0 0 0 0];
oriented oriented;
internalField nonuniform List<scalar>
12640
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2.41356640048e-06
2.50675700325e-06
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8.16651268106e-06
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1.06345673887e-05
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1.52429552823e-05
1.97856906742e-05
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-3.80085451739e-07
)
;
boundaryField
{
frontAndBack
{
type empty;
value nonuniform 0();
}
upperWall
{
type calculated;
value uniform 0;
}
lowerWall
{
type calculated;
value uniform 0;
}
inlet
{
type calculated;
value nonuniform List<scalar>
20
(
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
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-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
-0.000625
)
;
}
outlet
{
type calculated;
value nonuniform List<scalar>
20
(
0.000499496800657
0.000626495993648
0.000709220947868
0.000752919550836
0.000773884546586
0.000780428753039
0.000772485857554
0.000757461688682
0.000740396360162
0.000720703859556
0.00069843659666
0.000673454641238
0.000645562373797
0.000614475942096
0.000579780377067
0.000540847252551
0.000496437476171
0.000443094114043
0.000374746152543
0.000299671349794
)
;
}
}
// ************************************************************************* //
| [
"as998@snu.edu.in"
] | as998@snu.edu.in | |
fe5757ef59bf7cae57c3c606cef52ae317188873 | 77ee25aae73961b5abdb9d742dd29459b8816d41 | /cpp/platform/impl/windows/generated/winrt/impl/Windows.Services.Maps.LocalSearch.1.h | 31d3b739ae5a888cc6c353164430e08554402fc2 | [
"LicenseRef-scancode-generic-cla",
"Apache-2.0"
] | permissive | ciaraspissed/nearby-connections | eabaff88177289d3b15274fc4ed2e745fe022802 | 233c5f533771c4004bac87a49cbc9f0137d80bfb | refs/heads/master | 2023-08-12T14:43:09.092255 | 2021-09-16T20:18:26 | 2021-09-16T20:19:03 | 407,859,947 | 2 | 0 | Apache-2.0 | 2021-09-18T12:54:05 | 2021-09-18T12:54:04 | null | UTF-8 | C++ | false | false | 3,533 | h | // WARNING: Please don't edit this file. It was generated by C++/WinRT v2.0.210825.3
#pragma once
#ifndef WINRT_Windows_Services_Maps_LocalSearch_1_H
#define WINRT_Windows_Services_Maps_LocalSearch_1_H
#include "winrt/impl/Windows.Services.Maps.LocalSearch.0.h"
WINRT_EXPORT namespace winrt::Windows::Services::Maps::LocalSearch
{
struct __declspec(empty_bases) ILocalCategoriesStatics :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalCategoriesStatics>
{
ILocalCategoriesStatics(std::nullptr_t = nullptr) noexcept {}
ILocalCategoriesStatics(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocation :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocation>
{
ILocalLocation(std::nullptr_t = nullptr) noexcept {}
ILocalLocation(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocation2 :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocation2>
{
ILocalLocation2(std::nullptr_t = nullptr) noexcept {}
ILocalLocation2(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocationFinderResult :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocationFinderResult>
{
ILocalLocationFinderResult(std::nullptr_t = nullptr) noexcept {}
ILocalLocationFinderResult(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocationFinderStatics :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocationFinderStatics>
{
ILocalLocationFinderStatics(std::nullptr_t = nullptr) noexcept {}
ILocalLocationFinderStatics(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocationHoursOfOperationItem :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocationHoursOfOperationItem>
{
ILocalLocationHoursOfOperationItem(std::nullptr_t = nullptr) noexcept {}
ILocalLocationHoursOfOperationItem(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) ILocalLocationRatingInfo :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<ILocalLocationRatingInfo>
{
ILocalLocationRatingInfo(std::nullptr_t = nullptr) noexcept {}
ILocalLocationRatingInfo(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
struct __declspec(empty_bases) IPlaceInfoHelperStatics :
winrt::Windows::Foundation::IInspectable,
impl::consume_t<IPlaceInfoHelperStatics>
{
IPlaceInfoHelperStatics(std::nullptr_t = nullptr) noexcept {}
IPlaceInfoHelperStatics(void* ptr, take_ownership_from_abi_t) noexcept : winrt::Windows::Foundation::IInspectable(ptr, take_ownership_from_abi) {}
};
}
#endif
| [
"copybara-worker@google.com"
] | copybara-worker@google.com |
1ed74ed9b743050afa0124f8723d968e6ba0dfd3 | e02d07d4cdece38745d708ca9125d9a5315e8339 | /deps/node-6.10.2/deps/v8/src/heap/heap.h | 2d2029912cd7170171316cef99c6bab82b628069 | [
"BSD-3-Clause",
"bzip2-1.0.6",
"ICU",
"LicenseRef-scancode-unicode",
"NAIST-2003",
"MIT",
"ISC",
"LicenseRef-scancode-public-domain",
"NTP",
"Artistic-2.0",
"BSD-2-Clause",
"Zlib",
"LicenseRef-scancode-unknown-license-reference",
"LicenseRef-scancode-openssl"
] | permissive | wirelab/LiquidCore | b54d4d5239a24ea9228a21e63f16e6399d5caa15 | 4952250f433fd8dc1ad2bf290928197e094de8ed | refs/heads/master | 2021-01-02T08:17:48.282136 | 2017-08-03T11:34:46 | 2017-08-03T11:34:46 | 98,988,527 | 1 | 0 | null | 2017-08-01T10:16:56 | 2017-08-01T10:16:56 | null | UTF-8 | C++ | false | false | 104,068 | h | // Copyright 2012 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef V8_HEAP_HEAP_H_
#define V8_HEAP_HEAP_H_
#include <cmath>
#include <map>
// Clients of this interface shouldn't depend on lots of heap internals.
// Do not include anything from src/heap here!
#include "include/v8.h"
#include "src/allocation.h"
#include "src/assert-scope.h"
#include "src/atomic-utils.h"
#include "src/globals.h"
#include "src/heap-symbols.h"
// TODO(mstarzinger): Two more includes to kill!
#include "src/heap/spaces.h"
#include "src/heap/store-buffer.h"
#include "src/list.h"
namespace v8 {
namespace internal {
using v8::MemoryPressureLevel;
// Defines all the roots in Heap.
#define STRONG_ROOT_LIST(V) \
V(Map, byte_array_map, ByteArrayMap) \
V(Map, free_space_map, FreeSpaceMap) \
V(Map, one_pointer_filler_map, OnePointerFillerMap) \
V(Map, two_pointer_filler_map, TwoPointerFillerMap) \
/* Cluster the most popular ones in a few cache lines here at the top. */ \
V(Oddball, uninitialized_value, UninitializedValue) \
V(Oddball, undefined_value, UndefinedValue) \
V(Map, cell_map, CellMap) \
V(Oddball, null_value, NullValue) \
V(Oddball, true_value, TrueValue) \
V(Oddball, false_value, FalseValue) \
V(String, empty_string, empty_string) \
V(Oddball, the_hole_value, TheHoleValue) \
V(Map, global_property_cell_map, GlobalPropertyCellMap) \
V(Map, shared_function_info_map, SharedFunctionInfoMap) \
V(Map, meta_map, MetaMap) \
V(Map, heap_number_map, HeapNumberMap) \
V(Map, mutable_heap_number_map, MutableHeapNumberMap) \
V(Map, float32x4_map, Float32x4Map) \
V(Map, int32x4_map, Int32x4Map) \
V(Map, uint32x4_map, Uint32x4Map) \
V(Map, bool32x4_map, Bool32x4Map) \
V(Map, int16x8_map, Int16x8Map) \
V(Map, uint16x8_map, Uint16x8Map) \
V(Map, bool16x8_map, Bool16x8Map) \
V(Map, int8x16_map, Int8x16Map) \
V(Map, uint8x16_map, Uint8x16Map) \
V(Map, bool8x16_map, Bool8x16Map) \
V(Map, native_context_map, NativeContextMap) \
V(Map, fixed_array_map, FixedArrayMap) \
V(Map, code_map, CodeMap) \
V(Map, scope_info_map, ScopeInfoMap) \
V(Map, fixed_cow_array_map, FixedCOWArrayMap) \
V(Map, fixed_double_array_map, FixedDoubleArrayMap) \
V(Map, weak_cell_map, WeakCellMap) \
V(Map, transition_array_map, TransitionArrayMap) \
V(Map, one_byte_string_map, OneByteStringMap) \
V(Map, one_byte_internalized_string_map, OneByteInternalizedStringMap) \
V(Map, function_context_map, FunctionContextMap) \
V(FixedArray, empty_fixed_array, EmptyFixedArray) \
V(ByteArray, empty_byte_array, EmptyByteArray) \
V(DescriptorArray, empty_descriptor_array, EmptyDescriptorArray) \
/* The roots above this line should be boring from a GC point of view. */ \
/* This means they are never in new space and never on a page that is */ \
/* being compacted. */ \
V(Oddball, no_interceptor_result_sentinel, NoInterceptorResultSentinel) \
V(Oddball, arguments_marker, ArgumentsMarker) \
V(Oddball, exception, Exception) \
V(Oddball, termination_exception, TerminationException) \
V(Oddball, optimized_out, OptimizedOut) \
V(FixedArray, number_string_cache, NumberStringCache) \
V(Object, instanceof_cache_function, InstanceofCacheFunction) \
V(Object, instanceof_cache_map, InstanceofCacheMap) \
V(Object, instanceof_cache_answer, InstanceofCacheAnswer) \
V(FixedArray, single_character_string_cache, SingleCharacterStringCache) \
V(FixedArray, string_split_cache, StringSplitCache) \
V(FixedArray, regexp_multiple_cache, RegExpMultipleCache) \
V(Smi, hash_seed, HashSeed) \
V(Map, hash_table_map, HashTableMap) \
V(Map, ordered_hash_table_map, OrderedHashTableMap) \
V(Map, symbol_map, SymbolMap) \
V(Map, string_map, StringMap) \
V(Map, cons_one_byte_string_map, ConsOneByteStringMap) \
V(Map, cons_string_map, ConsStringMap) \
V(Map, sliced_string_map, SlicedStringMap) \
V(Map, sliced_one_byte_string_map, SlicedOneByteStringMap) \
V(Map, external_string_map, ExternalStringMap) \
V(Map, external_string_with_one_byte_data_map, \
ExternalStringWithOneByteDataMap) \
V(Map, external_one_byte_string_map, ExternalOneByteStringMap) \
V(Map, native_source_string_map, NativeSourceStringMap) \
V(Map, short_external_string_map, ShortExternalStringMap) \
V(Map, short_external_string_with_one_byte_data_map, \
ShortExternalStringWithOneByteDataMap) \
V(Map, internalized_string_map, InternalizedStringMap) \
V(Map, external_internalized_string_map, ExternalInternalizedStringMap) \
V(Map, external_internalized_string_with_one_byte_data_map, \
ExternalInternalizedStringWithOneByteDataMap) \
V(Map, external_one_byte_internalized_string_map, \
ExternalOneByteInternalizedStringMap) \
V(Map, short_external_internalized_string_map, \
ShortExternalInternalizedStringMap) \
V(Map, short_external_internalized_string_with_one_byte_data_map, \
ShortExternalInternalizedStringWithOneByteDataMap) \
V(Map, short_external_one_byte_internalized_string_map, \
ShortExternalOneByteInternalizedStringMap) \
V(Map, short_external_one_byte_string_map, ShortExternalOneByteStringMap) \
V(Map, fixed_uint8_array_map, FixedUint8ArrayMap) \
V(Map, fixed_int8_array_map, FixedInt8ArrayMap) \
V(Map, fixed_uint16_array_map, FixedUint16ArrayMap) \
V(Map, fixed_int16_array_map, FixedInt16ArrayMap) \
V(Map, fixed_uint32_array_map, FixedUint32ArrayMap) \
V(Map, fixed_int32_array_map, FixedInt32ArrayMap) \
V(Map, fixed_float32_array_map, FixedFloat32ArrayMap) \
V(Map, fixed_float64_array_map, FixedFloat64ArrayMap) \
V(Map, fixed_uint8_clamped_array_map, FixedUint8ClampedArrayMap) \
V(FixedTypedArrayBase, empty_fixed_uint8_array, EmptyFixedUint8Array) \
V(FixedTypedArrayBase, empty_fixed_int8_array, EmptyFixedInt8Array) \
V(FixedTypedArrayBase, empty_fixed_uint16_array, EmptyFixedUint16Array) \
V(FixedTypedArrayBase, empty_fixed_int16_array, EmptyFixedInt16Array) \
V(FixedTypedArrayBase, empty_fixed_uint32_array, EmptyFixedUint32Array) \
V(FixedTypedArrayBase, empty_fixed_int32_array, EmptyFixedInt32Array) \
V(FixedTypedArrayBase, empty_fixed_float32_array, EmptyFixedFloat32Array) \
V(FixedTypedArrayBase, empty_fixed_float64_array, EmptyFixedFloat64Array) \
V(FixedTypedArrayBase, empty_fixed_uint8_clamped_array, \
EmptyFixedUint8ClampedArray) \
V(Map, sloppy_arguments_elements_map, SloppyArgumentsElementsMap) \
V(Map, catch_context_map, CatchContextMap) \
V(Map, with_context_map, WithContextMap) \
V(Map, debug_evaluate_context_map, DebugEvaluateContextMap) \
V(Map, block_context_map, BlockContextMap) \
V(Map, module_context_map, ModuleContextMap) \
V(Map, script_context_map, ScriptContextMap) \
V(Map, script_context_table_map, ScriptContextTableMap) \
V(Map, undefined_map, UndefinedMap) \
V(Map, the_hole_map, TheHoleMap) \
V(Map, null_map, NullMap) \
V(Map, boolean_map, BooleanMap) \
V(Map, uninitialized_map, UninitializedMap) \
V(Map, arguments_marker_map, ArgumentsMarkerMap) \
V(Map, no_interceptor_result_sentinel_map, NoInterceptorResultSentinelMap) \
V(Map, exception_map, ExceptionMap) \
V(Map, termination_exception_map, TerminationExceptionMap) \
V(Map, optimized_out_map, OptimizedOutMap) \
V(Map, message_object_map, JSMessageObjectMap) \
V(Map, foreign_map, ForeignMap) \
V(Map, neander_map, NeanderMap) \
V(Map, external_map, ExternalMap) \
V(HeapNumber, nan_value, NanValue) \
V(HeapNumber, infinity_value, InfinityValue) \
V(HeapNumber, minus_zero_value, MinusZeroValue) \
V(HeapNumber, minus_infinity_value, MinusInfinityValue) \
V(JSObject, message_listeners, MessageListeners) \
V(UnseededNumberDictionary, code_stubs, CodeStubs) \
V(UnseededNumberDictionary, non_monomorphic_cache, NonMonomorphicCache) \
V(PolymorphicCodeCache, polymorphic_code_cache, PolymorphicCodeCache) \
V(Code, js_entry_code, JsEntryCode) \
V(Code, js_construct_entry_code, JsConstructEntryCode) \
V(FixedArray, natives_source_cache, NativesSourceCache) \
V(FixedArray, experimental_natives_source_cache, \
ExperimentalNativesSourceCache) \
V(FixedArray, extra_natives_source_cache, ExtraNativesSourceCache) \
V(FixedArray, experimental_extra_natives_source_cache, \
ExperimentalExtraNativesSourceCache) \
V(Script, empty_script, EmptyScript) \
V(NameDictionary, intrinsic_function_names, IntrinsicFunctionNames) \
V(NameDictionary, empty_properties_dictionary, EmptyPropertiesDictionary) \
V(Cell, undefined_cell, UndefinedCell) \
V(JSObject, observation_state, ObservationState) \
V(Object, symbol_registry, SymbolRegistry) \
V(Object, script_list, ScriptList) \
V(SeededNumberDictionary, empty_slow_element_dictionary, \
EmptySlowElementDictionary) \
V(FixedArray, materialized_objects, MaterializedObjects) \
V(FixedArray, microtask_queue, MicrotaskQueue) \
V(TypeFeedbackVector, dummy_vector, DummyVector) \
V(FixedArray, cleared_optimized_code_map, ClearedOptimizedCodeMap) \
V(FixedArray, detached_contexts, DetachedContexts) \
V(ArrayList, retained_maps, RetainedMaps) \
V(WeakHashTable, weak_object_to_code_table, WeakObjectToCodeTable) \
V(PropertyCell, array_protector, ArrayProtector) \
V(PropertyCell, empty_property_cell, EmptyPropertyCell) \
V(Object, weak_stack_trace_list, WeakStackTraceList) \
V(Object, noscript_shared_function_infos, NoScriptSharedFunctionInfos) \
V(Map, bytecode_array_map, BytecodeArrayMap) \
V(WeakCell, empty_weak_cell, EmptyWeakCell) \
V(PropertyCell, species_protector, SpeciesProtector)
// Entries in this list are limited to Smis and are not visited during GC.
#define SMI_ROOT_LIST(V) \
V(Smi, stack_limit, StackLimit) \
V(Smi, real_stack_limit, RealStackLimit) \
V(Smi, last_script_id, LastScriptId) \
V(Smi, arguments_adaptor_deopt_pc_offset, ArgumentsAdaptorDeoptPCOffset) \
V(Smi, construct_stub_deopt_pc_offset, ConstructStubDeoptPCOffset) \
V(Smi, getter_stub_deopt_pc_offset, GetterStubDeoptPCOffset) \
V(Smi, setter_stub_deopt_pc_offset, SetterStubDeoptPCOffset)
#define ROOT_LIST(V) \
STRONG_ROOT_LIST(V) \
SMI_ROOT_LIST(V) \
V(StringTable, string_table, StringTable)
// Heap roots that are known to be immortal immovable, for which we can safely
// skip write barriers. This list is not complete and has omissions.
#define IMMORTAL_IMMOVABLE_ROOT_LIST(V) \
V(ByteArrayMap) \
V(BytecodeArrayMap) \
V(FreeSpaceMap) \
V(OnePointerFillerMap) \
V(TwoPointerFillerMap) \
V(UndefinedValue) \
V(TheHoleValue) \
V(NullValue) \
V(TrueValue) \
V(FalseValue) \
V(UninitializedValue) \
V(CellMap) \
V(GlobalPropertyCellMap) \
V(SharedFunctionInfoMap) \
V(MetaMap) \
V(HeapNumberMap) \
V(MutableHeapNumberMap) \
V(Float32x4Map) \
V(Int32x4Map) \
V(Uint32x4Map) \
V(Bool32x4Map) \
V(Int16x8Map) \
V(Uint16x8Map) \
V(Bool16x8Map) \
V(Int8x16Map) \
V(Uint8x16Map) \
V(Bool8x16Map) \
V(NativeContextMap) \
V(FixedArrayMap) \
V(CodeMap) \
V(ScopeInfoMap) \
V(FixedCOWArrayMap) \
V(FixedDoubleArrayMap) \
V(WeakCellMap) \
V(TransitionArrayMap) \
V(NoInterceptorResultSentinel) \
V(HashTableMap) \
V(OrderedHashTableMap) \
V(EmptyFixedArray) \
V(EmptyByteArray) \
V(EmptyDescriptorArray) \
V(ArgumentsMarker) \
V(SymbolMap) \
V(SloppyArgumentsElementsMap) \
V(FunctionContextMap) \
V(CatchContextMap) \
V(WithContextMap) \
V(BlockContextMap) \
V(ModuleContextMap) \
V(ScriptContextMap) \
V(UndefinedMap) \
V(TheHoleMap) \
V(NullMap) \
V(BooleanMap) \
V(UninitializedMap) \
V(ArgumentsMarkerMap) \
V(JSMessageObjectMap) \
V(ForeignMap) \
V(NeanderMap) \
V(NanValue) \
V(InfinityValue) \
V(MinusZeroValue) \
V(MinusInfinityValue) \
V(EmptyWeakCell) \
V(empty_string) \
PRIVATE_SYMBOL_LIST(V)
// Forward declarations.
class AllocationObserver;
class ArrayBufferTracker;
class GCIdleTimeAction;
class GCIdleTimeHandler;
class GCIdleTimeHeapState;
class GCTracer;
class HeapObjectsFilter;
class HeapStats;
class HistogramTimer;
class Isolate;
class MemoryReducer;
class ObjectStats;
class Scavenger;
class ScavengeJob;
class WeakObjectRetainer;
typedef void (*ObjectSlotCallback)(HeapObject** from, HeapObject* to);
// A queue of objects promoted during scavenge. Each object is accompanied
// by it's size to avoid dereferencing a map pointer for scanning.
// The last page in to-space is used for the promotion queue. On conflict
// during scavenge, the promotion queue is allocated externally and all
// entries are copied to the external queue.
class PromotionQueue {
public:
explicit PromotionQueue(Heap* heap)
: front_(NULL),
rear_(NULL),
limit_(NULL),
emergency_stack_(0),
heap_(heap) {}
void Initialize();
void Destroy() {
DCHECK(is_empty());
delete emergency_stack_;
emergency_stack_ = NULL;
}
Page* GetHeadPage() {
return Page::FromAllocationTop(reinterpret_cast<Address>(rear_));
}
void SetNewLimit(Address limit) {
// If we are already using an emergency stack, we can ignore it.
if (emergency_stack_) return;
// If the limit is not on the same page, we can ignore it.
if (Page::FromAllocationTop(limit) != GetHeadPage()) return;
limit_ = reinterpret_cast<struct Entry*>(limit);
if (limit_ <= rear_) {
return;
}
RelocateQueueHead();
}
bool IsBelowPromotionQueue(Address to_space_top) {
// If an emergency stack is used, the to-space address cannot interfere
// with the promotion queue.
if (emergency_stack_) return true;
// If the given to-space top pointer and the head of the promotion queue
// are not on the same page, then the to-space objects are below the
// promotion queue.
if (GetHeadPage() != Page::FromAddress(to_space_top)) {
return true;
}
// If the to space top pointer is smaller or equal than the promotion
// queue head, then the to-space objects are below the promotion queue.
return reinterpret_cast<struct Entry*>(to_space_top) <= rear_;
}
bool is_empty() {
return (front_ == rear_) &&
(emergency_stack_ == NULL || emergency_stack_->length() == 0);
}
inline void insert(HeapObject* target, int32_t size, bool was_marked_black);
void remove(HeapObject** target, int32_t* size, bool* was_marked_black) {
DCHECK(!is_empty());
if (front_ == rear_) {
Entry e = emergency_stack_->RemoveLast();
*target = e.obj_;
*size = e.size_;
*was_marked_black = e.was_marked_black_;
return;
}
struct Entry* entry = reinterpret_cast<struct Entry*>(--front_);
*target = entry->obj_;
*size = entry->size_;
*was_marked_black = entry->was_marked_black_;
// Assert no underflow.
SemiSpace::AssertValidRange(reinterpret_cast<Address>(rear_),
reinterpret_cast<Address>(front_));
}
private:
struct Entry {
Entry(HeapObject* obj, int32_t size, bool was_marked_black)
: obj_(obj), size_(size), was_marked_black_(was_marked_black) {}
HeapObject* obj_;
int32_t size_ : 31;
bool was_marked_black_ : 1;
};
void RelocateQueueHead();
// The front of the queue is higher in the memory page chain than the rear.
struct Entry* front_;
struct Entry* rear_;
struct Entry* limit_;
List<Entry>* emergency_stack_;
Heap* heap_;
DISALLOW_COPY_AND_ASSIGN(PromotionQueue);
};
enum ArrayStorageAllocationMode {
DONT_INITIALIZE_ARRAY_ELEMENTS,
INITIALIZE_ARRAY_ELEMENTS_WITH_HOLE
};
enum class ClearRecordedSlots { kYes, kNo };
class Heap {
public:
// Declare all the root indices. This defines the root list order.
enum RootListIndex {
#define ROOT_INDEX_DECLARATION(type, name, camel_name) k##camel_name##RootIndex,
STRONG_ROOT_LIST(ROOT_INDEX_DECLARATION)
#undef ROOT_INDEX_DECLARATION
#define STRING_INDEX_DECLARATION(name, str) k##name##RootIndex,
INTERNALIZED_STRING_LIST(STRING_INDEX_DECLARATION)
#undef STRING_DECLARATION
#define SYMBOL_INDEX_DECLARATION(name) k##name##RootIndex,
PRIVATE_SYMBOL_LIST(SYMBOL_INDEX_DECLARATION)
#undef SYMBOL_INDEX_DECLARATION
#define SYMBOL_INDEX_DECLARATION(name, description) k##name##RootIndex,
PUBLIC_SYMBOL_LIST(SYMBOL_INDEX_DECLARATION)
WELL_KNOWN_SYMBOL_LIST(SYMBOL_INDEX_DECLARATION)
#undef SYMBOL_INDEX_DECLARATION
// Utility type maps
#define DECLARE_STRUCT_MAP(NAME, Name, name) k##Name##MapRootIndex,
STRUCT_LIST(DECLARE_STRUCT_MAP)
#undef DECLARE_STRUCT_MAP
kStringTableRootIndex,
#define ROOT_INDEX_DECLARATION(type, name, camel_name) k##camel_name##RootIndex,
SMI_ROOT_LIST(ROOT_INDEX_DECLARATION)
#undef ROOT_INDEX_DECLARATION
kRootListLength,
kStrongRootListLength = kStringTableRootIndex,
kSmiRootsStart = kStringTableRootIndex + 1
};
enum FindMementoMode { kForRuntime, kForGC };
enum HeapState { NOT_IN_GC, SCAVENGE, MARK_COMPACT };
// Indicates whether live bytes adjustment is triggered
// - from within the GC code before sweeping started (SEQUENTIAL_TO_SWEEPER),
// - or from within GC (CONCURRENT_TO_SWEEPER),
// - or mutator code (CONCURRENT_TO_SWEEPER).
enum InvocationMode { SEQUENTIAL_TO_SWEEPER, CONCURRENT_TO_SWEEPER };
enum UpdateAllocationSiteMode { kGlobal, kCached };
// Taking this lock prevents the GC from entering a phase that relocates
// object references.
class RelocationLock {
public:
explicit RelocationLock(Heap* heap) : heap_(heap) {
heap_->relocation_mutex_.Lock();
}
~RelocationLock() { heap_->relocation_mutex_.Unlock(); }
private:
Heap* heap_;
};
// Support for partial snapshots. After calling this we have a linear
// space to write objects in each space.
struct Chunk {
uint32_t size;
Address start;
Address end;
};
typedef List<Chunk> Reservation;
static const intptr_t kMinimumOldGenerationAllocationLimit =
8 * (Page::kPageSize > MB ? Page::kPageSize : MB);
static const int kInitalOldGenerationLimitFactor = 2;
#if V8_OS_ANDROID
// Don't apply pointer multiplier on Android since it has no swap space and
// should instead adapt it's heap size based on available physical memory.
static const int kPointerMultiplier = 1;
#else
static const int kPointerMultiplier = i::kPointerSize / 4;
#endif
// The new space size has to be a power of 2. Sizes are in MB.
static const int kMaxSemiSpaceSizeLowMemoryDevice = 1 * kPointerMultiplier;
static const int kMaxSemiSpaceSizeMediumMemoryDevice = 4 * kPointerMultiplier;
static const int kMaxSemiSpaceSizeHighMemoryDevice = 8 * kPointerMultiplier;
static const int kMaxSemiSpaceSizeHugeMemoryDevice = 8 * kPointerMultiplier;
// The old space size has to be a multiple of Page::kPageSize.
// Sizes are in MB.
static const int kMaxOldSpaceSizeLowMemoryDevice = 128 * kPointerMultiplier;
static const int kMaxOldSpaceSizeMediumMemoryDevice =
256 * kPointerMultiplier;
static const int kMaxOldSpaceSizeHighMemoryDevice = 512 * kPointerMultiplier;
static const int kMaxOldSpaceSizeHugeMemoryDevice = 700 * kPointerMultiplier;
// The executable size has to be a multiple of Page::kPageSize.
// Sizes are in MB.
static const int kMaxExecutableSizeLowMemoryDevice = 96 * kPointerMultiplier;
static const int kMaxExecutableSizeMediumMemoryDevice =
192 * kPointerMultiplier;
static const int kMaxExecutableSizeHighMemoryDevice =
256 * kPointerMultiplier;
static const int kMaxExecutableSizeHugeMemoryDevice =
256 * kPointerMultiplier;
static const int kTraceRingBufferSize = 512;
static const int kStacktraceBufferSize = 512;
static const double kMinHeapGrowingFactor;
static const double kMaxHeapGrowingFactor;
static const double kMaxHeapGrowingFactorMemoryConstrained;
static const double kMaxHeapGrowingFactorIdle;
static const double kTargetMutatorUtilization;
static const int kNoGCFlags = 0;
static const int kReduceMemoryFootprintMask = 1;
static const int kAbortIncrementalMarkingMask = 2;
static const int kFinalizeIncrementalMarkingMask = 4;
// Making the heap iterable requires us to abort incremental marking.
static const int kMakeHeapIterableMask = kAbortIncrementalMarkingMask;
// The roots that have an index less than this are always in old space.
static const int kOldSpaceRoots = 0x20;
// The minimum size of a HeapObject on the heap.
static const int kMinObjectSizeInWords = 2;
STATIC_ASSERT(kUndefinedValueRootIndex ==
Internals::kUndefinedValueRootIndex);
STATIC_ASSERT(kTheHoleValueRootIndex == Internals::kTheHoleValueRootIndex);
STATIC_ASSERT(kNullValueRootIndex == Internals::kNullValueRootIndex);
STATIC_ASSERT(kTrueValueRootIndex == Internals::kTrueValueRootIndex);
STATIC_ASSERT(kFalseValueRootIndex == Internals::kFalseValueRootIndex);
STATIC_ASSERT(kempty_stringRootIndex == Internals::kEmptyStringRootIndex);
// Calculates the maximum amount of filler that could be required by the
// given alignment.
static int GetMaximumFillToAlign(AllocationAlignment alignment);
// Calculates the actual amount of filler required for a given address at the
// given alignment.
static int GetFillToAlign(Address address, AllocationAlignment alignment);
template <typename T>
static inline bool IsOneByte(T t, int chars);
static void FatalProcessOutOfMemory(const char* location,
bool is_heap_oom = false);
static bool RootIsImmortalImmovable(int root_index);
// Checks whether the space is valid.
static bool IsValidAllocationSpace(AllocationSpace space);
// Generated code can embed direct references to non-writable roots if
// they are in new space.
static bool RootCanBeWrittenAfterInitialization(RootListIndex root_index);
// Zapping is needed for verify heap, and always done in debug builds.
static inline bool ShouldZapGarbage() {
#ifdef DEBUG
return true;
#else
#ifdef VERIFY_HEAP
return FLAG_verify_heap;
#else
return false;
#endif
#endif
}
static double HeapGrowingFactor(double gc_speed, double mutator_speed);
// Copy block of memory from src to dst. Size of block should be aligned
// by pointer size.
static inline void CopyBlock(Address dst, Address src, int byte_size);
// Determines a static visitor id based on the given {map} that can then be
// stored on the map to facilitate fast dispatch for {StaticVisitorBase}.
static int GetStaticVisitorIdForMap(Map* map);
// Notifies the heap that is ok to start marking or other activities that
// should not happen during deserialization.
void NotifyDeserializationComplete();
intptr_t old_generation_allocation_limit() const {
return old_generation_allocation_limit_;
}
bool always_allocate() { return always_allocate_scope_count_.Value() != 0; }
Address* NewSpaceAllocationTopAddress() {
return new_space_.allocation_top_address();
}
Address* NewSpaceAllocationLimitAddress() {
return new_space_.allocation_limit_address();
}
Address* OldSpaceAllocationTopAddress() {
return old_space_->allocation_top_address();
}
Address* OldSpaceAllocationLimitAddress() {
return old_space_->allocation_limit_address();
}
// TODO(hpayer): There is still a missmatch between capacity and actual
// committed memory size.
bool CanExpandOldGeneration(int size = 0) {
if (force_oom_) return false;
return (CommittedOldGenerationMemory() + size) < MaxOldGenerationSize();
}
// Clear the Instanceof cache (used when a prototype changes).
inline void ClearInstanceofCache();
// FreeSpace objects have a null map after deserialization. Update the map.
void RepairFreeListsAfterDeserialization();
// Move len elements within a given array from src_index index to dst_index
// index.
void MoveElements(FixedArray* array, int dst_index, int src_index, int len);
// Initialize a filler object to keep the ability to iterate over the heap
// when introducing gaps within pages. If slots could have been recorded in
// the freed area, then pass ClearRecordedSlots::kYes as the mode. Otherwise,
// pass ClearRecordedSlots::kNo.
void CreateFillerObjectAt(Address addr, int size, ClearRecordedSlots mode);
bool CanMoveObjectStart(HeapObject* object);
// Maintain consistency of live bytes during incremental marking.
void AdjustLiveBytes(HeapObject* object, int by, InvocationMode mode);
// Trim the given array from the left. Note that this relocates the object
// start and hence is only valid if there is only a single reference to it.
FixedArrayBase* LeftTrimFixedArray(FixedArrayBase* obj, int elements_to_trim);
// Trim the given array from the right.
template<Heap::InvocationMode mode>
void RightTrimFixedArray(FixedArrayBase* obj, int elements_to_trim);
// Converts the given boolean condition to JavaScript boolean value.
inline Oddball* ToBoolean(bool condition);
// Check whether the heap is currently iterable.
bool IsHeapIterable();
// Notify the heap that a context has been disposed.
int NotifyContextDisposed(bool dependant_context);
void set_native_contexts_list(Object* object) {
native_contexts_list_ = object;
}
Object* native_contexts_list() const { return native_contexts_list_; }
void set_allocation_sites_list(Object* object) {
allocation_sites_list_ = object;
}
Object* allocation_sites_list() { return allocation_sites_list_; }
// Used in CreateAllocationSiteStub and the (de)serializer.
Object** allocation_sites_list_address() { return &allocation_sites_list_; }
void set_encountered_weak_collections(Object* weak_collection) {
encountered_weak_collections_ = weak_collection;
}
Object* encountered_weak_collections() const {
return encountered_weak_collections_;
}
void set_encountered_weak_cells(Object* weak_cell) {
encountered_weak_cells_ = weak_cell;
}
Object* encountered_weak_cells() const { return encountered_weak_cells_; }
void set_encountered_transition_arrays(Object* transition_array) {
encountered_transition_arrays_ = transition_array;
}
Object* encountered_transition_arrays() const {
return encountered_transition_arrays_;
}
// Number of mark-sweeps.
int ms_count() const { return ms_count_; }
// Checks whether the given object is allowed to be migrated from it's
// current space into the given destination space. Used for debugging.
inline bool AllowedToBeMigrated(HeapObject* object, AllocationSpace dest);
void CheckHandleCount();
// Number of "runtime allocations" done so far.
uint32_t allocations_count() { return allocations_count_; }
// Print short heap statistics.
void PrintShortHeapStatistics();
inline HeapState gc_state() { return gc_state_; }
inline bool IsInGCPostProcessing() { return gc_post_processing_depth_ > 0; }
// If an object has an AllocationMemento trailing it, return it, otherwise
// return NULL;
template <FindMementoMode mode>
inline AllocationMemento* FindAllocationMemento(HeapObject* object);
// Returns false if not able to reserve.
bool ReserveSpace(Reservation* reservations);
//
// Support for the API.
//
void CreateApiObjects();
// Implements the corresponding V8 API function.
bool IdleNotification(double deadline_in_seconds);
bool IdleNotification(int idle_time_in_ms);
void MemoryPressureNotification(MemoryPressureLevel level,
bool is_isolate_locked);
void CheckMemoryPressure();
double MonotonicallyIncreasingTimeInMs();
void RecordStats(HeapStats* stats, bool take_snapshot = false);
// Check new space expansion criteria and expand semispaces if it was hit.
void CheckNewSpaceExpansionCriteria();
inline bool HeapIsFullEnoughToStartIncrementalMarking(intptr_t limit) {
if (FLAG_stress_compaction && (gc_count_ & 1) != 0) return true;
intptr_t adjusted_allocation_limit = limit - new_space_.Capacity();
if (PromotedTotalSize() >= adjusted_allocation_limit) return true;
if (HighMemoryPressure()) return true;
return false;
}
void VisitExternalResources(v8::ExternalResourceVisitor* visitor);
// An object should be promoted if the object has survived a
// scavenge operation.
inline bool ShouldBePromoted(Address old_address, int object_size);
void ClearNormalizedMapCaches();
void IncrementDeferredCount(v8::Isolate::UseCounterFeature feature);
inline bool OldGenerationAllocationLimitReached();
void QueueMemoryChunkForFree(MemoryChunk* chunk);
void FreeQueuedChunks(MemoryChunk* list_head);
void FreeQueuedChunks();
void WaitUntilUnmappingOfFreeChunksCompleted();
// Completely clear the Instanceof cache (to stop it keeping objects alive
// around a GC).
inline void CompletelyClearInstanceofCache();
inline uint32_t HashSeed();
inline int NextScriptId();
inline void SetArgumentsAdaptorDeoptPCOffset(int pc_offset);
inline void SetConstructStubDeoptPCOffset(int pc_offset);
inline void SetGetterStubDeoptPCOffset(int pc_offset);
inline void SetSetterStubDeoptPCOffset(int pc_offset);
// For post mortem debugging.
void RememberUnmappedPage(Address page, bool compacted);
// Global inline caching age: it is incremented on some GCs after context
// disposal. We use it to flush inline caches.
int global_ic_age() { return global_ic_age_; }
void AgeInlineCaches() {
global_ic_age_ = (global_ic_age_ + 1) & SharedFunctionInfo::ICAgeBits::kMax;
}
int64_t amount_of_external_allocated_memory() {
return amount_of_external_allocated_memory_;
}
void update_amount_of_external_allocated_memory(int64_t delta) {
amount_of_external_allocated_memory_ += delta;
}
void DeoptMarkedAllocationSites();
bool DeoptMaybeTenuredAllocationSites() {
return new_space_.IsAtMaximumCapacity() && maximum_size_scavenges_ == 0;
}
void AddWeakObjectToCodeDependency(Handle<HeapObject> obj,
Handle<DependentCode> dep);
DependentCode* LookupWeakObjectToCodeDependency(Handle<HeapObject> obj);
void AddRetainedMap(Handle<Map> map);
// This event is triggered after successful allocation of a new object made
// by runtime. Allocations of target space for object evacuation do not
// trigger the event. In order to track ALL allocations one must turn off
// FLAG_inline_new and FLAG_use_allocation_folding.
inline void OnAllocationEvent(HeapObject* object, int size_in_bytes);
// This event is triggered after object is moved to a new place.
inline void OnMoveEvent(HeapObject* target, HeapObject* source,
int size_in_bytes);
bool deserialization_complete() const { return deserialization_complete_; }
bool HasLowAllocationRate();
bool HasHighFragmentation();
bool HasHighFragmentation(intptr_t used, intptr_t committed);
void SetOptimizeForLatency() { optimize_for_memory_usage_ = false; }
void SetOptimizeForMemoryUsage();
bool ShouldOptimizeForMemoryUsage() {
return optimize_for_memory_usage_ || HighMemoryPressure();
}
bool HighMemoryPressure() {
return memory_pressure_level_.Value() != MemoryPressureLevel::kNone;
}
// ===========================================================================
// Initialization. ===========================================================
// ===========================================================================
// Configure heap size in MB before setup. Return false if the heap has been
// set up already.
bool ConfigureHeap(int max_semi_space_size, int max_old_space_size,
int max_executable_size, size_t code_range_size);
bool ConfigureHeapDefault();
// Prepares the heap, setting up memory areas that are needed in the isolate
// without actually creating any objects.
bool SetUp();
// Bootstraps the object heap with the core set of objects required to run.
// Returns whether it succeeded.
bool CreateHeapObjects();
// Destroys all memory allocated by the heap.
void TearDown();
// Returns whether SetUp has been called.
bool HasBeenSetUp();
// ===========================================================================
// Getters for spaces. =======================================================
// ===========================================================================
Address NewSpaceTop() { return new_space_.top(); }
NewSpace* new_space() { return &new_space_; }
OldSpace* old_space() { return old_space_; }
OldSpace* code_space() { return code_space_; }
MapSpace* map_space() { return map_space_; }
LargeObjectSpace* lo_space() { return lo_space_; }
PagedSpace* paged_space(int idx) {
switch (idx) {
case OLD_SPACE:
return old_space();
case MAP_SPACE:
return map_space();
case CODE_SPACE:
return code_space();
case NEW_SPACE:
case LO_SPACE:
UNREACHABLE();
}
return NULL;
}
Space* space(int idx) {
switch (idx) {
case NEW_SPACE:
return new_space();
case LO_SPACE:
return lo_space();
default:
return paged_space(idx);
}
}
// Returns name of the space.
const char* GetSpaceName(int idx);
// ===========================================================================
// API. ======================================================================
// ===========================================================================
void SetEmbedderHeapTracer(EmbedderHeapTracer* tracer);
void RegisterExternallyReferencedObject(Object** object);
// ===========================================================================
// Getters to other components. ==============================================
// ===========================================================================
GCTracer* tracer() { return tracer_; }
EmbedderHeapTracer* embedder_heap_tracer() { return embedder_heap_tracer_; }
PromotionQueue* promotion_queue() { return &promotion_queue_; }
inline Isolate* isolate();
MarkCompactCollector* mark_compact_collector() {
return mark_compact_collector_;
}
// ===========================================================================
// Root set access. ==========================================================
// ===========================================================================
// Heap root getters.
#define ROOT_ACCESSOR(type, name, camel_name) inline type* name();
ROOT_LIST(ROOT_ACCESSOR)
#undef ROOT_ACCESSOR
// Utility type maps.
#define STRUCT_MAP_ACCESSOR(NAME, Name, name) inline Map* name##_map();
STRUCT_LIST(STRUCT_MAP_ACCESSOR)
#undef STRUCT_MAP_ACCESSOR
#define STRING_ACCESSOR(name, str) inline String* name();
INTERNALIZED_STRING_LIST(STRING_ACCESSOR)
#undef STRING_ACCESSOR
#define SYMBOL_ACCESSOR(name) inline Symbol* name();
PRIVATE_SYMBOL_LIST(SYMBOL_ACCESSOR)
#undef SYMBOL_ACCESSOR
#define SYMBOL_ACCESSOR(name, description) inline Symbol* name();
PUBLIC_SYMBOL_LIST(SYMBOL_ACCESSOR)
WELL_KNOWN_SYMBOL_LIST(SYMBOL_ACCESSOR)
#undef SYMBOL_ACCESSOR
Object* root(RootListIndex index) { return roots_[index]; }
Handle<Object> root_handle(RootListIndex index) {
return Handle<Object>(&roots_[index]);
}
// Generated code can embed this address to get access to the roots.
Object** roots_array_start() { return roots_; }
// Sets the stub_cache_ (only used when expanding the dictionary).
void SetRootCodeStubs(UnseededNumberDictionary* value) {
roots_[kCodeStubsRootIndex] = value;
}
// Sets the non_monomorphic_cache_ (only used when expanding the dictionary).
void SetRootNonMonomorphicCache(UnseededNumberDictionary* value) {
roots_[kNonMonomorphicCacheRootIndex] = value;
}
void SetRootMaterializedObjects(FixedArray* objects) {
roots_[kMaterializedObjectsRootIndex] = objects;
}
void SetRootScriptList(Object* value) {
roots_[kScriptListRootIndex] = value;
}
void SetRootStringTable(StringTable* value) {
roots_[kStringTableRootIndex] = value;
}
void SetRootNoScriptSharedFunctionInfos(Object* value) {
roots_[kNoScriptSharedFunctionInfosRootIndex] = value;
}
// Set the stack limit in the roots_ array. Some architectures generate
// code that looks here, because it is faster than loading from the static
// jslimit_/real_jslimit_ variable in the StackGuard.
void SetStackLimits();
// The stack limit is thread-dependent. To be able to reproduce the same
// snapshot blob, we need to reset it before serializing.
void ClearStackLimits();
// Generated code can treat direct references to this root as constant.
bool RootCanBeTreatedAsConstant(RootListIndex root_index);
Map* MapForFixedTypedArray(ExternalArrayType array_type);
RootListIndex RootIndexForFixedTypedArray(ExternalArrayType array_type);
RootListIndex RootIndexForEmptyFixedTypedArray(ElementsKind kind);
FixedTypedArrayBase* EmptyFixedTypedArrayForMap(Map* map);
void RegisterStrongRoots(Object** start, Object** end);
void UnregisterStrongRoots(Object** start);
// ===========================================================================
// Inline allocation. ========================================================
// ===========================================================================
// Indicates whether inline bump-pointer allocation has been disabled.
bool inline_allocation_disabled() { return inline_allocation_disabled_; }
// Switch whether inline bump-pointer allocation should be used.
void EnableInlineAllocation();
void DisableInlineAllocation();
// ===========================================================================
// Methods triggering GCs. ===================================================
// ===========================================================================
// Performs garbage collection operation.
// Returns whether there is a chance that another major GC could
// collect more garbage.
inline bool CollectGarbage(
AllocationSpace space, const char* gc_reason = NULL,
const GCCallbackFlags gc_callback_flags = kNoGCCallbackFlags);
// Performs a full garbage collection. If (flags & kMakeHeapIterableMask) is
// non-zero, then the slower precise sweeper is used, which leaves the heap
// in a state where we can iterate over the heap visiting all objects.
void CollectAllGarbage(
int flags = kFinalizeIncrementalMarkingMask, const char* gc_reason = NULL,
const GCCallbackFlags gc_callback_flags = kNoGCCallbackFlags);
// Last hope GC, should try to squeeze as much as possible.
void CollectAllAvailableGarbage(const char* gc_reason = NULL);
// Reports and external memory pressure event, either performs a major GC or
// completes incremental marking in order to free external resources.
void ReportExternalMemoryPressure(const char* gc_reason = NULL);
// Invoked when GC was requested via the stack guard.
void HandleGCRequest();
// ===========================================================================
// Iterators. ================================================================
// ===========================================================================
// Iterates over all roots in the heap.
void IterateRoots(ObjectVisitor* v, VisitMode mode);
// Iterates over all strong roots in the heap.
void IterateStrongRoots(ObjectVisitor* v, VisitMode mode);
// Iterates over entries in the smi roots list. Only interesting to the
// serializer/deserializer, since GC does not care about smis.
void IterateSmiRoots(ObjectVisitor* v);
// Iterates over all the other roots in the heap.
void IterateWeakRoots(ObjectVisitor* v, VisitMode mode);
// Iterate pointers of promoted objects.
void IteratePromotedObject(HeapObject* target, int size,
bool was_marked_black,
ObjectSlotCallback callback);
void IteratePromotedObjectPointers(HeapObject* object, Address start,
Address end, bool record_slots,
ObjectSlotCallback callback);
// ===========================================================================
// Store buffer API. =========================================================
// ===========================================================================
// Write barrier support for object[offset] = o;
inline void RecordWrite(Object* object, int offset, Object* o);
Address* store_buffer_top_address() { return store_buffer()->top_address(); }
void ClearRecordedSlot(HeapObject* object, Object** slot);
void ClearRecordedSlotRange(Address start, Address end);
// ===========================================================================
// Incremental marking API. ==================================================
// ===========================================================================
// Start incremental marking and ensure that idle time handler can perform
// incremental steps.
void StartIdleIncrementalMarking();
// Starts incremental marking assuming incremental marking is currently
// stopped.
void StartIncrementalMarking(int gc_flags = kNoGCFlags,
const GCCallbackFlags gc_callback_flags =
GCCallbackFlags::kNoGCCallbackFlags,
const char* reason = nullptr);
void FinalizeIncrementalMarkingIfComplete(const char* comment);
bool TryFinalizeIdleIncrementalMarking(double idle_time_in_ms);
void RegisterReservationsForBlackAllocation(Reservation* reservations);
IncrementalMarking* incremental_marking() { return incremental_marking_; }
// ===========================================================================
// External string table API. ================================================
// ===========================================================================
// Registers an external string.
inline void RegisterExternalString(String* string);
// Finalizes an external string by deleting the associated external
// data and clearing the resource pointer.
inline void FinalizeExternalString(String* string);
// ===========================================================================
// Methods checking/returning the space of a given object/address. ===========
// ===========================================================================
// Returns whether the object resides in new space.
inline bool InNewSpace(Object* object);
inline bool InFromSpace(Object* object);
inline bool InToSpace(Object* object);
// Returns whether the object resides in old space.
inline bool InOldSpace(Object* object);
// Checks whether an address/object in the heap (including auxiliary
// area and unused area).
bool Contains(HeapObject* value);
// Checks whether an address/object in a space.
// Currently used by tests, serialization and heap verification only.
bool InSpace(HeapObject* value, AllocationSpace space);
// Slow methods that can be used for verification as they can also be used
// with off-heap Addresses.
bool ContainsSlow(Address addr);
bool InSpaceSlow(Address addr, AllocationSpace space);
inline bool InNewSpaceSlow(Address address);
inline bool InOldSpaceSlow(Address address);
// ===========================================================================
// Object statistics tracking. ===============================================
// ===========================================================================
// Returns the number of buckets used by object statistics tracking during a
// major GC. Note that the following methods fail gracefully when the bounds
// are exceeded though.
size_t NumberOfTrackedHeapObjectTypes();
// Returns object statistics about count and size at the last major GC.
// Objects are being grouped into buckets that roughly resemble existing
// instance types.
size_t ObjectCountAtLastGC(size_t index);
size_t ObjectSizeAtLastGC(size_t index);
// Retrieves names of buckets used by object statistics tracking.
bool GetObjectTypeName(size_t index, const char** object_type,
const char** object_sub_type);
// ===========================================================================
// GC statistics. ============================================================
// ===========================================================================
// Returns the maximum amount of memory reserved for the heap.
intptr_t MaxReserved() {
return 2 * max_semi_space_size_ + max_old_generation_size_;
}
int MaxSemiSpaceSize() { return max_semi_space_size_; }
int InitialSemiSpaceSize() { return initial_semispace_size_; }
intptr_t MaxOldGenerationSize() { return max_old_generation_size_; }
intptr_t MaxExecutableSize() { return max_executable_size_; }
// Returns the capacity of the heap in bytes w/o growing. Heap grows when
// more spaces are needed until it reaches the limit.
intptr_t Capacity();
// Returns the amount of memory currently committed for the heap.
intptr_t CommittedMemory();
// Returns the amount of memory currently committed for the old space.
intptr_t CommittedOldGenerationMemory();
// Returns the amount of executable memory currently committed for the heap.
intptr_t CommittedMemoryExecutable();
// Returns the amount of phyical memory currently committed for the heap.
size_t CommittedPhysicalMemory();
// Returns the maximum amount of memory ever committed for the heap.
intptr_t MaximumCommittedMemory() { return maximum_committed_; }
// Updates the maximum committed memory for the heap. Should be called
// whenever a space grows.
void UpdateMaximumCommitted();
// Returns the available bytes in space w/o growing.
// Heap doesn't guarantee that it can allocate an object that requires
// all available bytes. Check MaxHeapObjectSize() instead.
intptr_t Available();
// Returns of size of all objects residing in the heap.
intptr_t SizeOfObjects();
void UpdateSurvivalStatistics(int start_new_space_size);
inline void IncrementPromotedObjectsSize(intptr_t object_size) {
DCHECK_GE(object_size, 0);
promoted_objects_size_ += object_size;
}
inline intptr_t promoted_objects_size() { return promoted_objects_size_; }
inline void IncrementSemiSpaceCopiedObjectSize(intptr_t object_size) {
DCHECK_GE(object_size, 0);
semi_space_copied_object_size_ += object_size;
}
inline intptr_t semi_space_copied_object_size() {
return semi_space_copied_object_size_;
}
inline intptr_t SurvivedNewSpaceObjectSize() {
return promoted_objects_size_ + semi_space_copied_object_size_;
}
inline void IncrementNodesDiedInNewSpace() { nodes_died_in_new_space_++; }
inline void IncrementNodesCopiedInNewSpace() { nodes_copied_in_new_space_++; }
inline void IncrementNodesPromoted() { nodes_promoted_++; }
inline void IncrementYoungSurvivorsCounter(intptr_t survived) {
DCHECK_GE(survived, 0);
survived_last_scavenge_ = survived;
survived_since_last_expansion_ += survived;
}
inline intptr_t PromotedTotalSize() {
int64_t total = PromotedSpaceSizeOfObjects() + PromotedExternalMemorySize();
if (total > std::numeric_limits<intptr_t>::max()) {
// TODO(erikcorry): Use uintptr_t everywhere we do heap size calculations.
return std::numeric_limits<intptr_t>::max();
}
if (total < 0) return 0;
return static_cast<intptr_t>(total);
}
void UpdateNewSpaceAllocationCounter() {
new_space_allocation_counter_ = NewSpaceAllocationCounter();
}
size_t NewSpaceAllocationCounter() {
return new_space_allocation_counter_ + new_space()->AllocatedSinceLastGC();
}
// This should be used only for testing.
void set_new_space_allocation_counter(size_t new_value) {
new_space_allocation_counter_ = new_value;
}
void UpdateOldGenerationAllocationCounter() {
old_generation_allocation_counter_ = OldGenerationAllocationCounter();
}
size_t OldGenerationAllocationCounter() {
return old_generation_allocation_counter_ + PromotedSinceLastGC();
}
// This should be used only for testing.
void set_old_generation_allocation_counter(size_t new_value) {
old_generation_allocation_counter_ = new_value;
}
size_t PromotedSinceLastGC() {
return PromotedSpaceSizeOfObjects() - old_generation_size_at_last_gc_;
}
int gc_count() const { return gc_count_; }
// Returns the size of objects residing in non new spaces.
intptr_t PromotedSpaceSizeOfObjects();
double total_regexp_code_generated() { return total_regexp_code_generated_; }
void IncreaseTotalRegexpCodeGenerated(int size) {
total_regexp_code_generated_ += size;
}
void IncrementCodeGeneratedBytes(bool is_crankshafted, int size) {
if (is_crankshafted) {
crankshaft_codegen_bytes_generated_ += size;
} else {
full_codegen_bytes_generated_ += size;
}
}
// ===========================================================================
// Prologue/epilogue callback methods.========================================
// ===========================================================================
void AddGCPrologueCallback(v8::Isolate::GCCallback callback,
GCType gc_type_filter, bool pass_isolate = true);
void RemoveGCPrologueCallback(v8::Isolate::GCCallback callback);
void AddGCEpilogueCallback(v8::Isolate::GCCallback callback,
GCType gc_type_filter, bool pass_isolate = true);
void RemoveGCEpilogueCallback(v8::Isolate::GCCallback callback);
void CallGCPrologueCallbacks(GCType gc_type, GCCallbackFlags flags);
void CallGCEpilogueCallbacks(GCType gc_type, GCCallbackFlags flags);
// ===========================================================================
// Allocation methods. =======================================================
// ===========================================================================
// Creates a filler object and returns a heap object immediately after it.
MUST_USE_RESULT HeapObject* PrecedeWithFiller(HeapObject* object,
int filler_size);
// Creates a filler object if needed for alignment and returns a heap object
// immediately after it. If any space is left after the returned object,
// another filler object is created so the over allocated memory is iterable.
MUST_USE_RESULT HeapObject* AlignWithFiller(HeapObject* object,
int object_size,
int allocation_size,
AllocationAlignment alignment);
// ===========================================================================
// ArrayBuffer tracking. =====================================================
// ===========================================================================
void RegisterNewArrayBuffer(JSArrayBuffer* buffer);
void UnregisterArrayBuffer(JSArrayBuffer* buffer);
inline ArrayBufferTracker* array_buffer_tracker() {
return array_buffer_tracker_;
}
// ===========================================================================
// Allocation site tracking. =================================================
// ===========================================================================
// Updates the AllocationSite of a given {object}. If the global prenuring
// storage is passed as {pretenuring_feedback} the memento found count on
// the corresponding allocation site is immediately updated and an entry
// in the hash map is created. Otherwise the entry (including a the count
// value) is cached on the local pretenuring feedback.
template <UpdateAllocationSiteMode mode>
inline void UpdateAllocationSite(HeapObject* object,
HashMap* pretenuring_feedback);
// Removes an entry from the global pretenuring storage.
inline void RemoveAllocationSitePretenuringFeedback(AllocationSite* site);
// Merges local pretenuring feedback into the global one. Note that this
// method needs to be called after evacuation, as allocation sites may be
// evacuated and this method resolves forward pointers accordingly.
void MergeAllocationSitePretenuringFeedback(
const HashMap& local_pretenuring_feedback);
// =============================================================================
#ifdef VERIFY_HEAP
// Verify the heap is in its normal state before or after a GC.
void Verify();
#endif
#ifdef DEBUG
void set_allocation_timeout(int timeout) { allocation_timeout_ = timeout; }
void TracePathToObjectFrom(Object* target, Object* root);
void TracePathToObject(Object* target);
void TracePathToGlobal();
void Print();
void PrintHandles();
// Report heap statistics.
void ReportHeapStatistics(const char* title);
void ReportCodeStatistics(const char* title);
#endif
private:
class PretenuringScope;
class UnmapFreeMemoryTask;
// External strings table is a place where all external strings are
// registered. We need to keep track of such strings to properly
// finalize them.
class ExternalStringTable {
public:
// Registers an external string.
inline void AddString(String* string);
inline void Iterate(ObjectVisitor* v);
// Restores internal invariant and gets rid of collected strings.
// Must be called after each Iterate() that modified the strings.
void CleanUp();
// Destroys all allocated memory.
void TearDown();
private:
explicit ExternalStringTable(Heap* heap) : heap_(heap) {}
inline void Verify();
inline void AddOldString(String* string);
// Notifies the table that only a prefix of the new list is valid.
inline void ShrinkNewStrings(int position);
// To speed up scavenge collections new space string are kept
// separate from old space strings.
List<Object*> new_space_strings_;
List<Object*> old_space_strings_;
Heap* heap_;
friend class Heap;
DISALLOW_COPY_AND_ASSIGN(ExternalStringTable);
};
struct StrongRootsList;
struct StringTypeTable {
InstanceType type;
int size;
RootListIndex index;
};
struct ConstantStringTable {
const char* contents;
RootListIndex index;
};
struct StructTable {
InstanceType type;
int size;
RootListIndex index;
};
struct GCCallbackPair {
GCCallbackPair(v8::Isolate::GCCallback callback, GCType gc_type,
bool pass_isolate)
: callback(callback), gc_type(gc_type), pass_isolate(pass_isolate) {}
bool operator==(const GCCallbackPair& other) const {
return other.callback == callback;
}
v8::Isolate::GCCallback callback;
GCType gc_type;
bool pass_isolate;
};
typedef String* (*ExternalStringTableUpdaterCallback)(Heap* heap,
Object** pointer);
static const int kInitialStringTableSize = 2048;
static const int kInitialEvalCacheSize = 64;
static const int kInitialNumberStringCacheSize = 256;
static const int kRememberedUnmappedPages = 128;
static const StringTypeTable string_type_table[];
static const ConstantStringTable constant_string_table[];
static const StructTable struct_table[];
static const int kYoungSurvivalRateHighThreshold = 90;
static const int kYoungSurvivalRateAllowedDeviation = 15;
static const int kOldSurvivalRateLowThreshold = 10;
static const int kMaxMarkCompactsInIdleRound = 7;
static const int kIdleScavengeThreshold = 5;
static const int kInitialFeedbackCapacity = 256;
Heap();
static String* UpdateNewSpaceReferenceInExternalStringTableEntry(
Heap* heap, Object** pointer);
// Selects the proper allocation space based on the pretenuring decision.
static AllocationSpace SelectSpace(PretenureFlag pretenure) {
return (pretenure == TENURED) ? OLD_SPACE : NEW_SPACE;
}
#define ROOT_ACCESSOR(type, name, camel_name) \
inline void set_##name(type* value);
ROOT_LIST(ROOT_ACCESSOR)
#undef ROOT_ACCESSOR
StoreBuffer* store_buffer() { return &store_buffer_; }
void set_current_gc_flags(int flags) {
current_gc_flags_ = flags;
DCHECK(!ShouldFinalizeIncrementalMarking() ||
!ShouldAbortIncrementalMarking());
}
inline bool ShouldReduceMemory() const {
return current_gc_flags_ & kReduceMemoryFootprintMask;
}
inline bool ShouldAbortIncrementalMarking() const {
return current_gc_flags_ & kAbortIncrementalMarkingMask;
}
inline bool ShouldFinalizeIncrementalMarking() const {
return current_gc_flags_ & kFinalizeIncrementalMarkingMask;
}
void PreprocessStackTraces();
// Checks whether a global GC is necessary
GarbageCollector SelectGarbageCollector(AllocationSpace space,
const char** reason);
// Make sure there is a filler value behind the top of the new space
// so that the GC does not confuse some unintialized/stale memory
// with the allocation memento of the object at the top
void EnsureFillerObjectAtTop();
// Ensure that we have swept all spaces in such a way that we can iterate
// over all objects. May cause a GC.
void MakeHeapIterable();
// Performs garbage collection operation.
// Returns whether there is a chance that another major GC could
// collect more garbage.
bool CollectGarbage(
GarbageCollector collector, const char* gc_reason,
const char* collector_reason,
const GCCallbackFlags gc_callback_flags = kNoGCCallbackFlags);
// Performs garbage collection
// Returns whether there is a chance another major GC could
// collect more garbage.
bool PerformGarbageCollection(
GarbageCollector collector,
const GCCallbackFlags gc_callback_flags = kNoGCCallbackFlags);
inline void UpdateOldSpaceLimits();
// Initializes a JSObject based on its map.
void InitializeJSObjectFromMap(JSObject* obj, FixedArray* properties,
Map* map);
// Initializes JSObject body starting at given offset.
void InitializeJSObjectBody(JSObject* obj, Map* map, int start_offset);
void InitializeAllocationMemento(AllocationMemento* memento,
AllocationSite* allocation_site);
bool CreateInitialMaps();
void CreateInitialObjects();
// These five Create*EntryStub functions are here and forced to not be inlined
// because of a gcc-4.4 bug that assigns wrong vtable entries.
NO_INLINE(void CreateJSEntryStub());
NO_INLINE(void CreateJSConstructEntryStub());
void CreateFixedStubs();
HeapObject* DoubleAlignForDeserialization(HeapObject* object, int size);
// Commits from space if it is uncommitted.
void EnsureFromSpaceIsCommitted();
// Uncommit unused semi space.
bool UncommitFromSpace() { return new_space_.UncommitFromSpace(); }
// Fill in bogus values in from space
void ZapFromSpace();
// Deopts all code that contains allocation instruction which are tenured or
// not tenured. Moreover it clears the pretenuring allocation site statistics.
void ResetAllAllocationSitesDependentCode(PretenureFlag flag);
// Evaluates local pretenuring for the old space and calls
// ResetAllTenuredAllocationSitesDependentCode if too many objects died in
// the old space.
void EvaluateOldSpaceLocalPretenuring(uint64_t size_of_objects_before_gc);
// Record statistics before and after garbage collection.
void ReportStatisticsBeforeGC();
void ReportStatisticsAfterGC();
// Creates and installs the full-sized number string cache.
int FullSizeNumberStringCacheLength();
// Flush the number to string cache.
void FlushNumberStringCache();
// TODO(hpayer): Allocation site pretenuring may make this method obsolete.
// Re-visit incremental marking heuristics.
bool IsHighSurvivalRate() { return high_survival_rate_period_length_ > 0; }
void ConfigureInitialOldGenerationSize();
bool HasLowYoungGenerationAllocationRate();
bool HasLowOldGenerationAllocationRate();
double YoungGenerationMutatorUtilization();
double OldGenerationMutatorUtilization();
void ReduceNewSpaceSize();
bool TryFinalizeIdleIncrementalMarking(
double idle_time_in_ms, size_t size_of_objects,
size_t mark_compact_speed_in_bytes_per_ms);
GCIdleTimeHeapState ComputeHeapState();
bool PerformIdleTimeAction(GCIdleTimeAction action,
GCIdleTimeHeapState heap_state,
double deadline_in_ms);
void IdleNotificationEpilogue(GCIdleTimeAction action,
GCIdleTimeHeapState heap_state, double start_ms,
double deadline_in_ms);
inline void UpdateAllocationsHash(HeapObject* object);
inline void UpdateAllocationsHash(uint32_t value);
void PrintAlloctionsHash();
void AddToRingBuffer(const char* string);
void GetFromRingBuffer(char* buffer);
void CompactRetainedMaps(ArrayList* retained_maps);
void CollectGarbageOnMemoryPressure(const char* source);
// Attempt to over-approximate the weak closure by marking object groups and
// implicit references from global handles, but don't atomically complete
// marking. If we continue to mark incrementally, we might have marked
// objects that die later.
void FinalizeIncrementalMarking(const char* gc_reason);
// Returns the timer used for a given GC type.
// - GCScavenger: young generation GC
// - GCCompactor: full GC
// - GCFinalzeMC: finalization of incremental full GC
// - GCFinalizeMCReduceMemory: finalization of incremental full GC with
// memory reduction
HistogramTimer* GCTypeTimer(GarbageCollector collector);
// ===========================================================================
// Pretenuring. ==============================================================
// ===========================================================================
// Pretenuring decisions are made based on feedback collected during new space
// evacuation. Note that between feedback collection and calling this method
// object in old space must not move.
void ProcessPretenuringFeedback();
// ===========================================================================
// Actual GC. ================================================================
// ===========================================================================
// Code that should be run before and after each GC. Includes some
// reporting/verification activities when compiled with DEBUG set.
void GarbageCollectionPrologue();
void GarbageCollectionEpilogue();
// Performs a major collection in the whole heap.
void MarkCompact();
// Code to be run before and after mark-compact.
void MarkCompactPrologue();
void MarkCompactEpilogue();
// Performs a minor collection in new generation.
void Scavenge();
Address DoScavenge(ObjectVisitor* scavenge_visitor, Address new_space_front);
void UpdateNewSpaceReferencesInExternalStringTable(
ExternalStringTableUpdaterCallback updater_func);
void UpdateReferencesInExternalStringTable(
ExternalStringTableUpdaterCallback updater_func);
void ProcessAllWeakReferences(WeakObjectRetainer* retainer);
void ProcessYoungWeakReferences(WeakObjectRetainer* retainer);
void ProcessNativeContexts(WeakObjectRetainer* retainer);
void ProcessAllocationSites(WeakObjectRetainer* retainer);
void ProcessWeakListRoots(WeakObjectRetainer* retainer);
// ===========================================================================
// GC statistics. ============================================================
// ===========================================================================
inline intptr_t OldGenerationSpaceAvailable() {
return old_generation_allocation_limit_ - PromotedTotalSize();
}
// Returns maximum GC pause.
double get_max_gc_pause() { return max_gc_pause_; }
// Returns maximum size of objects alive after GC.
intptr_t get_max_alive_after_gc() { return max_alive_after_gc_; }
// Returns minimal interval between two subsequent collections.
double get_min_in_mutator() { return min_in_mutator_; }
// Update GC statistics that are tracked on the Heap.
void UpdateCumulativeGCStatistics(double duration, double spent_in_mutator,
double marking_time);
bool MaximumSizeScavenge() { return maximum_size_scavenges_ > 0; }
// ===========================================================================
// Growing strategy. =========================================================
// ===========================================================================
// Decrease the allocation limit if the new limit based on the given
// parameters is lower than the current limit.
void DampenOldGenerationAllocationLimit(intptr_t old_gen_size,
double gc_speed,
double mutator_speed);
// Calculates the allocation limit based on a given growing factor and a
// given old generation size.
intptr_t CalculateOldGenerationAllocationLimit(double factor,
intptr_t old_gen_size);
// Sets the allocation limit to trigger the next full garbage collection.
void SetOldGenerationAllocationLimit(intptr_t old_gen_size, double gc_speed,
double mutator_speed);
// ===========================================================================
// Idle notification. ========================================================
// ===========================================================================
bool RecentIdleNotificationHappened();
void ScheduleIdleScavengeIfNeeded(int bytes_allocated);
// ===========================================================================
// HeapIterator helpers. =====================================================
// ===========================================================================
void heap_iterator_start() { heap_iterator_depth_++; }
void heap_iterator_end() { heap_iterator_depth_--; }
bool in_heap_iterator() { return heap_iterator_depth_ > 0; }
// ===========================================================================
// Allocation methods. =======================================================
// ===========================================================================
// Returns a deep copy of the JavaScript object.
// Properties and elements are copied too.
// Optionally takes an AllocationSite to be appended in an AllocationMemento.
MUST_USE_RESULT AllocationResult CopyJSObject(JSObject* source,
AllocationSite* site = NULL);
// Allocates a JS Map in the heap.
MUST_USE_RESULT AllocationResult
AllocateMap(InstanceType instance_type, int instance_size,
ElementsKind elements_kind = TERMINAL_FAST_ELEMENTS_KIND);
// Allocates and initializes a new JavaScript object based on a
// constructor.
// If allocation_site is non-null, then a memento is emitted after the object
// that points to the site.
MUST_USE_RESULT AllocationResult AllocateJSObject(
JSFunction* constructor, PretenureFlag pretenure = NOT_TENURED,
AllocationSite* allocation_site = NULL);
// Allocates and initializes a new JavaScript object based on a map.
// Passing an allocation site means that a memento will be created that
// points to the site.
MUST_USE_RESULT AllocationResult
AllocateJSObjectFromMap(Map* map, PretenureFlag pretenure = NOT_TENURED,
AllocationSite* allocation_site = NULL);
// Allocates a HeapNumber from value.
MUST_USE_RESULT AllocationResult
AllocateHeapNumber(double value, MutableMode mode = IMMUTABLE,
PretenureFlag pretenure = NOT_TENURED);
// Allocates SIMD values from the given lane values.
#define SIMD_ALLOCATE_DECLARATION(TYPE, Type, type, lane_count, lane_type) \
AllocationResult Allocate##Type(lane_type lanes[lane_count], \
PretenureFlag pretenure = NOT_TENURED);
SIMD128_TYPES(SIMD_ALLOCATE_DECLARATION)
#undef SIMD_ALLOCATE_DECLARATION
// Allocates a byte array of the specified length
MUST_USE_RESULT AllocationResult
AllocateByteArray(int length, PretenureFlag pretenure = NOT_TENURED);
// Allocates a bytecode array with given contents.
MUST_USE_RESULT AllocationResult
AllocateBytecodeArray(int length, const byte* raw_bytecodes, int frame_size,
int parameter_count, FixedArray* constant_pool);
// Copy the code and scope info part of the code object, but insert
// the provided data as the relocation information.
MUST_USE_RESULT AllocationResult CopyCode(Code* code,
Vector<byte> reloc_info);
MUST_USE_RESULT AllocationResult CopyCode(Code* code);
MUST_USE_RESULT AllocationResult
CopyBytecodeArray(BytecodeArray* bytecode_array);
// Allocates a fixed array initialized with undefined values
MUST_USE_RESULT AllocationResult
AllocateFixedArray(int length, PretenureFlag pretenure = NOT_TENURED);
// Allocate an uninitialized object. The memory is non-executable if the
// hardware and OS allow. This is the single choke-point for allocations
// performed by the runtime and should not be bypassed (to extend this to
// inlined allocations, use the Heap::DisableInlineAllocation() support).
MUST_USE_RESULT inline AllocationResult AllocateRaw(
int size_in_bytes, AllocationSpace space,
AllocationAlignment aligment = kWordAligned);
// Allocates a heap object based on the map.
MUST_USE_RESULT AllocationResult
Allocate(Map* map, AllocationSpace space,
AllocationSite* allocation_site = NULL);
// Allocates a partial map for bootstrapping.
MUST_USE_RESULT AllocationResult
AllocatePartialMap(InstanceType instance_type, int instance_size);
// Allocate a block of memory in the given space (filled with a filler).
// Used as a fall-back for generated code when the space is full.
MUST_USE_RESULT AllocationResult
AllocateFillerObject(int size, bool double_align, AllocationSpace space);
// Allocate an uninitialized fixed array.
MUST_USE_RESULT AllocationResult
AllocateRawFixedArray(int length, PretenureFlag pretenure);
// Allocate an uninitialized fixed double array.
MUST_USE_RESULT AllocationResult
AllocateRawFixedDoubleArray(int length, PretenureFlag pretenure);
// Allocate an initialized fixed array with the given filler value.
MUST_USE_RESULT AllocationResult
AllocateFixedArrayWithFiller(int length, PretenureFlag pretenure,
Object* filler);
// Allocate and partially initializes a String. There are two String
// encodings: one-byte and two-byte. These functions allocate a string of
// the given length and set its map and length fields. The characters of
// the string are uninitialized.
MUST_USE_RESULT AllocationResult
AllocateRawOneByteString(int length, PretenureFlag pretenure);
MUST_USE_RESULT AllocationResult
AllocateRawTwoByteString(int length, PretenureFlag pretenure);
// Allocates an internalized string in old space based on the character
// stream.
MUST_USE_RESULT inline AllocationResult AllocateInternalizedStringFromUtf8(
Vector<const char> str, int chars, uint32_t hash_field);
MUST_USE_RESULT inline AllocationResult AllocateOneByteInternalizedString(
Vector<const uint8_t> str, uint32_t hash_field);
MUST_USE_RESULT inline AllocationResult AllocateTwoByteInternalizedString(
Vector<const uc16> str, uint32_t hash_field);
template <bool is_one_byte, typename T>
MUST_USE_RESULT AllocationResult
AllocateInternalizedStringImpl(T t, int chars, uint32_t hash_field);
template <typename T>
MUST_USE_RESULT inline AllocationResult AllocateInternalizedStringImpl(
T t, int chars, uint32_t hash_field);
// Allocates an uninitialized fixed array. It must be filled by the caller.
MUST_USE_RESULT AllocationResult AllocateUninitializedFixedArray(int length);
// Make a copy of src and return it.
MUST_USE_RESULT inline AllocationResult CopyFixedArray(FixedArray* src);
// Make a copy of src, also grow the copy, and return the copy.
MUST_USE_RESULT AllocationResult
CopyFixedArrayAndGrow(FixedArray* src, int grow_by, PretenureFlag pretenure);
// Make a copy of src, also grow the copy, and return the copy.
MUST_USE_RESULT AllocationResult CopyFixedArrayUpTo(FixedArray* src,
int new_len,
PretenureFlag pretenure);
// Make a copy of src, set the map, and return the copy.
MUST_USE_RESULT AllocationResult
CopyFixedArrayWithMap(FixedArray* src, Map* map);
// Make a copy of src and return it.
MUST_USE_RESULT inline AllocationResult CopyFixedDoubleArray(
FixedDoubleArray* src);
// Computes a single character string where the character has code.
// A cache is used for one-byte (Latin1) codes.
MUST_USE_RESULT AllocationResult
LookupSingleCharacterStringFromCode(uint16_t code);
// Allocate a symbol in old space.
MUST_USE_RESULT AllocationResult AllocateSymbol();
// Allocates an external array of the specified length and type.
MUST_USE_RESULT AllocationResult AllocateFixedTypedArrayWithExternalPointer(
int length, ExternalArrayType array_type, void* external_pointer,
PretenureFlag pretenure);
// Allocates a fixed typed array of the specified length and type.
MUST_USE_RESULT AllocationResult
AllocateFixedTypedArray(int length, ExternalArrayType array_type,
bool initialize, PretenureFlag pretenure);
// Make a copy of src and return it.
MUST_USE_RESULT AllocationResult CopyAndTenureFixedCOWArray(FixedArray* src);
// Make a copy of src, set the map, and return the copy.
MUST_USE_RESULT AllocationResult
CopyFixedDoubleArrayWithMap(FixedDoubleArray* src, Map* map);
// Allocates a fixed double array with uninitialized values. Returns
MUST_USE_RESULT AllocationResult AllocateUninitializedFixedDoubleArray(
int length, PretenureFlag pretenure = NOT_TENURED);
// Allocate empty fixed array.
MUST_USE_RESULT AllocationResult AllocateEmptyFixedArray();
// Allocate empty fixed typed array of given type.
MUST_USE_RESULT AllocationResult
AllocateEmptyFixedTypedArray(ExternalArrayType array_type);
// Allocate a tenured simple cell.
MUST_USE_RESULT AllocationResult AllocateCell(Object* value);
// Allocate a tenured JS global property cell initialized with the hole.
MUST_USE_RESULT AllocationResult AllocatePropertyCell();
MUST_USE_RESULT AllocationResult AllocateWeakCell(HeapObject* value);
MUST_USE_RESULT AllocationResult AllocateTransitionArray(int capacity);
// Allocates a new utility object in the old generation.
MUST_USE_RESULT AllocationResult AllocateStruct(InstanceType type);
// Allocates a new foreign object.
MUST_USE_RESULT AllocationResult
AllocateForeign(Address address, PretenureFlag pretenure = NOT_TENURED);
MUST_USE_RESULT AllocationResult
AllocateCode(int object_size, bool immovable);
MUST_USE_RESULT AllocationResult InternalizeStringWithKey(HashTableKey* key);
MUST_USE_RESULT AllocationResult InternalizeString(String* str);
// ===========================================================================
void set_force_oom(bool value) { force_oom_ = value; }
// The amount of external memory registered through the API kept alive
// by global handles
int64_t amount_of_external_allocated_memory_;
// Caches the amount of external memory registered at the last global gc.
int64_t amount_of_external_allocated_memory_at_last_global_gc_;
// This can be calculated directly from a pointer to the heap; however, it is
// more expedient to get at the isolate directly from within Heap methods.
Isolate* isolate_;
Object* roots_[kRootListLength];
size_t code_range_size_;
int max_semi_space_size_;
int initial_semispace_size_;
intptr_t max_old_generation_size_;
intptr_t initial_old_generation_size_;
bool old_generation_size_configured_;
intptr_t max_executable_size_;
intptr_t maximum_committed_;
// For keeping track of how much data has survived
// scavenge since last new space expansion.
intptr_t survived_since_last_expansion_;
// ... and since the last scavenge.
intptr_t survived_last_scavenge_;
// This is not the depth of nested AlwaysAllocateScope's but rather a single
// count, as scopes can be acquired from multiple tasks (read: threads).
AtomicNumber<size_t> always_allocate_scope_count_;
// Stores the memory pressure level that set by MemoryPressureNotification
// and reset by a mark-compact garbage collection.
AtomicValue<MemoryPressureLevel> memory_pressure_level_;
// For keeping track of context disposals.
int contexts_disposed_;
// The length of the retained_maps array at the time of context disposal.
// This separates maps in the retained_maps array that were created before
// and after context disposal.
int number_of_disposed_maps_;
int global_ic_age_;
NewSpace new_space_;
OldSpace* old_space_;
OldSpace* code_space_;
MapSpace* map_space_;
LargeObjectSpace* lo_space_;
HeapState gc_state_;
int gc_post_processing_depth_;
Address new_space_top_after_last_gc_;
// Returns the amount of external memory registered since last global gc.
int64_t PromotedExternalMemorySize();
// How many "runtime allocations" happened.
uint32_t allocations_count_;
// Running hash over allocations performed.
uint32_t raw_allocations_hash_;
// How many mark-sweep collections happened.
unsigned int ms_count_;
// How many gc happened.
unsigned int gc_count_;
// For post mortem debugging.
int remembered_unmapped_pages_index_;
Address remembered_unmapped_pages_[kRememberedUnmappedPages];
#ifdef DEBUG
// If the --gc-interval flag is set to a positive value, this
// variable holds the value indicating the number of allocations
// remain until the next failure and garbage collection.
int allocation_timeout_;
#endif // DEBUG
// Limit that triggers a global GC on the next (normally caused) GC. This
// is checked when we have already decided to do a GC to help determine
// which collector to invoke, before expanding a paged space in the old
// generation and on every allocation in large object space.
intptr_t old_generation_allocation_limit_;
// Indicates that an allocation has failed in the old generation since the
// last GC.
bool old_gen_exhausted_;
// Indicates that memory usage is more important than latency.
// TODO(ulan): Merge it with memory reducer once chromium:490559 is fixed.
bool optimize_for_memory_usage_;
// Indicates that inline bump-pointer allocation has been globally disabled
// for all spaces. This is used to disable allocations in generated code.
bool inline_allocation_disabled_;
// Weak list heads, threaded through the objects.
// List heads are initialized lazily and contain the undefined_value at start.
Object* native_contexts_list_;
Object* allocation_sites_list_;
// List of encountered weak collections (JSWeakMap and JSWeakSet) during
// marking. It is initialized during marking, destroyed after marking and
// contains Smi(0) while marking is not active.
Object* encountered_weak_collections_;
Object* encountered_weak_cells_;
Object* encountered_transition_arrays_;
List<GCCallbackPair> gc_epilogue_callbacks_;
List<GCCallbackPair> gc_prologue_callbacks_;
// Total RegExp code ever generated
double total_regexp_code_generated_;
int deferred_counters_[v8::Isolate::kUseCounterFeatureCount];
GCTracer* tracer_;
EmbedderHeapTracer* embedder_heap_tracer_;
int high_survival_rate_period_length_;
intptr_t promoted_objects_size_;
double promotion_ratio_;
double promotion_rate_;
intptr_t semi_space_copied_object_size_;
intptr_t previous_semi_space_copied_object_size_;
double semi_space_copied_rate_;
int nodes_died_in_new_space_;
int nodes_copied_in_new_space_;
int nodes_promoted_;
// This is the pretenuring trigger for allocation sites that are in maybe
// tenure state. When we switched to the maximum new space size we deoptimize
// the code that belongs to the allocation site and derive the lifetime
// of the allocation site.
unsigned int maximum_size_scavenges_;
// Maximum GC pause.
double max_gc_pause_;
// Total time spent in GC.
double total_gc_time_ms_;
// Maximum size of objects alive after GC.
intptr_t max_alive_after_gc_;
// Minimal interval between two subsequent collections.
double min_in_mutator_;
// Cumulative GC time spent in marking.
double marking_time_;
// Cumulative GC time spent in sweeping.
double sweeping_time_;
// Last time an idle notification happened.
double last_idle_notification_time_;
// Last time a garbage collection happened.
double last_gc_time_;
Scavenger* scavenge_collector_;
MarkCompactCollector* mark_compact_collector_;
StoreBuffer store_buffer_;
IncrementalMarking* incremental_marking_;
GCIdleTimeHandler* gc_idle_time_handler_;
MemoryReducer* memory_reducer_;
ObjectStats* object_stats_;
ScavengeJob* scavenge_job_;
AllocationObserver* idle_scavenge_observer_;
// These two counters are monotomically increasing and never reset.
size_t full_codegen_bytes_generated_;
size_t crankshaft_codegen_bytes_generated_;
// This counter is increased before each GC and never reset.
// To account for the bytes allocated since the last GC, use the
// NewSpaceAllocationCounter() function.
size_t new_space_allocation_counter_;
// This counter is increased before each GC and never reset. To
// account for the bytes allocated since the last GC, use the
// OldGenerationAllocationCounter() function.
size_t old_generation_allocation_counter_;
// The size of objects in old generation after the last MarkCompact GC.
size_t old_generation_size_at_last_gc_;
// If the --deopt_every_n_garbage_collections flag is set to a positive value,
// this variable holds the number of garbage collections since the last
// deoptimization triggered by garbage collection.
int gcs_since_last_deopt_;
// The feedback storage is used to store allocation sites (keys) and how often
// they have been visited (values) by finding a memento behind an object. The
// storage is only alive temporary during a GC. The invariant is that all
// pointers in this map are already fixed, i.e., they do not point to
// forwarding pointers.
HashMap* global_pretenuring_feedback_;
char trace_ring_buffer_[kTraceRingBufferSize];
// If it's not full then the data is from 0 to ring_buffer_end_. If it's
// full then the data is from ring_buffer_end_ to the end of the buffer and
// from 0 to ring_buffer_end_.
bool ring_buffer_full_;
size_t ring_buffer_end_;
// Shared state read by the scavenge collector and set by ScavengeObject.
PromotionQueue promotion_queue_;
// Flag is set when the heap has been configured. The heap can be repeatedly
// configured through the API until it is set up.
bool configured_;
// Currently set GC flags that are respected by all GC components.
int current_gc_flags_;
// Currently set GC callback flags that are used to pass information between
// the embedder and V8's GC.
GCCallbackFlags current_gc_callback_flags_;
ExternalStringTable external_string_table_;
MemoryChunk* chunks_queued_for_free_;
size_t concurrent_unmapping_tasks_active_;
base::Semaphore pending_unmapping_tasks_semaphore_;
base::Mutex relocation_mutex_;
int gc_callbacks_depth_;
bool deserialization_complete_;
StrongRootsList* strong_roots_list_;
ArrayBufferTracker* array_buffer_tracker_;
// The depth of HeapIterator nestings.
int heap_iterator_depth_;
// Used for testing purposes.
bool force_oom_;
// Classes in "heap" can be friends.
friend class AlwaysAllocateScope;
friend class GCCallbacksScope;
friend class GCTracer;
friend class HeapIterator;
friend class IdleScavengeObserver;
friend class IncrementalMarking;
friend class IteratePromotedObjectsVisitor;
friend class MarkCompactCollector;
friend class MarkCompactMarkingVisitor;
friend class NewSpace;
friend class ObjectStatsVisitor;
friend class Page;
friend class Scavenger;
friend class StoreBuffer;
// The allocator interface.
friend class Factory;
// The Isolate constructs us.
friend class Isolate;
// Used in cctest.
friend class HeapTester;
DISALLOW_COPY_AND_ASSIGN(Heap);
};
class HeapStats {
public:
static const int kStartMarker = 0xDECADE00;
static const int kEndMarker = 0xDECADE01;
int* start_marker; // 0
int* new_space_size; // 1
int* new_space_capacity; // 2
intptr_t* old_space_size; // 3
intptr_t* old_space_capacity; // 4
intptr_t* code_space_size; // 5
intptr_t* code_space_capacity; // 6
intptr_t* map_space_size; // 7
intptr_t* map_space_capacity; // 8
intptr_t* lo_space_size; // 9
int* global_handle_count; // 10
int* weak_global_handle_count; // 11
int* pending_global_handle_count; // 12
int* near_death_global_handle_count; // 13
int* free_global_handle_count; // 14
intptr_t* memory_allocator_size; // 15
intptr_t* memory_allocator_capacity; // 16
int* objects_per_type; // 17
int* size_per_type; // 18
int* os_error; // 19
char* last_few_messages; // 20
char* js_stacktrace; // 21
int* end_marker; // 22
};
class AlwaysAllocateScope {
public:
explicit inline AlwaysAllocateScope(Isolate* isolate);
inline ~AlwaysAllocateScope();
private:
Heap* heap_;
};
// Visitor class to verify interior pointers in spaces that do not contain
// or care about intergenerational references. All heap object pointers have to
// point into the heap to a location that has a map pointer at its first word.
// Caveat: Heap::Contains is an approximation because it can return true for
// objects in a heap space but above the allocation pointer.
class VerifyPointersVisitor : public ObjectVisitor {
public:
inline void VisitPointers(Object** start, Object** end) override;
};
// Verify that all objects are Smis.
class VerifySmisVisitor : public ObjectVisitor {
public:
inline void VisitPointers(Object** start, Object** end) override;
};
// Space iterator for iterating over all spaces of the heap. Returns each space
// in turn, and null when it is done.
class AllSpaces BASE_EMBEDDED {
public:
explicit AllSpaces(Heap* heap) : heap_(heap), counter_(FIRST_SPACE) {}
Space* next();
private:
Heap* heap_;
int counter_;
};
// Space iterator for iterating over all old spaces of the heap: Old space
// and code space. Returns each space in turn, and null when it is done.
class OldSpaces BASE_EMBEDDED {
public:
explicit OldSpaces(Heap* heap) : heap_(heap), counter_(OLD_SPACE) {}
OldSpace* next();
private:
Heap* heap_;
int counter_;
};
// Space iterator for iterating over all the paged spaces of the heap: Map
// space, old space, code space and cell space. Returns
// each space in turn, and null when it is done.
class PagedSpaces BASE_EMBEDDED {
public:
explicit PagedSpaces(Heap* heap) : heap_(heap), counter_(OLD_SPACE) {}
PagedSpace* next();
private:
Heap* heap_;
int counter_;
};
// Space iterator for iterating over all spaces of the heap.
// For each space an object iterator is provided. The deallocation of the
// returned object iterators is handled by the space iterator.
class SpaceIterator : public Malloced {
public:
explicit SpaceIterator(Heap* heap);
virtual ~SpaceIterator();
bool has_next();
ObjectIterator* next();
private:
ObjectIterator* CreateIterator();
Heap* heap_;
int current_space_; // from enum AllocationSpace.
ObjectIterator* iterator_; // object iterator for the current space.
};
// A HeapIterator provides iteration over the whole heap. It
// aggregates the specific iterators for the different spaces as
// these can only iterate over one space only.
//
// HeapIterator ensures there is no allocation during its lifetime
// (using an embedded DisallowHeapAllocation instance).
//
// HeapIterator can skip free list nodes (that is, de-allocated heap
// objects that still remain in the heap). As implementation of free
// nodes filtering uses GC marks, it can't be used during MS/MC GC
// phases. Also, it is forbidden to interrupt iteration in this mode,
// as this will leave heap objects marked (and thus, unusable).
class HeapIterator BASE_EMBEDDED {
public:
enum HeapObjectsFiltering { kNoFiltering, kFilterUnreachable };
explicit HeapIterator(Heap* heap,
HeapObjectsFiltering filtering = kNoFiltering);
~HeapIterator();
HeapObject* next();
private:
struct MakeHeapIterableHelper {
explicit MakeHeapIterableHelper(Heap* heap) { heap->MakeHeapIterable(); }
};
HeapObject* NextObject();
// The following two fields need to be declared in this order. Initialization
// order guarantees that we first make the heap iterable (which may involve
// allocations) and only then lock it down by not allowing further
// allocations.
MakeHeapIterableHelper make_heap_iterable_helper_;
DisallowHeapAllocation no_heap_allocation_;
Heap* heap_;
HeapObjectsFiltering filtering_;
HeapObjectsFilter* filter_;
// Space iterator for iterating all the spaces.
SpaceIterator* space_iterator_;
// Object iterator for the space currently being iterated.
ObjectIterator* object_iterator_;
};
// Cache for mapping (map, property name) into field offset.
// Cleared at startup and prior to mark sweep collection.
class KeyedLookupCache {
public:
// Lookup field offset for (map, name). If absent, -1 is returned.
int Lookup(Handle<Map> map, Handle<Name> name);
// Update an element in the cache.
void Update(Handle<Map> map, Handle<Name> name, int field_offset);
// Clear the cache.
void Clear();
static const int kLength = 256;
static const int kCapacityMask = kLength - 1;
static const int kMapHashShift = 5;
static const int kHashMask = -4; // Zero the last two bits.
static const int kEntriesPerBucket = 4;
static const int kEntryLength = 2;
static const int kMapIndex = 0;
static const int kKeyIndex = 1;
static const int kNotFound = -1;
// kEntriesPerBucket should be a power of 2.
STATIC_ASSERT((kEntriesPerBucket & (kEntriesPerBucket - 1)) == 0);
STATIC_ASSERT(kEntriesPerBucket == -kHashMask);
private:
KeyedLookupCache() {
for (int i = 0; i < kLength; ++i) {
keys_[i].map = NULL;
keys_[i].name = NULL;
field_offsets_[i] = kNotFound;
}
}
static inline int Hash(Handle<Map> map, Handle<Name> name);
// Get the address of the keys and field_offsets arrays. Used in
// generated code to perform cache lookups.
Address keys_address() { return reinterpret_cast<Address>(&keys_); }
Address field_offsets_address() {
return reinterpret_cast<Address>(&field_offsets_);
}
struct Key {
Map* map;
Name* name;
};
Key keys_[kLength];
int field_offsets_[kLength];
friend class ExternalReference;
friend class Isolate;
DISALLOW_COPY_AND_ASSIGN(KeyedLookupCache);
};
// Cache for mapping (map, property name) into descriptor index.
// The cache contains both positive and negative results.
// Descriptor index equals kNotFound means the property is absent.
// Cleared at startup and prior to any gc.
class DescriptorLookupCache {
public:
// Lookup descriptor index for (map, name).
// If absent, kAbsent is returned.
inline int Lookup(Map* source, Name* name);
// Update an element in the cache.
inline void Update(Map* source, Name* name, int result);
// Clear the cache.
void Clear();
static const int kAbsent = -2;
private:
DescriptorLookupCache() {
for (int i = 0; i < kLength; ++i) {
keys_[i].source = NULL;
keys_[i].name = NULL;
results_[i] = kAbsent;
}
}
static inline int Hash(Object* source, Name* name);
static const int kLength = 64;
struct Key {
Map* source;
Name* name;
};
Key keys_[kLength];
int results_[kLength];
friend class Isolate;
DISALLOW_COPY_AND_ASSIGN(DescriptorLookupCache);
};
// Abstract base class for checking whether a weak object should be retained.
class WeakObjectRetainer {
public:
virtual ~WeakObjectRetainer() {}
// Return whether this object should be retained. If NULL is returned the
// object has no references. Otherwise the address of the retained object
// should be returned as in some GC situations the object has been moved.
virtual Object* RetainAs(Object* object) = 0;
};
#ifdef DEBUG
// Helper class for tracing paths to a search target Object from all roots.
// The TracePathFrom() method can be used to trace paths from a specific
// object to the search target object.
class PathTracer : public ObjectVisitor {
public:
enum WhatToFind {
FIND_ALL, // Will find all matches.
FIND_FIRST // Will stop the search after first match.
};
// Tags 0, 1, and 3 are used. Use 2 for marking visited HeapObject.
static const int kMarkTag = 2;
// For the WhatToFind arg, if FIND_FIRST is specified, tracing will stop
// after the first match. If FIND_ALL is specified, then tracing will be
// done for all matches.
PathTracer(Object* search_target, WhatToFind what_to_find,
VisitMode visit_mode)
: search_target_(search_target),
found_target_(false),
found_target_in_trace_(false),
what_to_find_(what_to_find),
visit_mode_(visit_mode),
object_stack_(20),
no_allocation() {}
void VisitPointers(Object** start, Object** end) override;
void Reset();
void TracePathFrom(Object** root);
bool found() const { return found_target_; }
static Object* const kAnyGlobalObject;
protected:
class MarkVisitor;
class UnmarkVisitor;
void MarkRecursively(Object** p, MarkVisitor* mark_visitor);
void UnmarkRecursively(Object** p, UnmarkVisitor* unmark_visitor);
virtual void ProcessResults();
Object* search_target_;
bool found_target_;
bool found_target_in_trace_;
WhatToFind what_to_find_;
VisitMode visit_mode_;
List<Object*> object_stack_;
DisallowHeapAllocation no_allocation; // i.e. no gc allowed.
private:
DISALLOW_IMPLICIT_CONSTRUCTORS(PathTracer);
};
#endif // DEBUG
// -----------------------------------------------------------------------------
// Allows observation of allocations.
class AllocationObserver {
public:
explicit AllocationObserver(intptr_t step_size)
: step_size_(step_size), bytes_to_next_step_(step_size) {
DCHECK(step_size >= kPointerSize);
}
virtual ~AllocationObserver() {}
// Called each time the observed space does an allocation step. This may be
// more frequently than the step_size we are monitoring (e.g. when there are
// multiple observers, or when page or space boundary is encountered.)
void AllocationStep(int bytes_allocated, Address soon_object, size_t size) {
bytes_to_next_step_ -= bytes_allocated;
if (bytes_to_next_step_ <= 0) {
Step(static_cast<int>(step_size_ - bytes_to_next_step_), soon_object,
size);
step_size_ = GetNextStepSize();
bytes_to_next_step_ = step_size_;
}
}
protected:
intptr_t step_size() const { return step_size_; }
intptr_t bytes_to_next_step() const { return bytes_to_next_step_; }
// Pure virtual method provided by the subclasses that gets called when at
// least step_size bytes have been allocated. soon_object is the address just
// allocated (but not yet initialized.) size is the size of the object as
// requested (i.e. w/o the alignment fillers). Some complexities to be aware
// of:
// 1) soon_object will be nullptr in cases where we end up observing an
// allocation that happens to be a filler space (e.g. page boundaries.)
// 2) size is the requested size at the time of allocation. Right-trimming
// may change the object size dynamically.
// 3) soon_object may actually be the first object in an allocation-folding
// group. In such a case size is the size of the group rather than the
// first object.
virtual void Step(int bytes_allocated, Address soon_object, size_t size) = 0;
// Subclasses can override this method to make step size dynamic.
virtual intptr_t GetNextStepSize() { return step_size_; }
intptr_t step_size_;
intptr_t bytes_to_next_step_;
private:
friend class LargeObjectSpace;
friend class NewSpace;
friend class PagedSpace;
DISALLOW_COPY_AND_ASSIGN(AllocationObserver);
};
} // namespace internal
} // namespace v8
#endif // V8_HEAP_HEAP_H_
| [
"eric@flicket.tv"
] | eric@flicket.tv |
c15f7010501b1f50e86524aeaf358227595aea5e | 9bc6851e5cdf94882894a80640b08a1f1797aaff | /GXEngine/gx_particle.cpp | b290f05a69c8a0fd574e330f1fe2ef16621de1dd | [] | no_license | nwilsontech/gamesdk | 750762690041dfb7b0f8cd8134c8294cc3acfce0 | 8bbfaa702215caa8e4acd1b5cef24b9808ccd559 | refs/heads/master | 2021-05-30T03:01:51.604757 | 2015-12-24T02:03:20 | 2015-12-24T02:03:20 | 47,028,533 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 4,203 | cpp | #include "gx_particle.h"
#include <GL/gl.h>
#include <GL/glu.h>
GXParticle::GXParticle(int ID){
id = ID;
totalLife = 1.0f;
life = 1.0f;
alpha = 1.0f;
size = 1.0f;
bounciness = 0.9f;
active = true;
lasttime = -1;
angle = 0.0f;
}
void GXParticle::Update(long time)
{
if (!active)
return;
if (lasttime == -1)
lasttime = time;
float change = (float)(time-lasttime)/1000.0f;
velocity -= acceleration * change;//+
position -= velocity * change;//+
// float x = position.x;
// float y = position.y;
// float z = position.z;
if (position.y<0.0f){
velocity.y = velocity.y * -bounciness;
position.y = 0.0f;
}
const float fadeTime = 0.2f;
if (totalLife-life<fadeTime)
{
//glColor4f()
//change alpha
// ((totallife - life)/fadetime *alpha);
}else if (life < 1.0f){
/*
*(life *alpha);
*
*/
}else
{
// normal color;
}
glTranslatef(position.x,position.y,position.z);
life -= change;
if (life<0.0f)
active = false;
lasttime = time;
}
/***********************
* Emitter Class
***********************/
GXEmitter::GXEmitter(){
lastTime = -1;
tex = nullptr;
emissionRate = 10.0f;
emissionRadius = 0.0f;
life = 1.0f;
lifeRange = 0.5f;
size = 5.0f;
sizeRange = 2.0f;
saturation = 1.0f;
alpha = 0.5f;
spread = 1.0f;
gravity = 0.0f;
floor = 0.0f;
}
GXEmitter::~GXEmitter()
{
for(list<GXParticle *>::iterator it = particles.begin(); it!=particles.end(); it++){
delete (*it);
}
}
void GXEmitter::Update(long time){
if (tex==nullptr)
return;
if (lastTime==-1)
lastTime = time;
int numEmission = (int)((float)(time-lastTime)/1000.0 * emissionRate);
for(int i = 0; i < numEmission; i++)
addParticle();
if (numEmission > 0)
lastTime = time;
glDisable(GL_DEPTH_TEST);
glMatrixMode(GL_MODELVIEW);
glPushMatrix();
/**
* @brief Draw Sprites
*/
for(list<GXParticle *>::iterator it = particles.begin();it!=particles.end(); it++){
GXParticle *part = (*it);
part->floor = floor;
part->acceleration.y = -gravity;// -
//part->acceleration -= wind; // +
part->alpha = alpha;
part->rotation = rotation;
part->Update(time);
if ( part->active==false)
{
std::cout<<"\tdying\n";
delete part;
list<GXParticle *>::iterator pTemp = it--;
particles.erase(pTemp);
}
tex->theata = part->angle;
tex->SetCoord(part->position.x,
part->position.y,
part->position.z);
tex->SetSize(part->size,part->size);
tex->Draw();
}
glMatrixMode(GL_MODELVIEW);
glPopMatrix();
tex->theata = 0.0f;
}
void GXEmitter::SetTexture(GXSprite *texture){
tex = texture;
}
float GXEmitter::frand(float start, float end)
{
float num = (float)rand()/(float)RAND_MAX;
return (start + (end - start) * num);
}
void GXEmitter::addParticle(){
GXParticle *part = new GXParticle((int)particles.size());
// GenRandom Color
// float r = frand()*saturation+(1-saturation);
// float g = frand()*saturation+(1-saturation);
// float b = frand()*saturation+(1-saturation);
// part->color = Vec3(r,g,b);
part->angle = frand(0,360);
part->life = frand(life - lifeRange,life + lifeRange);
part->totalLife = part->life;
part->velocity = Vec3(frand(-spread,0),/*frand(-spread,spread)*/1,/*frand(-spread,spread)*/0);//Vec3(frand(-spread,spread),frand(3,20),frand(-spread,spread));
part->acceleration = Vec3(19*frand((-spread),0),-gravity,0);
part->size = frand(size-sizeRange,size+sizeRange);
part->position.x = position.x+frand(0,10);
part->position.y = position.y;//+frand(-emissionRadius,emissionRadius);
part->position.z = position.z;//+frand(-emissionRadius,emissionRadius);
particles.push_back(part);
}
| [
"nathaniel.wilson6@mycampus.apus.edu"
] | nathaniel.wilson6@mycampus.apus.edu |
f079f96ec5928710a524830e59b01faa111d872c | 5fa2292edcec6856b8cf6aa0374bf30d430d69af | /CPP_Exit_protoA/Source/CPP_Exit/Public/Arrow.h | 34d24dcbe31100c0f3a39c8c39d1b63a5d23aabc | [] | no_license | WhieJaeKim/EXIT_Project | cff6be3c900a19d5d58ce1383c868bc70cd9d007 | 9a5e9504bab1d1a882c321b5521a275784f83f72 | refs/heads/main | 2023-06-03T19:32:17.686849 | 2021-06-30T05:08:44 | 2021-06-30T05:08:44 | 380,975,277 | 0 | 0 | null | null | null | null | WINDOWS-1252 | C++ | false | false | 776 | h | // Fill out your copyright notice in the Description page of Project Settings.
#pragma once
#include "CoreMinimal.h"
#include "GameFramework/Actor.h"
#include "Arrow.generated.h"
UCLASS()
class CPP_EXIT_API AArrow : public AActor
{
GENERATED_BODY()
public:
UPROPERTY(VisibleAnywhere, Category = "Component")
class UBoxComponent* boxComp;
UPROPERTY(VisibleAnywhere, Category = "Component")
class UStaticMeshComponent* meshComp;
// À̵¿¼Óµµ
UPROPERTY(EditAnywhere, Category = "Stat")
float speed = 1000;
public:
// Sets default values for this actor's properties
AArrow();
protected:
// Called when the game starts or when spawned
virtual void BeginPlay() override;
public:
// Called every frame
virtual void Tick(float DeltaTime) override;
};
| [
"kwjlove1989@gmail.com"
] | kwjlove1989@gmail.com |
8e535157f9641fe7b33811100e21d54e6e80c6e7 | 00c00fd58b398b46cbf4ff46c1def997e8f63188 | /Candybowl_Server_MDNS/Candybowl_Server_MDNS.ino | 5c13c2062ea6610f090f084e238ff3a64382aa34 | [
"MIT"
] | permissive | tdicola/wifi_candybowl_monitor | 88185af50d6ebd35b01940676f9953b88d5b63bc | a6df6756f5267471eb3130164d3602ac4e7ba2ce | refs/heads/master | 2021-01-01T05:40:49.354115 | 2013-10-28T20:26:38 | 2013-10-28T20:26:38 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 6,329 | ino | /***************************************************
WiFi Candy Bowl Monitor With Multicast DNS Support
Monitor the status of your Halloween candy bowl remotely
with the CC3000 and an Arduino. This sketch uses and IR
sensor and LED to detect if a candy bowl is full or empty,
and exposes that sensor state to a WiFi network through a
simple telnet server. A multicast DNS query responder also
runs to make the telnet server available over the
'candybowl.local' address on your network.
See the Adafruit learning system guide for more details
and usage information:
http://learn.adafruit.com/wifi-candy-bowl/overview
License:
This example is copyright (c) 2013 Tony DiCola (tony@tonydicola.com)
and is released under an open source MIT license. See details at:
http://opensource.org/licenses/MIT
This code was adapted from Adafruit CC3000 library example
code which has the following license:
Designed specifically to work with the Adafruit WiFi products:
----> https://www.adafruit.com/products/1469
Adafruit invests time and resources providing this open source code,
please support Adafruit and open-source hardware by purchasing
products from Adafruit!
Written by Limor Fried & Kevin Townsend for Adafruit Industries.
BSD license, all text above must be included in any redistribution
****************************************************/
#include <Adafruit_CC3000.h>
#include <SPI.h>
#include <CC3000_MDNS.h>
// These are the interrupt and control pins
#define ADAFRUIT_CC3000_IRQ 3 // MUST be an interrupt pin!
// These can be any two pins
#define ADAFRUIT_CC3000_VBAT 5
#define ADAFRUIT_CC3000_CS 10
// Use hardware SPI for the remaining pins
// On an UNO, SCK = 13, MISO = 12, and MOSI = 11
Adafruit_CC3000 cc3000 = Adafruit_CC3000(ADAFRUIT_CC3000_CS, ADAFRUIT_CC3000_IRQ, ADAFRUIT_CC3000_VBAT,
SPI_CLOCK_DIV2); // you can change this clock speed
#define WLAN_SSID "myNetwork" // cannot be longer than 32 characters!
#define WLAN_PASS "myPassword"
// Security can be WLAN_SEC_UNSEC, WLAN_SEC_WEP, WLAN_SEC_WPA or WLAN_SEC_WPA2
#define WLAN_SECURITY WLAN_SEC_WPA2
#define LISTEN_PORT 23 // What TCP port to listen on for connections.
#define IR_LED 8 // Digital pin that is hooked up to the IR LED.
#define IR_SENSOR 7 // Digital pin that is hooked up to the IR sensor.
// Create an instance of the CC3000 server listening on the specified port.
Adafruit_CC3000_Server candyServer(LISTEN_PORT);
// Create an instance of the multicast DNS query responder.
MDNSResponder mdns;
void setup(void)
{
// Set up the input and output pins.
pinMode(IR_LED, OUTPUT);
pinMode(IR_SENSOR, INPUT);
// Set up the serial port connection.
Serial.begin(115200);
Serial.println(F("Hello, CC3000!\n"));
// Set up the CC3000, connect to the access point, and get an IP address.
Serial.println(F("\nInitializing..."));
if (!cc3000.begin())
{
Serial.println(F("Couldn't begin()! Check your wiring?"));
while(1);
}
if (!cc3000.connectToAP(WLAN_SSID, WLAN_PASS, WLAN_SECURITY)) {
Serial.println(F("Failed!"));
while(1);
}
Serial.println(F("Connected!"));
Serial.println(F("Request DHCP"));
while (!cc3000.checkDHCP())
{
delay(100);
}
while (!displayConnectionDetails()) {
delay(1000);
}
// Set up the multicast DNS query responder to resolve 'candybowl.local' address queries.
if (!mdns.begin("candybowl", cc3000, 3600)) {
Serial.println("Error setting up MDNS responder!");
while(1);
}
// Start the candy bowl server.
candyServer.begin();
Serial.println(F("Listening for connections..."));
}
void loop(void)
{
// Handle any multicast DNS requests
mdns.update();
// Handle a connected client.
Adafruit_CC3000_ClientRef client = candyServer.available();
if (client) {
// Check if there is data available to read.
if (client.available() > 0) {
uint8_t ch = client.read();
// Respond to candy a bowl status query.
if (ch == '?') {
client.fastrprint("Candy bowl status: ");
if (isBowlFull()) {
client.fastrprintln("FULL");
}
else {
client.fastrprintln("LOW");
}
}
}
}
}
// Return true if the bowl is detected to be full.
boolean isBowlFull() {
// Pulse the IR LED at 38khz for 1 millisecond
pulseIR(1000);
// Check if the IR sensor picked up the pulse (i.e. output wire went to ground).
if (digitalRead(IR_SENSOR) == LOW) {
return false; // Sensor can see LED, return not full.
}
return true; // Sensor can't see LED, return full.
}
// 38khz IR pulse function from Adafruit tutorial: http://learn.adafruit.com/ir-sensor/overview
void pulseIR(long microsecs) {
// we'll count down from the number of microseconds we are told to wait
cli(); // this turns off any background interrupts
while (microsecs > 0) {
// 38 kHz is about 13 microseconds high and 13 microseconds low
digitalWrite(IR_LED, HIGH); // this takes about 3 microseconds to happen
delayMicroseconds(10); // hang out for 10 microseconds, you can also change this to 9 if its not working
digitalWrite(IR_LED, LOW); // this also takes about 3 microseconds
delayMicroseconds(10); // hang out for 10 microseconds, you can also change this to 9 if its not working
// so 26 microseconds altogether
microsecs -= 26;
}
sei(); // this turns them back on
}
// Display connection details like the IP address.
bool displayConnectionDetails(void)
{
uint32_t ipAddress, netmask, gateway, dhcpserv, dnsserv;
if(!cc3000.getIPAddress(&ipAddress, &netmask, &gateway, &dhcpserv, &dnsserv))
{
Serial.println(F("Unable to retrieve the IP Address!\r\n"));
return false;
}
else
{
Serial.print(F("\nIP Addr: ")); cc3000.printIPdotsRev(ipAddress);
Serial.print(F("\nNetmask: ")); cc3000.printIPdotsRev(netmask);
Serial.print(F("\nGateway: ")); cc3000.printIPdotsRev(gateway);
Serial.print(F("\nDHCPsrv: ")); cc3000.printIPdotsRev(dhcpserv);
Serial.print(F("\nDNSserv: ")); cc3000.printIPdotsRev(dnsserv);
Serial.println();
return true;
}
}
| [
"tony@tonydicola.com"
] | tony@tonydicola.com |
198c3848208dea91116276fce2450e4cc6a0c8f6 | 01eb13ca8b6e93591359d25243fb7939c8077d4c | /PVStreamer/common/ConfigManager.cpp | 84c2445ff2022c9fab7b59792f44dd299dc1b6c6 | [
"BSD-3-Clause"
] | permissive | ADARA-Neutrons/adara | a961ea16a1ec17fda5bd31eb50c2a9b850c0f97c | 634a30e8238e247f2312e547e787da3012e20d06 | refs/heads/master | 2023-03-03T13:38:24.265049 | 2023-02-28T22:04:48 | 2023-02-28T22:04:48 | 19,054,234 | 2 | 3 | BSD-3-Clause | 2023-02-28T22:04:49 | 2014-04-23T02:31:49 | C++ | UTF-8 | C++ | false | false | 29,927 | cpp | #include <set>
#include <boost/lexical_cast.hpp>
#include "ConfigManager.h"
#include "StreamService.h"
#include "ADARA.h" // Needed for PV status bits
#include <syslog.h>
#include <unistd.h>
using namespace std;
namespace PVS {
//=============================================================================
//===== PUBLIC METHODS ========================================================
ConfigManager::ConfigManager( uint32_t a_offset )
: m_stream_api(0), m_offset(a_offset)
{}
ConfigManager::~ConfigManager()
{}
void
ConfigManager::attach( IInputAdapterAPI *a_stream_api )
{
boost::lock_guard<boost::mutex> lock(m_mutex);
m_stream_api = a_stream_api;
}
DeviceRecordPtr
ConfigManager::getDeviceConfig( const string &a_device_name, const string &a_source, Protocol a_protocol )
{
boost::lock_guard<boost::mutex> lock(m_mutex);
string key = makeDeviceKey( a_device_name, a_source, a_protocol );
map<string,DeviceRecordPtr>::iterator idev = m_devices.find( key );
if ( idev != m_devices.end())
{
DeviceRecordPtr dev( idev->second );
return dev;
}
return DeviceRecordPtr();
}
/**
* This method compares the provided device descriptor with any current
* configuration records and will either define a new device, redefine an
* existing device, or take no action if none is required.
*/
DeviceRecordPtr
ConfigManager::defineDevice( DeviceDescriptor &a_descriptor,
bool &a_device_changed )
{
// syslog( LOG_DEBUG, "ConfigMgr::defineDevice(): [%s] %s/%lu",
// a_descriptor.m_name.c_str(), a_descriptor.m_source.c_str(),
// (unsigned long)a_descriptor.m_protocol );
// usleep(33333); // give syslog a chance...
boost::lock_guard<boost::mutex> lock(m_mutex);
DeviceRecordPtr record;
a_device_changed = false;
// Compare to the latest configuration records
string key = makeDeviceKey( a_descriptor.m_name, a_descriptor.m_source,
a_descriptor.m_protocol );
map<string,DeviceRecordPtr>::iterator idev = m_devices.find( key );
// This is an existing device
if ( idev != m_devices.end() )
{
// Note: DeviceDescriptor's Operator== Does _Not_ Compare
// Device ID (m_id), Active Status PV or Ready Status (m_ready)!
if ( a_descriptor == *idev->second )
{
// Check for Device ID Re-Numbered...
if ( a_descriptor.m_id != idev->second->m_id )
{
syslog( LOG_ERR, "%s %s: %s: [%s] %s/%lu, (%s %d -> %d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device Definition Unchanged",
a_descriptor.m_name.c_str(),
a_descriptor.m_source.c_str(),
(unsigned long) a_descriptor.m_protocol,
"*** Device ID Re-Numbered",
idev->second->m_id, a_descriptor.m_id );
usleep(33333); // give syslog a chance...
DeviceDescriptor *new_desc = new DeviceDescriptor(
*idev->second ); // Deep Copy, Keep ID!
new_desc->m_id = a_descriptor.m_id;
// Device ID Changed, Use New Descriptor...
record = DeviceRecordPtr(new_desc);
sendDeviceRedefined( record, idev->second );
idev->second = record;
a_device_changed = true;
}
else
{
syslog( LOG_INFO, "%s: %s: [%s] %s/%lu (Device ID=%d)",
"ConfigManager::defineDevice()",
"Device Definition Unchanged",
a_descriptor.m_name.c_str(),
a_descriptor.m_source.c_str(),
(unsigned long) a_descriptor.m_protocol,
a_descriptor.m_id );
usleep(33333); // give syslog a chance...
// Descriptor has not changed, just return existing record
record = idev->second;
}
// Make Sure Any Updated Active Status PV is Used...
if ( !a_descriptor.m_active_pv_conn.empty() )
{
// If the Active Status PV Changed, Re-Create It...
if ( a_descriptor.m_active_pv_conn.compare(
record->m_active_pv_conn ) )
{
syslog( LOG_ERR,
"%s %s: %s: [%s] (%s: [%s] -> [%s], %s = %d (%s))",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Re-Creating Active Status PV",
a_descriptor.m_name.c_str(),
"*** Active Status PV Connection Changed",
record->m_active_pv_conn.c_str(),
a_descriptor.m_active_pv_conn.c_str(),
"active", a_descriptor.m_active,
( a_descriptor.m_active ) ? "true" : "false" );
usleep(33333); // give syslog a chance...
delete record->m_active_pv;
record->m_active_pv_conn =
a_descriptor.m_active_pv_conn;
record->m_active_pv = new PVDescriptor(
record.get(), *(a_descriptor.m_active_pv) );
record->m_active = a_descriptor.m_active;
}
}
// Otherwise, Clear Out Any Active Status Meta-Data...
else if ( !record->m_active_pv_conn.empty() )
{
syslog( LOG_ERR, "%s %s: %s: [%s] (%s: [%s] -> [])",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Removing Active Status PV",
a_descriptor.m_name.c_str(),
"New Descriptor No Longer Has Active Status PV",
record->m_active_pv_conn.c_str() );
usleep(33333); // give syslog a chance...
delete record->m_active_pv;
record->m_active_pv_conn.clear();
record->m_active = true;
}
}
else
{
// The descriptor is not identical to existing record,
// analyze differences
if ( a_descriptor.m_id != idev->second->m_id )
{
syslog( LOG_ERR,
"%s %s: Re-defining Device: [%s] %s/%lu (%s %d -> %d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
a_descriptor.m_name.c_str(),
a_descriptor.m_source.c_str(),
(unsigned long) a_descriptor.m_protocol,
"*** Device ID Re-Numbered",
idev->second->m_id, a_descriptor.m_id );
usleep(33333); // give syslog a chance...
}
else
{
syslog( LOG_ERR,
"%s %s: Re-defining Device: [%s] %s/%lu (Device ID=%d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
a_descriptor.m_name.c_str(),
a_descriptor.m_source.c_str(),
(unsigned long) a_descriptor.m_protocol,
idev->second->m_id );
usleep(33333); // give syslog a chance...
}
// Record is different, must make new record but
// try to re-use identifiers
DeviceDescriptor *new_desc = new DeviceDescriptor(
a_descriptor ); // Deep Copy, Keep ID!
// Initialize New Descriptor PV IDs to Zero (just to be sure!)
if ( new_desc->m_active_pv
&& !(new_desc->m_active_pv->m_ignore) )
{
new_desc->m_active_pv->m_id = 0;
}
vector<PVDescriptor*>::iterator ipv;
for ( ipv = new_desc->m_pvs.begin();
ipv != new_desc->m_pvs.end(); ++ipv )
{
(*ipv)->m_id = 0;
}
// Create PV IDs Set: Sorted Unique Element List
// - Use for Generating Guaranteed-Unique *New* PV Ids...! ;-D
std::set<Identifier> pv_ids;
// Clean Up Any Old Active Status PV that Subsumed a Device PV
if ( idev->second->m_active_pv
&& !(idev->second->m_active_pv->m_ignore) )
{
bool used_id = false;
// Does the New Device's Active Status PV Also Subsume a PV?
if ( new_desc->m_active_pv
&& !(new_desc->m_active_pv->m_ignore) )
{
// Re-Use Active Status PV ID, They're the Same PV...
// (Consider Diff Alias Name as Diff PV for Bookkeeping)
if ( !(new_desc->m_active_pv->m_name.compare(
idev->second->m_active_pv->m_name ))
&& !(new_desc->m_active_pv->m_connection.compare(
idev->second->m_active_pv->m_connection )) )
{
new_desc->m_active_pv->m_id =
idev->second->m_active_pv->m_id;
pv_ids.insert( new_desc->m_active_pv->m_id );
used_id = true;
syslog( LOG_INFO,
"%s: %s [%s] (%s=%d) %s <%s> (%s) - %s PV ID=%d",
"ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
"Active Status PV Persists",
new_desc->m_active_pv->m_name.c_str(),
new_desc->m_active_pv->m_connection.c_str(),
"Keep", new_desc->m_active_pv->m_id );
usleep(33333); // give syslog a chance...
}
}
// If Old Active Status PV ID Not Used,
// Just Clean Up the Old Active Statue PV...
if ( !used_id )
{
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d) %s <%s> (%s) (PV ID=%d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
"Undefining Old Active Status PV",
idev->second->m_active_pv->m_name.c_str(),
idev->second->m_active_pv->m_connection.c_str(),
idev->second->m_active_pv->m_id );
usleep(33333); // give syslog a chance...
sendPvUndefined( idev->second,
idev->second->m_active_pv );
}
}
// Check Old Descriptor PVs against New Descriptor's PVs...
// - If Found, Re-Use PV ID...
// - Else, Send PV Disconnected Packet...
for ( ipv = idev->second->m_pvs.begin();
ipv != idev->second->m_pvs.end(); ++ipv )
{
PVDescriptor *new_pv;
// Send PV Disconnected Packet for Old PVs that are
// Not in New Descriptor
if ( !(new_pv = new_desc->getPvByName( (*ipv)->m_name )) )
{
syslog( LOG_ERR,
"%s %s: %s [%s] (Device ID=%d) %s <%s> (%s) (PV ID=%d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(), new_desc->m_id,
"Undefining Old PV",
(*ipv)->m_name.c_str(),
(*ipv)->m_connection.c_str(),
(*ipv)->m_id );
usleep(33333); // give syslog a chance...
sendPvUndefined( idev->second, *ipv );
}
// Otherwise, Steal the PV ID from the Old Descriptor
// (for consistency, as amenable... :-)
else
{
new_pv->m_id = (*ipv)->m_id;
pv_ids.insert( new_pv->m_id );
syslog( LOG_INFO,
"%s: %s [%s] (Device ID=%d) %s <%s> (%s) - %s PV ID=%d",
"ConfigManager::defineDevice()", "Device",
new_desc->m_name.c_str(), new_desc->m_id,
"PV Persists",
new_pv->m_name.c_str(),
new_pv->m_connection.c_str(),
"Keep", new_pv->m_id );
usleep(33333); // give syslog a chance...
}
}
// Now Generate Any (Guaranteed-Unique) *New* PV Ids...! ;-D
Identifier next_id = 1;
// Check If the New Active Status PV Subsumed a Device PV
// And Needs a PV ID... ;-D
if ( new_desc->m_active_pv
&& !(new_desc->m_active_pv->m_ignore)
&& new_desc->m_active_pv->m_id == 0 )
{
// Find a Free ID
// (Not Re-Used from Old IDs or a Recent New...)
std::set<Identifier>::iterator idi;
while ( (idi = pv_ids.find( next_id )) != pv_ids.end() )
next_id++;
new_desc->m_active_pv->m_id = next_id++;
// Mark this PV ID, to be sure for the next guy... ;-D
pv_ids.insert( new_desc->m_active_pv->m_id );
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d) %s <%s> (%s) - %s PV ID=%d",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
"Found New Active Status PV",
new_desc->m_active_pv->m_name.c_str(),
new_desc->m_active_pv->m_connection.c_str(),
"Assign", new_desc->m_active_pv->m_id );
usleep(33333); // give syslog a chance...
}
for ( ipv = new_desc->m_pvs.begin();
ipv != new_desc->m_pvs.end(); ++ipv )
{
// Need a New PV Id...
if ( (*ipv)->m_id == 0 )
{
// New PV, Find a Free ID
// (Not Re-Used from Old IDs or a Recent New...)
std::set<Identifier>::iterator idi;
while ( (idi = pv_ids.find( next_id )) != pv_ids.end() )
next_id++;
(*ipv)->m_id = next_id++;
// Mark this PV ID, to be sure for the next guy... ;-D
pv_ids.insert( (*ipv)->m_id );
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d) %s <%s> (%s) - %s PV ID=%d",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
"Found New PV",
(*ipv)->m_name.c_str(),
(*ipv)->m_connection.c_str(),
"Assign", (*ipv)->m_id );
usleep(33333); // give syslog a chance...
}
}
// Now Ensure All New PV Names are Unique
makePvNamesUnique( key, *new_desc );
// Move old record to trash, and save new record
record = DeviceRecordPtr(new_desc);
sendDeviceRedefined( record, idev->second );
idev->second = record;
a_device_changed = true;
}
}
// This is a NEW device
else
{
// No existing record, create a new one copied from the
// passed-in descriptor
DeviceDescriptor *new_desc =
new DeviceDescriptor( a_descriptor ); // Deep Copy, Keep ID!
syslog( LOG_ERR,
"%s %s: Defining New Device: [%s] %s/%lu (Device ID=%d)",
"PVSD ERROR:", "ConfigManager::defineDevice()",
a_descriptor.m_name.c_str(), a_descriptor.m_source.c_str(),
(unsigned long) a_descriptor.m_protocol,
new_desc->m_id );
usleep(33333); // give syslog a chance...
// PV IDs can be assigned arbitrarily for new devices
Identifier id = 1;
if ( new_desc->m_active_pv
&& !(new_desc->m_active_pv->m_ignore) )
{
new_desc->m_active_pv->m_id = id++;
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d) %s <%s> (%s) - Assign PV ID=%d",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
"New Active Status PV",
new_desc->m_active_pv->m_name.c_str(),
new_desc->m_active_pv->m_connection.c_str(),
new_desc->m_active_pv->m_id );
usleep(33333); // give syslog a chance...
}
for ( vector<PVDescriptor*>::iterator ipv = new_desc->m_pvs.begin();
ipv != new_desc->m_pvs.end(); ++ipv )
{
(*ipv)->m_id = id++;
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d) New PV <%s> (%s) - Assign PV ID=%d",
"PVSD ERROR:", "ConfigManager::defineDevice()",
"Device", new_desc->m_name.c_str(),
"Device ID", new_desc->m_id,
(*ipv)->m_name.c_str(),
(*ipv)->m_connection.c_str(),
(*ipv)->m_id );
usleep(33333); // give syslog a chance...
}
// Ensure all new PV names are unique
makePvNamesUnique( key, *new_desc );
// Store new record in devices vector
record = DeviceRecordPtr(new_desc);
m_devices[key] = record;
sendDeviceDefined( record );
a_device_changed = true;
}
return record;
}
/**
* @brief Removes a device from configuration database
* @param a_record - Device to undefine
*
* This method undefines a device (removes from configuration database).
* This method results in stream packets being emitted to set the
* undefined device PVs to "disconnected" state, followed by a
* "device undefined" packet. Note that the device pointers in these
* messages are shared pointer, so the device record will persist
* until the emitted packets are consumed and cleared (even if device
* is actually deleted).
*/
void
ConfigManager::undefineDevice( DeviceRecordPtr &a_record,
bool a_delete_device )
{
syslog( LOG_ERR,
"%s %s: Un-defining device: [%s] %s/%lu (Device ID=%d) %s=%u",
"PVSD ERROR:", "ConfigManager::undefineDevice()",
a_record->m_name.c_str(), a_record->m_source.c_str(),
(unsigned long)a_record->m_protocol, a_record->m_id,
"delete_device", a_delete_device );
usleep(33333); // give syslog a chance...
boost::lock_guard<boost::mutex> lock(m_mutex);
// Compare to the latest configuration records
// (those in trash don't matter)
string key = makeDeviceKey(
a_record->m_name, a_record->m_source, a_record->m_protocol );
map<string,DeviceRecordPtr>::iterator idev = m_devices.find( key );
if ( idev != m_devices.end())
{
// Send PV disconnected packets for old PVs
// (that are not in new descriptor, if being re-defined...)
for ( vector<PVDescriptor*>::iterator ipv =
idev->second->m_pvs.begin();
ipv != idev->second->m_pvs.end(); ++ipv )
{
sendPvUndefined( idev->second, *ipv );
}
// Actually Delete the Device (All the Way Down the Pipeline...)
if ( a_delete_device )
{
sendDeviceUndefined( idev->second );
m_devices.erase( idev );
}
}
}
//=============================================================================
//===== PRIVATE METHODS =======================================================
/**
* @brief Generates a locally unique string identifier for device
* @param a_device_name - Name of device
* @param a_source - Name of source (or host)
* @param a_protocol - Protocal
* @return A string identifier (key) for device
*/
string
ConfigManager::makeDeviceKey( const string &a_device_name, const string &a_source, Protocol a_protocol ) const
{
return a_device_name + boost::lexical_cast<string>(a_protocol) + a_source;
}
/**
* @brief This method ensures PV names on device are unique
* @param a_key - Device map key for device being checked
* @param a_descriptor - Descriptor for device being checked
*
* This method examines the PV names of the specified descriptor against
* all currently configured PVs except for a descriptor being redefined
* (i.e. with the same key). If a conflict is found the new conflicting PV
* is renamed by appending a "_dupX" suffix (where X is a conflict counter)
* and checked again. This continues until all conflicts have been resolved.
*
* This step tries to ensure that ADARA clients will receive PVs with
* unique names. PV names are required to be unique, and this routine is
* a "just-in-case" measure to prevent editing errors from causing serious
* client issues. This method cannot prevent other data sources from
* injecting Device Descriptor packets with conflicting names. This
* condition must be trapped by the SMS.
*
* Addendum: As of the end of 2018, the ADARA STC has gotten much smarter
* about recognizing "Duplicate PVs" and Collapsing any redundant values
* into a single Merged PV Log. So we can be more cavalier now too,
* and only look for PV Name/Alias Clashes that are Distinct from the
* EPICS PV Connection Strings. It's actually "Ok" now to have the
* Same PV requested in Multiple Devices, just no Name/Alias Clashes...! ;-D
*/
void
ConfigManager::makePvNamesUnique( const string &a_key,
DeviceDescriptor &a_descriptor )
{
vector<PVDescriptor*>::const_iterator ipv;
set<string> names;
set<string>::iterator inames;
for ( map<string,DeviceRecordPtr>::iterator idev = m_devices.begin();
idev != m_devices.end(); ++idev )
{
// Skip device being redefined
if ( idev->first == a_key )
continue;
for ( ipv = idev->second->m_pvs.begin();
ipv != idev->second->m_pvs.end(); ++ipv )
{
// Only Consider Names/Aliases that are Distinct from
// the Given PV's Connection String... ;-D
if ( (*ipv)->m_name.compare( (*ipv)->m_connection ) )
names.insert( (*ipv)->m_name );
}
}
string new_name;
unsigned short count;
for ( ipv = a_descriptor.m_pvs.begin();
ipv != a_descriptor.m_pvs.end(); ++ipv )
{
// Only Check Names/Aliases that are Distinct from
// the Given PV's Connection String... ;-D
if ( !(*ipv)->m_name.compare( (*ipv)->m_connection ) )
continue;
count = 0;
new_name = (*ipv)->m_name;
while ( 1 )
{
if ( count )
{
new_name = (*ipv)->m_name + "_dup"
+ boost::lexical_cast<string>(count);
}
if ( names.find( new_name ) != names.end() )
++count;
else
break;
}
// Only Change the Name as Needed... ;-D
if ( count )
{
syslog( LOG_ERR,
"%s %s: %s [%s] (%s=%d): %s <%s> to <%s> (%s) (PV ID=%d)!",
"PVSD ERROR:", "ConfigManager::makePvNamesUnique()",
"Device", a_descriptor.m_name.c_str(),
"Device ID", a_descriptor.m_id,
"Renaming Name-Clash PV from",
(*ipv)->m_name.c_str(), new_name.c_str(),
(*ipv)->m_connection.c_str(), (*ipv)->m_id );
usleep(33333); // give syslog a chance...
(*ipv)->m_name = new_name;
}
}
}
void
ConfigManager::sendDeviceDefined( DeviceRecordPtr a_dev_desc )
{
bool timeout;
StreamPacket *pkt = m_stream_api->getFreePacket( 5000, timeout );
if ( pkt )
{
pkt->type = DeviceDefined;
pkt->device = a_dev_desc;
m_stream_api->putFilledPacket( pkt );
}
else
{
if ( m_stream_api->getFreeQueueActive() )
{
syslog( LOG_ERR,
"%s %s: %s! Device [%s] (Device ID=%d) %s! [%s = %lu]",
"PVSD ERROR:", "ConfigManager::sendDeviceDefined()",
"No Free Packets",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id,
"Descriptor Lost",
"Filled Queue Size",
(unsigned long) m_stream_api->getFilledQueueSize() );
usleep(33333); // give syslog a chance...
}
else
{
syslog( LOG_ERR,
"%s %s: %s, Ignore Define Device [%s] (Device ID=%d)",
"PVSD ERROR:", "ConfigManager::sendDeviceDefined()",
"Queue Deactivated",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id );
usleep(33333); // give syslog a chance...
}
}
}
void
ConfigManager::sendDeviceUndefined( DeviceRecordPtr a_dev_desc )
{
bool timeout;
StreamPacket *pkt = m_stream_api->getFreePacket( 5000, timeout );
if ( pkt )
{
pkt->type = DeviceUndefined;
pkt->device = a_dev_desc;
m_stream_api->putFilledPacket( pkt );
}
else
{
if ( m_stream_api->getFreeQueueActive() )
{
syslog( LOG_ERR,
"%s %s: %s! Device [%s] (Device ID=%d) %s! [%s = %lu]",
"PVSD ERROR:", "ConfigManager::sendDeviceUndefined()",
"No Free Packets",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id,
"Undefined Lost",
"Filled Queue Size",
(unsigned long) m_stream_api->getFilledQueueSize() );
usleep(33333); // give syslog a chance...
}
else
{
syslog( LOG_ERR,
"%s %s: %s, Ignore Undefine Device [%s] (Device ID=%d)",
"PVSD ERROR:", "ConfigManager::sendDeviceUndefined()",
"Queue Deactivated",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id );
usleep(33333); // give syslog a chance...
}
}
}
void
ConfigManager::sendDeviceRedefined( DeviceRecordPtr a_dev_desc,
DeviceRecordPtr a_old_dev_desc )
{
bool timeout;
StreamPacket *pkt = m_stream_api->getFreePacket( 5000, timeout );
if ( pkt )
{
pkt->type = DeviceRedefined;
pkt->device = a_dev_desc;
pkt->old_device = a_old_dev_desc;
m_stream_api->putFilledPacket( pkt );
}
else
{
if ( m_stream_api->getFreeQueueActive() )
{
syslog( LOG_ERR,
"%s %s: %s! %s [%s] (%s [%s]) (%s=%d) %s! [%s = %lu]",
"PVSD ERROR:", "ConfigManager::sendDeviceRedefined()",
"No Free Packets", "Device", a_dev_desc->m_name.c_str(),
"Old", a_old_dev_desc->m_name.c_str(),
"Device ID", a_dev_desc->m_id, "Descriptor Update Lost",
"Filled Queue Size",
(unsigned long) m_stream_api->getFilledQueueSize() );
usleep(33333); // give syslog a chance...
}
else
{
syslog( LOG_ERR,
"%s %s: %s, Ignore Redefine Device [%s] (Device ID=%d)",
"PVSD ERROR:", "ConfigManager::sendDeviceRedefined()",
"Queue Deactivated",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id );
usleep(33333); // give syslog a chance...
}
}
}
void
ConfigManager::sendPvUndefined( DeviceRecordPtr a_dev_desc, PVDescriptor *a_pv_desc )
{
bool timeout;
StreamPacket *pkt = m_stream_api->getFreePacket( 5000, timeout );
if ( pkt )
{
pkt->type = VariableUpdate;
pkt->device = a_dev_desc;
pkt->pv = a_pv_desc;
pkt->state = PVState(
::ADARA::VariableStatus::UPSTREAM_DISCONNECTED,
::ADARA::VariableSeverity::INVALID );
pkt->state.m_time.sec = (uint32_t)time(0) - EPICS_TIME_OFFSET;
pkt->state.m_time.nsec = 0;
m_stream_api->putFilledPacket( pkt );
}
else
{
if ( m_stream_api->getFreeQueueActive() )
{
syslog( LOG_ERR,
"%s %s: %s! %s [%s] (%s=%d) PV <%s> (%s) (PV ID=%d) %s! [%s = %lu]",
"PVSD ERROR:", "ConfigManager::sendPvUndefined()",
"No Free Packets", "Device", a_dev_desc->m_name.c_str(),
"Device ID", a_dev_desc->m_id,
a_pv_desc->m_name.c_str(),
a_pv_desc->m_connection.c_str(),
a_pv_desc->m_id, "Undefined Lost",
"Filled Queue Size",
(unsigned long) m_stream_api->getFilledQueueSize() );
usleep(33333); // give syslog a chance...
}
else
{
syslog( LOG_ERR,
"%s %s: %s Device [%s] (Device ID=%d) PV <%s> (%s) (PV ID=%d)",
"PVSD ERROR:", "ConfigManager::sendPvUndefined()",
"Queue Deactivated, Ignore PV Undefine",
a_dev_desc->m_name.c_str(), a_dev_desc->m_id,
a_pv_desc->m_name.c_str(),
a_pv_desc->m_connection.c_str(),
a_pv_desc->m_id );
usleep(33333); // give syslog a chance...
}
}
}
}
// vim: expandtab
| [
"kohlja@ornl.gov"
] | kohlja@ornl.gov |
3f8d3ae2e0a0c15e4afd7c8ec43dd739bc011ceb | 6fe2b5b4c38d41cea343a6586b17192f20bb688e | /main.cpp | 649432e8d4abe72c407c83aff0433ee728dbdd06 | [] | no_license | knewyousir/avlTree | a6da0742a973c1899ebaea9a432b1227fad2ddc9 | 17081c5cf5c2c3bf9d0641a0c624bfe2c2c4513b | refs/heads/master | 2020-04-07T18:08:21.359192 | 2018-11-21T19:49:22 | 2018-11-21T19:49:22 | 158,598,560 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 4,994 | cpp | #include<iostream>
using std::cin;
using std::cout;
using std::endl;
template<class T>
class RBT;
template<class T>
class RBTNode{
T data;
RBTNode<T>* parent, *left, *right;
bool isRed;
public:
friend class RBT<T>;
RBTNode(const T& newData = T(), RBTNode<T>* newParent = nullptr,
RBTNode<T>* newLeft = nullptr, RBTNode<T>* newRight = nullptr, bool isRed = 1) :
data(newData), parent(newParent), left(newLeft), right(newRight), isRed(isRed) {;}
void printInOrder()const{
if (left != nullptr)
left->printInOrder();
cout << data << endl;
if (right != nullptr)
right->printInOrder();
}
};
template<class T>
class RBT{
RBTNode<T>* root;
public:
RBT() : root(nullptr) {}
//Big 3
RBT(const RBT<T>& rhs) : root(nullptr) {*this = rhs; }
// virtual ~RBT() { clear(); } //Not needed since we aren't implementing removals
RBT& operator=(const RBT<T>& rhs);
void insert(const T& toInsert);
void insertFix(RBTNode<T>* toFix);
void singleCR(RBTNode<T>*& target);
void singleCCR(RBTNode<T>*& target);
void printInOrder() const { root->printInOrder(); }
};
int main(){
RBT<int> theTree;
int input;
while(true){
cout<<"Please enter a positive integer, -2 to print, or -1 to exit: ";
cin>>input;
if(input == -1)
break;
else if(input == -2)
theTree.printInOrder();
else if(input > -1)
theTree.insert(input);
else
cout<<"Bad input detected. Try again!"<<endl;
}
cout<<"program exited safely!"<<endl;
return 1;
}
template <class T>
void RBT<T>::insert(const T& toInsert){
// size++;
if (root == nullptr){
cout<<"root == nullptr!"<<endl;
root = new RBTNode<T>(toInsert);
root->isRed = 0;
}
else{
RBTNode<T>* temp = root;
RBTNode<T>* prev = temp;
while (temp != nullptr){
prev = temp;
if (toInsert < temp->data){
cout<<"slotted left!"<<endl;
temp = temp->left;
}
else{
cout<<"slotted right!"<<endl;
temp = temp->right;
}
}
//now temp points to null and prev points to the node we want to insert onto
if (toInsert < prev->data){ //insert onto the left of Prev
prev->left = new RBTNode<T>(toInsert, prev);
cout<<"inserted left!"<<endl;
if(prev != nullptr)
insertFix(prev->left);
}
else{
prev->right = new RBTNode<T>(toInsert, prev);
cout<<"inserted right!"<<endl;
if(prev != nullptr)
insertFix(prev->right);
}
}
return;
}
template<class T>
void RBT<T>::insertFix(RBTNode<T>* toFix){
RBTNode<T>* temp;
if(root == toFix){
toFix->isRed = 0; //isBlack
return;
}
while(toFix->parent != nullptr && toFix->parent->isRed == 1){
cout<<"toFix parent is red!"<<endl;
RBTNode<T>* gdprnt = toFix->parent->parent;
if(gdprnt->left == toFix->parent){
cout<<"toFix parent is on gdprnt left!"<<endl;
if(gdprnt->right != nullptr){
cout<<"gdprnt right is not null!"<<endl;
temp = gdprnt->right;
if(temp->isRed == 1){
toFix->parent->isRed = 0;
temp->isRed = 0;
gdprnt->isRed = 1;
toFix = gdprnt;
}
}
else{
cout<<"gdprnt right is null!"<<endl;
if(toFix->parent->right == toFix){
toFix = toFix->parent;
singleCCR(toFix);
}
toFix->parent->isRed = 0;
gdprnt->isRed = 1;
singleCR(gdprnt);
}
}
else{
cout<<"toFix parent is on gdprnt right!"<<endl;
if(gdprnt->left != nullptr){
cout<<"gdprnt left is not null!"<<endl;
temp = gdprnt->left;
if(temp->isRed == 1){
toFix->parent->isRed = 0;
temp->isRed = 0;
gdprnt->isRed = 1;
toFix = gdprnt;
}
}
else{
cout<<"gdprnt left is null!"<<endl;
if(toFix->parent->left == toFix){
toFix = toFix->parent;
singleCR(toFix);
}
toFix->parent->isRed = 0;
gdprnt->isRed = 1;
singleCCR(gdprnt);
}
}
root->isRed = 0;
}
return;
}
template<class T>
void RBT<T>::singleCR(RBTNode<T>*& target){
cout<<"started single CR!"<<endl;
if(target->left == nullptr)
return;
else{
RBTNode<T>* temp = target->left;
if(temp->right != nullptr){
target->left = target->right;
temp->right->parent = target;
}
else
target->left = nullptr;
if(target->parent != nullptr)
temp->parent = target->parent;
if(target->parent == nullptr)
root = temp;
else{
if(target == target->parent->left)
target->parent->left = temp;
else
target->parent->right = temp;
}
temp->right = target;
target->parent = temp;
}
return;
}
template<class T>
void RBT<T>::singleCCR(RBTNode<T>*& target){
cout<<"started single CCR!"<<endl;
if(target->right == nullptr)
return;
else{
RBTNode<T>* temp = target->right;
if(target->left != nullptr){
target->right = temp->left;
temp->left->parent = target;
}
else
target->right = nullptr;
if(target->parent != nullptr)
temp->parent = target->parent;
if(target->parent == nullptr)
root = temp;
else{
if(target == target->parent->left)
target->parent->left = temp;
else
target->parent->right = temp;
}
temp->left = target;
target->parent = temp;
}
return;
}
| [
"noreply@github.com"
] | knewyousir.noreply@github.com |
8a61b19e3c646bd168efc4f481581d5c4f53e372 | 2a227eef64b4914c7aefddc4ca89791839406164 | /tutorials/tutorial7/include/tutorial7/dispatch/DispatchMessage.h | 82d8624ce88c61a6ff9f68a04908c877d3c40d0f | [] | no_license | Vkd4U2NtVkZOVg/cc_tutorial | a305295d2f27c1f4bd5fe9ab56cf55e4f4efdc3f | 82ae9a68e2cb2ecfcd09c1fdf71183519f9fc414 | refs/heads/master | 2022-11-30T18:25:42.470611 | 2020-07-23T23:04:27 | 2020-07-23T23:04:27 | 286,372,368 | 1 | 0 | null | 2020-08-10T04:06:11 | 2020-08-10T04:06:10 | null | UTF-8 | C++ | false | false | 8,197 | h | // Generated by commsdsl2comms v3.4.3
/// @file
/// @brief Contains dispatch to handling function(s) for all input messages.
#pragma once
#include <type_traits>
#include "tutorial7/MsgId.h"
#include "tutorial7/input/AllMessages.h"
namespace tutorial7
{
namespace dispatch
{
/// @brief Dispatch message object to its appropriate handling function.
/// @details @b switch statement based (on message ID) cast and dispatch functionality.
/// @tparam TProtOptions Protocol options struct used for the application,
/// like @ref tutorial7::options::DefaultOptions.
/// @param[in] id Numeric message ID.
/// @param[in] msg Message object held by reference to its interface class.
/// @param[in] handler Reference to handling object. Must define
/// @b handle() member function for every message type it exects
/// to handle and one for the interface class as well.
/// @code
/// using MyInterface = tutorial7::Message<...>;
/// using MyMsg1 = tutorial7::message::Msg1<MyInterface, tutorial7::options::DefaultOptions>;
/// using MyMsg2 = tutorial7::message::Msg2<MyInterface, tutorial7::options::DefaultOptions>;
/// struct MyHandler {
/// void handle(MyMsg1& msg) {...}
/// void handle(MyMsg2& msg) {...}
/// ...
/// // Handle all unexpected or irrelevant messages.
/// void handle(MyInterface& msg) {...}
/// };
/// @endcode
/// Every @b handle() function may return a value, but every
/// function must return the @b same type.
/// @note Defined in tutorial7/dispatch/DispatchMessage.h
template<typename TProtOptions, typename TMsg, typename THandler>
auto dispatchMessage(
tutorial7::MsgId id,
TMsg& msg,
THandler& handler) -> decltype(handler.handle(msg))
{
using InterfaceType = typename std::decay<decltype(msg)>::type;
switch(id) {
case tutorial7::MsgId_M1:
{
using MsgType = tutorial7::message::Msg1<InterfaceType, TProtOptions>;
return handler.handle(static_cast<MsgType&>(msg));
}
case tutorial7::MsgId_M2:
{
using MsgType = tutorial7::message::Msg2<InterfaceType, TProtOptions>;
return handler.handle(static_cast<MsgType&>(msg));
}
case tutorial7::MsgId_M3:
{
using MsgType = tutorial7::message::Msg3<InterfaceType, TProtOptions>;
return handler.handle(static_cast<MsgType&>(msg));
}
default:
break;
};
return handler.handle(msg);
}
/// @brief Dispatch message object to its appropriate handling function.
/// @details Same as other dispatchMessage(), but receives extra @b idx parameter.
/// @tparam TProtOptions Protocol options struct used for the application,
/// like @ref tutorial7::options::DefaultOptions.
/// @param[in] id Numeric message ID.
/// @param[in] idx Index of the message among messages with the same ID.
/// Expected to be @b 0.
/// @param[in] msg Message object held by reference to its interface class.
/// @param[in] handler Reference to handling object.
/// @see dispatchMessage()
/// @note Defined in tutorial7/dispatch/DispatchMessage.h
template<typename TProtOptions, typename TMsg, typename THandler>
auto dispatchMessage(
tutorial7::MsgId id,
std::size_t idx,
TMsg& msg,
THandler& handler) -> decltype(handler.handle(msg))
{
if (idx != 0U) {
return handler.handle(msg);
}
return dispatchMessage<TProtOptions>(id, msg, handler);
}
/// @brief Dispatch message object to its appropriate handling function.
/// @details Same as other dispatchMessage(), but passing
/// tutorial7::options::DefaultOptions as first template parameter.
/// @param[in] id Numeric message ID.
/// @param[in] msg Message object held by reference to its interface class.
/// @param[in] handler Reference to handling object.
/// @see dispatchMessage()
/// @note Defined in tutorial7/dispatch/DispatchMessage.h
template<typename TMsg, typename THandler>
auto dispatchMessageDefaultOptions(
tutorial7::MsgId id,
TMsg& msg,
THandler& handler) -> decltype(handler.handle(msg))
{
return dispatchMessage<tutorial7::options::DefaultOptions>(id, msg, handler);
}
/// @brief Dispatch message object to its appropriate handling function.
/// @details Same as other dispatchMessageDefaultOptions(),
/// but receives extra @b idx parameter.
/// @param[in] id Numeric message ID.
/// @param[in] idx Index of the message among messages with the same ID.
/// @param[in] msg Message object held by reference to its interface class.
/// @param[in] handler Reference to handling object.
/// @see dispatchMessageDefaultOptions()
/// @note Defined in tutorial7/dispatch/DispatchMessage.h
template<typename TMsg, typename THandler>
auto dispatchMessageDefaultOptions(
tutorial7::MsgId id,
std::size_t idx,
TMsg& msg,
THandler& handler) -> decltype(handler.handle(msg))
{
return dispatchMessage<tutorial7::options::DefaultOptions>(id, idx, msg, handler);
}
/// @brief Message dispatcher class to be used with
/// @b comms::processAllWithDispatchViaDispatcher() function (or similar).
/// @tparam TProtOptions Protocol options struct used for the application,
/// like @ref tutorial7::options::DefaultOptions.
/// @headerfile "tutorial7/dispatch/DispatchMessage.h"
template <typename TProtOptions>
struct MsgDispatcher
{
/// @brief Class detection tag
using MsgDispatcherTag = void;
/// @brief Dispatch message to its handler.
/// @details Uses appropriate @ref dispatchMessage() function.
/// @param[in] id ID of the message.
/// @param[in] idx Index (or offset) of the message among those having the same numeric ID.
/// @param[in] msg Reference to message object.
/// @param[in] handler Reference to handler object.
/// @return What the @ref dispatchMessage() function returns.
template <typename TMsg, typename THandler>
static auto dispatch(tutorial7::MsgId id, std::size_t idx, TMsg& msg, THandler& handler) ->
decltype(tutorial7::dispatch::dispatchMessage<TProtOptions>(id, idx, msg, handler))
{
return tutorial7::dispatch::dispatchMessage<TProtOptions>(id, idx, msg, handler);
}
/// @brief Complementary dispatch function.
/// @details Same as other dispatch without @b TAllMessages template parameter,
/// used by @b comms::processAllWithDispatchViaDispatcher().
template <typename TAllMessages, typename TMsg, typename THandler>
static auto dispatch(tutorial7::MsgId id, std::size_t idx, TMsg& msg, THandler& handler) ->
decltype(dispatch(id, idx, msg, handler))
{
return dispatch(id, idx, msg, handler);
}
/// @brief Dispatch message to its handler.
/// @details Uses appropriate @ref dispatchMessage() function.
/// @param[in] id ID of the message.
/// @param[in] msg Reference to message object.
/// @param[in] handler Reference to handler object.
/// @return What the @ref dispatchMessage() function returns.
template <typename TMsg, typename THandler>
static auto dispatch(tutorial7::MsgId id, TMsg& msg, THandler& handler) ->
decltype(tutorial7::dispatch::dispatchMessage<TProtOptions>(id, msg, handler))
{
return tutorial7::dispatch::dispatchMessage<TProtOptions>(id, msg, handler);
}
/// @brief Complementary dispatch function.
/// @details Same as other dispatch without @b TAllMessages template parameter,
/// used by @b comms::processAllWithDispatchViaDispatcher().
template <typename TAllMessages, typename TMsg, typename THandler>
static auto dispatch(tutorial7::MsgId id, TMsg& msg, THandler& handler) ->
decltype(dispatch(id, msg, handler))
{
return dispatch(id, msg, handler);
}
};
/// @brief Message dispatcher class to be used with
/// @b comms::processAllWithDispatchViaDispatcher() function (or similar).
/// @details Same as @ref MsgDispatcher, but passing
/// @ref tutorial7::options::DefaultOptions as template parameter.
/// @note Defined in "tutorial7/dispatch/DispatchMessage.h"
using MsgDispatcherDefaultOptions =
MsgDispatcher<tutorial7::options::DefaultOptions>;
} // namespace dispatch
} // namespace tutorial7
| [
"arobenko@gmail.com"
] | arobenko@gmail.com |
21375b33c6f5a2063af761dd579e674331c3bf18 | d8b8699647476b0cde924dbcf830b3b95a410268 | /src/MayaBridge/SkeletonDriver/NuiMayaGestureData.h | 0d58bc8dc0b9708538225d8123b7700f95b57875 | [
"MIT"
] | permissive | hustztz/NatureUserInterfaceStudio | 1e55364ba2fec78c558ed9e752d7c6ff5ea1efa7 | 3cdac6b6ee850c5c8470fa5f1554c7447be0d8af | refs/heads/master | 2020-04-02T12:52:04.789022 | 2017-06-09T11:16:52 | 2017-06-09T11:16:52 | 61,989,309 | 3 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 1,001 | h | #pragma once
#include "Shape/NuiGestureResult.h"
#include <maya/MPxData.h>
#include <maya/MTypeId.h>
#include <maya/MString.h>
class NuiMayaGestureData : public MPxData
{
public:
//////////////////////////////////////////////////////////////////
//
// Overrides from MPxData
//
//////////////////////////////////////////////////////////////////
NuiMayaGestureData();
virtual ~NuiMayaGestureData();
virtual MStatus readASCII( const MArgList& argList, unsigned& idx );
virtual MStatus readBinary( istream& in, unsigned length );
virtual MStatus writeASCII( ostream& out );
virtual MStatus writeBinary( ostream& out );
virtual void copy ( const MPxData& );
virtual MTypeId typeId() const;
virtual MString name() const;
static void * creator();
public:
static const MString typeName;
static const MTypeId id;
// This is the geometry our data will pass though the DG
//
NuiGestureResult* m_pGestureResult;
}; | [
"ztz_mai@163.com"
] | ztz_mai@163.com |
990f4e9cea13296b1c249c49ec6ee899dbccba5e | 0379dd91363f38d8637ff242c1ce5d3595c9b549 | /windows_10_shared_source_kit/windows_10_shared_source_kit/unknown_version/Source/Tests/Graphics/Graphics/DirectX/Common/WGFTestFramework/DXGITest/DXGITest.h | 1c7f3c1de7bcf03b33c8d0f30c948340d9047987 | [] | no_license | zhanglGitHub/windows_10_shared_source_kit | 14f25e6fff898733892d0b5cc23b2b88b04458d9 | 6784379b0023185027894efe6b97afee24ca77e0 | refs/heads/master | 2023-03-21T05:04:08.653859 | 2020-09-28T16:44:54 | 2020-09-28T16:44:54 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,377 | h | //////////////////////////////////////////////////////////////////////
// File: DXGITest.h
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
// Purpose:
// Implementation of a DXGI test base class.
//
// History:
// 11 Sep 2007 SEdmison Created.
//////////////////////////////////////////////////////////////////////
#pragma once
/////////////////////////////////////////////////////////////////
//
// Includes
//
/////////////////////////////////////////////////////////////////
//
// Project headers
//
#include "DXGITestFramework.h"
#include "HResultHelp.h"
/////////////////////////////////////////////////////////////////
//
// Interfaces
//
/////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////
// Class: CDXGITest
//
// Purpose:
// Base class for DXGI test groups.
///////////////////////////////////////////////////////
class CDXGITest
:
public CTest
{
//
// Construction/destruction
//
public:
// Constructor.
CDXGITest();
// Destructor.
virtual ~CDXGITest();
//
// Framework override methods
//
protected:
virtual void InitTestParameters();
//
// Member data
//
protected:
TEST_FEATURE_LEVEL m_TestFeatureLevel;
testfactor::RFactor m_FeatureLevelFactor;
};
| [
"benjamin.barratt@icloud.com"
] | benjamin.barratt@icloud.com |
f7f46ed466dbf3180707788ce4cc004491ac38a0 | a488f0a755b178aae91f12f5cfbd62e3c9613380 | /Hazel/src/Hazel/Events/KeyEvent.h | c121e5abdecf68ed30749c814f31e7ff5665ec53 | [] | no_license | duonggiang152/stupidtriangle-Game | e091d3cb9f55412b65528e1715f3a7011ce62ca5 | ac2990a062c6875b842b93c61da8637178b6b2fb | refs/heads/master | 2023-01-31T03:32:33.628018 | 2020-12-14T04:32:36 | 2020-12-14T04:32:36 | 318,722,024 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,385 | h | #pragma once
#include "Hazel/Events/Event.h"
namespace Hazel {
class HAZEL_API KeyEvent : public Event
{
public:
inline int GetKeyCode() const { return m_KeyCode; }
EVENT_CLASS_CATEGORY(EventCategoryKeyboard | EventCategoryInput)
protected:
KeyEvent(int keycode)
: m_KeyCode(keycode) {}
int m_KeyCode;
};
class HAZEL_API KeyPressedEvent : public KeyEvent
{
public:
KeyPressedEvent(int keycode, int repeatCount)
: KeyEvent(keycode), m_RepeatCount(repeatCount) {}
inline int GetRepeatCount() const { return m_RepeatCount; }
std::string ToString() const override
{
std::stringstream ss;
ss << "KeyPressedEvent: " << m_KeyCode << " (" << m_RepeatCount << " repeats)";
return ss.str();
}
EVENT_CLASS_TYPE(KeyPressed)
private:
int m_RepeatCount;
};
class HAZEL_API KeyReleasedEvent : public KeyEvent
{
public:
KeyReleasedEvent(int keycode)
: KeyEvent(keycode) {}
std::string ToString() const override
{
std::stringstream ss;
ss << "KeyReleasedEvent: " << m_KeyCode;
return ss.str();
}
EVENT_CLASS_TYPE(KeyReleased)
};
class HAZEL_API KeyTypedEvent : public KeyEvent
{
public:
KeyTypedEvent(int keycode)
: KeyEvent(keycode) {}
std::string ToString() const override
{
std::stringstream ss;
ss << "KeyTypedEvent: " << m_KeyCode;
return ss.str();
}
EVENT_CLASS_TYPE(KeyTyped)
};
} | [
"62105435+duonggiang152@users.noreply.github.com"
] | 62105435+duonggiang152@users.noreply.github.com |
a728ff7462544b9cd9a137d8fc04e600093a00a9 | a27d7a4e14048467aa678489b21ef262de45446e | /main.cpp | d1da454930bd06b5d7154b393546dad29bf6905e | [] | no_license | VeskeR/cpp-lab-3 | b86be5f4c73e739c2e8c4d6b1fe95657c9550bc6 | d1a7b808ce066a5a24139f9b90c89b35b75e68f9 | refs/heads/master | 2016-08-12T10:24:25.969016 | 2016-03-22T21:53:22 | 2016-03-22T21:53:22 | 54,505,854 | 5 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 216 | cpp | #include "mainwindow.h"
#include <QApplication>
#include <QtGui>
int main(int argc, char *argv[])
{
QApplication app(argc, argv);
MainWindow w;
w.resize(400, 400);
w.show();
return app.exec();
}
| [
"andrii.bulat@gmail.com"
] | andrii.bulat@gmail.com |
a3916b9ff1345ce8b7a79b265ec888e238b7b41d | b45b27637c8e28e82e95111d3dbf455aa772d7b3 | /bin/Reapr_1.0.18/third_party/pezmaster31-bamtools-7f8b301/src/api/BamReader.h | fb9064d9994d08a4c2afe177b2ca205c1841da4c | [
"MIT",
"LicenseRef-scancode-public-domain",
"GPL-3.0-only"
] | permissive | Fu-Yilei/VALET | caa5e1cad5188cbb94418ad843ea32791e50974b | 8741d984056d499af2fd3585467067d1729c73c4 | refs/heads/master | 2020-08-09T12:17:34.989915 | 2019-10-10T05:10:12 | 2019-10-10T05:10:12 | 214,085,217 | 1 | 0 | MIT | 2019-10-10T04:18:34 | 2019-10-10T04:18:34 | null | UTF-8 | C++ | false | false | 4,146 | h | // ***************************************************************************
// BamReader.h (c) 2009 Derek Barnett, Michael Str�mberg
// Marth Lab, Department of Biology, Boston College
// ---------------------------------------------------------------------------
// Last modified: 10 October 2011 (DB)
// ---------------------------------------------------------------------------
// Provides read access to BAM files.
// ***************************************************************************
#ifndef BAMREADER_H
#define BAMREADER_H
#include "api/api_global.h"
#include "api/BamAlignment.h"
#include "api/BamIndex.h"
#include "api/SamHeader.h"
#include <string>
namespace BamTools {
namespace Internal {
class BamReaderPrivate;
} // namespace Internal
class API_EXPORT BamReader {
// constructor / destructor
public:
BamReader(void);
~BamReader(void);
// public interface
public:
// ----------------------
// BAM file operations
// ----------------------
// closes the current BAM file
bool Close(void);
// returns filename of current BAM file
const std::string GetFilename(void) const;
// returns true if a BAM file is open for reading
bool IsOpen(void) const;
// performs random-access jump within BAM file
bool Jump(int refID, int position = 0);
// opens a BAM file
bool Open(const std::string& filename);
// returns internal file pointer to beginning of alignment data
bool Rewind(void);
// sets the target region of interest
bool SetRegion(const BamRegion& region);
// sets the target region of interest
bool SetRegion(const int& leftRefID,
const int& leftPosition,
const int& rightRefID,
const int& rightPosition);
// ----------------------
// access alignment data
// ----------------------
// retrieves next available alignment
bool GetNextAlignment(BamAlignment& alignment);
// retrieves next available alignmnet (without populating the alignment's string data fields)
bool GetNextAlignmentCore(BamAlignment& alignment);
// ----------------------
// access header data
// ----------------------
// returns SAM header data
SamHeader GetHeader(void) const;
// returns SAM header data, as SAM-formatted text
std::string GetHeaderText(void) const;
// ----------------------
// access reference data
// ----------------------
// returns the number of reference sequences
int GetReferenceCount(void) const;
// returns all reference sequence entries
const RefVector& GetReferenceData(void) const;
// returns the ID of the reference with this name
int GetReferenceID(const std::string& refName) const;
// ----------------------
// BAM index operations
// ----------------------
// creates an index file for current BAM file, using the requested index type
bool CreateIndex(const BamIndex::IndexType& type = BamIndex::STANDARD);
// returns true if index data is available
bool HasIndex(void) const;
// looks in BAM file's directory for a matching index file
bool LocateIndex(const BamIndex::IndexType& preferredType = BamIndex::STANDARD);
// opens a BAM index file
bool OpenIndex(const std::string& indexFilename);
// sets a custom BamIndex on this reader
void SetIndex(BamIndex* index);
// ----------------------
// error handling
// ----------------------
// returns a human-readable description of the last error that occurred
std::string GetErrorString(void) const;
// private implementation
private:
Internal::BamReaderPrivate* d;
};
} // namespace BamTools
#endif // BAMREADER_H
| [
"yf20@gho.cs.rice.edu"
] | yf20@gho.cs.rice.edu |
f644ebbee3bd476341cd04f9784e1e423c3e6f81 | 0229b42656751ca134dd2c3e948f9ab9e4b9ddf5 | /AttackBullet.cpp | a02b23d3c0a6e997714e1c98cd693d37ba9d3821 | [] | no_license | ikageso1/ActionGameWithBox2d | a9980db918ef89f6d74cd7fcb27369eacf13beb9 | 1f1704c610a6a79ee51a5d46adee5db6441036b7 | refs/heads/master | 2021-01-17T17:54:13.669405 | 2016-07-02T17:10:40 | 2016-07-02T17:10:40 | 62,461,128 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 228 | cpp | #include "AttackBullet.h"
AttackBullet::AttackBullet(Character* character,Field* field) :CharacterController(character,field)
{
}
void AttackBullet::Think(){
character_->DoAttack();
}
AttackBullet::~AttackBullet(void)
{
}
| [
"1210370051g@kindai.ac.jp"
] | 1210370051g@kindai.ac.jp |
fa2630ef3ec3f6256024aa3484771de19acb39ec | f8975076e4394c7657fa8c602c2cd938b6191c48 | /Dependency/FbxSDk/include/fbxsdk/scene/fbxobjectscontainer.h | f806ad9d612ee9c278a6fec22f2f72ef4011fc87 | [] | no_license | miztook/wowmodelexplorer | baa87ee965c64ea53272b1cf8bd0c0ca966a76a4 | 78b5ea79668a551dd70cd0699b8393de4472ec5f | refs/heads/master | 2021-07-08T23:10:58.887309 | 2020-07-19T04:27:50 | 2020-07-19T04:27:50 | 145,582,892 | 7 | 2 | null | null | null | null | UTF-8 | C++ | false | false | 2,171 | h | /****************************************************************************************
Copyright (C) 2014 Autodesk, Inc.
All rights reserved.
Use of this software is subject to the terms of the Autodesk license agreement
provided at the time of installation or download, or which otherwise accompanies
this software in either electronic or hard copy form.
****************************************************************************************/
//! \file fbxobjectscontainer.h
#ifndef _FBXSDK_SCENE_OBJECTS_CONTAINER_H_
#define _FBXSDK_SCENE_OBJECTS_CONTAINER_H_
#include <fbxsdk/fbxsdk_def.h>
#include <fbxsdk/core/base/fbxarray.h>
#include <fbxsdk/scene/fbxscene.h>
#include <fbxsdk/fbxsdk_nsbegin.h>
typedef FbxArray<FbxNodeAttribute::EType> FbxAttributeFilters;
/* Internal helper class used to traverse scene in the FbxAxisSystem and FbxSystemUnit
*/
class FbxObjectsContainer
{
public:
enum EDepth
{
eChildOnly,
eChildAndSubChild,
eSubChildWithNoScaleInherit
};
FbxObjectsContainer() : mStartNode(NULL) {}
virtual ~FbxObjectsContainer(){ Clear(); }
// Store all anim curve nodes pointers that need to be converted
FbxArray<FbxAnimCurveNode*> mFCurvesT;
FbxArray<FbxAnimCurveNode*> mFCurvesR;
FbxArray<FbxAnimCurveNode*> mFCurvesS;
// Store all node that need to be converted
FbxArray<FbxNode*> mNodes;
public:
void ExtractSceneObjects(FbxScene* pScene, EDepth pDepth, const FbxAttributeFilters& pFilters);
void ExtractSceneObjects(FbxNode* pRootNode, EDepth pDepth, const FbxAttributeFilters& pFilters);
void Clear() { mFCurvesT.Clear(); mFCurvesR.Clear(); mFCurvesS.Clear(); mNodes.Clear(); mStartNode = NULL; }
protected:
// Extract all node and fcurve from all take for this node.
void ExtractNodesAnimCurveNodes(FbxNode* pNode, EDepth pDepth, const FbxAttributeFilters& pFilters);
void ExtractAnimCurveNodes(FbxNode* pNode);
bool InheritsScale( FbxNode* pNode ) const;
FbxNode* mStartNode;
};
#include <fbxsdk/fbxsdk_nsend.h>
#endif /* _FBXSDK_SCENE_OBJECTS_CONTAINER_H_ */
| [
"miztook@2a05eb2e-4a50-4195-aba3-4d59626bef6c"
] | miztook@2a05eb2e-4a50-4195-aba3-4d59626bef6c |
e4388447cfdfbdf2ce63fcde277a8ae2c18018b9 | 466aa6962977a3e353b2ef6d8babd8249b870ef5 | /BusySchedule.cpp | 96ca31b34fa32ec3ed56334ab1fcddec272750cb | [] | no_license | damosman/Kattis-Problems | 348b852651ff82f044416183b8a9a672a3252aa7 | 11be82d80d97ac496a66e31f12fddfed8933e9a1 | refs/heads/master | 2022-12-31T08:00:01.191031 | 2020-10-17T08:50:53 | 2020-10-17T08:50:53 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,587 | cpp | #include <iostream>
#include <string>
#include <regex>
#include <vector>
void PrintHours(std::vector<int> hours, std::string period);
bool CustomSort(int i, int j);
int main()
{
std::regex expression("^([0-9]{1,2})(?:\:)([0-9]{2}) ([a-z\.]+)");
std::string line;
std::smatch match;
int n;
std::vector<int> timesAM;
std::vector<int> timesPM;
std::getline(std::cin, line);
n = stoi(line);
while (n != 0)
{
for (int i = 0; i < n; i++)
{
std::getline(std::cin, line);
std::regex_search(line, match, expression);
if (match[3].str() == "a.m.")
timesAM.push_back(stoi(match[1].str() + match[2].str()));
else
timesPM.push_back(stoi(match[1].str() + match[2].str()));
}
std::sort(timesAM.begin(), timesAM.end(), CustomSort);
std::sort(timesPM.begin(), timesPM.end(), CustomSort);
PrintHours(timesAM, "a.m.");
std::cout << std::endl;
PrintHours(timesPM, "p.m.");
timesAM.clear();
timesPM.clear();
std::getline(std::cin, line);
n = stoi(line);
}
return 0;
}
void PrintHours(std::vector<int> hours, std::string period)
{
std::vector<int>::iterator iter;
for (iter = hours.begin(); iter != hours.end(); iter++)
{
std::string temp = std::to_string(*iter);
int hoursLength;
if (temp.length() == 3)
hoursLength = 1;
else
hoursLength = 2;
std::cout << temp.substr(0, hoursLength) << ":" << temp.substr(hoursLength) << " " + period << std::endl;
}
}
bool CustomSort(int i, int j)
{
if ((i >= 1200 && j >= 1200) || (i < 1200 && j < 1200))
return i < j;
else if (i >= 1200)
return true;
else
return false;
} | [
"georgekam96@gmail.com"
] | georgekam96@gmail.com |
0a58764d0ab61461a9f0fab6060f74c9f2ae3843 | c2bccd75822d0f9b01b32c41f5258ac48eced940 | /code/userprog/coremap.cc | f35ff2714ba512350310b616cfad5fab4918c6b7 | [] | no_license | nicodelpiano/NachOS | a2e86c43dbba81ab81231275407340cf96779482 | 3e9f1cbfb792943ca0fdf49caadb484f7410fed5 | refs/heads/master | 2020-05-30T14:29:35.027986 | 2014-02-23T03:02:31 | 2014-02-23T03:02:31 | 17,100,400 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,436 | cc | #include "coremap.h"
/*
Preferimos iniciar la estructura del coremap asi:
Si no tiene un addrspace asignado, es NULL, y en caso de no tener
asignada una memoria virtual, es -1.
*/
CoreMap::CoreMap(int nfpages){
counter = 0;
npages = nfpages;
bitmap = new BitMap(nfpages);
coremap = new fpage_info[nfpages];
for(int i=0;i<nfpages;i++)
{
coremap[i].vpage = -1;
coremap[i].aspace = NULL;
}
}
CoreMap::~CoreMap(){
delete coremap;
}
int CoreMap::NumClear()
{
return bitmap->NumClear();
}
void CoreMap::Mark(int fpage,int virp,AddrSpace *addr)
{
if(bitmap->Test(fpage))
bitmap->Mark(fpage);
coremap[fpage].vpage = virp;
coremap[fpage].aspace = addr;
}
//hace un mark, sin alterar el bitmap y borrando la entrada
//en el bitmap
void CoreMap::ClearUp(int fpage,int virp,AddrSpace *addr)
{
bitmap->Clear(fpage);
coremap[fpage].vpage = virp;
coremap[fpage].aspace = addr;
}
int CoreMap::Find(int virtpage,AddrSpace *addr)
{
int bit = bitmap->Find();
if(bit<0)
{
return -1;
}
Mark(bit,virtpage,addr);
return bit;
}
AddrSpace* CoreMap::owner(int fpage)
{
return(coremap[fpage].aspace);
}
int CoreMap::vpn(int fpage)
{
return(coremap[fpage].vpage);
}
void CoreMap::Print()
{
printf("\n==========Estado del coremap:==========\n");
for(int i=0;i<npages;i++)
printf("FisAddr:%d VirtAddr:%d Thread:%d\n",i,coremap[i].vpage,coremap[i].aspace);
printf("=======================================\n");
}
| [
"ndel314@gmail.com"
] | ndel314@gmail.com |
838e0a05e51c80d0d8b8cae3ad89b591e5775d26 | 3c27e8402755038a757d54d812983e0ee407e319 | /_build/debug/moc_bullet.cpp | b0588434ff2a00a20980c2aa0a5c1c45eda99985 | [] | no_license | SvyatKuznetsov/KursWorkShooter | a38142a4de89da837cc608d2676d25da97686250 | 8c32a6b7ee47ad2a1bc7a0cafb560162d0c6cf86 | refs/heads/main | 2023-03-15T11:02:30.292095 | 2021-03-05T14:30:21 | 2021-03-05T14:30:21 | 344,836,090 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 3,401 | cpp | /****************************************************************************
** Meta object code from reading C++ file 'bullet.h'
**
** Created by: The Qt Meta Object Compiler version 67 (Qt 5.12.6)
**
** WARNING! All changes made in this file will be lost!
*****************************************************************************/
#include "../../bullet.h"
#include <QtCore/qbytearray.h>
#include <QtCore/qmetatype.h>
#if !defined(Q_MOC_OUTPUT_REVISION)
#error "The header file 'bullet.h' doesn't include <QObject>."
#elif Q_MOC_OUTPUT_REVISION != 67
#error "This file was generated using the moc from 5.12.6. It"
#error "cannot be used with the include files from this version of Qt."
#error "(The moc has changed too much.)"
#endif
QT_BEGIN_MOC_NAMESPACE
QT_WARNING_PUSH
QT_WARNING_DISABLE_DEPRECATED
struct qt_meta_stringdata_bullet_t {
QByteArrayData data[3];
char stringdata0[24];
};
#define QT_MOC_LITERAL(idx, ofs, len) \
Q_STATIC_BYTE_ARRAY_DATA_HEADER_INITIALIZER_WITH_OFFSET(len, \
qptrdiff(offsetof(qt_meta_stringdata_bullet_t, stringdata0) + ofs \
- idx * sizeof(QByteArrayData)) \
)
static const qt_meta_stringdata_bullet_t qt_meta_stringdata_bullet = {
{
QT_MOC_LITERAL(0, 0, 6), // "bullet"
QT_MOC_LITERAL(1, 7, 15), // "slotTimerBullet"
QT_MOC_LITERAL(2, 23, 0) // ""
},
"bullet\0slotTimerBullet\0"
};
#undef QT_MOC_LITERAL
static const uint qt_meta_data_bullet[] = {
// content:
8, // revision
0, // classname
0, 0, // classinfo
1, 14, // methods
0, 0, // properties
0, 0, // enums/sets
0, 0, // constructors
0, // flags
0, // signalCount
// slots: name, argc, parameters, tag, flags
1, 0, 19, 2, 0x08 /* Private */,
// slots: parameters
QMetaType::Void,
0 // eod
};
void bullet::qt_static_metacall(QObject *_o, QMetaObject::Call _c, int _id, void **_a)
{
if (_c == QMetaObject::InvokeMetaMethod) {
auto *_t = static_cast<bullet *>(_o);
Q_UNUSED(_t)
switch (_id) {
case 0: _t->slotTimerBullet(); break;
default: ;
}
}
Q_UNUSED(_a);
}
QT_INIT_METAOBJECT const QMetaObject bullet::staticMetaObject = { {
&QObject::staticMetaObject,
qt_meta_stringdata_bullet.data,
qt_meta_data_bullet,
qt_static_metacall,
nullptr,
nullptr
} };
const QMetaObject *bullet::metaObject() const
{
return QObject::d_ptr->metaObject ? QObject::d_ptr->dynamicMetaObject() : &staticMetaObject;
}
void *bullet::qt_metacast(const char *_clname)
{
if (!_clname) return nullptr;
if (!strcmp(_clname, qt_meta_stringdata_bullet.stringdata0))
return static_cast<void*>(this);
if (!strcmp(_clname, "QGraphicsItem"))
return static_cast< QGraphicsItem*>(this);
return QObject::qt_metacast(_clname);
}
int bullet::qt_metacall(QMetaObject::Call _c, int _id, void **_a)
{
_id = QObject::qt_metacall(_c, _id, _a);
if (_id < 0)
return _id;
if (_c == QMetaObject::InvokeMetaMethod) {
if (_id < 1)
qt_static_metacall(this, _c, _id, _a);
_id -= 1;
} else if (_c == QMetaObject::RegisterMethodArgumentMetaType) {
if (_id < 1)
*reinterpret_cast<int*>(_a[0]) = -1;
_id -= 1;
}
return _id;
}
QT_WARNING_POP
QT_END_MOC_NAMESPACE
| [
"55543452+SvyatKuznetsov@users.noreply.github.com"
] | 55543452+SvyatKuznetsov@users.noreply.github.com |
8338809cf8441cbfbb4f070b106d5d33513e526a | cb7535e92e574980ecea0c980a1a5e98612ad67e | /nnet/main.cpp | cdec610ec34c381e00cbb4ba1cff4dedf8e9e976 | [] | no_license | mxw/cs181 | 559d7f47444b7beb25d5e4e3932ab20fe46ad664 | 0ec48b54591d8e124eeaf0c443a6e586d9c73b16 | refs/heads/master | 2020-12-30T10:37:15.365828 | 2013-05-06T02:01:41 | 2013-05-06T02:01:41 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 3,999 | cpp | /**
* main.cpp
*/
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <iostream>
#include <sstream>
#include <unistd.h>
#include "neural_network.h"
#include "image.h"
#include "util.h"
using namespace std;
#define USAGE "Usage: ./main -e EPOCHS -r RATE -l LAYERS [-h HIDDENS]\n"
#define IMGSIZE 36
#define SAMPLES 20
#define LIMIT 75000
#define TRAIN_FILE "../data/plants0.dat"
#define VALID_FILE "../data/plants1.dat"
#define TEST_FILE "../data/plants2.dat"
int
main(int argc, char *argv[])
{
int c, n, epochs, layers;
double rate;
bool verbose;
vector<unsigned> samples;
vector<unsigned> hiddens;
istringstream iss;
ofstream f;
epochs = 0;
layers = 0;
rate = 0.0;
verbose = false;
if (argc < 7) {
fprintf(stderr, USAGE);
return 1;
}
while ((c = getopt(argc, argv, "e:r:l:h:s:v")) != -1) {
switch (c) {
case 'e':
epochs = atoi(optarg);
break;
case 'r':
rate = atof(optarg);
break;
case 'l':
layers = atoi(optarg);
break;
case 'h':
iss.clear();
iss.str(optarg);
while (iss >> n) {
hiddens.push_back(n);
// Skip a comma.
n = iss.get();
if (n != -1 && n != ',') {
fprintf(stderr, "Hidden node counts must be comma-separated.\n");
}
}
break;
case 's':
iss.clear();
iss.str(optarg);
while (iss >> n) {
samples.push_back(n);
// Skip a comma.
n = iss.get();
if (n != -1 && n != ',') {
fprintf(stderr, "Sample sizes must be comma-separated.\n");
}
}
break;
case 'v':
verbose = true;
break;
case '?':
fprintf(stderr, USAGE);
return 1;
default:
abort();
}
}
if (epochs <= 0) {
fprintf(stderr, "Number of epochs must be positive.\n");
return 2;
}
if (layers <= 0) {
fprintf(stderr, "Number of layers must be positive.\n");
return 2;
}
if (layers <= 2 && hiddens.size() != 0) {
fprintf(stderr, "No hidden nodes allowed for < 3 layers.\n");
return 2;
}
if (layers > 2 && hiddens.size() + 2 != (unsigned)layers) {
fprintf(stderr, "Must specify n-2 hidden node counts for n layers.\n");
return 2;
}
if (samples.size() != 0 && samples.size() != 2) {
fprintf(stderr, "Must specify exactly two sample sizes.\n");
return 2;
}
if (rate <= 0.0) {
fprintf(stderr, "Learning rate must be positive.\n");
return 2;
}
srand(time(NULL));
vector<Example> train_set, valid_set, test_set;
train_set = encode_images(file_get_images(TRAIN_FILE, LIMIT));
valid_set = encode_images(file_get_images(VALID_FILE, LIMIT / 10));
test_set = encode_images(file_get_images(TEST_FILE, LIMIT / 10));
if (samples.size() != 0) {
train_set = sample_average(train_set, SAMPLES, samples[0]);
valid_set = sample_average(valid_set, SAMPLES, samples[0]);
test_set = sample_average(test_set, SAMPLES, samples[1]);
}
// Create the neural network.
vector<unsigned> spec;
spec.push_back(IMGSIZE);
spec.insert(spec.end(), hiddens.begin(), hiddens.end());
spec.push_back(NLABELS);
NeuralNetwork network(spec, -0.01, 0.01);
network.setVerbose(verbose);
// Train.
network.train(train_set, valid_set, rate, epochs);
// Write out the network.
f.open("weights.out");
vector<double> weights = network.save();
vector<unsigned>::iterator lt;
vector<double>::iterator wt;
for (lt = spec.begin(); lt != spec.end(); ++lt) {
f << *lt << " ";
}
f << "\n";
for (wt = weights.begin(); wt != weights.end(); ++wt) {
f << *wt << " ";
}
printf(
"Performance\n"
" training: %lf\n"
" validation: %lf\n"
" test: %lf\n",
network.performance(train_set),
network.performance(valid_set),
network.performance(test_set)
);
return 0;
}
| [
"mxawng@gmail.com"
] | mxawng@gmail.com |
42f9dcdd907067ce1049a3f7a4c01494c1ce4379 | 66b3ef6a474b25487b52c28d6ab777c4bff82431 | /old/v2/src/sim/units/Milliseconds.cpp | 98ea1dd440001319a344b0863c76c52cbf5aeebb | [
"MIT"
] | permissive | mackorone/mms | 63127b1aa27658e4d6ee88d3aefc9969b11497de | 9ec759a32b4ff882f71ad4315cf9abbc575b30a1 | refs/heads/main | 2023-07-20T06:10:47.377682 | 2023-07-17T01:08:53 | 2023-07-17T01:29:31 | 14,811,400 | 281 | 73 | MIT | 2023-07-08T09:59:59 | 2013-11-29T22:36:30 | C++ | UTF-8 | C++ | false | false | 476 | cpp | #include "Milliseconds.h"
namespace sim {
Milliseconds::Milliseconds(double milliseconds) {
static const double secondsPerMillisecond = 1.0 / 1000.0;
m_seconds = secondsPerMillisecond * milliseconds;
}
Milliseconds::Milliseconds(const Duration& duration) {
m_seconds = duration.getSeconds();
}
Milliseconds Milliseconds::operator+(const Duration& duration) const {
return Milliseconds(getMilliseconds() + duration.getMilliseconds());
}
} // namespace sim
| [
"mackorone@gmail.com"
] | mackorone@gmail.com |
596ba599a4a8945ac80a21fd7795116da928e323 | 5b2d81c7e73b0e71be2fd5f52e4398a992c6f6d4 | /include/node.hpp | e1d1684dd112fdf55ee6a38d037ac612bb42066a | [] | no_license | long64/AS-BFS | fbc2df15b13b2c17edc8ba972c60bb6c68052ba9 | 130639985d05a49d52f2ec1a28dd4acbd053a740 | refs/heads/master | 2020-12-28T09:35:53.120678 | 2020-02-04T18:16:36 | 2020-02-04T18:16:36 | 238,270,722 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 583 | hpp | #pragma once
#include <vector>
class Node
{
private:
int m_asn;
std::vector<int> m_parent;
std::vector<int> m_child;
int m_depth;
int m_stage;
int m_searched;
int m_flag;
public:
Node(const int asn = 0);
int GetAsn();
std::vector<int> GetParent();
void AddParent(const int asn);
std::vector<int> GetChild();
void AddChild(const int asn);
int GetDepth();
void SetDepth(const int depth);
int GetStage();
void SetStage(const int stage);
int GetSearched();
void SetSearched(const int searched);
int GetFlag();
void SetFlag(const int flag);
}; | [
"aki@aki.local"
] | aki@aki.local |
7ee7076cf745bee8443ce8d2ab44613df66758cd | 59daee962170b43cb88a84babb83acc6fb382a8f | /FMEGraphics/inc/ICamera.h | 922a7f3f5487faf707e91aff3b9f3954456ee3a4 | [
"MIT"
] | permissive | mohit3112/FullMetalEngine | da36ba209b62a93a9ee7fc69b086e68304ffc89b | 26fbdd14332f9ab158180efea176e7aaa47f570c | refs/heads/master | 2021-09-22T09:35:47.884072 | 2018-09-07T11:18:27 | 2018-09-07T11:18:27 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 630 | h | #ifndef ICAMERA_H_
#define ICAMERA_H_
#include <glm/glm.hpp>
namespace FME
{
namespace Graphics
{
/** \class ICamera
* \brief general interface for a camera, including the must-have's for rendering
*/
class ICamera
{
public:
virtual ~ICamera() {};
void SetProjectionMatrix(glm::mat4 proj) { m_proj = proj; };
void SetViewMatrix(glm::mat4 view) { m_view = view; };
glm::mat4 GetProjectionMatrix() const { return m_proj; };
glm::mat4 GetViewMatrix() const { return m_view; };
protected:
glm::mat4 m_view;
glm::mat4 m_proj;
};
}
}
#endif | [
"nickyfullmetal@gmail.com"
] | nickyfullmetal@gmail.com |
f1bbfc134d5e8c515476ec3e9a4b62be851b4a2f | 24f26275ffcd9324998d7570ea9fda82578eeb9e | /chrome/browser/ui/webui/chromeos/login/l10n_util.cc | 7392dc3d99c0ca497a9a2c2c1e86dcf9313fb6cd | [
"BSD-3-Clause"
] | permissive | Vizionnation/chromenohistory | 70a51193c8538d7b995000a1b2a654e70603040f | 146feeb85985a6835f4b8826ad67be9195455402 | refs/heads/master | 2022-12-15T07:02:54.461083 | 2019-10-25T15:07:06 | 2019-10-25T15:07:06 | 217,557,501 | 2 | 1 | BSD-3-Clause | 2022-11-19T06:53:07 | 2019-10-25T14:58:54 | null | UTF-8 | C++ | false | false | 24,006 | cc | // Copyright 2014 The Chromium Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include "chrome/browser/ui/webui/chromeos/login/l10n_util.h"
#include <stddef.h>
#include <iterator>
#include <map>
#include <memory>
#include <set>
#include <utility>
#include "base/bind.h"
#include "base/i18n/rtl.h"
#include "base/location.h"
#include "base/logging.h"
#include "base/memory/ref_counted.h"
#include "base/sequenced_task_runner.h"
#include "base/stl_util.h"
#include "base/strings/string16.h"
#include "base/strings/stringprintf.h"
#include "base/strings/utf_string_conversions.h"
#include "base/task/post_task.h"
#include "base/task_runner_util.h"
#include "base/threading/scoped_blocking_call.h"
#include "base/threading/sequenced_task_runner_handle.h"
#include "base/values.h"
#include "chrome/browser/browser_process.h"
#include "chrome/browser/chromeos/customization/customization_document.h"
#include "chrome/browser/chromeos/profiles/profile_helper.h"
#include "chrome/browser/profiles/profile_manager.h"
#include "chrome/grit/generated_resources.h"
#include "content/public/browser/browser_thread.h"
#include "ui/base/ime/chromeos/component_extension_ime_manager.h"
#include "ui/base/ime/chromeos/input_method_descriptor.h"
#include "ui/base/ime/chromeos/input_method_manager.h"
#include "ui/base/ime/chromeos/input_method_util.h"
#include "ui/base/l10n/l10n_util.h"
namespace chromeos {
const char kMostRelevantLanguagesDivider[] = "MOST_RELEVANT_LANGUAGES_DIVIDER";
namespace {
std::unique_ptr<base::DictionaryValue> CreateInputMethodsEntry(
const input_method::InputMethodDescriptor& method,
const std::string selected) {
input_method::InputMethodUtil* util =
input_method::InputMethodManager::Get()->GetInputMethodUtil();
const std::string& ime_id = method.id();
std::unique_ptr<base::DictionaryValue> input_method(
new base::DictionaryValue);
input_method->SetString("value", ime_id);
input_method->SetString(
"title", util->GetInputMethodLongNameStripped(method));
input_method->SetBoolean("selected", ime_id == selected);
return input_method;
}
// Returns true if element was inserted.
bool InsertString(const std::string& str, std::set<std::string>* to) {
const std::pair<std::set<std::string>::iterator, bool> result =
to->insert(str);
return result.second;
}
void AddOptgroupOtherLayouts(base::ListValue* input_methods_list) {
std::unique_ptr<base::DictionaryValue> optgroup(new base::DictionaryValue);
optgroup->SetString(
"optionGroupName",
l10n_util::GetStringUTF16(IDS_OOBE_OTHER_KEYBOARD_LAYOUTS));
input_methods_list->Append(std::move(optgroup));
}
std::unique_ptr<base::DictionaryValue> CreateLanguageEntry(
const std::string& language_code,
const base::string16& language_display_name,
const base::string16& language_native_display_name) {
base::string16 display_name = language_display_name;
const bool markup_removal =
base::i18n::UnadjustStringForLocaleDirection(&display_name);
DCHECK(markup_removal);
const bool has_rtl_chars =
base::i18n::StringContainsStrongRTLChars(display_name);
const std::string directionality = has_rtl_chars ? "rtl" : "ltr";
auto dictionary = std::make_unique<base::DictionaryValue>();
dictionary->SetString("code", language_code);
dictionary->SetString("displayName", language_display_name);
dictionary->SetString("textDirection", directionality);
dictionary->SetString("nativeDisplayName", language_native_display_name);
return dictionary;
}
// Gets the list of languages with |descriptors| based on |base_language_codes|.
// The |most_relevant_language_codes| will be first in the list. If
// |insert_divider| is true, an entry with its "code" attribute set to
// kMostRelevantLanguagesDivider is placed between the most relevant languages
// and all others.
std::unique_ptr<base::ListValue> GetLanguageList(
const input_method::InputMethodDescriptors& descriptors,
const std::vector<std::string>& base_language_codes,
const std::vector<std::string>& most_relevant_language_codes,
bool insert_divider) {
const std::string app_locale = g_browser_process->GetApplicationLocale();
std::set<std::string> language_codes;
// Collect the language codes from the supported input methods.
for (size_t i = 0; i < descriptors.size(); ++i) {
const input_method::InputMethodDescriptor& descriptor = descriptors[i];
const std::vector<std::string>& languages = descriptor.language_codes();
for (size_t i = 0; i < languages.size(); ++i)
language_codes.insert(languages[i]);
}
// Language sort order.
std::map<std::string, int /* index */> language_index;
for (size_t i = 0; i < most_relevant_language_codes.size(); ++i)
language_index[most_relevant_language_codes[i]] = i;
// Map of display name -> {language code, native_display_name}.
// In theory, we should be able to create a map that is sorted by
// display names using ICU comparator, but doing it is hard, thus we'll
// use an auxiliary vector to achieve the same result.
typedef std::pair<std::string, base::string16> LanguagePair;
typedef std::map<base::string16, LanguagePair> LanguageMap;
LanguageMap language_map;
// The auxiliary vector mentioned above (except the most relevant locales).
std::vector<base::string16> display_names;
// Separate vector of the most relevant locales.
std::vector<base::string16> most_relevant_locales_display_names(
most_relevant_language_codes.size());
size_t most_relevant_locales_count = 0;
// Build the list of display names, and build the language map.
// The list of configured locales might have entries not in
// base_language_codes. If there are unsupported language variants,
// but they resolve to backup locale within base_language_codes, also
// add them to the list.
for (std::map<std::string, int>::const_iterator it = language_index.begin();
it != language_index.end(); ++it) {
const std::string& language_id = it->first;
const std::string lang = l10n_util::GetLanguage(language_id);
// Ignore non-specific codes.
if (lang.empty() || lang == language_id)
continue;
if (base::Contains(base_language_codes, language_id)) {
// Language is supported. No need to replace
continue;
}
std::string resolved_locale;
if (!l10n_util::CheckAndResolveLocale(language_id, &resolved_locale))
continue;
if (!base::Contains(base_language_codes, resolved_locale)) {
// Resolved locale is not supported.
continue;
}
const base::string16 display_name =
l10n_util::GetDisplayNameForLocale(language_id, app_locale, true);
const base::string16 native_display_name =
l10n_util::GetDisplayNameForLocale(
language_id, language_id, true);
language_map[display_name] =
std::make_pair(language_id, native_display_name);
most_relevant_locales_display_names[it->second] = display_name;
++most_relevant_locales_count;
}
// Translate language codes, generated from input methods.
for (std::set<std::string>::const_iterator it = language_codes.begin();
it != language_codes.end(); ++it) {
// Exclude the language which is not in |base_langauge_codes| even it has
// input methods.
if (!base::Contains(base_language_codes, *it))
continue;
const base::string16 display_name =
l10n_util::GetDisplayNameForLocale(*it, app_locale, true);
const base::string16 native_display_name =
l10n_util::GetDisplayNameForLocale(*it, *it, true);
language_map[display_name] = std::make_pair(*it, native_display_name);
const std::map<std::string, int>::const_iterator index_pos =
language_index.find(*it);
if (index_pos != language_index.end()) {
base::string16& stored_display_name =
most_relevant_locales_display_names[index_pos->second];
if (stored_display_name.empty()) {
stored_display_name = display_name;
++most_relevant_locales_count;
}
} else {
display_names.push_back(display_name);
}
}
DCHECK_EQ(display_names.size() + most_relevant_locales_count,
language_map.size());
// Build the list of display names, and build the language map.
for (size_t i = 0; i < base_language_codes.size(); ++i) {
// Skip this language if it was already added.
if (language_codes.find(base_language_codes[i]) != language_codes.end())
continue;
base::string16 display_name =
l10n_util::GetDisplayNameForLocale(
base_language_codes[i], app_locale, false);
base::string16 native_display_name =
l10n_util::GetDisplayNameForLocale(
base_language_codes[i], base_language_codes[i], false);
language_map[display_name] =
std::make_pair(base_language_codes[i], native_display_name);
const std::map<std::string, int>::const_iterator index_pos =
language_index.find(base_language_codes[i]);
if (index_pos != language_index.end()) {
most_relevant_locales_display_names[index_pos->second] = display_name;
++most_relevant_locales_count;
} else {
display_names.push_back(display_name);
}
}
// Sort display names using locale specific sorter.
l10n_util::SortStrings16(app_locale, &display_names);
// Concatenate most_relevant_locales_display_names and display_names.
// Insert special divider in between.
std::vector<base::string16> out_display_names;
for (size_t i = 0; i < most_relevant_locales_display_names.size(); ++i) {
if (most_relevant_locales_display_names[i].size() == 0)
continue;
out_display_names.push_back(most_relevant_locales_display_names[i]);
}
base::string16 divider16;
if (insert_divider && !out_display_names.empty()) {
// Insert a divider if requested, but only if
// |most_relevant_locales_display_names| is not empty.
divider16 = base::ASCIIToUTF16(kMostRelevantLanguagesDivider);
out_display_names.push_back(divider16);
}
std::copy(display_names.begin(),
display_names.end(),
std::back_inserter(out_display_names));
// Build the language list from the language map.
std::unique_ptr<base::ListValue> language_list(new base::ListValue());
for (size_t i = 0; i < out_display_names.size(); ++i) {
// Sets the directionality of the display language name.
base::string16 display_name(out_display_names[i]);
if (insert_divider && display_name == divider16) {
// Insert divider.
auto dictionary = std::make_unique<base::DictionaryValue>();
dictionary->SetString("code", kMostRelevantLanguagesDivider);
language_list->Append(std::move(dictionary));
continue;
}
const LanguagePair& pair = language_map[out_display_names[i]];
language_list->Append(
CreateLanguageEntry(pair.first, out_display_names[i], pair.second));
}
return language_list;
}
// Note: this method updates |selected_locale| only if it is empty.
void GetAndMergeKeyboardLayoutsForLocale(input_method::InputMethodUtil* util,
const std::string& locale,
std::string* selected_locale,
std::vector<std::string>* layouts) {
std::vector<std::string> layouts_from_locale;
util->GetInputMethodIdsFromLanguageCode(
locale, input_method::kKeyboardLayoutsOnly, &layouts_from_locale);
layouts->insert(layouts->end(), layouts_from_locale.begin(),
layouts_from_locale.end());
if (selected_locale->empty() && !layouts_from_locale.empty()) {
*selected_locale =
util->GetInputMethodDescriptorFromId(layouts_from_locale[0])->id();
}
}
// Invokes |callback| with a list of keyboard layouts that can be used for
// |resolved_locale|.
void GetKeyboardLayoutsForResolvedLocale(
const std::string& requested_locale,
const GetKeyboardLayoutsForLocaleCallback& callback,
const std::string& resolved_locale) {
input_method::InputMethodUtil* util =
input_method::InputMethodManager::Get()->GetInputMethodUtil();
std::vector<std::string> layouts = util->GetHardwareInputMethodIds();
// "Selected" will be set from the fist non-empty list.
std::string selected;
GetAndMergeKeyboardLayoutsForLocale(util, requested_locale, &selected,
&layouts);
GetAndMergeKeyboardLayoutsForLocale(util, resolved_locale, &selected,
&layouts);
std::unique_ptr<base::ListValue> input_methods_list(new base::ListValue);
std::set<std::string> input_methods_added;
for (std::vector<std::string>::const_iterator it = layouts.begin();
it != layouts.end(); ++it) {
const input_method::InputMethodDescriptor* ime =
util->GetInputMethodDescriptorFromId(*it);
if (!InsertString(ime->id(), &input_methods_added))
continue;
input_methods_list->Append(CreateInputMethodsEntry(*ime, selected));
}
callback.Run(std::move(input_methods_list));
}
// For "UI Language" drop-down menu at OOBE screen we need to decide which
// entry to mark "selected". If user has just selected "requested_locale",
// but "loaded_locale" was actually loaded, we mark original user choice
// "selected" only if loaded_locale is a backup for "requested_locale".
std::string CalculateSelectedLanguage(const std::string& requested_locale,
const std::string& loaded_locale) {
std::string resolved_locale;
if (!l10n_util::CheckAndResolveLocale(requested_locale, &resolved_locale))
return loaded_locale;
if (resolved_locale == loaded_locale)
return requested_locale;
return loaded_locale;
}
void ResolveLanguageListInThreadPool(
std::unique_ptr<chromeos::locale_util::LanguageSwitchResult>
language_switch_result,
const scoped_refptr<base::TaskRunner> task_runner,
const UILanguageListResolvedCallback& resolved_callback) {
base::ScopedBlockingCall scoped_blocking_call(FROM_HERE,
base::BlockingType::MAY_BLOCK);
std::string selected_language;
if (!language_switch_result) {
if (!g_browser_process->GetApplicationLocale().empty()) {
selected_language = g_browser_process->GetApplicationLocale();
} else {
selected_language =
StartupCustomizationDocument::GetInstance()->initial_locale_default();
}
} else {
if (language_switch_result->success) {
if (language_switch_result->requested_locale ==
language_switch_result->loaded_locale) {
selected_language = language_switch_result->requested_locale;
} else {
selected_language =
CalculateSelectedLanguage(language_switch_result->requested_locale,
language_switch_result->loaded_locale);
}
} else {
selected_language = language_switch_result->loaded_locale;
}
}
const std::string selected_code =
selected_language.empty() ? g_browser_process->GetApplicationLocale()
: selected_language;
const std::string list_locale =
language_switch_result ? language_switch_result->loaded_locale
: g_browser_process->GetApplicationLocale();
std::unique_ptr<base::ListValue> language_list(
chromeos::GetUILanguageList(nullptr, selected_code));
task_runner->PostTask(
FROM_HERE, base::BindOnce(resolved_callback, base::Passed(&language_list),
list_locale, selected_language));
}
void AdjustUILanguageList(const std::string& selected,
base::ListValue* languages_list) {
for (size_t i = 0; i < languages_list->GetSize(); ++i) {
base::DictionaryValue* language_info = NULL;
if (!languages_list->GetDictionary(i, &language_info))
NOTREACHED();
std::string value;
language_info->GetString("code", &value);
std::string display_name;
language_info->GetString("displayName", &display_name);
std::string native_name;
language_info->GetString("nativeDisplayName", &native_name);
// If it's an option group divider, add field name.
if (value == kMostRelevantLanguagesDivider) {
language_info->SetString(
"optionGroupName",
l10n_util::GetStringUTF16(IDS_OOBE_OTHER_LANGUAGES));
}
if (display_name != native_name) {
display_name = base::StringPrintf("%s - %s",
display_name.c_str(),
native_name.c_str());
}
language_info->SetString("value", value);
language_info->SetString("title", display_name);
if (value == selected)
language_info->SetBoolean("selected", true);
}
}
} // namespace
void ResolveUILanguageList(
std::unique_ptr<chromeos::locale_util::LanguageSwitchResult>
language_switch_result,
const UILanguageListResolvedCallback& callback) {
DCHECK_CURRENTLY_ON(content::BrowserThread::UI);
base::PostTask(
FROM_HERE, {base::ThreadPool(), base::MayBlock()},
base::BindOnce(&ResolveLanguageListInThreadPool,
base::Passed(&language_switch_result),
base::SequencedTaskRunnerHandle::Get(), callback));
}
std::unique_ptr<base::ListValue> GetMinimalUILanguageList() {
const std::string application_locale =
g_browser_process->GetApplicationLocale();
base::string16 language_native_display_name =
l10n_util::GetDisplayNameForLocale(
application_locale, application_locale, true);
std::unique_ptr<base::ListValue> language_list(new base::ListValue());
language_list->Append(CreateLanguageEntry(application_locale,
language_native_display_name,
language_native_display_name));
AdjustUILanguageList(std::string(), language_list.get());
return language_list;
}
std::unique_ptr<base::ListValue> GetUILanguageList(
const std::vector<std::string>* most_relevant_language_codes,
const std::string& selected) {
ComponentExtensionIMEManager* manager =
input_method::InputMethodManager::Get()
->GetComponentExtensionIMEManager();
input_method::InputMethodDescriptors descriptors =
manager->GetXkbIMEAsInputMethodDescriptor();
std::unique_ptr<base::ListValue> languages_list(GetLanguageList(
descriptors, l10n_util::GetAvailableLocales(),
most_relevant_language_codes
? *most_relevant_language_codes
: StartupCustomizationDocument::GetInstance()->configured_locales(),
true));
AdjustUILanguageList(selected, languages_list.get());
return languages_list;
}
std::string FindMostRelevantLocale(
const std::vector<std::string>& most_relevant_language_codes,
const base::ListValue& available_locales,
const std::string& fallback_locale) {
for (std::vector<std::string>::const_iterator most_relevant_it =
most_relevant_language_codes.begin();
most_relevant_it != most_relevant_language_codes.end();
++most_relevant_it) {
for (base::ListValue::const_iterator available_it =
available_locales.begin();
available_it != available_locales.end(); ++available_it) {
const base::DictionaryValue* dict;
std::string available_locale;
if (!available_it->GetAsDictionary(&dict) ||
!dict->GetString("value", &available_locale)) {
NOTREACHED();
continue;
}
if (available_locale == *most_relevant_it)
return *most_relevant_it;
}
}
return fallback_locale;
}
std::unique_ptr<base::ListValue> GetAcceptLanguageList() {
// Collect the language codes from the supported accept-languages.
const std::string app_locale = g_browser_process->GetApplicationLocale();
std::vector<std::string> accept_language_codes;
l10n_util::GetAcceptLanguagesForLocale(app_locale, &accept_language_codes);
return GetLanguageList(
*input_method::InputMethodManager::Get()->GetSupportedInputMethods(),
accept_language_codes,
StartupCustomizationDocument::GetInstance()->configured_locales(),
false);
}
std::unique_ptr<base::ListValue> GetAndActivateLoginKeyboardLayouts(
const std::string& locale,
const std::string& selected,
bool activate_keyboards) {
std::unique_ptr<base::ListValue> input_methods_list(new base::ListValue);
input_method::InputMethodManager* manager =
input_method::InputMethodManager::Get();
input_method::InputMethodUtil* util = manager->GetInputMethodUtil();
const std::vector<std::string>& hardware_login_input_methods =
util->GetHardwareLoginInputMethodIds();
if (activate_keyboards) {
DCHECK(
ProfileHelper::IsSigninProfile(ProfileManager::GetActiveUserProfile()));
manager->GetActiveIMEState()->EnableLoginLayouts(
locale, hardware_login_input_methods);
}
std::unique_ptr<input_method::InputMethodDescriptors> input_methods(
manager->GetActiveIMEState()->GetActiveInputMethods());
std::set<std::string> input_methods_added;
for (std::vector<std::string>::const_iterator i =
hardware_login_input_methods.begin();
i != hardware_login_input_methods.end();
++i) {
const input_method::InputMethodDescriptor* ime =
util->GetInputMethodDescriptorFromId(*i);
// Do not crash in case of misconfiguration.
if (ime) {
input_methods_added.insert(*i);
input_methods_list->Append(CreateInputMethodsEntry(*ime, selected));
} else {
NOTREACHED();
}
}
bool optgroup_added = false;
for (size_t i = 0; i < input_methods->size(); ++i) {
// Makes sure the id is in legacy xkb id format.
const std::string& ime_id = (*input_methods)[i].id();
if (!InsertString(ime_id, &input_methods_added))
continue;
if (!optgroup_added) {
optgroup_added = true;
AddOptgroupOtherLayouts(input_methods_list.get());
}
input_methods_list->Append(
CreateInputMethodsEntry((*input_methods)[i], selected));
}
// "xkb:us::eng" should always be in the list of available layouts.
const std::string us_keyboard_id =
util->GetFallbackInputMethodDescriptor().id();
if (input_methods_added.find(us_keyboard_id) == input_methods_added.end()) {
const input_method::InputMethodDescriptor* us_eng_descriptor =
util->GetInputMethodDescriptorFromId(us_keyboard_id);
DCHECK(us_eng_descriptor);
if (!optgroup_added) {
optgroup_added = true;
AddOptgroupOtherLayouts(input_methods_list.get());
}
input_methods_list->Append(
CreateInputMethodsEntry(*us_eng_descriptor, selected));
manager->GetActiveIMEState()->EnableInputMethod(us_keyboard_id);
}
return input_methods_list;
}
void GetKeyboardLayoutsForLocale(
const GetKeyboardLayoutsForLocaleCallback& callback,
const std::string& locale) {
// Resolve |locale| on a background thread, then continue on the current
// thread.
std::string (*get_application_locale)(const std::string&, bool) =
&l10n_util::GetApplicationLocale;
base::PostTaskAndReplyWithResult(
FROM_HERE,
{base::ThreadPool(), base::MayBlock(),
base::TaskShutdownBehavior::SKIP_ON_SHUTDOWN},
base::BindOnce(get_application_locale, locale,
false /* set_icu_locale */),
base::BindOnce(&GetKeyboardLayoutsForResolvedLocale, locale, callback));
}
std::unique_ptr<base::DictionaryValue> GetCurrentKeyboardLayout() {
const input_method::InputMethodDescriptor current_input_method =
input_method::InputMethodManager::Get()
->GetActiveIMEState()
->GetCurrentInputMethod();
return CreateInputMethodsEntry(current_input_method,
current_input_method.id());
}
} // namespace chromeos
| [
"rjkroege@chromium.org"
] | rjkroege@chromium.org |
386bd914f68fb2f9014479317f208b86b0927000 | 00da929f354d5a9f547d0374b206108d1ea8a8f6 | /jni/jni_common/rgb2yuv.h | ac0ea7680fb9a3ad6dc66ef43b993c8a4efb7944 | [
"MIT"
] | permissive | LightSun/dlib-face-recognition-android | fe7fd32116f59960b0384db1c2c5fdfb4e71367f | 738eb5345b90b57cbca5e15f8dcac0cea896c3ab | refs/heads/master | 2020-03-28T20:30:06.030200 | 2018-09-18T12:42:54 | 2018-09-18T12:42:54 | 149,076,552 | 0 | 0 | MIT | 2018-09-17T06:05:46 | 2018-09-17T06:05:46 | null | UTF-8 | C++ | false | false | 585 | h | /*
* rgb2yuv.h using google-style
*
* Created on: May 24, 2016
* Author: Tzutalin
*
* Copyright (c) 2016 Tzutalin. All rights reserved.
*/
#pragma once
#include <jni_common/types.h>
namespace jnicommon {
#ifdef __cplusplus
extern "C" {
#endif
void ConvertARGB8888ToYUV420SP(const uint32* const input, uint8* const output,
int width, int height);
void ConvertRGB565ToYUV420SP(const uint16* const input, uint8* const output,
const int width, const int height);
#ifdef __cplusplus
} // end jnicommon
}
#endif
| [
"gauravguptakgn@gmail.com"
] | gauravguptakgn@gmail.com |
4e0f315bcc3bf9bd5065a49e67acbd6fbb6eff61 | 4bf2523f9a57ef0728630d05ce2d38b05686547d | /Compo/Dev_Ex/ExpressQuantumGrid 6/Packages/dclcxGridC14.cpp | 46b7c347f606ff2b9ef59e685e25200692e3ae38 | [] | no_license | zeroptr/ceda_tic | 980bee99b829f99575586b5110985ba90f8f56aa | 72586d6a10a5426a889d45ad37479c1bf6f3fb49 | refs/heads/main | 2023-03-17T16:36:58.586885 | 2021-03-07T20:30:34 | 2021-03-07T20:30:34 | 345,381,196 | 0 | 3 | null | null | null | null | UTF-8 | C++ | false | false | 2,000 | cpp | //---------------------------------------------------------------------------
#include <vcl.h>
#pragma hdrstop
USERES("dclcxGridC14.res");
USEPACKAGE("vcl.bpi");
USEPACKAGE("rtl.bpi");
USEPACKAGE("dxCoreC14.bpi");
USEPACKAGE("designide.bpi");
USEPACKAGE("vcldb.bpi");
USEPACKAGE("dbrtl.bpi");
USEPACKAGE("cxDataC14.bpi");
USEPACKAGE("cxEditorsC14.bpi");
USEPACKAGE("cxGridC14.bpi");
USEPACKAGE("cxLibraryC14.bpi");
USEPACKAGE("dclcxEditorsC14.bpi");
USEPACKAGE("dclcxLibraryC14.bpi");
USEPACKAGE("cxPageControlC14.bpi");
USEPACKAGE("dxThemeC14.bpi");
USEFORMNS("cxGridViewLayoutEditor.pas", Cxgridviewlayouteditor, cxGridViewLayoutEditor);
USEUNIT("cxCardViewEditor.pas");
USEUNIT("cxCustomTableViewEditor.pas");
USEUNIT("cxDBGridConverter.pas");
USEUNIT("cxDXGridConverter.pas");
USEFORMNS("cxGridEditor.pas", Cxgrideditor, cxGridEditor);
USEFORMNS("cxGridImportDialog.pas", Cxgridimportdialog, ImportDialog);
USEFORMNS("cxGridPredefinedStyles.pas", Cxgridpredefinedstyles, cxdmGridPredefinedStyles); /* TDataModule: File Type */
USEFORMNS("cxImageComboBoxItemsEditor.pas", Cximagecomboboxitemseditor, fmImageComboBoxItemsEditor);
USEUNIT("cxGridReg.pas");
USERES("cxGridReg.dcr");
USEUNIT("cxGridStructureNavigator.pas");
USEUNIT("cxChartViewEditor.pas");
USEUNIT("cxBandedTableViewEditor.pas");
USEUNIT("cxTableViewEditor.pas");
USEFORMNS("cxViewEditor.pas", Cxvieweditor, cxViewEditor);
USEUNIT("cxWWGridConverter.pas");
USEUNIT("cxGridConverter.pas");
USEUNIT("cxGridPopupMenuReg.pas");
USERES("cxGridPopupMenuReg.dcr");
//---------------------------------------------------------------------------
#pragma package(smart_init)
//---------------------------------------------------------------------------
// Package source.
//---------------------------------------------------------------------------
#pragma argsused
int WINAPI DllEntryPoint(HINSTANCE hinst, unsigned long reason, void*)
{
return 1;
}
//---------------------------------------------------------------------------
| [
"53816327+zeroptr@users.noreply.github.com"
] | 53816327+zeroptr@users.noreply.github.com |
8bcb64859568111100ee50da23af0d79f2df1fa7 | 74b3058ff7aead32d7691d3fda836acae9cddc95 | /algorithm/0540/res.cpp | f3da935862d015d6d2869f268b42044a2321e453 | [] | no_license | onehumanbeing/leetcode | 647f6d09a4b6c8075e2e254de2e99a5664864bba | 7fc0a7a87b082d5e8c63a35ee5f282b2d3f43bcb | refs/heads/master | 2020-03-22T10:03:04.967533 | 2018-09-09T09:01:53 | 2018-09-09T09:01:53 | 139,877,549 | 2 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 263 | cpp | #include <iostream>
#include <vector>
using namespace std;
//您的方案应该在 O(log n)时间复杂度和 O(1)空间复杂度中运行。
class Solution {
public:
int singleNonDuplicate(vector<int>& nums) {
}
};
int main(){
return 0;
} | [
"henryhenryhenry111@126.com"
] | henryhenryhenry111@126.com |
f214adae736cc4cc9ec7586666c37623e8af8f87 | 1e600374bdcf8ddbd632695aa424e03a88471460 | /Xilinx_HLS_Lab_Materials/hls/completed/improve_area/dct_prj/solution6/syn/systemc/dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2.h | cd75506304538c4483b784df4b927f12ceb5bb14 | [] | no_license | chongxi/vivado_hls_training | 960595275bfe1b530baeb5859958c32ef0415d05 | bc9a9958fcf39b2af026c2531249726fe71f7e93 | refs/heads/master | 2020-09-09T18:00:14.064048 | 2016-09-07T20:31:52 | 2016-09-07T20:31:52 | 67,640,668 | 0 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 2,610 | h | // ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef __dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_H__
#define __dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_H__
#include <systemc>
using namespace sc_core;
using namespace sc_dt;
#include <iostream>
#include <fstream>
struct dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_ram : public sc_core::sc_module {
static const unsigned DataWidth = 15;
static const unsigned AddressRange = 8;
static const unsigned AddressWidth = 3;
//latency = 1
//input_reg = 1
//output_reg = 0
sc_core::sc_in <sc_lv<AddressWidth> > address0;
sc_core::sc_in <sc_logic> ce0;
sc_core::sc_out <sc_lv<DataWidth> > q0;
sc_core::sc_in<sc_logic> reset;
sc_core::sc_in<bool> clk;
sc_lv<DataWidth> ram[AddressRange];
SC_CTOR(dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_ram) {
ram[0] = "0b010000000000000";
ram[1] = "0b001100100100100";
ram[2] = "0b110111010101111";
ram[3] = "0b101001110011110";
ram[4] = "0b110000000000000";
ram[5] = "0b000100011010100";
ram[6] = "0b010100111001111";
ram[7] = "0b010010110100001";
SC_METHOD(prc_write_0);
sensitive<<clk.pos();
}
void prc_write_0()
{
if (ce0.read() == sc_dt::Log_1)
{
if(address0.read().is_01() && address0.read().to_uint()<AddressRange)
q0 = ram[address0.read().to_uint()];
else
q0 = sc_lv<DataWidth>();
}
}
}; //endmodule
SC_MODULE(dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2) {
static const unsigned DataWidth = 15;
static const unsigned AddressRange = 8;
static const unsigned AddressWidth = 3;
sc_core::sc_in <sc_lv<AddressWidth> > address0;
sc_core::sc_in<sc_logic> ce0;
sc_core::sc_out <sc_lv<DataWidth> > q0;
sc_core::sc_in<sc_logic> reset;
sc_core::sc_in<bool> clk;
dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_ram* meminst;
SC_CTOR(dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2) {
meminst = new dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_ram("dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2_ram");
meminst->address0(address0);
meminst->ce0(ce0);
meminst->q0(q0);
meminst->reset(reset);
meminst->clk(clk);
}
~dct_Loop_Row_DCT_Loop_proc_dct_coeff_table_2() {
delete meminst;
}
};//endmodule
#endif
| [
"chongxi.lai@me.com"
] | chongxi.lai@me.com |
172639890d094e4b493db4a883aa42406fbb7c56 | b174c3f08406d45631b90878000042428f693069 | /src/VeloPacketsReader.cpp | 06f70187918980f8d65a93ce767ae14f9b06a89a | [
"MIT"
] | permissive | Tenant/pointcloud_converter | 1e4d0e828448edfba89909d52af73020b53963ae | b5bc8de273158ec03c6b20699145c36399864a0c | refs/heads/master | 2022-12-26T04:05:53.797872 | 2020-09-30T09:36:09 | 2020-09-30T09:36:09 | 299,519,171 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 998 | cpp | //
// Created by akira on 18-7-22.
//
#include "../include/VeloPacketsReader.h"
VeloPacketsReader::VeloPacketsReader() {
}
bool VeloPacketsReader::open(std::string packetfile) {
ofile.open(packetfile);
this->packetdata = new unsigned char[PACKETSIZE];
return ofile.fail();
}
void VeloPacketsReader::release() {
ofile.close();
if(this->packetdata != nullptr) {
delete[] this->packetdata;
this->packetdata = nullptr;
}
}
bool VeloPacketsReader::nextPacket(PacketData &packet) {
packet = PacketData(this->packetdata);
packet.size(PACKETSIZE);
long long time;
ofile.read((char*)&time, 8);
if(ofile.gcount() != 8)
return false;
packet.setHeaderTime(time);
ofile.read((char*)this->packetdata, PACKETSIZE);
if(ofile.gcount() != PACKETSIZE)
return false;
return true;
}
VeloPacketsReader::~VeloPacketsReader() {
this->release();
}
void VeloPacketsReader::reset() {
ofile.seekg(0, std::ios::beg);
}
| [
"gaoshuqi@pku.edu.cn"
] | gaoshuqi@pku.edu.cn |
7c361806d7519fdbe453c860ccfd2ac01cf8567a | 14ab5fdf93666403e2a6f54211618aabd4785f3b | /Arbol.h | 772b228c0b6850be96e860d02ce519e2ed736c30 | [] | no_license | carlosverduzco/8_Puzzle_Busqueda_En_Profundidad | cc7567c2db0f2ddba28866f100565151d8933563 | dd4a91bf0d1bd20ae63bf935d613f10b4d267deb | refs/heads/master | 2023-08-23T19:49:20.467780 | 2021-10-11T04:58:48 | 2021-10-11T04:58:48 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 9,179 | h | //
// Created by Dorian on 21/09/2021.
//
#ifndef BUSQUEDAENPROFUNDIDAD_8_PUZZLE_ARBOL_H
#define BUSQUEDAENPROFUNDIDAD_8_PUZZLE_ARBOL_H
#include "string"
#include "vector"
#include <iostream>
using namespace std;
class Nodo {
private:
Nodo* padre = nullptr;
Nodo* hermano = nullptr;
Nodo* primerHijo = nullptr;
string cadena;
int profundidad;
bool estaEstancado = false;
public:
Nodo() {}
Nodo(string cadena) {
this->cadena = cadena;
}
Nodo(string cadena, Nodo* padre, int profundidad) {
this->cadena = cadena;
this->padre = padre;
this->profundidad = profundidad;
}
Nodo* getPadre() {
return padre;
}
string getCadena() {
return cadena;
}
void setProfundidad(int profundidad){
this->profundidad = profundidad;
}
int getProfundidad(){
return this->profundidad;
}
bool getEstaEstancado () {
return this->estaEstancado;
}
void setEstaEstancado (bool estaEstancado) {
this->estaEstancado = estaEstancado;
}
void setHermano(Nodo* hermano) {
this->hermano = hermano;
}
Nodo* getHermano() {
return this->hermano;
}
Nodo* getPrimerHijo() const {
return primerHijo;
}
void setPrimerHijo(Nodo* primerHijo) {
this->primerHijo = primerHijo;
}
void print() {
cout << "Cadena:" << this->getCadena() << " - Padre:" << this->padre->getCadena() << endl;
}
};
class Arbol {
private:
int findZero(string cadena){
for (int i=0 ; i < cadena.length(); i++) {
if (cadena[i] == '0')
return i;
}
return -1;
}
string cambiarCaracteres (string cadena, int posicion1, int posicion2) {
char caracter1 = cadena[posicion1];
char caracter2 = cadena[posicion2];
cadena[posicion1] = caracter2;
cadena[posicion2] = caracter1;
return cadena;
}
vector<string> getMovimientosPosibles(string cadena) {
int posicionDeCero = findZero(cadena);
vector<string> arregloDePosiblesResultados;
switch(posicionDeCero){
case 0:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,0,1));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,0,3));
break;
case 1:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,1,0));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,1,2));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,1,4));
break;
case 2:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,2,1));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,2,5));
break;
case 3:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,3,0));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,3,4));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,3,6));
break;
case 4:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,4,1));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,4,3));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,4,5));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,4,7));
break;
case 5:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,5,2));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,5,4));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,5,8));
break;
case 6:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,6,3));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,6,7));
break;
case 7:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,7,4));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,7,6));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,7,8));
break;
case 8:
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,8,5));
arregloDePosiblesResultados.push_back(cambiarCaracteres(cadena,8,7));
break;
}
return arregloDePosiblesResultados;
}
vector<string> getPath(Nodo* resultado) {
vector<string> path;
Nodo* c = resultado;
while (c) {
path.push_back(c->getCadena());
c = c->getPadre();
}
return path;
}
bool checarSiLaRamaSeEstanco (Nodo* nodoAVerificar) {
string cadenaDelNodoAVerificar = nodoAVerificar->getCadena();
nodoAVerificar = nodoAVerificar->getPadre();
while (nodoAVerificar) {
if (nodoAVerificar->getCadena() == cadenaDelNodoAVerificar)
return true;
nodoAVerificar = nodoAVerificar->getPadre();
}
return false;
}
Nodo* ancla;
string punto_de_partida;
string resultado_esperado = "012345678";
uint64_t nodos_creados = 0;
public:
Arbol(string punto_de_partida) {
this->punto_de_partida = punto_de_partida;
ancla = new Nodo(punto_de_partida);
ancla->setProfundidad(0);
};
uint64_t getNodosCreados() {
return this->nodos_creados;
}
string getPuntoObjetivo() {
return this->resultado_esperado;
}
vector<string> busquedaPorProfundidad () {
Nodo* resultado = ancla;
if (resultado->getCadena() == this->resultado_esperado) {
cout << "Resultado Encontrado" << endl;
return getPath(resultado);
}
while (true) {
if (!resultado->getEstaEstancado()) {
vector<string> proximos_hijos = getMovimientosPosibles(resultado->getCadena());
Nodo *hijoPasado = nullptr;
for (string cadena_del_hijo: proximos_hijos) {
Nodo *hijo = new Nodo(cadena_del_hijo, resultado, (resultado->getProfundidad()) + 1);
if (hijo->getCadena() == this->resultado_esperado) {
cout << "Resultado Encontrado" << endl;
return getPath(hijo);
}
//hijo->print();
nodos_creados++;
if (hijoPasado) {
hijoPasado->setHermano(hijo);
} else {
hijo->getPadre()->setPrimerHijo(hijo);
}
hijo->setEstaEstancado(checarSiLaRamaSeEstanco(hijo));
hijoPasado = hijo;
}
}
if (resultado->getPrimerHijo()) {
resultado = resultado->getPrimerHijo();
} else if (resultado->getHermano()) {
resultado = resultado->getHermano();
} else {
do {
resultado = resultado->getPadre();
} while (!resultado->getHermano());
resultado = resultado->getHermano();
}
if (resultado)
cout <<"Nodos creados: "<< this->nodos_creados << " - Profunfidad actual:" <<resultado->getProfundidad()<< endl;
}
}
Nodo* search(Nodo* resultado) {
if (!resultado->getEstaEstancado()) {
vector<string> proximos_hijos = getMovimientosPosibles(resultado->getCadena());
Nodo *hijoPasado = nullptr;
for (string cadena_del_hijo: proximos_hijos) {
Nodo *hijo = new Nodo(cadena_del_hijo, resultado, (resultado->getProfundidad()) + 1);
if (resultado->getCadena() == this->resultado_esperado) {
cout << "Resultado Encontrado" << endl;
return resultado;
}
//hijo->print();
nodos_creados++;
if (hijoPasado) {
hijoPasado->setHermano(hijo);
} else {
hijo->getPadre()->setPrimerHijo(hijo);
}
hijo->setEstaEstancado(checarSiLaRamaSeEstanco(hijo));
hijoPasado = hijo;
}
resultado = resultado->getPrimerHijo();
Nodo *respuesta = nullptr;
while(resultado){
if (resultado)
cout <<"Nodos creados: "<< this->nodos_creados << " - Profunfidad actual:" <<resultado->getProfundidad()<< endl;
respuesta = search(resultado);
if (respuesta) {
return respuesta;
}
resultado = resultado->getHermano();
}
}
return nullptr;
}
};
#endif //BUSQUEDAENPROFUNDIDAD_8_PUZZLE_ARBOL_H
| [
"carloseverduzco@hotmail.com"
] | carloseverduzco@hotmail.com |
b54776139ad93ee67c5367d082192ae23b706990 | a8ae52d335a392ca10fc7e4e562139a7b6e942ee | /src/server/collision/Maps/TileAssembler.h | fb3b234aae49f26d694f8f86e609e52b96bce6ee | [] | no_license | bromacia/ProjectAxium | 54f3c622b17039c94b02914f22a1762cd635b327 | e815318616a57a343f9883340af7b8cb93007682 | refs/heads/master | 2021-04-27T11:03:48.445914 | 2017-09-09T18:16:53 | 2017-09-09T18:16:53 | 122,552,525 | 1 | 0 | null | 2018-02-23T00:29:29 | 2018-02-23T00:29:28 | null | UTF-8 | C++ | false | false | 2,895 | h | #ifndef _TILEASSEMBLER_H_
#define _TILEASSEMBLER_H_
#include <G3D/Vector3.h>
#include <G3D/Matrix3.h>
#include <map>
#include <set>
#include "ModelInstance.h"
#include "WorldModel.h"
namespace VMAP
{
/**
This Class is used to convert raw vector data into balanced BSP-Trees.
To start the conversion call convertWorld().
*/
//===============================================
class ModelPosition
{
private:
G3D::Matrix3 iRotation;
public:
G3D::Vector3 iPos;
G3D::Vector3 iDir;
float iScale;
void init()
{
iRotation = G3D::Matrix3::fromEulerAnglesZYX(G3D::pi()*iDir.y/180.f, G3D::pi()*iDir.x/180.f, G3D::pi()*iDir.z/180.f);
}
G3D::Vector3 transform(const G3D::Vector3& pIn) const;
void moveToBasePos(const G3D::Vector3& pBasePos) { iPos -= pBasePos; }
};
typedef std::map<uint32, ModelSpawn> UniqueEntryMap;
typedef std::multimap<uint32, uint32> TileMap;
struct MapSpawns
{
UniqueEntryMap UniqueEntries;
TileMap TileEntries;
};
typedef std::map<uint32, MapSpawns*> MapData;
//===============================================
struct GroupModel_Raw
{
uint32 mogpflags;
uint32 GroupWMOID;
G3D::AABox bounds;
uint32 liquidflags;
std::vector<MeshTriangle> triangles;
std::vector<G3D::Vector3> vertexArray;
class WmoLiquid *liquid;
GroupModel_Raw() : liquid(0) {}
~GroupModel_Raw();
bool Read(FILE * f);
};
struct WorldModel_Raw
{
uint32 RootWMOID;
std::vector<GroupModel_Raw> groupsArray;
bool Read(const char * path);
};
class TileAssembler
{
private:
std::string iDestDir;
std::string iSrcDir;
bool (*iFilterMethod)(char *pName);
G3D::Table<std::string, unsigned int > iUniqueNameIds;
unsigned int iCurrentUniqueNameId;
MapData mapData;
std::set<std::string> spawnedModelFiles;
public:
TileAssembler(const std::string& pSrcDirName, const std::string& pDestDirName);
virtual ~TileAssembler();
bool convertWorld2();
bool readMapSpawns();
bool calculateTransformedBound(ModelSpawn &spawn);
void exportGameobjectModels();
bool convertRawFile(const std::string& pModelFilename);
void setModelNameFilterMethod(bool (*pFilterMethod)(char *pName)) { iFilterMethod = pFilterMethod; }
std::string getDirEntryNameFromModName(unsigned int pMapId, const std::string& pModPosName);
};
} // VMAP
#endif /*_TILEASSEMBLER_H_*/
| [
"saeshyls@gmail.com"
] | saeshyls@gmail.com |
8190565c00af8884b8bc0d5472443de99eab59e7 | ecaab460af763306936529b981db0a996f1c865c | /include/utils/Drawings.h | e902b23831e436b388c5c7a7b04853ef84599be8 | [] | no_license | comkieffer/teleop-vision | 95673f10a711305470542b2741cdb6c7ec2b1cc3 | 95f7d7272e659fb27256584a8bb2726bfe5cf7e6 | refs/heads/master | 2021-01-19T02:28:26.790374 | 2017-04-03T23:19:26 | 2017-04-03T23:19:26 | 87,282,061 | 0 | 0 | null | 2017-04-05T07:52:44 | 2017-04-05T07:52:44 | null | UTF-8 | C++ | false | false | 3,287 | h | //
// Created by charm on 3/19/17.
//
#ifndef TELEOP_VISION_DRAWINGS_H
#define TELEOP_VISION_DRAWINGS_H
#include <opencv2/highgui/highgui.hpp>
#include <opencv2/calib3d/calib3d.hpp>
#include <opencv2/imgproc.hpp>
#include <kdl/frames.hpp>
struct CameraIntrinsics {
cv::Mat camMatrix;
cv::Mat distCoeffs;
};
namespace DrawingsCV{
/*!
* \briefUses opencv line function to draw a cube in task coordinate frame
*
* \param rvec is the orientation of the task coordinate frame in camera frame
* \param tvec is the the position of the task coordinate frame in camera frame
*/
void DrawCube(cv::InputOutputArray image,
const CameraIntrinsics &cam_intrinsics,
const cv::Vec3d &rvec, const cv::Vec3d &tvec,
const cv::Point3d &origin, const cv::Point3d &whd,
const cv::Scalar &color);
/*!
* \brief Draws a circle at the tool tip. Position is in task coordinate
* frame (task-space).
* \param rvec is the orientation of the task coordinate frame in camera frame
* \param tvec is the the position of the task coordinate frame in camera frame
*/
void DrawPoint(cv::InputOutputArray image,
const CameraIntrinsics &cam_intrinsics,
const cv::Vec3d &rvec, const cv::Vec3d &tvec,
KDL::Vector position,
const cv::Scalar color);
/*!
* \brief Uses opencv circle to draw a point at each element of the input vector.
*
* \param rvec is the orientation of the task coordinate frame in camera frame
* \param tvec is the the position of the task coordinate frame in camera frame
*/
void DrawPoint3dVector(cv::InputOutputArray image,
const std::vector<cv::Point3d> &points,
const CameraIntrinsics &cam_intrinsics,
const cv::Vec3d &rvec, const cv::Vec3d &tvec,
const cv::Scalar color);
void DrawLineFrom2KDLPoints(cv::InputOutputArray image,
const CameraIntrinsics &cam_intrinsics,
const cv::Vec3d &rvec,
const cv::Vec3d &tvec,
KDL::Vector current,
KDL::Vector desired,
const cv::Scalar color);
/*!
* \brief Uses opencv line to draw a coordinate frame seen from task coordinate frame
*
* \param rvec is the orientation of the task coordinate frame in camera frame
* \param tvec is the the position of the task coordinate frame in camera frame
*/
void DrawCoordinateFrameAntiAliased(const cv::InputOutputArray &_image,
const CameraIntrinsics &cam_intrinsics,
const cv::Vec3d &rvec, const cv::Vec3d &tvec,
float length);
void DrawCoordinateFrameInTaskSpace(
const cv::InputOutputArray &image, const CameraIntrinsics &cam_intrinsics,
const KDL::Frame,
const cv::Vec3d &rvec, const cv::Vec3d &tvec,
float length);
}
#endif //TELEOP_VISION_DRAWINGS_H
| [
"nima.en@gmail.com"
] | nima.en@gmail.com |
d488f0df0f1e15fe9d557cf573a3a80b687f430a | b97c1b35c0e6350c49bac6b3b489652584977d01 | /src/MissSbm.cpp | f9a1eae508f0fb95ed5fee5cef531fdd82c7db21 | [] | no_license | minghao2016/greed | 42f8e104381744ce719b2cb614652608182419f9 | 0cc68aac7fed229db1d8e4dbdeb0b16e0b466e2c | refs/heads/master | 2023-04-20T07:28:53.538857 | 2021-05-11T10:22:58 | 2021-05-11T10:22:58 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 6,385 | cpp | // [[Rcpp::depends(RcppArmadillo)]]
#include "gicl_tools.h"
#include "MergeMat.h"
#include "IclModel.h"
#include "MissSbm.h"
using namespace Rcpp;
MissSbm::MissSbm(arma::sp_mat& xp,arma::sp_mat& xpobs,S4 modeli,arma::vec& clt,bool verb){
model = modeli;
alpha = model.slot("alpha");
a0 = model.slot("a0");
b0 = model.slot("b0");
List sampling_priors = as<List>(model.slot("sampling_priors"));
a0obs = sampling_priors["a0obs"];
b0obs = sampling_priors["b0obs"];
x = xp;
xt = xp.t();
xobs = xpobs;
xtobs = xpobs.t();
N = x.n_rows;
set_cl(clt);
verbose=verb;
}
void MissSbm::set_cl(arma::vec clt){
cl = clt;
K = arma::max(cl)+1;
x_counts = gsum_mat(cl,x,K);
x_counts_obs = gsum_mat(cl,xobs,K);
counts = count(cl,K);
}
double MissSbm::icl_emiss(const List & obs_stats){
return 0;
}
double MissSbm::icl_emiss(const List & obs_stats,int oldcl,int newcl){
return 0;
}
List MissSbm::get_obs_stats(){
return List::create(Named("counts", counts), Named("x_counts", x_counts),Named("x_counts_obs", x_counts_obs));
}
arma::mat MissSbm::delta_swap(int i,arma::uvec iclust){
int self=x(i,i);
int selfobs=xobs(i,i);
int oldcl = cl(i);
arma::sp_mat col_sum = gsum_col(cl,x,i,K);
col_sum(oldcl)=col_sum(oldcl)-self;
arma::sp_mat col_sum_obs = gsum_col(cl,xobs,i,K);
col_sum_obs(oldcl)=col_sum_obs(oldcl)-selfobs;
arma::sp_mat row_sum = gsum_col(cl,xt,i,K);
row_sum(oldcl)=row_sum(oldcl)-self;
arma::sp_mat row_sum_obs = gsum_col(cl,xtobs,i,K);
row_sum_obs(oldcl)=row_sum_obs(oldcl)-selfobs;
arma::vec delta(K);
delta.fill(-std::numeric_limits<double>::infinity());
delta(oldcl)=0;
List old_stats = List::create(Named("counts", counts), Named("x_counts", x_counts), Named("x_counts_obs", x_counts_obs));
int k = 0;
// for each possible move
for(arma::uword j = 0; j < iclust.n_elem; ++j) {
k=iclust(j);
if(k!=oldcl){
arma::mat new_ec = x_counts;
new_ec.col(k) = new_ec.col(k)+col_sum;
new_ec.row(k) = new_ec.row(k)+row_sum.t();
new_ec.col(oldcl) = new_ec.col(oldcl)-col_sum;
new_ec.row(oldcl) = new_ec.row(oldcl)-row_sum.t();
new_ec(k,k)=new_ec(k,k)+self;
new_ec(oldcl,oldcl)=new_ec(oldcl,oldcl)-self;
arma::mat new_ec_obs = x_counts_obs;
new_ec_obs.col(k) = new_ec_obs.col(k)+col_sum_obs;
new_ec_obs.row(k) = new_ec_obs.row(k)+row_sum_obs.t();
new_ec_obs.col(oldcl) = new_ec_obs.col(oldcl)-col_sum_obs;
new_ec_obs.row(oldcl) = new_ec_obs.row(oldcl)-row_sum_obs.t();
new_ec_obs(k,k)=new_ec_obs(k,k)+selfobs;
new_ec_obs(oldcl,oldcl)=new_ec_obs(oldcl,oldcl)-selfobs;
arma::vec new_counts = update_count(counts,oldcl,k);
List new_stats = List::create(Named("counts", new_counts), Named("x_counts", new_ec), Named("x_counts_obs", new_ec_obs));
delta(k)=icl(new_stats,oldcl,k)-icl(old_stats,oldcl,k);
}
}
//Rcout << delta << std::endl;
return delta;
}
void MissSbm::swap_update(const int i,const int newcl){
int self=x(i,i);
int selfobs=xobs(i,i);
int oldcl = cl(i);
arma::sp_mat col_sum = gsum_col(cl,x,i,K);
col_sum(oldcl)=col_sum(oldcl)-self;
arma::sp_mat col_sum_obs = gsum_col(cl,xobs,i,K);
col_sum_obs(oldcl)=col_sum_obs(oldcl)-selfobs;
arma::sp_mat row_sum = gsum_col(cl,xt,i,K);
row_sum(oldcl)=row_sum(oldcl)-self;
arma::sp_mat row_sum_obs = gsum_col(cl,xtobs,i,K);
row_sum_obs(oldcl)=row_sum_obs(oldcl)-selfobs;
arma::mat new_ec = x_counts;
new_ec.col(newcl) = new_ec.col(newcl)+col_sum;
new_ec.row(newcl) = new_ec.row(newcl)+row_sum.t();
new_ec.col(oldcl) = new_ec.col(oldcl)-col_sum;
new_ec.row(oldcl) = new_ec.row(oldcl)-row_sum.t();
new_ec(newcl,newcl)=new_ec(newcl,newcl)+self;
new_ec(oldcl,oldcl)=new_ec(oldcl,oldcl)-self;
arma::mat new_ec_obs = x_counts_obs;
new_ec_obs.col(newcl) = new_ec_obs.col(newcl)+col_sum_obs;
new_ec_obs.row(newcl) = new_ec_obs.row(newcl)+row_sum_obs.t();
new_ec_obs.col(oldcl) = new_ec_obs.col(oldcl)-col_sum_obs;
new_ec_obs.row(oldcl) = new_ec_obs.row(oldcl)-row_sum_obs.t();
new_ec_obs(newcl,newcl)=new_ec_obs(newcl,newcl)+selfobs;
new_ec_obs(oldcl,oldcl)=new_ec_obs(oldcl,oldcl)-selfobs;
arma::mat new_counts = update_count(counts,oldcl,newcl);
cl(i)=newcl;
if(new_counts(oldcl)==0){
counts = new_counts.elem(arma::find(arma::linspace(0,K-1,K)!=oldcl));
x_counts = new_ec(arma::find(arma::linspace(0,K-1,K)!=oldcl),arma::find(arma::linspace(0,K-1,K)!=oldcl));
x_counts_obs = new_ec_obs(arma::find(arma::linspace(0,K-1,K)!=oldcl),arma::find(arma::linspace(0,K-1,K)!=oldcl));
cl.elem(arma::find(cl>oldcl))=cl.elem(arma::find(cl>oldcl))-1;
--K;
}else{
counts=new_counts;
x_counts=new_ec;
x_counts_obs=new_ec_obs;
}
}
double MissSbm::delta_merge(int k, int l){
arma::mat new_ec = x_counts;
arma::mat new_ec_obs = x_counts_obs;
arma::mat new_counts = counts;
new_counts(l)=new_counts(k)+new_counts(l);
new_counts(k)=0;
new_ec.col(l) = new_ec.col(k)+new_ec.col(l);
new_ec.row(l) = new_ec.row(k)+new_ec.row(l);
new_ec_obs.col(l) = new_ec_obs.col(k)+new_ec_obs.col(l);
new_ec_obs.row(l) = new_ec_obs.row(k)+new_ec_obs.row(l);
List old_stats = List::create(Named("counts", counts), Named("x_counts", x_counts), Named("x_counts_obs", x_counts_obs));
List new_stats = List::create(Named("counts", new_counts), Named("x_counts", new_ec), Named("x_counts_obs", new_ec_obs));
double delta = icl(new_stats,k,l)-icl(old_stats,k,l);
return delta;
}
void MissSbm::merge_update(int k,int l){
cl(arma::find(cl==k))=arma::ones(counts(k),1)*l;
cl.elem(arma::find(cl>k))=cl.elem(arma::find(cl>k))-1;
counts(l) = counts(k)+counts(l);
counts = counts.elem(arma::find(arma::linspace(0,K-1,K)!=k));
x_counts.col(l) = x_counts.col(k)+x_counts.col(l);
x_counts.row(l) = x_counts.row(k)+x_counts.row(l);
x_counts = x_counts(arma::find(arma::linspace(0,K-1,K)!=k),arma::find(arma::linspace(0,K-1,K)!=k));
x_counts_obs.col(l) = x_counts_obs.col(k)+x_counts_obs.col(l);
x_counts_obs.row(l) = x_counts_obs.row(k)+x_counts_obs.row(l);
x_counts_obs = x_counts_obs(arma::find(arma::linspace(0,K-1,K)!=k),arma::find(arma::linspace(0,K-1,K)!=k));
--K;
}
double MissSbm::delta_merge_correction(int k,int l,int obk,int obl,const List & old_stats){
return 0;
}
| [
"etienne.come@gmail.com"
] | etienne.come@gmail.com |
17d67086e159ef0bf5b14516b32cbf2765cb67b7 | ab29d62c80b07af118b50c80d879595c3748a844 | /sipsl-code/src/SUDP.cpp | e996e2e77e8e73e87b163987993c9b8a6ebf5385 | [] | no_license | guincisa/SIPSL | 932217d176ebcc0f047666c855b6188c8577e03f | a9c0cc91cf2bb886cc5cbbd2f059be6a12b21ae4 | refs/heads/master | 2021-01-19T21:39:13.565489 | 2017-05-16T14:24:50 | 2017-05-16T14:24:50 | 88,679,621 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 18,748 | cpp | //**********************************************************************************
//**********************************************************************************
//**********************************************************************************
// SIPCSL Sip Core And Service Layer
// Copyright (C) 2011 Guglielmo Incisa di Camerana
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//**********************************************************************************
//**********************************************************************************
//**********************************************************************************
#include <algorithm>
#include <arpa/inet.h>
#include <assert.h>
#include <errno.h>
#include <iostream>
#include <map>
#include <memory>
#include <netdb.h>
#include <pthread.h>
#include <signal.h>
#include <sstream>
#include <stack>
#include <stdio.h>
#include <string>
#include <string.h>
#include <strings.h>
#include <sys/socket.h>
#include <sys/time.h>
#include <sys/types.h>
#include <time.h>
#include <unistd.h>
#include <vector>
#include <unordered_map>
#include "UTIL.h"
#ifndef CS_HEADERS_H
#include "CS_HEADERS.h"
#endif
#ifndef MESSAGE_H
#include "MESSAGE.h"
#endif
#ifndef SPIN_H
#include "SPIN.h"
#endif
#ifndef ENGINE_H
#include "ENGINE.h"
#endif
#ifndef SIPENGINE_H
#include "SIPENGINE.h"
#endif
#ifndef SL_CC_H
#include "SL_CC.h"
#endif
#ifndef ACTION_H
#include "ACTION.h"
#endif
#ifndef DOA_H
#include "DOA.h"
#endif
#ifndef SUDP_H
#include "SUDP.h"
#endif
#ifndef CALL_OSET_H
#include "CALL_OSET.h"
#endif
#ifndef COMAP_H
#include "COMAP.h"
#endif
#ifndef ALO_H
#include "ALO.h"
#endif
#ifndef VALO_H
#include "VALO.h"
#endif
#ifndef SIP_PROPERTIES_H
#include "SIP_PROPERTIES.h"
#endif
#ifndef ALARM_H
#include "ALARM.h"
#endif
#ifndef SIPUTIL_H
#include "SIPUTIL.h"
#endif
#ifndef TRNSPRT_H
#include "TRNSPRT.h"
#endif
#ifndef DAO_H
#include "DAO.h"
#endif
static SIPUTIL SipUtil;
// *****************************************************************************************
// Socket listener thread
// *****************************************************************************************
// *****************************************************************************************
extern "C" void* SUPDSTACK (void*);
void * SUDPSTACK(void *_tgtObject) {
DBSUDP_3("SUDPSTACK thread id",pthread_self())
DBSUDP_3("SUDPSTACK start","")
SUDPtuple *tgtObject = (SUDPtuple *)_tgtObject;
tgtObject->st->listen(tgtObject->thid);
DBSUDP_3("SUDPSTACK started","")
return (NULL);
}
// *****************************************************************************************
// Set DAO
// *****************************************************************************************
// *****************************************************************************************
void SUDP::setDAO(DAO* _dao) {
dao = _dao;
}
// *****************************************************************************************
// Return processing type
// *****************************************************************************************
// *****************************************************************************************
int SUDP::getProcessingType(void){
return processingType;
}
// *****************************************************************************************
// SUDP
// Initialize Stack
// *****************************************************************************************
// *****************************************************************************************
//void SUDP::init(int _port, ENGINE *_engine, DOA* _doa, string _domain, ALMGR* _alarm, bool singleThread){
void SUDP::init(int _port, TRNSPRT* _engine, string _domain, ALMGR* _alarm, bool singleThread){
DBSUDP_3("SUDP init",_domain)
domain = _domain;
echoServPort = _port;
transport = _engine;
cliAddrLen = sizeof(echoClntAddr);
alarm = _alarm;
//doa = _doa;
if ( singleThread ){
threadNum = 1;
}else {
threadNum = SUDPTH;
}
/* Create socket for sending datagrams */
for (int i = 0 ; i <threadNum ; i++){
if ((sock_se[i] = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) {
DEBASSERT("socket() failed)")
return;
}
}
/* Create socket for receiving datagrams */
if ((sock_re = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP)) < 0) {
DEBASSERT("socket() failed)")
return;
}
/* Construct local address structure */
memset(&echoServAddr, 0, sizeof(echoServAddr)); /* Zero out structure */
echoServAddr.sin_family = AF_INET; /* Internet address family */
echoServAddr.sin_addr.s_addr = htonl(INADDR_ANY); /* Any incoming interface */
echoServAddr.sin_port = htons(echoServPort); /* Local port */
//Init mutex
#ifdef USEMESSAGEMAP
for (int i = 0; i < MESSAGEMAPS;i++){
pthread_mutex_init(&messTableMtx[i],NULL);
}
#endif
#ifdef USEMAPMODUL
#ifndef MAPMODULHYBRID
pthread_mutex_init(&modulusMapMtx,NULL);
modulusIter = 0;
#else
for (int zi = 0 ; zi < PREMODMAP ; zi ++){
pthread_mutex_init(&(modulusMapMtx[zi]),NULL);
modulusIter[zi] = 0;
}
#endif
#endif
/* Bind to the local address */
// moved to start
// if (bind(sock_re, (struct sockaddr *) &echoServAddr, sizeof(echoServAddr)) < 0) {
// DEBERROR("bind() failed)");
// }
//DEFINE LOCAL ADDRESS for VIA
char hostname[1024];
char str[INET_ADDRSTRLEN];
hostname[1023]='\0';
gethostname(hostname,1023);
struct addrinfo _hints, *info;
memset(&_hints, 0, sizeof _hints);
_hints.ai_family = AF_UNSPEC; /*either IPV4 or IPV6*/
_hints.ai_socktype = SOCK_DGRAM;
char ss[GENSTRINGLEN];
sprintf(ss,"%d",echoServPort);
localport = ss;
if (getaddrinfo(hostname, ss, &_hints, &info) != 0) {
DEBASSERT("getaddrinfo")
}
inet_ntop(AF_INET, &((struct sockaddr_in *) info->ai_addr)->sin_addr, str, INET_ADDRSTRLEN);
localip = str;
DBSUDP("local ip address",localip<<"]["<<localport)
// END DEFINE LOCAL ADDRESS
#ifdef VODAFONEBB
localip = "sipsl.ddns.net";
#endif
//sipengine->linkSUDP(this);
DBSUDP_3("SUDP init done","")
return;
}
// *****************************************************************************************
// Start Stack
// *****************************************************************************************
// *****************************************************************************************
void SUDP::start(int _processingType) {
processingType = _processingType;
// allocate thread and starts
if (bind(sock_re, (struct sockaddr *) &echoServAddr, sizeof(echoServAddr)) < 0) {
DEBERROR("bind() failed)");
}
DBSUDP_3("SUDP::start threads",threadNum)
SUDPtuple *t1[threadNum*2];
for (int i = 0 ; i <(2*threadNum) ; i++){
NEWPTR2(listenerThread[i], ThreadWrapper,"ThreadWrapper"<<i)
NEWPTR2(t1[i], SUDPtuple,"SUDPtuple")
t1[i]->st = this;
t1[i]->thid = i;
pthread_create(&(listenerThread[i]->thread), NULL, SUDPSTACK, (void *) t1[i] );
}
return;
}
// *****************************************************************************************
// Listen to network
// *****************************************************************************************
void SUDP::listen(int _socknum) {
//processing type
// If router then I can receive
// [network] -> SUDP
// [C_PROC] -> SUDP
// we distinguish in transport
TIMEDEF
DBSUDP_3("SUDP::listen","listen " << _socknum)
char echoBuffer[ECHOMAX];
sockaddr_inX _echoClntAddr;
unsigned int _cliAddrLen;
for (;;){
/* Block until receive message from a client */
memset(&echoBuffer, 0x0, ECHOMAX);
int recvMsgSize;
int _sok;
if ( _socknum < threadNum ){
_sok = sock_se[_socknum];
}
else {
_sok = sock_re;
}
if ((recvMsgSize = recvfrom(_sok, echoBuffer, ECHOMAX, 0,
(struct sockaddr *) &_echoClntAddr, (socklen_t*)&_cliAddrLen)) < 0) {
DEBERROR("SUDP::listen() recvfrom() failed")
}else if ( recvMsgSize < 1){
DEBERROR("SUDP::listen() abnormal message")
}else {
SETNOW
PROFILE("SUDP:Message arrived from socket")
//Message handling
MESSAGE* message=0x0;
CREATENEWMESSAGE_EXT(message, echoBuffer, _sok, _echoClntAddr, SODE_NTWPOINT)
if (message != 0x0 ){
DBSUDP_3("New message from buffer ", message)
DBSUDP("SINPORT",echoClntAddr.sin_port)
DBSUDP("SINPORT",ntohs(echoClntAddr.sin_port))
//problem if not sip...?
message->fillIn();
DEBOUT("MODULUS DEBUG",message->getModulus())
//engine->p_w((void*)message);
transport->upCall(message);
PRINTDIFF("SUDP listen")
}else {
DEBERROR("SUDP::listen() could not allocate memory for incoming message")
}
CALCPERF("SUDP::listen() Message sent to SIPENGINE",1)
}
}
}
// *****************************************************************************************
// getters
// *****************************************************************************************
// *****************************************************************************************
string SUDP::getDomain(void) {
return domain;
}
int SUDP::getPort(void){
return echoServPort;
}
ALMGR* SUDP::getAlmgr(void){
return alarm;
}
//void SUDP::sendRequest(MESSAGE* _message){
// DEBINFSUDP("void SUDP::sendRequest(MESSAGE* _message)",_message)
//
// struct sockaddr_in si_part;
// struct hostent *host;
// memset((char *) &si_part, 0, sizeof(si_part));
//
// DEBMESSAGE("SUDP::sendRequest sending Message ", _message)
//
// pair<string,int> _pair = _message->getUri("REQUEST");
// const char* _hostchar = _pair.first.c_str();
// host = gethostbyname(_hostchar);
// if (host == NULL){
// DEBASSERT("host = gethostbyname(_hostchar); is null "<< _hostchar)
// }
//
// si_part.sin_family = AF_INET;
// si_part.sin_port = htons(_pair.second);
// //core qui
// si_part.sin_addr = *( struct in_addr*)( host -> h_addr_list[0]);
//
// int i = _message->getModulus() % threadNum;
//
// sendto(sock_se[i], _message->getMessageBuffer(), strlen(_message->getMessageBuffer()) , 0, (struct sockaddr *)&si_part, sizeof(si_part));
// if (!_message->getLock()){
// PURGEMESSAGE(_message)
// }
//
// return;
//}
void SUDP::sendRawMessage(string* message, string address, int port){
struct sockaddr_in si_part;
si_part.sin_family = AF_INET;
si_part.sin_port = port;
inet_aton(address.c_str(), &si_part.sin_addr);
//heart beat messages always sent to socket 0
sendto(sock_se[0], message->c_str(), message->length(), 0, (struct sockaddr *)&si_part, sizeof(si_part));
DEBY
}
void SUDP::sendRequest(MESSAGE* _message){
DBSUDP_3("void SUDP::sendRequest(MESSAGE* _message)",_message)
TIMEDEF
SETNOW
#ifdef IPNUMERIC
pair<string,string> _pair;
if(_message->hasRoute()){
_pair = _message->getRoute();
DBSUDP("hasroute",_pair.first<<"]["<<_pair.second)
}
else if (_message->natTraversal()){
_pair = _message->getNatAddress();
DBSUDP("hasNat",_pair.first<<"]["<<_pair.second)
}
else{
#ifdef VODAFONEBB
//get the called user id
DBSUDP("getHeadTo",_message->getHeadTo())
DBSUDP("getHeadToName",_message->getHeadToName())
//non arriva
//riprova 5060
_pair = brkin2string(dao->getData(TBL_REGISTER,_message->getHeadToName()), ":");
DBSUDP("Use REGISTER table",_pair.first<<"]["<<_pair.second)
#else
_pair = _message->getRequestUriProtocol();
DBSUDP("use request",_pair.first<<"]["<<_pair.second)
#endif
}
DBSUDP("sending to",_pair.first<<"]["<<_pair.second)
const char* _hostchar = _pair.first.c_str();
struct sockaddr_in si_part;
si_part.sin_family = AF_INET;
si_part.sin_port = htons(atoi(_pair.second.c_str()));
inet_aton(_hostchar, &si_part.sin_addr);
int i = _message->getModulus() % threadNum;
sendto(sock_se[i], _message->getMessageBuffer(),strlen(_message->getMessageBuffer()) , 0, (struct sockaddr *)&si_part, sizeof(si_part));
if (!_message->getLock()){
PURGEMESSAGE(_message)
}
PRINTDIFF("IPNUMERIC SUDP::sendRequest")
return;
#else
pair<string,string> _pair;
if(_message->hasRoute()){
_pair = _message->getRoute();
DEBOUT("hasroute",_pair.first<<"]["<<_pair.second)
}
else if (_message->natTraversal()){
_pair = _message->getNatAddress();
DEBOUT("hasNat",_pair.first<<"]["<<_pair.second)
}
else{
_pair = _message->getRequestUriProtocol();
DEBOUT("use request",_pair.first<<"]["<<_pair.second)
}
DEBOUT("sending to",_pair.first<<"]["<<_pair.second)
const char* _hostchar = _pair.first.c_str();
struct addrinfo hints,*servinfo;
memset(&hints, 0, sizeof hints);
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = SOCK_DGRAM;
hints.ai_flags = AI_NUMERICHOST;
int res = getaddrinfo(_hostchar,_pair.second.c_str(),&hints, &servinfo);
if (res != 0){
DEBASSERT("getaddrinfo")
}
int i = _message->getModulus() % threadNum;
//CHECK ERROR HERE
sendto(sock_se[i], _message->getMessageBuffer(), strlen(_message->getMessageBuffer()) , 0, servinfo->ai_addr, servinfo->ai_addrlen);
if (!_message->getLock()){
PURGEMESSAGE(_message)
}
freeaddrinfo(servinfo);
PRINTDIFF("NON IPNUMERIC SUDP::sendRequest")
return;
#endif
}
void SUDP::sendReply(MESSAGE* _message){
DBSUDP_3("void SUDP::sendReply(MESSAGE* _message)",_message)
TIMEDEF
SETNOW
#ifdef IPNUMERIC
string receivedProp = _message->getProperty("Via:","received");
const char* _hostchar;
char cstr[256];
string reportPro;
DBSUDP("receivedProp",receivedProp)
if (receivedProp.length() != 0){
reportPro = _message->getProperty("Via:","rport");
strcpy(cstr, receivedProp.c_str());
}else{
DBSUDP("_message->getViaUriHost()",_message->getViaUriHost())
strcpy(cstr, _message->getViaUriHost().c_str());
}
_hostchar = cstr;
DBSUDP("PORT",_message->getEchoClntAddr().sin_port)
DBSUDP("ReplyHost",_hostchar)
DBSUDP("reportPro",reportPro)
//DEBOUT("PORT",_message->getEchoClntAddr().sin_port);
DBSUDP("reply message", _message->getMessageBuffer())
struct sockaddr_in si_part;
si_part.sin_family = AF_INET;
si_part.sin_port = _message->getEchoClntAddr().sin_port;
inet_aton(_hostchar, &si_part.sin_addr);
sendto(sock_re, _message->getMessageBuffer(),strlen(_message->getMessageBuffer()) , 0, (struct sockaddr *)&si_part, sizeof(si_part));
if (!_message->getLock()){
PURGEMESSAGE(_message)
}
PRINTDIFF("IPNUMERIC SUDP::sendReply")
return;
#else
//Reply uses topmost Via header
DEBSUP_3("SUDP::sendReply sending Message ", _message)
struct addrinfo hints,*servinfo;
memset(&hints, 0, sizeof hints);
hints.ai_family = AF_UNSPEC;
hints.ai_socktype = SOCK_DGRAM;
hints.ai_flags = AI_NUMERICHOST;
// string receivedProp = _message->getProperty("Via:","received");
// if (receivedProp.length() != 0){
// string reportPro = _message->getProperty("Via:","rport");
// const char* _hostchar = receivedProp.c_str();
// int res = getaddrinfo(_hostchar,reportPro.c_str(),&hints, &servinfo);
// if (res != 0){
// DEBASSERT("getaddrinfo")
// }
//
// }else{
// const char* _hostchar = _message->getViaUriHost().c_str();
// int res = getaddrinfo(_hostchar,_message->getViaUriProtocol().c_str(),&hints, &servinfo);
// if (res != 0){
// DEBASSERT("getaddrinfo")
// }
// }
const char* _hostchar = inet_ntoa(_message->getEchoClntAddr().sin_addr);
char xx[GENSTRINGLEN];
sprintf(xx,"%d",ntohs((_message->getEchoClntAddr()).sin_port));
DEBSUP("sendReply to", _hostchar <<"]["<<xx)
int res = getaddrinfo(_hostchar,xx,&hints, &servinfo);
if (res != 0){
DEBASSERT("getaddrinfo")
}
//CHECK ERROR HERE
sendto(sock_re, _message->getMessageBuffer(), strlen(_message->getMessageBuffer()) , 0, servinfo->ai_addr, servinfo->ai_addrlen);
if (!_message->getLock()){
PURGEMESSAGE(_message)
}
freeaddrinfo(servinfo);
PRINTDIFF("NON IPNUMERIC SUDP::sendReply")
return;
#endif
}
string SUDP::getLocalIp(void){
return localip;
}
string SUDP::getLocalPort(void){
return localport;
}
int SUDP::getRealm(void){
return realm;
}
//void SUDP::sendReply(MESSAGE* _message){
// DEBINFSUDP("void SUDP::sendReply(MESSAGE* _message)",_message)
//
// //Reply uses topmost Via header
//
// struct sockaddr_in si_part;
// struct hostent *host;
// memset((char *) &si_part, 0, sizeof(si_part));
//
// DEBMESSAGE("SUDP::sendReply sending Message ", _message)
//
//
// const char* _hostchar = _message->getViaUriHost().c_str();
// host = gethostbyname(_hostchar);
// if (host == NULL){
// DEBASSERT("host = gethostbyname(_hostchar); is null "<< _hostchar)
// }
//
// si_part.sin_family = AF_INET;
// //core qui
// si_part.sin_addr = *( struct in_addr*)( host -> h_addr_list[0]);
// si_part.sin_port = htons(_message->getViaUriPort());
//
// sendto(sock_re, _message->getMessageBuffer(), strlen(_message->getMessageBuffer()) , 0, (struct sockaddr *)&si_part, sizeof(si_part));
// if (!_message->getLock()){
// PURGEMESSAGE(_message)
// }
// return;
//}
| [
"guic@8d13bd44-46d8-4671-819c-ea08f47c0839"
] | guic@8d13bd44-46d8-4671-819c-ea08f47c0839 |
38794200e1104faec9f2e7769fa39a05f2a2dd60 | 55d0224c99ce313246c6d7aada74458923d57822 | /test/set/make.cpp | 325695ddacc478864f0ecbc88f856cd064d2e255 | [
"BSL-1.0",
"LicenseRef-scancode-unknown-license-reference"
] | permissive | boostorg/hana | 94535aadaa43cb88f09dde9172a578b2b049dc95 | d3634a3e9ce49a2207bd7870407c05e74ce29ef5 | refs/heads/master | 2023-08-24T11:47:37.357757 | 2023-03-17T14:00:22 | 2023-03-17T14:00:22 | 19,887,998 | 1,480 | 245 | BSL-1.0 | 2023-08-08T05:39:22 | 2014-05-17T14:06:06 | C++ | UTF-8 | C++ | false | false | 961 | cpp | // Copyright Louis Dionne 2013-2022
// Distributed under the Boost Software License, Version 1.0.
// (See accompanying file LICENSE.md or copy at http://boost.org/LICENSE_1_0.txt)
#include <boost/hana/assert.hpp>
#include <boost/hana/equal.hpp>
#include <boost/hana/set.hpp>
#include <laws/base.hpp>
namespace hana = boost::hana;
using hana::test::ct_eq;
int main() {
BOOST_HANA_CONSTANT_CHECK(hana::equal(
hana::make<hana::set_tag>(),
hana::make_set()
));
BOOST_HANA_CONSTANT_CHECK(hana::equal(
hana::make<hana::set_tag>(ct_eq<0>{}),
hana::make_set(ct_eq<0>{})
));
BOOST_HANA_CONSTANT_CHECK(hana::equal(
hana::make<hana::set_tag>(ct_eq<0>{}, ct_eq<1>{}),
hana::make_set(ct_eq<0>{}, ct_eq<1>{})
));
BOOST_HANA_CONSTANT_CHECK(hana::equal(
hana::make<hana::set_tag>(ct_eq<0>{}, ct_eq<1>{}, ct_eq<2>{}),
hana::make_set(ct_eq<0>{}, ct_eq<1>{}, ct_eq<2>{})
));
}
| [
"ldionne.2@gmail.com"
] | ldionne.2@gmail.com |
425910765437854edbb5e6d406c2ed7f8642b505 | 60bfd14fe506b4e0e3472f996eddfe158418d751 | /shell/platform/windows/flutter_windows_view.h | 259d4cc2b896fe916b453053b8dea6116d759b5f | [
"BSD-3-Clause"
] | permissive | chinmaygarde/flutter_engine | 440e73918e9b74e23862eb20e497236b51a0b6f3 | 28a195ed2e1390ed6c89005371c79b309983cf71 | refs/heads/main | 2023-08-03T12:40:35.376829 | 2023-04-04T20:27:53 | 2023-04-04T20:27:53 | 39,225,162 | 3 | 3 | BSD-3-Clause | 2023-02-27T08:09:11 | 2015-07-16T23:24:34 | C++ | UTF-8 | C++ | false | false | 14,047 | h | // Copyright 2013 The Flutter Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef FLUTTER_SHELL_PLATFORM_WINDOWS_FLUTTER_WINDOWS_VIEW_H_
#define FLUTTER_SHELL_PLATFORM_WINDOWS_FLUTTER_WINDOWS_VIEW_H_
#include <memory>
#include <mutex>
#include <string>
#include <unordered_map>
#include <utility>
#include <vector>
#include "flutter/fml/macros.h"
#include "flutter/shell/platform/common/client_wrapper/include/flutter/plugin_registrar.h"
#include "flutter/shell/platform/common/geometry.h"
#include "flutter/shell/platform/embedder/embedder.h"
#include "flutter/shell/platform/windows/angle_surface_manager.h"
#include "flutter/shell/platform/windows/flutter_windows_engine.h"
#include "flutter/shell/platform/windows/public/flutter_windows.h"
#include "flutter/shell/platform/windows/text_input_plugin_delegate.h"
#include "flutter/shell/platform/windows/window_binding_handler.h"
#include "flutter/shell/platform/windows/window_binding_handler_delegate.h"
#include "flutter/shell/platform/windows/window_state.h"
namespace flutter {
// ID for the window frame buffer.
inline constexpr uint32_t kWindowFrameBufferID = 0;
// An OS-windowing neutral abstration for flutter
// view that works with win32 hwnds and Windows::UI::Composition visuals.
class FlutterWindowsView : public WindowBindingHandlerDelegate,
public TextInputPluginDelegate {
public:
// Creates a FlutterWindowsView with the given implementor of
// WindowBindingHandler.
//
// In order for object to render Flutter content the SetEngine method must be
// called with a valid FlutterWindowsEngine instance.
FlutterWindowsView(std::unique_ptr<WindowBindingHandler> window_binding);
virtual ~FlutterWindowsView();
// Configures the window instance with an instance of a running Flutter
// engine.
void SetEngine(std::unique_ptr<FlutterWindowsEngine> engine);
// Creates rendering surface for Flutter engine to draw into.
// Should be called before calling FlutterEngineRun using this view.
void CreateRenderSurface();
// Destroys current rendering surface if one has been allocated.
void DestroyRenderSurface();
// Return the currently configured WindowsRenderTarget.
WindowsRenderTarget* GetRenderTarget() const;
// Return the currently configured PlatformWindow.
PlatformWindow GetPlatformWindow() const;
// Returns the engine backing this view.
FlutterWindowsEngine* GetEngine();
// Tells the engine to generate a new frame
void ForceRedraw();
// Callbacks for clearing context, settings context and swapping buffers,
// these are typically called on an engine-controlled (non-platform) thread.
bool ClearContext();
bool MakeCurrent();
bool MakeResourceCurrent();
bool SwapBuffers();
// Callback for presenting a software bitmap.
bool PresentSoftwareBitmap(const void* allocation,
size_t row_bytes,
size_t height);
// Send initial bounds to embedder. Must occur after engine has initialized.
void SendInitialBounds();
// Send the initial accessibility features to the window
void SendInitialAccessibilityFeatures();
// Set the text of the alert, and create it if it does not yet exist.
void AnnounceAlert(const std::wstring& text);
// |WindowBindingHandlerDelegate|
void UpdateHighContrastEnabled(bool enabled) override;
// Returns the frame buffer id for the engine to render to.
uint32_t GetFrameBufferId(size_t width, size_t height);
// Sets the cursor that should be used when the mouse is over the Flutter
// content. See mouse_cursor.dart for the values and meanings of cursor_name.
void UpdateFlutterCursor(const std::string& cursor_name);
// Sets the cursor directly from a cursor handle.
void SetFlutterCursor(HCURSOR cursor);
// |WindowBindingHandlerDelegate|
void OnWindowSizeChanged(size_t width, size_t height) override;
// |WindowBindingHandlerDelegate|
void OnWindowRepaint() override;
// |WindowBindingHandlerDelegate|
void OnPointerMove(double x,
double y,
FlutterPointerDeviceKind device_kind,
int32_t device_id,
int modifiers_state) override;
// |WindowBindingHandlerDelegate|
void OnPointerDown(double x,
double y,
FlutterPointerDeviceKind device_kind,
int32_t device_id,
FlutterPointerMouseButtons button) override;
// |WindowBindingHandlerDelegate|
void OnPointerUp(double x,
double y,
FlutterPointerDeviceKind device_kind,
int32_t device_id,
FlutterPointerMouseButtons button) override;
// |WindowBindingHandlerDelegate|
void OnPointerLeave(double x,
double y,
FlutterPointerDeviceKind device_kind,
int32_t device_id = 0) override;
// |WindowBindingHandlerDelegate|
virtual void OnPointerPanZoomStart(int32_t device_id) override;
// |WindowBindingHandlerDelegate|
virtual void OnPointerPanZoomUpdate(int32_t device_id,
double pan_x,
double pan_y,
double scale,
double rotation) override;
// |WindowBindingHandlerDelegate|
virtual void OnPointerPanZoomEnd(int32_t device_id) override;
// |WindowBindingHandlerDelegate|
void OnText(const std::u16string&) override;
// |WindowBindingHandlerDelegate|
void OnKey(int key,
int scancode,
int action,
char32_t character,
bool extended,
bool was_down,
KeyEventCallback callback) override;
// |WindowBindingHandlerDelegate|
void OnComposeBegin() override;
// |WindowBindingHandlerDelegate|
void OnComposeCommit() override;
// |WindowBindingHandlerDelegate|
void OnComposeEnd() override;
// |WindowBindingHandlerDelegate|
void OnComposeChange(const std::u16string& text, int cursor_pos) override;
// |WindowBindingHandlerDelegate|
void OnScroll(double x,
double y,
double delta_x,
double delta_y,
int scroll_offset_multiplier,
FlutterPointerDeviceKind device_kind,
int32_t device_id) override;
// |WindowBindingHandlerDelegate|
void OnScrollInertiaCancel(int32_t device_id) override;
// |WindowBindingHandlerDelegate|
virtual void OnUpdateSemanticsEnabled(bool enabled) override;
// |WindowBindingHandlerDelegate|
virtual gfx::NativeViewAccessible GetNativeViewAccessible() override;
// |TextInputPluginDelegate|
void OnCursorRectUpdated(const Rect& rect) override;
// |TextInputPluginDelegate|
void OnResetImeComposing() override;
// Get a pointer to the alert node for this view.
ui::AXPlatformNodeWin* AlertNode() const;
// |WindowBindingHandlerDelegate|
virtual ui::AXFragmentRootDelegateWin* GetAxFragmentRootDelegate() override;
protected:
virtual void NotifyWinEventWrapper(ui::AXPlatformNodeWin* node,
ax::mojom::Event event);
private:
// Struct holding the state of an individual pointer. The engine doesn't keep
// track of which buttons have been pressed, so it's the embedding's
// responsibility.
struct PointerState {
// The device kind.
FlutterPointerDeviceKind device_kind = kFlutterPointerDeviceKindMouse;
// A virtual pointer ID that is unique across all device kinds.
int32_t pointer_id = 0;
// True if the last event sent to Flutter had at least one button pressed.
bool flutter_state_is_down = false;
// True if kAdd has been sent to Flutter. Used to determine whether
// to send a kAdd event before sending an incoming pointer event, since
// Flutter expects pointers to be added before events are sent for them.
bool flutter_state_is_added = false;
// The currently pressed buttons, as represented in FlutterPointerEvent.
uint64_t buttons = 0;
// The x position where the last pan/zoom started.
double pan_zoom_start_x = 0;
// The y position where the last pan/zoom started.
double pan_zoom_start_y = 0;
};
// States a resize event can be in.
enum class ResizeState {
// When a resize event has started but is in progress.
kResizeStarted,
// After a resize event starts and the framework has been notified to
// generate a frame for the right size.
kFrameGenerated,
// Default state for when no resize is in progress. Also used to indicate
// that during a resize event, a frame with the right size has been rendered
// and the buffers have been swapped.
kDone,
};
// Sends a window metrics update to the Flutter engine using current window
// dimensions in physical
void SendWindowMetrics(size_t width, size_t height, double dpiscale) const;
// Reports a mouse movement to Flutter engine.
void SendPointerMove(double x, double y, PointerState* state);
// Reports mouse press to Flutter engine.
void SendPointerDown(double x, double y, PointerState* state);
// Reports mouse release to Flutter engine.
void SendPointerUp(double x, double y, PointerState* state);
// Reports mouse left the window client area.
//
// Win32 api doesn't have "mouse enter" event. Therefore, there is no
// SendPointerEnter method. A mouse enter event is tracked then the "move"
// event is called.
void SendPointerLeave(double x, double y, PointerState* state);
void SendPointerPanZoomStart(int32_t device_id, double x, double y);
void SendPointerPanZoomUpdate(int32_t device_id,
double pan_x,
double pan_y,
double scale,
double rotation);
void SendPointerPanZoomEnd(int32_t device_id);
// Reports a keyboard character to Flutter engine.
void SendText(const std::u16string&);
// Reports a raw keyboard message to Flutter engine.
void SendKey(int key,
int scancode,
int action,
char32_t character,
bool extended,
bool was_down,
KeyEventCallback callback);
// Reports an IME compose begin event.
//
// Triggered when the user begins editing composing text using a multi-step
// input method such as in CJK text input.
void SendComposeBegin();
// Reports an IME compose commit event.
//
// Triggered when the user commits the current composing text while using a
// multi-step input method such as in CJK text input. Composing continues with
// the next keypress.
void SendComposeCommit();
// Reports an IME compose end event.
//
// Triggered when the user commits the composing text while using a multi-step
// input method such as in CJK text input.
void SendComposeEnd();
// Reports an IME composing region change event.
//
// Triggered when the user edits the composing text while using a multi-step
// input method such as in CJK text input.
void SendComposeChange(const std::u16string& text, int cursor_pos);
// Reports scroll wheel events to Flutter engine.
void SendScroll(double x,
double y,
double delta_x,
double delta_y,
int scroll_offset_multiplier,
FlutterPointerDeviceKind device_kind,
int32_t device_id);
// Reports scroll inertia cancel events to Flutter engine.
void SendScrollInertiaCancel(int32_t device_id, double x, double y);
// Creates a PointerState object unless it already exists.
PointerState* GetOrCreatePointerState(FlutterPointerDeviceKind device_kind,
int32_t device_id);
// Sets |event_data|'s phase to either kMove or kHover depending on the
// current primary mouse button state.
void SetEventPhaseFromCursorButtonState(FlutterPointerEvent* event_data,
const PointerState* state) const;
// Sends a pointer event to the Flutter engine based on given data. Since
// all input messages are passed in physical pixel values, no translation is
// needed before passing on to engine.
void SendPointerEventWithData(const FlutterPointerEvent& event_data,
PointerState* state);
// Currently configured WindowsRenderTarget for this view used by
// surface_manager for creation of render surfaces and bound to the physical
// os window.
std::unique_ptr<WindowsRenderTarget> render_target_;
// The engine associated with this view.
std::unique_ptr<FlutterWindowsEngine> engine_;
// Keeps track of pointer states in relation to the window.
std::unordered_map<int32_t, std::unique_ptr<PointerState>> pointer_states_;
// Currently configured WindowBindingHandler for view.
std::unique_ptr<WindowBindingHandler> binding_handler_;
// Resize events are synchronized using this mutex and the corresponding
// condition variable.
std::mutex resize_mutex_;
std::condition_variable resize_cv_;
// Indicates the state of a window resize event. Platform thread will be
// blocked while this is not done. Guarded by resize_mutex_.
ResizeState resize_status_ = ResizeState::kDone;
// Target for the window width. Valid when resize_pending_ is set. Guarded by
// resize_mutex_.
size_t resize_target_width_ = 0;
// Target for the window width. Valid when resize_pending_ is set. Guarded by
// resize_mutex_.
size_t resize_target_height_ = 0;
// True when flutter's semantics tree is enabled.
bool semantics_enabled_ = false;
FML_DISALLOW_COPY_AND_ASSIGN(FlutterWindowsView);
};
} // namespace flutter
#endif // FLUTTER_SHELL_PLATFORM_WINDOWS_FLUTTER_WINDOWS_VIEW_H_
| [
"noreply@github.com"
] | chinmaygarde.noreply@github.com |
1e80312592b1555e2abea784723cc7ef8e2eaafe | 2bc835b044f306fca1affd1c61b8650b06751756 | /winhttp/v5.1/inc/proxreg.h | 77b361183537151a61fa3d0310ceec065698c4bf | [] | no_license | KernelPanic-OpenSource/Win2K3_NT_inetcore | bbb2354d95a51a75ce2dfd67b18cfb6b21c94939 | 75f614d008bfce1ea71e4a727205f46b0de8e1c3 | refs/heads/master | 2023-04-04T02:55:25.139618 | 2021-04-14T05:25:01 | 2021-04-14T05:25:01 | 357,780,123 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 4,767 | h | #include <inetreg.h>
#define BLOB_BUFF_GRANULARITY 1024
class CRegBlob
{
private:
HKEY _hkey;
BOOL _fWrite;
BOOL _fCommit;
DWORD _dwOffset;
DWORD _dwBufferLimit;
BYTE * _pBuffer;
LPCSTR _pszValue;
public:
CRegBlob(BOOL fWrite);
~CRegBlob();
DWORD Init(HKEY hBaseKey, LPCSTR pszSubKey, LPCSTR pszValue);
DWORD Abandon();
DWORD Commit();
DWORD WriteString(LPCSTR pszString);
DWORD ReadString(LPCSTR * ppszString);
DWORD WriteBytes(LPCVOID pBytes, DWORD dwByteCount);
DWORD ReadBytes(LPVOID pBytes, DWORD dwByteCount);
};
typedef struct {
//
// dwStructSize - Structure size to handle growing list of new entries or priv/pub structures
//
DWORD dwStructSize;
//
// dwFlags - Proxy type flags
//
DWORD dwFlags;
//
// dwCurrentSettingsVersion - a counter incremented every time we change our settings
//
DWORD dwCurrentSettingsVersion;
//
// lpszConnectionName - name of the Connectoid for this connection
//
LPCSTR lpszConnectionName;
//
// lpszProxy - proxy server list
//
LPCSTR lpszProxy;
//
// lpszProxyBypass - proxy bypass list
//
LPCSTR lpszProxyBypass;
} INTERNET_PROXY_INFO_EX, * LPINTERNET_PROXY_INFO_EX;
#define INTERNET_PROXY_INFO_VERSION 24 // sizeof 32-bit INTERNET_PROXY_INFO_EX
struct WINHTTP_AUTOPROXY_RESULTS
{
//
// dwFlags - Proxy type flags
//
DWORD dwFlags;
//
// dwCurrentSettingsVersion - a counter incremented every time we change our settings
//
DWORD dwCurrentSettingsVersion;
//
// lpszProxy - proxy server list
//
LPCSTR lpszProxy;
//
// lpszProxyBypass - proxy bypass list
//
LPCSTR lpszProxyBypass;
//
// lpszAutoconfigUrl - autoconfig URL set by app
//
LPCSTR lpszAutoconfigUrl;
//
// lpszAutoconfigUrlFromAutodect - autoconfig URL from autodiscovery
//
LPCSTR lpszAutoconfigUrlFromAutodetect;
//
// dwAutoDiscoveryFlags - auto detect flags.
//
DWORD dwAutoDiscoveryFlags;
//
// lpszLastKnownGoodAutoConfigUrl - Last Successful Url
//
LPCSTR lpszLastKnownGoodAutoConfigUrl;
//
// dwAutoconfigReloadDelayMins - number of mins until automatic
// refresh of auto-config Url, 0 == disabled.
//
DWORD dwAutoconfigReloadDelayMins;
//
// ftLastKnownDetectTime - When the last known good Url was found with detection.
//
FILETIME ftLastKnownDetectTime;
//
// dwDetectedInterfaceIpCount - Number of IPs detected in last detection
//
DWORD dwDetectedInterfaceIpCount;
//
// dwDetectedInterfaceIp - Array of DWORD of IPs detected in last detection
//
DWORD *pdwDetectedInterfaceIp;
};
DWORD
LoadProxySettings();
DWORD
WriteProxySettings(
INTERNET_PROXY_INFO_EX * pInfo
);
DWORD
ReadProxySettings(
LPINTERNET_PROXY_INFO_EX pInfo
);
void
CleanProxyStruct(
LPINTERNET_PROXY_INFO_EX pInfo
);
BOOL
IsConnectionMatch(
LPCSTR lpszConnection1,
LPCSTR lpszConnection2
);
HKEY
FindBaseProxyKey(
VOID
);
typedef struct {
// dwStructSize - Version stamp / Structure size
DWORD dwStructSize;
// dwFlags - Proxy type flags
DWORD dwFlags;
// dwCurrentSettingsVersion -
DWORD dwCurrentSettingsVersion;
// lpszConnectionName - name of the Connectoid for this connection
LPCSTR lpszConnectionName;
// lpszProxy - proxy server list
LPCSTR lpszProxy;
// lpszProxyBypass - proxy bypass list
LPCSTR lpszProxyBypass;
// lpszAutoconfigUrl - autoconfig URL
LPCSTR lpszAutoconfigUrl;
LPCSTR lpszAutoconfigSecondaryUrl;
// dwAutoDiscoveryFlags - auto detect flags.
DWORD dwAutoDiscoveryFlags;
// lpszLastKnownGoodAutoConfigUrl - Last Successful Url
LPCSTR lpszLastKnownGoodAutoConfigUrl;
// dwAutoconfigReloadDelayMins
DWORD dwAutoconfigReloadDelayMins;
// ftLastKnownDetectTime - When the last known good Url was found with detection.
FILETIME ftLastKnownDetectTime;
// dwDetectedInterfaceIpCount - Number of IPs detected in last detection
DWORD dwDetectedInterfaceIpCount;
// dwDetectedInterfaceIp - Array of DWORD of IPs detected in last detection
DWORD *pdwDetectedInterfaceIp;
} WININET_PROXY_INFO_EX, * LPWININET_PROXY_INFO_EX;
// version stamp of INTERNET_PROXY_INFO_EX
#define WININET_PROXY_INFO_EX_VERSION 60 // 60 := IE 5.x & 6.0 format
DWORD ReadWinInetProxySettings(LPWININET_PROXY_INFO_EX pInfo);
void CleanWinInetProxyStruct(LPWININET_PROXY_INFO_EX pInfo);
| [
"polarisdp@gmail.com"
] | polarisdp@gmail.com |
715ba4ab89a2c60c6aa50b2b3cd0d875245256da | 4a3134ced92b1e6f6440ac67b69449302bf32f5c | /DSA/sortingAlgorithms/selectionSort/selectionSort.cpp | 397bda1aa724bec68648f51945633014fab31260 | [] | no_license | Arihant416/Dsa-cp | 4454f2d1f6b16e94d33bd1d8760fe0ac27354715 | cdfea5ccb8040fc22588a7a7e22616f1d1d411f6 | refs/heads/master | 2023-03-23T16:23:33.692728 | 2021-03-07T05:52:49 | 2021-03-07T05:52:49 | 326,686,346 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,282 | cpp | /*
Author : Arihant Jain
github:https://github.com/Arihant416
linkedin : https://www.linkedin.com/in/arihant416
*/
#include <bits/stdc++.h>
using namespace std;
#define ll long long int
#define ull unsigned ll
#define PB push_back
#define MP make_pair
#define flash ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr)
#define vi vector<int>
#define vl vector<ll>
#define vll vector<ull>
#define mpi map<int, int>
#define mpl map<ll, ll>
#define mpll map<ull, ull>
#define pi pair<int, int>
#define pl pair<ll, ll>
#define all(a) begin(a), end(a)
#define maxEl(a) *max_element(all(a))
#define minEl(a) *min_element(all(a))
#define uimap unordered_map<int, int>
#define ulmap unordered_map<ll, ll>
#define mppii map<pi, int>
void selectionSort(vi &A, int N)
{
for (int i = 0; i < N - 1; i++)
{
int minIndex = i;
for (int j = i + 1; j < N; j++)
{
if (A[j] < A[minIndex])
{
minIndex = j;
}
}
swap(A[minIndex], A[i]);
}
}
void print(vi &A)
{
for (auto &i : A)
{
cout << i << " ";
}
}
int32_t main()
{
flash;
int N;
cin >> N;
vi A(N);
for (auto &i : A)
cin >> i;
selectionSort(A, N);
print(A);
return 0;
} | [
"arihantjain416@gmail.com"
] | arihantjain416@gmail.com |
dff272d63ad0d7be71abf32dd79210101c09b6a0 | 80816eb7fd304d652eab656d004a59246eda260d | /cpp-holy/forWhileEx.h | 0b51e470cb24381ee6d445a113c9db61456b5a2d | [] | no_license | holy1017-cpp/cpp-holy | b264ac39787ed0759a84030607f4bcb031670197 | 223a69b5c52b8d1b7a3def04d677eda872587848 | refs/heads/master | 2022-12-10T16:34:06.161294 | 2020-09-19T08:30:55 | 2020-09-19T08:30:55 | 290,492,713 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 254 | h | #pragma once
#ifndef forWhile_H
#define forWhile_H
#include <iostream>
using namespace std;
namespace forWhile {
void testFor();
void testForRang();
void testForRang2();
void testWhile();
void testTrim();
char* trim(char* szSource);
}
#endif | [
"holy1017@naver.com"
] | holy1017@naver.com |
20981aa539a54e3a501abd302d08033af8866740 | 2e48a571d4b0f1a127d3cb2ed8c67ddac4a01c86 | /model/lora-sink-application.h | 936a524cfd481c30c23918732cfcacce45f11997 | [] | no_license | ConstantJoe/ku-leuven-lorawan-with-energy-model | 53bc7b8ee8f667e570444c0f040c43086ee8d326 | 9fbf4856230b460c0bd6be5de919f62a16b7260c | refs/heads/master | 2020-03-28T15:57:48.639058 | 2018-09-13T14:04:29 | 2018-09-13T14:04:29 | 148,643,859 | 1 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 3,749 | h | /* -*- Mode:C++; c-file-style:"gnu"; indent-tabs-mode:nil; -*- */
/*
* Copyright (c) 2018 KU Leuven
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Author: Brecht Reynders <brecht.reynders@esat.kuleuven.be>
*/
#ifndef LORA_SINK_APPLICATION_H
#define LORA_SINK_APPLICATION_H
#include "ns3/event-id.h"
#include "ns3/nstime.h"
#include "ns3/object.h"
#include "ns3/ptr.h"
#include "ns3/node.h"
#include "ns3/callback.h"
#include "ns3/application.h"
namespace ns3 {
class Node;
class Packet;
class Socket;
/**
* \ingroup lora
* \brief The application running on LoRa gateways
*
* This application is running on each LoRa Gateway. The fuctionality is really trivial: it forwards all incoming messages to the network application and forwards all messages from the network server to the nodes.
*/
class LoRaSinkApplication : public Application
{
public:
/**
* \brief Get the type ID.
* \return the object TypeId
*/
static TypeId GetTypeId (void);
/**
* Default constructor
*/
LoRaSinkApplication ();
/**
* Default destructor
*/
virtual ~LoRaSinkApplication ();
/**
* HandleRead is the function that gets executed every time there is a message from the network server.
* This function reads all incoming messages and checks if it needs to transmit these on its network.
* Forwarding functionality is enabled or disabled with the ACK flag and a downlink message. If this flag is not set, the message is NOT transmitted
*
* \param socket The socket that received the messages
*/
void HandleRead (Ptr<Socket> socket);
/**
* HandleLoRa is the function that gets executed every time there is a new LoRa message received.
* All messages are forwarded to the network server and a downlink slot is scheduled for the case messages need to be transmitted on the network
*
* \param socket The socket that is listening on the LoRa Network.
*/
void HandleLoRa (Ptr<Socket> socket);
/**
* SetNetDevice stores the netdevice that is responsible for the LoRa Network.
*
* \param device Netdevice that is listening to the LoRa Network.
*/
void SetNetDevice (Ptr<NetDevice> device);
private:
/**
* \brief Application specific startup code
*
* The StartApplication method is called at the start time specified by Start
* This method should be overridden by all or most application
* subclasses.
*/
void StartApplication (void);
/**
* \brief Application specific shutdown code
*
* The StopApplication method is called at the stop time specified by Stop
* This method should be overridden by all or most application
* subclasses.
*/
void StopApplication (void);
Ptr<Socket> m_socket; //!< socket for connecting with the LoRa network server
Ptr<Socket> m_loraSocket; //!< socket for connecting with the LoRa network
Address m_serverAddress; //!< address of the LoRa network server
uint16_t m_port; //!< port of the LoRa Network server
Ptr<NetDevice> m_device; //!< netdevice connected to the LoRa Network
protected:
virtual void DoDispose (void);
virtual void DoInitialize (void);
};
} // namespace ns3
#endif /* APPLICATION_H */
| [
"brecht.reynders@esat.kuleuven.be"
] | brecht.reynders@esat.kuleuven.be |
6ba4128df1788698e80eab60cf45d3d10663cd75 | eda1764f63ceba09f5bf90e5e4db7087f6d99cdb | /DlmsReader.h | 78ab3081ba2b03265e36f9601dc5d89d27f99e8a | [] | no_license | charuga/HANToMQTT | 8a027250199c2453818264112a995d7fb4b97926 | 7ba81efe25e39622b6c582fb5bc63fec9e211ce0 | refs/heads/master | 2020-05-04T13:01:39.059835 | 2019-04-01T21:06:49 | 2019-04-01T21:06:49 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,296 | h | #ifndef _DLMSREADER_h
#define _DLMSREADER_h
#include "Crc16.h"
#if defined(ARDUINO) && ARDUINO >= 100
#include "arduino.h"
#else
#include "WProgram.h"
#endif
typedef void(*LOG_FN)(const char *fmt, ...);
#define DLMS_READER_BUFFER_SIZE 512
#define DLMS_READER_MAX_ADDRESS_SIZE 5
enum HDLCState { kHDLCState_Waiting, kHDLCState_Data, kHDLCState_Escaped};
class DlmsReader
{
public:
uint8_t debugLevel;
Stream *debug;
LOG_FN netLog;
DlmsReader();
bool Read(byte data);
bool ReadOld(byte data);
bool GetUserDataBuffer(byte *&dataBuffer, int& length);
//int GetRawData(byte *buffer, int start, int length);
protected:
Crc16Class Crc16;
private:
byte buffer[DLMS_READER_BUFFER_SIZE];
int position;
int dataLength;
HDLCState state;
byte frameFormatType;
byte destinationAddress[DLMS_READER_MAX_ADDRESS_SIZE];
byte destinationAddressLength;
byte sourceAddress[DLMS_READER_MAX_ADDRESS_SIZE];
byte sourceAddressLength;
void Clear();
int GetAddress(int addressPosition, byte* buffer, int start, int length);
unsigned short GetChecksum(int checksumPosition);
bool IsValidFrameFormat(byte frameFormatType);
void WriteBuffer();
void debugPrint(byte *buffer, int start, int length);
};
#endif
| [
"aleksander@toppe.no"
] | aleksander@toppe.no |
bba3ba1b51d37630347d95f2a939f1810241961f | 98db230948b3a2f10724b72529ba1475c3d40459 | /src/Config.cpp | b1e9e899a2cf0c10fe48a92d984cb72e70929768 | [] | no_license | tyl12/ipc | 158507bd90e6446b9d74d52b0255a56c9ba0d154 | 7f64e003cd7c1be11bbd1f4eaa4e3703f6ead5d8 | refs/heads/master | 2021-09-07T16:35:19.114314 | 2018-02-26T03:56:44 | 2018-02-26T03:56:44 | 114,473,086 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 8,144 | cpp |
#include <string.h>
#include <unistd.h>
#include <stdio.h>
#include <iostream>
#include "GetStream.h"
#include "public.h"
#include "ConfigParams.h"
#include "Alarm.h"
#include "CapPicture.h"
#include "playback.h"
#include "Voice.h"
#include "tool.h"
#include "Config.h"
using namespace std;
/** @fn void CALLBACK ExceptionCallBack(DWORD dwType, LONG lUserID, LONG lHandle, void *pUser)
* @brief Process exception.
* @param (IN) DWORD dwType
* @param (IN) LONG lUserID
* @param (IN) LONG lHandle
* @param (IN) void *pUser
* @return none.
*/
#if defined(_WIN32)
static void CALLBACK ExceptionCallBack(DWORD dwType, LONG lUserID, LONG lHandle, void *pUser)
#else
static void CALLBACK g_ExceptionCallBack(DWORD dwType, LONG lUserID, LONG lHandle, void *pUser)
#endif
{
printf("ExceptionCallBack lUserID:%d, handle:%d, user data:%p", lUserID, lHandle, pUser);
char tempbuf[256];
memset(tempbuf, 0, 256);
switch(dwType)
{
case EXCEPTION_AUDIOEXCHANGE: //Audio exchange exception
cout<<"Audio exchange exception!"<<endl;
//TODO: close audio exchange
break;
//Alarm//
case EXCEPTION_ALARM: //Alarm exception
cout<<"Alarm exception!"<<endl;
//TODO: close alarm update
break;
case EXCEPTION_ALARMRECONNECT: //Alarm reconnect
cout<<"Alarm reconnect."<<endl;
break;
case ALARM_RECONNECTSUCCESS: //Alarm reconnect success
cout<<"Alarm reconnect success."<<endl;
break;
case EXCEPTION_SERIAL: //Serial exception
cout<<"Serial exception!"<<endl;
//TODO: close exception
break;
//Preview//
case EXCEPTION_PREVIEW: //Preview exception
cout<<"Preview exception!"<<endl;
//TODO: close preview
break;
case EXCEPTION_RECONNECT: //preview reconnect
cout<<"preview reconnecting."<<endl;
break;
case PREVIEW_RECONNECTSUCCESS: //Preview reconnect success
cout<<"Preview reconncet success."<<endl;
break;
default:
break;
}
}
static void setSubStreamConfig(NET_DVR_COMPRESSION_INFO_V30& highPara){
highPara.byStreamType=0;
highPara.byResolution=6;//19 for 720p, 16 for vga, 6 for qvga
highPara.byBitrateType=1;//0 for variable rate, 1 for fix
highPara.byPicQuality=3;//0 for best, 5 for worst, 0xfe for auto
highPara.dwVideoBitrate=4;//25 for 4096k
highPara.dwVideoFrameRate=0;//0 for all, 1 for 1/60, 10 for 10, 14 for 15, 18 for 30
highPara.wIntervalFrameI=50;
highPara.byVideoEncType=10;//1 for std h264, 0 for pri h264, 10 for h265
highPara.byVideoEncComplexity=1; //0 for low, 1 for middle, 2 for high
highPara.byEnableSvc=0;//0 for disable, 1 for enable, 2 for auto
highPara.bySmartCodec=0;//0 for disable, 1 for enable
highPara.byStreamSmooth=50;//1~100, 1 for clear, 100 for smooth
}
static void setMainStreamConfig(NET_DVR_COMPRESSION_INFO_V30& highPara){
highPara.byStreamType=0;
highPara.byResolution=19;//19 for 720p, 16 for vga, 6 for qvga
highPara.byBitrateType=0;//0 for variable rate, 1 for fix
highPara.byPicQuality=3;//0 for best, 5 for worst, 0xfe for auto
highPara.dwVideoBitrate=25;//25 for 4096k, 4 for 64k
highPara.dwVideoFrameRate=10;//0 for all, 1 for 1/60, 10 for 10, 14 for 15, 18 for 30
highPara.wIntervalFrameI=20;
highPara.byVideoEncType=1;//1 for std h264, 0 for pri h264, 10 for h265
highPara.byVideoEncComplexity=1; //0 for low, 1 for middle, 2 for high
highPara.byEnableSvc=0;//0 for disable, 1 for enable, 2 for auto
highPara.bySmartCodec=0;//0 for disable, 1 for enable
highPara.byStreamSmooth=50;//1~100, 1 for clear, 100 for smooth
//keep other default
//highPara.byIntervalBPFrame=;
//highPara.byAudioEncType=;
//highPara.byFormatType=;
//highPara.byAudioBitRate=2;//0 for def, 1 for 8k, 2 for 16k, 4 for 64k
//highPara.byAudioSamplingRate=;
//highPara.byres=;
//highPara.wAverageVideoBitrate=;
}
static void showStreamConfig(const NET_DVR_COMPRESSION_INFO_V30& highPara){
cout<< "*********major config**********" <<endl;
cout<< "byStreamType= " <<"\t" << int(highPara.byStreamType) <<endl;
cout<< "byResolution= " <<"\t" << int(highPara.byResolution) <<endl;
cout<< "byBitrateType= " <<"\t" << int(highPara.byBitrateType) <<endl;
cout<< "byPicQuality= " <<"\t" << int(highPara.byPicQuality) <<endl;
cout<< "dwVideoBitrate= " <<"\t" << int(highPara.dwVideoBitrate) <<endl;
cout<< "dwVideoFrameRate= " <<"\t" << int(highPara.dwVideoFrameRate) <<endl;
cout<< "wIntervalFrameI= " <<"\t" << int(highPara.wIntervalFrameI) <<endl;
cout<< "byVideoEncType= " <<"\t" << int(highPara.byVideoEncType) <<endl;
cout<< "byVideoEncComplexity= " <<"\t" << int(highPara.byVideoEncComplexity) <<endl;
cout<< "byEnableSvc= " <<"\t" << int(highPara.byEnableSvc) <<endl;
cout<< "bySmartCodec= " <<"\t" << int(highPara.bySmartCodec) <<endl;
cout<< "*********minor config**********" <<endl;
cout<< "byIntervalBPFrame= " <<"\t" << int(highPara.byIntervalBPFrame) <<endl;
cout<< "byAudioEncType= " <<"\t" << int(highPara.byAudioEncType) <<endl;
cout<< "byFormatType= " <<"\t" << int(highPara.byFormatType) <<endl;
cout<< "byStreamSmooth= " <<"\t" << int(highPara.byStreamSmooth) <<endl;
cout<< "byAudioBitRate= " <<"\t" << int(highPara.byAudioBitRate) <<endl;
cout<< "byAudioSamplingRate= " <<"\t" << int(highPara.byAudioSamplingRate) <<endl;
cout<< "byres= " <<"\t" << int(highPara.byres) <<endl;
cout<< "wAverageVideoBitrate= " <<"\t" << int(highPara.wAverageVideoBitrate) <<endl;
}
Config::Config(){
cout<<"Config ctor"<<endl;
}
Config::~Config(){
cout<<"~Config"<<endl;
NET_DVR_Cleanup();
}
int Config::updateConfig(string ip, int port, string user, string passwd)
{
LONG lUserID = 0;
cout<<__LINE__<<endl;
NET_DVR_DEVICEINFO_V30 struDeviceInfo = {0};
cout<<__LINE__<<endl;
usleep(1000*1000*3);
cout<<__LINE__<<endl;
//lUserID = NET_DVR_Login_V30("192.168.1.104", 8000, "admin", "Aim@12345", &struDeviceInfo);
lUserID = NET_DVR_Login_V30((char*)ip.c_str(), port, (char*)user.c_str(), (char*)passwd.c_str(), &struDeviceInfo);
if (lUserID < 0)
{
printf("Login error, %d\n", NET_DVR_GetLastError());
NET_DVR_Cleanup();
return -1;
}
//---------------------------------------
NET_DVR_SetExceptionCallBack_V30(0, NULL, g_ExceptionCallBack, NULL);
//---------------------------------------
LONG lRealPlayHandle;
NET_DVR_PREVIEWINFO struPlayInfo = { 0 };
struPlayInfo.lChannel = 1; //Ô¤ÀÀͨµÀºÅ
//struPlayInfo.hPlayWnd = h; //ÐèÒªSDK½âÂëʱ¾ä±úÉèΪÓÐЧֵ£¬½öÈ¡Á÷²»½âÂëʱ¿ÉÉèΪ¿Õ
//struPlayInfo.dwStreamType = 1; //0-Ö÷ÂëÁ÷£¬1-×ÓÂëÁ÷£¬2-ÂëÁ÷3£¬3-ÂëÁ÷4£¬ÒÔ´ËÀàÍÆ
//struPlayInfo.dwLinkMode = 0; //0- TCP·½Ê½£¬1- UDP·½Ê½£¬2- ¶à²¥·½Ê½£¬3- RTP·½Ê½£¬4-RTP/RTSP£¬5-RSTP/HTTP
int Ret;
NET_DVR_COMPRESSIONCFG_V30 struParams = { 0 };
DWORD dwReturnLen;
Ret = NET_DVR_GetDVRConfig(lUserID, NET_DVR_GET_COMPRESSCFG_V30, struPlayInfo.lChannel, &struParams, sizeof(NET_DVR_COMPRESSIONCFG_V30), &dwReturnLen);
if (!Ret)
{
cout << "Failed to get config" << endl;
printf("error code: %d\n", NET_DVR_GetLastError());
}
else
{
cout<<"----------------------------------------show main-----------------------------------"<<endl;
showStreamConfig(struParams.struNormHighRecordPara);
cout<<"----------------------------------------show sub-----------------------------------"<<endl;
showStreamConfig(struParams.struNetPara);
cout<<"----------------------------------------update main & sub-----------------------------------"<<endl;
setMainStreamConfig(struParams.struNormHighRecordPara);
setSubStreamConfig(struParams.struNetPara);
cout<<"----------------------------------------set main & sub-----------------------------------"<<endl;
int SetCamera = NET_DVR_SetDVRConfig(lUserID, NET_DVR_SET_COMPRESSCFG_V30, struPlayInfo.lChannel, &struParams, sizeof(NET_DVR_COMPRESSIONCFG_V30));
if (SetCamera)
{
cout<<"update config success" <<endl;
}
}
NET_DVR_Logout(lUserID);
return 0;
}
| [
"ylteng@outlook.com"
] | ylteng@outlook.com |
a10f164261ccaf8271c098e8fd04215cfecfac1c | 8bff531fe2f9efb5ffb5da95ae3df0406b51e5b3 | /graf1111111.cpp | 9544d336aa1c406df092dfea12c01387ad9cbbe9 | [] | no_license | Irina121-star/- | e3ec0ecfa9c5c7bbe5d9966b770840e63de37bff | e67c18e1dbb4ada43a0e5b669b4bd7114a852cad | refs/heads/master | 2021-01-31T14:30:43.275714 | 2020-03-01T13:05:37 | 2020-03-01T13:05:37 | 243,516,690 | 3 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 606 | cpp | #include "TXLib.h"
void DrawGraphic (double (*func) (double x), COLORREF color);
double Sqr (double x);
int main ()
{
txCreateWindow (800, 600);
DrawGraphic(&Sqr, TX_LIGHTRED);
DrawGraphic(&sin, TX_LIGHTGREEN);
}
void DrawGraphic (double (*func) (double x), COLORREF color)
{
txSetColor (color);
txSetFillColor (color);
double x = - 10;
while (x <= +10)
{
double y = (*func) (x);
txCircle (400 + 50 * x, 300 - 50 * y, 3);
x += 0.01;
}
}
double Sqr (double x) {return x*x;}
| [
"noreply@github.com"
] | Irina121-star.noreply@github.com |
44fc70f682e8e20542fd77f5211b5efdde5cb206 | a965ffd57bb0514349ef952ab950965a1cd81c95 | /src/DEKF.cpp | 902ebd319cc7be91958654cbf4d9d665d1091465 | [] | no_license | svilsen/BatteryPrognostics | 0c2b8e652405defb12f85683f9ce62120a75ddb2 | b08b20f4b8e7e17027d05e9a96742375bd334317 | refs/heads/master | 2021-11-09T20:46:32.370307 | 2018-10-08T07:42:30 | 2018-10-08T07:42:30 | 145,852,428 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 12,007 | cpp | #include <RcppArmadillo.h>
#include <boost/random/variate_generator.hpp>
#include <boost/generator_iterator.hpp>
#include <boost/random/mersenne_twister.hpp>
#include <boost/random/uniform_01.hpp>
template <typename T> int sgn(T val)
{
return(T(0) < val) - (val < T(0));
}
class DEKFModel {
private:
//
arma::colvec I, V, ocv_parameters;
double dt, eta, C_max; //
int sign_I;
bool trace;
unsigned int traceLimit, S, N, K, T;
//
double V_OC(const double & SOC_, const double & alpha)
{
const double p0 = ocv_parameters[0];
const double p1 = ocv_parameters[1];
const double p2 = ocv_parameters[2];
const double p3 = ocv_parameters[3];
const double & _SOC_ = SOC_;
const double & SOC_2 = _SOC_ * _SOC_;
const double & SOC_3 = _SOC_ * SOC_2;
return p0 + p1 * _SOC_ + p2 * SOC_2 + p3 * SOC_3 + sign_I * alpha;
}
double V_OC_(const double & SOC_)
{
const double p1 = ocv_parameters[1];
const double p2 = ocv_parameters[2];
const double p3 = ocv_parameters[3];
const double & _SOC_ = SOC_;
const double & SOC_2 = _SOC_ * _SOC_;
return p1 + 2.0 * p2 * _SOC_ + 3.0 * p3 * SOC_2;
}
double h(const unsigned int & t, const arma::colvec & X_, const arma::colvec & theta_)
{
const double & R0 = std::exp(theta_[0]);
double V_ = V_OC(X_[0], theta_[S - 1]) + I[t] * R0;
for (unsigned int k = 0; k < K; k++)
{
V_ += X_[k + 1];
}
return V_;
}
arma::colvec f(const unsigned int & t, const arma::colvec & X_, const arma::colvec & theta_)
{
arma::colvec X_new = arma::zeros(X_.size());
X_new[0] = X_[0] + eta * dt / C_max * I[t]; // theta_[2 * K + 1] *
for (unsigned int k = 0; k < K; k++)
{
const double & Rk = std::exp(theta[2 * k + 1]);
const double & tau_k = theta[2 * k + 2];
const double & Vk_ = std::exp(-dt / tau_k);
X_new[k + 1] = X_[k + 1] * Vk_ + Rk * (1.0 - Vk_) * I[t];
}
return X_new;
}
void update_F(const unsigned int & t)
{
F = arma::zeros(K + 1, K + 1);
F(0, 0) = 1.0;
for (unsigned int k = 0; k < K; k++)
{
F(k + 1, k + 1) = std::exp(-dt / theta[2 * k + 2]);
}
}
void update_H_x()
{
H_x = arma::ones(1, K + 1);
H_x(0, 0) = V_OC_(X[0]);
}
void update_H_theta(const unsigned int & t)
{
arma::mat H = arma::zeros(1, S);
H(0, 0) = I[t];
H(0, S - 1) = sign_I; // 1;
arma::mat x_theta = arma::zeros(K + 1, S);
for (unsigned int k = 0; k < K; k++)
{
const double Rk = std::exp(theta[2 * k + 1]);
const double tau_k = theta[2 * k + 2];
const double tau_squared = tau_k * tau_k;
x_theta(k + 1, 2 * k + 1) = I[t] * (std::exp(dt / tau_squared) - 1.0);
x_theta(k + 1, 2 * k + 2) = (dt / tau_squared) *
(X[k + 1] + Rk * I[t]) * std::exp(-dt / tau_k);
}
// x_theta(0, 2 * K + 1) = dt * I[t] / C_max;
arma::mat H_ = H_x * x_theta;
H_theta = H + H_;
}
public:
//
arma::colvec theta, X, VT, SOC;
arma::mat F, H_x, H_theta, Q_x, Q_theta, P_x, P_theta, R_x, R_theta, theta_trace;
double LogLikelihood;
//
DEKFModel(const arma::colvec & I_, const arma::colvec & V_, const arma::colvec & theta_,
const arma::colvec & ocv_parameters_, const std::vector<arma::mat> & P,
const std::vector<arma::mat> & Q, const std::vector<arma::mat> & R,
const double & dt_, const unsigned int K_, const double SOC_intial_, const double C_max_,
const double & eta_, const bool & trace_, const unsigned int & traceLimit_) :
I(I_), V(V_), theta(theta_), ocv_parameters(ocv_parameters_), dt(dt_), K(K_),
trace(trace_), traceLimit(traceLimit_), N(1), eta(eta_)
{
C_max = 3600 * C_max_;
// eta = 1.0;
sign_I = 0;
T = I.size();
S = theta.size();
VT = arma::colvec(T);
SOC = arma::colvec(T);
theta_trace = arma::mat(S, T);
X = arma::zeros(K + 1);
X[0] = SOC_intial_;
Q_x = Q[0];
P_x = P[0];
R_x = R[0];
Q_theta = Q[1];
P_theta = P[1];
R_theta = R[1];
}
//
void Filter()
{
boost::mt19937 rng;
boost::random::uniform_01<> uniform_real;
boost::variate_generator<boost::mt19937 &, boost::random::uniform_01<> > generate_uniform_real(rng, uniform_real);
double V_hat;
arma::colvec X_, theta_;
arma::mat P_x_, P_theta_, L_x, L_theta, S_x, S_theta, HL_x, HL_theta;
LogLikelihood = 0;
for (unsigned int t = 0; t < T; t++)
{
if (trace & ((t == 0) | ((t % traceLimit) == 0) | (t == (T - 1))))
{
Rcpp::Rcout << "Iteration: " << t + 1 << " / " << T << "\n";
}
if (sgn(I[t]) != 0)
{
sign_I = sgn(I[t]);
}
update_F(t);
//// Time-update
theta_ = theta;
X_ = f(t, X, theta_);
P_x_ = F * P_x * F.t() + Q_x;
P_theta_ = P_theta + Q_theta;
//// Measurement-update
// X
update_H_x();
S_x = H_x * P_x_ * H_x.t() + R_x;
L_x = P_x_ * H_x.t() * arma::inv(S_x);
V_hat = h(t, X_, theta_);
X = X_ + L_x * (V[t] - V_hat);
HL_x = arma::eye(K + 1, K + 1) - L_x * H_x;
P_x = HL_x * P_x_ * HL_x.t() + L_x * R_x * L_x.t();
// Theta
update_H_theta(t);
S_theta = H_theta * P_theta_ * H_theta.t() + R_theta;
L_theta = P_theta_ * H_theta.t() * arma::inv(S_theta);
theta = theta_ + L_theta * (V[t] - V_hat);
HL_theta = arma::eye(S, S) - L_theta * H_theta;
P_theta = HL_theta * P_theta_ * HL_theta.t() + L_theta * R_theta * L_theta.t();
VT[t] = h(t, X, theta);
SOC[t] = X[0];
theta_trace.col(t) = theta;
const double & error = V[t] - VT[t];
LogLikelihood += (std::abs(S_x(0, 0)) + (error * error) / S_x(0, 0));
}
}
void Smooth()
{
boost::mt19937 rng;
boost::random::uniform_01<> uniform_real;
boost::variate_generator<boost::mt19937 &, boost::random::uniform_01<> > generate_uniform_real(rng, uniform_real);
double V_hat;
arma::colvec X_, theta_;
arma::mat P_x_, P_theta_, L_x, L_theta, S_x, S_theta, HL_x, HL_theta;
LogLikelihood = 0;
for (unsigned int t = (T - 1); t > -1; t--)
{
if (trace & ((t == 0) | ((t % traceLimit) == 0) | (t == (T - 1))))
{
Rcpp::Rcout << "Iteration: " << t + 1 << " / " << T << "\n";
}
update_F(t);
//// Time-update
theta_ = theta;
X_ = f(t, X, theta_);
P_x_ = F * P_x * F.t() + Q_x;
P_theta_ = P_theta + Q_theta;
//// Measurement-update
// X
update_H_x();
S_x = H_x * P_x_ * H_x.t() + R_x;
L_x = P_x_ * H_x.t() * arma::inv(S_x);
V_hat = h(t, X_, theta_);
X = X_ + L_x * (V[t] - V_hat);
HL_x = arma::eye(K + 1, K + 1) - L_x * H_x;
P_x = HL_x * P_x_ * HL_x.t() + L_x * R_x * L_x.t();
// Theta
update_H_theta(t);
S_theta = H_theta * P_theta_ * H_theta.t() + R_theta;
L_theta = P_theta_ * H_theta.t() * arma::inv(S_theta);
theta = theta_ + L_theta * (V[t] - V_hat);
HL_theta = arma::eye(S, S) - L_theta * H_theta;
P_theta = HL_theta * P_theta_ * HL_theta.t() + L_theta * R_theta * L_theta.t();
VT[t] = h(t, X, theta);
SOC[t] = X[0];
theta_trace.col(t) = theta;
const double & error = V[t] - VT[t];
LogLikelihood += (std::abs(S_x(0, 0)) + (error * error) / S_x(0, 0));
}
}
};
//[[Rcpp::export]]
Rcpp::List SODEFKFilterCpp(const arma::colvec & I, const arma::colvec & V, const arma::colvec & theta_0,
const arma::colvec & ocv_parameters, const double & SOC_0, const double & C_max, const double & eta,
const std::vector<arma::mat> & P, const std::vector<arma::mat> & Q, const std::vector<arma::mat> & R,
const double & dt, const unsigned int K, const bool & trace, const unsigned int & traceLimit)
{
DEKFModel DEKF(I, V, theta_0, ocv_parameters, P, Q, R, dt, K, SOC_0, C_max, eta, trace, traceLimit);
DEKF.Filter();
return Rcpp::List::create(Rcpp::Named("V") = V,
Rcpp::Named("V_hat") = DEKF.VT,
Rcpp::Named("SOC") = DEKF.SOC,
Rcpp::Named("Theta") = DEKF.theta,
Rcpp::Named("ThetaTrace") = DEKF.theta_trace,
Rcpp::Named("LogLikelihood") = DEKF.LogLikelihood);
}
//[[Rcpp::export]]
Rcpp::List SODEFKSmoothCpp(const arma::colvec & I, const arma::colvec & V, const arma::colvec & theta_0,
const arma::colvec & ocv_parameters, const double & SOC_0, const double & C_max, const double & eta,
const std::vector<arma::mat> & P, const std::vector<arma::mat> & Q, const std::vector<arma::mat> & R,
const double & dt, const unsigned int K, const bool & trace, const unsigned int & traceLimit)
{
DEKFModel DEKF(I, V, theta_0, ocv_parameters, P, Q, R, dt, K, SOC_0, C_max, eta, trace, traceLimit);
DEKF.Filter();
DEKF.Smooth();
return Rcpp::List::create(Rcpp::Named("V") = V,
Rcpp::Named("V_hat") = DEKF.VT,
Rcpp::Named("SOC") = DEKF.SOC,
Rcpp::Named("Theta") = DEKF.theta,
Rcpp::Named("ThetaTrace") = DEKF.theta_trace,
Rcpp::Named("LogLikelihood") = DEKF.LogLikelihood);
} | [
"svilsen@math.aau.dk"
] | svilsen@math.aau.dk |
6af7a9c8b2146aa69d32a6fd3f53c12ac64c23a5 | fd2109e771386dc8d291a0f162dd788070b19fbd | /hardware/firmware/lib/ip/altera/hps/altera_hps/hwlib/include/soc_a10/socal/alt_usb.h | 794f7a87670963c718dc37b96687acc24f65f657 | [] | no_license | lcfyi/quarantine-monitor | bb9cc4cc2e6f28fc7348bd41ac52b9dec281a1c9 | 3579bd7095b6cf123767cc187ebad87f8a02f352 | refs/heads/master | 2023-04-08T08:02:07.407664 | 2021-04-15T06:59:50 | 2021-04-15T06:59:50 | 337,192,645 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 5,708,998 | h | /***********************************************************************************
* *
* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
* *
* Redistribution and use in source and binary forms, with or without *
* modification, are permitted provided that the following conditions are met: *
* *
* 1. Redistributions of source code must retain the above copyright notice, *
* this list of conditions and the following disclaimer. *
* *
* 2. Redistributions in binary form must reproduce the above copyright notice, *
* this list of conditions and the following disclaimer in the documentation *
* and/or other materials provided with the distribution. *
* *
* 3. Neither the name of the copyright holder nor the names of its contributors *
* may be used to endorse or promote products derived from this software without *
* specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************/
/* Altera - ALT_USB_GLOB */
#ifndef __ALT_SOCAL_USB_H__
#define __ALT_SOCAL_USB_H__
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#include <cstdint>
extern "C"
{
#else /* __cplusplus */
#include <stdint.h>
#endif /* __cplusplus */
#endif /* __ASSEMBLY__ */
/*
* Component : ALT_USB_GLOB
*
*/
/*
* Register : gotgctl
*
* OTG Control and Status Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_SESREQSCS
* [1] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_SESREQ
* [2] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
* [3] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
* [4] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
* [5] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
* [6] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
* [7] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
* [8] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
* [9] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_HNPREQ
* [10] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
* [11] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_DEVHNPEN
* [13:12] | ??? | 0x0 | *UNDEFINED*
* [14] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_EHEN
* [15] | ??? | 0x0 | *UNDEFINED*
* [16] | R | 0x1 | ALT_USB_GLOB_GOTGCTL_CONIDSTS
* [17] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_DBNCTIME
* [18] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_ASESVLD
* [19] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_BSESVLD
* [20] | RW | 0x0 | ALT_USB_GLOB_GOTGCTL_OTGVER
* [21] | R | 0x0 | ALT_USB_GLOB_GOTGCTL_CURMOD
* [31:22] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : sesreqscs
*
* Mode: Device only
*
* Session Request Success (SesReqScs)
*
* The core sets this bit when a session request initiation is
*
* successful.
*
* 1'b0: Session request failure
*
* 1'b1: Session request success
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL | 0x0 | Session request failure
* ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS | 0x1 | Session request success
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
*
* Session request failure
*/
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_FAIL 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQSCS
*
* Session request success
*/
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_E_SUCCESS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_MSB 0
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQSCS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQSCS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQSCS_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : sesreq
*
* Mode: Device only
*
* Session Request (SesReq)
*
* The application sets this bit to initiate a session request on the
*
* USB. The application can clear this bit by writing a 0 when the
*
* Host Negotiation Success Status Change bit in the OTG
*
* Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The
*
* core clears this bit when the HstNegSucStsChng bit is cleared.
*
* If you use the USB 1.1 Full-Speed Serial Transceiver interface to
*
* initiate the session request, the application must wait until the
*
* VBUS discharges to 0.2 V, after the B-Session Valid bit in this
*
* register (GOTGCTL.BSesVld) is cleared. This discharge time
*
* varies between different PHYs and can be obtained from the
*
* PHY vendor.
*
* 1'b0: No session request
*
* 1'b1: Session request
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------
* ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST | 0x0 | No session request
* ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST | 0x1 | Session request
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
*
* No session request
*/
#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_NOREQUEST 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_SESREQ
*
* Session request
*/
#define ALT_USB_GLOB_GOTGCTL_SESREQ_E_REQUEST 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_MSB 1
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_SESREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_GLOB_GOTGCTL_SESREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_SESREQ field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GOTGCTL_SESREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_SESREQ_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : vbvalidoven
*
* VBUS Valid Override Enable (VbvalidOvEn)
*
* This bit is used to enable/disable the software to
*
* override the Bvalid signal using the GOTGCTL.VbvalidOvVal.
*
* 1'b1 : Internally Bvalid received from the PHY is overridden with
* GOTGCTL.VbvalidOvVal.
*
* 1'b0 : Override is disabled and bvalid signal from the respective PHY selected
* is used
*
* internally by the core
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the
* : | | respective PHY selected is used internally by
* : | | the force
* ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END | 0x1 | The vbus-valid signal received from the PHY is
* : | | overridden with GOTGCTL.vbvalidOvVal
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
*
* Override is disabled and bvalid signal from the respective PHY selected is used
* internally by the force
*/
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN
*
* The vbus-valid signal received from the PHY is overridden with
* GOTGCTL.vbvalidOvVal
*/
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_MSB 2
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : vbvalidovval
*
* VBUS Valid OverrideValue (VbvalidOvVal)
*
* This bit is used to set Override value for vbusvalid
*
* signal when GOTGCTL.VbvalidOvEn is set.
*
* 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1
*
* 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------------------------
* ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 | 0x0 | vbusvalid value when GOTGCTL.VbvalidOvEn = 1
* ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 | 0x1 | vbusvalid value when GOTGCTL.VbvalidOvEn is 1
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
*
* vbusvalid value when GOTGCTL.VbvalidOvEn = 1
*/
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL
*
* vbusvalid value when GOTGCTL.VbvalidOvEn is 1
*/
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_E_SET1 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_MSB 3
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : avalidoven
*
* A-Peripheral Session Valid Override Enable (AvalidOvEn)
*
* This bit is used to enable/disable the software to
*
* override the Avalid signal using the GOTGCTL.AvalidOvVal.
*
* 1'b1 : Internally Avalid received from the PHY is overridden with
* GOTGCTL.AvalidOvVal.
*
* 1'b0 : Override is disabled and avalid signal from the respective PHY selected
* is used
*
* internally by the core
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD | 0x0 | Override is disabled and Avalid signal from the
* : | | respective PHY is used internally by the core.
* ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END | 0x1 | Internally Avalid received from the PHY is
* : | | overridden with GOTGCTL.AvalidOvVa
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
*
* Override is disabled and Avalid signal from the respective PHY is used
* internally by the core.
*/
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVEN
*
* Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVa
*/
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_MSB 4
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVEN_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : avalidovval
*
* A-Peripheral Session Valid OverrideValue (AvalidOvVal)
*
* This bit is used to set Override value for Avalid signal
*
* when GOTGCTL.AvalidOvEn is set.
*
* 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1
*
* 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 | 0x0 | Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
* ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 | 0x1 | Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
*
* Avalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
*/
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL
*
* Avalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
*/
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_E_VALUE1 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_MSB 5
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : bvalidoven
*
* B-Peripheral Session Valid Override Enable (BvalidOvEn)
*
* This bit is used to enable/disable the software to
*
* override the Bvalid signal using the GOTGCTL.BvalidOvVal.
*
* 1'b1 : Internally Bvalid received from the PHY is overridden with
* GOTGCTL.BvalidOvVal.
*
* 1'b0 : Override is disabled and bvalid signal from the respective PHY selected
* is used
*
* internally by the force
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD | 0x0 | Override is disabled and bvalid signal from the
* : | | respective PHY selected is used internally by
* : | | the core
* ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END | 0x1 | Internally Bvalid received from the PHY is
* : | | overridden with GOTGCTL.BvalidOvVal
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
*
* Override is disabled and bvalid signal from the respective PHY selected is used
* internally by the core
*/
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVEN
*
* Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal
*/
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_MSB 6
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVEN_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : bvalidovval
*
* B-Peripheral Session Valid OverrideValue (BvalidOvVal)
*
* This bit is used to set Override value for Bvalid
*
* signal when GOTGCTL.BvalidOvEn is set.
*
* 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1
*
* 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------------------
* ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 | 0x0 | Bvalid value when GOTGCTL.AvalidOvEn =1
* ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 | 0x1 | Bvalid value when GOTGCTL.AvalidOvEn =1
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
*
* Bvalid value when GOTGCTL.AvalidOvEn =1
*/
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL
*
* Bvalid value when GOTGCTL.AvalidOvEn =1
*/
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_E_VALUE1 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_MSB 7
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : hstnegscs
*
* Mode: Device only
*
* Host Negotiation Success (HstNegScs)
*
* The core sets this bit when host negotiation is successful. The
*
* core clears this bit when the HNP Request (HNPReq) bit in this
*
* register is SET.
*
* 1'b0: Host negotiation failure
*
* 1'b1: Host negotiation success
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------
* ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL | 0x0 | Host negotiation failure
* ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS | 0x1 | Host negotiation success
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
*
* Host negotiation failure
*/
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_FAIL 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTNEGSCS
*
* Host negotiation success
*/
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_E_SUCCESS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_MSB 8
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTNEGSCS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GOTGCTL_HSTNEGSCS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HSTNEGSCS_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : hnpreq
*
* Mode: Device only
*
* HNP Request (HNPReq)
*
* The application sets this bit to initiate an HNP request to the
*
* connected USB host. The application can clear this bit by writing
*
* a 0 when the Host Negotiation Success Status Change bit in the
*
* OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET.
*
* The core clears this bit when the HstNegSucStsChng bit is
*
* cleared.
*
* 1'b0: No HNP request
*
* 1'b1: HNP request
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------
* ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD | 0x0 | No HNP request
* ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END | 0x1 | HNP request
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
*
* No HNP request
*/
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HNPREQ
*
* HNP request
*/
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_MSB 9
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HNPREQ register field value. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HNPREQ register field. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HNPREQ field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GOTGCTL_HNPREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HNPREQ_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : hstsethnpen
*
* Mode: Host only
*
* Host Set HNP Enable (HstSetHNPEn)
*
* The application sets this bit when it has successfully enabled
*
* HNP (using the SetFeature.SetHNPEnable command) on the
*
* connected device.
*
* 1'b0: Host Set HNP is not enabled
*
* 1'b1: Host Set HNP is enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD | 0x0 | Host Set HNP is not enabled
* ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END | 0x1 | Host Set HNP is enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
*
* Host Set HNP is not enabled
*/
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN
*
* Host Set HNP is enabled
*/
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_MSB 10
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : devhnpen
*
* Mode: Device only
*
* Device HNP Enabled (DevHNPEn)
*
* The application sets this bit when it successfully receives a
*
* SetFeature.SetHNPEnable command from the connected USB
*
* host.
*
* 1'b0: HNP is not enabled in the application
*
* 1'b1: HNP is enabled in the application
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------------------
* ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD | 0x0 | HNP is not enabled in the application
* ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END | 0x1 | HNP Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
*
* HNP is not enabled in the application
*/
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DEVHNPEN
*
* HNP Enabled
*/
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_MSB 11
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_DEVHNPEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GOTGCTL_DEVHNPEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_DEVHNPEN_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : ehen
*
* Mode: SRP Capable Host
*
* Embedded Host Enable (EHEn)
*
* 1’b1 : Enable Embedded Host Mode.
*
* 1’b0: Disable Embedded Host Mode.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_MSB 14
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_EHEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_EHEN register field value. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_EHEN register field. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_EHEN field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GOTGCTL_EHEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_EHEN_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : conidsts
*
* Mode: Host and Device
*
* Connector ID Status (ConIDSts)
*
* Indicates the connector ID status on a connect event.
*
* 1'b0: The DWC_otg core is in A-Device mode
*
* 1'b1: The DWC_otg core is in B-Device mode
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-------------------------------------
* ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA | 0x0 | The DWC_otg core is in A-Device mode
* ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB | 0x1 | The otg core is in B-Device mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
*
* The DWC_otg core is in A-Device mode
*/
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODA 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_CONIDSTS
*
* The otg core is in B-Device mode
*/
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_E_MODB 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_MSB 16
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_CONIDSTS register field. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_RESET 0x1
/* Extracts the ALT_USB_GLOB_GOTGCTL_CONIDSTS field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_GLOB_GOTGCTL_CONIDSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_CONIDSTS_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : dbnctime
*
* Mode: Host only
*
* Long/Short Debounce Time (DbncTime)
*
* Indicates the debounce time of a detected connection.
*
* 1'b0: Long debounce time, used FOR physical connections
*
* (100 ms + 2.5 micro-sec)
*
* 1'b1: Short debounce time, used FOR soft connections (2.5 micro-sec)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG | 0x0 | Long debounce time, used FOR physical
* : | | connections (100 ms + 2.5 s)
* ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT | 0x1 | Short debounce time, used FOR soft connections
* : | | (2.5 s
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
*
* Long debounce time, used FOR physical connections (100 ms + 2.5 s)
*/
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_LONG 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_DBNCTIME
*
* Short debounce time, used FOR soft connections (2.5 s
*/
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_E_SHORT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_MSB 17
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_DBNCTIME register field. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_DBNCTIME field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GOTGCTL_DBNCTIME register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_DBNCTIME_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : asesvld
*
* Mode: Host only
*
* A-Session Valid (ASesVld)
*
* Indicates the Host mode transceiver status.
*
* 1'b0: A-session is not valid
*
* 1'b1: A-session is valid
*
* Note: If you do not enabled OTG features (such as SRP and HNP), the
*
* read reset value will be 1.The vbus assigns the values internally for non-
*
* SRP or non-HNP configurations.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------
* ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID | 0x0 | A-session is not valid
* ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID | 0x1 | A-session is valid
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
*
* A-session is not valid
*/
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_VALID 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_ASESVLD
*
* A-session is valid
*/
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_E_NOTVALID 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_MSB 18
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_ASESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_ASESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_ASESVLD field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GOTGCTL_ASESVLD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_ASESVLD_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : bsesvld
*
* Mode: Device only
*
* B-Session Valid (BSesVld)
*
* Indicates the Device mode transceiver status.
*
* 1'b0: B-session is not valid.
*
* 1'b1: B-session is valid.
*
* In OTG mode, you can use this bit to determine IF the device is
*
* connected or disconnected.
*
* Note: If you do not enabled OTG features (such as SRP and HNP), the
*
* read reset value will be 1.The vbus assigns the values internally for non-
*
* SRP or non-HNP configurations.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------
* ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID | 0x0 | B-session is not valid
* ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID | 0x1 | B-session is valid
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
*
* B-session is not valid
*/
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_NOTVALID 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_BSESVLD
*
* B-session is valid
*/
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_E_VALID 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_MSB 19
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_BSESVLD register field value. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_BSESVLD register field. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_BSESVLD field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GOTGCTL_BSESVLD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_BSESVLD_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : otgver
*
* OTG Version (OTGVer)
*
* Indicates the OTG revision.
*
* 1'b0: OTG Version 1.3. In this version the core supports Data line
*
* pulsing and VBus pulsing for SRP.
*
* 1'b1: OTG Version 2.0. In this version the core supports only Data
*
* line pulsing for SRP.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------------------
* ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 | 0x0 | OTG Version 1.3. In this version the core
* : | | supports Data line
* ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 | 0x1 | OTG Version 2.0. In this version the core
* : | | supports only Data line pulsing for SRP
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
*
* OTG Version 1.3. In this version the core supports Data line
*/
#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER13 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGCTL_OTGVER
*
* OTG Version 2.0. In this version the core supports only Data line pulsing for
* SRP
*/
#define ALT_USB_GLOB_GOTGCTL_OTGVER_E_VER20 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_MSB 20
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_OTGVER register field value. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_OTGVER register field. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_OTGVER field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GOTGCTL_OTGVER register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_OTGVER_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : curmod
*
* Mode: Host and Device
*
* Current Mode of Operation (CurMod)
*
* Indicates the current mode.
*
* 1'b0: Device mode
*
* 1'b1: Host mode
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_MSB 21
/* The width in bits of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGCTL_CURMOD register field value. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GOTGCTL_CURMOD register field value. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GOTGCTL_CURMOD register field. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGCTL_CURMOD field value from a register. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GOTGCTL_CURMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGCTL_CURMOD_SET(value) (((value) << 21) & 0x00200000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GOTGCTL.
*/
struct ALT_USB_GLOB_GOTGCTL_s
{
const uint32_t sesreqscs : 1; /* ALT_USB_GLOB_GOTGCTL_SESREQSCS */
uint32_t sesreq : 1; /* ALT_USB_GLOB_GOTGCTL_SESREQ */
uint32_t vbvalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_VBVALIDOVEN */
uint32_t vbvalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_VBVALIDOVVAL */
uint32_t avalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_AVALIDOVEN */
uint32_t avalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_AVALIDOVVAL */
uint32_t bvalidoven : 1; /* ALT_USB_GLOB_GOTGCTL_BVALIDOVEN */
uint32_t bvalidovval : 1; /* ALT_USB_GLOB_GOTGCTL_BVALIDOVVAL */
const uint32_t hstnegscs : 1; /* ALT_USB_GLOB_GOTGCTL_HSTNEGSCS */
uint32_t hnpreq : 1; /* ALT_USB_GLOB_GOTGCTL_HNPREQ */
uint32_t hstsethnpen : 1; /* ALT_USB_GLOB_GOTGCTL_HSTSETHNPEN */
uint32_t devhnpen : 1; /* ALT_USB_GLOB_GOTGCTL_DEVHNPEN */
uint32_t : 2; /* *UNDEFINED* */
uint32_t ehen : 1; /* ALT_USB_GLOB_GOTGCTL_EHEN */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t conidsts : 1; /* ALT_USB_GLOB_GOTGCTL_CONIDSTS */
const uint32_t dbnctime : 1; /* ALT_USB_GLOB_GOTGCTL_DBNCTIME */
const uint32_t asesvld : 1; /* ALT_USB_GLOB_GOTGCTL_ASESVLD */
const uint32_t bsesvld : 1; /* ALT_USB_GLOB_GOTGCTL_BSESVLD */
uint32_t otgver : 1; /* ALT_USB_GLOB_GOTGCTL_OTGVER */
const uint32_t curmod : 1; /* ALT_USB_GLOB_GOTGCTL_CURMOD */
uint32_t : 10; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GOTGCTL. */
typedef volatile struct ALT_USB_GLOB_GOTGCTL_s ALT_USB_GLOB_GOTGCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GOTGCTL register. */
#define ALT_USB_GLOB_GOTGCTL_RESET 0x00010000
/* The byte offset of the ALT_USB_GLOB_GOTGCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GOTGCTL_OFST 0x0
/* The address of the ALT_USB_GLOB_GOTGCTL register. */
#define ALT_USB_GLOB_GOTGCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGCTL_OFST))
/*
* Register : gotgint
*
* OTG Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [1:0] | ??? | 0x0 | *UNDEFINED*
* [2] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_SESENDDET
* [7:3] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
* [9] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
* [16:10] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_HSTNEGDET
* [18] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
* [19] | RW | 0x0 | ALT_USB_GLOB_GOTGINT_DBNCEDONE
* [31:20] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : sesenddet
*
* Mode:Host and Device
*
* Session End Detected (SesEndDet)
*
* The core sets this bit when the utmiotg_bvalid signal is
*
* deasserted.This bit can be set only by the core and the application should write
* 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT | 0x0 | Non Active State
* ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT | 0x1 | Set when utmisrp_bvalid signal is deasserted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
*
* Non Active State
*/
#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESENDDET
*
* Set when utmisrp_bvalid signal is deasserted
*/
#define ALT_USB_GLOB_GOTGINT_SESENDDET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_MSB 2
/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESENDDET register field value. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_GLOB_GOTGINT_SESENDDET register field. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_SESENDDET field value from a register. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GOTGINT_SESENDDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_SESENDDET_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : sesreqsucstschng
*
* Mode:Host and Device
*
* Session Request Success Status Change
*
* (SesReqSucStsChng)
*
* The core sets this bit on the success or failure of a session
*
* request. The application must read the Session Request
*
* Success bit in the OTG Control and Status register
*
* (GOTGCTL.SesReqScs) to check For success or failure.This bit can be set only by
* the core and the application should write 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:-----------------------
* ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT | 0x0 | No change
* ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT | 0x1 | Session Request Status
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
*
* No change
*/
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG
*
* Session Request Status
*/
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_MSB 8
/* The width in bits of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : hstnegsucstschng
*
* Mode:Host and Device
*
* Host Negotiation Success Status Change (HstNegSucStsChng)
*
* The core sets this bit on the success or failure of a USB host
*
* negotiation request. The application must read the Host
*
* Negotiation Success bit of the OTG Control and Status register
*
* (GOTGCTL.HstNegScs) to check For success or failure.This bit can be set only by
* the core and the application should write 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:-------------------------------
* ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT | 0x0 | No Change
* ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT | 0x1 | Host Negotiation Status Change
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
*
* No Change
*/
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG
*
* Host Negotiation Status Change
*/
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_MSB 9
/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : hstnegdet
*
* Mode:Host and Device
*
* Host Negotiation Detected (HstNegDet)
*
* The core sets this bit when it detects a host negotiation request
*
* on the USB.This bit can be set only by the core and the application should write
* 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------------
* ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT | 0x0 | No Change
* ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT | 0x1 | Host Negotiation Detected
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
*
* No Change
*/
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_HSTNEGDET
*
* Host Negotiation Detected
*/
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_MSB 17
/* The width in bits of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_HSTNEGDET register field. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_HSTNEGDET field value from a register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GOTGINT_HSTNEGDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_HSTNEGDET_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : adevtoutchg
*
* Mode:Host and Device
*
* A-Device Timeout Change (ADevTOUTChg)
*
* The core sets this bit to indicate that the A-device has timed out
*
* WHILE waiting FOR the B-device to connect.This bit can be set only by the core
* and the application should write 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-----------------
* ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT | 0x0 | No Change
* ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT | 0x1 | A-Device Timeout
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
*
* No Change
*/
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG
*
* A-Device Timeout
*/
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_MSB 18
/* The width in bits of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG field value from a register. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : dbncedone
*
* Mode: Host only
*
* Debounce Done (DbnceDone)
*
* The core sets this bit when the debounce is completed after the
*
* device connect. The application can start driving USB reset after
*
* seeing this interrupt. This bit is only valid when the HNP
*
* Capable or SRP Capable bit is SET in the Core USB
*
* Configuration register (GUSBCFG.HNPCap or
*
* GUSBCFG.SRPCap, respectively).This bit can be set only by the core and the
* application should write 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-------------------
* ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT | 0x0 | No Change
* ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT | 0x1 | Debounce completed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
*
* No Change
*/
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GOTGINT_DBNCEDONE
*
* Debounce completed
*/
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_MSB 19
/* The width in bits of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GOTGINT_DBNCEDONE register field. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GOTGINT_DBNCEDONE field value from a register. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GOTGINT_DBNCEDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GOTGINT_DBNCEDONE_SET(value) (((value) << 19) & 0x00080000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GOTGINT.
*/
struct ALT_USB_GLOB_GOTGINT_s
{
uint32_t : 2; /* *UNDEFINED* */
uint32_t sesenddet : 1; /* ALT_USB_GLOB_GOTGINT_SESENDDET */
uint32_t : 5; /* *UNDEFINED* */
uint32_t sesreqsucstschng : 1; /* ALT_USB_GLOB_GOTGINT_SESREQSUCSTSCHNG */
uint32_t hstnegsucstschng : 1; /* ALT_USB_GLOB_GOTGINT_HSTNEGSUCSTSCHNG */
uint32_t : 7; /* *UNDEFINED* */
uint32_t hstnegdet : 1; /* ALT_USB_GLOB_GOTGINT_HSTNEGDET */
uint32_t adevtoutchg : 1; /* ALT_USB_GLOB_GOTGINT_ADEVTOUTCHG */
uint32_t dbncedone : 1; /* ALT_USB_GLOB_GOTGINT_DBNCEDONE */
uint32_t : 12; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GOTGINT. */
typedef volatile struct ALT_USB_GLOB_GOTGINT_s ALT_USB_GLOB_GOTGINT_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GOTGINT register. */
#define ALT_USB_GLOB_GOTGINT_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GOTGINT register from the beginning of the component. */
#define ALT_USB_GLOB_GOTGINT_OFST 0x4
/* The address of the ALT_USB_GLOB_GOTGINT register. */
#define ALT_USB_GLOB_GOTGINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GOTGINT_OFST))
/*
* Register : gahbcfg
*
* AHB Configuration Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
* [4:1] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_HBSTLEN
* [5] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_DMAEN
* [6] | ??? | 0x0 | *UNDEFINED*
* [7] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
* [8] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
* [20:9] | ??? | 0x0 | *UNDEFINED*
* [21] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
* [22] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
* [23] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_AHBSINGLE
* [24] | RW | 0x0 | ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS
* [31:25] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : glblintrmsk
*
* Mode:Host and device
*
* Global Interrupt Mask (GlblIntrMsk)
*
* The application uses this bit to mask or unmask the interrupt line
*
* assertion to itself. Irrespective of this bit's setting, the interrupt
*
* status registers are updated by the core.
*
* 1'b0: Mask the interrupt assertion to the application.
*
* 1'b1: Unmask the interrupt assertion to the application.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK | 0x0 | Mask the interrupt assertion to the application
* ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK | 0x1 | Unmask the interrupt assertion to the
* : | | application.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
*
* Mask the interrupt assertion to the application
*/
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK
*
* Unmask the interrupt assertion to the application.
*/
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_MSB 0
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : hbstlen
*
* Mode:Host and device
*
* Burst Length/Type (HBstLen)
*
* This field is used in both External and Internal DMA modes. In
*
* External DMA mode, these bits appear on dma_burst[3:0] ports,
*
* which can be used by an external wrapper to interface the
*
* External DMA Controller interface to Synopsys DW_ahb_dmac
*
* or ARM PrimeCell.
*
* External DMA Modedefines the DMA burst length in terms of
*
* 32-bit words:
*
* 4'b0000: 1 word
*
* 4'b0001: 4 words
*
* 4'b0010: 8 words
*
* 4'b0011: 16 words
*
* 4'b0100: 32 words
*
* 4'b0101: 64 word
*
* s
*
* 4'b0110: 128 words
*
* 4'b0111: 256 words
*
* Others: Reserved
*
* Internal DMA ModeAHB Master burst type:
*
* 4'b0000 Single
*
* 4'b0001 INCR
*
* 4'b0011 INCR4
*
* 4'b0101 INCR8
*
* 4'b0111 INCR16
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:-------------------
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE | 0x0 | 1 word or single
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR | 0x1 | 4 word or incr
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 | 0x2 | 8 word
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 | 0x3 | 16 word or incr4
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 | 0x4 | 32 word
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 | 0x5 | 64 word or incr8
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 | 0x6 | 128 word
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 | 0x7 | 256 word or incr16
* ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX | 0x8 | Others reserved
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 1 word or single
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD1ORSINGLE 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 4 word or incr
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD4ORINCR 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 8 word
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD8 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 16 word or incr4
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD16ORINCR4 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 32 word
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD32 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 64 word or incr8
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD64ORINCR8 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 128 word
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD128 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* 256 word or incr16
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORD256ORINCR16 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_HBSTLEN
*
* Others reserved
*/
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_E_WORDX 0x8
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_MSB 4
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET_MSK 0x0000001e
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_CLR_MSK 0xffffffe1
/* The reset value of the ALT_USB_GLOB_GAHBCFG_HBSTLEN register field. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_HBSTLEN field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_GET(value) (((value) & 0x0000001e) >> 1)
/* Produces a ALT_USB_GLOB_GAHBCFG_HBSTLEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_HBSTLEN_SET(value) (((value) << 1) & 0x0000001e)
/*
* Field : dmaen
*
* Mode:Host and device
*
* DMA Enable (DMAEn)
*
* 1'b0: Core operates in Slave mode
*
* 1'b1: Core operates in a DMA mode
*
* This bit is always 0 when Slave-Only mode has been selected
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD | 0x0 | Core operates in Slave mode
* ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD | 0x1 | Core operates in a DMA mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
*
* Core operates in Slave mode
*/
#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_SLVMOD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_DMAEN
*
* Core operates in a DMA mode
*/
#define ALT_USB_GLOB_GAHBCFG_DMAEN_E_DMAMOD 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_MSB 5
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_DMAEN register field value. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GAHBCFG_DMAEN register field. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_DMAEN field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GAHBCFG_DMAEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_DMAEN_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nptxfemplvl
*
* Mode:Host and device
*
* Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
*
* This bit is used only in Slave mode.
*
* In host mode and with Shared FIFO with device mode, this bit
*
* indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
*
* the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
*
* With dedicated FIFO in device mode, this bit indicates when IN
*
* endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is
*
* triggered.
*
* Host mode and with Shared FIFO with device mode:-
*
* 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
*
* Periodic TxFIFO is half empty
*
* 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
*
* Periodic TxFIFO is completely empty
*
* Dedicated FIFO in device mode :-
*
* 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN
*
* Endpoint TxFIFO is half empty
*
* 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN
*
* Endpoint TxFIFO is completely empty
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY | 0x0 | DIEPINTn.TxFEmp interrupt indicates that the IN
* : | | Endpoint TxFIFO is half empty or DIEPINTn.TxFEmp
* : | | interrupt indicates that the IN Endpoint TxFIFO
* : | | is half empty
* ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.NPTxFEmp interrupt indicates that the
* : | | Non-Periodic TxFIFO is completely empty or
* : | | DIEPINTn.TxFEmp interrupt indicates that the IN
* : | | Endpoint TxFIFO is completely empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
*
* DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty or
* DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
*/
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_HALFEMPTY 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL
*
* GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely
* empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is
* completely empty
*/
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_E_EMPTY 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_MSB 7
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : ptxfemplvl
*
* Mode:Host only
*
* Periodic TxFIFO Empty Level (PTxFEmpLvl)
*
* Indicates when the Periodic TxFIFO Empty Interrupt bit in the
*
* Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
*
* bit is used only in Slave mode.
*
* 1'b0: GINTSTS.PTxFEmp interrupt indicates that the
*
* Periodic TxFIFO is half empty
*
* 1'b1: GINTSTS.PTxFEmp interrupt indicates that the
*
* Periodic TxFIFO is completely empty
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY | 0x0 | GINTSTS.PTxFEmp interrupt indicates that the
* : | | Periodic TxFIFO is half empty
* ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY | 0x1 | GINTSTS.PTxFEmp interrupt indicates that the
* : | | Periodic TxFIFO is completely empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
*
* GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty
*/
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_HALFEMPTY 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL
*
* GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty
*/
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_E_EMPTY 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_MSB 8
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : remmemsupp
*
* Remote Memory Support (RemMemSupp)
*
* This bit is programmed to enable the functionality to wait for the system DMA
*
* Done Signal for the DMA Write Transfers.
*
* GAHBCFG.RemMemSupp=1
*
* * The int_dma_req output signal is asserted when HSOTG DMA starts
*
* write transfer to the external memory. When the core is done with the
*
* Transfers it asserts int_dma_done signal to flag the completion of DMA
*
* writes from HSOTG. The core then waits for sys_dma_done signal from
*
* the system to proceed further and complete the Data Transfer
*
* corresponding to a particular Channel/Endpoint.
*
* GAHBCFG.RemMemSupp=0
*
* * The int_dma_req and int_dma_done signals are not asserted and the
*
* core proceeds with the assertion of the XferComp interrupt as soon as
*
* the DMA write transfer is done at the HSOTG Core Boundary and it
*
* doesn't wait for the sys_dma_done signal to complete the DATA transfers
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD | 0x0 | Disable wait for system DMA Done Signal
* ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END | 0x1 | Enable wait for the system DMA Done Signal for
* : | | the DMA Write Transfers
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
*
* Disable wait for system DMA Done Signal
*/
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_REMMEMSUPP
*
* Enable wait for the system DMA Done Signal for the DMA Write Transfers
*/
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_MSB 21
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_REMMEMSUPP field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GAHBCFG_REMMEMSUPP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_REMMEMSUPP_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : notialldmawrit
*
* Notify All Dma Write Transactions (NotiAllDmaWrit)
*
* This bit is programmed to enable the System DMA Done functionality for all
*
* the DMA write Transactions corresponding to the Channel/Endpoint. This bit
*
* is valid only when GAHBCFG.RemMemSupp is set to 1.
*
* GAHBCFG.NotiAllDmaWrit = 1
*
* * HSOTG core asserts int_dma_req for all the DMA write transactions on
*
* the AHB interface along with int_dma_done, chep_last_transact and
*
* chep_number signal informations. The core waits for sys_dma_done
*
* signal for all the DMA write transactions in order to complete the transfer
*
* of a particular Channel/Endpoint.
*
* GAHBCFG.NotiAllDmaWrit = 0
*
* * HSOTG core asserts int_dma_req signal only for the last transaction of
*
* DMA write transfer corresponding to a particular Channel/Endpoint.
*
* Similarly, the core waits for sys_dma_done signal only for that
*
* transaction of DMA write to complete the transfer of a particular
*
* Channel/Endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS | 0x0 | HSOTG core asserts int_dma_req signal only for
* : | | the last transaction of DMA write transfer
* : | | corresponding to a particular Channel/Endpoint.
* : | | Similarly, the core waits for sys_dma_done
* : | | signal only for that transaction of DMA write to
* : | | complete the transfer of a particular
* : | | Channel/Endpoint
* ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS | 0x1 | HSOTG core asserts int_dma_req for all the DMA
* : | | write transactions on the AHB interface along
* : | | with int_dma_done, chep_last_transact and
* : | | chep_number signal informations. The core waits
* : | | for sys_dma_done signal for all the DMA write
* : | | transactions in order to complete the transfer
* : | | of a particular Channel/Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
*
* HSOTG core asserts int_dma_req signal only for the last transaction of DMA write
* transfer corresponding to a particular Channel/Endpoint. Similarly, the core
* waits for sys_dma_done signal only for that transaction of DMA write to complete
* the transfer of a particular Channel/Endpoint
*/
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_LASTTRANS 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT
*
* HSOTG core asserts int_dma_req for all the DMA write transactions on the AHB
* interface along with int_dma_done, chep_last_transact and chep_number signal
* informations. The core waits for sys_dma_done signal for all the DMA write
* transactions in order to complete the transfer of a particular Channel/Endpoint
*/
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_E_ALLTRANS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_MSB 22
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : ahbsingle
*
* AHB Single Support (AHBSingle)
*
* This bit when programmed supports Single transfers for the remaining data in a
*
* transfer when the DWC_otg core is operating in DMA mode.
*
* 1'b0: This is the default mode. When this bit is set to 1'b0,
*
* the remaining data in the transfer is sent using INCR burst size.
*
* 1'b1: When set to 1'b1, the remaining data in a transfer is sent using Single
*
* burst size.
*
* Note: if this feature is enabled, the AHB RETRY and SPLIT transfers still have
* INCR
*
* burst type. Enable this feature when the AHB Slave connected to the DWC_otg core
* does
*
* not support INCR burst (and when Split, and Retry transactions are not being
* used
*
* in the bus).
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_MSB 23
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_AHBSINGLE field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GAHBCFG_AHBSINGLE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_AHBSINGLE_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : invdescendianess
*
* Invert Descriptor Endianess (InvDescEndianess)
*
* 1’b0: Descriptor Endianness is same as AHB Master Endianness
*
* 1’b1: Descriptor Endianness is Little Endian if AHB Master Endianness is Big
* Endian.
*
* Descriptor Endianness is Big Endian if AHB Master Endianness is Little Endian.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_MSB 24
/* The width in bits of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS field value from a register. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS_SET(value) (((value) << 24) & 0x01000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GAHBCFG.
*/
struct ALT_USB_GLOB_GAHBCFG_s
{
uint32_t glblintrmsk : 1; /* ALT_USB_GLOB_GAHBCFG_GLBLINTRMSK */
uint32_t hbstlen : 4; /* ALT_USB_GLOB_GAHBCFG_HBSTLEN */
uint32_t dmaen : 1; /* ALT_USB_GLOB_GAHBCFG_DMAEN */
uint32_t : 1; /* *UNDEFINED* */
uint32_t nptxfemplvl : 1; /* ALT_USB_GLOB_GAHBCFG_NPTXFEMPLVL */
uint32_t ptxfemplvl : 1; /* ALT_USB_GLOB_GAHBCFG_PTXFEMPLVL */
uint32_t : 12; /* *UNDEFINED* */
uint32_t remmemsupp : 1; /* ALT_USB_GLOB_GAHBCFG_REMMEMSUPP */
uint32_t notialldmawrit : 1; /* ALT_USB_GLOB_GAHBCFG_NOTIALLDMAWRIT */
uint32_t ahbsingle : 1; /* ALT_USB_GLOB_GAHBCFG_AHBSINGLE */
uint32_t invdescendianess : 1; /* ALT_USB_GLOB_GAHBCFG_INVDESCENDIANESS */
uint32_t : 7; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GAHBCFG. */
typedef volatile struct ALT_USB_GLOB_GAHBCFG_s ALT_USB_GLOB_GAHBCFG_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GAHBCFG register. */
#define ALT_USB_GLOB_GAHBCFG_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GAHBCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GAHBCFG_OFST 0x8
/* The address of the ALT_USB_GLOB_GAHBCFG register. */
#define ALT_USB_GLOB_GAHBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GAHBCFG_OFST))
/*
* Register : gusbcfg
*
* USB Configuration Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------------
* [2:0] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TOUTCAL
* [3] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_PHYIF
* [4] | R | 0x1 | ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL
* [5] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_FSINTF
* [6] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_PHYSEL
* [7] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_DDRSEL
* [8] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_SRPCAP
* [9] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_HNPCAP
* [13:10] | RW | 0x5 | ALT_USB_GLOB_GUSBCFG_USBTRDTIM
* [17:14] | ??? | 0x0 | *UNDEFINED*
* [18] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
* [19] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
* [20] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
* [21] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
* [22] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
* [23] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_COMPLEMENT
* [24] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_INDICATOR
* [25] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_ULPI
* [26] | R | 0x0 | ALT_USB_GLOB_GUSBCFG_IC_USBCAP
* [27] | ??? | 0x0 | *UNDEFINED*
* [28] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_TXENDDELAY
* [29] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
* [30] | RW | 0x0 | ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
* [31] | W | 0x0 | ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
*
*/
/*
* Field : toutcal
*
* Mode:Host and Device
*
* HS/FS Timeout Calibration (TOutCal)
*
* The number of PHY clocks that the application programs in this
*
* field is added to the high-speed/full-speed interpacket timeout
*
* duration in the core to account For any additional delays
*
* introduced by the PHY. This can be required, because the delay
*
* introduced by the PHY in generating the linestate condition can
*
* vary from one PHY to another.
*
* The USB standard timeout value For high-speed operation is 736
*
* to 816 (inclusive) bit times. The USB standard timeout value For
*
* full-speed operation is 16 to 18 (inclusive) bit times. The
*
* application must program this field based on the speed of
*
* enumeration. The number of bit times added per PHY clock are:
*
* High-speed operation:
*
* One 30-MHz PHY clock = 16 bit times
*
* One 60-MHz PHY clock = 8 bit times
*
* Full-speed operation:
*
* One 30-MHz PHY clock = 0.4 bit times
*
* One 60-MHz PHY clock = 0.2 bit times
*
* One 48-MHz PHY clock = 0.25 bit times
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_MSB 2
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_WIDTH 3
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET_MSK 0x00000007
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_CLR_MSK 0xfffffff8
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TOUTCAL register field. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TOUTCAL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_GET(value) (((value) & 0x00000007) >> 0)
/* Produces a ALT_USB_GLOB_GUSBCFG_TOUTCAL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TOUTCAL_SET(value) (((value) << 0) & 0x00000007)
/*
* Field : phyif
*
* Mode:Host and Device
*
* PHY Interface (PHYIf)
*
* The application uses this bit to configure the core To support a
*
* UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is
*
* chosen, this must be Set to 8-bit mode.
*
* 1'b0: 8 bits
*
* 1'b1: 16 bits
*
* This bit is writable only If UTMI+ and ULPI were selected
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------
* ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 | 0x0 | PHY 8bit Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYIF
*
* PHY 8bit Mode
*/
#define ALT_USB_GLOB_GUSBCFG_PHYIF_E_BITS8 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_MSB 3
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYIF register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYIF register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYIF field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GUSBCFG_PHYIF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_PHYIF_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : ulpi_utmi_sel
*
* Mode:Host and Device
*
* ULPI or UTMI+ Select (ULPI_UTMI_Sel)
*
* The application uses this bit to select either a UTMI+ interface or
*
* ULPI Interface.
*
* 1'b0: UTMI+ Interface
*
* 1'b1: ULPI Interface
*
* This bit is writable only If UTMI+ and ULPI was specified For
*
* High-Speed PHY Interface(s).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI | 0x0 | ULPI PHY
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL
*
* ULPI PHY
*/
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_E_ULPI 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_MSB 4
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x1
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : fsintf
*
* Mode:Host and Device
*
* Full-Speed Serial Interface Select (FSIntf)
*
* The application uses this bit to select either a unidirectional or
*
* bidirectional USB 1.1 full-speed serial transceiver interface.
*
* 1'b0: 6-pin unidirectional full-speed serial interface
*
* 1'b1: 3-pin bidirectional full-speed serial interface
*
* If a USB 1.1 Full-Speed Serial Transceiver interface was not
*
* selected, this bit is always 0, with Write
*
* Only access. If a USB 1.1 FS interface was selected, Then the
*
* application can Set this bit to select between the 3- and 6-pin
*
* interfaces, and access is Read and Write.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN | 0x0 | 6-pin unidirectional full-speed serial interface
* ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN | 0x1 | 3-pin bidirectional full-speed serial interface
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
*
* 6-pin unidirectional full-speed serial interface
*/
#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS6PIN 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FSINTF
*
* 3-pin bidirectional full-speed serial interface
*/
#define ALT_USB_GLOB_GUSBCFG_FSINTF_E_FS3PIN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_MSB 5
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FSINTF register field value. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FSINTF register field. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FSINTF field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GUSBCFG_FSINTF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FSINTF_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : physel
*
* Mode:Host and Device
*
* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
*
* Transceiver Select (PHYSel)
*
* The application uses this bit to select either a high-speed UTMI+
*
* or ULPI PHY, or a full-speed transceiver.
*
* 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
*
* 1'b1: USB 1.1 full-speed serial transceiver
*
* If a USB 1.1 Full-Speed Serial Transceiver interface was not
*
* selected in, this bit is always 0, with Write Only access.
*
* If a high-speed PHY interface was not selected in,
*
* this bit is always 1, with Write Only access.
*
* If both interface types were selected (parameters have non-zero values),
*
* the application uses this bit to select which interface is active,
*
* and access is Read and Write.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 | 0x0 | USB 2.0 high-speed ULPI
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_PHYSEL
*
* USB 2.0 high-speed ULPI
*/
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_E_USB20 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_MSB 6
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_PHYSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_GLOB_GUSBCFG_PHYSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_PHYSEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GUSBCFG_PHYSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_PHYSEL_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : ddrsel
*
* Mode:Host and Device
*
* ULPI DDR Select (DDRSel)
*
* The application uses this bit to select a Single Data Rate (SDR)
*
* or Double Data Rate (DDR) or ULPI interface.
*
* 1'b0: Single Data Rate ULPI Interface, with 8-bit-wide data
*
* bus
*
* 1'b1: Double Data Rate ULPI Interface, with 4-bit-wide data
*
* bus
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR | 0x0 | Single Data Rate ULPI Interfacewith 8-bit-wide
* : | | data bus
* ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR | 0x1 | Double Data Rate ULPI Interface, with 4-bit-wide
* : | | data bus
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
*
* Single Data Rate ULPI Interfacewith 8-bit-wide data bus
*/
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_SDR 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_DDRSEL
*
* Double Data Rate ULPI Interface, with 4-bit-wide data bus
*/
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_E_DDR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_MSB 7
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_DDRSEL register field value. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GUSBCFG_DDRSEL register field. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_DDRSEL field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GUSBCFG_DDRSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_DDRSEL_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : srpcap
*
* Mode:Host and Device
*
* SRP-Capable (SRPCap)
*
* The application uses this bit to control the DWC_otg core SRP
*
* capabilities. If the core operates as a non-SRP-capable
*
* B-device, it cannot request the connected A-device (host) to
*
* activate VBUS and start a session.
*
* 1'b0: SRP capability is not enabled.
*
* 1'b1: SRP capability is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------------
* ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD | 0x0 | SRP capability is not enabled
* ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END | 0x1 | SRP capability is enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
*
* SRP capability is not enabled
*/
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_SRPCAP
*
* SRP capability is enabled
*/
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_MSB 8
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_SRPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_SRPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_SRPCAP field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GUSBCFG_SRPCAP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_SRPCAP_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : hnpcap
*
* Mode:Host and Device
*
* HNP-Capable (HNPCap)
*
* The application uses this bit to control the DWC_otg core's HNP
*
* capabilities.
*
* 1'b0: HNP capability is not enabled.
*
* 1'b1: HNP capability is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------
* ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD | 0x0 | HNP capability is not enabled.
* ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END | 0x1 | HNP capability is enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
*
* HNP capability is not enabled.
*/
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_HNPCAP
*
* HNP capability is enabled
*/
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_MSB 9
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_HNPCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_HNPCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_HNPCAP field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GUSBCFG_HNPCAP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_HNPCAP_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : usbtrdtim
*
* Mode: Device only
*
* USB Turnaround Time (USBTrdTim)
*
* Sets the turnaround time in PHY clocks.
*
* Specifies the response time For a MAC request to the Packet
*
* FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
*
* This must be programmed to
*
* 4'h5: When the MAC interface is 16-bit UTMI+ .
*
* 4'h9: When the MAC interface is 8-bit UTMI+ .
*
* Note: The values above are calculated For the minimum AHB
*
* frequency of 30 MHz. USB turnaround time is critical For
*
* certification where long cables and 5-Hubs are used, so If you
*
* need the AHB to run at less than 30 MHz, and If USB turnaround
*
* time is not critical, these bits can be programmed to a larger
*
* value.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------------
* ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME | 0x9 | MAC interface is 8-bit UTMI+.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_USBTRDTIM
*
* MAC interface is 8-bit UTMI+.
*/
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_E_TURNTIME 0x9
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_MSB 13
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET_MSK 0x00003c00
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_CLR_MSK 0xffffc3ff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_RESET 0x5
/* Extracts the ALT_USB_GLOB_GUSBCFG_USBTRDTIM field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_GET(value) (((value) & 0x00003c00) >> 10)
/* Produces a ALT_USB_GLOB_GUSBCFG_USBTRDTIM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_USBTRDTIM_SET(value) (((value) << 10) & 0x00003c00)
/*
* Field : ulpiautores
*
* Mode:Host and Device
*
* ULPI Auto Resume (ULPIAutoRes)
*
* This bit sets the AutoResume bit in the Interface Control register
*
* on the ULPI PHY.
*
* 1'b0: PHY does not use AutoResume feature.
*
* 1'b1: PHY uses AutoResume feature.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD | 0x0 | PHY does not use AutoResume feature
* ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END | 0x1 | PHY uses AutoResume feature
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
*
* PHY does not use AutoResume feature
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIAUTORES
*
* PHY uses AutoResume feature
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_MSB 18
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIAUTORES field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIAUTORES register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIAUTORES_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : ulpiclksusm
*
* Mode:Host and Device
*
* ULPI Clock SuspendM (ULPIClkSusM)
*
* This bit sets the ClockSuspendM bit in the Interface Control
*
* register on the ULPI PHY. This bit applies only in serial or carkit
*
* modes.
*
* 1'b0: PHY powers down internal clock during suspend.
*
* 1'b1: PHY does not power down internal clock.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:----------------------------------------------
* ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK | 0x0 | PHY powers down internal clock during suspend
* ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK | 0x1 | PHY does not power down internal clock
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
*
* PHY powers down internal clock during suspend
*/
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_PWDCLK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM
*
* PHY does not power down internal clock
*/
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_E_NONPWDCLK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_MSB 19
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : ulpiextvbusdrv
*
* Mode:Host only
*
* ULPI External VBUS Drive (ULPIExtVbusDrv)
*
* This bit selects between internal or external supply to drive 5V
*
* on VBUS, in ULPI PHY.
*
* 1'b0: PHY drives VBUS using internal charge pump (Default).
*
* 1'b1: PHY drives VBUS using external supply.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:-------------------------------------------
* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN | 0x0 | PHY drives VBUS using internal charge pump
* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN | 0x1 | PHY drives VBUS using external supply
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
*
* PHY drives VBUS using internal charge pump
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_INTERN 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV
*
* PHY drives VBUS using external supply
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_E_EXTERN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_MSB 20
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : ulpiextvbusindicator
*
* Mode:Host only
*
* ULPI External VBUS Indicator (ULPIExtVbusIndicator)
*
* This bit indicates to the ULPI PHY to use an external VBUS overcurrent
*
* indicator.
*
* 1'b0: PHY uses internal VBUS valid comparator.
*
* 1'b1: PHY uses external VBUS valid comparator.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:----------------------------------------
* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN | 0x0 | PHY uses internal VBUS valid comparator
* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN | 0x1 | PHY uses external VBUS valid comparator
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
*
* PHY uses internal VBUS valid comparator
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_INTERN 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR
*
* PHY uses external VBUS valid comparator
*/
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_E_EXTERN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_MSB 21
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : termseldlpulse
*
* Mode:Device only
*
* TermSel DLine Pulsing Selection (TermSelDLPulse)
*
* This bit selects utmi_termselect to drive data line pulse during
*
* SRP.
*
* 1'b0: Data line pulsing using utmi_txvalid (Default).
*
* 1'b1: Data line pulsing using utmi_termsel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:-------------------------------------
* ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID | 0x0 | Data line pulsing using utmi_txvalid
* ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL | 0x1 | Data line pulsing using utmi_termsel
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
*
* Data line pulsing using utmi_txvalid
*/
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TXVALID 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE
*
* Data line pulsing using utmi_termsel
*/
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_E_TERMSEL 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_MSB 22
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : complement
*
* Mode:Host only
*
* Indicator Complement
*
* Controls the PHY to invert the ExternalVbusIndicator input
*
* signal, generating the Complement
*
* Output. Please refer to the ULPI Spec For more detail
*
* 1'b0: PHY does not invert ExternalVbusIndicator signal
*
* 1'b1: PHY does invert ExternalVbusIndicator signal
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT | 0x0 | PHY does not invert ExternalVbusIndicator signal
* ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT | 0x1 | PHY does invert ExternalVbusIndicator signal
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
*
* PHY does not invert ExternalVbusIndicator signal
*/
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_NONINVERT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_COMPLEMENT
*
* PHY does invert ExternalVbusIndicator signal
*/
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_E_INVERT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_MSB 23
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_COMPLEMENT field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GUSBCFG_COMPLEMENT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_COMPLEMENT_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : indicator
*
* Mode:Host only
*
* Indicator Pass Through
*
* Controls wether the Complement Output is qualified with the
*
* Internal Vbus Valid comparator before being used
*
* in the Vbus State in the RX CMD. Please refer to the ULPI Spec
*
* for more detail.
*
* 1'b0: Complement Output signal is qualified with the Internal
*
* VbusValid comparator.
*
* 1'b1: Complement Output signal is not qualified with the
*
* Internal VbusValid comparator.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED | 0x0 | Complement Output signal is qualified with the
* : | | Internal VbusValid comparator
* ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED | 0x1 | Complement Output signal is not qualified with
* : | | the Internal VbusValid comparator
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
*
* Complement Output signal is qualified with the Internal VbusValid comparator
*/
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_QUALIFIED 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_INDICATOR
*
* Complement Output signal is not qualified with the Internal VbusValid
* comparator
*/
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_E_NONQUALIFIED 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_MSB 24
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_INDICATOR register field value. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_INDICATOR register field. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_INDICATOR field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GUSBCFG_INDICATOR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_INDICATOR_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : ulpi
*
* Mode:Host only
*
* ULPI Interface Protect Disable
*
* Controls circuitry built into the PHY For protecting the ULPI
*
* interface when the link tri-states STP and data.
*
* Any pull-ups or pull-downs employed by this feature can be
*
* disabled. Please refer to the ULPI Specification For more detail.
*
* 1'b0: Enables the interface protect circuit
*
* 1'b1: Disables the interface protect circuit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:---------------------------------------
* ALT_USB_GLOB_GUSBCFG_ULPI_E_END | 0x0 | Enables the interface protect circuit
* ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD | 0x1 | Disables the interface protect circuit
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
*
* Enables the interface protect circuit
*/
#define ALT_USB_GLOB_GUSBCFG_ULPI_E_END 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_ULPI
*
* Disables the interface protect circuit
*/
#define ALT_USB_GLOB_GUSBCFG_ULPI_E_DISD 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_MSB 25
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_ULPI register field value. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_ULPI register field. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_ULPI field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GUSBCFG_ULPI register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_ULPI_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : ic_usbcap
*
* IC_USB-Capable (IC_USBCap)
*
* The application uses this bit to control the DWC_otg core's IC_USB
*
* capabilities.
*
* 1'b0: IC_USB PHY Interface is not selected.
*
* 1'b1: IC_USB PHY Interface is selected.
*
* This bit is writable only if IC_USB is selected
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_MSB 26
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_IC_USBCAP field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GUSBCFG_IC_USBCAP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_IC_USBCAP_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : txenddelay
*
* Mode: Device only
*
* Tx End Delay (TxEndDelay)
*
* Writing 1'b1 to this bit enables the core to follow the TxEndDelay timings as
* per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote
* wakeup.
*
* 1'b0 : Normal Mode.
*
* 1'b1 : Tx End delay.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------
* ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD | 0x0 | Normal Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_TXENDDELAY
*
* Normal Mode
*/
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_MSB 28
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_TXENDDELAY field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GUSBCFG_TXENDDELAY register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_TXENDDELAY_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : forcehstmode
*
* Mode:Host and device
*
* Force Host Mode (ForceHstMode)
*
* Writing a 1 to this bit forces the core to host mode irrespective of
*
* utmiotg_iddig input pin.
*
* 1'b0 : Normal Mode.
*
* 1'b1 : Force Host Mode.
*
* After setting the force bit, the application must wait at least 25 ms before
*
* the change to take effect. When the simulation is in scale down mode,
*
* waiting for 500 micro sec is sufficient.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------
* ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD | 0x0 | Normal Mode
* ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END | 0x1 | Force Host Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
*
* Normal Mode
*/
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD
*
* Force Host Mode
*/
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_MSB 29
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : forcedevmode
*
* Mode:Host and device
*
* Force Device Mode (ForceDevMode)
*
* Writing a 1 to this bit forces the core to device mode irrespective
*
* of utmiotg_iddig input pin.
*
* 1'b0 : Normal Mode.
*
* 1'b1 : Force Device Mode.
*
* After setting the force bit, the application must wait at least 25 ms before
*
* the change to take effect. When the simulation is in scale down mode,
*
* waiting for 500 micro sec is sufficient.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------
* ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD | 0x0 | Normal Mode
* ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END | 0x1 | Force Device Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
*
* Normal Mode
*/
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD
*
* Force Device Mode
*/
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_MSB 30
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : corrupttxpkt
*
* Mode:Host and device
*
* Corrupt Tx packet
*
* This bit is FOr debug purposes only. Never Set this bit to 1.The application
* should always write 1'b0 to this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG | 0x0 | Normal Mode
* ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG | 0x1 | Debug Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
*
* Normal Mode
*/
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_NODBG 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT
*
* Debug Mode
*/
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_E_DBG 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_MSB 31
/* The width in bits of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT field value from a register. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GUSBCFG.
*/
struct ALT_USB_GLOB_GUSBCFG_s
{
uint32_t toutcal : 3; /* ALT_USB_GLOB_GUSBCFG_TOUTCAL */
const uint32_t phyif : 1; /* ALT_USB_GLOB_GUSBCFG_PHYIF */
const uint32_t ulpi_utmi_sel : 1; /* ALT_USB_GLOB_GUSBCFG_ULPI_UTMI_SEL */
const uint32_t fsintf : 1; /* ALT_USB_GLOB_GUSBCFG_FSINTF */
const uint32_t physel : 1; /* ALT_USB_GLOB_GUSBCFG_PHYSEL */
uint32_t ddrsel : 1; /* ALT_USB_GLOB_GUSBCFG_DDRSEL */
uint32_t srpcap : 1; /* ALT_USB_GLOB_GUSBCFG_SRPCAP */
uint32_t hnpcap : 1; /* ALT_USB_GLOB_GUSBCFG_HNPCAP */
uint32_t usbtrdtim : 4; /* ALT_USB_GLOB_GUSBCFG_USBTRDTIM */
uint32_t : 4; /* *UNDEFINED* */
uint32_t ulpiautores : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIAUTORES */
uint32_t ulpiclksusm : 1; /* ALT_USB_GLOB_GUSBCFG_ULPICLKSUSM */
uint32_t ulpiextvbusdrv : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSDRV */
uint32_t ulpiextvbusindicator : 1; /* ALT_USB_GLOB_GUSBCFG_ULPIEXTVBUSINDICATOR */
uint32_t termseldlpulse : 1; /* ALT_USB_GLOB_GUSBCFG_TERMSELDLPULSE */
uint32_t complement : 1; /* ALT_USB_GLOB_GUSBCFG_COMPLEMENT */
uint32_t indicator : 1; /* ALT_USB_GLOB_GUSBCFG_INDICATOR */
uint32_t ulpi : 1; /* ALT_USB_GLOB_GUSBCFG_ULPI */
const uint32_t ic_usbcap : 1; /* ALT_USB_GLOB_GUSBCFG_IC_USBCAP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t txenddelay : 1; /* ALT_USB_GLOB_GUSBCFG_TXENDDELAY */
uint32_t forcehstmode : 1; /* ALT_USB_GLOB_GUSBCFG_FORCEHSTMOD */
uint32_t forcedevmode : 1; /* ALT_USB_GLOB_GUSBCFG_FORCEDEVMOD */
uint32_t corrupttxpkt : 1; /* ALT_USB_GLOB_GUSBCFG_CORRUPTTXPKT */
};
/* The typedef declaration for register ALT_USB_GLOB_GUSBCFG. */
typedef volatile struct ALT_USB_GLOB_GUSBCFG_s ALT_USB_GLOB_GUSBCFG_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GUSBCFG register. */
#define ALT_USB_GLOB_GUSBCFG_RESET 0x00001410
/* The byte offset of the ALT_USB_GLOB_GUSBCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GUSBCFG_OFST 0xc
/* The address of the ALT_USB_GLOB_GUSBCFG register. */
#define ALT_USB_GLOB_GUSBCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUSBCFG_OFST))
/*
* Register : grstctl
*
* Reset Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:---------------------------------
* [0] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_CSFTRST
* [1] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST
* [2] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
* [3] | ??? | 0x0 | *UNDEFINED*
* [4] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_RXFFLSH
* [5] | R-W once | 0x0 | ALT_USB_GLOB_GRSTCTL_TXFFLSH
* [10:6] | RW | 0x0 | ALT_USB_GLOB_GRSTCTL_TXFNUM
* [29:11] | ??? | 0x0 | *UNDEFINED*
* [30] | R | 0x0 | ALT_USB_GLOB_GRSTCTL_DMAREQ
* [31] | R | 0x1 | ALT_USB_GLOB_GRSTCTL_AHBIDLE
*
*/
/*
* Field : csftrst
*
* Mode:Host and Device
*
* Core Soft Reset (CSftRst)
*
* Resets the hclk and phy_clock domains as follows:
*
* Clears the interrupts and all the CSR registers except the
*
* following register bits:
*
* * PCGCCTL.RstPdwnModule
*
* * PCGCCTL.GateHclk
*
* * PCGCCTL.PwrClmp
*
* * PCGCCTL.StopPPhyLPwrClkSelclk
*
* * GUSBCFG.PhyLPwrClkSel
*
* * GUSBCFG.DDRSel
*
* * GUSBCFG.PHYSel
*
* * GUSBCFG.FSIntf
*
* * GUSBCFG.ULPI_UTMI_Sel
*
* * GUSBCFG.PHYIf
*
* * GUSBCFG.TxEndDelay
*
* * GUSBCFG.TermSelDLPulse
*
* * GUSBCFG.ULPIClkSusM
*
* * GUSBCFG.ULPIAutoRes
*
* * GUSBCFG.ULPIFsLs
*
* * GGPIO
*
* * GPWRDN
*
* * GADPCTL
*
* * HCFG.FSLSPclkSel
*
* * DCFG.DevSpd
*
* * DCTL.SftDiscon
*
* * All module state machines
*
* All module state machines (except the AHB Slave Unit) are
*
* reset to the IDLE state, and all the transmit FIFOs and the
*
* receive FIFO are flushed.
*
* Any transactions on the AHB Master are terminated as soon
*
* as possible, after gracefully completing the last data phase of
*
* an AHB transfer. Any transactions on the USB are terminated
*
* immediately.
*
* When Hibernation or ADP feature is enabled, the PMU module is not
*
* reset by the Core Soft Reset.
*
* The application can write to this bit any time it wants to reset the
*
* core. This is a self-clearing bit and the core clears this bit after
*
* all the necessary logic is reset in the core, which can take
*
* several clocks, depending on the current state of the core. Once
*
* this bit is cleared software must wait at least 3 PHY clocks
*
* before doing any access to the PHY domain (synchronization
*
* delay). Software must also must check that bit 31 of this register
*
* is 1 (AHB Master is IDLE) before starting any operation.
*
* Typically software reset is used during software development
*
* and also when you dynamically change the PHY selection bits in
*
* the USB configuration registers listed above. When you change
*
* the PHY, the corresponding clock For the PHY is selected and
*
* used in the PHY domain. Once a new clock is selected, the PHY
*
* domain has to be reset for proper operation.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------
* ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT | 0x0 | No reset
* ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT | 0x1 | Resets hclk and phy_clock domains
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
*
* No reset
*/
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST
*
* Resets hclk and phy_clock domains
*/
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB 0
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_CSFTRST field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GRSTCTL_CSFTRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : piufssftrst
*
* Mode:Host and Device
*
* PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)
*
* Resets the PIU FS Dedicated Controller
*
* All module state machines in FS Dedicated Controller of PIU are
*
* reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in
* case of any PHY Errors like Loss of activity or Babble Error resulting in the
* PHY remaining in RX state for more than one frame boundary
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_MSB 1
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : frmcntrrst
*
* Mode:Host only
*
* Host Frame Counter Reset (FrmCntrRst)
*
* The application writes this bit to reset the (micro)frame number
*
* counter inside the core. When the (micro)frame counter is reset,
*
* the subsequent SOF sent out by the core has a (micro)frame
*
* number of 0.When application writes 1 to the bit, it might not
*
* be able to read back the value as it will get cleared by the core in a few clock
* cycles.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------
* ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT | 0x0 | No reset
* ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT | 0x1 | Host Frame Counter Reset
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
*
* No reset
*/
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST
*
* Host Frame Counter Reset
*/
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB 2
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : rxfflsh
*
* Mode:Host and Device
*
* RxFIFO Flush (RxFFlsh)
*
* The application can flush the entire RxFIFO using this bit, but
*
* must first ensure that the core is not in the middle of a
*
* transaction.
*
* The application must only write to this bit after checking that the
*
* core is neither reading from the RxFIFO nor writing to the
*
* RxFIFO.
*
* The application must wait until the bit is cleared before
*
* performing any other operations. This bit requires 8 clocks
*
* (slowest of PHY or AHB clock) to clear.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT | 0x0 | no flush the entire RxFIFO
* ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT | 0x1 | flush the entire RxFIFO
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
*
* no flush the entire RxFIFO
*/
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH
*
* flush the entire RxFIFO
*/
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB 4
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_RXFFLSH field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : txfflsh
*
* Mode:Host and Device
*
* TxFIFO Flush (TxFFlsh)
*
* This bit selectively flushes a single or all transmit FIFOs, but
*
* cannot do so If the core is in the midst of a transaction.
*
* The application must write this bit only after checking that the
*
* core is neither writing to the TxFIFO nor reading from the
*
* TxFIFO. Verify using these registers:
*
* ReadNAK Effective Interrupt ensures the core is not
*
* reading from the FIFO
*
* WriteGRSTCTL.AHBIdle ensures the core is not writing
*
* anything to the FIFO.
*
* Flushing is normally recommended when FIFOs are
*
* reconfigured or when switching between Shared FIFO and
*
* Dedicated Transmit FIFO operation. FIFO flushing is also
*
* recommended during device endpoint disable.
*
* The application must wait until the core clears this bit before
*
* performing any operations. This bit takes eight clocks to clear,
*
* using the slower clock of phy_clk or hclk.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT | 0x0 | No Flush
* ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT | 0x1 | selectively flushes a single or all transmit
* : | | FIFOs
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
*
* No Flush
*/
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH
*
* selectively flushes a single or all transmit FIFOs
*/
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB 5
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFFLSH field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : txfnum
*
* Mode:Host and Device
*
* TxFIFO Number (TxFNum)
*
* This is the FIFO number that must be flushed using the TxFIFO
*
* Flush bit. This field must not be changed until the core clears the
*
* TxFIFO Flush bit.
*
* 5'h0:
*
* * Non-periodic TxFIFO flush in Host mode
*
* * Non-periodic TxFIFO flush in device mode when in shared
*
* FIFO operation
*
* * Tx FIFO 0 flush in device mode when in dedicated FIFO
*
* mode
*
* 5'h1:
*
* * Periodic TxFIFO flush in Host mode
*
* * Periodic TxFIFO 1 flush in Device mode when in shared
*
* FIFO operation
*
* * TXFIFO 1 flush in device mode when in dedicated FIFO
*
* mode
*
* 5'h2:
*
* * Periodic TxFIFO 2 flush in Device mode when in shared
*
* FIFO operation
*
* * TXFIFO 2 flush in device mode when in dedicated FIFO
*
* mode
*
* ...
*
* 5'hF:
*
* * Periodic TxFIFO 15 flush in Device mode when in shared
*
* FIFO operation
*
* * TXFIFO 15 flush in device mode when in dedicated FIFO
*
* mode
*
* 5'h10: Flush all the transmit FIFOs in device or host mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 | 0x0 | - Non-periodic TxFIFO flush in Host mode - Non-
* : | | periodic TxFIFO flush in device mode when in
* : | | shared FIFO operation
* ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 | 0x1 | - Periodic TxFIFO flush in Host mode - Periodic
* : | | TxFIFO 1 flush in Device mode when in sharedFIFO
* : | | operation
* ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 | 0x2 | - Periodic TxFIFO 2 flush in Device mode when in
* : | | sharedFIFO operation- TXFIFO 2 flush in device
* : | | mode when in dedicated FIFO mode
* ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 | 0xf | - Periodic TxFIFO 15 flush in Device mode when
* : | | in shared FIFO operation - TXFIFO 15 flush in
* : | | device mode when in dedicated FIFO mode
* ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 | 0x10 | Flush all the transmit FIFOs in device or host
* : | | mode.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
*
* * Non-periodic TxFIFO flush in Host mode
*
* * Non-periodic TxFIFO flush in device mode when in shared FIFO operation
*/
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
*
* * Periodic TxFIFO flush in Host mode
*
* * Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation
*/
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
*
* * Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2
* flush in device mode when in dedicated FIFO mode
*/
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
*
* * Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation
*
* * TXFIFO 15 flush in device mode when in dedicated FIFO mode
*/
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 0xf
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM
*
* Flush all the transmit FIFOs in device or host mode.
*/
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 0x10
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB 10
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH 5
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK 0x000007c0
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK 0xfffff83f
/* The reset value of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_TXFNUM field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_USB_GLOB_GRSTCTL_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET(value) (((value) << 6) & 0x000007c0)
/*
* Field : dmareq
*
* Mode:Host and Device
*
* DMA Request Signal (DMAReq)
*
* Indicates that the DMA request is in progress. Used For debug.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT | 0x0 | No DMA request
* ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT | 0x1 | DMA request is in progress
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
*
* No DMA request
*/
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ
*
* DMA request is in progress
*/
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB 30
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRSTCTL_DMAREQ field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GRSTCTL_DMAREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : ahbidle
*
* Mode:Host and Device
*
* AHB Master Idle (AHBIdle)
*
* Indicates that the AHB Master State Machine is in the IDLE
*
* condition.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------
* ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT | 0x0 | Not Idle
* ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT | 0x1 | AHB Master Idle
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
*
* Not Idle
*/
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE
*
* AHB Master Idle
*/
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB 31
/* The width in bits of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET 0x1
/* Extracts the ALT_USB_GLOB_GRSTCTL_AHBIDLE field value from a register. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GRSTCTL.
*/
struct ALT_USB_GLOB_GRSTCTL_s
{
uint32_t csftrst : 1; /* ALT_USB_GLOB_GRSTCTL_CSFTRST */
uint32_t piufssftrst : 1; /* ALT_USB_GLOB_GRSTCTL_PIUFSSFTRST */
uint32_t frmcntrrst : 1; /* ALT_USB_GLOB_GRSTCTL_FRMCNTRRST */
uint32_t : 1; /* *UNDEFINED* */
uint32_t rxfflsh : 1; /* ALT_USB_GLOB_GRSTCTL_RXFFLSH */
uint32_t txfflsh : 1; /* ALT_USB_GLOB_GRSTCTL_TXFFLSH */
uint32_t txfnum : 5; /* ALT_USB_GLOB_GRSTCTL_TXFNUM */
uint32_t : 19; /* *UNDEFINED* */
const uint32_t dmareq : 1; /* ALT_USB_GLOB_GRSTCTL_DMAREQ */
const uint32_t ahbidle : 1; /* ALT_USB_GLOB_GRSTCTL_AHBIDLE */
};
/* The typedef declaration for register ALT_USB_GLOB_GRSTCTL. */
typedef volatile struct ALT_USB_GLOB_GRSTCTL_s ALT_USB_GLOB_GRSTCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GRSTCTL register. */
#define ALT_USB_GLOB_GRSTCTL_RESET 0x80000000
/* The byte offset of the ALT_USB_GLOB_GRSTCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GRSTCTL_OFST 0x10
/* The address of the ALT_USB_GLOB_GRSTCTL register. */
#define ALT_USB_GLOB_GRSTCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST))
/*
* Register : gintsts
*
* Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :------|:-------|:------|:----------------------------------
* [0] | R | 0x0 | ALT_USB_GLOB_GINTSTS_CURMOD
* [1] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_MODMIS
* [2] | R | 0x0 | ALT_USB_GLOB_GINTSTS_OTGINT
* [3] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_SOF
* [4] | R | 0x0 | ALT_USB_GLOB_GINTSTS_RXFLVL
* [5] | R | 0x1 | ALT_USB_GLOB_GINTSTS_NPTXFEMP
* [6] | R | 0x0 | ALT_USB_GLOB_GINTSTS_GINNAKEFF
* [7] | R | 0x0 | ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
* [9:8] | ??? | 0x0 | *UNDEFINED*
* [10] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ERLYSUSP
* [11] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_USBSUSP
* [12] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_USBRST
* [13] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ENUMDONE
* [14] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_ISOOUTDROP
* [15] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_EOPF
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_EPMIS
* [18] | R | 0x0 | ALT_USB_GLOB_GINTSTS_IEPINT
* [19] | R | 0x0 | ALT_USB_GLOB_GINTSTS_OEPINT
* [20] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_INCOMPISOIN
* [21] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_INCOMPLP
* [22] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_FETSUSP
* [23] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_RSTDET
* [24] | R | 0x0 | ALT_USB_GLOB_GINTSTS_PRTINT
* [25] | R | 0x0 | ALT_USB_GLOB_GINTSTS_HCHINT
* [26] | R | 0x1 | ALT_USB_GLOB_GINTSTS_PTXFEMP
* [27] | ??? | 0x0 | *UNDEFINED*
* [28] | RW | 0x1 | ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
* [29] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_DISCONNINT
* [30] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_SESSREQINT
* [31] | RW | 0x0 | ALT_USB_GLOB_GINTSTS_WKUPINT
*
*/
/*
* Field : curmod
*
* Mode: Host and Device
*
* Current Mode of Operation (CurMod)
*
* Indicates the current mode.
*
* 1'b0: Device mode
*
* 1'b1: Host mode
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE | 0x0 | Device mode
* ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST | 0x1 | Host mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
*
* Device mode
*/
#define ALT_USB_GLOB_GINTSTS_CURMOD_E_DEVICE 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_CURMOD
*
* Host mode
*/
#define ALT_USB_GLOB_GINTSTS_CURMOD_E_HOST 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_MSB 0
/* The width in bits of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CURMOD register field value. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_GLOB_GINTSTS_CURMOD register field. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_CURMOD field value from a register. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_GLOB_GINTSTS_CURMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_CURMOD_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : modemis
*
* Mode: Host and Device
*
* Mode Mismatch Interrupt (ModeMis)
*
* The core sets this bit when the application is trying to access:
*
* A Host mode register, when the core is operating in Device
*
* mode
*
* A Device mode register, when the core is operating in Host
*
* mode
*
* The register access is completed on the AHB with an OKAY
*
* response, but is ignored by the core internally and does not
*
* affect the operation of the core.This bit can be set only by the core and the
* application should write 1 to clear
*
* it
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT | 0x0 | No Mode Mismatch Interrupt
* ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT | 0x1 | Mode Mismatch Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
*
* No Mode Mismatch Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_MODMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_MODMIS
*
* Mode Mismatch Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_MODMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_MSB 1
/* The width in bits of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_MODMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_GLOB_GINTSTS_MODMIS register field. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_MODMIS field value from a register. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GINTSTS_MODMIS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_MODMIS_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : otgint
*
* Mode: Host and Device
*
* OTG Interrupt (OTGInt)
*
* The core sets this bit to indicate an OTG protocol event. The
*
* application must read the OTG Interrupt Status (GOTGINT)
*
* register to determine the exact event that caused this interrupt.
*
* The application must clear the appropriate status bit in the
*
* GOTGINT register to clear this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------
* ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT | 0x0 | No Interrupt
* ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT | 0x1 | OTG Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
*
* No Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_OTGINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_OTGINT
*
* OTG Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_OTGINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_MSB 2
/* The width in bits of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OTGINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_GLOB_GINTSTS_OTGINT register field. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_OTGINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GINTSTS_OTGINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_OTGINT_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : sof
*
* Mode: Host and Device
*
* Start of (micro)Frame (Sof)
*
* In Host mode, the core sets this bit to indicate that an SOF (FS),
*
* micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB.
*
* The application must write a 1 to this bit to clear the interrupt.
*
* In Device mode, in the core sets this bit to indicate that an SOF
*
* token has been received on the USB. The application can read
*
* the Device Status register to get the current (micro)Frame
*
* number. This interrupt is seen only when the core is operating at
*
* either HS or FS.
*
* Note: This register may return 1’b1 if read immediately after power on
*
* reset. If the register bit reads 1’b1 immediately after power on reset it does
*
* not indicate that an SOF has been sent (in case of host mode) or SOF has
*
* been received (in case of device mode). The read value of this interrupt is
*
* valid only after a valid connection between host and device is established. If
*
* the bit is set after power on reset the application can clear the bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:---------------
* ALT_USB_GLOB_GINTSTS_SOF_E_INTACT | 0x0 | No sof
* ALT_USB_GLOB_GINTSTS_SOF_E_ACT | 0x1 | Start of Frame
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
*
* No sof
*/
#define ALT_USB_GLOB_GINTSTS_SOF_E_INTACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_SOF
*
* Start of Frame
*/
#define ALT_USB_GLOB_GINTSTS_SOF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_MSB 3
/* The width in bits of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_SOF register field value. */
#define ALT_USB_GLOB_GINTSTS_SOF_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SOF register field value. */
#define ALT_USB_GLOB_GINTSTS_SOF_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_GLOB_GINTSTS_SOF register field. */
#define ALT_USB_GLOB_GINTSTS_SOF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_SOF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_SOF_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GINTSTS_SOF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_SOF_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : rxflvl
*
* Mode: Host and Device
*
* RxFIFO Non-Empty (RxFLvl)
*
* Indicates that there is at least one packet pending to be read
*
* from the RxFIFO.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT | 0x0 | Not Active
* ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT | 0x1 | Rx Fifo Non Empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
*
* Not Active
*/
#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_RXFLVL
*
* Rx Fifo Non Empty
*/
#define ALT_USB_GLOB_GINTSTS_RXFLVL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_MSB 4
/* The width in bits of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RXFLVL register field value. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GINTSTS_RXFLVL register field. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_RXFLVL field value from a register. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GINTSTS_RXFLVL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_RXFLVL_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : nptxfemp
*
* Mode: Host and Device
*
* Non-periodic TxFIFO Empty (NPTxFEmp)
*
* This interrupt is asserted when the Non-periodic TxFIFO is
*
* either half or completely empty, and there is space For at least
*
* one Entry to be written to the Non-periodic Transmit Request
*
* Queue. The half or completely empty status is determined by
*
* the Non-periodic TxFIFO Empty Level bit in the Core AHB
*
* Configuration register (GAHBCFG.NPTxFEmpLvl).
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_MSB 5
/* The width in bits of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GINTSTS_NPTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_RESET 0x1
/* Extracts the ALT_USB_GLOB_GINTSTS_NPTXFEMP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GINTSTS_NPTXFEMP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_NPTXFEMP_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : ginnakeff
*
* Mode: Device only
*
* Global IN Non-periodic NAK Effective (GINNakEff)
*
* Indicates that the Set Global Non-periodic IN NAK bit in the
*
* Device Control register (DCTL.SGNPInNak), Set by the
*
* application, has taken effect in the core. That is, the core has
*
* sampled the Global IN NAK bit Set by the application. This bit
*
* can be cleared by clearing the Clear Global Non-periodic IN
*
* NAK bit in the Device Control register (DCTL.CGNPInNak).
*
* This interrupt does not necessarily mean that a NAK handshake
*
* is sent out on the USB. The STALL bit takes precedence over
*
* the NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------------
* ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT | 0x1 | Set Global Non-periodic IN NAK bi
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_GINNAKEFF
*
* Set Global Non-periodic IN NAK bi
*/
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_MSB 6
/* The width in bits of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_GLOB_GINTSTS_GINNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_GINNAKEFF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GINTSTS_GINNAKEFF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_GINNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : goutnakeff
*
* Mode: Device only
*
* Global OUT NAK Effective (GOUTNakEff)
*
* Indicates that the Set Global OUT NAK bit in the Device Control
*
* register (DCTL.SGOUTNak), Set by the application, has taken
*
* effect in the core. This bit can be cleared by writing the Clear
*
* Global OUT NAK bit in the Device Control register
*
* (DCTL.CGOUTNak).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------
* ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT | 0x0 | No Active
* ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT | 0x1 | Global OUT NAK Effective
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
*
* No Active
*/
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_GOUTNAKEFF
*
* Global OUT NAK Effective
*/
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_MSB 7
/* The width in bits of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_GOUTNAKEFF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GINTSTS_GOUTNAKEFF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_GOUTNAKEFF_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : erlysusp
*
* Mode: Device only
*
* Early Suspend (ErlySusp)
*
* The core sets this bit to indicate that an Idle state has been
*
* detected on the USB For 3 ms.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT | 0x0 | No Idle
* ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT | 0x1 | Idle state detecetd
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
*
* No Idle
*/
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ERLYSUSP
*
* Idle state detecetd
*/
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_MSB 10
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ERLYSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ERLYSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GINTSTS_ERLYSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ERLYSUSP_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : usbsusp
*
* Mode: Device only
*
* USB Suspend (USBSusp)
*
* The core sets this bit to indicate that a suspend was detected on
*
* the USB. The core enters the Suspended state when there is no
*
* activity on the linestate signal For an extended period of
*
* time.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT | 0x0 | Not Active
* ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT | 0x1 | USB Suspend
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
*
* Not Active
*/
#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBSUSP
*
* USB Suspend
*/
#define ALT_USB_GLOB_GINTSTS_USBSUSP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_MSB 11
/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GINTSTS_USBSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_USBSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GINTSTS_USBSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_USBSUSP_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : usbrst
*
* Mode: Device only
*
* USB Reset (USBRst)
*
* The core sets this bit to indicate that a reset is detected on the
*
* USB.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_GLOB_GINTSTS_USBRST_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_USBRST_E_ACT | 0x1 | USB Reset
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_USBRST_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_USBRST
*
* USB Reset
*/
#define ALT_USB_GLOB_GINTSTS_USBRST_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_MSB 12
/* The width in bits of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
#define ALT_USB_GLOB_GINTSTS_USBRST_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_USBRST register field value. */
#define ALT_USB_GLOB_GINTSTS_USBRST_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_GLOB_GINTSTS_USBRST register field. */
#define ALT_USB_GLOB_GINTSTS_USBRST_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_USBRST field value from a register. */
#define ALT_USB_GLOB_GINTSTS_USBRST_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GINTSTS_USBRST register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_USBRST_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : enumdone
*
* Mode: Device only
*
* Enumeration Done (EnumDone)
*
* The core sets this bit to indicate that speed enumeration is
*
* complete. The application must read the Device Status (DSTS)
*
* register to obtain the enumerated speed.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT | 0x1 | Enumeration Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ENUMDONE
*
* Enumeration Done
*/
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_MSB 13
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ENUMDONE register field value. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ENUMDONE register field. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ENUMDONE field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GINTSTS_ENUMDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ENUMDONE_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : isooutdrop
*
* Mode: Device only
*
* Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
*
* The core sets this bit when it fails to write an isochronous OUT
*
* packet into the RxFIFO because the RxFIFO does not have
*
* enough space to accommodate a maximum packet size packet
*
* for the isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------------------------------
* ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT | 0x1 | Isochronous OUT Packet Dropped Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_ISOOUTDROP
*
* Isochronous OUT Packet Dropped Interrup
*/
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_MSB 14
/* The width in bits of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_ISOOUTDROP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GINTSTS_ISOOUTDROP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_ISOOUTDROP_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : eopf
*
* Mode: Device only
*
* End of Periodic Frame Interrupt (EOPF)
*
* Indicates that the period specified in the Periodic Frame Interval
*
* field of the Device Configuration register (DCFG.PerFrInt) has
*
* been reached in the current microframe.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
#define ALT_USB_GLOB_GINTSTS_EOPF_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
#define ALT_USB_GLOB_GINTSTS_EOPF_MSB 15
/* The width in bits of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
#define ALT_USB_GLOB_GINTSTS_EOPF_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_EOPF register field value. */
#define ALT_USB_GLOB_GINTSTS_EOPF_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_EOPF register field value. */
#define ALT_USB_GLOB_GINTSTS_EOPF_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_GLOB_GINTSTS_EOPF register field. */
#define ALT_USB_GLOB_GINTSTS_EOPF_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_EOPF field value from a register. */
#define ALT_USB_GLOB_GINTSTS_EOPF_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_GLOB_GINTSTS_EOPF register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_EOPF_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : epmis
*
* Mode: Device only
*
* Endpoint Mismatch Interrupt (EPMis)
*
* Note: This interrupt is valid only in shared FIFO operation.
*
* Indicates that an IN token has been received For a non-periodic
*
* endpoint, but the data For another endpoint is present in the top
*
* of the Non-periodic Transmit FIFO and the IN endpoint
*
* mismatch count programmed by the application has expired.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT | 0x1 | Endpoint Mismatch Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_EPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_EPMIS
*
* Endpoint Mismatch Interrup
*/
#define ALT_USB_GLOB_GINTSTS_EPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_MSB 17
/* The width in bits of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_EPMIS register field value. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_EPMIS register field. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_EPMIS field value from a register. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GINTSTS_EPMIS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_EPMIS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : iepint
*
* Mode: Device only
*
* IN Endpoints Interrupt (IEPInt)
*
* The core sets this bit to indicate that an interrupt is pending on
*
* one of the IN endpoints of the core (in Device mode). The
*
* application must read the Device All Endpoints Interrupt (DAINT)
*
* register to determine the exact number of the IN endpoint on
*
* Device IN Endpoint-n Interrupt (DIEPINTn) register to determine
*
* the exact cause of the interrupt. The application must clear the
*
* appropriate status bit in the corresponding DIEPINTn register to
*
* clear this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------------
* ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT | 0x1 | IN Endpoints Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_IEPINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_IEPINT
*
* IN Endpoints Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_IEPINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_MSB 18
/* The width in bits of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_IEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_IEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_IEPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GINTSTS_IEPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_IEPINT_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : oepint
*
* Mode: Device only
*
* OUT Endpoints Interrupt (OEPInt)
*
* The core sets this bit to indicate that an interrupt is pending on
*
* one of the OUT endpoints of the core (in Device mode). The
*
* application must read the Device All Endpoints Interrupt (DAINT)
*
* register to determine the exact number of the OUT endpoint on
*
* which the interrupt occurred, and Then read the corresponding
*
* Device OUT Endpoint-n Interrupt (DOEPINTn) register to
*
* determine the exact cause of the interrupt. The application must
*
* clear the appropriate status bit in the corresponding DOEPINTn
*
* register to clear this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT | 0x1 | OUT Endpoints Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_OEPINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_OEPINT
*
* OUT Endpoints Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_OEPINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_MSB 19
/* The width in bits of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_OEPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_OEPINT register field. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_OEPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GINTSTS_OEPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_OEPINT_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : incompisoin
*
* Mode: Device only
*
* Incomplete Isochronous IN Transfer (incompISOIN)
*
* The core sets this interrupt to indicate that there is at least one
*
* isochronous IN endpoint on which the transfer is not completed
*
* in the current microframe. This interrupt is asserted along with
*
* the End of Periodic Frame Interrupt (EOPF) bit in this register.
*
* Note: This interrupt is not asserted in Scatter/Gather DMA
*
* mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-----------------------------------
* ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT | 0x1 | Incomplete Isochronous IN Transfer
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPISOIN
*
* Incomplete Isochronous IN Transfer
*/
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_MSB 20
/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPISOIN field value from a register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPISOIN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPISOIN_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : incomplp
*
* Incomplete Periodic Transfer (incomplP)
*
* In Host mode, the core sets this interrupt bit when there are
*
* incomplete periodic transactions still pending which are
*
* scheduled For the current microframe.
*
* Incomplete Isochronous OUT Transfer (incompISOOUT)
*
* The Device mode, the core sets this interrupt to indicate that
*
* there is at least one isochronous OUT endpoint on which the
*
* transfer is not completed in the current microframe. This
*
* interrupt is asserted along with the End of Periodic Frame
*
* Interrupt (EOPF) bit in this register.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT | 0x1 | Incomplete Periodic Transfer
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_INCOMPLP
*
* Incomplete Periodic Transfer
*/
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_MSB 21
/* The width in bits of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_INCOMPLP register field value. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_INCOMPLP register field. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_INCOMPLP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GINTSTS_INCOMPLP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_INCOMPLP_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : fetsusp
*
* Mode: Device only
*
* Data Fetch Suspended (FetSusp)
*
* This interrupt is valid only in DMA mode. This interrupt indicates
*
* that the core has stopped fetching data For IN endpoints due to
*
* the unavailability of TxFIFO space or Request Queue space.
*
* This interrupt is used by the application For an endpoint
*
* mismatch algorithm.
*
* For example, after detecting an endpoint mismatch, the
*
* application:
*
* Sets a Global non-periodic IN NAK handshake
*
* Disables In endpoints
*
* Flushes the FIFO
*
* Determines the token sequence from the IN Token Sequence
*
* Learning Queue
*
* Re-enables the endpoints
*
* Clears the Global non-periodic IN NAK handshake
*
* If the Global non-periodic IN NAK is cleared, the core has not yet
*
* fetched data For the IN endpoint, and the IN token is received:
*
* the core generates an 'IN token received when FIFO empty'
*
* interrupt. The OTG Then sends the host a NAK response. To
*
* avoid this scenario, the application can check the
*
* GINTSTS.FetSusp interrupt, which ensures that the FIFO is full
*
* before clearing a Global NAK handshake.
*
* Alternatively, the application can mask the “IN token received
*
* when FIFO empty” interrupt when clearing a Global IN NAK
*
* handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT | 0x1 | Data Fetch Suspended
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_FETSUSP
*
* Data Fetch Suspended
*/
#define ALT_USB_GLOB_GINTSTS_FETSUSP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_MSB 22
/* The width in bits of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_FETSUSP register field value. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_FETSUSP register field. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_FETSUSP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GINTSTS_FETSUSP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_FETSUSP_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : resetdet
*
* Mode: Device only
*
* Reset detected Interrupt (ResetDet)
*
* In Device mode, this interrupt is asserted when a reset is detected on the USB
* in
*
* partial power-down mode when the device is in Suspend.
*
* In Host mode, this interrupt is not asserted.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT | 0x1 | Reset detected Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_RSTDET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_RSTDET
*
* Reset detected Interrup
*/
#define ALT_USB_GLOB_GINTSTS_RSTDET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_MSB 23
/* The width in bits of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_RSTDET register field value. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_RSTDET register field. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_RSTDET field value from a register. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GINTSTS_RSTDET register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_RSTDET_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : prtint
*
* Mode:Host only
*
* Host Port Interrupt (PrtInt)
*
* The core sets this bit to indicate a change in port status of one of
*
* the DWC_otg core ports in Host mode. The application must
*
* read the Host Port Control and Status (HPRT) register to
*
* determine the exact event that caused this interrupt. The
*
* application must clear the appropriate status bit in the Host Port
*
* Control and Status register to clear this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT | 0x0 |
* ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT | 0x1 | Host Port Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
*
*/
#define ALT_USB_GLOB_GINTSTS_PRTINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_PRTINT
*
* Host Port Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_PRTINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_MSB 24
/* The width in bits of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PRTINT register field value. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_PRTINT register field. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_PRTINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GINTSTS_PRTINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_PRTINT_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : hchint
*
* Mode:Host only
*
* Host Channels Interrupt (HChInt)
*
* The core sets this bit to indicate that an interrupt is pending on
*
* one of the channels of the core (in Host mode). The application
*
* must read the Host All Channels Interrupt (HAINT) register to
*
* determine the exact number of the channel on which the
*
* interrupt occurred, and Then read the corresponding Host
*
* Channel-n Interrupt (HCINTn) register to determine the exact
*
* cause of the interrupt. The application must clear the
*
* appropriate status bit in the HCINTn register to clear this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT | 0x1 | Host Channels Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_HCHINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_HCHINT
*
* Host Channels Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_HCHINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_MSB 25
/* The width in bits of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_HCHINT register field value. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_HCHINT register field. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_HCHINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GINTSTS_HCHINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_HCHINT_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : ptxfemp
*
* Mode:Host only
*
* Periodic TxFIFO Empty (PTxFEmp)
*
* This interrupt is asserted when the Periodic Transmit FIFO is either half or
*
* completely empty and there is space for at least one entry to be written in
*
* the Periodic Request Queue. The half or completely empty status is
*
* determined by the Periodic TxFIFO Empty Level bit in the Core AHB
*
* Configuration register (GAHBCFG.PTxFEmpLvl).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------
* ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT | 0x1 | Periodic TxFIFO Empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_PTXFEMP
*
* Periodic TxFIFO Empty
*/
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_MSB 26
/* The width in bits of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_PTXFEMP register field value. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_PTXFEMP register field. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_RESET 0x1
/* Extracts the ALT_USB_GLOB_GINTSTS_PTXFEMP field value from a register. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GINTSTS_PTXFEMP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_PTXFEMP_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : conidstschng
*
* Mode:Host and Device
*
* Connector ID Status Change (ConIDStsChng)
*
* The core sets this bit when there is a change in connector ID
*
* status.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT | 0x0 | Not Active
* ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT | 0x1 | Connector ID Status Change
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
*
* Not Active
*/
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG
*
* Connector ID Status Change
*/
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_MSB 28
/* The width in bits of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_RESET 0x1
/* Extracts the ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG field value from a register. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : disconnint
*
* Mode:Host only
*
* Disconnect Detected Interrupt (DisconnInt)
*
* Asserted when a device disconnect is detected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------
* ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT | 0x1 | Disconnect Detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_DISCONNINT
*
* Disconnect Detected Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_MSB 29
/* The width in bits of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_DISCONNINT register field value. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_DISCONNINT register field. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_DISCONNINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GINTSTS_DISCONNINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_DISCONNINT_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : sessreqint
*
* Mode:Host and Device
*
* Session Request/New Session Detected Interrupt (SessReqInt)
*
* In Host mode, this interrupt is asserted when a session request is detected
*
* from the device. In Host mode, this interrupt is asserted when a session
*
* request is detected from the device.
*
* In Device mode, this interrupt is asserted when the utmisrp_bvalid signal
*
* goes high.
*
* For more information on how to use this interrupt, see 'Partial Power-Down
*
* and Clock Gating Programming Model'.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------------------------
* ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT | 0x1 | Session Request New Session Detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_SESSREQINT
*
* Session Request New Session Detected Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_MSB 30
/* The width in bits of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_SESSREQINT register field value. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_SESSREQINT register field. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_SESSREQINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GINTSTS_SESSREQINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_SESSREQINT_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : wkupint
*
* Mode:Host and Device
*
* Resume/Remote Wakeup Detected Interrupt (WkUpInt)
*
* Wakeup Interrupt during Suspend(L2) or LPM(L1) state.
*
* During Suspend(L2):
*
* * Device Mode - This interrupt is asserted only when Host Initiated
*
* Resume is detected on USB.
*
* * Host Mode - This interrupt is asserted only when Device Initiated
*
* Remote Wakeup is detected on USB.
*
* For more information, see 'Partial Power-Down and Clock Gating
*
* Programming Model'.
*
* During LPM(L1):-
*
* * Device Mode - This interrupt is asserted for either Host Initiated
*
* Resume or Device Initiated Remote Wakeup on USB.
*
* * Host Mode - This interrupt is asserted for either Host Initiated Resume
*
* or Device Initiated Remote Wakeup on USB.
*
* For more information, see 'LPM Entry and Exit Programming Model'
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT | 0x0 | Not active
* ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT | 0x1 | Resume Remote Wakeup Detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
*
* Not active
*/
#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTSTS_WKUPINT
*
* Resume Remote Wakeup Detected Interrupt
*/
#define ALT_USB_GLOB_GINTSTS_WKUPINT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_MSB 31
/* The width in bits of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GINTSTS_WKUPINT register field value. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GINTSTS_WKUPINT register field. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTSTS_WKUPINT field value from a register. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GINTSTS_WKUPINT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTSTS_WKUPINT_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GINTSTS.
*/
struct ALT_USB_GLOB_GINTSTS_s
{
const uint32_t curmod : 1; /* ALT_USB_GLOB_GINTSTS_CURMOD */
uint32_t modemis : 1; /* ALT_USB_GLOB_GINTSTS_MODMIS */
const uint32_t otgint : 1; /* ALT_USB_GLOB_GINTSTS_OTGINT */
uint32_t sof : 1; /* ALT_USB_GLOB_GINTSTS_SOF */
const uint32_t rxflvl : 1; /* ALT_USB_GLOB_GINTSTS_RXFLVL */
const uint32_t nptxfemp : 1; /* ALT_USB_GLOB_GINTSTS_NPTXFEMP */
const uint32_t ginnakeff : 1; /* ALT_USB_GLOB_GINTSTS_GINNAKEFF */
const uint32_t goutnakeff : 1; /* ALT_USB_GLOB_GINTSTS_GOUTNAKEFF */
uint32_t : 2; /* *UNDEFINED* */
uint32_t erlysusp : 1; /* ALT_USB_GLOB_GINTSTS_ERLYSUSP */
uint32_t usbsusp : 1; /* ALT_USB_GLOB_GINTSTS_USBSUSP */
uint32_t usbrst : 1; /* ALT_USB_GLOB_GINTSTS_USBRST */
uint32_t enumdone : 1; /* ALT_USB_GLOB_GINTSTS_ENUMDONE */
uint32_t isooutdrop : 1; /* ALT_USB_GLOB_GINTSTS_ISOOUTDROP */
uint32_t eopf : 1; /* ALT_USB_GLOB_GINTSTS_EOPF */
uint32_t : 1; /* *UNDEFINED* */
uint32_t epmis : 1; /* ALT_USB_GLOB_GINTSTS_EPMIS */
const uint32_t iepint : 1; /* ALT_USB_GLOB_GINTSTS_IEPINT */
const uint32_t oepint : 1; /* ALT_USB_GLOB_GINTSTS_OEPINT */
uint32_t incompisoin : 1; /* ALT_USB_GLOB_GINTSTS_INCOMPISOIN */
uint32_t incomplp : 1; /* ALT_USB_GLOB_GINTSTS_INCOMPLP */
uint32_t fetsusp : 1; /* ALT_USB_GLOB_GINTSTS_FETSUSP */
uint32_t resetdet : 1; /* ALT_USB_GLOB_GINTSTS_RSTDET */
const uint32_t prtint : 1; /* ALT_USB_GLOB_GINTSTS_PRTINT */
const uint32_t hchint : 1; /* ALT_USB_GLOB_GINTSTS_HCHINT */
const uint32_t ptxfemp : 1; /* ALT_USB_GLOB_GINTSTS_PTXFEMP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t conidstschng : 1; /* ALT_USB_GLOB_GINTSTS_CONIDSTSCHNG */
uint32_t disconnint : 1; /* ALT_USB_GLOB_GINTSTS_DISCONNINT */
uint32_t sessreqint : 1; /* ALT_USB_GLOB_GINTSTS_SESSREQINT */
uint32_t wkupint : 1; /* ALT_USB_GLOB_GINTSTS_WKUPINT */
};
/* The typedef declaration for register ALT_USB_GLOB_GINTSTS. */
typedef volatile struct ALT_USB_GLOB_GINTSTS_s ALT_USB_GLOB_GINTSTS_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GINTSTS register. */
#define ALT_USB_GLOB_GINTSTS_RESET 0x14000020
/* The byte offset of the ALT_USB_GLOB_GINTSTS register from the beginning of the component. */
#define ALT_USB_GLOB_GINTSTS_OFST 0x14
/* The address of the ALT_USB_GLOB_GINTSTS register. */
#define ALT_USB_GLOB_GINTSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTSTS_OFST))
/*
* Register : gintmsk
*
* Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :------|:-------|:------|:-------------------------------------
* [0] | ??? | 0x0 | *UNDEFINED*
* [1] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_MODMISMSK
* [2] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_OTGINTMSK
* [3] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_SOFMSK
* [4] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_RXFLVLMSK
* [5] | ??? | 0x0 | *UNDEFINED*
* [6] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
* [7] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
* [9:8] | ??? | 0x0 | *UNDEFINED*
* [10] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
* [11] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_USBSUSPMSK
* [12] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_USBRSTMSK
* [13] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
* [14] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
* [15] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_EOPFMSK
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_EPMISMSK
* [18] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_IEPINTMSK
* [19] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_OEPINTMSK
* [20] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
* [21] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
* [22] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_FETSUSPMSK
* [23] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_RSTDETMSK
* [24] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_PRTINTMSK
* [25] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_HCHINTMSK
* [26] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
* [27] | ??? | 0x0 | *UNDEFINED*
* [28] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
* [29] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
* [30] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
* [31] | RW | 0x0 | ALT_USB_GLOB_GINTMSK_WKUPINTMSK
*
*/
/*
* Field : modemismsk
*
* Mode: Host and Device
*
* Mode Mismatch Interrupt Mask (ModeMisMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------------------
* ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK | 0x0 | Mode Mismatch Interrupt Mask
* ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK | 0x1 | No Mask Mode Mismatch Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
*
* Mode Mismatch Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_MODMISMSK
*
* No Mask Mode Mismatch Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_MSB 1
/* The width in bits of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_MODMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_GLOB_GINTMSK_MODMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_MODMISMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_GLOB_GINTMSK_MODMISMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_MODMISMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : otgintmsk
*
* Mode: Host and Device
*
* OTG Interrupt Mask (OTGIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------
* ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK | 0x0 | OTG Interrupt Mask
* ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK | 0x1 | No mask OTG Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
*
* OTG Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_OTGINTMSK
*
* No mask OTG Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_MSB 2
/* The width in bits of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_GLOB_GINTMSK_OTGINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_OTGINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_GLOB_GINTMSK_OTGINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_OTGINTMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : sofmsk
*
* Mode: Host and Device
*
* Start of (micro)Frame Mask (SofMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------------
* ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK | 0x0 | Start of Frame Mask
* ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK | 0x1 | No Mask Start of Frame
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
*
* Start of Frame Mask
*/
#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_SOFMSK
*
* No Mask Start of Frame
*/
#define ALT_USB_GLOB_GINTMSK_SOFMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_MSB 3
/* The width in bits of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SOFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_GLOB_GINTMSK_SOFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_SOFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_GLOB_GINTMSK_SOFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_SOFMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : rxflvlmsk
*
* Mode: Host and Device
*
* Receive FIFO Non-Empty Mask (RxFLvlMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-------------------------------
* ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK | 0x0 | Receive FIFO Non-Empty Mask
* ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK | 0x1 | No maks Receive FIFO Non-Empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
*
* Receive FIFO Non-Empty Mask
*/
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_RXFLVLMSK
*
* No maks Receive FIFO Non-Empty
*/
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_MSB 4
/* The width in bits of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_RXFLVLMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GINTMSK_RXFLVLMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_RXFLVLMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ginnakeffmsk
*
* Mode: Device only
*
* Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK | 0x0 | Global Non-periodic IN NAK Effective Mask
* ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK | 0x1 | No mask Global Non-periodic IN NAK Effective
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
*
* Global Non-periodic IN NAK Effective Mask
*/
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK
*
* No mask Global Non-periodic IN NAK Effective
*/
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_MSB 6
/* The width in bits of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : goutnakeffmsk
*
* Mode: Device only
*
* Global OUT NAK Effective Mask (GOUTNakEffMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------
* ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK | 0x0 | Global OUT NAK Effective Mask
* ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS | 0x1 | No mask Global OUT NAK Effective
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
*
* Global OUT NAK Effective Mask
*/
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK
*
* No mask Global OUT NAK Effective
*/
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_E_NOMAKS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_MSB 7
/* The width in bits of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : erlysuspmsk
*
* Mode: Device only
*
* Early Suspend Mask (ErlySuspMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK | 0x0 | Early Suspend Mask
* ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK | 0x1 | No mask Early Suspend Mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
*
* Early Suspend Mask
*/
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK
*
* No mask Early Suspend Mask
*/
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_MSB 10
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : usbsuspmsk
*
* Mode: Device only
*
* USB Suspend Mask (USBSuspMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK | 0x0 | USB Suspend Mask
* ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK | 0x1 | No mask USB Suspend
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
*
* USB Suspend Mask
*/
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBSUSPMSK
*
* No mask USB Suspend
*/
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_MSB 11
/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_USBSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GINTMSK_USBSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_USBSUSPMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : usbrstmsk
*
* Mode: Device only
*
* USB Reset Mask (USBRstMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------
* ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK | 0x0 | USB Reset Mask
* ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK | 0x1 | No mask USB Reset
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
*
* USB Reset Mask
*/
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_USBRSTMSK
*
* No mask USB Reset
*/
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_MSB 12
/* The width in bits of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_GLOB_GINTMSK_USBRSTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_USBRSTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GINTMSK_USBRSTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_USBRSTMSK_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : enumdonemsk
*
* Mode: Device only
*
* Enumeration Done Mask (EnumDoneMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------
* ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK | 0x0 | Enumeration Done Mask
* ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK | 0x1 | No mask Enumeration Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
*
* Enumeration Done Mask
*/
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ENUMDONEMSK
*
* No mask Enumeration Done
*/
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_MSB 13
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ENUMDONEMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GINTMSK_ENUMDONEMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ENUMDONEMSK_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : isooutdropmsk
*
* Mode: Device only
*
* Isochronous OUT Packet Dropped Interrupt Mask
*
* (ISOOutDropMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK | 0x0 | Isochronous OUT Packet Dropped Interrupt Mask
* ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK | 0x1 | No mask Isochronous OUT Packet Dropped Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
*
* Isochronous OUT Packet Dropped Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK
*
* No mask Isochronous OUT Packet Dropped Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_MSB 14
/* The width in bits of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : eopfmsk
*
* Mode: Device only
*
* End of Periodic Frame Interrupt Mask (EOPFMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK | 0x0 | End of Periodic Frame Interrupt Mask
* ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK | 0x1 | No mask End of Periodic Frame Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
*
* End of Periodic Frame Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_EOPFMSK
*
* No mask End of Periodic Frame Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_MSB 15
/* The width in bits of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EOPFMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_GLOB_GINTMSK_EOPFMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_EOPFMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_GLOB_GINTMSK_EOPFMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_EOPFMSK_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : epmismsk
*
* Mode: Device only
*
* Endpoint Mismatch Interrupt Mask (EPMisMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK | 0x0 | Endpoint Mismatch Interrupt Mask
* ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK | 0x1 | No mask Endpoint Mismatch Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
*
* Endpoint Mismatch Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_EPMISMSK
*
* No mask Endpoint Mismatch Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_MSB 17
/* The width in bits of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_EPMISMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_EPMISMSK register field. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_EPMISMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_GLOB_GINTMSK_EPMISMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_EPMISMSK_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : iepintmsk
*
* Mode: Device only
*
* IN Endpoints Interrupt Mask (IEPIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK | 0x0 | IN Endpoints Interrupt Mask
* ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS | 0x1 | No mask IN Endpoints Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
*
* IN Endpoints Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_IEPINTMSK
*
* No mask IN Endpoints Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_E_NOMAKS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_MSB 18
/* The width in bits of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_IEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_IEPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GINTMSK_IEPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_IEPINTMSK_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : oepintmsk
*
* Mode: Device only
*
* OUT Endpoints Interrupt Mask (OEPIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------------------
* ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK | 0x0 | OUT Endpoints Interrupt Mask
* ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK | 0x1 | No mask OUT Endpoints Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
*
* OUT Endpoints Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_OEPINTMSK
*
* No mask OUT Endpoints Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_MSB 19
/* The width in bits of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_OEPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_OEPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GINTMSK_OEPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_OEPINTMSK_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : incompisoinmsk
*
* Mode: Device only
*
* Incomplete Isochronous IN Transfer Mask (incompISOINMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------------------
* ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK | 0x0 | Incomplete Isochronous IN Transfer Mask
* ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK | 0x1 | No mask Incomplete Isochronous IN Transfer
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
*
* Incomplete Isochronous IN Transfer Mask
*/
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK
*
* No mask Incomplete Isochronous IN Transfer
*/
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_MSB 20
/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : incomplpmsk
*
* Mode: Host only
*
* Incomplete Periodic Transfer Mask (incomplPMsk)
*
* Mode: Device only
*
* Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------
* ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK | 0x0 | Incomplete Periodic Transfer Mask
* ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK | 0x1 | No mask Incomplete Periodic Transfer
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
*
* Incomplete Periodic Transfer Mask
*/
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_INCOMPLPMSK
*
* No mask Incomplete Periodic Transfer
*/
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_MSB 21
/* The width in bits of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_INCOMPLPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GINTMSK_INCOMPLPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_INCOMPLPMSK_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : fetsuspmsk
*
* Mode: Device only
*
* Data Fetch Suspended Mask (FetSuspMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK | 0x0 | Data Fetch Suspended Mask
* ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK | 0x1 | No mask Data Fetch Suspended
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
*
* Data Fetch Suspended Mask
*/
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_FETSUSPMSK
*
* No mask Data Fetch Suspended
*/
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_MSB 22
/* The width in bits of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_FETSUSPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GINTMSK_FETSUSPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_FETSUSPMSK_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : resetdetmsk
*
* Mode: Device only
*
* Reset detected Interrupt Mask (ResetDetMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------------------
* ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK | 0x0 | Reset detected Interrupt Mask
* ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK | 0x1 | No mask Reset detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
*
* Reset detected Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_RSTDETMSK
*
* No mask Reset detected Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_MSB 23
/* The width in bits of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_RSTDETMSK register field. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_RSTDETMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GINTMSK_RSTDETMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_RSTDETMSK_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : prtintmsk
*
* Mode: Host only
*
* Host Port Interrupt Mask (PrtIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK | 0x0 | Host Port Interrupt Mask
* ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK | 0x1 | No mask Host Port Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
*
* Host Port Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_PRTINTMSK
*
* No mask Host Port Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_MSB 24
/* The width in bits of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_PRTINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_PRTINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GINTMSK_PRTINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_PRTINTMSK_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : hchintmsk
*
* Mode: Host only
*
* Host Channels Interrupt Mask (HChIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------------------
* ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK | 0x0 | Host Channels Interrupt Mask
* ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK | 0x1 | No mask Host Channels Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
*
* Host Channels Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_HCHINTMSK
*
* No mask Host Channels Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_MSB 25
/* The width in bits of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_HCHINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_HCHINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GINTMSK_HCHINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_HCHINTMSK_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : ptxfempmsk
*
* Mode: Host only
*
* Periodic TxFIFO Empty Mask (PTxFEmpMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------
* ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK | 0x0 | Periodic TxFIFO Empty Mask
* ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK | 0x1 | No mask Periodic TxFIFO Empty
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
*
* Periodic TxFIFO Empty Mask
*/
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_PTXFEMPMSK
*
* No mask Periodic TxFIFO Empty
*/
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_MSB 26
/* The width in bits of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_PTXFEMPMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GINTMSK_PTXFEMPMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_PTXFEMPMSK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : conidstschngmsk
*
* Mode: Host and Device
*
* Connector ID Status Change Mask (ConIDStsChngMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:-----------------------------------
* ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK | 0x0 | Connector ID Status Change Mask
* ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK | 0x1 | No mask Connector ID Status Change
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
*
* Connector ID Status Change Mask
*/
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK
*
* No mask Connector ID Status Change
*/
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_MSB 28
/* The width in bits of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : disconnintmsk
*
* Mode: Host and Device
*
* Disconnect Detected Interrupt Mask (DisconnIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------------
* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK | 0x0 | Disconnect Detected Interrupt Mask
* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK | 0x1 | No mask Disconnect Detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
*
* Disconnect Detected Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_DISCONNINTMSK
*
* No mask Disconnect Detected Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_MSB 29
/* The width in bits of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_DISCONNINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_GLOB_GINTMSK_DISCONNINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_DISCONNINTMSK_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : sessreqintmsk
*
* Mode: Host and Device
*
* Session Request/New Session Detected Interrupt Mask
*
* (SessReqIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-----------------------------------------------
* ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK | 0x0 | Session Request New Session Detected Interrupt
* : | | Mask
* ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK | 0x1 | No mask Session RequestNew Session Detected
* : | | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
*
* Session Request New Session Detected Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_SESSREQINTMSK
*
* No mask Session RequestNew Session Detected Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_MSB 30
/* The width in bits of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_SESSREQINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GINTMSK_SESSREQINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_SESSREQINTMSK_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : wkupintmsk
*
* Mode: Host and Device
*
* Resume/Remote Wakeup Detected Interrupt Mask
*
* The WakeUp bit is used for LPM state wake up in a way similar to that of wake up
* in suspend state.
*
* (WkUpIntMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------------------------
* ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK | 0x0 | Resume Remote Wakeup Detected Interrupt Mask
* ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK | 0x1 | No maskResume Remote Wakeup Detected Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
*
* Resume Remote Wakeup Detected Interrupt Mask
*/
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GINTMSK_WKUPINTMSK
*
* No maskResume Remote Wakeup Detected Interrupt
*/
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_MSB 31
/* The width in bits of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_RESET 0x0
/* Extracts the ALT_USB_GLOB_GINTMSK_WKUPINTMSK field value from a register. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GINTMSK_WKUPINTMSK register field value suitable for setting the register. */
#define ALT_USB_GLOB_GINTMSK_WKUPINTMSK_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GINTMSK.
*/
struct ALT_USB_GLOB_GINTMSK_s
{
uint32_t : 1; /* *UNDEFINED* */
uint32_t modemismsk : 1; /* ALT_USB_GLOB_GINTMSK_MODMISMSK */
uint32_t otgintmsk : 1; /* ALT_USB_GLOB_GINTMSK_OTGINTMSK */
uint32_t sofmsk : 1; /* ALT_USB_GLOB_GINTMSK_SOFMSK */
uint32_t rxflvlmsk : 1; /* ALT_USB_GLOB_GINTMSK_RXFLVLMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t ginnakeffmsk : 1; /* ALT_USB_GLOB_GINTMSK_GINNAKEFFMSK */
uint32_t goutnakeffmsk : 1; /* ALT_USB_GLOB_GINTMSK_GOUTNAKEFFMSK */
uint32_t : 2; /* *UNDEFINED* */
uint32_t erlysuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_ERLYSUSPMSK */
uint32_t usbsuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_USBSUSPMSK */
uint32_t usbrstmsk : 1; /* ALT_USB_GLOB_GINTMSK_USBRSTMSK */
uint32_t enumdonemsk : 1; /* ALT_USB_GLOB_GINTMSK_ENUMDONEMSK */
uint32_t isooutdropmsk : 1; /* ALT_USB_GLOB_GINTMSK_ISOOUTDROPMSK */
uint32_t eopfmsk : 1; /* ALT_USB_GLOB_GINTMSK_EOPFMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t epmismsk : 1; /* ALT_USB_GLOB_GINTMSK_EPMISMSK */
uint32_t iepintmsk : 1; /* ALT_USB_GLOB_GINTMSK_IEPINTMSK */
uint32_t oepintmsk : 1; /* ALT_USB_GLOB_GINTMSK_OEPINTMSK */
uint32_t incompisoinmsk : 1; /* ALT_USB_GLOB_GINTMSK_INCOMPISOINMSK */
uint32_t incomplpmsk : 1; /* ALT_USB_GLOB_GINTMSK_INCOMPLPMSK */
uint32_t fetsuspmsk : 1; /* ALT_USB_GLOB_GINTMSK_FETSUSPMSK */
uint32_t resetdetmsk : 1; /* ALT_USB_GLOB_GINTMSK_RSTDETMSK */
uint32_t prtintmsk : 1; /* ALT_USB_GLOB_GINTMSK_PRTINTMSK */
uint32_t hchintmsk : 1; /* ALT_USB_GLOB_GINTMSK_HCHINTMSK */
uint32_t ptxfempmsk : 1; /* ALT_USB_GLOB_GINTMSK_PTXFEMPMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t conidstschngmsk : 1; /* ALT_USB_GLOB_GINTMSK_CONIDSTSCHNGMSK */
uint32_t disconnintmsk : 1; /* ALT_USB_GLOB_GINTMSK_DISCONNINTMSK */
uint32_t sessreqintmsk : 1; /* ALT_USB_GLOB_GINTMSK_SESSREQINTMSK */
uint32_t wkupintmsk : 1; /* ALT_USB_GLOB_GINTMSK_WKUPINTMSK */
};
/* The typedef declaration for register ALT_USB_GLOB_GINTMSK. */
typedef volatile struct ALT_USB_GLOB_GINTMSK_s ALT_USB_GLOB_GINTMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GINTMSK register. */
#define ALT_USB_GLOB_GINTMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GINTMSK register from the beginning of the component. */
#define ALT_USB_GLOB_GINTMSK_OFST 0x18
/* The address of the ALT_USB_GLOB_GINTMSK register. */
#define ALT_USB_GLOB_GINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GINTMSK_OFST))
/*
* Register : grxstsr
*
* Receive Status Debug Read Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------
* [3:0] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_CHNUM
* [14:4] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_BCNT
* [16:15] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_DPID
* [20:17] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_PKTSTS
* [24:21] | R | 0x0 | ALT_USB_GLOB_GRXSTSR_FN
* [31:25] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : chnum
*
* Mode: Host only
*
* Channel Number (ChNum)
*
* Indicates the channel number to which the current received
*
* packet belongs.
*
* Mode: Device only
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number to which the current received
*
* packet belongs.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_MSB 3
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET_MSK 0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_CLR_MSK 0xfffffff0
/* The reset value of the ALT_USB_GLOB_GRXSTSR_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_CHNUM field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GRXSTSR_CHNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_CHNUM_SET(value) (((value) << 0) & 0x0000000f)
/*
* Field : bcnt
*
* Mode: Host only
*
* Byte Count (BCnt)
*
* Indicates the byte count of the received IN data packet.
*
* Mode: Device only
*
* Byte Count (BCnt)
*
* Indicates the byte count of the received data packet.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_MSB 14
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_WIDTH 11
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_SET_MSK 0x00007ff0
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_CLR_MSK 0xffff800f
/* The reset value of the ALT_USB_GLOB_GRXSTSR_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_BCNT field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
/* Produces a ALT_USB_GLOB_GRXSTSR_BCNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_BCNT_SET(value) (((value) << 4) & 0x00007ff0)
/*
* Field : dpid
*
* Mode: Host only
*
* Data PID (DPID)
*
* Indicates the Data PID of the received packet
*
* 2'b00: DATA0
*
* 2'b10: DATA1
*
* 2'b01: DATA2
*
* 2'b11: MDATA
*
* Mode: Device only
*
* Data PID (DPID)
*
* Indicates the Data PID of the received OUT data packet
*
* 2'b00: DATA0
*
* 2'b10: DATA1
*
* 2'b01: DATA2
*
* 2'b11: MDATA
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 | 0x1 | DATA2
* ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 | 0x2 | DATA1
* ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA | 0x3 | MDATA
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
*
* DATA0
*/
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
*
* DATA2
*/
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
*
* DATA1
*/
#define ALT_USB_GLOB_GRXSTSR_DPID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_DPID
*
* MDATA
*/
#define ALT_USB_GLOB_GRXSTSR_DPID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_MSB 16
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSR_DPID_SET_MSK 0x00018000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSR_DPID_CLR_MSK 0xfffe7fff
/* The reset value of the ALT_USB_GLOB_GRXSTSR_DPID register field. */
#define ALT_USB_GLOB_GRXSTSR_DPID_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_DPID field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_DPID_GET(value) (((value) & 0x00018000) >> 15)
/* Produces a ALT_USB_GLOB_GRXSTSR_DPID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_DPID_SET(value) (((value) << 15) & 0x00018000)
/*
* Field : pktsts
*
* Mode: Host only
*
* Packet Status (PktSts)
*
* Indicates the status of the received packet
*
* 4'b0010: IN data packet received
*
* 4'b0011: IN transfer completed (triggers an interrupt)
*
* 4'b0101: Data toggle error (triggers an interrupt)
*
* 4'b0111: Channel halted (triggers an interrupt)
*
* Others: Reserved
*
* Mode: Device only
*
* Packet Status (PktSts)
*
* Indicates the status of the received packet
*
* 4'b0001: Global OUT NAK (triggers an interrupt)
*
* 4'b0010: OUT data packet received
*
* 4'b0011: OUT transfer completed (triggers an interrupt)
*
* 4'b0100: SETUP transaction completed (triggers an
*
* interrupt)
*
* 4'b0110: SETUP data packet received
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX | 0x2 | IN data packet received
* ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM | 0x3 | IN transfer completed (triggers an interrupt
* ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG | 0x5 | Data toggle error (triggers an interrupt)
* ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT | 0x7 | Channel halted (triggers an interrupt)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
*
* IN data packet received
*/
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INDPRX 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
*
* IN transfer completed (triggers an interrupt
*/
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_INTRCOM 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
*
* Data toggle error (triggers an interrupt)
*/
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_DTTOG 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSR_PKTSTS
*
* Channel halted (triggers an interrupt)
*/
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_E_CHHALT 0x7
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_MSB 20
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET_MSK 0x001e0000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_CLR_MSK 0xffe1ffff
/* The reset value of the ALT_USB_GLOB_GRXSTSR_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_PKTSTS field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
/* Produces a ALT_USB_GLOB_GRXSTSR_PKTSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)
/*
* Field : fn
*
* Mode: Device only
*
* Frame Number (FN)
*
* This is the least significant 4 bits of the (micro)Frame number in
*
* which the packet is received on the USB. This field is supported
*
* only when isochronous OUT endpoints are supported.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSR_FN register field. */
#define ALT_USB_GLOB_GRXSTSR_FN_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSR_FN register field. */
#define ALT_USB_GLOB_GRXSTSR_FN_MSB 24
/* The width in bits of the ALT_USB_GLOB_GRXSTSR_FN register field. */
#define ALT_USB_GLOB_GRXSTSR_FN_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSR_FN register field value. */
#define ALT_USB_GLOB_GRXSTSR_FN_SET_MSK 0x01e00000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSR_FN register field value. */
#define ALT_USB_GLOB_GRXSTSR_FN_CLR_MSK 0xfe1fffff
/* The reset value of the ALT_USB_GLOB_GRXSTSR_FN register field. */
#define ALT_USB_GLOB_GRXSTSR_FN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSR_FN field value from a register. */
#define ALT_USB_GLOB_GRXSTSR_FN_GET(value) (((value) & 0x01e00000) >> 21)
/* Produces a ALT_USB_GLOB_GRXSTSR_FN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSR_FN_SET(value) (((value) << 21) & 0x01e00000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GRXSTSR.
*/
struct ALT_USB_GLOB_GRXSTSR_s
{
const uint32_t chnum : 4; /* ALT_USB_GLOB_GRXSTSR_CHNUM */
const uint32_t bcnt : 11; /* ALT_USB_GLOB_GRXSTSR_BCNT */
const uint32_t dpid : 2; /* ALT_USB_GLOB_GRXSTSR_DPID */
const uint32_t pktsts : 4; /* ALT_USB_GLOB_GRXSTSR_PKTSTS */
const uint32_t fn : 4; /* ALT_USB_GLOB_GRXSTSR_FN */
uint32_t : 7; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GRXSTSR. */
typedef volatile struct ALT_USB_GLOB_GRXSTSR_s ALT_USB_GLOB_GRXSTSR_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GRXSTSR register. */
#define ALT_USB_GLOB_GRXSTSR_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GRXSTSR register from the beginning of the component. */
#define ALT_USB_GLOB_GRXSTSR_OFST 0x1c
/* The address of the ALT_USB_GLOB_GRXSTSR register. */
#define ALT_USB_GLOB_GRXSTSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSR_OFST))
/*
* Register : grxstsp
*
* Receive Status Read /Pop Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------
* [3:0] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_CHNUM
* [14:4] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_BCNT
* [16:15] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_DPID
* [20:17] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_PKTSTS
* [24:21] | R | 0x0 | ALT_USB_GLOB_GRXSTSP_FN
* [31:25] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : chnum
*
* Mode: Host only
*
* Channel Number (ChNum)
*
* Indicates the channel number to which the current received
*
* packet belongs.
*
* Mode: Device only
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number to which the current received
*
* packet belongs.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_MSB 3
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET_MSK 0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_CHNUM register field value. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_CLR_MSK 0xfffffff0
/* The reset value of the ALT_USB_GLOB_GRXSTSP_CHNUM register field. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_CHNUM field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GRXSTSP_CHNUM register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_CHNUM_SET(value) (((value) << 0) & 0x0000000f)
/*
* Field : bcnt
*
* Mode: Host only
*
* Byte Count (BCnt)
*
* Indicates the byte count of the received IN data packet.
*
* Mode: Device only
*
* Byte Count (BCnt)
*
* Indicates the byte count of the received data packet.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_MSB 14
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_WIDTH 11
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_SET_MSK 0x00007ff0
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_BCNT register field value. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_CLR_MSK 0xffff800f
/* The reset value of the ALT_USB_GLOB_GRXSTSP_BCNT register field. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_BCNT field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_GET(value) (((value) & 0x00007ff0) >> 4)
/* Produces a ALT_USB_GLOB_GRXSTSP_BCNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_BCNT_SET(value) (((value) << 4) & 0x00007ff0)
/*
* Field : dpid
*
* Mode: Host only
*
* Data PID (DPID)
*
* Indicates the Data PID of the received packet
*
* 2'b00: DATA0
*
* 2'b10: DATA1
*
* 2'b01: DATA2
*
* 2'b11: MDATA
*
* Mode: Device only
*
* Data PID (DPID)
*
* Indicates the Data PID of the received OUT data packet
*
* 2'b00: DATA0
*
* 2'b10: DATA1
*
* 2'b01: DATA2
*
* 2'b11: MDATA
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 | 0x1 | DATA2
* ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 | 0x2 | DATA1
* ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA | 0x3 | MDATA
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
*
* DATA0
*/
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
*
* DATA2
*/
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
*
* DATA1
*/
#define ALT_USB_GLOB_GRXSTSP_DPID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_DPID
*
* MDATA
*/
#define ALT_USB_GLOB_GRXSTSP_DPID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_MSB 16
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSP_DPID_SET_MSK 0x00018000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_DPID register field value. */
#define ALT_USB_GLOB_GRXSTSP_DPID_CLR_MSK 0xfffe7fff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_DPID register field. */
#define ALT_USB_GLOB_GRXSTSP_DPID_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_DPID field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_DPID_GET(value) (((value) & 0x00018000) >> 15)
/* Produces a ALT_USB_GLOB_GRXSTSP_DPID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_DPID_SET(value) (((value) << 15) & 0x00018000)
/*
* Field : pktsts
*
* Mode: Host only
*
* Packet Status (PktSts)
*
* Indicates the status of the received packet
*
* 4'b0010: IN data packet received
*
* 4'b0011: IN transfer completed (triggers an interrupt)
*
* 4'b0101: Data toggle error (triggers an interrupt)
*
* 4'b0111: Channel halted (triggers an interrupt)
*
* Others: Reserved
*
* Mode: Device only
*
* Packet Status (PktSts)
*
* Indicates the status of the received packet
*
* 4'b0001: Global OUT NAK (triggers an interrupt)
*
* 4'b0010: OUT data packet received
*
* 4'b0011: OUT transfer completed (triggers an interrupt)
*
* 4'b0100: SETUP transaction completed (triggers an
*
* interrupt)
*
* 4'b0110: SETUP data packet received
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 | 0x0 | DATA0
* ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 | 0x1 | DATA2
* ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 | 0x2 | DATA1
* ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA | 0x3 | MDATA
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
*
* DATA0
*/
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
*
* DATA2
*/
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
*
* DATA1
*/
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GRXSTSP_PKTSTS
*
* MDATA
*/
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_MSB 20
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET_MSK 0x001e0000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_PKTSTS register field value. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_CLR_MSK 0xffe1ffff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_PKTSTS register field. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_PKTSTS field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_GET(value) (((value) & 0x001e0000) >> 17)
/* Produces a ALT_USB_GLOB_GRXSTSP_PKTSTS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_PKTSTS_SET(value) (((value) << 17) & 0x001e0000)
/*
* Field : fn
*
* Mode: Device only
*
* Frame Number (FN)
*
* This is the least significant 4 bits of the (micro)Frame number in
*
* which the packet is received on the USB. This field is supported
*
* only when isochronous OUT endpoints are supported.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_MSB 24
/* The width in bits of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GRXSTSP_FN register field value. */
#define ALT_USB_GLOB_GRXSTSP_FN_SET_MSK 0x01e00000
/* The mask used to clear the ALT_USB_GLOB_GRXSTSP_FN register field value. */
#define ALT_USB_GLOB_GRXSTSP_FN_CLR_MSK 0xfe1fffff
/* The reset value of the ALT_USB_GLOB_GRXSTSP_FN register field. */
#define ALT_USB_GLOB_GRXSTSP_FN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GRXSTSP_FN field value from a register. */
#define ALT_USB_GLOB_GRXSTSP_FN_GET(value) (((value) & 0x01e00000) >> 21)
/* Produces a ALT_USB_GLOB_GRXSTSP_FN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXSTSP_FN_SET(value) (((value) << 21) & 0x01e00000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GRXSTSP.
*/
struct ALT_USB_GLOB_GRXSTSP_s
{
const uint32_t chnum : 4; /* ALT_USB_GLOB_GRXSTSP_CHNUM */
const uint32_t bcnt : 11; /* ALT_USB_GLOB_GRXSTSP_BCNT */
const uint32_t dpid : 2; /* ALT_USB_GLOB_GRXSTSP_DPID */
const uint32_t pktsts : 4; /* ALT_USB_GLOB_GRXSTSP_PKTSTS */
const uint32_t fn : 4; /* ALT_USB_GLOB_GRXSTSP_FN */
uint32_t : 7; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GRXSTSP. */
typedef volatile struct ALT_USB_GLOB_GRXSTSP_s ALT_USB_GLOB_GRXSTSP_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GRXSTSP register. */
#define ALT_USB_GLOB_GRXSTSP_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GRXSTSP register from the beginning of the component. */
#define ALT_USB_GLOB_GRXSTSP_OFST 0x20
/* The address of the ALT_USB_GLOB_GRXSTSP register. */
#define ALT_USB_GLOB_GRXSTSP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXSTSP_OFST))
/*
* Register : grxfsiz
*
* Receive FIFO Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:----------------------------
* [13:0] | RW | 0x2000 | ALT_USB_GLOB_GRXFSIZ_RXFDEP
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : rxfdep
*
* Mode: Host and Device
*
* RxFIFO Depth (RxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth during configuration. If Enable Dynamic FIFO Sizing
* was selected,
*
* you can write a new value in this field. Programmed values must not exceed the
* power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_MSB 13
/* The width in bits of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET_MSK 0x00003fff
/* The mask used to clear the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_CLR_MSK 0xffffc000
/* The reset value of the ALT_USB_GLOB_GRXFSIZ_RXFDEP register field. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_GRXFSIZ_RXFDEP field value from a register. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_GET(value) (((value) & 0x00003fff) >> 0)
/* Produces a ALT_USB_GLOB_GRXFSIZ_RXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GRXFSIZ_RXFDEP_SET(value) (((value) << 0) & 0x00003fff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GRXFSIZ.
*/
struct ALT_USB_GLOB_GRXFSIZ_s
{
uint32_t rxfdep : 14; /* ALT_USB_GLOB_GRXFSIZ_RXFDEP */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GRXFSIZ. */
typedef volatile struct ALT_USB_GLOB_GRXFSIZ_s ALT_USB_GLOB_GRXFSIZ_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GRXFSIZ register. */
#define ALT_USB_GLOB_GRXFSIZ_RESET 0x00002000
/* The byte offset of the ALT_USB_GLOB_GRXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_GRXFSIZ_OFST 0x24
/* The address of the ALT_USB_GLOB_GRXFSIZ register. */
#define ALT_USB_GLOB_GRXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRXFSIZ_OFST))
/*
* Register : gnptxfsiz
*
* Non-periodic Transmit FIFO Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-----------------------------------
* [15:0] | RW | 0x2000 | ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR
* [31:16] | RW | 0x2000 | ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP
*
*/
/*
* Field : nptxfstaddr
*
* Mode: Host only
*
* Non-periodic Transmit RAM Start Address (NPTxFStAddr)
*
* For host mode, this field is always valid. This field contains the memory start
* address
*
* For Non-periodic Transmit FIFO RAM.
*
* Programmed values must not exceed the power-on value.
*
* Mode: Device only
*
* IN Endpoint FIFO0 Transmit RAM Start Address
*
* (INEPTxF0StAddr)
*
* This field contains the memory start address For IN Endpoint
*
* Transmit FIFO# 0.
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_RESET 0x2000
/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : nptxfdep
*
* Mode: Host only
*
* Non-periodic TxFIFO Depth (NPTxFDep)
*
* For host mode, this field is always valid.
*
* For Device mode, this field is valid for shared fifo
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* Programmed values must not exceed the power-on value.
*
* Mode: Device only
*
* IN Endpoint TxFIFO 0 Depth (INEPTxF0Dep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* This field is determined by Enable Dynamic FIFO Sizing
*
* Programmed values must not
*
* exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_MSB 31
/* The width in bits of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET_MSK 0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_CLR_MSK 0x0000ffff
/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP field value from a register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP_SET(value) (((value) << 16) & 0xffff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GNPTXFSIZ.
*/
struct ALT_USB_GLOB_GNPTXFSIZ_s
{
uint32_t nptxfstaddr : 16; /* ALT_USB_GLOB_GNPTXFSIZ_NPTXFSTADDR */
uint32_t nptxfdep : 16; /* ALT_USB_GLOB_GNPTXFSIZ_NPTXFDEP */
};
/* The typedef declaration for register ALT_USB_GLOB_GNPTXFSIZ. */
typedef volatile struct ALT_USB_GLOB_GNPTXFSIZ_s ALT_USB_GLOB_GNPTXFSIZ_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GNPTXFSIZ register. */
#define ALT_USB_GLOB_GNPTXFSIZ_RESET 0x20002000
/* The byte offset of the ALT_USB_GLOB_GNPTXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_GNPTXFSIZ_OFST 0x28
/* The address of the ALT_USB_GLOB_GNPTXFSIZ register. */
#define ALT_USB_GLOB_GNPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXFSIZ_OFST))
/*
* Register : gnptxsts
*
* Non-periodic Transmit FIFO/Queue Status Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL
* [23:16] | R | 0x8 | ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
* [30:24] | R | 0x0 | ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : nptxfspcavail
*
* Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)
*
* Indicates the amount of free space available in the Non-periodic
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Non-periodic TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 <= n <= 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : nptxqspcavail
*
* Non-periodic Transmit Request Queue Space Available
*
* (NPTxQSpcAvail)
*
* Indicates the amount of free space available in the Non-periodic
*
* Transmit Request Queue. This queue holds both IN and OUT
*
* requests in Host mode. Device mode has only IN requests.
*
* 8'h0: Non-periodic Transmit Request Queue is full
*
* 8'h1: 1 location available
*
* 8'h2: 2 locations available
*
* n: n locations available (0 <= n <= 8)
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------------------
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL | 0x0 | Non-periodic Transmit Request Queue is full
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 | 0x1 | 1 location available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 | 0x2 | 2 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 | 0x3 | 3 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 | 0x4 | 4 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 | 0x5 | 5 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 | 0x6 | 6 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 | 0x7 | 7 locations available
* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 | 0x8 | 8 locations available
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* Non-periodic Transmit Request Queue is full
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_FULL 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 1 location available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE1 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 2 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE2 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 3 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE3 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 4 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE4 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 5 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE5 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 6 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE6 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 7 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE7 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL
*
* 8 locations available
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_E_QUE8 0x8
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_MSB 23
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_WIDTH 8
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET_MSK 0x00ff0000
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_CLR_MSK 0xff00ffff
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_RESET 0x8
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)
/*
* Field : nptxqtop
*
* Top of the Non-periodic Transmit Request Queue (NPTxQTop)
*
* Entry in the Non-periodic Tx Request Queue that is currently
*
* being processed by the MAC.
*
* Bits [30:27]: Channel/endpoint number
*
* Bits [26:25]:
*
* * 2'b00: IN/OUT token
*
* * 2'b01: Zero-length transmit packet (device IN/host OUT)
*
* * 2'b10: PING/CSPLIT token
*
* * 2'b11: Channel halt command
*
* Bit [24]: Terminate (last Entry For selected channel/endpoint)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK | 0x0 | IN/OUT token
* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX | 0x1 | Zero-length transmit packet (device IN/host OUT)
* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT | 0x2 | PING/CSPLIT token
* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT | 0x3 | Channel halt command
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
*
* IN/OUT token
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_INOUTTK 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
*
* Zero-length transmit packet (device IN/host OUT)
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_ZEROTX 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
*
* PING/CSPLIT token
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_PINGCSPLIT 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GNPTXSTS_NPTXQTOP
*
* Channel halt command
*/
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_E_CHNHALT 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_MSB 30
/* The width in bits of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_WIDTH 7
/* The mask used to set the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET_MSK 0x7f000000
/* The mask used to clear the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_CLR_MSK 0x80ffffff
/* The reset value of the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_RESET 0x0
/* Extracts the ALT_USB_GLOB_GNPTXSTS_NPTXQTOP field value from a register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_GET(value) (((value) & 0x7f000000) >> 24)
/* Produces a ALT_USB_GLOB_GNPTXSTS_NPTXQTOP register field value suitable for setting the register. */
#define ALT_USB_GLOB_GNPTXSTS_NPTXQTOP_SET(value) (((value) << 24) & 0x7f000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GNPTXSTS.
*/
struct ALT_USB_GLOB_GNPTXSTS_s
{
const uint32_t nptxfspcavail : 16; /* ALT_USB_GLOB_GNPTXSTS_NPTXFSPCAVAIL */
const uint32_t nptxqspcavail : 8; /* ALT_USB_GLOB_GNPTXSTS_NPTXQSPCAVAIL */
const uint32_t nptxqtop : 7; /* ALT_USB_GLOB_GNPTXSTS_NPTXQTOP */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GNPTXSTS. */
typedef volatile struct ALT_USB_GLOB_GNPTXSTS_s ALT_USB_GLOB_GNPTXSTS_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GNPTXSTS register. */
#define ALT_USB_GLOB_GNPTXSTS_RESET 0x00082000
/* The byte offset of the ALT_USB_GLOB_GNPTXSTS register from the beginning of the component. */
#define ALT_USB_GLOB_GNPTXSTS_OFST 0x2c
/* The address of the ALT_USB_GLOB_GNPTXSTS register. */
#define ALT_USB_GLOB_GNPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GNPTXSTS_OFST))
/*
* Register : gpvndctl
*
* PHY Vendor Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:----------------------------------
* [7:0] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGDATA
* [15:8] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_VCTL
* [21:16] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGADDR
* [22] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_REGWR
* [24:23] | ??? | 0x0 | *UNDEFINED*
* [25] | R-W once | 0x0 | ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
* [26] | R | 0x0 | ALT_USB_GLOB_GPVNDCTL_VSTSBSY
* [27] | RW | 0x0 | ALT_USB_GLOB_GPVNDCTL_VSTSDONE
* [30:28] | ??? | 0x0 | *UNDEFINED*
* [31] | R-W once | 0x0 | ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
*
*/
/*
* Field : regdata
*
* Register Data (RegData)
*
* Contains the write data For register write. Read data For
*
* register read, valid when VStatus Done is Set.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_MSB 7
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_WIDTH 8
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET_MSK 0x000000ff
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGDATA register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_CLR_MSK 0xffffff00
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGDATA register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGDATA field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGDATA register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGDATA_SET(value) (((value) << 0) & 0x000000ff)
/*
* Field : vctrl
*
* UTMI+ Vendor Control Register Address (VCtrl)
*
* The 4-bit register address a vendor defined 4-bit parallel
*
* output bus. Bits 11:8 of this field are placed on
*
* utmi_vcontrol[3:0].
*
* ULPI Extended Register Address (ExtRegAddr)
*
* The 6-bit PHY extended register address.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_MSB 15
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_WIDTH 8
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET_MSK 0x0000ff00
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VCTL register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_CLR_MSK 0xffff00ff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VCTL register field. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VCTL field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_GET(value) (((value) & 0x0000ff00) >> 8)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VCTL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VCTL_SET(value) (((value) << 8) & 0x0000ff00)
/*
* Field : regaddr
*
* Register Address (RegAddr)
*
* The 6-bit PHY register address For immediate PHY Register
*
* Set access. Set to 6'h2F For Extended PHY Register Set
*
* access.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_MSB 21
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_WIDTH 6
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET_MSK 0x003f0000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGADDR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_CLR_MSK 0xffc0ffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGADDR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGADDR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_GET(value) (((value) & 0x003f0000) >> 16)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGADDR_SET(value) (((value) << 16) & 0x003f0000)
/*
* Field : regwr
*
* Register Write (RegWr)
*
* Set this bit For register writes, and clear it For register reads.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:---------------
* ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD | 0x0 | Register Write
* ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR | 0x1 | Register Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
*
* Register Write
*/
#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_RD 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_REGWR
*
* Register Write
*/
#define ALT_USB_GLOB_GPVNDCTL_REGWR_E_WR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_MSB 22
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_REGWR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_REGWR register field. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_REGWR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GPVNDCTL_REGWR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_REGWR_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : newregreq
*
* New Register Request (NewRegReq)
*
* The application sets this bit For a new vendor control
*
* access.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------------------
* ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT | 0x0 | New Register Request not active
* ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT | 0x1 | New Register Request active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
*
* New Register Request not active
*/
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_NEWREGREQ
*
* New Register Request active
*/
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_MSB 25
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_NEWREGREQ field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GPVNDCTL_NEWREGREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_NEWREGREQ_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : vstsbsy
*
* VStatus Busy (VStsBsy)
*
* The core sets this bit when the vendor control access is in
*
* progress and clears this bit when done.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------
* ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT | 0x0 | VStatus Busy inactive
* ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT | 0x1 | VStatus Busy active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
*
* VStatus Busy inactive
*/
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSBSY
*
* VStatus Busy active
*/
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_MSB 26
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSBSY field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSBSY register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSBSY_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : vstsdone
*
* VStatus Done (VStsDone)
*
* The core sets this bit when the vendor control access is
*
* done.
*
* This bit is cleared by the core when the application sets the
*
* New Register Request bit (bit 25).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------
* ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT | 0x0 | VStatus Done inactive
* ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT | 0x1 | VStatus Done active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
*
* VStatus Done inactive
*/
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_VSTSDONE
*
* VStatus Done active
*/
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_MSB 27
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_VSTSDONE field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_GLOB_GPVNDCTL_VSTSDONE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_VSTSDONE_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : disulpidrvr
*
* Disable ULPI Drivers (DisUlpiDrvr)
*
* The application sets this bit when it has finished processing
*
* the ULPI Carkit Interrupt (GINTSTS.ULPICKINT). When
*
* Set, the DWC_otg core disables drivers For output signals
*
* and masks input signal For the ULPI interface. DWC_otg
*
* clears this bit before enabling the ULPI interface.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END | 0x0 | ULPI ouput signals
* ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD | 0x1 | Disable ULPI ouput signals
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
*
* ULPI ouput signals
*/
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_END 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR
*
* Disable ULPI ouput signals
*/
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_E_DISD 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_MSB 31
/* The width in bits of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR field value from a register. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GPVNDCTL.
*/
struct ALT_USB_GLOB_GPVNDCTL_s
{
uint32_t regdata : 8; /* ALT_USB_GLOB_GPVNDCTL_REGDATA */
uint32_t vctrl : 8; /* ALT_USB_GLOB_GPVNDCTL_VCTL */
uint32_t regaddr : 6; /* ALT_USB_GLOB_GPVNDCTL_REGADDR */
uint32_t regwr : 1; /* ALT_USB_GLOB_GPVNDCTL_REGWR */
uint32_t : 2; /* *UNDEFINED* */
uint32_t newregreq : 1; /* ALT_USB_GLOB_GPVNDCTL_NEWREGREQ */
const uint32_t vstsbsy : 1; /* ALT_USB_GLOB_GPVNDCTL_VSTSBSY */
uint32_t vstsdone : 1; /* ALT_USB_GLOB_GPVNDCTL_VSTSDONE */
uint32_t : 3; /* *UNDEFINED* */
uint32_t disulpidrvr : 1; /* ALT_USB_GLOB_GPVNDCTL_DISULPIDRVR */
};
/* The typedef declaration for register ALT_USB_GLOB_GPVNDCTL. */
typedef volatile struct ALT_USB_GLOB_GPVNDCTL_s ALT_USB_GLOB_GPVNDCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GPVNDCTL register. */
#define ALT_USB_GLOB_GPVNDCTL_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GPVNDCTL register from the beginning of the component. */
#define ALT_USB_GLOB_GPVNDCTL_OFST 0x34
/* The address of the ALT_USB_GLOB_GPVNDCTL register. */
#define ALT_USB_GLOB_GPVNDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GPVNDCTL_OFST))
/*
* Register : ggpio
*
* General Purpose Input/Output Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-----------------------
* [15:0] | R | 0x0 | ALT_USB_GLOB_GGPIO_GPI
* [31:16] | RW | 0x0 | ALT_USB_GLOB_GGPIO_GPO
*
*/
/*
* Field : gpi
*
* General Purpose Input (GPI)
*
* This field's read value reflects the gp_i[15:0] core input value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_MSB 15
/* The width in bits of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GGPIO_GPI register field value. */
#define ALT_USB_GLOB_GGPIO_GPI_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPI register field value. */
#define ALT_USB_GLOB_GGPIO_GPI_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_GGPIO_GPI register field. */
#define ALT_USB_GLOB_GGPIO_GPI_RESET 0x0
/* Extracts the ALT_USB_GLOB_GGPIO_GPI field value from a register. */
#define ALT_USB_GLOB_GGPIO_GPI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GGPIO_GPI register field value suitable for setting the register. */
#define ALT_USB_GLOB_GGPIO_GPI_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : gpo
*
* General Purpose Output (GPO)
*
* This field is driven as an output from the core, gp_o[15:0]. The
*
* application can program this field to determine the
*
* corresponding value on the gp_o[15:0] output.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_MSB 31
/* The width in bits of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GGPIO_GPO register field value. */
#define ALT_USB_GLOB_GGPIO_GPO_SET_MSK 0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GGPIO_GPO register field value. */
#define ALT_USB_GLOB_GGPIO_GPO_CLR_MSK 0x0000ffff
/* The reset value of the ALT_USB_GLOB_GGPIO_GPO register field. */
#define ALT_USB_GLOB_GGPIO_GPO_RESET 0x0
/* Extracts the ALT_USB_GLOB_GGPIO_GPO field value from a register. */
#define ALT_USB_GLOB_GGPIO_GPO_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GGPIO_GPO register field value suitable for setting the register. */
#define ALT_USB_GLOB_GGPIO_GPO_SET(value) (((value) << 16) & 0xffff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GGPIO.
*/
struct ALT_USB_GLOB_GGPIO_s
{
const uint32_t gpi : 16; /* ALT_USB_GLOB_GGPIO_GPI */
uint32_t gpo : 16; /* ALT_USB_GLOB_GGPIO_GPO */
};
/* The typedef declaration for register ALT_USB_GLOB_GGPIO. */
typedef volatile struct ALT_USB_GLOB_GGPIO_s ALT_USB_GLOB_GGPIO_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GGPIO register. */
#define ALT_USB_GLOB_GGPIO_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GGPIO register from the beginning of the component. */
#define ALT_USB_GLOB_GGPIO_OFST 0x38
/* The address of the ALT_USB_GLOB_GGPIO register. */
#define ALT_USB_GLOB_GGPIO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GGPIO_OFST))
/*
* Register : guid
*
* User ID Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:-----------|:-----------------------
* [31:0] | R | 0x12345678 | ALT_USB_GLOB_GUID_GUID
*
*/
/*
* Field : guid
*
* User ID (UserID)
*
* Application-programmable ID field.
*
* Reset: Configurable
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_MSB 31
/* The width in bits of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_WIDTH 32
/* The mask used to set the ALT_USB_GLOB_GUID_GUID register field value. */
#define ALT_USB_GLOB_GUID_GUID_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GUID_GUID register field value. */
#define ALT_USB_GLOB_GUID_GUID_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_GLOB_GUID_GUID register field. */
#define ALT_USB_GLOB_GUID_GUID_RESET 0x12345678
/* Extracts the ALT_USB_GLOB_GUID_GUID field value from a register. */
#define ALT_USB_GLOB_GUID_GUID_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GUID_GUID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GUID_GUID_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GUID.
*/
struct ALT_USB_GLOB_GUID_s
{
const uint32_t guid : 32; /* ALT_USB_GLOB_GUID_GUID */
};
/* The typedef declaration for register ALT_USB_GLOB_GUID. */
typedef volatile struct ALT_USB_GLOB_GUID_s ALT_USB_GLOB_GUID_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GUID register. */
#define ALT_USB_GLOB_GUID_RESET 0x12345678
/* The byte offset of the ALT_USB_GLOB_GUID register from the beginning of the component. */
#define ALT_USB_GLOB_GUID_OFST 0x3c
/* The address of the ALT_USB_GLOB_GUID register. */
#define ALT_USB_GLOB_GUID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GUID_OFST))
/*
* Register : gsnpsid
*
* Synopsys ID Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:-----------|:-----------------------------
* [31:0] | R | 0x4f54320a | ALT_USB_GLOB_GSNPSID_GSNPSID
*
*/
/*
* Field : gsnpsid
*
* Release number of the DWC_otg core being used is currently
*
* OTG
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_MSB 31
/* The width in bits of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_WIDTH 32
/* The mask used to set the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GSNPSID_GSNPSID register field value. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_GLOB_GSNPSID_GSNPSID register field. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_RESET 0x4f54320a
/* Extracts the ALT_USB_GLOB_GSNPSID_GSNPSID field value from a register. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GSNPSID_GSNPSID register field value suitable for setting the register. */
#define ALT_USB_GLOB_GSNPSID_GSNPSID_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GSNPSID.
*/
struct ALT_USB_GLOB_GSNPSID_s
{
const uint32_t gsnpsid : 32; /* ALT_USB_GLOB_GSNPSID_GSNPSID */
};
/* The typedef declaration for register ALT_USB_GLOB_GSNPSID. */
typedef volatile struct ALT_USB_GLOB_GSNPSID_s ALT_USB_GLOB_GSNPSID_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GSNPSID register. */
#define ALT_USB_GLOB_GSNPSID_RESET 0x4f54320a
/* The byte offset of the ALT_USB_GLOB_GSNPSID register from the beginning of the component. */
#define ALT_USB_GLOB_GSNPSID_OFST 0x40
/* The address of the ALT_USB_GLOB_GSNPSID register. */
#define ALT_USB_GLOB_GSNPSID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GSNPSID_OFST))
/*
* Register : ghwcfg1
*
* User HW Config1 Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG1_GHWCFG1
*
*/
/*
* Field : ghwcfg1
*
* This 32-bit field uses two bits per
*
* endpoint to determine the endpoint direction.
*
* Endpoint
*
* Bits [31:30]: Endpoint 15 direction
*
* Bits [29:28]: Endpoint 14 direction
*
* ...
*
* Bits [3:2]: Endpoint 1 direction
*
* Bits[1:0]: Endpoint 0 direction (always BIDIR)
*
* Direction
*
* 2'b00: BIDIR (IN and OUT) endpoint
*
* 2'b01: IN endpoint
*
* 2'b10: OUT endpoint
*
* 2'b11: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR | 0x0 | BIDIR (IN and OUT) endpoint
* ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT | 0x1 | IN endpoint
* ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT | 0x2 | OUT endpoint
* ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD | 0x3 | Reserved
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
*
* BIDIR (IN and OUT) endpoint
*/
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_BDIR 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
*
* IN endpoint
*/
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_INENDPT 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
*
* OUT endpoint
*/
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_OUTENDPT 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG1_GHWCFG1
*
* Reserved
*/
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_E_RSVD 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_MSB 31
/* The width in bits of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_WIDTH 32
/* The mask used to set the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG1_GHWCFG1 field value from a register. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG1_GHWCFG1 register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG1_GHWCFG1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GHWCFG1.
*/
struct ALT_USB_GLOB_GHWCFG1_s
{
const uint32_t ghwcfg1 : 32; /* ALT_USB_GLOB_GHWCFG1_GHWCFG1 */
};
/* The typedef declaration for register ALT_USB_GLOB_GHWCFG1. */
typedef volatile struct ALT_USB_GLOB_GHWCFG1_s ALT_USB_GLOB_GHWCFG1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GHWCFG1 register. */
#define ALT_USB_GLOB_GHWCFG1_RESET 0x00000000
/* The byte offset of the ALT_USB_GLOB_GHWCFG1 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG1_OFST 0x44
/* The address of the ALT_USB_GLOB_GHWCFG1 register. */
#define ALT_USB_GLOB_GHWCFG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG1_OFST))
/*
* Register : ghwcfg2
*
* User HW Config2 Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [2:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_OTGMOD
* [4:3] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_OTGARCH
* [5] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_SINGPNT
* [7:6] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
* [9:8] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_FSPHYTYPE
* [13:10] | R | 0xf | ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
* [17:14] | R | 0xf | ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
* [18] | R | 0x1 | ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT
* [19] | R | 0x1 | ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING
* [20] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT
* [21] | ??? | 0x0 | *UNDEFINED*
* [23:22] | R | 0x2 | ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
* [25:24] | R | 0x0 | ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
* [30:26] | R | 0x8 | ALT_USB_GLOB_GHWCFG2_TKNQDEPTH
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : otgmode
*
* Mode of Operation (OtgMode)
*
* 3'b000: HNP- and SRP-Capable OTG (Host & Device)
*
* 3'b001: SRP-Capable OTG (Host & Device)
*
* 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
*
* Device)
*
* 3'b011: SRP-Capable Device
*
* 3'b100: Non-OTG Device
*
* 3'b101: SRP-Capable Host
*
* 3'b110: Non-OTG Host
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP | 0x0 | HNP- and SRP-Capable OTG (Host & Device
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG | 0x1 | SRP-Capable OTG (Host & Device)
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP | 0x2 | Non-HNP and Non-SRP Capable OTG (Host & Device)
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD | 0x3 | SRP-Capable Device
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD | 0x4 | Non-OTG Device
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH | 0x5 | SRP-Capable Host
* ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH | 0x6 | Non-OTG Host
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* HNP- and SRP-Capable OTG (Host & Device
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_HNPSRP 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* SRP-Capable OTG (Host & Device)
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPOTG 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* Non-HNP and Non-SRP Capable OTG (Host & Device)
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NHNPNSRP 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* SRP-Capable Device
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPD 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* Non-OTG Device
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGD 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* SRP-Capable Host
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_SRPCAPH 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGMOD
*
* Non-OTG Host
*/
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_E_NONOTGH 0x6
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_MSB 2
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_WIDTH 3
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET_MSK 0x00000007
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGMOD register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_CLR_MSK 0xfffffff8
/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGMOD register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_GET(value) (((value) & 0x00000007) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG2_OTGMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_OTGMOD_SET(value) (((value) << 0) & 0x00000007)
/*
* Field : otgarch
*
* Architecture (OtgArch)
*
* 2'b00: Slave-Only
*
* 2'b01: External DMA
*
* 2'b10: Internal DMA
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-------------
* ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD | 0x2 | Internal DMA
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_OTGARCH
*
* Internal DMA
*/
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_E_DMAMOD 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_MSB 4
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET_MSK 0x00000018
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_OTGARCH register field value. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_CLR_MSK 0xffffffe7
/* The reset value of the ALT_USB_GLOB_GHWCFG2_OTGARCH register field. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_RESET 0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_OTGARCH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_GET(value) (((value) & 0x00000018) >> 3)
/* Produces a ALT_USB_GLOB_GHWCFG2_OTGARCH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_OTGARCH_SET(value) (((value) << 3) & 0x00000018)
/*
* Field : singpnt
*
* Point-to-Point (SingPnt)
*
* 1'b0: Multi-point application (hub and split support)
*
* 1'b1: Single-point application (no hub and split support)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------------------
* ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT | 0x1 | Single-point applicatio
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_SINGPNT
*
* Single-point applicatio
*/
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_E_SINGLEPOINT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_MSB 5
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_SINGPNT register field value. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GHWCFG2_SINGPNT register field. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_SINGPNT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GHWCFG2_SINGPNT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_SINGPNT_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : hsphytype
*
* High-Speed PHY Interface Type (HSPhyType)
*
* 2'b00: High-Speed interface not supported
*
* 2'b01: UTMI+
*
* 2'b10: ULPI
*
* 2'b11: UTMI+ and ULPI
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------
* ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS | 0x0 | High-Speed interface not supported
* ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI | 0x2 | ULPI
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
*
* High-Speed interface not supported
*/
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_NOHS 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_HSPHYTYPE
*
* ULPI
*/
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_E_ULPI 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_MSB 7
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET_MSK 0x000000c0
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_CLR_MSK 0xffffff3f
/* The reset value of the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_RESET 0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_HSPHYTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_GET(value) (((value) & 0x000000c0) >> 6)
/* Produces a ALT_USB_GLOB_GHWCFG2_HSPHYTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_HSPHYTYPE_SET(value) (((value) << 6) & 0x000000c0)
/*
* Field : fsphytype
*
* Full-Speed PHY Interface Type (FSPhyType)
*
* 2'b00: Full-speed interface not supported
*
* 2'b01: Dedicated full-speed interface
*
* 2'b10: FS pins shared with UTMI+ pins
*
* 2'b11: FS pins shared with ULPI pins
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED | 0x2 | ULPI Type
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_FSPHYTYPE
*
* ULPI Type
*/
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_E_FULLSPEED 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_MSB 9
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET_MSK 0x00000300
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_CLR_MSK 0xfffffcff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_FSPHYTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_GET(value) (((value) & 0x00000300) >> 8)
/* Produces a ALT_USB_GLOB_GHWCFG2_FSPHYTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_FSPHYTYPE_SET(value) (((value) << 8) & 0x00000300)
/*
* Field : numdeveps
*
* Number of Device Endpoints (NumDevEps)
*
* Indicates the number of device endpoints supported by the core
*
* in Device mode in addition to control endpoint 0. The range of
*
* this field is 1-15.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:--------------
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 | 0xa | End point 10
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 | 0xb | End point 11
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 | 0xc | End point 12
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 | 0xd | End point 13
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 | 0xe | End point 14
* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 0
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 1
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 2
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 3
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 4
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 5
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 6
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 7
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 8
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 9
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 10
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 11
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 12
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 13
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 14
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMDEVEPS
*
* End point 15
*/
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_MSB 13
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET_MSK 0x00003c00
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_CLR_MSK 0xffffc3ff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_RESET 0xf
/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMDEVEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_GET(value) (((value) & 0x00003c00) >> 10)
/* Produces a ALT_USB_GLOB_GHWCFG2_NUMDEVEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NUMDEVEPS_SET(value) (((value) << 10) & 0x00003c00)
/*
* Field : numhstchnl
*
* Number of Host Channels (NumHstChnl)
*
* Indicates the number of host channels supported by the core in
*
* Host mode. The range of this field is 0-15: 0 specifies 1 channel,
*
* 15 specifies 16 channels.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:----------------
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 | 0x0 | Host Channel 1
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 | 0x1 | Host Channel 2
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 | 0x2 | Host Channel 3
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 | 0x3 | Host Channel 4
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 | 0x4 | Host Channel 5
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 | 0x5 | Host Channel 6
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 | 0x6 | Host Channel 7
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 | 0x7 | Host Channel 8
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 | 0x8 | Host Channel 9
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 | 0x9 | Host Channel 10
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 | 0xa | Host Channel 11
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 | 0xb | Host Channel 12
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 | 0xc | Host Channel 13
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 | 0xd | Host Channel 14
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 | 0xe | Host Channel 15
* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 | 0xf | Host Channel 16
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 1
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 2
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH1 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 3
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH2 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 4
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH3 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 5
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH4 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 6
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH5 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 7
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH6 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 8
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH7 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 9
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH8 0x8
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 10
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH9 0x9
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 11
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH10 0xa
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 12
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH11 0xb
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 13
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH12 0xc
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 14
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH13 0xd
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 15
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH14 0xe
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL
*
* Host Channel 16
*/
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_E_HOSTCH15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_MSB 17
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET_MSK 0x0003c000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_CLR_MSK 0xfffc3fff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_RESET 0xf
/* Extracts the ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_GET(value) (((value) & 0x0003c000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL_SET(value) (((value) << 14) & 0x0003c000)
/*
* Field : periosupport
*
* Periodic OUT Channels Supported in Host Mode (PerioSupport)
*
* 1'b0: No
*
* 1'b1: Yes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END | 0x1 | Periodic OUT Channels Supported in Host Mode
* : | | Supported
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT
*
* Periodic OUT Channels Supported in Host Mode Supported
*/
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_MSB 18
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : dynfifosizing
*
* Dynamic FIFO Sizing Enabled (DynFifoSizing)
*
* 1'b0: No
*
* 1'b1: Yes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END | 0x1 | Dynamic FIFO Sizing Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING
*
* Dynamic FIFO Sizing Enabled
*/
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_MSB 19
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : multiprocintrpt
*
* Multi Processor Interrupt Enabled (MultiProcIntrpt)
*
* 1'b0: No
*
* 1'b1: Yes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------------
* ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD | 0x0 | No Multi Processor Interrupt Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT
*
* No Multi Processor Interrupt Enabled
*/
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_MSB 20
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : nptxqdepth
*
* Non-periodic Request Queue Depth (NPTxQDepth)
*
* 2'b00: 2
*
* 2'b01: 4
*
* 2'b10: 8
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO | 0x0 | Que size 2
* ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR | 0x1 | Que size 4
* ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT | 0x2 | Que size 8
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
*
* Que size 2
*/
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_TWO 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
*
* Que size 4
*/
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_FOUR 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH
*
* Que size 8
*/
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_E_EIGHT 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_MSB 23
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET_MSK 0x00c00000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_CLR_MSK 0xff3fffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_RESET 0x2
/* Extracts the ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_GET(value) (((value) & 0x00c00000) >> 22)
/* Produces a ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH_SET(value) (((value) << 22) & 0x00c00000)
/*
* Field : ptxqdepth
*
* Host Mode Periodic Request Queue Depth (PTxQDepth)
*
* 2'b00: 2
*
* 2'b01: 4
*
* 2'b10: 8
*
* 2'b11:16
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-------------
* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 | 0x0 | Que Depth 2
* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 | 0x1 | Que Depth 4
* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 | 0x2 | Que Depth 8
* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 | 0x3 | Que Depth 16
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
*
* Que Depth 2
*/
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE2 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
*
* Que Depth 4
*/
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE4 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
*
* Que Depth 8
*/
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE8 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG2_PTXQDEPTH
*
* Que Depth 16
*/
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_E_QUE16 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_MSB 25
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET_MSK 0x03000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_CLR_MSK 0xfcffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG2_PTXQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_GLOB_GHWCFG2_PTXQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_PTXQDEPTH_SET(value) (((value) << 24) & 0x03000000)
/*
* Field : tknqdepth
*
* Device Mode IN Token Sequence Learning Queue Depth
*
* (TknQDepth)
*
* Range: 0-30
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_MSB 30
/* The width in bits of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_WIDTH 5
/* The mask used to set the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET_MSK 0x7c000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_CLR_MSK 0x83ffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_RESET 0x8
/* Extracts the ALT_USB_GLOB_GHWCFG2_TKNQDEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_GET(value) (((value) & 0x7c000000) >> 26)
/* Produces a ALT_USB_GLOB_GHWCFG2_TKNQDEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG2_TKNQDEPTH_SET(value) (((value) << 26) & 0x7c000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GHWCFG2.
*/
struct ALT_USB_GLOB_GHWCFG2_s
{
const uint32_t otgmode : 3; /* ALT_USB_GLOB_GHWCFG2_OTGMOD */
const uint32_t otgarch : 2; /* ALT_USB_GLOB_GHWCFG2_OTGARCH */
const uint32_t singpnt : 1; /* ALT_USB_GLOB_GHWCFG2_SINGPNT */
const uint32_t hsphytype : 2; /* ALT_USB_GLOB_GHWCFG2_HSPHYTYPE */
const uint32_t fsphytype : 2; /* ALT_USB_GLOB_GHWCFG2_FSPHYTYPE */
const uint32_t numdeveps : 4; /* ALT_USB_GLOB_GHWCFG2_NUMDEVEPS */
const uint32_t numhstchnl : 4; /* ALT_USB_GLOB_GHWCFG2_NUMHSTCHNL */
const uint32_t periosupport : 1; /* ALT_USB_GLOB_GHWCFG2_PERIOSUPPORT */
const uint32_t dynfifosizing : 1; /* ALT_USB_GLOB_GHWCFG2_DYNFIFOSIZING */
const uint32_t multiprocintrpt : 1; /* ALT_USB_GLOB_GHWCFG2_MULTIPROCINTRPT */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t nptxqdepth : 2; /* ALT_USB_GLOB_GHWCFG2_NPTXQDEPTH */
const uint32_t ptxqdepth : 2; /* ALT_USB_GLOB_GHWCFG2_PTXQDEPTH */
const uint32_t tknqdepth : 5; /* ALT_USB_GLOB_GHWCFG2_TKNQDEPTH */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_GHWCFG2. */
typedef volatile struct ALT_USB_GLOB_GHWCFG2_s ALT_USB_GLOB_GHWCFG2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GHWCFG2 register. */
#define ALT_USB_GLOB_GHWCFG2_RESET 0x208ffc90
/* The byte offset of the ALT_USB_GLOB_GHWCFG2 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG2_OFST 0x48
/* The address of the ALT_USB_GLOB_GHWCFG2 register. */
#define ALT_USB_GLOB_GHWCFG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG2_OFST))
/*
* Register : ghwcfg3
*
* User HW Config3 Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-----------------------------------
* [3:0] | R | 0x8 | ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
* [6:4] | R | 0x6 | ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
* [7] | R | 0x1 | ALT_USB_GLOB_GHWCFG3_OTGEN
* [8] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_I2CINTSEL
* [9] | R | 0x1 | ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT
* [10] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_OPTFEATURE
* [11] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_RSTTYPE
* [12] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_ADPSUPPORT
* [13] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_HSICMOD
* [14] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_BCSUPPORT
* [15] | R | 0x0 | ALT_USB_GLOB_GHWCFG3_LPMMOD
* [31:16] | R | 0x1f80 | ALT_USB_GLOB_GHWCFG3_DFIFODEPTH
*
*/
/*
* Field : xfersizewidth
*
* Width of Transfer Size Counters (XferSizeWidth)
*
* 4'b0000: 11 bits
*
* 4'b0001: 12 bits
*
* ...
*
* 4'b1000: 19 bits
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 | 0x0 | Width of Transfer Size Counter 11 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 | 0x1 | Width of Transfer Size Counter 12 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 | 0x2 | Width of Transfer Size Counter 13 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 | 0x3 | Width of Transfer Size Counter 14 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 | 0x4 | Width of Transfer Size Counter 15 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 | 0x5 | Width of Transfer Size Counter 16 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 | 0x6 | Width of Transfer Size Counter 17 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 | 0x7 | Width of Transfer Size Counter 18 bits
* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 | 0x8 | Width of Transfer Size Counter 19 bits
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 11 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH11 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 12 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH12 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 13 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH13 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 14 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH14 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 15 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH15 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 16 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH16 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 17 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH17 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 18 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH18 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH
*
* Width of Transfer Size Counter 19 bits
*/
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_E_WIDTH19 0x8
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_MSB 3
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET_MSK 0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_CLR_MSK 0xfffffff0
/* The reset value of the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_RESET 0x8
/* Extracts the ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH_SET(value) (((value) << 0) & 0x0000000f)
/*
* Field : pktsizewidth
*
* Width of Packet Size Counters (PktSizeWidth)
*
* 3'b000: 4 bits
*
* 3'b001: 5 bits
*
* 3'b010: 6 bits
*
* 3'b011: 7 bits
*
* 3'b100: 8 bits
*
* 3'b101: 9 bits
*
* 3'b110: 10 bits
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 | 0x0 | Width of Packet Size Counter 4
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 | 0x1 | Width of Packet Size Counter 5
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 | 0x2 | Width of Packet Size Counter 6
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 | 0x3 | Width of Packet Size Counter 7
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 | 0x4 | Width of Packet Size Counter 8
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 | 0x5 | Width of Packet Size Counter 9
* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 | 0x6 | Width of Packet Size Counter 10
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 4
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS4 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 5
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS5 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 6
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS6 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 7
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS7 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 8
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS8 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 9
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS9 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH
*
* Width of Packet Size Counter 10
*/
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_E_BITS10 0x6
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_MSB 6
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_WIDTH 3
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET_MSK 0x00000070
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_CLR_MSK 0xffffff8f
/* The reset value of the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_RESET 0x6
/* Extracts the ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_GET(value) (((value) & 0x00000070) >> 4)
/* Produces a ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH_SET(value) (((value) << 4) & 0x00000070)
/*
* Field : otgen
*
* OTG Function Enabled (OtgEn)
*
* The application uses this bit to indicate the DWC_otg core's
*
* OTG capabilities.
*
* 1'b0: Not OTG capable
*
* 1'b1: OTG Capable
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG3_OTGEN_E_END | 0x1 | OTG Capable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OTGEN
*
* OTG Capable
*/
#define ALT_USB_GLOB_GHWCFG3_OTGEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_MSB 7
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OTGEN register field value. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GHWCFG3_OTGEN register field. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG3_OTGEN field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GHWCFG3_OTGEN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_OTGEN_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : i2cintsel
*
* I2C Selection (I2CIntSel)
*
* 1'b0: I2C Interface is not available on the core.
*
* 1'b1: I2C Interface is available on the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD | 0x0 | I2C Interface
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_I2CINTSEL
*
* I2C Interface
*/
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_MSB 8
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_I2CINTSEL field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_GLOB_GHWCFG3_I2CINTSEL register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_I2CINTSEL_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : vndctlsupt
*
* Vendor Control Interface Support (VndctlSupt)
*
* 1'b0: Vendor Control Interface is not available on the core.
*
* 1'b1: Vendor Control Interface is available.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END | 0x1 | Vendor Control Interface is not available on the
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT
*
* Vendor Control Interface is not available on the
*/
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_MSB 9
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : optfeature
*
* Optional Features Removed (OptFeature)
*
* Indicates whether the User ID register, GPIO interface ports,
*
* and SOF toggle and counter ports were removed For gate count
*
* optimization by enabling Remove Optional Features.
*
* 1'b0: No
*
* 1'b1: Yes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD | 0x0 | No Optional features
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_OPTFEATURE
*
* No Optional features
*/
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_MSB 10
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_OPTFEATURE field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_GLOB_GHWCFG3_OPTFEATURE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_OPTFEATURE_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : rsttype
*
* Reset Style For Clocked always Blocks in RTL (RstType)
*
* 1'b0: Asynchronous reset is used in the core
*
* 1'b1: Synchronous reset is used in the core
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------------
* ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END | 0x0 | Asynchronous reset is used in the core
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_RSTTYPE
*
* Asynchronous reset is used in the core
*/
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_E_END 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_MSB 11
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_RSTTYPE register field. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_RSTTYPE field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_GLOB_GHWCFG3_RSTTYPE register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_RSTTYPE_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : adpsupport
*
* This bit indicates whether ADP logic is present within or external to the HS OTG
*
* controller
*
* 0: No ADP logic present with HSOTG controller
*
* 1: ADP logic is present along with HSOTG controller.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-------------------------------------------------
* ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END | 0x1 | ADP logic is present along with HSOTG controller
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_ADPSUPPORT
*
* ADP logic is present along with HSOTG controller
*/
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_MSB 12
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_ADPSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_GLOB_GHWCFG3_ADPSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_ADPSUPPORT_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : hsicmode
*
* HSIC mode specified for Mode of Operation
*
* Value Range: 0 - 1
*
* 1: HSIC-capable with shared UTMI PHY interface
*
* 0: Non-HSIC-capable
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD | 0x0 | Non-HSIC-capable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_HSICMOD
*
* Non-HSIC-capable
*/
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_MSB 13
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_HSICMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_HSICMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_HSICMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_GLOB_GHWCFG3_HSICMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_HSICMOD_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : bcsupport
*
* This bit indicates the HS OTG controller support for Battery Charger.
*
* 0 - No Battery Charger Support
*
* 1 - Battery Charger support present.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD | 0x0 | No Battery Charger Support
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_BCSUPPORT
*
* No Battery Charger Support
*/
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_MSB 14
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_BCSUPPORT field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG3_BCSUPPORT register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_BCSUPPORT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : lpmmode
*
* LPM mode specified for Mode of Operation.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD | 0x0 | LPM disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG3_LPMMOD
*
* LPM disabled
*/
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_MSB 15
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_LPMMOD register field value. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_LPMMOD register field. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG3_LPMMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_GLOB_GHWCFG3_LPMMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_LPMMOD_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dfifodepth
*
* DFIFO Depth (DfifoDepth - EP_LOC_CNT)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 32
*
* Maximum value is 32,768
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_MSB 31
/* The width in bits of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET_MSK 0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_CLR_MSK 0x0000ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_RESET 0x1f80
/* Extracts the ALT_USB_GLOB_GHWCFG3_DFIFODEPTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GHWCFG3_DFIFODEPTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG3_DFIFODEPTH_SET(value) (((value) << 16) & 0xffff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GHWCFG3.
*/
struct ALT_USB_GLOB_GHWCFG3_s
{
const uint32_t xfersizewidth : 4; /* ALT_USB_GLOB_GHWCFG3_XFERSIZEWIDTH */
const uint32_t pktsizewidth : 3; /* ALT_USB_GLOB_GHWCFG3_PKTSIZEWIDTH */
const uint32_t otgen : 1; /* ALT_USB_GLOB_GHWCFG3_OTGEN */
const uint32_t i2cintsel : 1; /* ALT_USB_GLOB_GHWCFG3_I2CINTSEL */
const uint32_t vndctlsupt : 1; /* ALT_USB_GLOB_GHWCFG3_VNDCTLSUPT */
const uint32_t optfeature : 1; /* ALT_USB_GLOB_GHWCFG3_OPTFEATURE */
const uint32_t rsttype : 1; /* ALT_USB_GLOB_GHWCFG3_RSTTYPE */
const uint32_t adpsupport : 1; /* ALT_USB_GLOB_GHWCFG3_ADPSUPPORT */
const uint32_t hsicmode : 1; /* ALT_USB_GLOB_GHWCFG3_HSICMOD */
const uint32_t bcsupport : 1; /* ALT_USB_GLOB_GHWCFG3_BCSUPPORT */
const uint32_t lpmmode : 1; /* ALT_USB_GLOB_GHWCFG3_LPMMOD */
const uint32_t dfifodepth : 16; /* ALT_USB_GLOB_GHWCFG3_DFIFODEPTH */
};
/* The typedef declaration for register ALT_USB_GLOB_GHWCFG3. */
typedef volatile struct ALT_USB_GLOB_GHWCFG3_s ALT_USB_GLOB_GHWCFG3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GHWCFG3 register. */
#define ALT_USB_GLOB_GHWCFG3_RESET 0x1f8002e8
/* The byte offset of the ALT_USB_GLOB_GHWCFG3 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG3_OFST 0x4c
/* The address of the ALT_USB_GLOB_GHWCFG3 register. */
#define ALT_USB_GLOB_GHWCFG3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG3_OFST))
/*
* Register : ghwcfg4
*
* User HW Config4 Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-----------------------------------------
* [3:0] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS
* [4] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN
* [5] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_AHBFREQ
* [6] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_HIBERNATION
* [7] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION
* [13:8] | ??? | 0x0 | *UNDEFINED*
* [15:14] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH
* [19:16] | R | 0xf | ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
* [20] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_IDDGFLTR
* [21] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR
* [22] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_AVALIDFLTR
* [23] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_BVALIDFLTR
* [24] | R | 0x0 | ALT_USB_GLOB_GHWCFG4_SESSENDFLTR
* [25] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD
* [29:26] | R | 0xf | ALT_USB_GLOB_GHWCFG4_INEPS
* [30] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DMA_CFG
* [31] | R | 0x1 | ALT_USB_GLOB_GHWCFG4_DMA
*
*/
/*
* Field : numdevperioeps
*
* Number of Device Mode Periodic IN Endpoints
*
* (NumDevPerioEps)
*
* Range: 0-15
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_MSB 3
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET_MSK 0x0000000f
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_CLR_MSK 0xfffffff0
/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS_SET(value) (((value) << 0) & 0x0000000f)
/*
* Field : partialpwrdn
*
* Enable Partial Power Down (PartialPwrDn)
*
* 1'b0: Partial Power Down Not Enabled
*
* 1'b1: Partial Power Down Enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD | 0x0 | Partial Power Down disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN
*
* Partial Power Down disabled
*/
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_MSB 4
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ahbfreq
*
* Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
*
* 1'b0: No
*
* 1'b1: Yes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------------
* ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END | 0x1 | Minimum AHB Frequency Less Than 60 MH
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AHBFREQ
*
* Minimum AHB Frequency Less Than 60 MH
*/
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_MSB 5
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_GLOB_GHWCFG4_AHBFREQ register field. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_AHBFREQ field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_GLOB_GHWCFG4_AHBFREQ register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_AHBFREQ_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : hibernation
*
* Enable Hibernation (Hibernation)
*
* 1'b0: Hibernation feature not enabled
*
* 1'b1: Hibernation feature enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD | 0x0 | Hibernation feature disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_HIBERNATION
*
* Hibernation feature disabled
*/
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_MSB 6
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_GLOB_GHWCFG4_HIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_HIBERNATION field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_GLOB_GHWCFG4_HIBERNATION register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_HIBERNATION_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : extendedhibernation
*
* Enable Hibernation
*
* 1'b0: Extended Hibernation feature not enabled
*
* 1'b1: Extended Hibernation feature enabled
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_MSB 7
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : phydatawidth
*
* UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
*
* (PhyDataWidth)
*
* When a ULPI PHY is used, an internal wrapper converts ULPI to
*
* UTMI+ .
*
* 2'b00: 8 bits
*
* 2'b01: 16 bits
*
* 2'b10: 8/16 bits, software selectable
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_MSB 15
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_WIDTH 2
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : numctleps
*
* Number of Device Mode Control Endpoints in Addition to
*
* Endpoint 0 (NumCtlEps)
*
* Range: 0-15
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:--------------
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 | 0xa | End point 10
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 | 0xb | End point 11
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 | 0xc | End point 12
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 | 0xd | End point 13
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 | 0xe | End point 14
* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 0
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 1
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 2
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 3
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 4
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 5
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 6
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 7
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 8
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 9
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 10
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 11
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 12
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 13
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 14
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_NUMCTLEPS
*
* End point 15
*/
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_MSB 19
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET_MSK 0x000f0000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_CLR_MSK 0xfff0ffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_RESET 0xf
/* Extracts the ALT_USB_GLOB_GHWCFG4_NUMCTLEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_GET(value) (((value) & 0x000f0000) >> 16)
/* Produces a ALT_USB_GLOB_GHWCFG4_NUMCTLEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_NUMCTLEPS_SET(value) (((value) << 16) & 0x000f0000)
/*
* Field : iddgfltr
*
* IDDIG Filter Enable (IddgFltr)
*
* 1'b0: No filter
*
* 1'b1: Filter
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------
* ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD | 0x0 | Iddig Filter Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_IDDGFLTR
*
* Iddig Filter Disabled
*/
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_MSB 20
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_IDDGFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_GLOB_GHWCFG4_IDDGFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_IDDGFLTR_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : vbusvalidfltr
*
* VBUS Valid Filter Enabled (VBusValidFltr)
*
* 1'b0: No filter
*
* 1'b1: Filter
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------
* ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD | 0x0 | Vbus Valid Filter Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR
*
* Vbus Valid Filter Disabled
*/
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_MSB 21
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : avalidfltr
*
* a_valid Filter Enabled (AValidFltr)
*
* 1'b0: No filter
*
* 1'b1: Filter
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD | 0x0 | No filter
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_AVALIDFLTR
*
* No filter
*/
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_MSB 22
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_AVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_GLOB_GHWCFG4_AVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_AVALIDFLTR_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : bvalidfltr
*
* b_valid Filter Enabled (BValidFltr)
*
* 1'b0: No filter
*
* 1'b1: Filter
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD | 0x0 | No Filter
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_BVALIDFLTR
*
* No Filter
*/
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_MSB 23
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_BVALIDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_GLOB_GHWCFG4_BVALIDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_BVALIDFLTR_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : sessendfltr
*
* session_end Filter Enabled (SessEndFltr)
*
* 1'b0: No filter
*
* 1'b1: Filter
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------
* ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD | 0x0 | No filter
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_SESSENDFLTR
*
* No filter
*/
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_E_DISD 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_MSB 24
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_RESET 0x0
/* Extracts the ALT_USB_GLOB_GHWCFG4_SESSENDFLTR field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_GLOB_GHWCFG4_SESSENDFLTR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_SESSENDFLTR_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : dedfifomode
*
* Enable Dedicated Transmit FIFO For device IN Endpoints
*
* (DedFifoMode)
*
* 1'b0 : Dedicated Transmit FIFO Operation not enabled.
*
* 1'b1 : Dedicated Transmit FIFO Operation enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------
* ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END | 0x1 | Dedicated Transmit FIFO Operation enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD
*
* Dedicated Transmit FIFO Operation enabled
*/
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_MSB 25
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : ineps
*
* Number of Device Mode IN Endpoints Including Control
*
* Endpoints (INEps)
*
* Range 0 -15
*
* 0 : 1 IN Endpoint
*
* 1 : 2 IN Endpoints
*
* ....
*
* 15 : 16 IN Endpoints
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 | 0x0 | In Endpoint 1
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 | 0x1 | In Endpoint 2
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 | 0x2 | In Endpoint 3
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 | 0x3 | In Endpoint 4
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 | 0x4 | In Endpoint 5
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 | 0x5 | In Endpoint 6
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 | 0x6 | In Endpoint 7
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 | 0x7 | In Endpoint 8
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 | 0x8 | In Endpoint 9
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 | 0x9 | In Endpoint 10
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 | 0xa | In Endpoint 11
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 | 0xb | In Endpoint 12
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 | 0xc | In Endpoint 13
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 | 0xd | In Endpoint 14
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 | 0xe | In Endpoint 15
* ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 | 0xf | In Endpoint 16
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 1
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT1 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 2
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT2 0x1
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 3
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT3 0x2
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 4
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT4 0x3
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 5
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT5 0x4
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 6
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT6 0x5
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 7
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT7 0x6
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 8
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT8 0x7
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 9
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT9 0x8
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 10
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT10 0x9
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 11
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT11 0xa
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 12
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT12 0xb
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 13
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT13 0xc
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 14
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT14 0xd
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 15
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT15 0xe
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_INEPS
*
* In Endpoint 16
*/
#define ALT_USB_GLOB_GHWCFG4_INEPS_E_ENDPT16 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_MSB 29
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_WIDTH 4
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_SET_MSK 0x3c000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_INEPS register field value. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_CLR_MSK 0xc3ffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_INEPS register field. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_RESET 0xf
/* Extracts the ALT_USB_GLOB_GHWCFG4_INEPS field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_GET(value) (((value) & 0x3c000000) >> 26)
/* Produces a ALT_USB_GLOB_GHWCFG4_INEPS register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_INEPS_SET(value) (((value) << 26) & 0x3c000000)
/*
* Field : dma_configuration
*
* Scatter/Gather DMA configuration
*
* 1'b0: Non-Scatter/Gather DMA configuration
*
* 1'b1: Scatter/Gather DMA configuration
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------
* ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER | 0x0 | Non-Scatter/Gather DMA configuration
* ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER | 0x1 | Scatter/Gather DMA configuration
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
*
* Non-Scatter/Gather DMA configuration
*/
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_NONSCATTER 0x0
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA_CFG
*
* Scatter/Gather DMA configuration
*/
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_E_SCATTER 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_MSB 30
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA_CFG register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA_CFG field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_GLOB_GHWCFG4_DMA_CFG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CFG_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : dma
*
* Scatter/Gather DMA configuration
*
* 1'b0: Non Dynamic configuration
*
* 1'b1: Dynamic configuration
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:----------------------
* ALT_USB_GLOB_GHWCFG4_DMA_E_END | 0x1 | Dynamic configuration
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_GLOB_GHWCFG4_DMA
*
* Dynamic configuration
*/
#define ALT_USB_GLOB_GHWCFG4_DMA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_MSB 31
/* The width in bits of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_WIDTH 1
/* The mask used to set the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_GLOB_GHWCFG4_DMA register field value. */
#define ALT_USB_GLOB_GHWCFG4_DMA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_GLOB_GHWCFG4_DMA register field. */
#define ALT_USB_GLOB_GHWCFG4_DMA_RESET 0x1
/* Extracts the ALT_USB_GLOB_GHWCFG4_DMA field value from a register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_GLOB_GHWCFG4_DMA register field value suitable for setting the register. */
#define ALT_USB_GLOB_GHWCFG4_DMA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GHWCFG4.
*/
struct ALT_USB_GLOB_GHWCFG4_s
{
const uint32_t numdevperioeps : 4; /* ALT_USB_GLOB_GHWCFG4_NUMDEVPERIOEPS */
const uint32_t partialpwrdn : 1; /* ALT_USB_GLOB_GHWCFG4_PARTIALPWRDN */
const uint32_t ahbfreq : 1; /* ALT_USB_GLOB_GHWCFG4_AHBFREQ */
const uint32_t hibernation : 1; /* ALT_USB_GLOB_GHWCFG4_HIBERNATION */
const uint32_t extendedhibernation : 1; /* ALT_USB_GLOB_GHWCFG4_EXTENDEDHIBERNATION */
uint32_t : 6; /* *UNDEFINED* */
const uint32_t phydatawidth : 2; /* ALT_USB_GLOB_GHWCFG4_PHYDATAWIDTH */
const uint32_t numctleps : 4; /* ALT_USB_GLOB_GHWCFG4_NUMCTLEPS */
const uint32_t iddgfltr : 1; /* ALT_USB_GLOB_GHWCFG4_IDDGFLTR */
const uint32_t vbusvalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_VBUSVALIDFLTR */
const uint32_t avalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_AVALIDFLTR */
const uint32_t bvalidfltr : 1; /* ALT_USB_GLOB_GHWCFG4_BVALIDFLTR */
const uint32_t sessendfltr : 1; /* ALT_USB_GLOB_GHWCFG4_SESSENDFLTR */
const uint32_t dedfifomode : 1; /* ALT_USB_GLOB_GHWCFG4_DEDFIFOMOD */
const uint32_t ineps : 4; /* ALT_USB_GLOB_GHWCFG4_INEPS */
const uint32_t dma_configuration : 1; /* ALT_USB_GLOB_GHWCFG4_DMA_CFG */
const uint32_t dma : 1; /* ALT_USB_GLOB_GHWCFG4_DMA */
};
/* The typedef declaration for register ALT_USB_GLOB_GHWCFG4. */
typedef volatile struct ALT_USB_GLOB_GHWCFG4_s ALT_USB_GLOB_GHWCFG4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GHWCFG4 register. */
#define ALT_USB_GLOB_GHWCFG4_RESET 0xfe0f0020
/* The byte offset of the ALT_USB_GLOB_GHWCFG4 register from the beginning of the component. */
#define ALT_USB_GLOB_GHWCFG4_OFST 0x50
/* The address of the ALT_USB_GLOB_GHWCFG4 register. */
#define ALT_USB_GLOB_GHWCFG4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GHWCFG4_OFST))
/*
* Register : gdfifocfg
*
* Global DFIFO Configuration Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0x2000 | ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG
* [31:16] | RW | 0x1f80 | ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR
*
*/
/*
* Field : gdfifocfg
*
* GDFIFOCfg
*
* This field is for dynamic programming of the DFIFO Size. This value takes effect
*
* only when the application programs a non zero value to this register. The
*
* value programmed must conform to the guidelines described in 'FIFO RAM
*
* Allocation'. The DWC_otg core does not have any corrective logic
*
* if the FIFO sizes are programmed incorrectly.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_MSB 15
/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_RESET 0x2000
/* Extracts the ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG field value from a register. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG register field value suitable for setting the register. */
#define ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : epinfobaseaddr
*
* EPInfoBaseAddr
*
* This field provides the start address of the EP info controller.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_MSB 31
/* The width in bits of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET_MSK 0xffff0000
/* The mask used to clear the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_CLR_MSK 0x0000ffff
/* The reset value of the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_RESET 0x1f80
/* Extracts the ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR field value from a register. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR_SET(value) (((value) << 16) & 0xffff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_GDFIFOCFG.
*/
struct ALT_USB_GLOB_GDFIFOCFG_s
{
uint32_t gdfifocfg : 16; /* ALT_USB_GLOB_GDFIFOCFG_GDFIFOCFG */
uint32_t epinfobaseaddr : 16; /* ALT_USB_GLOB_GDFIFOCFG_EPINFOBASEADDR */
};
/* The typedef declaration for register ALT_USB_GLOB_GDFIFOCFG. */
typedef volatile struct ALT_USB_GLOB_GDFIFOCFG_s ALT_USB_GLOB_GDFIFOCFG_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_GDFIFOCFG register. */
#define ALT_USB_GLOB_GDFIFOCFG_RESET 0x1f802000
/* The byte offset of the ALT_USB_GLOB_GDFIFOCFG register from the beginning of the component. */
#define ALT_USB_GLOB_GDFIFOCFG_OFST 0x5c
/* The address of the ALT_USB_GLOB_GDFIFOCFG register. */
#define ALT_USB_GLOB_GDFIFOCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GDFIFOCFG_OFST))
/*
* Register : hptxfsiz
*
* Host Periodic Transmit FIFO Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:---------------------------------
* [14:0] | RW | 0x4000 | ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR
* [15] | ??? | 0x0 | *UNDEFINED*
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ptxfstaddr
*
* Host Periodic TxFIFO Start Address (PTxFStAddr)
*
* The power-on reset value of this register is the sum of the Largest Rx Data
*
* FIFO Depth and Largest Non-periodic Tx Data FIFO Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_MSB 14
/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_WIDTH 15
/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET_MSK 0x00007fff
/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_CLR_MSK 0xffff8000
/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_RESET 0x4000
/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
/*
* Field : ptxfsize
*
* Host Periodic TxFIFO Depth (PTxFSize)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the Largest Host
*
* Mode Periodic Tx Data FIFO Depth.
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_MSB 29
/* The width in bits of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_RESET 0x2000
/* Extracts the ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE field value from a register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE register field value suitable for setting the register. */
#define ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_HPTXFSIZ.
*/
struct ALT_USB_GLOB_HPTXFSIZ_s
{
uint32_t ptxfstaddr : 15; /* ALT_USB_GLOB_HPTXFSIZ_PTXFSTADDR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t ptxfsize : 14; /* ALT_USB_GLOB_HPTXFSIZ_PTXFSIZE */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_HPTXFSIZ. */
typedef volatile struct ALT_USB_GLOB_HPTXFSIZ_s ALT_USB_GLOB_HPTXFSIZ_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_HPTXFSIZ register. */
#define ALT_USB_GLOB_HPTXFSIZ_RESET 0x20004000
/* The byte offset of the ALT_USB_GLOB_HPTXFSIZ register from the beginning of the component. */
#define ALT_USB_GLOB_HPTXFSIZ_OFST 0x100
/* The address of the ALT_USB_GLOB_HPTXFSIZ register. */
#define ALT_USB_GLOB_HPTXFSIZ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_HPTXFSIZ_OFST))
/*
* Register : dieptxf1
*
* Device IN Endpoint Transmit FIFO Size Register 1
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [14:0] | RW | 0x4000 | ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR
* [15] | ??? | 0x0 | *UNDEFINED*
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_MSB 14
/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_WIDTH 15
/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET_MSK 0x00007fff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_CLR_MSK 0xffff8000
/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_RESET 0x4000
/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF1.
*/
struct ALT_USB_GLOB_DIEPTXF1_s
{
uint32_t inepntxfstaddr : 15; /* ALT_USB_GLOB_DIEPTXF1_INEPNTXFSTADDR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF1_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF1. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF1_s ALT_USB_GLOB_DIEPTXF1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF1 register. */
#define ALT_USB_GLOB_DIEPTXF1_RESET 0x20004000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF1 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF1_OFST 0x104
/* The address of the ALT_USB_GLOB_DIEPTXF1 register. */
#define ALT_USB_GLOB_DIEPTXF1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF1_OFST))
/*
* Register : dieptxf2
*
* Device IN Endpoint Transmit FIFO Size Register 2
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [14:0] | RW | 0x6000 | ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR
* [15] | ??? | 0x0 | *UNDEFINED*
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_MSB 14
/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_WIDTH 15
/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET_MSK 0x00007fff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_CLR_MSK 0xffff8000
/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_RESET 0x6000
/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_GET(value) (((value) & 0x00007fff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x00007fff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF2.
*/
struct ALT_USB_GLOB_DIEPTXF2_s
{
uint32_t inepntxfstaddr : 15; /* ALT_USB_GLOB_DIEPTXF2_INEPNTXFSTADDR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF2_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF2. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF2_s ALT_USB_GLOB_DIEPTXF2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF2 register. */
#define ALT_USB_GLOB_DIEPTXF2_RESET 0x20006000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF2 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF2_OFST 0x108
/* The address of the ALT_USB_GLOB_DIEPTXF2 register. */
#define ALT_USB_GLOB_DIEPTXF2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF2_OFST))
/*
* Register : dieptxf3
*
* Device IN Endpoint Transmit FIFO Size Register 3
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0x8000 | ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_RESET 0x8000
/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF3.
*/
struct ALT_USB_GLOB_DIEPTXF3_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF3_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF3_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF3. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF3_s ALT_USB_GLOB_DIEPTXF3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF3 register. */
#define ALT_USB_GLOB_DIEPTXF3_RESET 0x20008000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF3 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF3_OFST 0x10c
/* The address of the ALT_USB_GLOB_DIEPTXF3 register. */
#define ALT_USB_GLOB_DIEPTXF3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF3_OFST))
/*
* Register : dieptxf4
*
* Device IN Endpoint Transmit FIFO Size Register 4
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0xa000 | ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_RESET 0xa000
/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF4.
*/
struct ALT_USB_GLOB_DIEPTXF4_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF4_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF4_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF4. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF4_s ALT_USB_GLOB_DIEPTXF4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF4 register. */
#define ALT_USB_GLOB_DIEPTXF4_RESET 0x2000a000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF4 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF4_OFST 0x110
/* The address of the ALT_USB_GLOB_DIEPTXF4 register. */
#define ALT_USB_GLOB_DIEPTXF4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF4_OFST))
/*
* Register : dieptxf5
*
* Device IN Endpoint Transmit FIFO Size Register 5
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0xc000 | ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_RESET 0xc000
/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF5.
*/
struct ALT_USB_GLOB_DIEPTXF5_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF5_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF5_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF5. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF5_s ALT_USB_GLOB_DIEPTXF5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF5 register. */
#define ALT_USB_GLOB_DIEPTXF5_RESET 0x2000c000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF5 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF5_OFST 0x114
/* The address of the ALT_USB_GLOB_DIEPTXF5 register. */
#define ALT_USB_GLOB_DIEPTXF5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF5_OFST))
/*
* Register : dieptxf6
*
* Device IN Endpoint Transmit FIFO Size Register 6
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0xe000 | ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_RESET 0xe000
/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF6.
*/
struct ALT_USB_GLOB_DIEPTXF6_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF6_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF6_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF6. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF6_s ALT_USB_GLOB_DIEPTXF6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF6 register. */
#define ALT_USB_GLOB_DIEPTXF6_RESET 0x2000e000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF6 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF6_OFST 0x118
/* The address of the ALT_USB_GLOB_DIEPTXF6 register. */
#define ALT_USB_GLOB_DIEPTXF6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF6_OFST))
/*
* Register : dieptxf7
*
* Device IN Endpoint Transmit FIFO Size Register 7
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0x0 | ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_RESET 0x0
/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF7.
*/
struct ALT_USB_GLOB_DIEPTXF7_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF7_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF7_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF7. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF7_s ALT_USB_GLOB_DIEPTXF7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF7 register. */
#define ALT_USB_GLOB_DIEPTXF7_RESET 0x20000000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF7 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF7_OFST 0x11c
/* The address of the ALT_USB_GLOB_DIEPTXF7 register. */
#define ALT_USB_GLOB_DIEPTXF7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF7_OFST))
/*
* Register : dieptxf8
*
* Device IN Endpoint Transmit FIFO Size Register 8
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF8.
*/
struct ALT_USB_GLOB_DIEPTXF8_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF8_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF8_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF8. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF8_s ALT_USB_GLOB_DIEPTXF8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF8 register. */
#define ALT_USB_GLOB_DIEPTXF8_RESET 0x20002000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF8 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF8_OFST 0x120
/* The address of the ALT_USB_GLOB_DIEPTXF8 register. */
#define ALT_USB_GLOB_DIEPTXF8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF8_OFST))
/*
* Register : dieptxf9
*
* Device IN Endpoint Transmit FIFO Size Register 9
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | RW | 0x4000 | ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_RESET 0x4000
/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF9.
*/
struct ALT_USB_GLOB_DIEPTXF9_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF9_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF9_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF9. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF9_s ALT_USB_GLOB_DIEPTXF9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF9 register. */
#define ALT_USB_GLOB_DIEPTXF9_RESET 0x20004000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF9 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF9_OFST 0x124
/* The address of the ALT_USB_GLOB_DIEPTXF9 register. */
#define ALT_USB_GLOB_DIEPTXF9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF9_OFST))
/*
* Register : dieptxf10
*
* Device IN Endpoint Transmit FIFO Size Register 10
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0x6000 | ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_RESET 0x6000
/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF10.
*/
struct ALT_USB_GLOB_DIEPTXF10_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF10_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF10_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF10. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF10_s ALT_USB_GLOB_DIEPTXF10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF10 register. */
#define ALT_USB_GLOB_DIEPTXF10_RESET 0x20006000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF10 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF10_OFST 0x128
/* The address of the ALT_USB_GLOB_DIEPTXF10 register. */
#define ALT_USB_GLOB_DIEPTXF10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF10_OFST))
/*
* Register : dieptxf11
*
* Device IN Endpoint Transmit FIFO Size Register 11
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0x8000 | ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_RESET 0x8000
/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF11.
*/
struct ALT_USB_GLOB_DIEPTXF11_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF11_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF11_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF11. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF11_s ALT_USB_GLOB_DIEPTXF11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF11 register. */
#define ALT_USB_GLOB_DIEPTXF11_RESET 0x20008000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF11 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF11_OFST 0x12c
/* The address of the ALT_USB_GLOB_DIEPTXF11 register. */
#define ALT_USB_GLOB_DIEPTXF11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF11_OFST))
/*
* Register : dieptxf12
*
* Device IN Endpoint Transmit FIFO Size Register 12
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0xa000 | ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_RESET 0xa000
/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF12.
*/
struct ALT_USB_GLOB_DIEPTXF12_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF12_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF12_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF12. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF12_s ALT_USB_GLOB_DIEPTXF12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF12 register. */
#define ALT_USB_GLOB_DIEPTXF12_RESET 0x2000a000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF12 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF12_OFST 0x130
/* The address of the ALT_USB_GLOB_DIEPTXF12 register. */
#define ALT_USB_GLOB_DIEPTXF12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF12_OFST))
/*
* Register : dieptxf13
*
* Device IN Endpoint Transmit FIFO Size Register 13
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0xc000 | ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_RESET 0xc000
/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF13.
*/
struct ALT_USB_GLOB_DIEPTXF13_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF13_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF13_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF13. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF13_s ALT_USB_GLOB_DIEPTXF13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF13 register. */
#define ALT_USB_GLOB_DIEPTXF13_RESET 0x2000c000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF13 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF13_OFST 0x134
/* The address of the ALT_USB_GLOB_DIEPTXF13 register. */
#define ALT_USB_GLOB_DIEPTXF13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF13_OFST))
/*
* Register : dieptxf14
*
* Device IN Endpoint Transmit FIFO Size Register 14
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0xe000 | ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_RESET 0xe000
/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF14.
*/
struct ALT_USB_GLOB_DIEPTXF14_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF14_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF14_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF14. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF14_s ALT_USB_GLOB_DIEPTXF14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF14 register. */
#define ALT_USB_GLOB_DIEPTXF14_RESET 0x2000e000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF14 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF14_OFST 0x138
/* The address of the ALT_USB_GLOB_DIEPTXF14 register. */
#define ALT_USB_GLOB_DIEPTXF14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF14_OFST))
/*
* Register : dieptxf15
*
* Device IN Endpoint Transmit FIFO Size Register 15
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | RW | 0x0 | ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR
* [29:16] | RW | 0x2000 | ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP
* [31:30] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : inepntxfstaddr
*
* IN Endpoint FIFOn Transmit RAM Start Address
*
* (INEPnTxFStAddr)
*
* This field contains the memory start address For IN endpoint
*
* Transmit FIFOn (0<n< = 15).
*
* The power-on reset value of this register is specified as the
*
* Largest Rx Data FIFO Depth
*
* Programmed values must not exceed the power-on value.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_MSB 15
/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_WIDTH 16
/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_RESET 0x0
/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR field value from a register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : inepntxfdep
*
* IN Endpoint TxFIFO Depth (INEPnTxFDep)
*
* This value is in terms of 32-bit words.
*
* Minimum value is 16
*
* Maximum value is 32,768
*
* The power-on reset value of this register is specified as the
*
* Largest IN Endpoint FIFO number Depth
*
* Programmed values must not exceed the power-on value
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_MSB 29
/* The width in bits of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_WIDTH 14
/* The mask used to set the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET_MSK 0x3fff0000
/* The mask used to clear the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_CLR_MSK 0xc000ffff
/* The reset value of the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_RESET 0x2000
/* Extracts the ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP field value from a register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_GET(value) (((value) & 0x3fff0000) >> 16)
/* Produces a ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP register field value suitable for setting the register. */
#define ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP_SET(value) (((value) << 16) & 0x3fff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_GLOB_DIEPTXF15.
*/
struct ALT_USB_GLOB_DIEPTXF15_s
{
uint32_t inepntxfstaddr : 16; /* ALT_USB_GLOB_DIEPTXF15_INEPNTXFSTADDR */
uint32_t inepntxfdep : 14; /* ALT_USB_GLOB_DIEPTXF15_INEPNTXFDEP */
uint32_t : 2; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_GLOB_DIEPTXF15. */
typedef volatile struct ALT_USB_GLOB_DIEPTXF15_s ALT_USB_GLOB_DIEPTXF15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_GLOB_DIEPTXF15 register. */
#define ALT_USB_GLOB_DIEPTXF15_RESET 0x20000000
/* The byte offset of the ALT_USB_GLOB_DIEPTXF15 register from the beginning of the component. */
#define ALT_USB_GLOB_DIEPTXF15_OFST 0x13c
/* The address of the ALT_USB_GLOB_DIEPTXF15 register. */
#define ALT_USB_GLOB_DIEPTXF15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_DIEPTXF15_OFST))
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_USB_GLOB.
*/
struct ALT_USB_GLOB_s
{
volatile ALT_USB_GLOB_GOTGCTL_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */
volatile ALT_USB_GLOB_GOTGINT_t gotgint; /* ALT_USB_GLOB_GOTGINT */
volatile ALT_USB_GLOB_GAHBCFG_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */
volatile ALT_USB_GLOB_GUSBCFG_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */
volatile ALT_USB_GLOB_GRSTCTL_t grstctl; /* ALT_USB_GLOB_GRSTCTL */
volatile ALT_USB_GLOB_GINTSTS_t gintsts; /* ALT_USB_GLOB_GINTSTS */
volatile ALT_USB_GLOB_GINTMSK_t gintmsk; /* ALT_USB_GLOB_GINTMSK */
volatile ALT_USB_GLOB_GRXSTSR_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */
volatile ALT_USB_GLOB_GRXSTSP_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */
volatile ALT_USB_GLOB_GRXFSIZ_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */
volatile ALT_USB_GLOB_GNPTXFSIZ_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */
volatile ALT_USB_GLOB_GNPTXSTS_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */
volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
volatile ALT_USB_GLOB_GPVNDCTL_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */
volatile ALT_USB_GLOB_GGPIO_t ggpio; /* ALT_USB_GLOB_GGPIO */
volatile ALT_USB_GLOB_GUID_t guid; /* ALT_USB_GLOB_GUID */
volatile ALT_USB_GLOB_GSNPSID_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */
volatile ALT_USB_GLOB_GHWCFG1_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */
volatile ALT_USB_GLOB_GHWCFG2_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */
volatile ALT_USB_GLOB_GHWCFG3_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */
volatile ALT_USB_GLOB_GHWCFG4_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */
volatile uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */
volatile ALT_USB_GLOB_GDFIFOCFG_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */
volatile uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */
volatile ALT_USB_GLOB_HPTXFSIZ_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */
volatile ALT_USB_GLOB_DIEPTXF1_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */
volatile ALT_USB_GLOB_DIEPTXF2_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */
volatile ALT_USB_GLOB_DIEPTXF3_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */
volatile ALT_USB_GLOB_DIEPTXF4_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */
volatile ALT_USB_GLOB_DIEPTXF5_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */
volatile ALT_USB_GLOB_DIEPTXF6_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */
volatile ALT_USB_GLOB_DIEPTXF7_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */
volatile ALT_USB_GLOB_DIEPTXF8_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */
volatile ALT_USB_GLOB_DIEPTXF9_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */
volatile ALT_USB_GLOB_DIEPTXF10_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */
volatile ALT_USB_GLOB_DIEPTXF11_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */
volatile ALT_USB_GLOB_DIEPTXF12_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */
volatile ALT_USB_GLOB_DIEPTXF13_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */
volatile ALT_USB_GLOB_DIEPTXF14_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */
volatile ALT_USB_GLOB_DIEPTXF15_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */
};
/* The typedef declaration for register group ALT_USB_GLOB. */
typedef volatile struct ALT_USB_GLOB_s ALT_USB_GLOB_t;
/* The struct declaration for the raw register contents of register group ALT_USB_GLOB. */
struct ALT_USB_GLOB_raw_s
{
volatile uint32_t gotgctl; /* ALT_USB_GLOB_GOTGCTL */
volatile uint32_t gotgint; /* ALT_USB_GLOB_GOTGINT */
volatile uint32_t gahbcfg; /* ALT_USB_GLOB_GAHBCFG */
volatile uint32_t gusbcfg; /* ALT_USB_GLOB_GUSBCFG */
volatile uint32_t grstctl; /* ALT_USB_GLOB_GRSTCTL */
volatile uint32_t gintsts; /* ALT_USB_GLOB_GINTSTS */
volatile uint32_t gintmsk; /* ALT_USB_GLOB_GINTMSK */
volatile uint32_t grxstsr; /* ALT_USB_GLOB_GRXSTSR */
volatile uint32_t grxstsp; /* ALT_USB_GLOB_GRXSTSP */
volatile uint32_t grxfsiz; /* ALT_USB_GLOB_GRXFSIZ */
volatile uint32_t gnptxfsiz; /* ALT_USB_GLOB_GNPTXFSIZ */
volatile uint32_t gnptxsts; /* ALT_USB_GLOB_GNPTXSTS */
volatile uint32_t _pad_0x30_0x33; /* *UNDEFINED* */
volatile uint32_t gpvndctl; /* ALT_USB_GLOB_GPVNDCTL */
volatile uint32_t ggpio; /* ALT_USB_GLOB_GGPIO */
volatile uint32_t guid; /* ALT_USB_GLOB_GUID */
volatile uint32_t gsnpsid; /* ALT_USB_GLOB_GSNPSID */
volatile uint32_t ghwcfg1; /* ALT_USB_GLOB_GHWCFG1 */
volatile uint32_t ghwcfg2; /* ALT_USB_GLOB_GHWCFG2 */
volatile uint32_t ghwcfg3; /* ALT_USB_GLOB_GHWCFG3 */
volatile uint32_t ghwcfg4; /* ALT_USB_GLOB_GHWCFG4 */
volatile uint32_t _pad_0x54_0x5b[2]; /* *UNDEFINED* */
volatile uint32_t gdfifocfg; /* ALT_USB_GLOB_GDFIFOCFG */
volatile uint32_t _pad_0x60_0xff[40]; /* *UNDEFINED* */
volatile uint32_t hptxfsiz; /* ALT_USB_GLOB_HPTXFSIZ */
volatile uint32_t dieptxf1; /* ALT_USB_GLOB_DIEPTXF1 */
volatile uint32_t dieptxf2; /* ALT_USB_GLOB_DIEPTXF2 */
volatile uint32_t dieptxf3; /* ALT_USB_GLOB_DIEPTXF3 */
volatile uint32_t dieptxf4; /* ALT_USB_GLOB_DIEPTXF4 */
volatile uint32_t dieptxf5; /* ALT_USB_GLOB_DIEPTXF5 */
volatile uint32_t dieptxf6; /* ALT_USB_GLOB_DIEPTXF6 */
volatile uint32_t dieptxf7; /* ALT_USB_GLOB_DIEPTXF7 */
volatile uint32_t dieptxf8; /* ALT_USB_GLOB_DIEPTXF8 */
volatile uint32_t dieptxf9; /* ALT_USB_GLOB_DIEPTXF9 */
volatile uint32_t dieptxf10; /* ALT_USB_GLOB_DIEPTXF10 */
volatile uint32_t dieptxf11; /* ALT_USB_GLOB_DIEPTXF11 */
volatile uint32_t dieptxf12; /* ALT_USB_GLOB_DIEPTXF12 */
volatile uint32_t dieptxf13; /* ALT_USB_GLOB_DIEPTXF13 */
volatile uint32_t dieptxf14; /* ALT_USB_GLOB_DIEPTXF14 */
volatile uint32_t dieptxf15; /* ALT_USB_GLOB_DIEPTXF15 */
};
/* The typedef declaration for the raw register contents of register group ALT_USB_GLOB. */
typedef volatile struct ALT_USB_GLOB_raw_s ALT_USB_GLOB_raw_t;
#endif /* __ASSEMBLY__ */
/*
* Component : ALT_USB_HOST
*
*/
/*
* Register : hcfg
*
* Host Configuration Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [1:0] | RW | 0x0 | ALT_USB_HOST_HCFG_FSLSPCLKSEL
* [2] | RW | 0x0 | ALT_USB_HOST_HCFG_FSLSSUPP
* [6:3] | ??? | 0x0 | *UNDEFINED*
* [7] | RW | 0x0 | ALT_USB_HOST_HCFG_ENA32KHZS
* [15:8] | RW | 0x2 | ALT_USB_HOST_HCFG_RESVALID
* [22:16] | ??? | 0x0 | *UNDEFINED*
* [23] | RW | 0x0 | ALT_USB_HOST_HCFG_DESCDMA
* [25:24] | RW | 0x0 | ALT_USB_HOST_HCFG_FRLISTEN
* [26] | RW | 0x0 | ALT_USB_HOST_HCFG_PERSCHEDENA
* [30:27] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCFG_MODCHTIMEN
*
*/
/*
* Field : fslspclksel
*
* FS/LS PHY Clock Select (FSLSPclkSel)
*
* When the core is in FS Host mode
*
* 2'b00: PHY clock is running at 30/60 MHz
*
* 2'b01: PHY clock is running at 48 MHz
*
* Others: Reserved
*
* When the core is in LS Host mode
*
* 2'b00: PHY clock is running at 30/60 MHz. When the
*
* UTMI+/ULPI PHY Low Power mode is not selected, use
*
* 30/60 MHz.
*
* 2'b01: PHY clock is running at 48 MHz. When the UTMI+
*
* PHY Low Power mode is selected, use 48MHz If the PHY
*
* supplies a 48 MHz clock during LS mode.
*
* 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
*
* use 6 MHz when the UTMI+ PHY Low Power mode is
*
* selected and the PHY supplies a 6 MHz clock during LS
*
* mode. If you select a 6 MHz clock during LS mode, you must
*
* do a soft reset.
*
* 2'b11: Reserved
*
* Notes:
*
* When Core in FS mode, the internal and external clocks have the same frequency.
*
* When Core in LS mode,
*
* * If FSLSPclkSel = 2’b00: Internal and external clocks have the same frequency
*
* * If FSLSPclkSel = 2’b10: Internal clock is the divided by eight version of
* external 48 MHz clock
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------------------------
* ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 | 0x0 | PHY clock is running at 30/60 MHz
* ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 | 0x1 | PHY clock is running at 48 MHz
* ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 | 0x2 | PHY clock is running at 6 MHz
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
*
* PHY clock is running at 30/60 MHz
*/
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK3060 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
*
* PHY clock is running at 48 MHz
*/
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK48 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FSLSPCLKSEL
*
* PHY clock is running at 6 MHz
*/
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_E_CLK6 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_MSB 1
/* The width in bits of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET_MSK 0x00000003
/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_CLR_MSK 0xfffffffc
/* The reset value of the ALT_USB_HOST_HCFG_FSLSPCLKSEL register field. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_FSLSPCLKSEL field value from a register. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_HOST_HCFG_FSLSPCLKSEL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FSLSPCLKSEL_SET(value) (((value) << 0) & 0x00000003)
/*
* Field : fslssupp
*
* FS- and LS-Only Support (FSLSSupp)
*
* The application uses this bit to control the core's enumeration
*
* speed. Using this bit, the application can make the core
*
* enumerate as a FS host, even If the connected device supports
*
* HS traffic. Do not make changes to this field after initial
*
* programming.
*
* 1'b0: HS/FS/LS, based on the maximum speed supported by
*
* the connected device
*
* 1'b1: FS/LS-only, even If the connected device can support
*
* HS
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS | 0x0 | HS/FS/LS, based on the maximum speed supported
* : | | by the connected device
* ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS | 0x1 | FS/LS-only, even if the connected device can
* : | | support HS
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
*
* HS/FS/LS, based on the maximum speed supported by the connected device
*/
#define ALT_USB_HOST_HCFG_FSLSSUPP_E_HSFSLS 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FSLSSUPP
*
* FS/LS-only, even if the connected device can support HS
*/
#define ALT_USB_HOST_HCFG_FSLSSUPP_E_FSLS 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_MSB 2
/* The width in bits of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCFG_FSLSSUPP register field value. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCFG_FSLSSUPP register field. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_FSLSSUPP field value from a register. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCFG_FSLSSUPP register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FSLSSUPP_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : ena32khzs
*
* Enable 32 KHz Suspend mode (Ena32KHzS)
*
* This bit can be set only in FS PHY interface is selected.
*
* Else, this bit needs to be set to zero.
*
* When FS PHY interface is chosen and this bit is set,
*
* the core expects that the PHY clock during Suspend is switched
*
* from 48 MHz to 32 KHz.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD | 0x0 | USB 1.1 Full-Speed Not Selected
* ALT_USB_HOST_HCFG_ENA32KHZS_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface
* : | | selected
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
*
* USB 1.1 Full-Speed Not Selected
*/
#define ALT_USB_HOST_HCFG_ENA32KHZS_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_ENA32KHZS
*
* USB 1.1 Full-Speed Serial Transceiver Interface selected
*/
#define ALT_USB_HOST_HCFG_ENA32KHZS_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_MSB 7
/* The width in bits of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCFG_ENA32KHZS register field value. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCFG_ENA32KHZS register field. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_ENA32KHZS field value from a register. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCFG_ENA32KHZS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_ENA32KHZS_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : resvalid
*
* Resume Validation Period (ResValid)
*
* This field is effective only when HCFG.Ena32KHzS is set.
*
* It will control the resume period when the core resumes from suspend.
*
* The core counts for 'ResValid' number of clock cycles to detect a
*
* valid resume when this is set.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_MSB 15
/* The width in bits of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_WIDTH 8
/* The mask used to set the ALT_USB_HOST_HCFG_RESVALID register field value. */
#define ALT_USB_HOST_HCFG_RESVALID_SET_MSK 0x0000ff00
/* The mask used to clear the ALT_USB_HOST_HCFG_RESVALID register field value. */
#define ALT_USB_HOST_HCFG_RESVALID_CLR_MSK 0xffff00ff
/* The reset value of the ALT_USB_HOST_HCFG_RESVALID register field. */
#define ALT_USB_HOST_HCFG_RESVALID_RESET 0x2
/* Extracts the ALT_USB_HOST_HCFG_RESVALID field value from a register. */
#define ALT_USB_HOST_HCFG_RESVALID_GET(value) (((value) & 0x0000ff00) >> 8)
/* Produces a ALT_USB_HOST_HCFG_RESVALID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_RESVALID_SET(value) (((value) << 8) & 0x0000ff00)
/*
* Field : descdma
*
* Enable Scatter/gather DMA in Host mode (DescDMA).
*
* When the Scatter/Gather DMA option selected during configuration
*
* of the RTL, the application can set this bit during initialization
*
* to enable the Scatter/Gather DMA operation.
*
* NOTE: This bit must be modified only once after a reset.
*
* \The following combinations are available for programming:
*
* GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode
*
* GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid
*
* GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode
*
* GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCFG_DESCDMA_E_DISD | 0x0 | No Scatter/Gather DMA
* ALT_USB_HOST_HCFG_DESCDMA_E_END | 0x1 | Scatter/Gather DMA selected
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
*
* No Scatter/Gather DMA
*/
#define ALT_USB_HOST_HCFG_DESCDMA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_DESCDMA
*
* Scatter/Gather DMA selected
*/
#define ALT_USB_HOST_HCFG_DESCDMA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_MSB 23
/* The width in bits of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCFG_DESCDMA register field value. */
#define ALT_USB_HOST_HCFG_DESCDMA_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_HOST_HCFG_DESCDMA register field value. */
#define ALT_USB_HOST_HCFG_DESCDMA_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_HOST_HCFG_DESCDMA register field. */
#define ALT_USB_HOST_HCFG_DESCDMA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_DESCDMA field value from a register. */
#define ALT_USB_HOST_HCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_HOST_HCFG_DESCDMA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : frlisten
*
* Frame List Entries(FrListEn). The value in the register specifies the number
*
* of entries in the Frame list.
*
* This field is valid only in Scatter/Gather DMA mode.
*
* 2'b00: 8 Entries
*
* 2'b01: 16 Entries
*
* 2'b10: 32 Entries
*
* 2'b11: 63 Entries
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD | 0x0 | Reserved
* ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 | 0x1 | 8 Entries
* ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 | 0x2 | 16 Entries
* ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 | 0x3 | 32 Entries
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
*
* Reserved
*/
#define ALT_USB_HOST_HCFG_FRLISTEN_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
*
* 8 Entries
*/
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY8 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
*
* 16 Entries
*/
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY16 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_FRLISTEN
*
* 32 Entries
*/
#define ALT_USB_HOST_HCFG_FRLISTEN_E_ENTRY32 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_MSB 25
/* The width in bits of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
#define ALT_USB_HOST_HCFG_FRLISTEN_SET_MSK 0x03000000
/* The mask used to clear the ALT_USB_HOST_HCFG_FRLISTEN register field value. */
#define ALT_USB_HOST_HCFG_FRLISTEN_CLR_MSK 0xfcffffff
/* The reset value of the ALT_USB_HOST_HCFG_FRLISTEN register field. */
#define ALT_USB_HOST_HCFG_FRLISTEN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_FRLISTEN field value from a register. */
#define ALT_USB_HOST_HCFG_FRLISTEN_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_HOST_HCFG_FRLISTEN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_FRLISTEN_SET(value) (((value) << 24) & 0x03000000)
/*
* Field : perschedena
*
* Enable Periodic Scheduling (PerSchedEna):
*
* Applicable in host DDMA mode only.
*
* Enables periodic scheduling within the core. Initially, the bit is reset.
*
* The core will not process any periodic channels. As soon as this bit is set,
*
* the core will get ready to start scheduling periodic channels and
*
* sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core
*
* has enabled periodic scheduling. Once HCFG.PerSchedEna is set,
*
* the application is not supposed to again reset the bit unless HCFG.PerSchedStat
*
* is set. As soon as this bit is reset, the core will get ready to
*
* stop scheduling periodic channels and resets HCFG.PerSchedStat.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------------------------------
* ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD | 0x0 | Disables periodic scheduling within the core
* ALT_USB_HOST_HCFG_PERSCHEDENA_E_END | 0x1 | Enables periodic scheduling within the core
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
*
* Disables periodic scheduling within the core
*/
#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_PERSCHEDENA
*
* Enables periodic scheduling within the core
*/
#define ALT_USB_HOST_HCFG_PERSCHEDENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_MSB 26
/* The width in bits of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_HOST_HCFG_PERSCHEDENA register field value. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_HOST_HCFG_PERSCHEDENA register field. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_PERSCHEDENA field value from a register. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_HOST_HCFG_PERSCHEDENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_PERSCHEDENA_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : modechtimen
*
* Mode Change Ready Timer Enable (ModeChTimEn)
*
* This bit is used to enable/disable the Host core
*
* to wait 200 PHY clock cycles at the end of Resumeto change the opmode signal to
* the PHY to 00
*
* after Suspend or LPM.
*
* 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate
*
* of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00
*
* 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume
*
* to change the opmode from 2'b10 to 2'b00.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCFG_MODCHTIMEN_E_END | 0x0 | The Host core waits for either 200 PHY clock
* : | | cycles or a linestate of SE0 at the end of
* : | | resume to change the opmode from 0x2 to 0x0
* ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD | 0x1 | The Host core waits only for a linestate of SE0
* : | | at the end of resume to change the opmode from
* : | | 0x2 to 0x0
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
*
* The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the
* end of resume to change the opmode from 0x2 to 0x0
*/
#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_END 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCFG_MODCHTIMEN
*
* The Host core waits only for a linestate of SE0 at the end of resume to change
* the opmode from 0x2 to 0x0
*/
#define ALT_USB_HOST_HCFG_MODCHTIMEN_E_DISD 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_MSB 31
/* The width in bits of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCFG_MODCHTIMEN register field value. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCFG_MODCHTIMEN register field. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCFG_MODCHTIMEN field value from a register. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCFG_MODCHTIMEN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCFG_MODCHTIMEN_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCFG.
*/
struct ALT_USB_HOST_HCFG_s
{
uint32_t fslspclksel : 2; /* ALT_USB_HOST_HCFG_FSLSPCLKSEL */
uint32_t fslssupp : 1; /* ALT_USB_HOST_HCFG_FSLSSUPP */
uint32_t : 4; /* *UNDEFINED* */
uint32_t ena32khzs : 1; /* ALT_USB_HOST_HCFG_ENA32KHZS */
uint32_t resvalid : 8; /* ALT_USB_HOST_HCFG_RESVALID */
uint32_t : 7; /* *UNDEFINED* */
uint32_t descdma : 1; /* ALT_USB_HOST_HCFG_DESCDMA */
uint32_t frlisten : 2; /* ALT_USB_HOST_HCFG_FRLISTEN */
uint32_t perschedena : 1; /* ALT_USB_HOST_HCFG_PERSCHEDENA */
uint32_t : 4; /* *UNDEFINED* */
uint32_t modechtimen : 1; /* ALT_USB_HOST_HCFG_MODCHTIMEN */
};
/* The typedef declaration for register ALT_USB_HOST_HCFG. */
typedef volatile struct ALT_USB_HOST_HCFG_s ALT_USB_HOST_HCFG_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCFG register. */
#define ALT_USB_HOST_HCFG_RESET 0x00000200
/* The byte offset of the ALT_USB_HOST_HCFG register from the beginning of the component. */
#define ALT_USB_HOST_HCFG_OFST 0x0
/* The address of the ALT_USB_HOST_HCFG register. */
#define ALT_USB_HOST_HCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCFG_OFST))
/*
* Register : hfir
*
* Host Frame Interval Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-----------------------------
* [15:0] | RW | 0xea60 | ALT_USB_HOST_HFIR_FRINT
* [16] | RW | 0x0 | ALT_USB_HOST_HFIR_HFIRRLDCTL
* [31:17] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : frint
*
* Frame Interval (FrInt)
*
* The value that the application programs to this field specifies
*
* the interval between two consecutive SOFs (FS) or micro-
*
* SOFs (HS) or Keep-Alive tokens (HS). This field contains the
*
* number of PHY clocks that constitute the required frame
*
* interval. The Default value Set in this field For a FS operation
*
* when the PHY clock frequency is 60 MHz. The application can
*
* write a value to this register only after the Port Enable bit of the
*
* Host Port Control and Status register (HPRT.PrtEnaPort) has
*
* been Set. If no value is programmed, the core calculates the
*
* value based on the PHY clock specified in the FS/LS PHY
*
* Clock Select field of the Host Configuration register
*
* (HCFG.FSLSPclkSel). Do not change the value of this field
*
* after the initial configuration.
*
* 125 s * (PHY clock frequency For HS)
*
* 1 ms * (PHY clock frequency For FS/LS)
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_MSB 15
/* The width in bits of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HFIR_FRINT register field value. */
#define ALT_USB_HOST_HFIR_FRINT_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HFIR_FRINT register field value. */
#define ALT_USB_HOST_HFIR_FRINT_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_HOST_HFIR_FRINT register field. */
#define ALT_USB_HOST_HFIR_FRINT_RESET 0xea60
/* Extracts the ALT_USB_HOST_HFIR_FRINT field value from a register. */
#define ALT_USB_HOST_HFIR_FRINT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HFIR_FRINT register field value suitable for setting the register. */
#define ALT_USB_HOST_HFIR_FRINT_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : hfirrldctrl
*
* Reload Control (HFIRRldCtrl)
*
* This bit allows dynamic reloading of the HFIR register during run time.
*
* 1'b0 : The HFIR cannot be reloaded dynamically
*
* 1'b1: the HFIR can be dynamically reloaded during runtime.
*
* This bit needs to be programmed during initial configuration and its value
* should not be changed during runtime.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------------------
* ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD | 0x0 | The HFIR cannot be reloaded dynamically
* ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END | 0x1 | The HFIR can be dynamically reloaded during
* : | | runtime
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
*
* The HFIR cannot be reloaded dynamically
*/
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HFIR_HFIRRLDCTL
*
* The HFIR can be dynamically reloaded during runtime
*/
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_MSB 16
/* The width in bits of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HFIR_HFIRRLDCTL register field value. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HFIR_HFIRRLDCTL register field. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_RESET 0x0
/* Extracts the ALT_USB_HOST_HFIR_HFIRRLDCTL field value from a register. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HFIR_HFIRRLDCTL register field value suitable for setting the register. */
#define ALT_USB_HOST_HFIR_HFIRRLDCTL_SET(value) (((value) << 16) & 0x00010000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HFIR.
*/
struct ALT_USB_HOST_HFIR_s
{
uint32_t frint : 16; /* ALT_USB_HOST_HFIR_FRINT */
uint32_t hfirrldctrl : 1; /* ALT_USB_HOST_HFIR_HFIRRLDCTL */
uint32_t : 15; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HFIR. */
typedef volatile struct ALT_USB_HOST_HFIR_s ALT_USB_HOST_HFIR_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HFIR register. */
#define ALT_USB_HOST_HFIR_RESET 0x0000ea60
/* The byte offset of the ALT_USB_HOST_HFIR register from the beginning of the component. */
#define ALT_USB_HOST_HFIR_OFST 0x4
/* The address of the ALT_USB_HOST_HFIR register. */
#define ALT_USB_HOST_HFIR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFIR_OFST))
/*
* Register : hfnum
*
* Host Frame Number/Frame Time Remaining Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------
* [15:0] | R | 0x3fff | ALT_USB_HOST_HFNUM_FRNUM
* [31:16] | R | 0x0 | ALT_USB_HOST_HFNUM_FRREM
*
*/
/*
* Field : frnum
*
* Frame Number (FrNum)
*
* This field increments when a new SOF is transmitted on the
*
* USB, and is reset to 0 when it reaches 16'h3FFF.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:----------------------
* ALT_USB_HOST_HFNUM_FRNUM_E_INACT | 0x0 | No SOF is transmitted
* ALT_USB_HOST_HFNUM_FRNUM_E_ACT | 0x1 | SOF is transmitted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
*
* No SOF is transmitted
*/
#define ALT_USB_HOST_HFNUM_FRNUM_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HFNUM_FRNUM
*
* SOF is transmitted
*/
#define ALT_USB_HOST_HFNUM_FRNUM_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_MSB 15
/* The width in bits of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HFNUM_FRNUM register field value. */
#define ALT_USB_HOST_HFNUM_FRNUM_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HFNUM_FRNUM register field value. */
#define ALT_USB_HOST_HFNUM_FRNUM_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_HOST_HFNUM_FRNUM register field. */
#define ALT_USB_HOST_HFNUM_FRNUM_RESET 0x3fff
/* Extracts the ALT_USB_HOST_HFNUM_FRNUM field value from a register. */
#define ALT_USB_HOST_HFNUM_FRNUM_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HFNUM_FRNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HFNUM_FRNUM_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : frrem
*
* Frame Time Remaining (FrRem)
*
* Indicates the amount of time remaining in the current
*
* microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This
*
* field decrements on each PHY clock. When it reaches zero, this
*
* field is reloaded with the value in the Frame Interval register and
*
* a new SOF is transmitted on the USB.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_MSB 31
/* The width in bits of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HFNUM_FRREM register field value. */
#define ALT_USB_HOST_HFNUM_FRREM_SET_MSK 0xffff0000
/* The mask used to clear the ALT_USB_HOST_HFNUM_FRREM register field value. */
#define ALT_USB_HOST_HFNUM_FRREM_CLR_MSK 0x0000ffff
/* The reset value of the ALT_USB_HOST_HFNUM_FRREM register field. */
#define ALT_USB_HOST_HFNUM_FRREM_RESET 0x0
/* Extracts the ALT_USB_HOST_HFNUM_FRREM field value from a register. */
#define ALT_USB_HOST_HFNUM_FRREM_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_USB_HOST_HFNUM_FRREM register field value suitable for setting the register. */
#define ALT_USB_HOST_HFNUM_FRREM_SET(value) (((value) << 16) & 0xffff0000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HFNUM.
*/
struct ALT_USB_HOST_HFNUM_s
{
const uint32_t frnum : 16; /* ALT_USB_HOST_HFNUM_FRNUM */
const uint32_t frrem : 16; /* ALT_USB_HOST_HFNUM_FRREM */
};
/* The typedef declaration for register ALT_USB_HOST_HFNUM. */
typedef volatile struct ALT_USB_HOST_HFNUM_s ALT_USB_HOST_HFNUM_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HFNUM register. */
#define ALT_USB_HOST_HFNUM_RESET 0x00003fff
/* The byte offset of the ALT_USB_HOST_HFNUM register from the beginning of the component. */
#define ALT_USB_HOST_HFNUM_OFST 0x8
/* The address of the ALT_USB_HOST_HFNUM register. */
#define ALT_USB_HOST_HFNUM_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFNUM_OFST))
/*
* Register : hptxsts
*
* Host Periodic Transmit FIFO/Queue Status Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:----------------------------------
* [15:0] | R | 0x2000 | ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL
* [23:16] | R | 0x10 | ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
* [24] | R | 0x0 | Terminate
* [26:25] | R | 0x0 | Type
* [30:27] | R | 0x0 | Channel Endpoint Number
* [31] | R | 0x0 | Odd Even Micro Frame
*
*/
/*
* Field : ptxfspcavail
*
* Periodic Transmit Data FIFO Space Available
*
* (PTxFSpcAvail)
*
* Indicates the number of free locations available to be written to in the
* Periodic
*
* TxFIFO.
*
* Values are in terms of 32-bit words
*
* 16'h0 : Periodic TxFIFO is full
*
* 16'h1 : 1 word available
*
* 16'h2 : 2 words available
*
* 16'hn : n words available (where 0 n 32,768)
*
* 16’h8000 : 32,768 words
*
* Others : Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL field value from a register. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
/*
* Field : ptxqspcavail
*
* Periodic Transmit Request Queue Space Available
*
* (PTxQSpcAvail)
*
* Indicates the number of free locations available to be written in
*
* the Periodic Transmit Request Queue. This queue holds both IN
*
* and OUT requests.
*
* 8'h0: Periodic Transmit Request Queue is full
*
* 8'h1: 1 location available
*
* 8'h2: 2 locations available
*
* n: n locations available (0 <= n <= 16)
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL | 0x0 | Periodic Transmit Request Queue is full
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 | 0x1 | 1 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 | 0x2 | 2 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 | 0x3 | 3 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 | 0x4 | 4 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 | 0x5 | 5 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 | 0x6 | 6 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 | 0x7 | 7 location available
* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 | 0x8 | 8 location available
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* Periodic Transmit Request Queue is full
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FULL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 1 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 2 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 3 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 4 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 5 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 6 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 7 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL
*
* 8 location available
*/
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_E_FREE8 0x8
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_MSB 23
/* The width in bits of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_WIDTH 8
/* The mask used to set the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET_MSK 0x00ff0000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_CLR_MSK 0xff00ffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_RESET 0x10
/* Extracts the ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL field value from a register. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_GET(value) (((value) & 0x00ff0000) >> 16)
/* Produces a ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL_SET(value) (((value) << 16) & 0x00ff0000)
/*
* Field : Terminate - term
*
* Terminate last entry for selected channel/endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:----------------------------------
* ALT_USB_HOST_HPTXSTS_TERM_E_INACT | 0x0 | No termination
* ALT_USB_HOST_HPTXSTS_TERM_E_ACT | 0x1 | Terminate last entry for selected
* : | | channel/endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
*
* No termination
*/
#define ALT_USB_HOST_HPTXSTS_TERM_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TERM
*
* Terminate last entry for selected channel/endpoint
*/
#define ALT_USB_HOST_HPTXSTS_TERM_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_MSB 24
/* The width in bits of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPTXSTS_TERM register field value. */
#define ALT_USB_HOST_HPTXSTS_TERM_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TERM register field value. */
#define ALT_USB_HOST_HPTXSTS_TERM_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_TERM register field. */
#define ALT_USB_HOST_HPTXSTS_TERM_RESET 0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_TERM field value from a register. */
#define ALT_USB_HOST_HPTXSTS_TERM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_HOST_HPTXSTS_TERM register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_TERM_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : Type - type
*
* This indicates the Entry in the Periodic Tx Request Queue that is currently
* being processes by the MAC.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------
* ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT | 0x0 | IN/OUT type
* ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH | 0x1 | Zero-length packet type
* ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT | 0x2 | CSPLIT type
* ALT_USB_HOST_HPTXSTS_TYPE_E_DIS | 0x3 | Disable channel command
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
*
* IN/OUT type
*/
#define ALT_USB_HOST_HPTXSTS_TYPE_E_INOUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
*
* Zero-length packet type
*/
#define ALT_USB_HOST_HPTXSTS_TYPE_E_ZEROLNGTH 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
*
* CSPLIT type
*/
#define ALT_USB_HOST_HPTXSTS_TYPE_E_CSPLIT 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_TYPE
*
* Disable channel command
*/
#define ALT_USB_HOST_HPTXSTS_TYPE_E_DIS 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_MSB 26
/* The width in bits of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
#define ALT_USB_HOST_HPTXSTS_TYPE_SET_MSK 0x06000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_TYPE register field value. */
#define ALT_USB_HOST_HPTXSTS_TYPE_CLR_MSK 0xf9ffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_TYPE register field. */
#define ALT_USB_HOST_HPTXSTS_TYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_TYPE field value from a register. */
#define ALT_USB_HOST_HPTXSTS_TYPE_GET(value) (((value) & 0x06000000) >> 25)
/* Produces a ALT_USB_HOST_HPTXSTS_TYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_TYPE_SET(value) (((value) << 25) & 0x06000000)
/*
* Field : Channel Endpoint Number - chanendpt
*
* This indicates the channel endpoint number that is currently being processes by
* the MAC.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:--------------
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 | 0x0 | End point 1
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 | 0x1 | End point 2
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 | 0x2 | End point 3
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 | 0x3 | End point 4
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 | 0x4 | End point 5
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 | 0x5 | End point 6
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 | 0x6 | End point 7
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 | 0x7 | End point 8
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 | 0x8 | End point 9
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 | 0x9 | End point 10
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 | 0xa | End point 11
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 | 0xb | End point 12
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 | 0xc | End point 13
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 | 0xd | End point 14
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 | 0xe | End point 15
* ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 | 0xf | End point 16
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 1
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 2
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 3
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 4
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 5
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 6
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 7
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 8
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 9
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 10
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 11
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 12
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 13
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 14
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 15
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_CHANENDPT
*
* End point 16
*/
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_MSB 30
/* The width in bits of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET_MSK 0x78000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_CHANENDPT register field value. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_CLR_MSK 0x87ffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_CHANENDPT register field. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_RESET 0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_CHANENDPT field value from a register. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_GET(value) (((value) & 0x78000000) >> 27)
/* Produces a ALT_USB_HOST_HPTXSTS_CHANENDPT register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_CHANENDPT_SET(value) (((value) << 27) & 0x78000000)
/*
* Field : Odd Even Micro Frame - oddevnmframe
*
* This indicates the odd/even micro frame that is currently being processes by the
* MAC.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------------
* ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN | 0x0 | Send in even (micro)Frame
* ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD | 0x1 | Send in odd (micro)Frame
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
*
* Send in even (micro)Frame
*/
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_EVEN 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPTXSTS_ODDEVNMFRM
*
* Send in odd (micro)Frame
*/
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_E_ODD 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_MSB 31
/* The width in bits of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HPTXSTS_ODDEVNMFRM field value from a register. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HPTXSTS_ODDEVNMFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HPTXSTS_ODDEVNMFRM_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HPTXSTS.
*/
struct ALT_USB_HOST_HPTXSTS_s
{
const uint32_t ptxfspcavail : 16; /* ALT_USB_HOST_HPTXSTS_PTXFSPCAVAIL */
const uint32_t ptxqspcavail : 8; /* ALT_USB_HOST_HPTXSTS_PTXQSPCAVAIL */
const uint32_t term : 1; /* Terminate */
const uint32_t type : 2; /* Type */
const uint32_t chanendpt : 4; /* Channel Endpoint Number */
const uint32_t oddevnmframe : 1; /* Odd Even Micro Frame */
};
/* The typedef declaration for register ALT_USB_HOST_HPTXSTS. */
typedef volatile struct ALT_USB_HOST_HPTXSTS_s ALT_USB_HOST_HPTXSTS_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HPTXSTS register. */
#define ALT_USB_HOST_HPTXSTS_RESET 0x00102000
/* The byte offset of the ALT_USB_HOST_HPTXSTS register from the beginning of the component. */
#define ALT_USB_HOST_HPTXSTS_OFST 0x10
/* The address of the ALT_USB_HOST_HPTXSTS register. */
#define ALT_USB_HOST_HPTXSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPTXSTS_OFST))
/*
* Register : haint
*
* Host All Channels Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------
* [15:0] | R | 0x0 | ALT_USB_HOST_HAINT_HAINT
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : haint
*
* Channel Interrupt for channel no.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_MSB 15
/* The width in bits of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HAINT_HAINT register field value. */
#define ALT_USB_HOST_HAINT_HAINT_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HAINT_HAINT register field value. */
#define ALT_USB_HOST_HAINT_HAINT_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_HOST_HAINT_HAINT register field. */
#define ALT_USB_HOST_HAINT_HAINT_RESET 0x0
/* Extracts the ALT_USB_HOST_HAINT_HAINT field value from a register. */
#define ALT_USB_HOST_HAINT_HAINT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HAINT_HAINT register field value suitable for setting the register. */
#define ALT_USB_HOST_HAINT_HAINT_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HAINT.
*/
struct ALT_USB_HOST_HAINT_s
{
const uint32_t haint : 16; /* ALT_USB_HOST_HAINT_HAINT */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HAINT. */
typedef volatile struct ALT_USB_HOST_HAINT_s ALT_USB_HOST_HAINT_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HAINT register. */
#define ALT_USB_HOST_HAINT_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HAINT register from the beginning of the component. */
#define ALT_USB_HOST_HAINT_OFST 0x14
/* The address of the ALT_USB_HOST_HAINT register. */
#define ALT_USB_HOST_HAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINT_OFST))
/*
* Register : haintmsk
*
* Host All Channels Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [15:0] | RW | 0x0 | ALT_USB_HOST_HAINTMSK_HAINTMSK
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : haintmsk
*
* Channel Interrupt Msk for channel
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------
* ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK | 0x0 | Mask interrupt
* ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK | 0x1 | Unmask interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
*
* Mask interrupt
*/
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HAINTMSK_HAINTMSK
*
* Unmask interrupt
*/
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_MSB 15
/* The width in bits of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_WIDTH 16
/* The mask used to set the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_HOST_HAINTMSK_HAINTMSK register field value. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_HOST_HAINTMSK_HAINTMSK register field. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HAINTMSK_HAINTMSK field value from a register. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_HOST_HAINTMSK_HAINTMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HAINTMSK_HAINTMSK_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HAINTMSK.
*/
struct ALT_USB_HOST_HAINTMSK_s
{
uint32_t haintmsk : 16; /* ALT_USB_HOST_HAINTMSK_HAINTMSK */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HAINTMSK. */
typedef volatile struct ALT_USB_HOST_HAINTMSK_s ALT_USB_HOST_HAINTMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HAINTMSK register. */
#define ALT_USB_HOST_HAINTMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HAINTMSK register from the beginning of the component. */
#define ALT_USB_HOST_HAINTMSK_OFST 0x18
/* The address of the ALT_USB_HOST_HAINTMSK register. */
#define ALT_USB_HOST_HAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HAINTMSK_OFST))
/*
* Register : hflbaddr
*
* Host Frame List Base Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HFLBADDR_HFLBADDR
*
*/
/*
* Field : hflbaddr
*
* The starting address of the Frame list.
*
* This register is used only for Isochronous and Interrupt Channels.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_MSB 31
/* The width in bits of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HFLBADDR_HFLBADDR register field value. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HFLBADDR_HFLBADDR register field. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HFLBADDR_HFLBADDR field value from a register. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HFLBADDR_HFLBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HFLBADDR_HFLBADDR_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HFLBADDR.
*/
struct ALT_USB_HOST_HFLBADDR_s
{
uint32_t hflbaddr : 32; /* ALT_USB_HOST_HFLBADDR_HFLBADDR */
};
/* The typedef declaration for register ALT_USB_HOST_HFLBADDR. */
typedef volatile struct ALT_USB_HOST_HFLBADDR_s ALT_USB_HOST_HFLBADDR_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HFLBADDR register. */
#define ALT_USB_HOST_HFLBADDR_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HFLBADDR register from the beginning of the component. */
#define ALT_USB_HOST_HFLBADDR_OFST 0x1c
/* The address of the ALT_USB_HOST_HFLBADDR register. */
#define ALT_USB_HOST_HFLBADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HFLBADDR_OFST))
/*
* Register : hprt
*
* Host Port Control and Status Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:---------------------------------
* [0] | R | 0x0 | ALT_USB_HOST_HPRT_PRTCONNSTS
* [1] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTCONNDET
* [2] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTENA
* [3] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTENCHNG
* [4] | R | 0x0 | ALT_USB_HOST_HPRT_PRTOVRCURRACT
* [5] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
* [6] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTRES
* [7] | R-W once | 0x0 | ALT_USB_HOST_HPRT_PRTSUSP
* [8] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTRST
* [9] | ??? | 0x0 | *UNDEFINED*
* [11:10] | R | 0x0 | ALT_USB_HOST_HPRT_PRTLNSTS
* [12] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTPWR
* [16:13] | RW | 0x0 | ALT_USB_HOST_HPRT_PRTTSTCTL
* [18:17] | R | 0x0 | ALT_USB_HOST_HPRT_PRTSPD
* [31:19] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : prtconnsts
*
* Port Connect Status (PrtConnSts)
*
* 0: No device is attached to the port.
*
* 1: A device is attached to the port.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:----------------------------------
* ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED | 0x0 | No device is attached to the port
* ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED | 0x1 | A device is attached to the port
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
*
* No device is attached to the port
*/
#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_NOTATTACHED 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNSTS
*
* A device is attached to the port
*/
#define ALT_USB_HOST_HPRT_PRTCONNSTS_E_ATTACHED 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_MSB 0
/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTCONNSTS field value from a register. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HPRT_PRTCONNSTS register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTCONNSTS_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : prtconndet
*
* Port Connect Detected (PrtConnDet)
*
* The core sets this bit when a device connection is detected
*
* to trigger an interrupt to the application using the Host Port
*
* Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be
* set only by the core and the application should write 1 to clear it.The
* application must write a 1 to this bit to clear the
*
* interrupt.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT | 0x0 | Device connection detected
* ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT | 0x1 | No device connection detected
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
*
* Device connection detected
*/
#define ALT_USB_HOST_HPRT_PRTCONNDET_E_ACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTCONNDET
*
* No device connection detected
*/
#define ALT_USB_HOST_HPRT_PRTCONNDET_E_INACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_MSB 1
/* The width in bits of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTCONNDET register field value. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HPRT_PRTCONNDET register field. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTCONNDET field value from a register. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HPRT_PRTCONNDET register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTCONNDET_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : prtena
*
* Port Enable (PrtEna)
*
* A port is enabled only by the core after a reset sequence,
*
* and is disabled by an overcurrent condition, a disconnect
*
* condition, or by the application clearing this bit. The
*
* application cannot Set this bit by a register write. It can only
*
* clear it to disable the port by writing 1.. This bit does not trigger any
*
* interrupt to the application.
*
* 1'b0: Port disabled
*
* 1'b1: Port enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:--------------
* ALT_USB_HOST_HPRT_PRTENA_E_DISD | 0x0 | Port disabled
* ALT_USB_HOST_HPRT_PRTENA_E_END | 0x1 | Port enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
*
* Port disabled
*/
#define ALT_USB_HOST_HPRT_PRTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTENA
*
* Port enabled
*/
#define ALT_USB_HOST_HPRT_PRTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_MSB 2
/* The width in bits of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTENA register field value. */
#define ALT_USB_HOST_HPRT_PRTENA_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENA register field value. */
#define ALT_USB_HOST_HPRT_PRTENA_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HPRT_PRTENA register field. */
#define ALT_USB_HOST_HPRT_PRTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTENA field value from a register. */
#define ALT_USB_HOST_HPRT_PRTENA_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HPRT_PRTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTENA_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : prtenchng
*
* Port Enable/Disable Change (PrtEnChng)
*
* The core sets this bit when the status of the Port Enable bit
*
* [2] of this register changes.This bit can be set only by the core and the
* application should write 1 to clear it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT | 0x0 | Port Enable bit 2 no change
* ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT | 0x1 | Port Enable bit 2 changed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
*
* Port Enable bit 2 no change
*/
#define ALT_USB_HOST_HPRT_PRTENCHNG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTENCHNG
*
* Port Enable bit 2 changed
*/
#define ALT_USB_HOST_HPRT_PRTENCHNG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_MSB 3
/* The width in bits of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTENCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HPRT_PRTENCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTENCHNG field value from a register. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HPRT_PRTENCHNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTENCHNG_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : prtovrcurract
*
* Port Overcurrent Active (PrtOvrCurrAct)
*
* Indicates the overcurrent condition of the port.
*
* 1'b0: No overcurrent condition
*
* 1'b1: Overcurrent condition
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------
* ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT | 0x0 | No overcurrent condition
* ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT | 0x1 | Overcurrent condition
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
*
* No overcurrent condition
*/
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRACT
*
* Overcurrent condition
*/
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_MSB 4
/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRACT register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRACT field value from a register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRACT register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRACT_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : prtovrcurrchng
*
* Port Overcurrent Change (PrtOvrCurrChng)
*
* The core sets this bit when the status of the Port
*
* Overcurrent Active bit (bit 4) in this register changes.This bit can be set only
* by the core and the application should write 1 to clear it
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------
* ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT | 0x0 | Status of port overcurrent no change
* ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT | 0x1 | Status of port overcurrent changed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
*
* Status of port overcurrent no change
*/
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTOVRCURRCHNG
*
* Status of port overcurrent changed
*/
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_MSB 5
/* The width in bits of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTOVRCURRCHNG field value from a register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HPRT_PRTOVRCURRCHNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTOVRCURRCHNG_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : prtres
*
* Port Resume (PrtRes)
*
* The application sets this bit to drive resume signaling on the
*
* port. The core continues to drive the resume signal until the
*
* application clears this bit.
*
* If the core detects a USB remote wakeup sequence, as
*
* indicated by the Port Resume/Remote Wakeup Detected
*
* Interrupt bit of the Core Interrupt register
*
* (GINTSTS.WkUpInt), the core starts driving resume
*
* signaling without application intervention and clears this bit
*
* when it detects a disconnect condition. The read value of
*
* this bit indicates whether the core is currently driving
*
* resume signaling.
*
* 1'b0: No resume driven
*
* 1'b1: Resume driven
*
* When LPM is enabled, In L1 state the behavior of this bit is as follows:
*
* The application sets this bit to drive resume signaling on the port.
*
* The core continues to drive the resume signal until a pre-determined time
*
* specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote
*
* wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected
*
* Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt),
*
* the core starts driving resume signaling without application intervention
*
* and clears this bit at the end of resume.This bit can be set by both core or
* application
*
* and also cleared by core or application. This bit is cleared by the core even if
* there is
*
* no device connected to the Host.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HPRT_PRTRES_E_NORESUME | 0x0 | No resume driven
* ALT_USB_HOST_HPRT_PRTRES_E_RESUME | 0x1 | Resume driven
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
*
* No resume driven
*/
#define ALT_USB_HOST_HPRT_PRTRES_E_NORESUME 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTRES
*
* Resume driven
*/
#define ALT_USB_HOST_HPRT_PRTRES_E_RESUME 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_MSB 6
/* The width in bits of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTRES register field value. */
#define ALT_USB_HOST_HPRT_PRTRES_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRES register field value. */
#define ALT_USB_HOST_HPRT_PRTRES_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HPRT_PRTRES register field. */
#define ALT_USB_HOST_HPRT_PRTRES_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTRES field value from a register. */
#define ALT_USB_HOST_HPRT_PRTRES_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HPRT_PRTRES register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTRES_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : prtsusp
*
* Port Suspend (PrtSusp)
*
* The application sets this bit to put this port in Suspend
*
* mode. The core only stops sending SOFs when this is Set.
*
* To stop the PHY clock, the application must Set the Port
*
* Clock Stop bit, which asserts the suspend input pin of the
*
* PHY.
*
* The read value of this bit reflects the current suspend status
*
* of the port. This bit is cleared by the core after a remote
*
* wakeup signal is detected or the application sets the Port
*
* Reset bit or Port Resume bit in this register or the
*
* Resume/Remote Wakeup Detected Interrupt bit or
*
* Disconnect Detected Interrupt bit in the Core Interrupt
*
* register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
*
* respectively).This bit is cleared by the core even if there is
*
* no device connected to the Host.
*
* 1'b0: Port not in Suspend mode
*
* 1'b1: Port in Suspend mode
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------------
* ALT_USB_HOST_HPRT_PRTSUSP_E_INACT | 0x0 | Port not in Suspend mode
* ALT_USB_HOST_HPRT_PRTSUSP_E_ACT | 0x1 | Port in Suspend mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
*
* Port not in Suspend mode
*/
#define ALT_USB_HOST_HPRT_PRTSUSP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSUSP
*
* Port in Suspend mode
*/
#define ALT_USB_HOST_HPRT_PRTSUSP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_MSB 7
/* The width in bits of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
#define ALT_USB_HOST_HPRT_PRTSUSP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSUSP register field value. */
#define ALT_USB_HOST_HPRT_PRTSUSP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HPRT_PRTSUSP register field. */
#define ALT_USB_HOST_HPRT_PRTSUSP_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTSUSP field value from a register. */
#define ALT_USB_HOST_HPRT_PRTSUSP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HPRT_PRTSUSP register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTSUSP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : prtrst
*
* Port Reset (PrtRst)
*
* When the application sets this bit, a reset sequence is
*
* started on this port. The application must time the reset
*
* period and clear this bit after the reset sequence is
*
* complete.
*
* 1'b0: Port not in reset
*
* 1'b1: Port in reset
*
* The application must leave this bit Set For at least a
*
* minimum duration mentioned below to start a reset on the
*
* port. The application can leave it Set For another 10 ms in
*
* addition to the required minimum duration, before clearing
*
* the bit, even though there is no maximum limit Set by the
*
* USB standard.This bit is cleared by the core even if there is
*
* no device connected to the Host.
*
* High speed: 50 ms
*
* Full speed/Low speed: 10 ms
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:------------------
* ALT_USB_HOST_HPRT_PRTRST_E_DISD | 0x0 | Port not in reset
* ALT_USB_HOST_HPRT_PRTRST_E_END | 0x1 | Port in reset
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
*
* Port not in reset
*/
#define ALT_USB_HOST_HPRT_PRTRST_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTRST
*
* Port in reset
*/
#define ALT_USB_HOST_HPRT_PRTRST_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_MSB 8
/* The width in bits of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTRST register field value. */
#define ALT_USB_HOST_HPRT_PRTRST_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTRST register field value. */
#define ALT_USB_HOST_HPRT_PRTRST_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HPRT_PRTRST register field. */
#define ALT_USB_HOST_HPRT_PRTRST_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTRST field value from a register. */
#define ALT_USB_HOST_HPRT_PRTRST_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HPRT_PRTRST register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTRST_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : prtlnsts
*
* Port Line Status (PrtLnSts)
*
* Indicates the current logic level USB data lines
*
* Bit [10]: Logic level of D+
*
* Bit [11]: Logic level of D-
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD | 0x1 | Logic level of D+
* ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD | 0x2 | Logic level of D-
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
*
* Logic level of D+
*/
#define ALT_USB_HOST_HPRT_PRTLNSTS_E_PLUSD 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTLNSTS
*
* Logic level of D-
*/
#define ALT_USB_HOST_HPRT_PRTLNSTS_E_MINUSD 0x2
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_MSB 11
/* The width in bits of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_SET_MSK 0x00000c00
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTLNSTS register field value. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_CLR_MSK 0xfffff3ff
/* The reset value of the ALT_USB_HOST_HPRT_PRTLNSTS register field. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTLNSTS field value from a register. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_GET(value) (((value) & 0x00000c00) >> 10)
/* Produces a ALT_USB_HOST_HPRT_PRTLNSTS register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTLNSTS_SET(value) (((value) << 10) & 0x00000c00)
/*
* Field : prtpwr
*
* Port Power (PrtPwr)
*
* The application uses this field to control power to this port (write 1'b1 to set
* to 1'b1
*
* and write 1'b0 to set to 1'b0), and the core can clear this bit on an over
* current
*
* condition.
*
* 1'b0: Power off
*
* 1'b1: Power on
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:------------
* ALT_USB_HOST_HPRT_PRTPWR_E_OFF | 0x0 | Power off
* ALT_USB_HOST_HPRT_PRTPWR_E_ON | 0x1 | Power on
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
*
* Power off
*/
#define ALT_USB_HOST_HPRT_PRTPWR_E_OFF 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTPWR
*
* Power on
*/
#define ALT_USB_HOST_HPRT_PRTPWR_E_ON 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_MSB 12
/* The width in bits of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HPRT_PRTPWR register field value. */
#define ALT_USB_HOST_HPRT_PRTPWR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTPWR register field value. */
#define ALT_USB_HOST_HPRT_PRTPWR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HPRT_PRTPWR register field. */
#define ALT_USB_HOST_HPRT_PRTPWR_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTPWR field value from a register. */
#define ALT_USB_HOST_HPRT_PRTPWR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HPRT_PRTPWR register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTPWR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : prttstctl
*
* Port Test Control (PrtTstCtl)
*
* The application writes a nonzero value to this field to put the
*
* port into a Test mode, and the corresponding pattern is
*
* signaled on the port.
*
* 4'b0000: Test mode disabled
*
* 4'b0001: Test_J mode
*
* 4'b0010: Test_K mode
*
* 4'b0011: Test_SE0_NAK mode
*
* 4'b0100: Test_Packet mode
*
* 4'b0101: Test_Force_Enable
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-------------------
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD | 0x0 | Test mode disabled
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ | 0x1 | Test_J mode
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK | 0x2 | Test_K mode
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM | 0x4 | Test_Packet mode
* ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB | 0x5 | Test_force_Enable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test mode disabled
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test_J mode
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTJ 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test_K mode
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test_SE0_NAK mode
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTSN 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test_Packet mode
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTPM 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTTSTCTL
*
* Test_force_Enable
*/
#define ALT_USB_HOST_HPRT_PRTTSTCTL_E_TESTFENB 0x5
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_MSB 16
/* The width in bits of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET_MSK 0x0001e000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTTSTCTL register field value. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_CLR_MSK 0xfffe1fff
/* The reset value of the ALT_USB_HOST_HPRT_PRTTSTCTL register field. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTTSTCTL field value from a register. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_GET(value) (((value) & 0x0001e000) >> 13)
/* Produces a ALT_USB_HOST_HPRT_PRTTSTCTL register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTTSTCTL_SET(value) (((value) << 13) & 0x0001e000)
/*
* Field : prtspd
*
* Port Speed (PrtSpd)
*
* Indicates the speed of the device attached to this port.
*
* 2'b00: High speed
*
* 2'b01: Full speed
*
* 2'b10: Low speed
*
* 2'b11: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD | 0x0 | High speed
* ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD | 0x1 | Full speed
* ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD | 0x2 | Low speed
* ALT_USB_HOST_HPRT_PRTSPD_E_RSVD | 0x3 | Reserved
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
*
* High speed
*/
#define ALT_USB_HOST_HPRT_PRTSPD_E_HIGHSPD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
*
* Full speed
*/
#define ALT_USB_HOST_HPRT_PRTSPD_E_FULLSPD 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
*
* Low speed
*/
#define ALT_USB_HOST_HPRT_PRTSPD_E_LOWSPD 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HPRT_PRTSPD
*
* Reserved
*/
#define ALT_USB_HOST_HPRT_PRTSPD_E_RSVD 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_MSB 18
/* The width in bits of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HPRT_PRTSPD register field value. */
#define ALT_USB_HOST_HPRT_PRTSPD_SET_MSK 0x00060000
/* The mask used to clear the ALT_USB_HOST_HPRT_PRTSPD register field value. */
#define ALT_USB_HOST_HPRT_PRTSPD_CLR_MSK 0xfff9ffff
/* The reset value of the ALT_USB_HOST_HPRT_PRTSPD register field. */
#define ALT_USB_HOST_HPRT_PRTSPD_RESET 0x0
/* Extracts the ALT_USB_HOST_HPRT_PRTSPD field value from a register. */
#define ALT_USB_HOST_HPRT_PRTSPD_GET(value) (((value) & 0x00060000) >> 17)
/* Produces a ALT_USB_HOST_HPRT_PRTSPD register field value suitable for setting the register. */
#define ALT_USB_HOST_HPRT_PRTSPD_SET(value) (((value) << 17) & 0x00060000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HPRT.
*/
struct ALT_USB_HOST_HPRT_s
{
const uint32_t prtconnsts : 1; /* ALT_USB_HOST_HPRT_PRTCONNSTS */
uint32_t prtconndet : 1; /* ALT_USB_HOST_HPRT_PRTCONNDET */
uint32_t prtena : 1; /* ALT_USB_HOST_HPRT_PRTENA */
uint32_t prtenchng : 1; /* ALT_USB_HOST_HPRT_PRTENCHNG */
const uint32_t prtovrcurract : 1; /* ALT_USB_HOST_HPRT_PRTOVRCURRACT */
uint32_t prtovrcurrchng : 1; /* ALT_USB_HOST_HPRT_PRTOVRCURRCHNG */
uint32_t prtres : 1; /* ALT_USB_HOST_HPRT_PRTRES */
uint32_t prtsusp : 1; /* ALT_USB_HOST_HPRT_PRTSUSP */
uint32_t prtrst : 1; /* ALT_USB_HOST_HPRT_PRTRST */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t prtlnsts : 2; /* ALT_USB_HOST_HPRT_PRTLNSTS */
uint32_t prtpwr : 1; /* ALT_USB_HOST_HPRT_PRTPWR */
uint32_t prttstctl : 4; /* ALT_USB_HOST_HPRT_PRTTSTCTL */
const uint32_t prtspd : 2; /* ALT_USB_HOST_HPRT_PRTSPD */
uint32_t : 13; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HPRT. */
typedef volatile struct ALT_USB_HOST_HPRT_s ALT_USB_HOST_HPRT_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HPRT register. */
#define ALT_USB_HOST_HPRT_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HPRT register from the beginning of the component. */
#define ALT_USB_HOST_HPRT_OFST 0x40
/* The address of the ALT_USB_HOST_HPRT register. */
#define ALT_USB_HOST_HPRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HPRT_OFST))
/*
* Register : hcchar0
*
* Host Channel 0 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR0_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR0_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR0_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR0_MPS register field value. */
#define ALT_USB_HOST_HCCHAR0_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_MPS register field value. */
#define ALT_USB_HOST_HCCHAR0_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR0_MPS register field. */
#define ALT_USB_HOST_HCCHAR0_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR0_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR0_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR0_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR0_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR | 0x0 | OUT
* ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR | 0x1 | IN
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
*
* OUT
*/
#define ALT_USB_HOST_HCCHAR0_EPDIR_E_OUTDIR 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPDIR
*
* IN
*/
#define ALT_USB_HOST_HCCHAR0_EPDIR_E_INDIR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR0_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
* ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
*
* Communicating with non lowspeed
*/
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_NONLOWSPEED 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_LSPDDEV
*
* Communicating with lowspeed
*/
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_E_LOWSPEED 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR0_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR0_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR0_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
* ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
*
* Reserved This field yields undefined results
*/
#define ALT_USB_HOST_HCCHAR0_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR0_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR0_EC register field value. */
#define ALT_USB_HOST_HCCHAR0_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_EC register field value. */
#define ALT_USB_HOST_HCCHAR0_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_EC register field. */
#define ALT_USB_HOST_HCCHAR0_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR0_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR0_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR0_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR0_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT | 0x0 | No activity
* ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
*
* No activity
*/
#define ALT_USB_HOST_HCCHAR0_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHDIS
*
* Stop transmitting/receiving data
*/
#define ALT_USB_HOST_HCCHAR0_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR0_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR0_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
* : | | buffer with data is setup and this channel can
* : | | access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR0_CHENA_E_NOTRDY 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR0_CHENA
*
* Indicates that the descriptor structure and data buffer with data is setup and
* this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR0_CHENA_E_RDY 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR0_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR0_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR0_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR0_CHENA register field. */
#define ALT_USB_HOST_HCCHAR0_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR0_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR0_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR0_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR0_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR0.
*/
struct ALT_USB_HOST_HCCHAR0_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR0_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR0_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR0_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR0_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR0_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR0_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR0_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR0_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR0_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR0_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR0. */
typedef volatile struct ALT_USB_HOST_HCCHAR0_s ALT_USB_HOST_HCCHAR0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR0 register. */
#define ALT_USB_HOST_HCCHAR0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR0 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR0_OFST 0x100
/* The address of the ALT_USB_HOST_HCCHAR0 register. */
#define ALT_USB_HOST_HCCHAR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR0_OFST))
/*
* Register : hcsplt0
*
* Host Channel 0 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT0_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT0_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT0_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT0_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT0_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT0_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT0_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT0_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT0_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT0_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT0_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT0_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT0_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT0_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT0_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT0_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT0_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT0_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT0_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT0.
*/
struct ALT_USB_HOST_HCSPLT0_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT0_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT0_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT0_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT0_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT0_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT0. */
typedef volatile struct ALT_USB_HOST_HCSPLT0_s ALT_USB_HOST_HCSPLT0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT0 register. */
#define ALT_USB_HOST_HCSPLT0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT0 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT0_OFST 0x104
/* The address of the ALT_USB_HOST_HCSPLT0 register. */
#define ALT_USB_HOST_HCSPLT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT0_OFST))
/*
* Register : hcint0
*
* Host Channel 0 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT0_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT0_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT0_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT0_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT0_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT0_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT0_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT0_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT0_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT0_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT0_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT0_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT0_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT0_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT0_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT0_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT0_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT0_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT0_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT0_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT0_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT0_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT0_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT0_CHHLTD register field. */
#define ALT_USB_HOST_HCINT0_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT0_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT0_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT0_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT0_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT0_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT0_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_AHBERR register field value. */
#define ALT_USB_HOST_HCINT0_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT0_AHBERR register field value. */
#define ALT_USB_HOST_HCINT0_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT0_AHBERR register field. */
#define ALT_USB_HOST_HCINT0_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT0_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT0_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT0_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT0_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_STALL register field value. */
#define ALT_USB_HOST_HCINT0_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT0_STALL register field value. */
#define ALT_USB_HOST_HCINT0_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT0_STALL register field. */
#define ALT_USB_HOST_HCINT0_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_STALL field value from a register. */
#define ALT_USB_HOST_HCINT0_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT0_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT0_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT0_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT0_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT0_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_NAK register field value. */
#define ALT_USB_HOST_HCINT0_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT0_NAK register field value. */
#define ALT_USB_HOST_HCINT0_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT0_NAK register field. */
#define ALT_USB_HOST_HCINT0_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_NAK field value from a register. */
#define ALT_USB_HOST_HCINT0_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT0_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT0_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT0_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT0_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT0_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_ACK register field value. */
#define ALT_USB_HOST_HCINT0_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT0_ACK register field value. */
#define ALT_USB_HOST_HCINT0_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT0_ACK register field. */
#define ALT_USB_HOST_HCINT0_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_ACK field value from a register. */
#define ALT_USB_HOST_HCINT0_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT0_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT0_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT0_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT0_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT0_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_NYET register field value. */
#define ALT_USB_HOST_HCINT0_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT0_NYET register field value. */
#define ALT_USB_HOST_HCINT0_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT0_NYET register field. */
#define ALT_USB_HOST_HCINT0_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_NYET field value from a register. */
#define ALT_USB_HOST_HCINT0_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT0_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT0_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT0_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT0_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT0_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_XACTERR register field value. */
#define ALT_USB_HOST_HCINT0_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT0_XACTERR register field value. */
#define ALT_USB_HOST_HCINT0_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT0_XACTERR register field. */
#define ALT_USB_HOST_HCINT0_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT0_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT0_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT0_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT0_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT0_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT0_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_BBLERR register field value. */
#define ALT_USB_HOST_HCINT0_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT0_BBLERR register field value. */
#define ALT_USB_HOST_HCINT0_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT0_BBLERR register field. */
#define ALT_USB_HOST_HCINT0_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT0_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT0_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT0_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT0_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT0_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT0_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT0_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT0_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT0_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT0_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT0_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT0_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT0_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT0_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT0_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT0_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT0_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT0_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT0_BNAINTR register field. */
#define ALT_USB_HOST_HCINT0_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT0_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT0_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT0.
*/
struct ALT_USB_HOST_HCINT0_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT0_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT0_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT0_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT0_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT0_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT0_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT0_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT0_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT0_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT0_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT0_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT0_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT0_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT0_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT0. */
typedef volatile struct ALT_USB_HOST_HCINT0_s ALT_USB_HOST_HCINT0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT0 register. */
#define ALT_USB_HOST_HCINT0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT0 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT0_OFST 0x108
/* The address of the ALT_USB_HOST_HCINT0 register. */
#define ALT_USB_HOST_HCINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT0_OFST))
/*
* Register : hcintmsk0
*
* Host Channel 0 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK0_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK0_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK0_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK0_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK0_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK0_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK0_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK0_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK0_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK0_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK0_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK0_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK0_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK0.
*/
struct ALT_USB_HOST_HCINTMSK0_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK0_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK0_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK0_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK0_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK0_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK0_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK0_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK0_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK0. */
typedef volatile struct ALT_USB_HOST_HCINTMSK0_s ALT_USB_HOST_HCINTMSK0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK0 register. */
#define ALT_USB_HOST_HCINTMSK0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK0 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK0_OFST 0x10c
/* The address of the ALT_USB_HOST_HCINTMSK0 register. */
#define ALT_USB_HOST_HCINTMSK0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK0_OFST))
/*
* Register : hctsiz0
*
* Host Channel 0 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ0_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ0_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ0_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ0_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ0_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_PID register field value. */
#define ALT_USB_HOST_HCTSIZ0_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_PID register field value. */
#define ALT_USB_HOST_HCTSIZ0_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_PID register field. */
#define ALT_USB_HOST_HCTSIZ0_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ0_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ0_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ0_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ0_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ0_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ0_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ0_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ0_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ0.
*/
struct ALT_USB_HOST_HCTSIZ0_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ0_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ0_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ0_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ0_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ0. */
typedef volatile struct ALT_USB_HOST_HCTSIZ0_s ALT_USB_HOST_HCTSIZ0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ0 register. */
#define ALT_USB_HOST_HCTSIZ0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ0 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ0_OFST 0x110
/* The address of the ALT_USB_HOST_HCTSIZ0 register. */
#define ALT_USB_HOST_HCTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ0_OFST))
/*
* Register : hcdma0
*
* Host Channel 0 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA0_HCDMA0
*
*/
/*
* Field : hcdma0
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA0_HCDMA0 register field value. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA0_HCDMA0 register field. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA0_HCDMA0 field value from a register. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA0_HCDMA0 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA0_HCDMA0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA0.
*/
struct ALT_USB_HOST_HCDMA0_s
{
uint32_t hcdma0 : 32; /* ALT_USB_HOST_HCDMA0_HCDMA0 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA0. */
typedef volatile struct ALT_USB_HOST_HCDMA0_s ALT_USB_HOST_HCDMA0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA0 register. */
#define ALT_USB_HOST_HCDMA0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA0 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA0_OFST 0x114
/* The address of the ALT_USB_HOST_HCDMA0 register. */
#define ALT_USB_HOST_HCDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA0_OFST))
/*
* Register : hcdmab0
*
* Host Channel 0 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB0_HCDMAB0
*
*/
/*
* Field : hcdmab0
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB0_HCDMAB0 register field. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB0_HCDMAB0 field value from a register. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB0_HCDMAB0 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB0_HCDMAB0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB0.
*/
struct ALT_USB_HOST_HCDMAB0_s
{
uint32_t hcdmab0 : 32; /* ALT_USB_HOST_HCDMAB0_HCDMAB0 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB0. */
typedef volatile struct ALT_USB_HOST_HCDMAB0_s ALT_USB_HOST_HCDMAB0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB0 register. */
#define ALT_USB_HOST_HCDMAB0_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB0 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB0_OFST 0x11c
/* The address of the ALT_USB_HOST_HCDMAB0 register. */
#define ALT_USB_HOST_HCDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB0_OFST))
/*
* Register : hcchar1
*
* Host Channel 1 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR1_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR1_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR1_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR1_MPS register field value. */
#define ALT_USB_HOST_HCCHAR1_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_MPS register field value. */
#define ALT_USB_HOST_HCCHAR1_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR1_MPS register field. */
#define ALT_USB_HOST_HCCHAR1_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR1_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR1_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR1_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR1_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR1_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR1_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR1_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR1_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR1_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR1_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR1_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR1_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR1_EC register field value. */
#define ALT_USB_HOST_HCCHAR1_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_EC register field value. */
#define ALT_USB_HOST_HCCHAR1_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_EC register field. */
#define ALT_USB_HOST_HCCHAR1_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR1_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR1_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR1_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR1_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR1_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR1_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR1_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR1_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR1_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR1_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR1_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR1_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR1_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR1_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR1_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR1_CHENA register field. */
#define ALT_USB_HOST_HCCHAR1_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR1_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR1_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR1_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR1_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR1.
*/
struct ALT_USB_HOST_HCCHAR1_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR1_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR1_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR1_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR1_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR1_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR1_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR1_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR1_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR1_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR1_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR1. */
typedef volatile struct ALT_USB_HOST_HCCHAR1_s ALT_USB_HOST_HCCHAR1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR1 register. */
#define ALT_USB_HOST_HCCHAR1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR1 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR1_OFST 0x120
/* The address of the ALT_USB_HOST_HCCHAR1 register. */
#define ALT_USB_HOST_HCCHAR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR1_OFST))
/*
* Register : hcsplt1
*
* Host Channel 1 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT1_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT1_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT1_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT1_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT1_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT1_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT1_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT1_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT1_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT1_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT1_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT1_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT1_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT1_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT1_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT1_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT1_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT1_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT1_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT1.
*/
struct ALT_USB_HOST_HCSPLT1_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT1_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT1_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT1_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT1_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT1_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT1. */
typedef volatile struct ALT_USB_HOST_HCSPLT1_s ALT_USB_HOST_HCSPLT1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT1 register. */
#define ALT_USB_HOST_HCSPLT1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT1 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT1_OFST 0x124
/* The address of the ALT_USB_HOST_HCSPLT1 register. */
#define ALT_USB_HOST_HCSPLT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT1_OFST))
/*
* Register : hcint1
*
* Host Channel 1 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT1_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT1_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT1_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT1_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT1_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT1_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT1_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT1_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT1_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT1_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT1_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT1_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT1_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT1_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT1_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT1_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT1_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT1_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT1_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT1_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT1_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT1_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT1_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT1_CHHLTD register field. */
#define ALT_USB_HOST_HCINT1_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT1_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT1_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT1_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT1_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT1_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT1_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_AHBERR register field value. */
#define ALT_USB_HOST_HCINT1_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT1_AHBERR register field value. */
#define ALT_USB_HOST_HCINT1_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT1_AHBERR register field. */
#define ALT_USB_HOST_HCINT1_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT1_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT1_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT1_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT1_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_STALL register field value. */
#define ALT_USB_HOST_HCINT1_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT1_STALL register field value. */
#define ALT_USB_HOST_HCINT1_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT1_STALL register field. */
#define ALT_USB_HOST_HCINT1_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_STALL field value from a register. */
#define ALT_USB_HOST_HCINT1_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT1_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT1_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT1_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT1_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT1_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_NAK register field value. */
#define ALT_USB_HOST_HCINT1_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT1_NAK register field value. */
#define ALT_USB_HOST_HCINT1_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT1_NAK register field. */
#define ALT_USB_HOST_HCINT1_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_NAK field value from a register. */
#define ALT_USB_HOST_HCINT1_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT1_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT1_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT1_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT1_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT1_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_ACK register field value. */
#define ALT_USB_HOST_HCINT1_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT1_ACK register field value. */
#define ALT_USB_HOST_HCINT1_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT1_ACK register field. */
#define ALT_USB_HOST_HCINT1_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_ACK field value from a register. */
#define ALT_USB_HOST_HCINT1_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT1_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT1_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT1_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT1_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT1_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_NYET register field value. */
#define ALT_USB_HOST_HCINT1_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT1_NYET register field value. */
#define ALT_USB_HOST_HCINT1_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT1_NYET register field. */
#define ALT_USB_HOST_HCINT1_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_NYET field value from a register. */
#define ALT_USB_HOST_HCINT1_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT1_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT1_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT1_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT1_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT1_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_XACTERR register field value. */
#define ALT_USB_HOST_HCINT1_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT1_XACTERR register field value. */
#define ALT_USB_HOST_HCINT1_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT1_XACTERR register field. */
#define ALT_USB_HOST_HCINT1_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT1_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT1_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT1_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT1_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT1_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT1_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_BBLERR register field value. */
#define ALT_USB_HOST_HCINT1_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT1_BBLERR register field value. */
#define ALT_USB_HOST_HCINT1_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT1_BBLERR register field. */
#define ALT_USB_HOST_HCINT1_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT1_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT1_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT1_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT1_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT1_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT1_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT1_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT1_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT1_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT1_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT1_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT1_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT1_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT1_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT1_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT1_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT1_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT1_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT1_BNAINTR register field. */
#define ALT_USB_HOST_HCINT1_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT1_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT1_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT1.
*/
struct ALT_USB_HOST_HCINT1_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT1_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT1_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT1_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT1_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT1_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT1_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT1_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT1_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT1_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT1_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT1_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT1_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT1_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT1_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT1. */
typedef volatile struct ALT_USB_HOST_HCINT1_s ALT_USB_HOST_HCINT1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT1 register. */
#define ALT_USB_HOST_HCINT1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT1 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT1_OFST 0x128
/* The address of the ALT_USB_HOST_HCINT1 register. */
#define ALT_USB_HOST_HCINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT1_OFST))
/*
* Register : hcintmsk1
*
* Host Channel 1 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK1_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK1_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK1_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK1_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK1_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK1_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK1_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK1_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK1_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK1_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK1_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK1_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK1_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK1.
*/
struct ALT_USB_HOST_HCINTMSK1_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK1_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK1_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK1_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK1_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK1_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK1_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK1_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK1_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK1. */
typedef volatile struct ALT_USB_HOST_HCINTMSK1_s ALT_USB_HOST_HCINTMSK1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK1 register. */
#define ALT_USB_HOST_HCINTMSK1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK1 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK1_OFST 0x12c
/* The address of the ALT_USB_HOST_HCINTMSK1 register. */
#define ALT_USB_HOST_HCINTMSK1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK1_OFST))
/*
* Register : hctsiz1
*
* Host Channel 1 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ1_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ1_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ1_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ1_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ1_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_PID register field value. */
#define ALT_USB_HOST_HCTSIZ1_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_PID register field value. */
#define ALT_USB_HOST_HCTSIZ1_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_PID register field. */
#define ALT_USB_HOST_HCTSIZ1_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ1_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ1_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ1_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ1_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ1_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ1_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ1_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ1_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ1.
*/
struct ALT_USB_HOST_HCTSIZ1_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ1_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ1_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ1_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ1_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ1. */
typedef volatile struct ALT_USB_HOST_HCTSIZ1_s ALT_USB_HOST_HCTSIZ1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ1 register. */
#define ALT_USB_HOST_HCTSIZ1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ1 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ1_OFST 0x130
/* The address of the ALT_USB_HOST_HCTSIZ1 register. */
#define ALT_USB_HOST_HCTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ1_OFST))
/*
* Register : hcdma1
*
* Host Channel 1 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA1_HCDMA1
*
*/
/*
* Field : hcdma1
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA1_HCDMA1 register field value. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA1_HCDMA1 register field. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA1_HCDMA1 field value from a register. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA1_HCDMA1 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA1_HCDMA1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA1.
*/
struct ALT_USB_HOST_HCDMA1_s
{
uint32_t hcdma1 : 32; /* ALT_USB_HOST_HCDMA1_HCDMA1 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA1. */
typedef volatile struct ALT_USB_HOST_HCDMA1_s ALT_USB_HOST_HCDMA1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA1 register. */
#define ALT_USB_HOST_HCDMA1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA1 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA1_OFST 0x134
/* The address of the ALT_USB_HOST_HCDMA1 register. */
#define ALT_USB_HOST_HCDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA1_OFST))
/*
* Register : hcdmab1
*
* Host Channel 1 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB1_HCDMAB1
*
*/
/*
* Field : hcdmab1
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB1_HCDMAB1 register field. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB1_HCDMAB1 field value from a register. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB1_HCDMAB1 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB1_HCDMAB1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB1.
*/
struct ALT_USB_HOST_HCDMAB1_s
{
uint32_t hcdmab1 : 32; /* ALT_USB_HOST_HCDMAB1_HCDMAB1 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB1. */
typedef volatile struct ALT_USB_HOST_HCDMAB1_s ALT_USB_HOST_HCDMAB1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB1 register. */
#define ALT_USB_HOST_HCDMAB1_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB1 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB1_OFST 0x13c
/* The address of the ALT_USB_HOST_HCDMAB1 register. */
#define ALT_USB_HOST_HCDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB1_OFST))
/*
* Register : hcchar2
*
* Host Channel 2 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR2_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR2_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR2_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR2_MPS register field value. */
#define ALT_USB_HOST_HCCHAR2_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_MPS register field value. */
#define ALT_USB_HOST_HCCHAR2_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR2_MPS register field. */
#define ALT_USB_HOST_HCCHAR2_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR2_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR2_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR2_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR2_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR2_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR2_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR2_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR2_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR2_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR2_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR2_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR2_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR2_EC register field value. */
#define ALT_USB_HOST_HCCHAR2_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_EC register field value. */
#define ALT_USB_HOST_HCCHAR2_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_EC register field. */
#define ALT_USB_HOST_HCCHAR2_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR2_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR2_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR2_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR2_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR2_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR2_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR2_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR2_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR2_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR2_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR2_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR2_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR2_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR2_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR2_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR2_CHENA register field. */
#define ALT_USB_HOST_HCCHAR2_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR2_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR2_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR2_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR2_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR2.
*/
struct ALT_USB_HOST_HCCHAR2_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR2_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR2_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR2_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR2_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR2_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR2_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR2_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR2_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR2_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR2_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR2. */
typedef volatile struct ALT_USB_HOST_HCCHAR2_s ALT_USB_HOST_HCCHAR2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR2 register. */
#define ALT_USB_HOST_HCCHAR2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR2 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR2_OFST 0x140
/* The address of the ALT_USB_HOST_HCCHAR2 register. */
#define ALT_USB_HOST_HCCHAR2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR2_OFST))
/*
* Register : hcsplt2
*
* Host Channel 2 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT2_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT2_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT2_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT2_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT2_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT2_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT2_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT2_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT2_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT2_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT2_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT2_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT2_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT2_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT2_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT2_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT2_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT2_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT2_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT2.
*/
struct ALT_USB_HOST_HCSPLT2_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT2_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT2_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT2_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT2_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT2_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT2. */
typedef volatile struct ALT_USB_HOST_HCSPLT2_s ALT_USB_HOST_HCSPLT2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT2 register. */
#define ALT_USB_HOST_HCSPLT2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT2 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT2_OFST 0x144
/* The address of the ALT_USB_HOST_HCSPLT2 register. */
#define ALT_USB_HOST_HCSPLT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT2_OFST))
/*
* Register : hcint2
*
* Host Channel 2 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT2_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT2_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT2_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT2_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT2_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT2_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT2_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT2_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT2_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT2_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT2_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT2_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT2_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT2_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT2_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT2_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT2_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT2_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT2_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT2_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT2_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT2_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT2_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT2_CHHLTD register field. */
#define ALT_USB_HOST_HCINT2_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT2_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT2_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT2_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT2_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT2_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT2_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_AHBERR register field value. */
#define ALT_USB_HOST_HCINT2_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT2_AHBERR register field value. */
#define ALT_USB_HOST_HCINT2_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT2_AHBERR register field. */
#define ALT_USB_HOST_HCINT2_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT2_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT2_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT2_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT2_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_STALL register field value. */
#define ALT_USB_HOST_HCINT2_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT2_STALL register field value. */
#define ALT_USB_HOST_HCINT2_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT2_STALL register field. */
#define ALT_USB_HOST_HCINT2_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_STALL field value from a register. */
#define ALT_USB_HOST_HCINT2_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT2_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT2_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT2_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT2_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT2_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_NAK register field value. */
#define ALT_USB_HOST_HCINT2_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT2_NAK register field value. */
#define ALT_USB_HOST_HCINT2_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT2_NAK register field. */
#define ALT_USB_HOST_HCINT2_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_NAK field value from a register. */
#define ALT_USB_HOST_HCINT2_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT2_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT2_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT2_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT2_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT2_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_ACK register field value. */
#define ALT_USB_HOST_HCINT2_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT2_ACK register field value. */
#define ALT_USB_HOST_HCINT2_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT2_ACK register field. */
#define ALT_USB_HOST_HCINT2_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_ACK field value from a register. */
#define ALT_USB_HOST_HCINT2_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT2_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT2_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT2_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT2_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT2_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_NYET register field value. */
#define ALT_USB_HOST_HCINT2_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT2_NYET register field value. */
#define ALT_USB_HOST_HCINT2_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT2_NYET register field. */
#define ALT_USB_HOST_HCINT2_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_NYET field value from a register. */
#define ALT_USB_HOST_HCINT2_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT2_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT2_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT2_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT2_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT2_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_XACTERR register field value. */
#define ALT_USB_HOST_HCINT2_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT2_XACTERR register field value. */
#define ALT_USB_HOST_HCINT2_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT2_XACTERR register field. */
#define ALT_USB_HOST_HCINT2_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT2_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT2_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT2_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT2_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT2_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT2_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_BBLERR register field value. */
#define ALT_USB_HOST_HCINT2_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT2_BBLERR register field value. */
#define ALT_USB_HOST_HCINT2_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT2_BBLERR register field. */
#define ALT_USB_HOST_HCINT2_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT2_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT2_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT2_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT2_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT2_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT2_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT2_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT2_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT2_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT2_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT2_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT2_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT2_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT2_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT2_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT2_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT2_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT2_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT2_BNAINTR register field. */
#define ALT_USB_HOST_HCINT2_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT2_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT2_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT2.
*/
struct ALT_USB_HOST_HCINT2_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT2_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT2_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT2_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT2_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT2_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT2_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT2_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT2_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT2_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT2_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT2_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT2_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT2_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT2_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT2. */
typedef volatile struct ALT_USB_HOST_HCINT2_s ALT_USB_HOST_HCINT2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT2 register. */
#define ALT_USB_HOST_HCINT2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT2 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT2_OFST 0x148
/* The address of the ALT_USB_HOST_HCINT2 register. */
#define ALT_USB_HOST_HCINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT2_OFST))
/*
* Register : hcintmsk2
*
* Host Channel 2 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK2_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK2_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK2_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK2_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK2_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK2_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK2_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK2_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK2_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK2_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK2_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK2_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK2_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK2.
*/
struct ALT_USB_HOST_HCINTMSK2_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK2_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK2_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK2_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK2_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK2_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK2_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK2_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK2_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK2. */
typedef volatile struct ALT_USB_HOST_HCINTMSK2_s ALT_USB_HOST_HCINTMSK2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK2 register. */
#define ALT_USB_HOST_HCINTMSK2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK2 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK2_OFST 0x14c
/* The address of the ALT_USB_HOST_HCINTMSK2 register. */
#define ALT_USB_HOST_HCINTMSK2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK2_OFST))
/*
* Register : hctsiz2
*
* Host Channel 2 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ2_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ2_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ2_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ2_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ2_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_PID register field value. */
#define ALT_USB_HOST_HCTSIZ2_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_PID register field value. */
#define ALT_USB_HOST_HCTSIZ2_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_PID register field. */
#define ALT_USB_HOST_HCTSIZ2_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ2_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ2_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ2_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ2_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ2_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ2_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ2_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ2_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ2.
*/
struct ALT_USB_HOST_HCTSIZ2_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ2_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ2_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ2_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ2_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ2. */
typedef volatile struct ALT_USB_HOST_HCTSIZ2_s ALT_USB_HOST_HCTSIZ2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ2 register. */
#define ALT_USB_HOST_HCTSIZ2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ2 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ2_OFST 0x150
/* The address of the ALT_USB_HOST_HCTSIZ2 register. */
#define ALT_USB_HOST_HCTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ2_OFST))
/*
* Register : hcdma2
*
* Host Channel 2 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA2_HCDMA2
*
*/
/*
* Field : hcdma2
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA2_HCDMA2 register field value. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA2_HCDMA2 register field. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA2_HCDMA2 field value from a register. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA2_HCDMA2 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA2_HCDMA2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA2.
*/
struct ALT_USB_HOST_HCDMA2_s
{
uint32_t hcdma2 : 32; /* ALT_USB_HOST_HCDMA2_HCDMA2 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA2. */
typedef volatile struct ALT_USB_HOST_HCDMA2_s ALT_USB_HOST_HCDMA2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA2 register. */
#define ALT_USB_HOST_HCDMA2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA2 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA2_OFST 0x154
/* The address of the ALT_USB_HOST_HCDMA2 register. */
#define ALT_USB_HOST_HCDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA2_OFST))
/*
* Register : hcdmab2
*
* Host Channel 2 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB2_HCDMAB2
*
*/
/*
* Field : hcdmab2
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB2_HCDMAB2 register field. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB2_HCDMAB2 field value from a register. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB2_HCDMAB2 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB2_HCDMAB2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB2.
*/
struct ALT_USB_HOST_HCDMAB2_s
{
uint32_t hcdmab2 : 32; /* ALT_USB_HOST_HCDMAB2_HCDMAB2 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB2. */
typedef volatile struct ALT_USB_HOST_HCDMAB2_s ALT_USB_HOST_HCDMAB2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB2 register. */
#define ALT_USB_HOST_HCDMAB2_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB2 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB2_OFST 0x15c
/* The address of the ALT_USB_HOST_HCDMAB2 register. */
#define ALT_USB_HOST_HCDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB2_OFST))
/*
* Register : hcchar3
*
* Host Channel 3 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR3_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR3_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR3_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR3_MPS register field value. */
#define ALT_USB_HOST_HCCHAR3_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_MPS register field value. */
#define ALT_USB_HOST_HCCHAR3_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR3_MPS register field. */
#define ALT_USB_HOST_HCCHAR3_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR3_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR3_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR3_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR | 0x0 | OUT
* ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR | 0x1 | IN
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
*
* OUT
*/
#define ALT_USB_HOST_HCCHAR3_EPDIR_E_OUTDIR 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPDIR
*
* IN
*/
#define ALT_USB_HOST_HCCHAR3_EPDIR_E_INDIR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR3_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
* ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
*
* Communicating with non lowspeed
*/
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_NONLOWSPEED 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_LSPDDEV
*
* Communicating with lowspeed
*/
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_E_LOWSPEED 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR3_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR3_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR3_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
* ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
*
* Reserved This field yields undefined results
*/
#define ALT_USB_HOST_HCCHAR3_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR3_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR3_EC register field value. */
#define ALT_USB_HOST_HCCHAR3_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_EC register field value. */
#define ALT_USB_HOST_HCCHAR3_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_EC register field. */
#define ALT_USB_HOST_HCCHAR3_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR3_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR3_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR3_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR3_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT | 0x0 | No activity
* ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
*
* No activity
*/
#define ALT_USB_HOST_HCCHAR3_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHDIS
*
* Stop transmitting/receiving data
*/
#define ALT_USB_HOST_HCCHAR3_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR3_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR3_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
* : | | buffer with data is setup and this channel can
* : | | access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR3_CHENA_E_NOTRDY 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR3_CHENA
*
* Indicates that the descriptor structure and data buffer with data is setup and
* this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR3_CHENA_E_RDY 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR3_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR3_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR3_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR3_CHENA register field. */
#define ALT_USB_HOST_HCCHAR3_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR3_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR3_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR3_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR3_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR3.
*/
struct ALT_USB_HOST_HCCHAR3_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR3_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR3_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR3_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR3_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR3_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR3_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR3_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR3_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR3_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR3_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR3. */
typedef volatile struct ALT_USB_HOST_HCCHAR3_s ALT_USB_HOST_HCCHAR3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR3 register. */
#define ALT_USB_HOST_HCCHAR3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR3 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR3_OFST 0x160
/* The address of the ALT_USB_HOST_HCCHAR3 register. */
#define ALT_USB_HOST_HCCHAR3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR3_OFST))
/*
* Register : hcsplt3
*
* Host Channel 3 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT3_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT3_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT3_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT3_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT3_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT3_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT3_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT3_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT3_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT3_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT3_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT3_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT3_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT3_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT3_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT3_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT3_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT3_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT3_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT3.
*/
struct ALT_USB_HOST_HCSPLT3_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT3_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT3_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT3_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT3_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT3_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT3. */
typedef volatile struct ALT_USB_HOST_HCSPLT3_s ALT_USB_HOST_HCSPLT3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT3 register. */
#define ALT_USB_HOST_HCSPLT3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT3 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT3_OFST 0x164
/* The address of the ALT_USB_HOST_HCSPLT3 register. */
#define ALT_USB_HOST_HCSPLT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT3_OFST))
/*
* Register : hcint3
*
* Host Channel 3 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT3_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT3_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT3_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT3_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT3_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT3_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT3_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT3_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT3_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT3_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT3_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT3_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT3_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT3_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT3_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT3_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT3_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT3_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT3_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT3_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT3_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT3_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT3_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT3_CHHLTD register field. */
#define ALT_USB_HOST_HCINT3_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT3_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT3_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT3_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT3_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT3_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT3_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_AHBERR register field value. */
#define ALT_USB_HOST_HCINT3_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT3_AHBERR register field value. */
#define ALT_USB_HOST_HCINT3_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT3_AHBERR register field. */
#define ALT_USB_HOST_HCINT3_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT3_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT3_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT3_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT3_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_STALL register field value. */
#define ALT_USB_HOST_HCINT3_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT3_STALL register field value. */
#define ALT_USB_HOST_HCINT3_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT3_STALL register field. */
#define ALT_USB_HOST_HCINT3_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_STALL field value from a register. */
#define ALT_USB_HOST_HCINT3_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT3_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT3_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT3_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT3_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT3_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_NAK register field value. */
#define ALT_USB_HOST_HCINT3_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT3_NAK register field value. */
#define ALT_USB_HOST_HCINT3_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT3_NAK register field. */
#define ALT_USB_HOST_HCINT3_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_NAK field value from a register. */
#define ALT_USB_HOST_HCINT3_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT3_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT3_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT3_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT3_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT3_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_ACK register field value. */
#define ALT_USB_HOST_HCINT3_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT3_ACK register field value. */
#define ALT_USB_HOST_HCINT3_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT3_ACK register field. */
#define ALT_USB_HOST_HCINT3_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_ACK field value from a register. */
#define ALT_USB_HOST_HCINT3_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT3_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT3_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT3_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT3_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT3_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_NYET register field value. */
#define ALT_USB_HOST_HCINT3_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT3_NYET register field value. */
#define ALT_USB_HOST_HCINT3_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT3_NYET register field. */
#define ALT_USB_HOST_HCINT3_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_NYET field value from a register. */
#define ALT_USB_HOST_HCINT3_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT3_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT3_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT3_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT3_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT3_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_XACTERR register field value. */
#define ALT_USB_HOST_HCINT3_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT3_XACTERR register field value. */
#define ALT_USB_HOST_HCINT3_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT3_XACTERR register field. */
#define ALT_USB_HOST_HCINT3_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT3_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT3_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT3_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT3_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT3_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT3_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_BBLERR register field value. */
#define ALT_USB_HOST_HCINT3_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT3_BBLERR register field value. */
#define ALT_USB_HOST_HCINT3_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT3_BBLERR register field. */
#define ALT_USB_HOST_HCINT3_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT3_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT3_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT3_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT3_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT3_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT3_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT3_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT3_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT3_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT3_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT3_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT3_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT3_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT3_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT3_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT3_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT3_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT3_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT3_BNAINTR register field. */
#define ALT_USB_HOST_HCINT3_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT3_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT3_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT3.
*/
struct ALT_USB_HOST_HCINT3_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT3_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT3_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT3_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT3_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT3_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT3_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT3_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT3_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT3_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT3_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT3_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT3_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT3_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT3_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT3. */
typedef volatile struct ALT_USB_HOST_HCINT3_s ALT_USB_HOST_HCINT3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT3 register. */
#define ALT_USB_HOST_HCINT3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT3 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT3_OFST 0x168
/* The address of the ALT_USB_HOST_HCINT3 register. */
#define ALT_USB_HOST_HCINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT3_OFST))
/*
* Register : hcintmsk3
*
* Host Channel 3 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK3_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK3_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK3_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK3_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK3_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK3_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK3_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK3_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK3_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK3_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK3_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK3_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK3_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK3.
*/
struct ALT_USB_HOST_HCINTMSK3_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK3_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK3_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK3_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK3_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK3_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK3_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK3_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK3_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK3. */
typedef volatile struct ALT_USB_HOST_HCINTMSK3_s ALT_USB_HOST_HCINTMSK3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK3 register. */
#define ALT_USB_HOST_HCINTMSK3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK3 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK3_OFST 0x16c
/* The address of the ALT_USB_HOST_HCINTMSK3 register. */
#define ALT_USB_HOST_HCINTMSK3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK3_OFST))
/*
* Register : hctsiz3
*
* Host Channel 3 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ3_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ3_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ3_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ3_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ3_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_PID register field value. */
#define ALT_USB_HOST_HCTSIZ3_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_PID register field value. */
#define ALT_USB_HOST_HCTSIZ3_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_PID register field. */
#define ALT_USB_HOST_HCTSIZ3_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ3_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ3_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ3_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ3_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ3_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ3_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ3_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ3_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ3.
*/
struct ALT_USB_HOST_HCTSIZ3_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ3_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ3_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ3_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ3_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ3. */
typedef volatile struct ALT_USB_HOST_HCTSIZ3_s ALT_USB_HOST_HCTSIZ3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ3 register. */
#define ALT_USB_HOST_HCTSIZ3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ3 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ3_OFST 0x170
/* The address of the ALT_USB_HOST_HCTSIZ3 register. */
#define ALT_USB_HOST_HCTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ3_OFST))
/*
* Register : hcdma3
*
* Host Channel 3 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA3_HCDMA3
*
*/
/*
* Field : hcdma3
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA3_HCDMA3 register field value. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA3_HCDMA3 register field. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA3_HCDMA3 field value from a register. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA3_HCDMA3 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA3_HCDMA3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA3.
*/
struct ALT_USB_HOST_HCDMA3_s
{
uint32_t hcdma3 : 32; /* ALT_USB_HOST_HCDMA3_HCDMA3 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA3. */
typedef volatile struct ALT_USB_HOST_HCDMA3_s ALT_USB_HOST_HCDMA3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA3 register. */
#define ALT_USB_HOST_HCDMA3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA3 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA3_OFST 0x174
/* The address of the ALT_USB_HOST_HCDMA3 register. */
#define ALT_USB_HOST_HCDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA3_OFST))
/*
* Register : hcdmab3
*
* Host Channel 3 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB3_HCDMAB3
*
*/
/*
* Field : hcdmab3
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB3_HCDMAB3 register field. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB3_HCDMAB3 field value from a register. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB3_HCDMAB3 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB3_HCDMAB3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB3.
*/
struct ALT_USB_HOST_HCDMAB3_s
{
uint32_t hcdmab3 : 32; /* ALT_USB_HOST_HCDMAB3_HCDMAB3 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB3. */
typedef volatile struct ALT_USB_HOST_HCDMAB3_s ALT_USB_HOST_HCDMAB3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB3 register. */
#define ALT_USB_HOST_HCDMAB3_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB3 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB3_OFST 0x17c
/* The address of the ALT_USB_HOST_HCDMAB3 register. */
#define ALT_USB_HOST_HCDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB3_OFST))
/*
* Register : hcchar4
*
* Host Channel 4 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:----------------------------------
* [31:0] | RW | 0x0 | Host Channel 0 DMA Buffer Address
*
*/
/*
* Field : Host Channel 0 DMA Buffer Address - hcdmab4
*
* These registers are present only in case of Scatter/Gather DMA. These
* registers are implemented in RAM instead of flop-based implementation. Holds
* the current buffer address. This register is updated as and when the data
* transfer for the corresponding end point is in progress. This register is
* present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCCHAR4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR4_HCDMAB4 field value from a register. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR4_HCDMAB4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR4.
*/
struct ALT_USB_HOST_HCCHAR4_s
{
uint32_t hcdmab4 : 32; /* Host Channel 0 DMA Buffer Address */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR4. */
typedef volatile struct ALT_USB_HOST_HCCHAR4_s ALT_USB_HOST_HCCHAR4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR4 register. */
#define ALT_USB_HOST_HCCHAR4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR4 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR4_OFST 0x180
/* The address of the ALT_USB_HOST_HCCHAR4 register. */
#define ALT_USB_HOST_HCCHAR4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR4_OFST))
/*
* Register : hcsplt4
*
* Host Channel 4 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT4_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT4_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT4_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT4_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT4_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT4_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT4_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT4_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT4_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT4_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT4_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT4_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT4_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT4_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT4_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT4_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT4_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT4_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT4_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT4.
*/
struct ALT_USB_HOST_HCSPLT4_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT4_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT4_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT4_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT4_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT4_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT4. */
typedef volatile struct ALT_USB_HOST_HCSPLT4_s ALT_USB_HOST_HCSPLT4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT4 register. */
#define ALT_USB_HOST_HCSPLT4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT4 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT4_OFST 0x184
/* The address of the ALT_USB_HOST_HCSPLT4 register. */
#define ALT_USB_HOST_HCSPLT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT4_OFST))
/*
* Register : hcint4
*
* Host Channel 4 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT4_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT4_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT4_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT4_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT4_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT4_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT4_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT4_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT4_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT4_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT4_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT4_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT4_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT4_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT4_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT4_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT4_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT4_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT4_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT4_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT4_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT4_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT4_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT4_CHHLTD register field. */
#define ALT_USB_HOST_HCINT4_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT4_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT4_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT4_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT4_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT4_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT4_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_AHBERR register field value. */
#define ALT_USB_HOST_HCINT4_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT4_AHBERR register field value. */
#define ALT_USB_HOST_HCINT4_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT4_AHBERR register field. */
#define ALT_USB_HOST_HCINT4_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT4_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT4_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT4_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT4_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_STALL register field value. */
#define ALT_USB_HOST_HCINT4_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT4_STALL register field value. */
#define ALT_USB_HOST_HCINT4_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT4_STALL register field. */
#define ALT_USB_HOST_HCINT4_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_STALL field value from a register. */
#define ALT_USB_HOST_HCINT4_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT4_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT4_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT4_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT4_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT4_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_NAK register field value. */
#define ALT_USB_HOST_HCINT4_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT4_NAK register field value. */
#define ALT_USB_HOST_HCINT4_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT4_NAK register field. */
#define ALT_USB_HOST_HCINT4_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_NAK field value from a register. */
#define ALT_USB_HOST_HCINT4_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT4_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT4_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT4_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT4_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT4_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_ACK register field value. */
#define ALT_USB_HOST_HCINT4_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT4_ACK register field value. */
#define ALT_USB_HOST_HCINT4_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT4_ACK register field. */
#define ALT_USB_HOST_HCINT4_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_ACK field value from a register. */
#define ALT_USB_HOST_HCINT4_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT4_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT4_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT4_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT4_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT4_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_NYET register field value. */
#define ALT_USB_HOST_HCINT4_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT4_NYET register field value. */
#define ALT_USB_HOST_HCINT4_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT4_NYET register field. */
#define ALT_USB_HOST_HCINT4_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_NYET field value from a register. */
#define ALT_USB_HOST_HCINT4_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT4_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT4_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT4_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT4_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT4_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_XACTERR register field value. */
#define ALT_USB_HOST_HCINT4_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT4_XACTERR register field value. */
#define ALT_USB_HOST_HCINT4_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT4_XACTERR register field. */
#define ALT_USB_HOST_HCINT4_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT4_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT4_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT4_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT4_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT4_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT4_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_BBLERR register field value. */
#define ALT_USB_HOST_HCINT4_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT4_BBLERR register field value. */
#define ALT_USB_HOST_HCINT4_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT4_BBLERR register field. */
#define ALT_USB_HOST_HCINT4_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT4_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT4_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT4_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT4_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT4_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT4_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT4_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT4_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT4_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT4_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT4_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT4_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT4_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT4_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT4_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT4_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT4_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT4_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT4_BNAINTR register field. */
#define ALT_USB_HOST_HCINT4_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT4_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT4_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT4.
*/
struct ALT_USB_HOST_HCINT4_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT4_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT4_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT4_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT4_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT4_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT4_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT4_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT4_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT4_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT4_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT4_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT4_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT4_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT4_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT4. */
typedef volatile struct ALT_USB_HOST_HCINT4_s ALT_USB_HOST_HCINT4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT4 register. */
#define ALT_USB_HOST_HCINT4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT4 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT4_OFST 0x188
/* The address of the ALT_USB_HOST_HCINT4 register. */
#define ALT_USB_HOST_HCINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT4_OFST))
/*
* Register : hcintmsk4
*
* Host Channel 4 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK4_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK4_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK4_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK4_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK4_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK4_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK4_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK4_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK4_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK4_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK4_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK4_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK4_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK4.
*/
struct ALT_USB_HOST_HCINTMSK4_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK4_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK4_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK4_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK4_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK4_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK4_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK4_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK4_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK4. */
typedef volatile struct ALT_USB_HOST_HCINTMSK4_s ALT_USB_HOST_HCINTMSK4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK4 register. */
#define ALT_USB_HOST_HCINTMSK4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK4 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK4_OFST 0x18c
/* The address of the ALT_USB_HOST_HCINTMSK4 register. */
#define ALT_USB_HOST_HCINTMSK4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK4_OFST))
/*
* Register : hctsiz4
*
* Host Channel 4 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ4_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ4_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ4_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ4_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ4_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_PID register field value. */
#define ALT_USB_HOST_HCTSIZ4_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_PID register field value. */
#define ALT_USB_HOST_HCTSIZ4_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_PID register field. */
#define ALT_USB_HOST_HCTSIZ4_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ4_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ4_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ4_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ4_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ4_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ4_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ4_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ4_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ4.
*/
struct ALT_USB_HOST_HCTSIZ4_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ4_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ4_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ4_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ4_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ4. */
typedef volatile struct ALT_USB_HOST_HCTSIZ4_s ALT_USB_HOST_HCTSIZ4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ4 register. */
#define ALT_USB_HOST_HCTSIZ4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ4 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ4_OFST 0x190
/* The address of the ALT_USB_HOST_HCTSIZ4 register. */
#define ALT_USB_HOST_HCTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ4_OFST))
/*
* Register : hcdma4
*
* Host Channel 4 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA4_HCDMA4
*
*/
/*
* Field : hcdma4
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA4_HCDMA4 register field value. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA4_HCDMA4 register field. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA4_HCDMA4 field value from a register. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA4_HCDMA4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA4_HCDMA4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA4.
*/
struct ALT_USB_HOST_HCDMA4_s
{
uint32_t hcdma4 : 32; /* ALT_USB_HOST_HCDMA4_HCDMA4 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA4. */
typedef volatile struct ALT_USB_HOST_HCDMA4_s ALT_USB_HOST_HCDMA4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA4 register. */
#define ALT_USB_HOST_HCDMA4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA4 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA4_OFST 0x194
/* The address of the ALT_USB_HOST_HCDMA4 register. */
#define ALT_USB_HOST_HCDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA4_OFST))
/*
* Register : hcdmab4
*
* Host Channel 4 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB4_HCDMAB4
*
*/
/*
* Field : hcdmab4
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB4_HCDMAB4 register field. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB4_HCDMAB4 field value from a register. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB4_HCDMAB4 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB4_HCDMAB4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB4.
*/
struct ALT_USB_HOST_HCDMAB4_s
{
uint32_t hcdmab4 : 32; /* ALT_USB_HOST_HCDMAB4_HCDMAB4 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB4. */
typedef volatile struct ALT_USB_HOST_HCDMAB4_s ALT_USB_HOST_HCDMAB4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB4 register. */
#define ALT_USB_HOST_HCDMAB4_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB4 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB4_OFST 0x19c
/* The address of the ALT_USB_HOST_HCDMAB4 register. */
#define ALT_USB_HOST_HCDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB4_OFST))
/*
* Register : hcchar5
*
* Host Channel 5 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR5_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR5_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR5_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR5_MPS register field value. */
#define ALT_USB_HOST_HCCHAR5_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_MPS register field value. */
#define ALT_USB_HOST_HCCHAR5_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR5_MPS register field. */
#define ALT_USB_HOST_HCCHAR5_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR5_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR5_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR5_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR | 0x0 | OUT
* ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR | 0x1 | IN
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
*
* OUT
*/
#define ALT_USB_HOST_HCCHAR5_EPDIR_E_OUTDIR 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPDIR
*
* IN
*/
#define ALT_USB_HOST_HCCHAR5_EPDIR_E_INDIR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR5_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED | 0x0 | Communicating with non lowspeed
* ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED | 0x1 | Communicating with lowspeed
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
*
* Communicating with non lowspeed
*/
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_NONLOWSPEED 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_LSPDDEV
*
* Communicating with lowspeed
*/
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_E_LOWSPEED 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR5_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR5_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR5_EC_E_RSVD | 0x0 | Reserved This field yields undefined results
* ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
*
* Reserved This field yields undefined results
*/
#define ALT_USB_HOST_HCCHAR5_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR5_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR5_EC register field value. */
#define ALT_USB_HOST_HCCHAR5_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_EC register field value. */
#define ALT_USB_HOST_HCCHAR5_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_EC register field. */
#define ALT_USB_HOST_HCCHAR5_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR5_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR5_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR5_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR5_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT | 0x0 | No activity
* ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving data
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
*
* No activity
*/
#define ALT_USB_HOST_HCCHAR5_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHDIS
*
* Stop transmitting/receiving data
*/
#define ALT_USB_HOST_HCCHAR5_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR5_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR5_CHENA_E_RDY | 0x1 | Indicates that the descriptor structure and data
* : | | buffer with data is setup and this channel can
* : | | access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR5_CHENA_E_NOTRDY 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR5_CHENA
*
* Indicates that the descriptor structure and data buffer with data is setup and
* this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR5_CHENA_E_RDY 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR5_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR5_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR5_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR5_CHENA register field. */
#define ALT_USB_HOST_HCCHAR5_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR5_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR5_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR5_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR5_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR5.
*/
struct ALT_USB_HOST_HCCHAR5_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR5_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR5_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR5_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR5_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR5_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR5_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR5_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR5_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR5_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR5_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR5. */
typedef volatile struct ALT_USB_HOST_HCCHAR5_s ALT_USB_HOST_HCCHAR5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR5 register. */
#define ALT_USB_HOST_HCCHAR5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR5 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR5_OFST 0x1a0
/* The address of the ALT_USB_HOST_HCCHAR5 register. */
#define ALT_USB_HOST_HCCHAR5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR5_OFST))
/*
* Register : hcsplt5
*
* Host Channel 5 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT5_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT5_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT5_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT5_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT5_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT5_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT5_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT5_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT5_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT5_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT5_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT5_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT5_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT5_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT5_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT5_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT5_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT5_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT5_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT5.
*/
struct ALT_USB_HOST_HCSPLT5_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT5_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT5_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT5_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT5_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT5_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT5. */
typedef volatile struct ALT_USB_HOST_HCSPLT5_s ALT_USB_HOST_HCSPLT5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT5 register. */
#define ALT_USB_HOST_HCSPLT5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT5 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT5_OFST 0x1a4
/* The address of the ALT_USB_HOST_HCSPLT5 register. */
#define ALT_USB_HOST_HCSPLT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT5_OFST))
/*
* Register : hcint5
*
* Host Channel 5 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT5_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT5_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT5_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT5_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT5_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT5_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT5_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT5_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT5_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT5_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT5_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT5_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT5_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT5_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT5_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT5_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT5_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT5_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT5_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT5_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT5_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT5_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT5_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT5_CHHLTD register field. */
#define ALT_USB_HOST_HCINT5_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT5_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT5_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT5_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT5_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT5_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT5_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_AHBERR register field value. */
#define ALT_USB_HOST_HCINT5_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT5_AHBERR register field value. */
#define ALT_USB_HOST_HCINT5_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT5_AHBERR register field. */
#define ALT_USB_HOST_HCINT5_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT5_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT5_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT5_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT5_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_STALL register field value. */
#define ALT_USB_HOST_HCINT5_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT5_STALL register field value. */
#define ALT_USB_HOST_HCINT5_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT5_STALL register field. */
#define ALT_USB_HOST_HCINT5_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_STALL field value from a register. */
#define ALT_USB_HOST_HCINT5_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT5_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT5_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT5_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT5_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT5_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_NAK register field value. */
#define ALT_USB_HOST_HCINT5_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT5_NAK register field value. */
#define ALT_USB_HOST_HCINT5_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT5_NAK register field. */
#define ALT_USB_HOST_HCINT5_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_NAK field value from a register. */
#define ALT_USB_HOST_HCINT5_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT5_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT5_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT5_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT5_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT5_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_ACK register field value. */
#define ALT_USB_HOST_HCINT5_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT5_ACK register field value. */
#define ALT_USB_HOST_HCINT5_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT5_ACK register field. */
#define ALT_USB_HOST_HCINT5_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_ACK field value from a register. */
#define ALT_USB_HOST_HCINT5_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT5_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT5_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT5_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT5_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT5_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_NYET register field value. */
#define ALT_USB_HOST_HCINT5_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT5_NYET register field value. */
#define ALT_USB_HOST_HCINT5_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT5_NYET register field. */
#define ALT_USB_HOST_HCINT5_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_NYET field value from a register. */
#define ALT_USB_HOST_HCINT5_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT5_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT5_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT5_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT5_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT5_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_XACTERR register field value. */
#define ALT_USB_HOST_HCINT5_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT5_XACTERR register field value. */
#define ALT_USB_HOST_HCINT5_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT5_XACTERR register field. */
#define ALT_USB_HOST_HCINT5_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT5_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT5_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT5_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT5_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT5_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT5_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_BBLERR register field value. */
#define ALT_USB_HOST_HCINT5_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT5_BBLERR register field value. */
#define ALT_USB_HOST_HCINT5_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT5_BBLERR register field. */
#define ALT_USB_HOST_HCINT5_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT5_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT5_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT5_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT5_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT5_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT5_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT5_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT5_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT5_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT5_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT5_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT5_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT5_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT5_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT5_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT5_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT5_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT5_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT5_BNAINTR register field. */
#define ALT_USB_HOST_HCINT5_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT5_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT5_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT5.
*/
struct ALT_USB_HOST_HCINT5_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT5_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT5_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT5_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT5_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT5_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT5_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT5_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT5_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT5_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT5_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT5_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT5_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT5_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT5_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT5. */
typedef volatile struct ALT_USB_HOST_HCINT5_s ALT_USB_HOST_HCINT5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT5 register. */
#define ALT_USB_HOST_HCINT5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT5 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT5_OFST 0x1a8
/* The address of the ALT_USB_HOST_HCINT5 register. */
#define ALT_USB_HOST_HCINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT5_OFST))
/*
* Register : hcintmsk5
*
* Host Channel 5 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK5_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK5_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK5_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK5_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK5_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK5_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK5_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK5_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK5_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK5_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK5_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK5_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK5_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK5.
*/
struct ALT_USB_HOST_HCINTMSK5_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK5_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK5_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK5_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK5_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK5_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK5_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK5_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK5_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK5. */
typedef volatile struct ALT_USB_HOST_HCINTMSK5_s ALT_USB_HOST_HCINTMSK5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK5 register. */
#define ALT_USB_HOST_HCINTMSK5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK5 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK5_OFST 0x1ac
/* The address of the ALT_USB_HOST_HCINTMSK5 register. */
#define ALT_USB_HOST_HCINTMSK5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK5_OFST))
/*
* Register : hctsiz5
*
* Host Channel 5 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ5_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ5_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ5_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ5_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ5_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_PID register field value. */
#define ALT_USB_HOST_HCTSIZ5_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_PID register field value. */
#define ALT_USB_HOST_HCTSIZ5_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_PID register field. */
#define ALT_USB_HOST_HCTSIZ5_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ5_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ5_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ5_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ5_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ5_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ5_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ5_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ5_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ5.
*/
struct ALT_USB_HOST_HCTSIZ5_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ5_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ5_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ5_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ5_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ5. */
typedef volatile struct ALT_USB_HOST_HCTSIZ5_s ALT_USB_HOST_HCTSIZ5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ5 register. */
#define ALT_USB_HOST_HCTSIZ5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ5 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ5_OFST 0x1b0
/* The address of the ALT_USB_HOST_HCTSIZ5 register. */
#define ALT_USB_HOST_HCTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ5_OFST))
/*
* Register : hcdma5
*
* Host Channel 5 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA5_HCDMA5
*
*/
/*
* Field : hcdma5
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA5_HCDMA5 register field value. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA5_HCDMA5 register field. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA5_HCDMA5 field value from a register. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA5_HCDMA5 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA5_HCDMA5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA5.
*/
struct ALT_USB_HOST_HCDMA5_s
{
uint32_t hcdma5 : 32; /* ALT_USB_HOST_HCDMA5_HCDMA5 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA5. */
typedef volatile struct ALT_USB_HOST_HCDMA5_s ALT_USB_HOST_HCDMA5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA5 register. */
#define ALT_USB_HOST_HCDMA5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA5 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA5_OFST 0x1b4
/* The address of the ALT_USB_HOST_HCDMA5 register. */
#define ALT_USB_HOST_HCDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA5_OFST))
/*
* Register : hcdmab5
*
* Host Channel 5 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB5_HCDMAB5
*
*/
/*
* Field : hcdmab5
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB5_HCDMAB5 register field. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB5_HCDMAB5 field value from a register. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB5_HCDMAB5 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB5_HCDMAB5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB5.
*/
struct ALT_USB_HOST_HCDMAB5_s
{
uint32_t hcdmab5 : 32; /* ALT_USB_HOST_HCDMAB5_HCDMAB5 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB5. */
typedef volatile struct ALT_USB_HOST_HCDMAB5_s ALT_USB_HOST_HCDMAB5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB5 register. */
#define ALT_USB_HOST_HCDMAB5_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB5 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB5_OFST 0x1bc
/* The address of the ALT_USB_HOST_HCDMAB5 register. */
#define ALT_USB_HOST_HCDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB5_OFST))
/*
* Register : hcchar6
*
* Host Channel 6 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR6_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR6_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR6_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR6_MPS register field value. */
#define ALT_USB_HOST_HCCHAR6_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_MPS register field value. */
#define ALT_USB_HOST_HCCHAR6_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR6_MPS register field. */
#define ALT_USB_HOST_HCCHAR6_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR6_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR6_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR6_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR6_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR6_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR6_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR6_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR6_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR6_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR6_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR6_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR6_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR6_EC register field value. */
#define ALT_USB_HOST_HCCHAR6_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_EC register field value. */
#define ALT_USB_HOST_HCCHAR6_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_EC register field. */
#define ALT_USB_HOST_HCCHAR6_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR6_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR6_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR6_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR6_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR6_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR6_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR6_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR6_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR6_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR6_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR6_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR6_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR6_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR6_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR6_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR6_CHENA register field. */
#define ALT_USB_HOST_HCCHAR6_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR6_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR6_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR6_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR6_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR6.
*/
struct ALT_USB_HOST_HCCHAR6_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR6_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR6_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR6_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR6_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR6_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR6_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR6_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR6_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR6_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR6_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR6. */
typedef volatile struct ALT_USB_HOST_HCCHAR6_s ALT_USB_HOST_HCCHAR6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR6 register. */
#define ALT_USB_HOST_HCCHAR6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR6 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR6_OFST 0x1c0
/* The address of the ALT_USB_HOST_HCCHAR6 register. */
#define ALT_USB_HOST_HCCHAR6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR6_OFST))
/*
* Register : hcsplt6
*
* Host Channel 6 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT6_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT6_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT6_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT6_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT6_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT6_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT6_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT6_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT6_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT6_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT6_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT6_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT6_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT6_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT6_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT6_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT6_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT6_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT6_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT6.
*/
struct ALT_USB_HOST_HCSPLT6_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT6_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT6_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT6_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT6_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT6_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT6. */
typedef volatile struct ALT_USB_HOST_HCSPLT6_s ALT_USB_HOST_HCSPLT6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT6 register. */
#define ALT_USB_HOST_HCSPLT6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT6 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT6_OFST 0x1c4
/* The address of the ALT_USB_HOST_HCSPLT6 register. */
#define ALT_USB_HOST_HCSPLT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT6_OFST))
/*
* Register : hcint6
*
* Host Channel 6 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT6_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT6_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT6_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT6_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT6_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT6_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT6_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT6_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT6_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT6_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT6_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT6_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT6_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT6_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT6_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT6_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT6_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT6_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT6_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT6_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT6_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT6_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT6_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT6_CHHLTD register field. */
#define ALT_USB_HOST_HCINT6_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT6_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT6_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT6_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT6_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT6_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT6_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_AHBERR register field value. */
#define ALT_USB_HOST_HCINT6_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT6_AHBERR register field value. */
#define ALT_USB_HOST_HCINT6_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT6_AHBERR register field. */
#define ALT_USB_HOST_HCINT6_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT6_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT6_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT6_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT6_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_STALL register field value. */
#define ALT_USB_HOST_HCINT6_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT6_STALL register field value. */
#define ALT_USB_HOST_HCINT6_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT6_STALL register field. */
#define ALT_USB_HOST_HCINT6_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_STALL field value from a register. */
#define ALT_USB_HOST_HCINT6_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT6_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT6_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT6_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT6_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT6_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_NAK register field value. */
#define ALT_USB_HOST_HCINT6_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT6_NAK register field value. */
#define ALT_USB_HOST_HCINT6_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT6_NAK register field. */
#define ALT_USB_HOST_HCINT6_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_NAK field value from a register. */
#define ALT_USB_HOST_HCINT6_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT6_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT6_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT6_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT6_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT6_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_ACK register field value. */
#define ALT_USB_HOST_HCINT6_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT6_ACK register field value. */
#define ALT_USB_HOST_HCINT6_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT6_ACK register field. */
#define ALT_USB_HOST_HCINT6_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_ACK field value from a register. */
#define ALT_USB_HOST_HCINT6_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT6_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT6_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT6_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT6_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT6_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_NYET register field value. */
#define ALT_USB_HOST_HCINT6_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT6_NYET register field value. */
#define ALT_USB_HOST_HCINT6_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT6_NYET register field. */
#define ALT_USB_HOST_HCINT6_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_NYET field value from a register. */
#define ALT_USB_HOST_HCINT6_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT6_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT6_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT6_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT6_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT6_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_XACTERR register field value. */
#define ALT_USB_HOST_HCINT6_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT6_XACTERR register field value. */
#define ALT_USB_HOST_HCINT6_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT6_XACTERR register field. */
#define ALT_USB_HOST_HCINT6_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT6_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT6_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT6_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT6_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT6_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT6_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_BBLERR register field value. */
#define ALT_USB_HOST_HCINT6_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT6_BBLERR register field value. */
#define ALT_USB_HOST_HCINT6_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT6_BBLERR register field. */
#define ALT_USB_HOST_HCINT6_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT6_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT6_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT6_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT6_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT6_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT6_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT6_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT6_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT6_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT6_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT6_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT6_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT6_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT6_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT6_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT6_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT6_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT6_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT6_BNAINTR register field. */
#define ALT_USB_HOST_HCINT6_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT6_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT6_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT6.
*/
struct ALT_USB_HOST_HCINT6_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT6_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT6_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT6_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT6_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT6_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT6_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT6_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT6_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT6_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT6_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT6_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT6_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT6_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT6_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT6. */
typedef volatile struct ALT_USB_HOST_HCINT6_s ALT_USB_HOST_HCINT6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT6 register. */
#define ALT_USB_HOST_HCINT6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT6 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT6_OFST 0x1c8
/* The address of the ALT_USB_HOST_HCINT6 register. */
#define ALT_USB_HOST_HCINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT6_OFST))
/*
* Register : hcintmsk6
*
* Host Channel 6 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK6_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK6_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK6_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK6_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK6_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK6_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK6_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK6_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK6_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK6_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK6_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK6_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK6_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK6.
*/
struct ALT_USB_HOST_HCINTMSK6_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK6_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK6_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK6_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK6_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK6_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK6_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK6_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK6_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK6. */
typedef volatile struct ALT_USB_HOST_HCINTMSK6_s ALT_USB_HOST_HCINTMSK6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK6 register. */
#define ALT_USB_HOST_HCINTMSK6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK6 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK6_OFST 0x1cc
/* The address of the ALT_USB_HOST_HCINTMSK6 register. */
#define ALT_USB_HOST_HCINTMSK6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK6_OFST))
/*
* Register : hctsiz6
*
* Host Channel 6 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ6_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ6_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ6_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ6_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ6_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_PID register field value. */
#define ALT_USB_HOST_HCTSIZ6_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_PID register field value. */
#define ALT_USB_HOST_HCTSIZ6_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_PID register field. */
#define ALT_USB_HOST_HCTSIZ6_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ6_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ6_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ6_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ6_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ6_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ6_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ6_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ6_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ6.
*/
struct ALT_USB_HOST_HCTSIZ6_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ6_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ6_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ6_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ6_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ6. */
typedef volatile struct ALT_USB_HOST_HCTSIZ6_s ALT_USB_HOST_HCTSIZ6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ6 register. */
#define ALT_USB_HOST_HCTSIZ6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ6 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ6_OFST 0x1d0
/* The address of the ALT_USB_HOST_HCTSIZ6 register. */
#define ALT_USB_HOST_HCTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ6_OFST))
/*
* Register : hcdma6
*
* Host Channel 6 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA6_HCDMA6
*
*/
/*
* Field : hcdma6
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA6_HCDMA6 register field value. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA6_HCDMA6 register field. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA6_HCDMA6 field value from a register. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA6_HCDMA6 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA6_HCDMA6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA6.
*/
struct ALT_USB_HOST_HCDMA6_s
{
uint32_t hcdma6 : 32; /* ALT_USB_HOST_HCDMA6_HCDMA6 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA6. */
typedef volatile struct ALT_USB_HOST_HCDMA6_s ALT_USB_HOST_HCDMA6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA6 register. */
#define ALT_USB_HOST_HCDMA6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA6 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA6_OFST 0x1d4
/* The address of the ALT_USB_HOST_HCDMA6 register. */
#define ALT_USB_HOST_HCDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA6_OFST))
/*
* Register : hcdmab6
*
* Host Channel 6 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB6_HCDMAB6
*
*/
/*
* Field : hcdmab6
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB6_HCDMAB6 register field. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB6_HCDMAB6 field value from a register. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB6_HCDMAB6 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB6_HCDMAB6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB6.
*/
struct ALT_USB_HOST_HCDMAB6_s
{
uint32_t hcdmab6 : 32; /* ALT_USB_HOST_HCDMAB6_HCDMAB6 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB6. */
typedef volatile struct ALT_USB_HOST_HCDMAB6_s ALT_USB_HOST_HCDMAB6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB6 register. */
#define ALT_USB_HOST_HCDMAB6_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB6 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB6_OFST 0x1dc
/* The address of the ALT_USB_HOST_HCDMAB6 register. */
#define ALT_USB_HOST_HCDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB6_OFST))
/*
* Register : hcchar7
*
* Host Channel 7 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR7_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR7_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR7_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR7_MPS register field value. */
#define ALT_USB_HOST_HCCHAR7_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_MPS register field value. */
#define ALT_USB_HOST_HCCHAR7_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR7_MPS register field. */
#define ALT_USB_HOST_HCCHAR7_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR7_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR7_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR7_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR7_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR7_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR7_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR7_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR7_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR7_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR7_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR7_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR7_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR7_EC register field value. */
#define ALT_USB_HOST_HCCHAR7_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_EC register field value. */
#define ALT_USB_HOST_HCCHAR7_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_EC register field. */
#define ALT_USB_HOST_HCCHAR7_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR7_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR7_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR7_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR7_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR7_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR7_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR7_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR7_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR7_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR7_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR7_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR7_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR7_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR7_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR7_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR7_CHENA register field. */
#define ALT_USB_HOST_HCCHAR7_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR7_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR7_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR7_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR7_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR7.
*/
struct ALT_USB_HOST_HCCHAR7_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR7_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR7_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR7_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR7_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR7_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR7_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR7_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR7_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR7_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR7_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR7. */
typedef volatile struct ALT_USB_HOST_HCCHAR7_s ALT_USB_HOST_HCCHAR7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR7 register. */
#define ALT_USB_HOST_HCCHAR7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR7 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR7_OFST 0x1e0
/* The address of the ALT_USB_HOST_HCCHAR7 register. */
#define ALT_USB_HOST_HCCHAR7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR7_OFST))
/*
* Register : hcsplt7
*
* Host Channel 7 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT7_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT7_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT7_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT7_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT7_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT7_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT7_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT7_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT7_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT7_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT7_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT7_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT7_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT7_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT7_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT7_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT7_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT7_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT7_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT7.
*/
struct ALT_USB_HOST_HCSPLT7_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT7_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT7_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT7_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT7_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT7_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT7. */
typedef volatile struct ALT_USB_HOST_HCSPLT7_s ALT_USB_HOST_HCSPLT7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT7 register. */
#define ALT_USB_HOST_HCSPLT7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT7 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT7_OFST 0x1e4
/* The address of the ALT_USB_HOST_HCSPLT7 register. */
#define ALT_USB_HOST_HCSPLT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT7_OFST))
/*
* Register : hcint7
*
* Host Channel 7 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT7_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT7_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT7_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT7_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT7_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT7_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT7_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT7_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT7_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT7_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT7_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT7_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT7_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT7_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT7_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT7_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT7_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT7_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT7_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT7_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT7_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT7_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT7_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT7_CHHLTD register field. */
#define ALT_USB_HOST_HCINT7_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT7_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT7_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT7_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT7_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT7_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT7_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_AHBERR register field value. */
#define ALT_USB_HOST_HCINT7_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT7_AHBERR register field value. */
#define ALT_USB_HOST_HCINT7_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT7_AHBERR register field. */
#define ALT_USB_HOST_HCINT7_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT7_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT7_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT7_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT7_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_STALL register field value. */
#define ALT_USB_HOST_HCINT7_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT7_STALL register field value. */
#define ALT_USB_HOST_HCINT7_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT7_STALL register field. */
#define ALT_USB_HOST_HCINT7_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_STALL field value from a register. */
#define ALT_USB_HOST_HCINT7_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT7_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT7_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT7_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT7_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT7_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_NAK register field value. */
#define ALT_USB_HOST_HCINT7_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT7_NAK register field value. */
#define ALT_USB_HOST_HCINT7_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT7_NAK register field. */
#define ALT_USB_HOST_HCINT7_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_NAK field value from a register. */
#define ALT_USB_HOST_HCINT7_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT7_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT7_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT7_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT7_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT7_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_ACK register field value. */
#define ALT_USB_HOST_HCINT7_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT7_ACK register field value. */
#define ALT_USB_HOST_HCINT7_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT7_ACK register field. */
#define ALT_USB_HOST_HCINT7_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_ACK field value from a register. */
#define ALT_USB_HOST_HCINT7_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT7_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT7_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT7_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT7_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT7_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_NYET register field value. */
#define ALT_USB_HOST_HCINT7_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT7_NYET register field value. */
#define ALT_USB_HOST_HCINT7_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT7_NYET register field. */
#define ALT_USB_HOST_HCINT7_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_NYET field value from a register. */
#define ALT_USB_HOST_HCINT7_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT7_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT7_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT7_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT7_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT7_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_XACTERR register field value. */
#define ALT_USB_HOST_HCINT7_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT7_XACTERR register field value. */
#define ALT_USB_HOST_HCINT7_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT7_XACTERR register field. */
#define ALT_USB_HOST_HCINT7_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT7_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT7_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT7_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT7_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT7_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT7_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_BBLERR register field value. */
#define ALT_USB_HOST_HCINT7_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT7_BBLERR register field value. */
#define ALT_USB_HOST_HCINT7_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT7_BBLERR register field. */
#define ALT_USB_HOST_HCINT7_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT7_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT7_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT7_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT7_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT7_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT7_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT7_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT7_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT7_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT7_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT7_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT7_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT7_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT7_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT7_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT7_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT7_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT7_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT7_BNAINTR register field. */
#define ALT_USB_HOST_HCINT7_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT7_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT7_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT7.
*/
struct ALT_USB_HOST_HCINT7_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT7_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT7_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT7_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT7_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT7_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT7_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT7_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT7_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT7_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT7_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT7_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT7_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT7_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT7_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT7. */
typedef volatile struct ALT_USB_HOST_HCINT7_s ALT_USB_HOST_HCINT7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT7 register. */
#define ALT_USB_HOST_HCINT7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT7 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT7_OFST 0x1e8
/* The address of the ALT_USB_HOST_HCINT7 register. */
#define ALT_USB_HOST_HCINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT7_OFST))
/*
* Register : hcintmsk7
*
* Host Channel 7 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK7_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK7_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK7_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK7_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK7_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK7_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK7_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK7_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK7_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK7_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK7_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK7_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK7_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK7.
*/
struct ALT_USB_HOST_HCINTMSK7_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK7_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK7_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK7_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK7_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK7_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK7_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK7_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK7_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK7. */
typedef volatile struct ALT_USB_HOST_HCINTMSK7_s ALT_USB_HOST_HCINTMSK7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK7 register. */
#define ALT_USB_HOST_HCINTMSK7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK7 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK7_OFST 0x1ec
/* The address of the ALT_USB_HOST_HCINTMSK7 register. */
#define ALT_USB_HOST_HCINTMSK7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK7_OFST))
/*
* Register : hctsiz7
*
* Host Channel 7 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ7_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ7_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ7_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ7_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ7_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_PID register field value. */
#define ALT_USB_HOST_HCTSIZ7_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_PID register field value. */
#define ALT_USB_HOST_HCTSIZ7_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_PID register field. */
#define ALT_USB_HOST_HCTSIZ7_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ7_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ7_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ7_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ7_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ7_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ7_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ7_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ7_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ7.
*/
struct ALT_USB_HOST_HCTSIZ7_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ7_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ7_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ7_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ7_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ7. */
typedef volatile struct ALT_USB_HOST_HCTSIZ7_s ALT_USB_HOST_HCTSIZ7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ7 register. */
#define ALT_USB_HOST_HCTSIZ7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ7 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ7_OFST 0x1f0
/* The address of the ALT_USB_HOST_HCTSIZ7 register. */
#define ALT_USB_HOST_HCTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ7_OFST))
/*
* Register : hcdma7
*
* Host Channel 7 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA7_HCDMA7
*
*/
/*
* Field : hcdma7
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA7_HCDMA7 register field value. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA7_HCDMA7 register field. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA7_HCDMA7 field value from a register. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA7_HCDMA7 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA7_HCDMA7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA7.
*/
struct ALT_USB_HOST_HCDMA7_s
{
uint32_t hcdma7 : 32; /* ALT_USB_HOST_HCDMA7_HCDMA7 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA7. */
typedef volatile struct ALT_USB_HOST_HCDMA7_s ALT_USB_HOST_HCDMA7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA7 register. */
#define ALT_USB_HOST_HCDMA7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA7 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA7_OFST 0x1f4
/* The address of the ALT_USB_HOST_HCDMA7 register. */
#define ALT_USB_HOST_HCDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA7_OFST))
/*
* Register : hcdmab7
*
* Host Channel 7 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB7_HCDMAB7
*
*/
/*
* Field : hcdmab7
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB7_HCDMAB7 register field. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB7_HCDMAB7 field value from a register. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB7_HCDMAB7 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB7_HCDMAB7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB7.
*/
struct ALT_USB_HOST_HCDMAB7_s
{
uint32_t hcdmab7 : 32; /* ALT_USB_HOST_HCDMAB7_HCDMAB7 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB7. */
typedef volatile struct ALT_USB_HOST_HCDMAB7_s ALT_USB_HOST_HCDMAB7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB7 register. */
#define ALT_USB_HOST_HCDMAB7_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB7 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB7_OFST 0x1fc
/* The address of the ALT_USB_HOST_HCDMAB7 register. */
#define ALT_USB_HOST_HCDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB7_OFST))
/*
* Register : hcchar8
*
* Host Channel 8 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR8_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR8_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR8_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR8_MPS register field value. */
#define ALT_USB_HOST_HCCHAR8_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_MPS register field value. */
#define ALT_USB_HOST_HCCHAR8_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR8_MPS register field. */
#define ALT_USB_HOST_HCCHAR8_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR8_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR8_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR8_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR8_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR8_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR8_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR8_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR8_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR8_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR8_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR8_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR8_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR8_EC register field value. */
#define ALT_USB_HOST_HCCHAR8_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_EC register field value. */
#define ALT_USB_HOST_HCCHAR8_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_EC register field. */
#define ALT_USB_HOST_HCCHAR8_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR8_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR8_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR8_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR8_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR8_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR8_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR8_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR8_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR8_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR8_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR8_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR8_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR8_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR8_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR8_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR8_CHENA register field. */
#define ALT_USB_HOST_HCCHAR8_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR8_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR8_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR8_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR8_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR8.
*/
struct ALT_USB_HOST_HCCHAR8_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR8_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR8_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR8_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR8_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR8_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR8_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR8_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR8_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR8_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR8_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR8. */
typedef volatile struct ALT_USB_HOST_HCCHAR8_s ALT_USB_HOST_HCCHAR8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR8 register. */
#define ALT_USB_HOST_HCCHAR8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR8 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR8_OFST 0x200
/* The address of the ALT_USB_HOST_HCCHAR8 register. */
#define ALT_USB_HOST_HCCHAR8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR8_OFST))
/*
* Register : hcsplt8
*
* Host Channel 8 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT8_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT8_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT8_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT8_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT8_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT8_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT8_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT8_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT8_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT8_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT8_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT8_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT8_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT8_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT8_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT8_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT8_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT8_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT8_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT8.
*/
struct ALT_USB_HOST_HCSPLT8_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT8_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT8_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT8_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT8_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT8_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT8. */
typedef volatile struct ALT_USB_HOST_HCSPLT8_s ALT_USB_HOST_HCSPLT8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT8 register. */
#define ALT_USB_HOST_HCSPLT8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT8 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT8_OFST 0x204
/* The address of the ALT_USB_HOST_HCSPLT8 register. */
#define ALT_USB_HOST_HCSPLT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT8_OFST))
/*
* Register : hcint8
*
* Host Channel 8 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT8_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT8_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT8_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT8_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT8_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT8_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT8_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT8_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT8_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT8_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT8_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT8_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT8_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT8_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT8_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT8_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT8_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT8_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT8_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT8_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT8_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT8_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT8_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT8_CHHLTD register field. */
#define ALT_USB_HOST_HCINT8_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT8_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT8_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT8_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT8_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT8_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT8_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_AHBERR register field value. */
#define ALT_USB_HOST_HCINT8_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT8_AHBERR register field value. */
#define ALT_USB_HOST_HCINT8_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT8_AHBERR register field. */
#define ALT_USB_HOST_HCINT8_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT8_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT8_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT8_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT8_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_STALL register field value. */
#define ALT_USB_HOST_HCINT8_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT8_STALL register field value. */
#define ALT_USB_HOST_HCINT8_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT8_STALL register field. */
#define ALT_USB_HOST_HCINT8_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_STALL field value from a register. */
#define ALT_USB_HOST_HCINT8_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT8_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT8_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT8_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT8_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT8_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_NAK register field value. */
#define ALT_USB_HOST_HCINT8_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT8_NAK register field value. */
#define ALT_USB_HOST_HCINT8_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT8_NAK register field. */
#define ALT_USB_HOST_HCINT8_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_NAK field value from a register. */
#define ALT_USB_HOST_HCINT8_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT8_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT8_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT8_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT8_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT8_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_ACK register field value. */
#define ALT_USB_HOST_HCINT8_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT8_ACK register field value. */
#define ALT_USB_HOST_HCINT8_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT8_ACK register field. */
#define ALT_USB_HOST_HCINT8_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_ACK field value from a register. */
#define ALT_USB_HOST_HCINT8_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT8_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT8_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT8_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT8_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT8_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_NYET register field value. */
#define ALT_USB_HOST_HCINT8_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT8_NYET register field value. */
#define ALT_USB_HOST_HCINT8_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT8_NYET register field. */
#define ALT_USB_HOST_HCINT8_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_NYET field value from a register. */
#define ALT_USB_HOST_HCINT8_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT8_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT8_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT8_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT8_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT8_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_XACTERR register field value. */
#define ALT_USB_HOST_HCINT8_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT8_XACTERR register field value. */
#define ALT_USB_HOST_HCINT8_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT8_XACTERR register field. */
#define ALT_USB_HOST_HCINT8_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT8_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT8_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT8_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT8_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT8_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT8_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_BBLERR register field value. */
#define ALT_USB_HOST_HCINT8_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT8_BBLERR register field value. */
#define ALT_USB_HOST_HCINT8_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT8_BBLERR register field. */
#define ALT_USB_HOST_HCINT8_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT8_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT8_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT8_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT8_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT8_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT8_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT8_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT8_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT8_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT8_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT8_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT8_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT8_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT8_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT8_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT8_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT8_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT8_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT8_BNAINTR register field. */
#define ALT_USB_HOST_HCINT8_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT8_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT8_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT8.
*/
struct ALT_USB_HOST_HCINT8_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT8_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT8_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT8_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT8_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT8_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT8_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT8_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT8_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT8_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT8_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT8_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT8_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT8_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT8_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT8. */
typedef volatile struct ALT_USB_HOST_HCINT8_s ALT_USB_HOST_HCINT8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT8 register. */
#define ALT_USB_HOST_HCINT8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT8 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT8_OFST 0x208
/* The address of the ALT_USB_HOST_HCINT8 register. */
#define ALT_USB_HOST_HCINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT8_OFST))
/*
* Register : hcintmsk8
*
* Host Channel 8 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK8_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK8_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK8_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK8_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK8_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK8_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK8_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK8_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK8_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK8_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK8_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK8_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK8_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK8.
*/
struct ALT_USB_HOST_HCINTMSK8_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK8_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK8_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK8_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK8_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK8_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK8_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK8_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK8_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK8. */
typedef volatile struct ALT_USB_HOST_HCINTMSK8_s ALT_USB_HOST_HCINTMSK8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK8 register. */
#define ALT_USB_HOST_HCINTMSK8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK8 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK8_OFST 0x20c
/* The address of the ALT_USB_HOST_HCINTMSK8 register. */
#define ALT_USB_HOST_HCINTMSK8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK8_OFST))
/*
* Register : hctsiz8
*
* Host Channel 8 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ8_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ8_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ8_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ8_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ8_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_PID register field value. */
#define ALT_USB_HOST_HCTSIZ8_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_PID register field value. */
#define ALT_USB_HOST_HCTSIZ8_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_PID register field. */
#define ALT_USB_HOST_HCTSIZ8_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ8_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ8_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ8_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ8_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ8_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ8_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ8_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ8_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ8.
*/
struct ALT_USB_HOST_HCTSIZ8_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ8_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ8_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ8_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ8_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ8. */
typedef volatile struct ALT_USB_HOST_HCTSIZ8_s ALT_USB_HOST_HCTSIZ8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ8 register. */
#define ALT_USB_HOST_HCTSIZ8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ8 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ8_OFST 0x210
/* The address of the ALT_USB_HOST_HCTSIZ8 register. */
#define ALT_USB_HOST_HCTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ8_OFST))
/*
* Register : hcdma8
*
* Host Channel 8 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA8_HCDMA8
*
*/
/*
* Field : hcdma8
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA8_HCDMA8 register field value. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA8_HCDMA8 register field. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA8_HCDMA8 field value from a register. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA8_HCDMA8 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA8_HCDMA8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA8.
*/
struct ALT_USB_HOST_HCDMA8_s
{
uint32_t hcdma8 : 32; /* ALT_USB_HOST_HCDMA8_HCDMA8 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA8. */
typedef volatile struct ALT_USB_HOST_HCDMA8_s ALT_USB_HOST_HCDMA8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA8 register. */
#define ALT_USB_HOST_HCDMA8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA8 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA8_OFST 0x214
/* The address of the ALT_USB_HOST_HCDMA8 register. */
#define ALT_USB_HOST_HCDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA8_OFST))
/*
* Register : hcdmab8
*
* Host Channel 8 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB8_HCDMAB8
*
*/
/*
* Field : hcdmab8
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB8_HCDMAB8 register field. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB8_HCDMAB8 field value from a register. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB8_HCDMAB8 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB8_HCDMAB8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB8.
*/
struct ALT_USB_HOST_HCDMAB8_s
{
uint32_t hcdmab8 : 32; /* ALT_USB_HOST_HCDMAB8_HCDMAB8 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB8. */
typedef volatile struct ALT_USB_HOST_HCDMAB8_s ALT_USB_HOST_HCDMAB8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB8 register. */
#define ALT_USB_HOST_HCDMAB8_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB8 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB8_OFST 0x21c
/* The address of the ALT_USB_HOST_HCDMAB8 register. */
#define ALT_USB_HOST_HCDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB8_OFST))
/*
* Register : hcchar9
*
* Host Channel 9 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-----------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR9_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR9_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR9_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR9_MPS register field value. */
#define ALT_USB_HOST_HCCHAR9_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_MPS register field value. */
#define ALT_USB_HOST_HCCHAR9_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR9_MPS register field. */
#define ALT_USB_HOST_HCCHAR9_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR9_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR9_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR9_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR9_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR9_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR9_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR9_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR9_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR9_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR9_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR9_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR9_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR9_EC register field value. */
#define ALT_USB_HOST_HCCHAR9_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_EC register field value. */
#define ALT_USB_HOST_HCCHAR9_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_EC register field. */
#define ALT_USB_HOST_HCCHAR9_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR9_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR9_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR9_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR9_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR9_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR9_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR9_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR9_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR9_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR9_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR9_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR9_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR9_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR9_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR9_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR9_CHENA register field. */
#define ALT_USB_HOST_HCCHAR9_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR9_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR9_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR9_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR9_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR9.
*/
struct ALT_USB_HOST_HCCHAR9_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR9_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR9_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR9_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR9_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR9_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR9_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR9_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR9_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR9_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR9_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR9. */
typedef volatile struct ALT_USB_HOST_HCCHAR9_s ALT_USB_HOST_HCCHAR9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR9 register. */
#define ALT_USB_HOST_HCCHAR9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR9 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR9_OFST 0x220
/* The address of the ALT_USB_HOST_HCCHAR9 register. */
#define ALT_USB_HOST_HCCHAR9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR9_OFST))
/*
* Register : hcsplt9
*
* Host Channel 9 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT9_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT9_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT9_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT9_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT9_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT9_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT9_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT9_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT9_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT9_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT9_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT9_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT9_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT9_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT9_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT9_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT9_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT9_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT9_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT9.
*/
struct ALT_USB_HOST_HCSPLT9_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT9_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT9_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT9_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT9_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT9_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT9. */
typedef volatile struct ALT_USB_HOST_HCSPLT9_s ALT_USB_HOST_HCSPLT9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT9 register. */
#define ALT_USB_HOST_HCSPLT9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT9 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT9_OFST 0x224
/* The address of the ALT_USB_HOST_HCSPLT9 register. */
#define ALT_USB_HOST_HCSPLT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT9_OFST))
/*
* Register : hcint9
*
* Host Channel 9 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT9_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT9_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT9_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT9_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT9_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT9_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT9_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT9_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT9_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT9_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT9_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT9_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT9_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT9_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT9_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT9_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT9_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT9_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT9_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT9_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT9_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT9_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT9_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT9_CHHLTD register field. */
#define ALT_USB_HOST_HCINT9_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT9_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT9_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT9_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT9_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT9_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT9_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_AHBERR register field value. */
#define ALT_USB_HOST_HCINT9_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT9_AHBERR register field value. */
#define ALT_USB_HOST_HCINT9_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT9_AHBERR register field. */
#define ALT_USB_HOST_HCINT9_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT9_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT9_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT9_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT9_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_STALL register field value. */
#define ALT_USB_HOST_HCINT9_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT9_STALL register field value. */
#define ALT_USB_HOST_HCINT9_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT9_STALL register field. */
#define ALT_USB_HOST_HCINT9_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_STALL field value from a register. */
#define ALT_USB_HOST_HCINT9_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT9_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT9_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT9_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT9_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT9_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_NAK register field value. */
#define ALT_USB_HOST_HCINT9_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT9_NAK register field value. */
#define ALT_USB_HOST_HCINT9_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT9_NAK register field. */
#define ALT_USB_HOST_HCINT9_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_NAK field value from a register. */
#define ALT_USB_HOST_HCINT9_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT9_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT9_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT9_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT9_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT9_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_ACK register field value. */
#define ALT_USB_HOST_HCINT9_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT9_ACK register field value. */
#define ALT_USB_HOST_HCINT9_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT9_ACK register field. */
#define ALT_USB_HOST_HCINT9_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_ACK field value from a register. */
#define ALT_USB_HOST_HCINT9_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT9_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT9_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT9_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT9_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT9_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_NYET register field value. */
#define ALT_USB_HOST_HCINT9_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT9_NYET register field value. */
#define ALT_USB_HOST_HCINT9_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT9_NYET register field. */
#define ALT_USB_HOST_HCINT9_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_NYET field value from a register. */
#define ALT_USB_HOST_HCINT9_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT9_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT9_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT9_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT9_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT9_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_XACTERR register field value. */
#define ALT_USB_HOST_HCINT9_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT9_XACTERR register field value. */
#define ALT_USB_HOST_HCINT9_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT9_XACTERR register field. */
#define ALT_USB_HOST_HCINT9_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT9_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT9_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT9_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT9_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT9_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT9_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_BBLERR register field value. */
#define ALT_USB_HOST_HCINT9_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT9_BBLERR register field value. */
#define ALT_USB_HOST_HCINT9_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT9_BBLERR register field. */
#define ALT_USB_HOST_HCINT9_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT9_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT9_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT9_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT9_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT9_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT9_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT9_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT9_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT9_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT9_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT9_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT9_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT9_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT9_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT9_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT9_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT9_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT9_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT9_BNAINTR register field. */
#define ALT_USB_HOST_HCINT9_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT9_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT9_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT9.
*/
struct ALT_USB_HOST_HCINT9_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT9_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT9_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT9_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT9_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT9_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT9_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT9_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT9_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT9_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT9_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT9_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT9_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT9_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT9_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT9. */
typedef volatile struct ALT_USB_HOST_HCINT9_s ALT_USB_HOST_HCINT9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT9 register. */
#define ALT_USB_HOST_HCINT9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT9 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT9_OFST 0x228
/* The address of the ALT_USB_HOST_HCINT9 register. */
#define ALT_USB_HOST_HCINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT9_OFST))
/*
* Register : hcintmsk9
*
* Host Channel 9 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK9_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK9_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK9_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK9_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK9_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK9_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK9_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK9_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK9_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK9_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK9_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK9_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK9_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK9.
*/
struct ALT_USB_HOST_HCINTMSK9_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK9_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK9_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK9_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK9_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK9_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK9_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK9_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK9_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK9. */
typedef volatile struct ALT_USB_HOST_HCINTMSK9_s ALT_USB_HOST_HCINTMSK9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK9 register. */
#define ALT_USB_HOST_HCINTMSK9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK9 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK9_OFST 0x22c
/* The address of the ALT_USB_HOST_HCINTMSK9 register. */
#define ALT_USB_HOST_HCINTMSK9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK9_OFST))
/*
* Register : hctsiz9
*
* Host Channel 9 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ9_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ9_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ9_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ9_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ9_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_PID register field value. */
#define ALT_USB_HOST_HCTSIZ9_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_PID register field value. */
#define ALT_USB_HOST_HCTSIZ9_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_PID register field. */
#define ALT_USB_HOST_HCTSIZ9_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ9_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ9_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ9_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ9_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ9_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ9_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ9_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ9_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ9.
*/
struct ALT_USB_HOST_HCTSIZ9_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ9_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ9_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ9_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ9_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ9. */
typedef volatile struct ALT_USB_HOST_HCTSIZ9_s ALT_USB_HOST_HCTSIZ9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ9 register. */
#define ALT_USB_HOST_HCTSIZ9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ9 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ9_OFST 0x230
/* The address of the ALT_USB_HOST_HCTSIZ9 register. */
#define ALT_USB_HOST_HCTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ9_OFST))
/*
* Register : hcdma9
*
* Host Channel 9 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:---------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA9_HCDMA9
*
*/
/*
* Field : hcdma9
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA9_HCDMA9 register field value. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA9_HCDMA9 register field. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA9_HCDMA9 field value from a register. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA9_HCDMA9 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA9_HCDMA9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA9.
*/
struct ALT_USB_HOST_HCDMA9_s
{
uint32_t hcdma9 : 32; /* ALT_USB_HOST_HCDMA9_HCDMA9 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA9. */
typedef volatile struct ALT_USB_HOST_HCDMA9_s ALT_USB_HOST_HCDMA9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA9 register. */
#define ALT_USB_HOST_HCDMA9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA9 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA9_OFST 0x234
/* The address of the ALT_USB_HOST_HCDMA9 register. */
#define ALT_USB_HOST_HCDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA9_OFST))
/*
* Register : hcdmab9
*
* Host Channel 9 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB9_HCDMAB9
*
*/
/*
* Field : hcdmab9
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB9_HCDMAB9 register field. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB9_HCDMAB9 field value from a register. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB9_HCDMAB9 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB9_HCDMAB9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB9.
*/
struct ALT_USB_HOST_HCDMAB9_s
{
uint32_t hcdmab9 : 32; /* ALT_USB_HOST_HCDMAB9_HCDMAB9 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB9. */
typedef volatile struct ALT_USB_HOST_HCDMAB9_s ALT_USB_HOST_HCDMAB9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB9 register. */
#define ALT_USB_HOST_HCDMAB9_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB9 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB9_OFST 0x23c
/* The address of the ALT_USB_HOST_HCDMAB9 register. */
#define ALT_USB_HOST_HCDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB9_OFST))
/*
* Register : hcchar10
*
* Host Channel 10 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR10_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR10_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR10_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR10_MPS register field value. */
#define ALT_USB_HOST_HCCHAR10_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_MPS register field value. */
#define ALT_USB_HOST_HCCHAR10_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR10_MPS register field. */
#define ALT_USB_HOST_HCCHAR10_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR10_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR10_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR10_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR10_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR10_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR10_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR10_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR10_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR10_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR10_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR10_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR10_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR10_EC register field value. */
#define ALT_USB_HOST_HCCHAR10_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_EC register field value. */
#define ALT_USB_HOST_HCCHAR10_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_EC register field. */
#define ALT_USB_HOST_HCCHAR10_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR10_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR10_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR10_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR10_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR10_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR10_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR10_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR10_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR10_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR10_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR10_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR10_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR10_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR10_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR10_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR10_CHENA register field. */
#define ALT_USB_HOST_HCCHAR10_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR10_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR10_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR10_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR10_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR10.
*/
struct ALT_USB_HOST_HCCHAR10_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR10_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR10_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR10_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR10_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR10_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR10_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR10_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR10_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR10_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR10_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR10. */
typedef volatile struct ALT_USB_HOST_HCCHAR10_s ALT_USB_HOST_HCCHAR10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR10 register. */
#define ALT_USB_HOST_HCCHAR10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR10 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR10_OFST 0x240
/* The address of the ALT_USB_HOST_HCCHAR10 register. */
#define ALT_USB_HOST_HCCHAR10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR10_OFST))
/*
* Register : hcsplt10
*
* Host Channel 10 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT10_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT10_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT10_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT10_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT10_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT10_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT10_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT10_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT10_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT10_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT10_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT10_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT10_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT10_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT10_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT10_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT10_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT10_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT10_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT10.
*/
struct ALT_USB_HOST_HCSPLT10_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT10_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT10_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT10_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT10_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT10_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT10. */
typedef volatile struct ALT_USB_HOST_HCSPLT10_s ALT_USB_HOST_HCSPLT10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT10 register. */
#define ALT_USB_HOST_HCSPLT10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT10 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT10_OFST 0x244
/* The address of the ALT_USB_HOST_HCSPLT10 register. */
#define ALT_USB_HOST_HCSPLT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT10_OFST))
/*
* Register : hcint10
*
* Host Channel 10 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT10_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT10_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT10_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT10_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT10_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT10_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT10_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT10_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT10_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT10_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT10_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT10_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT10_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT10_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT10_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT10_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT10_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT10_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT10_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT10_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT10_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT10_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT10_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT10_CHHLTD register field. */
#define ALT_USB_HOST_HCINT10_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT10_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT10_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT10_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT10_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT10_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT10_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_AHBERR register field value. */
#define ALT_USB_HOST_HCINT10_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT10_AHBERR register field value. */
#define ALT_USB_HOST_HCINT10_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT10_AHBERR register field. */
#define ALT_USB_HOST_HCINT10_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT10_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT10_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT10_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT10_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_STALL register field value. */
#define ALT_USB_HOST_HCINT10_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT10_STALL register field value. */
#define ALT_USB_HOST_HCINT10_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT10_STALL register field. */
#define ALT_USB_HOST_HCINT10_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_STALL field value from a register. */
#define ALT_USB_HOST_HCINT10_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT10_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT10_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT10_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT10_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT10_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_NAK register field value. */
#define ALT_USB_HOST_HCINT10_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT10_NAK register field value. */
#define ALT_USB_HOST_HCINT10_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT10_NAK register field. */
#define ALT_USB_HOST_HCINT10_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_NAK field value from a register. */
#define ALT_USB_HOST_HCINT10_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT10_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT10_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT10_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT10_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT10_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_ACK register field value. */
#define ALT_USB_HOST_HCINT10_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT10_ACK register field value. */
#define ALT_USB_HOST_HCINT10_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT10_ACK register field. */
#define ALT_USB_HOST_HCINT10_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_ACK field value from a register. */
#define ALT_USB_HOST_HCINT10_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT10_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT10_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT10_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT10_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT10_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_NYET register field value. */
#define ALT_USB_HOST_HCINT10_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT10_NYET register field value. */
#define ALT_USB_HOST_HCINT10_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT10_NYET register field. */
#define ALT_USB_HOST_HCINT10_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_NYET field value from a register. */
#define ALT_USB_HOST_HCINT10_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT10_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT10_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT10_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT10_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT10_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_XACTERR register field value. */
#define ALT_USB_HOST_HCINT10_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT10_XACTERR register field value. */
#define ALT_USB_HOST_HCINT10_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT10_XACTERR register field. */
#define ALT_USB_HOST_HCINT10_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT10_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT10_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT10_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT10_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT10_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT10_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_BBLERR register field value. */
#define ALT_USB_HOST_HCINT10_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT10_BBLERR register field value. */
#define ALT_USB_HOST_HCINT10_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT10_BBLERR register field. */
#define ALT_USB_HOST_HCINT10_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT10_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT10_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT10_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT10_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT10_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT10_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT10_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT10_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT10_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT10_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT10_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT10_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT10_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT10_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT10_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT10_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT10_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT10_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT10_BNAINTR register field. */
#define ALT_USB_HOST_HCINT10_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT10_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT10_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT10.
*/
struct ALT_USB_HOST_HCINT10_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT10_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT10_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT10_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT10_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT10_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT10_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT10_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT10_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT10_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT10_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT10_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT10_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT10_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT10_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT10. */
typedef volatile struct ALT_USB_HOST_HCINT10_s ALT_USB_HOST_HCINT10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT10 register. */
#define ALT_USB_HOST_HCINT10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT10 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT10_OFST 0x248
/* The address of the ALT_USB_HOST_HCINT10 register. */
#define ALT_USB_HOST_HCINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT10_OFST))
/*
* Register : hcintmsk10
*
* Host Channel 10 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK10_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK10_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK10_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK10_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK10_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK10_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK10_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK10_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK10_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK10_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK10_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK10_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK10_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK10.
*/
struct ALT_USB_HOST_HCINTMSK10_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK10_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK10_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK10_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK10_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK10_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK10_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK10_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK10_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK10. */
typedef volatile struct ALT_USB_HOST_HCINTMSK10_s ALT_USB_HOST_HCINTMSK10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK10 register. */
#define ALT_USB_HOST_HCINTMSK10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK10 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK10_OFST 0x24c
/* The address of the ALT_USB_HOST_HCINTMSK10 register. */
#define ALT_USB_HOST_HCINTMSK10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK10_OFST))
/*
* Register : hctsiz10
*
* Host Channel 10 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ10_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ10_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ10_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ10_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ10_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_PID register field value. */
#define ALT_USB_HOST_HCTSIZ10_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_PID register field value. */
#define ALT_USB_HOST_HCTSIZ10_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_PID register field. */
#define ALT_USB_HOST_HCTSIZ10_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ10_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ10_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ10_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ10_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ10_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ10_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ10_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ10_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ10.
*/
struct ALT_USB_HOST_HCTSIZ10_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ10_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ10_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ10_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ10_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ10. */
typedef volatile struct ALT_USB_HOST_HCTSIZ10_s ALT_USB_HOST_HCTSIZ10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ10 register. */
#define ALT_USB_HOST_HCTSIZ10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ10 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ10_OFST 0x250
/* The address of the ALT_USB_HOST_HCTSIZ10 register. */
#define ALT_USB_HOST_HCTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ10_OFST))
/*
* Register : hcdma10
*
* Host Channel 10 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA10_HCDMA10
*
*/
/*
* Field : hcdma10
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA10_HCDMA10 register field value. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA10_HCDMA10 register field. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA10_HCDMA10 field value from a register. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA10_HCDMA10 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA10_HCDMA10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA10.
*/
struct ALT_USB_HOST_HCDMA10_s
{
uint32_t hcdma10 : 32; /* ALT_USB_HOST_HCDMA10_HCDMA10 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA10. */
typedef volatile struct ALT_USB_HOST_HCDMA10_s ALT_USB_HOST_HCDMA10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA10 register. */
#define ALT_USB_HOST_HCDMA10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA10 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA10_OFST 0x254
/* The address of the ALT_USB_HOST_HCDMA10 register. */
#define ALT_USB_HOST_HCDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA10_OFST))
/*
* Register : hcdmab10
*
* Host Channel 10 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB10_HCDMAB10
*
*/
/*
* Field : hcdmab10
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB10_HCDMAB10 register field. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB10_HCDMAB10 field value from a register. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB10_HCDMAB10 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB10_HCDMAB10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB10.
*/
struct ALT_USB_HOST_HCDMAB10_s
{
uint32_t hcdmab10 : 32; /* ALT_USB_HOST_HCDMAB10_HCDMAB10 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB10. */
typedef volatile struct ALT_USB_HOST_HCDMAB10_s ALT_USB_HOST_HCDMAB10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB10 register. */
#define ALT_USB_HOST_HCDMAB10_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB10 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB10_OFST 0x25c
/* The address of the ALT_USB_HOST_HCDMAB10 register. */
#define ALT_USB_HOST_HCDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB10_OFST))
/*
* Register : hcchar11
*
* Host Channel 11 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR11_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR11_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR11_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR11_MPS register field value. */
#define ALT_USB_HOST_HCCHAR11_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_MPS register field value. */
#define ALT_USB_HOST_HCCHAR11_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR11_MPS register field. */
#define ALT_USB_HOST_HCCHAR11_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR11_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR11_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR11_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR11_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR11_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR11_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR11_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR11_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR11_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR11_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR11_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR11_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR11_EC register field value. */
#define ALT_USB_HOST_HCCHAR11_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_EC register field value. */
#define ALT_USB_HOST_HCCHAR11_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_EC register field. */
#define ALT_USB_HOST_HCCHAR11_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR11_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR11_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR11_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR11_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR11_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR11_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR11_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR11_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR11_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR11_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR11_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR11_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR11_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR11_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR11_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR11_CHENA register field. */
#define ALT_USB_HOST_HCCHAR11_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR11_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR11_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR11_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR11_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR11.
*/
struct ALT_USB_HOST_HCCHAR11_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR11_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR11_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR11_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR11_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR11_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR11_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR11_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR11_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR11_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR11_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR11. */
typedef volatile struct ALT_USB_HOST_HCCHAR11_s ALT_USB_HOST_HCCHAR11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR11 register. */
#define ALT_USB_HOST_HCCHAR11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR11 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR11_OFST 0x260
/* The address of the ALT_USB_HOST_HCCHAR11 register. */
#define ALT_USB_HOST_HCCHAR11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR11_OFST))
/*
* Register : hcsplt11
*
* Host Channel 11 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT11_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT11_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT11_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT11_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT11_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT11_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT11_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT11_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT11_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT11_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT11_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT11_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT11_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT11_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT11_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT11_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT11_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT11_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT11_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT11.
*/
struct ALT_USB_HOST_HCSPLT11_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT11_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT11_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT11_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT11_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT11_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT11. */
typedef volatile struct ALT_USB_HOST_HCSPLT11_s ALT_USB_HOST_HCSPLT11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT11 register. */
#define ALT_USB_HOST_HCSPLT11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT11 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT11_OFST 0x264
/* The address of the ALT_USB_HOST_HCSPLT11 register. */
#define ALT_USB_HOST_HCSPLT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT11_OFST))
/*
* Register : hcint11
*
* Host Channel 11 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT11_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT11_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT11_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT11_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT11_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT11_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT11_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT11_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT11_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT11_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT11_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT11_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT11_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT11_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT11_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT11_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT11_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT11_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT11_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT11_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT11_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT11_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT11_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT11_CHHLTD register field. */
#define ALT_USB_HOST_HCINT11_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT11_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT11_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT11_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT11_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT11_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT11_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_AHBERR register field value. */
#define ALT_USB_HOST_HCINT11_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT11_AHBERR register field value. */
#define ALT_USB_HOST_HCINT11_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT11_AHBERR register field. */
#define ALT_USB_HOST_HCINT11_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT11_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT11_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT11_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT11_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_STALL register field value. */
#define ALT_USB_HOST_HCINT11_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT11_STALL register field value. */
#define ALT_USB_HOST_HCINT11_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT11_STALL register field. */
#define ALT_USB_HOST_HCINT11_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_STALL field value from a register. */
#define ALT_USB_HOST_HCINT11_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT11_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT11_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT11_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT11_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT11_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_NAK register field value. */
#define ALT_USB_HOST_HCINT11_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT11_NAK register field value. */
#define ALT_USB_HOST_HCINT11_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT11_NAK register field. */
#define ALT_USB_HOST_HCINT11_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_NAK field value from a register. */
#define ALT_USB_HOST_HCINT11_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT11_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT11_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT11_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT11_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT11_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_ACK register field value. */
#define ALT_USB_HOST_HCINT11_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT11_ACK register field value. */
#define ALT_USB_HOST_HCINT11_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT11_ACK register field. */
#define ALT_USB_HOST_HCINT11_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_ACK field value from a register. */
#define ALT_USB_HOST_HCINT11_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT11_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT11_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT11_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT11_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT11_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_NYET register field value. */
#define ALT_USB_HOST_HCINT11_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT11_NYET register field value. */
#define ALT_USB_HOST_HCINT11_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT11_NYET register field. */
#define ALT_USB_HOST_HCINT11_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_NYET field value from a register. */
#define ALT_USB_HOST_HCINT11_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT11_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT11_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT11_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT11_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT11_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_XACTERR register field value. */
#define ALT_USB_HOST_HCINT11_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT11_XACTERR register field value. */
#define ALT_USB_HOST_HCINT11_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT11_XACTERR register field. */
#define ALT_USB_HOST_HCINT11_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT11_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT11_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT11_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT11_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT11_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT11_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_BBLERR register field value. */
#define ALT_USB_HOST_HCINT11_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT11_BBLERR register field value. */
#define ALT_USB_HOST_HCINT11_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT11_BBLERR register field. */
#define ALT_USB_HOST_HCINT11_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT11_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT11_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT11_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT11_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT11_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT11_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT11_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT11_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT11_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT11_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT11_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT11_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT11_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT11_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT11_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT11_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT11_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT11_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT11_BNAINTR register field. */
#define ALT_USB_HOST_HCINT11_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT11_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT11_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT11.
*/
struct ALT_USB_HOST_HCINT11_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT11_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT11_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT11_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT11_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT11_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT11_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT11_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT11_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT11_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT11_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT11_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT11_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT11_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT11_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT11. */
typedef volatile struct ALT_USB_HOST_HCINT11_s ALT_USB_HOST_HCINT11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT11 register. */
#define ALT_USB_HOST_HCINT11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT11 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT11_OFST 0x268
/* The address of the ALT_USB_HOST_HCINT11 register. */
#define ALT_USB_HOST_HCINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT11_OFST))
/*
* Register : hcintmsk11
*
* Host Channel 11 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK11_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK11_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK11_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK11_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK11_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK11_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK11_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK11_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK11_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK11_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK11_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK11_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK11_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK11.
*/
struct ALT_USB_HOST_HCINTMSK11_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK11_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK11_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK11_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK11_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK11_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK11_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK11_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK11_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK11. */
typedef volatile struct ALT_USB_HOST_HCINTMSK11_s ALT_USB_HOST_HCINTMSK11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK11 register. */
#define ALT_USB_HOST_HCINTMSK11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK11 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK11_OFST 0x26c
/* The address of the ALT_USB_HOST_HCINTMSK11 register. */
#define ALT_USB_HOST_HCINTMSK11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK11_OFST))
/*
* Register : hctsiz11
*
* Host Channel 11 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ11_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ11_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ11_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ11_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ11_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_PID register field value. */
#define ALT_USB_HOST_HCTSIZ11_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_PID register field value. */
#define ALT_USB_HOST_HCTSIZ11_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_PID register field. */
#define ALT_USB_HOST_HCTSIZ11_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ11_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ11_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ11_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ11_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ11_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ11_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ11_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ11_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ11.
*/
struct ALT_USB_HOST_HCTSIZ11_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ11_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ11_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ11_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ11_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ11. */
typedef volatile struct ALT_USB_HOST_HCTSIZ11_s ALT_USB_HOST_HCTSIZ11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ11 register. */
#define ALT_USB_HOST_HCTSIZ11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ11 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ11_OFST 0x270
/* The address of the ALT_USB_HOST_HCTSIZ11 register. */
#define ALT_USB_HOST_HCTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ11_OFST))
/*
* Register : hcdma11
*
* Host Channel 11 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA11_HCDMA11
*
*/
/*
* Field : hcdma11
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA11_HCDMA11 register field value. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA11_HCDMA11 register field. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA11_HCDMA11 field value from a register. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA11_HCDMA11 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA11_HCDMA11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA11.
*/
struct ALT_USB_HOST_HCDMA11_s
{
uint32_t hcdma11 : 32; /* ALT_USB_HOST_HCDMA11_HCDMA11 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA11. */
typedef volatile struct ALT_USB_HOST_HCDMA11_s ALT_USB_HOST_HCDMA11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA11 register. */
#define ALT_USB_HOST_HCDMA11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA11 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA11_OFST 0x274
/* The address of the ALT_USB_HOST_HCDMA11 register. */
#define ALT_USB_HOST_HCDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA11_OFST))
/*
* Register : hcdmab11
*
* Host Channel 11 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB11_HCDMAB11
*
*/
/*
* Field : hcdmab11
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB11_HCDMAB11 register field. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB11_HCDMAB11 field value from a register. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB11_HCDMAB11 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB11_HCDMAB11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB11.
*/
struct ALT_USB_HOST_HCDMAB11_s
{
uint32_t hcdmab11 : 32; /* ALT_USB_HOST_HCDMAB11_HCDMAB11 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB11. */
typedef volatile struct ALT_USB_HOST_HCDMAB11_s ALT_USB_HOST_HCDMAB11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB11 register. */
#define ALT_USB_HOST_HCDMAB11_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB11 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB11_OFST 0x27c
/* The address of the ALT_USB_HOST_HCDMAB11 register. */
#define ALT_USB_HOST_HCDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB11_OFST))
/*
* Register : hcchar12
*
* Host Channel 12 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR12_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR12_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR12_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR12_MPS register field value. */
#define ALT_USB_HOST_HCCHAR12_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_MPS register field value. */
#define ALT_USB_HOST_HCCHAR12_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR12_MPS register field. */
#define ALT_USB_HOST_HCCHAR12_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR12_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR12_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR12_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR12_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR12_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR12_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR12_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR12_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR12_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR12_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR12_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR12_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR12_EC register field value. */
#define ALT_USB_HOST_HCCHAR12_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_EC register field value. */
#define ALT_USB_HOST_HCCHAR12_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_EC register field. */
#define ALT_USB_HOST_HCCHAR12_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR12_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR12_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR12_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR12_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR12_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR12_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR12_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR12_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR12_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR12_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR12_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR12_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR12_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR12_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR12_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR12_CHENA register field. */
#define ALT_USB_HOST_HCCHAR12_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR12_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR12_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR12_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR12_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR12.
*/
struct ALT_USB_HOST_HCCHAR12_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR12_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR12_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR12_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR12_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR12_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR12_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR12_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR12_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR12_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR12_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR12. */
typedef volatile struct ALT_USB_HOST_HCCHAR12_s ALT_USB_HOST_HCCHAR12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR12 register. */
#define ALT_USB_HOST_HCCHAR12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR12 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR12_OFST 0x280
/* The address of the ALT_USB_HOST_HCCHAR12 register. */
#define ALT_USB_HOST_HCCHAR12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR12_OFST))
/*
* Register : hcsplt12
*
* Host Channel 12 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT12_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT12_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT12_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT12_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT12_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT12_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT12_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT12_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT12_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT12_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT12_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT12_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT12_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT12_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT12_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT12_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT12_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT12_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT12_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT12.
*/
struct ALT_USB_HOST_HCSPLT12_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT12_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT12_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT12_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT12_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT12_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT12. */
typedef volatile struct ALT_USB_HOST_HCSPLT12_s ALT_USB_HOST_HCSPLT12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT12 register. */
#define ALT_USB_HOST_HCSPLT12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT12 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT12_OFST 0x284
/* The address of the ALT_USB_HOST_HCSPLT12 register. */
#define ALT_USB_HOST_HCSPLT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT12_OFST))
/*
* Register : hcint12
*
* Host Channel 12 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT12_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT12_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT12_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT12_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT12_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT12_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT12_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT12_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT12_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT12_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT12_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT12_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT12_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT12_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT12_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT12_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT12_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT12_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT12_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT12_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT12_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT12_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT12_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT12_CHHLTD register field. */
#define ALT_USB_HOST_HCINT12_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT12_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT12_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT12_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT12_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT12_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT12_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_AHBERR register field value. */
#define ALT_USB_HOST_HCINT12_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT12_AHBERR register field value. */
#define ALT_USB_HOST_HCINT12_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT12_AHBERR register field. */
#define ALT_USB_HOST_HCINT12_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT12_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT12_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT12_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT12_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_STALL register field value. */
#define ALT_USB_HOST_HCINT12_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT12_STALL register field value. */
#define ALT_USB_HOST_HCINT12_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT12_STALL register field. */
#define ALT_USB_HOST_HCINT12_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_STALL field value from a register. */
#define ALT_USB_HOST_HCINT12_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT12_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT12_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT12_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT12_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT12_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_NAK register field value. */
#define ALT_USB_HOST_HCINT12_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT12_NAK register field value. */
#define ALT_USB_HOST_HCINT12_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT12_NAK register field. */
#define ALT_USB_HOST_HCINT12_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_NAK field value from a register. */
#define ALT_USB_HOST_HCINT12_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT12_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT12_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT12_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT12_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT12_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_ACK register field value. */
#define ALT_USB_HOST_HCINT12_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT12_ACK register field value. */
#define ALT_USB_HOST_HCINT12_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT12_ACK register field. */
#define ALT_USB_HOST_HCINT12_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_ACK field value from a register. */
#define ALT_USB_HOST_HCINT12_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT12_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT12_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT12_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT12_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT12_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_NYET register field value. */
#define ALT_USB_HOST_HCINT12_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT12_NYET register field value. */
#define ALT_USB_HOST_HCINT12_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT12_NYET register field. */
#define ALT_USB_HOST_HCINT12_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_NYET field value from a register. */
#define ALT_USB_HOST_HCINT12_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT12_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT12_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT12_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT12_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT12_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_XACTERR register field value. */
#define ALT_USB_HOST_HCINT12_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT12_XACTERR register field value. */
#define ALT_USB_HOST_HCINT12_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT12_XACTERR register field. */
#define ALT_USB_HOST_HCINT12_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT12_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT12_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT12_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT12_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT12_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT12_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_BBLERR register field value. */
#define ALT_USB_HOST_HCINT12_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT12_BBLERR register field value. */
#define ALT_USB_HOST_HCINT12_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT12_BBLERR register field. */
#define ALT_USB_HOST_HCINT12_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT12_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT12_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT12_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT12_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT12_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT12_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT12_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT12_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT12_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT12_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT12_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT12_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT12_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT12_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT12_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT12_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT12_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT12_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT12_BNAINTR register field. */
#define ALT_USB_HOST_HCINT12_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT12_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT12_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT12.
*/
struct ALT_USB_HOST_HCINT12_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT12_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT12_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT12_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT12_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT12_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT12_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT12_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT12_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT12_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT12_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT12_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT12_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT12_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT12_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT12. */
typedef volatile struct ALT_USB_HOST_HCINT12_s ALT_USB_HOST_HCINT12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT12 register. */
#define ALT_USB_HOST_HCINT12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT12 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT12_OFST 0x288
/* The address of the ALT_USB_HOST_HCINT12 register. */
#define ALT_USB_HOST_HCINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT12_OFST))
/*
* Register : hcintmsk12
*
* Host Channel 12 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK12_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK12_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK12_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK12_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK12_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK12_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK12_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK12_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK12_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK12_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK12_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK12_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK12_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK12.
*/
struct ALT_USB_HOST_HCINTMSK12_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK12_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK12_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK12_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK12_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK12_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK12_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK12_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK12_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK12. */
typedef volatile struct ALT_USB_HOST_HCINTMSK12_s ALT_USB_HOST_HCINTMSK12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK12 register. */
#define ALT_USB_HOST_HCINTMSK12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK12 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK12_OFST 0x28c
/* The address of the ALT_USB_HOST_HCINTMSK12 register. */
#define ALT_USB_HOST_HCINTMSK12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK12_OFST))
/*
* Register : hctsiz12
*
* Host Channel 12 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ12_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ12_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ12_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ12_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ12_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_PID register field value. */
#define ALT_USB_HOST_HCTSIZ12_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_PID register field value. */
#define ALT_USB_HOST_HCTSIZ12_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_PID register field. */
#define ALT_USB_HOST_HCTSIZ12_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ12_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ12_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ12_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ12_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ12_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ12_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ12_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ12_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ12.
*/
struct ALT_USB_HOST_HCTSIZ12_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ12_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ12_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ12_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ12_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ12. */
typedef volatile struct ALT_USB_HOST_HCTSIZ12_s ALT_USB_HOST_HCTSIZ12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ12 register. */
#define ALT_USB_HOST_HCTSIZ12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ12 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ12_OFST 0x290
/* The address of the ALT_USB_HOST_HCTSIZ12 register. */
#define ALT_USB_HOST_HCTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ12_OFST))
/*
* Register : hcdma12
*
* Host Channel 12 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA12_HCDMA12
*
*/
/*
* Field : hcdma12
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA12_HCDMA12 register field value. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA12_HCDMA12 register field. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA12_HCDMA12 field value from a register. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA12_HCDMA12 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA12_HCDMA12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA12.
*/
struct ALT_USB_HOST_HCDMA12_s
{
uint32_t hcdma12 : 32; /* ALT_USB_HOST_HCDMA12_HCDMA12 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA12. */
typedef volatile struct ALT_USB_HOST_HCDMA12_s ALT_USB_HOST_HCDMA12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA12 register. */
#define ALT_USB_HOST_HCDMA12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA12 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA12_OFST 0x294
/* The address of the ALT_USB_HOST_HCDMA12 register. */
#define ALT_USB_HOST_HCDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA12_OFST))
/*
* Register : hcdmab12
*
* Host Channel 12 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB12_HCDMAB12
*
*/
/*
* Field : hcdmab12
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB12_HCDMAB12 register field. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB12_HCDMAB12 field value from a register. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB12_HCDMAB12 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB12_HCDMAB12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB12.
*/
struct ALT_USB_HOST_HCDMAB12_s
{
uint32_t hcdmab12 : 32; /* ALT_USB_HOST_HCDMAB12_HCDMAB12 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB12. */
typedef volatile struct ALT_USB_HOST_HCDMAB12_s ALT_USB_HOST_HCDMAB12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB12 register. */
#define ALT_USB_HOST_HCDMAB12_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB12 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB12_OFST 0x29c
/* The address of the ALT_USB_HOST_HCDMAB12 register. */
#define ALT_USB_HOST_HCDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB12_OFST))
/*
* Register : hcchar13
*
* Host Channel 13 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR13_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR13_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR13_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR13_MPS register field value. */
#define ALT_USB_HOST_HCCHAR13_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_MPS register field value. */
#define ALT_USB_HOST_HCCHAR13_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR13_MPS register field. */
#define ALT_USB_HOST_HCCHAR13_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR13_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR13_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR13_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR13_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR13_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR13_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR13_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR13_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR13_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR13_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR13_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR13_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR13_EC register field value. */
#define ALT_USB_HOST_HCCHAR13_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_EC register field value. */
#define ALT_USB_HOST_HCCHAR13_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_EC register field. */
#define ALT_USB_HOST_HCCHAR13_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR13_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR13_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR13_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR13_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR13_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR13_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR13_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR13_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR13_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR13_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR13_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR13_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR13_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR13_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR13_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR13_CHENA register field. */
#define ALT_USB_HOST_HCCHAR13_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR13_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR13_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR13_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR13_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR13.
*/
struct ALT_USB_HOST_HCCHAR13_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR13_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR13_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR13_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR13_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR13_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR13_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR13_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR13_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR13_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR13_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR13. */
typedef volatile struct ALT_USB_HOST_HCCHAR13_s ALT_USB_HOST_HCCHAR13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR13 register. */
#define ALT_USB_HOST_HCCHAR13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR13 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR13_OFST 0x2a0
/* The address of the ALT_USB_HOST_HCCHAR13 register. */
#define ALT_USB_HOST_HCCHAR13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR13_OFST))
/*
* Register : hcsplt13
*
* Host Channel 13 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT13_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT13_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT13_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT13_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT13_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT13_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT13_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT13_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT13_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT13_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT13_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT13_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT13_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT13_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT13_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT13_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT13_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT13_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT13_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT13.
*/
struct ALT_USB_HOST_HCSPLT13_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT13_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT13_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT13_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT13_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT13_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT13. */
typedef volatile struct ALT_USB_HOST_HCSPLT13_s ALT_USB_HOST_HCSPLT13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT13 register. */
#define ALT_USB_HOST_HCSPLT13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT13 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT13_OFST 0x2a4
/* The address of the ALT_USB_HOST_HCSPLT13 register. */
#define ALT_USB_HOST_HCSPLT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT13_OFST))
/*
* Register : hcint13
*
* Host Channel 13 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT13_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT13_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT13_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT13_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT13_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT13_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT13_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT13_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT13_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT13_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT13_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT13_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT13_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT13_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT13_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT13_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT13_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT13_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT13_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT13_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT13_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT13_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT13_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT13_CHHLTD register field. */
#define ALT_USB_HOST_HCINT13_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT13_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT13_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT13_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT13_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT13_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT13_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_AHBERR register field value. */
#define ALT_USB_HOST_HCINT13_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT13_AHBERR register field value. */
#define ALT_USB_HOST_HCINT13_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT13_AHBERR register field. */
#define ALT_USB_HOST_HCINT13_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT13_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT13_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT13_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT13_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_STALL register field value. */
#define ALT_USB_HOST_HCINT13_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT13_STALL register field value. */
#define ALT_USB_HOST_HCINT13_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT13_STALL register field. */
#define ALT_USB_HOST_HCINT13_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_STALL field value from a register. */
#define ALT_USB_HOST_HCINT13_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT13_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT13_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT13_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT13_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT13_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_NAK register field value. */
#define ALT_USB_HOST_HCINT13_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT13_NAK register field value. */
#define ALT_USB_HOST_HCINT13_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT13_NAK register field. */
#define ALT_USB_HOST_HCINT13_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_NAK field value from a register. */
#define ALT_USB_HOST_HCINT13_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT13_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT13_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT13_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT13_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT13_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_ACK register field value. */
#define ALT_USB_HOST_HCINT13_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT13_ACK register field value. */
#define ALT_USB_HOST_HCINT13_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT13_ACK register field. */
#define ALT_USB_HOST_HCINT13_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_ACK field value from a register. */
#define ALT_USB_HOST_HCINT13_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT13_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT13_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT13_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT13_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT13_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_NYET register field value. */
#define ALT_USB_HOST_HCINT13_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT13_NYET register field value. */
#define ALT_USB_HOST_HCINT13_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT13_NYET register field. */
#define ALT_USB_HOST_HCINT13_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_NYET field value from a register. */
#define ALT_USB_HOST_HCINT13_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT13_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT13_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT13_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT13_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT13_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_XACTERR register field value. */
#define ALT_USB_HOST_HCINT13_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT13_XACTERR register field value. */
#define ALT_USB_HOST_HCINT13_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT13_XACTERR register field. */
#define ALT_USB_HOST_HCINT13_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT13_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT13_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT13_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT13_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT13_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT13_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_BBLERR register field value. */
#define ALT_USB_HOST_HCINT13_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT13_BBLERR register field value. */
#define ALT_USB_HOST_HCINT13_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT13_BBLERR register field. */
#define ALT_USB_HOST_HCINT13_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT13_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT13_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT13_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT13_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT13_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT13_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT13_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT13_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT13_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT13_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT13_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT13_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT13_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT13_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT13_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT13_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT13_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT13_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT13_BNAINTR register field. */
#define ALT_USB_HOST_HCINT13_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT13_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT13_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT13.
*/
struct ALT_USB_HOST_HCINT13_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT13_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT13_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT13_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT13_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT13_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT13_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT13_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT13_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT13_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT13_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT13_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT13_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT13_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT13_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT13. */
typedef volatile struct ALT_USB_HOST_HCINT13_s ALT_USB_HOST_HCINT13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT13 register. */
#define ALT_USB_HOST_HCINT13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT13 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT13_OFST 0x2a8
/* The address of the ALT_USB_HOST_HCINT13 register. */
#define ALT_USB_HOST_HCINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT13_OFST))
/*
* Register : hcintmsk13
*
* Host Channel 13 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK13_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK13_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK13_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK13_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK13_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK13_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK13_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK13_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK13_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK13_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK13_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK13_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK13_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK13.
*/
struct ALT_USB_HOST_HCINTMSK13_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK13_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK13_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK13_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK13_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK13_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK13_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK13_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK13_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK13. */
typedef volatile struct ALT_USB_HOST_HCINTMSK13_s ALT_USB_HOST_HCINTMSK13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK13 register. */
#define ALT_USB_HOST_HCINTMSK13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK13 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK13_OFST 0x2ac
/* The address of the ALT_USB_HOST_HCINTMSK13 register. */
#define ALT_USB_HOST_HCINTMSK13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK13_OFST))
/*
* Register : hctsiz13
*
* Host Channel 13 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ13_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ13_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ13_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ13_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ13_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_PID register field value. */
#define ALT_USB_HOST_HCTSIZ13_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_PID register field value. */
#define ALT_USB_HOST_HCTSIZ13_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_PID register field. */
#define ALT_USB_HOST_HCTSIZ13_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ13_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ13_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ13_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ13_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ13_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ13_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ13_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ13_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ13.
*/
struct ALT_USB_HOST_HCTSIZ13_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ13_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ13_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ13_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ13_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ13. */
typedef volatile struct ALT_USB_HOST_HCTSIZ13_s ALT_USB_HOST_HCTSIZ13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ13 register. */
#define ALT_USB_HOST_HCTSIZ13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ13 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ13_OFST 0x2b0
/* The address of the ALT_USB_HOST_HCTSIZ13 register. */
#define ALT_USB_HOST_HCTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ13_OFST))
/*
* Register : hcdma13
*
* Host Channel 13 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA13_HCDMA13
*
*/
/*
* Field : hcdma13
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA13_HCDMA13 register field value. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA13_HCDMA13 register field. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA13_HCDMA13 field value from a register. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA13_HCDMA13 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA13_HCDMA13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA13.
*/
struct ALT_USB_HOST_HCDMA13_s
{
uint32_t hcdma13 : 32; /* ALT_USB_HOST_HCDMA13_HCDMA13 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA13. */
typedef volatile struct ALT_USB_HOST_HCDMA13_s ALT_USB_HOST_HCDMA13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA13 register. */
#define ALT_USB_HOST_HCDMA13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA13 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA13_OFST 0x2b4
/* The address of the ALT_USB_HOST_HCDMA13 register. */
#define ALT_USB_HOST_HCDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA13_OFST))
/*
* Register : hcdmab13
*
* Host Channel 13 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB13_HCDMAB13
*
*/
/*
* Field : hcdmab13
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB13_HCDMAB13 register field. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB13_HCDMAB13 field value from a register. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB13_HCDMAB13 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB13_HCDMAB13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB13.
*/
struct ALT_USB_HOST_HCDMAB13_s
{
uint32_t hcdmab13 : 32; /* ALT_USB_HOST_HCDMAB13_HCDMAB13 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB13. */
typedef volatile struct ALT_USB_HOST_HCDMAB13_s ALT_USB_HOST_HCDMAB13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB13 register. */
#define ALT_USB_HOST_HCDMAB13_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB13 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB13_OFST 0x2bc
/* The address of the ALT_USB_HOST_HCDMAB13 register. */
#define ALT_USB_HOST_HCDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB13_OFST))
/*
* Register : hcchar14
*
* Host Channel 14 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR14_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR14_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR14_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR14_MPS register field value. */
#define ALT_USB_HOST_HCCHAR14_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_MPS register field value. */
#define ALT_USB_HOST_HCCHAR14_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR14_MPS register field. */
#define ALT_USB_HOST_HCCHAR14_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR14_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR14_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR14_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR14_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR14_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR14_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR14_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR14_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR14_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR14_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR14_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR14_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR14_EC register field value. */
#define ALT_USB_HOST_HCCHAR14_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_EC register field value. */
#define ALT_USB_HOST_HCCHAR14_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_EC register field. */
#define ALT_USB_HOST_HCCHAR14_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR14_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR14_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR14_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR14_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR14_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR14_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR14_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR14_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR14_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR14_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR14_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR14_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR14_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR14_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR14_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR14_CHENA register field. */
#define ALT_USB_HOST_HCCHAR14_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR14_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR14_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR14_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR14_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR14.
*/
struct ALT_USB_HOST_HCCHAR14_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR14_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR14_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR14_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR14_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR14_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR14_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR14_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR14_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR14_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR14_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR14. */
typedef volatile struct ALT_USB_HOST_HCCHAR14_s ALT_USB_HOST_HCCHAR14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR14 register. */
#define ALT_USB_HOST_HCCHAR14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR14 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR14_OFST 0x2c0
/* The address of the ALT_USB_HOST_HCCHAR14 register. */
#define ALT_USB_HOST_HCCHAR14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR14_OFST))
/*
* Register : hcsplt14
*
* Host Channel 14 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT14_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT14_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT14_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT14_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT14_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT14_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT14_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT14_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT14_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT14_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT14_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT14_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT14_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT14_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT14_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT14_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT14_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT14_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT14_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT14.
*/
struct ALT_USB_HOST_HCSPLT14_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT14_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT14_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT14_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT14_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT14_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT14. */
typedef volatile struct ALT_USB_HOST_HCSPLT14_s ALT_USB_HOST_HCSPLT14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT14 register. */
#define ALT_USB_HOST_HCSPLT14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT14 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT14_OFST 0x2c4
/* The address of the ALT_USB_HOST_HCSPLT14 register. */
#define ALT_USB_HOST_HCSPLT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT14_OFST))
/*
* Register : hcint14
*
* Host Channel 14 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT14_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT14_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT14_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT14_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT14_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT14_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT14_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT14_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT14_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT14_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT14_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT14_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT14_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT14_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT14_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT14_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT14_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT14_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT14_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT14_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT14_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT14_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT14_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT14_CHHLTD register field. */
#define ALT_USB_HOST_HCINT14_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT14_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT14_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT14_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT14_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT14_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT14_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_AHBERR register field value. */
#define ALT_USB_HOST_HCINT14_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT14_AHBERR register field value. */
#define ALT_USB_HOST_HCINT14_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT14_AHBERR register field. */
#define ALT_USB_HOST_HCINT14_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT14_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT14_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT14_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT14_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_STALL register field value. */
#define ALT_USB_HOST_HCINT14_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT14_STALL register field value. */
#define ALT_USB_HOST_HCINT14_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT14_STALL register field. */
#define ALT_USB_HOST_HCINT14_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_STALL field value from a register. */
#define ALT_USB_HOST_HCINT14_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT14_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT14_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT14_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT14_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT14_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_NAK register field value. */
#define ALT_USB_HOST_HCINT14_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT14_NAK register field value. */
#define ALT_USB_HOST_HCINT14_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT14_NAK register field. */
#define ALT_USB_HOST_HCINT14_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_NAK field value from a register. */
#define ALT_USB_HOST_HCINT14_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT14_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT14_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT14_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT14_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT14_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_ACK register field value. */
#define ALT_USB_HOST_HCINT14_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT14_ACK register field value. */
#define ALT_USB_HOST_HCINT14_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT14_ACK register field. */
#define ALT_USB_HOST_HCINT14_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_ACK field value from a register. */
#define ALT_USB_HOST_HCINT14_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT14_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT14_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT14_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT14_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT14_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_NYET register field value. */
#define ALT_USB_HOST_HCINT14_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT14_NYET register field value. */
#define ALT_USB_HOST_HCINT14_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT14_NYET register field. */
#define ALT_USB_HOST_HCINT14_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_NYET field value from a register. */
#define ALT_USB_HOST_HCINT14_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT14_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT14_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT14_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT14_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT14_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_XACTERR register field value. */
#define ALT_USB_HOST_HCINT14_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT14_XACTERR register field value. */
#define ALT_USB_HOST_HCINT14_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT14_XACTERR register field. */
#define ALT_USB_HOST_HCINT14_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT14_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT14_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT14_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT14_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT14_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT14_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_BBLERR register field value. */
#define ALT_USB_HOST_HCINT14_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT14_BBLERR register field value. */
#define ALT_USB_HOST_HCINT14_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT14_BBLERR register field. */
#define ALT_USB_HOST_HCINT14_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT14_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT14_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT14_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT14_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT14_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT14_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT14_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT14_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT14_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT14_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT14_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT14_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT14_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT14_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT14_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT14_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT14_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT14_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT14_BNAINTR register field. */
#define ALT_USB_HOST_HCINT14_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT14_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT14_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT14.
*/
struct ALT_USB_HOST_HCINT14_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT14_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT14_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT14_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT14_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT14_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT14_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT14_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT14_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT14_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT14_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT14_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT14_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT14_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT14_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT14. */
typedef volatile struct ALT_USB_HOST_HCINT14_s ALT_USB_HOST_HCINT14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT14 register. */
#define ALT_USB_HOST_HCINT14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT14 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT14_OFST 0x2c8
/* The address of the ALT_USB_HOST_HCINT14 register. */
#define ALT_USB_HOST_HCINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT14_OFST))
/*
* Register : hcintmsk14
*
* Host Channel 14 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK14_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK14_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK14_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK14_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK14_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK14_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK14_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK14_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK14_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK14_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK14_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK14_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK14_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK14.
*/
struct ALT_USB_HOST_HCINTMSK14_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK14_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK14_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK14_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK14_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK14_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK14_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK14_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK14_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK14. */
typedef volatile struct ALT_USB_HOST_HCINTMSK14_s ALT_USB_HOST_HCINTMSK14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK14 register. */
#define ALT_USB_HOST_HCINTMSK14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK14 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK14_OFST 0x2cc
/* The address of the ALT_USB_HOST_HCINTMSK14 register. */
#define ALT_USB_HOST_HCINTMSK14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK14_OFST))
/*
* Register : hctsiz14
*
* Host Channel 14 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ14_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ14_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ14_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ14_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ14_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_PID register field value. */
#define ALT_USB_HOST_HCTSIZ14_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_PID register field value. */
#define ALT_USB_HOST_HCTSIZ14_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_PID register field. */
#define ALT_USB_HOST_HCTSIZ14_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ14_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ14_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ14_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ14_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ14_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ14_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ14_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ14_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ14.
*/
struct ALT_USB_HOST_HCTSIZ14_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ14_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ14_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ14_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ14_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ14. */
typedef volatile struct ALT_USB_HOST_HCTSIZ14_s ALT_USB_HOST_HCTSIZ14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ14 register. */
#define ALT_USB_HOST_HCTSIZ14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ14 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ14_OFST 0x2d0
/* The address of the ALT_USB_HOST_HCTSIZ14 register. */
#define ALT_USB_HOST_HCTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ14_OFST))
/*
* Register : hcdma14
*
* Host Channel 14 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA14_HCDMA14
*
*/
/*
* Field : hcdma14
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA14_HCDMA14 register field value. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA14_HCDMA14 register field. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA14_HCDMA14 field value from a register. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA14_HCDMA14 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA14_HCDMA14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA14.
*/
struct ALT_USB_HOST_HCDMA14_s
{
uint32_t hcdma14 : 32; /* ALT_USB_HOST_HCDMA14_HCDMA14 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA14. */
typedef volatile struct ALT_USB_HOST_HCDMA14_s ALT_USB_HOST_HCDMA14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA14 register. */
#define ALT_USB_HOST_HCDMA14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA14 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA14_OFST 0x2d4
/* The address of the ALT_USB_HOST_HCDMA14 register. */
#define ALT_USB_HOST_HCDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA14_OFST))
/*
* Register : hcdmab14
*
* Host Channel 14 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB14_HCDMAB14
*
*/
/*
* Field : hcdmab14
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB14_HCDMAB14 register field. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB14_HCDMAB14 field value from a register. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB14_HCDMAB14 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB14_HCDMAB14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB14.
*/
struct ALT_USB_HOST_HCDMAB14_s
{
uint32_t hcdmab14 : 32; /* ALT_USB_HOST_HCDMAB14_HCDMAB14 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB14. */
typedef volatile struct ALT_USB_HOST_HCDMAB14_s ALT_USB_HOST_HCDMAB14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB14 register. */
#define ALT_USB_HOST_HCDMAB14_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB14 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB14_OFST 0x2dc
/* The address of the ALT_USB_HOST_HCDMAB14 register. */
#define ALT_USB_HOST_HCDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB14_OFST))
/*
* Register : hcchar15
*
* Host Channel 15 Characteristics Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_MPS
* [14:11] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPNUM
* [15] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPDIR
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_LSPDDEV
* [19:18] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EPTYPE
* [21:20] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_EC
* [28:22] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_DEVADDR
* [29] | RW | 0x0 | ALT_USB_HOST_HCCHAR15_ODDFRM
* [30] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR15_CHDIS
* [31] | R-W once | 0x0 | ALT_USB_HOST_HCCHAR15_CHENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Indicates the maximum packet size of the associated endpoint.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_MSB 10
/* The width in bits of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_WIDTH 11
/* The mask used to set the ALT_USB_HOST_HCCHAR15_MPS register field value. */
#define ALT_USB_HOST_HCCHAR15_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_MPS register field value. */
#define ALT_USB_HOST_HCCHAR15_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_HOST_HCCHAR15_MPS register field. */
#define ALT_USB_HOST_HCCHAR15_MPS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_MPS field value from a register. */
#define ALT_USB_HOST_HCCHAR15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_HOST_HCCHAR15_MPS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : epnum
*
* Endpoint Number (EPNum)
*
* Indicates the endpoint number on the device serving as the data
*
* source or sink.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 | 0x0 | End point 0
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 | 0x1 | End point 1
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 | 0x2 | End point 2
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 | 0x3 | End point 3
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 | 0x4 | End point 4
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 | 0x5 | End point 5
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 | 0x6 | End point 6
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 | 0x7 | End point 7
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 | 0x8 | End point 8
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 | 0x9 | End point 9
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 | 0xa | End point 10
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 | 0xb | End point 11
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 | 0xc | End point 12
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 | 0xd | End point 13
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 | 0xe | End point 14
* ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 | 0xf | End point 15
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 0
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 1
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT1 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 2
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT2 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 3
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT3 0x3
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 4
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT4 0x4
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 5
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT5 0x5
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 6
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT6 0x6
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 7
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT7 0x7
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 8
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT8 0x8
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 9
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT9 0x9
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 10
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT10 0xa
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 11
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT11 0xb
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 12
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT12 0xc
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 13
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT13 0xd
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 14
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT14 0xe
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPNUM
*
* End point 15
*/
#define ALT_USB_HOST_HCCHAR15_EPNUM_E_ENDPT15 0xf
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_MSB 14
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_WIDTH 4
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_SET_MSK 0x00007800
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPNUM register field value. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_CLR_MSK 0xffff87ff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPNUM register field. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPNUM field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_GET(value) (((value) & 0x00007800) >> 11)
/* Produces a ALT_USB_HOST_HCCHAR15_EPNUM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPNUM_SET(value) (((value) << 11) & 0x00007800)
/*
* Field : epdir
*
* Endpoint Direction (EPDir)
*
* Indicates whether the transaction is IN or OUT.
*
* 1'b0: OUT
*
* 1'b1: IN
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:--------------
* ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT | 0x0 | OUT Direction
* ALT_USB_HOST_HCCHAR15_EPDIR_E_IN | 0x1 | IN Direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
*
* OUT Direction
*/
#define ALT_USB_HOST_HCCHAR15_EPDIR_E_OUT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPDIR
*
* IN Direction
*/
#define ALT_USB_HOST_HCCHAR15_EPDIR_E_IN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_MSB 15
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPDIR register field value. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPDIR register field. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPDIR field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_HOST_HCCHAR15_EPDIR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPDIR_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : lspddev
*
* Low-Speed Device (LSpdDev)
*
* This field is Set by the application to indicate that this channel is
*
* communicating to a low-speed device.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------------
* ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD | 0x0 | Not Communicating with low speed device
* ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END | 0x1 | Communicating with low speed device
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
*
* Not Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_LSPDDEV
*
* Communicating with low speed device
*/
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_MSB 17
/* The width in bits of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_LSPDDEV register field value. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_LSPDDEV register field. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_LSPDDEV field value from a register. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_HOST_HCCHAR15_LSPDDEV register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_LSPDDEV_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Indicates the transfer type selected.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------
* ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC | 0x1 | Isochronous
* ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
*
* Control
*/
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
*
* Isochronous
*/
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_ISOC 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
*
* Bulk
*/
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EPTYPE
*
* Interrupt
*/
#define ALT_USB_HOST_HCCHAR15_EPTYPE_E_INTERR 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EPTYPE register field value. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EPTYPE register field. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EPTYPE field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_HOST_HCCHAR15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : ec
*
* Multi Count (MC) / Error Count (EC)
*
* When the Split Enable bit of the Host Channel-n Split Control
*
* register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to
*
* the host the number of transactions that must be executed per
*
* microframe For this periodic endpoint. For non periodic transfers,
*
* this field is used only in DMA mode, and specifies the number
*
* packets to be fetched For this channel before the internal DMA
*
* engine changes arbitration.
*
* 2'b00: Reserved This field yields undefined results.
*
* 2'b01: 1 transaction
*
* 2'b10: 2 transactions to be issued For this endpoint per
*
* microframe
*
* 2'b11: 3 transactions to be issued For this endpoint per
*
* microframe
*
* When HCSPLTn.SpltEna is Set (1'b1), this field indicates the
*
* number of immediate retries to be performed For a periodic split
*
* transactions on transaction errors. This field must be Set to at
*
* least 2'b01.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------------------------
* ALT_USB_HOST_HCCHAR15_EC_E_RSVD | 0x0 | Reserved This field yields undefined result
* ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE | 0x1 | 1 transaction
* ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO | 0x2 | 2 transactions to be issued for this endpoint
* : | | per microframe
* ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE | 0x3 | 3 transactions to be issued for this endpoint
* : | | per microframe
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
*
* Reserved This field yields undefined result
*/
#define ALT_USB_HOST_HCCHAR15_EC_E_RSVD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
*
* 1 transaction
*/
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSONE 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
*
* 2 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTWO 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_EC
*
* 3 transactions to be issued for this endpoint per microframe
*/
#define ALT_USB_HOST_HCCHAR15_EC_E_TRANSTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_MSB 21
/* The width in bits of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCCHAR15_EC register field value. */
#define ALT_USB_HOST_HCCHAR15_EC_SET_MSK 0x00300000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_EC register field value. */
#define ALT_USB_HOST_HCCHAR15_EC_CLR_MSK 0xffcfffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_EC register field. */
#define ALT_USB_HOST_HCCHAR15_EC_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_EC field value from a register. */
#define ALT_USB_HOST_HCCHAR15_EC_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_USB_HOST_HCCHAR15_EC register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_EC_SET(value) (((value) << 20) & 0x00300000)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* This field selects the specific device serving as the data source
*
* or sink.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_MSB 28
/* The width in bits of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET_MSK 0x1fc00000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_DEVADDR register field value. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_CLR_MSK 0xe03fffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_DEVADDR register field. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_DEVADDR field value from a register. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_GET(value) (((value) & 0x1fc00000) >> 22)
/* Produces a ALT_USB_HOST_HCCHAR15_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_DEVADDR_SET(value) (((value) << 22) & 0x1fc00000)
/*
* Field : oddfrm
*
* Odd Frame (OddFrm)
*
* This field is set (reset) by the application to indicate that the OTG host must
* perform
*
* a transfer in an odd (micro)frame. This field is applicable for only periodic
*
* (isochronous and interrupt) transactions.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_MSB 29
/* The width in bits of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_ODDFRM register field value. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_ODDFRM register field. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_ODDFRM field value from a register. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_HOST_HCCHAR15_ODDFRM register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_ODDFRM_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : chdis
*
* Channel Disable (ChDis)
*
* The application sets this bit to stop transmitting/receiving data
*
* on a channel, even before the transfer For that channel is
*
* complete. The application must wait For the Channel Disabled
*
* interrupt before treating the channel as disabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT | 0x0 | Transmit/Recieve normal
* ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT | 0x1 | Stop transmitting/receiving
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
*
* Transmit/Recieve normal
*/
#define ALT_USB_HOST_HCCHAR15_CHDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHDIS
*
* Stop transmitting/receiving
*/
#define ALT_USB_HOST_HCCHAR15_CHDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_MSB 30
/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHDIS register field value. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_CHDIS register field. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_CHDIS field value from a register. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_HOST_HCCHAR15_CHDIS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_CHDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : chena
*
* Channel Enable (ChEna)
*
* When Scatter/Gather mode is enabled
*
* 1'b0: Indicates that the descriptor structure is not yet ready.
*
* 1'b1: Indicates that the descriptor structure and data buffer with
*
* data is setup and this channel can access the descriptor.
*
* When Scatter/Gather mode is disabled
*
* This field is set by the application and cleared by the OTG host.
*
* 1'b0: Channel disabled
*
* 1'b1: Channel enabled
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_HOST_HCCHAR15_CHENA_E_INACT | 0x0 | Indicates that the descriptor structure is not
* : | | yet ready
* ALT_USB_HOST_HCCHAR15_CHENA_E_ACT | 0x1 | Indicates that the descriptor structure and
* : | | data buffer with data is setup and this
* : | | channel can access the descriptor
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
*
* Indicates that the descriptor structure is not yet ready
*/
#define ALT_USB_HOST_HCCHAR15_CHENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCCHAR15_CHENA
*
* Indicates that the descriptor structure and data buffer with data is
* setup and this channel can access the descriptor
*/
#define ALT_USB_HOST_HCCHAR15_CHENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR15_CHENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCCHAR15_CHENA register field value. */
#define ALT_USB_HOST_HCCHAR15_CHENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCCHAR15_CHENA register field. */
#define ALT_USB_HOST_HCCHAR15_CHENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCCHAR15_CHENA field value from a register. */
#define ALT_USB_HOST_HCCHAR15_CHENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCCHAR15_CHENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCCHAR15_CHENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCCHAR15.
*/
struct ALT_USB_HOST_HCCHAR15_s
{
uint32_t mps : 11; /* ALT_USB_HOST_HCCHAR15_MPS */
uint32_t epnum : 4; /* ALT_USB_HOST_HCCHAR15_EPNUM */
uint32_t epdir : 1; /* ALT_USB_HOST_HCCHAR15_EPDIR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t lspddev : 1; /* ALT_USB_HOST_HCCHAR15_LSPDDEV */
uint32_t eptype : 2; /* ALT_USB_HOST_HCCHAR15_EPTYPE */
uint32_t ec : 2; /* ALT_USB_HOST_HCCHAR15_EC */
uint32_t devaddr : 7; /* ALT_USB_HOST_HCCHAR15_DEVADDR */
uint32_t oddfrm : 1; /* ALT_USB_HOST_HCCHAR15_ODDFRM */
uint32_t chdis : 1; /* ALT_USB_HOST_HCCHAR15_CHDIS */
uint32_t chena : 1; /* ALT_USB_HOST_HCCHAR15_CHENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCCHAR15. */
typedef volatile struct ALT_USB_HOST_HCCHAR15_s ALT_USB_HOST_HCCHAR15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCCHAR15 register. */
#define ALT_USB_HOST_HCCHAR15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCCHAR15 register from the beginning of the component. */
#define ALT_USB_HOST_HCCHAR15_OFST 0x2e0
/* The address of the ALT_USB_HOST_HCCHAR15 register. */
#define ALT_USB_HOST_HCCHAR15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCCHAR15_OFST))
/*
* Register : hcsplt15
*
* Host Channel 15 Split Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_PRTADDR
* [13:7] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_HUBADDR
* [15:14] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_XACTPOS
* [16] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_COMPSPLT
* [30:17] | ??? | 0x0 | *UNDEFINED*
* [31] | RW | 0x0 | ALT_USB_HOST_HCSPLT15_SPLTENA
*
*/
/*
* Field : prtaddr
*
* Port Address (PrtAddr)
*
* This field is the port number of the recipient transaction
*
* translator.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_MSB 6
/* The width in bits of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_PRTADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_HOST_HCSPLT15_PRTADDR register field. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_PRTADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_HOST_HCSPLT15_PRTADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_PRTADDR_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : hubaddr
*
* Hub Address (HubAddr)
*
* This field holds the device address of the transaction translator's
*
* hub.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_WIDTH 7
/* The mask used to set the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET_MSK 0x00003f80
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_HUBADDR register field value. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_CLR_MSK 0xffffc07f
/* The reset value of the ALT_USB_HOST_HCSPLT15_HUBADDR register field. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_HUBADDR field value from a register. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_GET(value) (((value) & 0x00003f80) >> 7)
/* Produces a ALT_USB_HOST_HCSPLT15_HUBADDR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_HUBADDR_SET(value) (((value) << 7) & 0x00003f80)
/*
* Field : xactpos
*
* Transaction Position (XactPos)
*
* This field is used to determine whether to send all, first, middle,
*
* or last payloads with each OUT transaction.
*
* 2'b11: All. This is the entire data payload is of this transaction
*
* (which is less than or equal to 188 bytes).
*
* 2'b10: Begin. This is the first data payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b00: Mid. This is the middle payload of this transaction
*
* (which is larger than 188 bytes).
*
* 2'b01: End. This is the last payload of this transaction (which
*
* is larger than 188 bytes).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------------------------
* ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE | 0x0 | Mid. This is the middle payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT15_XACTPOS_E_END | 0x1 | End. This is the last payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN | 0x2 | Begin. This is the first data payload of this
* : | | transaction (which is larger than 188 bytes)
* ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL | 0x3 | All. This is the entire data payload is of this
* : | | transaction (which is less than or equal to 188
* : | | bytes)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
*
* Mid. This is the middle payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_MIDDLE 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
*
* End. This is the last payload of this transaction (which is larger than 188
* bytes)
*/
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_END 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
*
* Begin. This is the first data payload of this transaction (which is larger than
* 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_BEGIN 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_XACTPOS
*
* All. This is the entire data payload is of this transaction (which is less than
* or equal to 188 bytes)
*/
#define ALT_USB_HOST_HCSPLT15_XACTPOS_E_ALL 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_MSB 15
/* The width in bits of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET_MSK 0x0000c000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_XACTPOS register field value. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_CLR_MSK 0xffff3fff
/* The reset value of the ALT_USB_HOST_HCSPLT15_XACTPOS register field. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_XACTPOS field value from a register. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_GET(value) (((value) & 0x0000c000) >> 14)
/* Produces a ALT_USB_HOST_HCSPLT15_XACTPOS register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_XACTPOS_SET(value) (((value) << 14) & 0x0000c000)
/*
* Field : compsplt
*
* Do Complete Split (CompSplt)
*
* The application sets this field to request the OTG host to perform
*
* a complete split transaction.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT | 0x0 | No split transaction
* ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT | 0x1 | Split transaction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
*
* No split transaction
*/
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_NOSPLIT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_COMPSPLT
*
* Split transaction
*/
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_E_SPLIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_MSB 16
/* The width in bits of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_COMPSPLT register field value. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_HOST_HCSPLT15_COMPSPLT register field. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_COMPSPLT field value from a register. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_HOST_HCSPLT15_COMPSPLT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_COMPSPLT_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : spltena
*
* Split Enable (SpltEna)
*
* The application sets this field to indicate that this channel is
*
* enabled to perform split transactions.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD | 0x0 | Split not enabled
* ALT_USB_HOST_HCSPLT15_SPLTENA_E_END | 0x1 | Split enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
*
* Split not enabled
*/
#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCSPLT15_SPLTENA
*
* Split enabled
*/
#define ALT_USB_HOST_HCSPLT15_SPLTENA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_MSB 31
/* The width in bits of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCSPLT15_SPLTENA register field value. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCSPLT15_SPLTENA register field. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_RESET 0x0
/* Extracts the ALT_USB_HOST_HCSPLT15_SPLTENA field value from a register. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCSPLT15_SPLTENA register field value suitable for setting the register. */
#define ALT_USB_HOST_HCSPLT15_SPLTENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCSPLT15.
*/
struct ALT_USB_HOST_HCSPLT15_s
{
uint32_t prtaddr : 7; /* ALT_USB_HOST_HCSPLT15_PRTADDR */
uint32_t hubaddr : 7; /* ALT_USB_HOST_HCSPLT15_HUBADDR */
uint32_t xactpos : 2; /* ALT_USB_HOST_HCSPLT15_XACTPOS */
uint32_t compsplt : 1; /* ALT_USB_HOST_HCSPLT15_COMPSPLT */
uint32_t : 14; /* *UNDEFINED* */
uint32_t spltena : 1; /* ALT_USB_HOST_HCSPLT15_SPLTENA */
};
/* The typedef declaration for register ALT_USB_HOST_HCSPLT15. */
typedef volatile struct ALT_USB_HOST_HCSPLT15_s ALT_USB_HOST_HCSPLT15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCSPLT15 register. */
#define ALT_USB_HOST_HCSPLT15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCSPLT15 register from the beginning of the component. */
#define ALT_USB_HOST_HCSPLT15_OFST 0x2e4
/* The address of the ALT_USB_HOST_HCSPLT15 register. */
#define ALT_USB_HOST_HCSPLT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCSPLT15_OFST))
/*
* Register : hcint15
*
* Host Channel 15 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINT15_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_HOST_HCINT15_CHHLTD
* [2] | RW | 0x0 | ALT_USB_HOST_HCINT15_AHBERR
* [3] | RW | 0x0 | ALT_USB_HOST_HCINT15_STALL
* [4] | RW | 0x0 | ALT_USB_HOST_HCINT15_NAK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINT15_ACK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINT15_NYET
* [7] | RW | 0x0 | ALT_USB_HOST_HCINT15_XACTERR
* [8] | RW | 0x0 | ALT_USB_HOST_HCINT15_BBLERR
* [9] | RW | 0x0 | ALT_USB_HOST_HCINT15_FRMOVRUN
* [10] | RW | 0x0 | ALT_USB_HOST_HCINT15_DATATGLERR
* [11] | RW | 0x0 | ALT_USB_HOST_HCINT15_BNAINTR
* [12] | RW | 0x0 | ALT_USB_HOST_HCINT15_XCS_XACT_ERR
* [13] | RW | 0x0 | ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed (XferCompl)
*
* Transfer completed normally without any errors.This bit can be set only by the
* core and the application should write 1 to clear it.
*
* For Scatter/Gather DMA mode, it indicates that current descriptor processing got
*
* completed with IOC bit set in its descriptor.
*
* In non Scatter/Gather DMA mode, it indicates that Transfer completed normally
* without
*
* any errors.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT | 0x0 | No transfer
* ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT | 0x1 | Transfer completed normally without any errors
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
*
* No transfer
*/
#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XFERCOMPL
*
* Transfer completed normally without any errors
*/
#define ALT_USB_HOST_HCINT15_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINT15_XFERCOMPL register field value. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINT15_XFERCOMPL register field. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_XFERCOMPL field value from a register. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltd
*
* Channel Halted (ChHltd)
*
* In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally
* either because of any USB transaction error or in response to disable request by
* the application or because of a completed transfer.
*
* in Scatter/gather DMA mode, this indicates that transfer completed due to any of
* the following
*
* . EOL being set in descriptor
*
* . AHB error
*
* . Excessive transaction errors
*
* . Babble
*
* . Stall
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT15_CHHLTD_E_INACT | 0x0 | Channel not halted
* ALT_USB_HOST_HCINT15_CHHLTD_E_ACT | 0x1 | Channel Halted
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
*
* Channel not halted
*/
#define ALT_USB_HOST_HCINT15_CHHLTD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_CHHLTD
*
* Channel Halted
*/
#define ALT_USB_HOST_HCINT15_CHHLTD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT15_CHHLTD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINT15_CHHLTD register field value. */
#define ALT_USB_HOST_HCINT15_CHHLTD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINT15_CHHLTD register field. */
#define ALT_USB_HOST_HCINT15_CHHLTD_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_CHHLTD field value from a register. */
#define ALT_USB_HOST_HCINT15_CHHLTD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINT15_CHHLTD register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_CHHLTD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during AHB read/write. The application can read the
*
* corresponding channel's DMA address register to get the error
*
* address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------
* ALT_USB_HOST_HCINT15_AHBERR_E_INACT | 0x0 | No AHB error
* ALT_USB_HOST_HCINT15_AHBERR_E_ACT | 0x1 | AHB error during AHB read/write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
*
* No AHB error
*/
#define ALT_USB_HOST_HCINT15_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_AHBERR
*
* AHB error during AHB read/write
*/
#define ALT_USB_HOST_HCINT15_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_AHBERR register field value. */
#define ALT_USB_HOST_HCINT15_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINT15_AHBERR register field value. */
#define ALT_USB_HOST_HCINT15_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINT15_AHBERR register field. */
#define ALT_USB_HOST_HCINT15_AHBERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_AHBERR field value from a register. */
#define ALT_USB_HOST_HCINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stall
*
* STALL Response Received Interrupt (STALL)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------
* ALT_USB_HOST_HCINT15_STALL_E_INACT | 0x0 | No Stall Interrupt
* ALT_USB_HOST_HCINT15_STALL_E_ACT | 0x1 | Stall Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
*
* No Stall Interrupt
*/
#define ALT_USB_HOST_HCINT15_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_STALL
*
* Stall Interrupt
*/
#define ALT_USB_HOST_HCINT15_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_STALL register field value. */
#define ALT_USB_HOST_HCINT15_STALL_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINT15_STALL register field value. */
#define ALT_USB_HOST_HCINT15_STALL_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINT15_STALL register field. */
#define ALT_USB_HOST_HCINT15_STALL_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_STALL field value from a register. */
#define ALT_USB_HOST_HCINT15_STALL_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINT15_STALL register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_STALL_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nak
*
* NAK Response Received Interrupt (NAK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_HOST_HCINT15_NAK_E_INACT | 0x0 | No NAK Response Received Interrupt
* ALT_USB_HOST_HCINT15_NAK_E_ACT | 0x1 | NAK Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
*
* No NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT15_NAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_NAK
*
* NAK Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT15_NAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_NAK register field value. */
#define ALT_USB_HOST_HCINT15_NAK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINT15_NAK register field value. */
#define ALT_USB_HOST_HCINT15_NAK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINT15_NAK register field. */
#define ALT_USB_HOST_HCINT15_NAK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_NAK field value from a register. */
#define ALT_USB_HOST_HCINT15_NAK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINT15_NAK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_NAK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ack
*
* ACK Response Received/Transmitted Interrupt (ACK)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------------------
* ALT_USB_HOST_HCINT15_ACK_E_INACT | 0x0 | No ACK Response Received Transmitted Interrupt
* ALT_USB_HOST_HCINT15_ACK_E_ACT | 0x1 | ACK Response Received Transmitted Interrup
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
*
* No ACK Response Received Transmitted Interrupt
*/
#define ALT_USB_HOST_HCINT15_ACK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_ACK
*
* ACK Response Received Transmitted Interrup
*/
#define ALT_USB_HOST_HCINT15_ACK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_ACK register field value. */
#define ALT_USB_HOST_HCINT15_ACK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINT15_ACK register field value. */
#define ALT_USB_HOST_HCINT15_ACK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINT15_ACK register field. */
#define ALT_USB_HOST_HCINT15_ACK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_ACK field value from a register. */
#define ALT_USB_HOST_HCINT15_ACK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINT15_ACK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_ACK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyet
*
* NYET Response Received Interrupt (NYET)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCINT15_NYET_E_INACT | 0x0 | No NYET Response Received Interrupt
* ALT_USB_HOST_HCINT15_NYET_E_ACT | 0x1 | NYET Response Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
*
* No NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT15_NYET_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_NYET
*
* NYET Response Received Interrupt
*/
#define ALT_USB_HOST_HCINT15_NYET_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_NYET register field value. */
#define ALT_USB_HOST_HCINT15_NYET_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINT15_NYET register field value. */
#define ALT_USB_HOST_HCINT15_NYET_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINT15_NYET register field. */
#define ALT_USB_HOST_HCINT15_NYET_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_NYET field value from a register. */
#define ALT_USB_HOST_HCINT15_NYET_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINT15_NYET register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_NYET_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterr
*
* Transaction Error (XactErr)
*
* Indicates one of the following errors occurred on the USB.
*
* CRC check failure
*
* Timeout
*
* Bit stuff error
*
* False EOP
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT15_XACTERR_E_INACT | 0x0 | No Transaction Error
* ALT_USB_HOST_HCINT15_XACTERR_E_ACT | 0x1 | Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
*
* No Transaction Error
*/
#define ALT_USB_HOST_HCINT15_XACTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XACTERR
*
* Transaction Error
*/
#define ALT_USB_HOST_HCINT15_XACTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_XACTERR register field value. */
#define ALT_USB_HOST_HCINT15_XACTERR_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINT15_XACTERR register field value. */
#define ALT_USB_HOST_HCINT15_XACTERR_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINT15_XACTERR register field. */
#define ALT_USB_HOST_HCINT15_XACTERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_XACTERR field value from a register. */
#define ALT_USB_HOST_HCINT15_XACTERR_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINT15_XACTERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XACTERR_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerr
*
* Babble Error (BblErr)
*
* In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core..This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------
* ALT_USB_HOST_HCINT15_BBLERR_E_INACT | 0x0 | No Babble Error
* ALT_USB_HOST_HCINT15_BBLERR_E_ACT | 0x1 | Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
*
* No Babble Error
*/
#define ALT_USB_HOST_HCINT15_BBLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_BBLERR
*
* Babble Error
*/
#define ALT_USB_HOST_HCINT15_BBLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_BBLERR register field value. */
#define ALT_USB_HOST_HCINT15_BBLERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINT15_BBLERR register field value. */
#define ALT_USB_HOST_HCINT15_BBLERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINT15_BBLERR register field. */
#define ALT_USB_HOST_HCINT15_BBLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_BBLERR field value from a register. */
#define ALT_USB_HOST_HCINT15_BBLERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINT15_BBLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_BBLERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrun
*
* Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode, the interrupt due to this
* bit is masked
*
* in the core.This bit can be set only by the core and the application should
* write 1 to clear
*
* it.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT | 0x0 | No Frame Overrun
* ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT | 0x1 | Frame Overrun
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
*
* No Frame Overrun
*/
#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_FRMOVRUN
*
* Frame Overrun
*/
#define ALT_USB_HOST_HCINT15_FRMOVRUN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINT15_FRMOVRUN register field value. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINT15_FRMOVRUN register field. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_FRMOVRUN field value from a register. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINT15_FRMOVRUN register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_FRMOVRUN_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerr
*
* Data Toggle Error (DataTglErr).This bit can be set only by the core and the
* application should write 1 to clear
*
* it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked
*
* in the core.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------
* ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT | 0x0 | No Data Toggle Error
* ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT | 0x1 | Data Toggle Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
*
* No Data Toggle Error
*/
#define ALT_USB_HOST_HCINT15_DATATGLERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_DATATGLERR
*
* Data Toggle Error
*/
#define ALT_USB_HOST_HCINT15_DATATGLERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINT15_DATATGLERR register field value. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINT15_DATATGLERR register field. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_DATATGLERR field value from a register. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINT15_DATATGLERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_DATATGLERR_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready for the Core to process. BNA will not be generated
*
* for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCINT15_BNAINTR_E_INACT | 0x0 | No BNA Interrupt
* ALT_USB_HOST_HCINT15_BNAINTR_E_ACT | 0x1 | BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
*
* No BNA Interrupt
*/
#define ALT_USB_HOST_HCINT15_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_BNAINTR
*
* BNA Interrupt
*/
#define ALT_USB_HOST_HCINT15_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT15_BNAINTR_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINT15_BNAINTR register field value. */
#define ALT_USB_HOST_HCINT15_BNAINTR_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINT15_BNAINTR register field. */
#define ALT_USB_HOST_HCINT15_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_BNAINTR field value from a register. */
#define ALT_USB_HOST_HCINT15_BNAINTR_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_BNAINTR_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : xcs_xact_err
*
* Excessive Transaction Error (XCS_XACT_ERR)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will
*
* not be generated for Isochronous channels.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:-------------------------------
* ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT | 0x0 | No Excessive Transaction Error
* ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE | 0x1 | Excessive Transaction Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
*
* No Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_XCS_XACT_ERR
*
* Excessive Transaction Error
*/
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_E_ACVTIVE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_MSB 12
/* The width in bits of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_XCS_XACT_ERR field value from a register. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_HOST_HCINT15_XCS_XACT_ERR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_XCS_XACT_ERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : desc_lst_rollintr
*
* Descriptor rollover interrupt (DESC_LST_ROLLIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets
* this bit
*
* when the corresponding channel's descriptor list rolls over.
*
* For non Scatter/Gather DMA mode, this bit is reserved.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:---------------------------------
* ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT | 0x0 | No Descriptor rollover interrupt
* ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT | 0x1 | Descriptor rollover interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
*
* No Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR
*
* Descriptor rollover interrupt
*/
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR field value from a register. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINT15.
*/
struct ALT_USB_HOST_HCINT15_s
{
uint32_t xfercompl : 1; /* ALT_USB_HOST_HCINT15_XFERCOMPL */
uint32_t chhltd : 1; /* ALT_USB_HOST_HCINT15_CHHLTD */
uint32_t ahberr : 1; /* ALT_USB_HOST_HCINT15_AHBERR */
uint32_t stall : 1; /* ALT_USB_HOST_HCINT15_STALL */
uint32_t nak : 1; /* ALT_USB_HOST_HCINT15_NAK */
uint32_t ack : 1; /* ALT_USB_HOST_HCINT15_ACK */
uint32_t nyet : 1; /* ALT_USB_HOST_HCINT15_NYET */
uint32_t xacterr : 1; /* ALT_USB_HOST_HCINT15_XACTERR */
uint32_t bblerr : 1; /* ALT_USB_HOST_HCINT15_BBLERR */
uint32_t frmovrun : 1; /* ALT_USB_HOST_HCINT15_FRMOVRUN */
uint32_t datatglerr : 1; /* ALT_USB_HOST_HCINT15_DATATGLERR */
uint32_t bnaintr : 1; /* ALT_USB_HOST_HCINT15_BNAINTR */
uint32_t xcs_xact_err : 1; /* ALT_USB_HOST_HCINT15_XCS_XACT_ERR */
uint32_t desc_lst_rollintr : 1; /* ALT_USB_HOST_HCINT15_DESC_LST_ROLLINTR */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINT15. */
typedef volatile struct ALT_USB_HOST_HCINT15_s ALT_USB_HOST_HCINT15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINT15 register. */
#define ALT_USB_HOST_HCINT15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINT15 register from the beginning of the component. */
#define ALT_USB_HOST_HCINT15_OFST 0x2e8
/* The address of the ALT_USB_HOST_HCINT15 register. */
#define ALT_USB_HOST_HCINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINT15_OFST))
/*
* Register : hcintmsk15
*
* Host Channel 15 Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------------------
* [0] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
* [2] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_STALLMSK
* [4] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_NAKMSK
* [5] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_ACKMSK
* [6] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_NYETMSK
* [7] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_XACTERRMSK
* [8] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_BBLERRMSK
* [9] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK
* [10] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK
* [11] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
* [12] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : chhltdmsk
*
* Channel Halted Mask (ChHltdMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_CHHLTDMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_MSB 1
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_CHHLTDMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_HOST_HCINTMSK15_CHHLTDMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_CHHLTDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_AHBERRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_AHBERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_HOST_HCINTMSK15_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : stallmsk
*
* STALL Response Received Interrupt Mask (StallMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_MSB 3
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_STALLMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_HOST_HCINTMSK15_STALLMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_STALLMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_HOST_HCINTMSK15_STALLMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_STALLMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : nakmsk
*
* NAK Response Received Interrupt Mask (NakMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_MSB 4
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_NAKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_HOST_HCINTMSK15_NAKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_NAKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_HOST_HCINTMSK15_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_NAKMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : ackmsk
*
* ACK Response Received/Transmitted Interrupt Mask (AckMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_MSB 5
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_ACKMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_HOST_HCINTMSK15_ACKMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_ACKMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_HOST_HCINTMSK15_ACKMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_ACKMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : nyetmsk
*
* NYET Response Received Interrupt Mask (NyetMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_MSB 6
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_NYETMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_HOST_HCINTMSK15_NYETMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_NYETMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_HOST_HCINTMSK15_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_NYETMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : xacterrmsk
*
* Transaction Error Mask (XactErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_MSB 7
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_XACTERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_HOST_HCINTMSK15_XACTERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_XACTERRMSK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : bblerrmsk
*
* Babble Error Mask (BblErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_MSB 8
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_BBLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_HOST_HCINTMSK15_BBLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_BBLERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : frmovrunmsk
*
* Frame Overrun Mask (FrmOvrunMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_MSB 9
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : datatglerrmsk
*
* Data Toggle Error Mask (DataTglErrMsk)
*
* In scatter/gather DMA mode for host,
*
* interrupts will not be generated due to the corresponding bits set in
*
* HCINTn.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_MSB 10
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : bnaintrmsk
*
* BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_BNAINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_MSB 11
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_BNAINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_HOST_HCINTMSK15_BNAINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_BNAINTRMSK_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : frm_lst_rollintrmsk
*
* Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------------|:------|:------------
* ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK | 0x0 | Mask
* ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
*
* Mask
*/
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK
*
* No mask
*/
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_MSB 13
/* The width in bits of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_RESET 0x0
/* Extracts the ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK field value from a register. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK register field value suitable for setting the register. */
#define ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCINTMSK15.
*/
struct ALT_USB_HOST_HCINTMSK15_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_HOST_HCINTMSK15_XFERCOMPLMSK */
uint32_t chhltdmsk : 1; /* ALT_USB_HOST_HCINTMSK15_CHHLTDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_AHBERRMSK */
uint32_t stallmsk : 1; /* ALT_USB_HOST_HCINTMSK15_STALLMSK */
uint32_t nakmsk : 1; /* ALT_USB_HOST_HCINTMSK15_NAKMSK */
uint32_t ackmsk : 1; /* ALT_USB_HOST_HCINTMSK15_ACKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_HOST_HCINTMSK15_NYETMSK */
uint32_t xacterrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_XACTERRMSK */
uint32_t bblerrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_BBLERRMSK */
uint32_t frmovrunmsk : 1; /* ALT_USB_HOST_HCINTMSK15_FRMOVRUNMSK */
uint32_t datatglerrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_DATATGLERRMSK */
uint32_t bnaintrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_BNAINTRMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t frm_lst_rollintrmsk : 1; /* ALT_USB_HOST_HCINTMSK15_FRM_LST_ROLLINTRMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_HOST_HCINTMSK15. */
typedef volatile struct ALT_USB_HOST_HCINTMSK15_s ALT_USB_HOST_HCINTMSK15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCINTMSK15 register. */
#define ALT_USB_HOST_HCINTMSK15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCINTMSK15 register from the beginning of the component. */
#define ALT_USB_HOST_HCINTMSK15_OFST 0x2ec
/* The address of the ALT_USB_HOST_HCINTMSK15 register. */
#define ALT_USB_HOST_HCINTMSK15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCINTMSK15_OFST))
/*
* Register : hctsiz15
*
* Host Channel 15 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_PID
* [31] | RW | 0x0 | ALT_USB_HOST_HCTSIZ15_DOPNG
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* For an OUT, this field is the number of data bytes the host sends
*
* during the transfer.
*
* For an IN, this field is the buffer size that the application has
*
* Reserved For the transfer. The application is expected to
*
* program this field as an integer multiple of the maximum packet
*
* size For IN transactions (periodic and non-periodic).
*
* The width of this counter is specified as Width of Transfer Size
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_HOST_HCTSIZ15_XFERSIZE register field. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_HOST_HCTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is programmed by the application with the expected
*
* number of packets to be transmitted (OUT) or received (IN).
*
* The host decrements this count on every successful
*
* transmission or reception of an OUT/IN packet. Once this count
*
* reaches zero, the application is interrupted to indicate normal
*
* completion.
*
* The width of this counter is specified as Width of Packet
*
* Counters
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PKTCNT register field value. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_PKTCNT register field. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_HOST_HCTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : pid
*
* PID (Pid)
*
* The application programs this field with the type of PID to use For
*
* the initial transaction. The host maintains this field For the rest of
*
* the transfer.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA (non-control)/SETUP (control)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------------------------
* ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 | 0x0 | DATA0
* ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 | 0x1 | DATA2
* ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 | 0x2 | DATA1
* ALT_USB_HOST_HCTSIZ15_PID_E_MDATA | 0x3 | MDATA (non-control)/SETUP (control)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
*
* DATA0
*/
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
*
* DATA2
*/
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA2 0x1
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
*
* DATA1
*/
#define ALT_USB_HOST_HCTSIZ15_PID_E_DATA1 0x2
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_PID
*
* MDATA (non-control)/SETUP (control)
*/
#define ALT_USB_HOST_HCTSIZ15_PID_E_MDATA 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_MSB 30
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_WIDTH 2
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_PID register field value. */
#define ALT_USB_HOST_HCTSIZ15_PID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_PID register field value. */
#define ALT_USB_HOST_HCTSIZ15_PID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_PID register field. */
#define ALT_USB_HOST_HCTSIZ15_PID_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_PID field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_PID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_HOST_HCTSIZ15_PID register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_PID_SET(value) (((value) << 29) & 0x60000000)
/*
* Field : dopng
*
* Do Ping (DoPng)
*
* This bit is used only For OUT transfers.
*
* Setting this field to 1 directs the host to do PING protocol.
*
* Note: Do not Set this bit For IN transfers. If this bit is Set For
*
* for IN transfers it disables the channel.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------
* ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING | 0x0 | No ping protocol
* ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING | 0x1 | Ping protocol
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
*
* No ping protocol
*/
#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_NOPING 0x0
/*
* Enumerated value for register field ALT_USB_HOST_HCTSIZ15_DOPNG
*
* Ping protocol
*/
#define ALT_USB_HOST_HCTSIZ15_DOPNG_E_PING 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_MSB 31
/* The width in bits of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_WIDTH 1
/* The mask used to set the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_HOST_HCTSIZ15_DOPNG register field value. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_HOST_HCTSIZ15_DOPNG register field. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_RESET 0x0
/* Extracts the ALT_USB_HOST_HCTSIZ15_DOPNG field value from a register. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_HOST_HCTSIZ15_DOPNG register field value suitable for setting the register. */
#define ALT_USB_HOST_HCTSIZ15_DOPNG_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCTSIZ15.
*/
struct ALT_USB_HOST_HCTSIZ15_s
{
uint32_t xfersize : 19; /* ALT_USB_HOST_HCTSIZ15_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_HOST_HCTSIZ15_PKTCNT */
uint32_t pid : 2; /* ALT_USB_HOST_HCTSIZ15_PID */
uint32_t dopng : 1; /* ALT_USB_HOST_HCTSIZ15_DOPNG */
};
/* The typedef declaration for register ALT_USB_HOST_HCTSIZ15. */
typedef volatile struct ALT_USB_HOST_HCTSIZ15_s ALT_USB_HOST_HCTSIZ15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCTSIZ15 register. */
#define ALT_USB_HOST_HCTSIZ15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCTSIZ15 register from the beginning of the component. */
#define ALT_USB_HOST_HCTSIZ15_OFST 0x2f0
/* The address of the ALT_USB_HOST_HCTSIZ15 register. */
#define ALT_USB_HOST_HCTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCTSIZ15_OFST))
/*
* Register : hcdma15
*
* Host Channel 15 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-----------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMA15_HCDMA15
*
*/
/*
* Field : hcdma15
*
* Buffer DMA Mode:
*
* [31:0] DMA Address (DMAAddr)
*
* This field holds the start address in the external memory from which the data
* for
*
* the endpoint must be fetched or to which it must be stored. This register is
*
* incremented on every AHB transaction.
*
* Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.Scatter-Gather DMA (DescDMA) Mode:
*
* [31:9] (Non Isoc) Non-Isochronous:
*
* [31:N] (Isoc) Isochronous:
*
* This field holds the start address of the 512 bytes
*
* page. The first descriptor in the list should be located
*
* in this address. The first descriptor may be or may
*
* not be ready. The core starts processing the list from
*
* the CTD value.
*
* This field holds the address of the 2*(nTD+1) bytes of
*
* locations in which the isochronous descriptors are
*
* present where N is based on nTD as per Table below
*
* [31:N] Base Address
*
* [N-1:3] Offset
*
* [2:0] 000
*
* HS ISOC
*
* nTD N
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* 127 10
*
* 255 11
*
* FS ISOC
*
* nTD N
*
* 1 4
*
* 3 5
*
* 7 6
*
* 15 7
*
* 31 8
*
* 63 9
*
* [N-1:3] (Isoc):
*
* [8:3] (Non Isoc): Current Transfer Desc(CTD):
*
* Non Isochronous:
*
* This value is in terms of number of descriptors. The values can be from 0 to 63.
*
* 0 - 1 descriptor.
*
* 63 - 64 descriptors.
*
* This field indicates the current descriptor processed in the list. This field is
* updated
*
* both by application and the core. For example, if the application enables the
*
* channel after programming CTD=5, then the core will start processing the 6th
*
* descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal)
*
* to DMAAddr.
*
* Isochronous:
*
* CTD for isochronous is based on the current frame/(micro)frame value. Need to be
* set
*
* to zero by application.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMA15_HCDMA15 register field value. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMA15_HCDMA15 register field. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMA15_HCDMA15 field value from a register. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMA15_HCDMA15 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMA15_HCDMA15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMA15.
*/
struct ALT_USB_HOST_HCDMA15_s
{
uint32_t hcdma15 : 32; /* ALT_USB_HOST_HCDMA15_HCDMA15 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMA15. */
typedef volatile struct ALT_USB_HOST_HCDMA15_s ALT_USB_HOST_HCDMA15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMA15 register. */
#define ALT_USB_HOST_HCDMA15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMA15 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMA15_OFST 0x2f4
/* The address of the ALT_USB_HOST_HCDMA15 register. */
#define ALT_USB_HOST_HCDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMA15_OFST))
/*
* Register : hcdmab15
*
* Host Channel 15 DMA Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------
* [31:0] | RW | 0x0 | ALT_USB_HOST_HCDMAB15_HCDMAB15
*
*/
/*
* Field : hcdmab15
*
* Holds the current buffer address.
*
* This register is updated as and when the data transfer for the corresponding end
* point
*
* is in progress. This register is present only in Scatter/Gather DMA mode.
* Otherwise this
*
* field is reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_MSB 31
/* The width in bits of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_WIDTH 32
/* The mask used to set the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_HOST_HCDMAB15_HCDMAB15 register field. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_RESET 0x0
/* Extracts the ALT_USB_HOST_HCDMAB15_HCDMAB15 field value from a register. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_HOST_HCDMAB15_HCDMAB15 register field value suitable for setting the register. */
#define ALT_USB_HOST_HCDMAB15_HCDMAB15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_HOST_HCDMAB15.
*/
struct ALT_USB_HOST_HCDMAB15_s
{
uint32_t hcdmab15 : 32; /* ALT_USB_HOST_HCDMAB15_HCDMAB15 */
};
/* The typedef declaration for register ALT_USB_HOST_HCDMAB15. */
typedef volatile struct ALT_USB_HOST_HCDMAB15_s ALT_USB_HOST_HCDMAB15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_HOST_HCDMAB15 register. */
#define ALT_USB_HOST_HCDMAB15_RESET 0x00000000
/* The byte offset of the ALT_USB_HOST_HCDMAB15 register from the beginning of the component. */
#define ALT_USB_HOST_HCDMAB15_OFST 0x2fc
/* The address of the ALT_USB_HOST_HCDMAB15 register. */
#define ALT_USB_HOST_HCDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_HOST_HCDMAB15_OFST))
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_USB_HOST.
*/
struct ALT_USB_HOST_s
{
volatile ALT_USB_HOST_HCFG_t hcfg; /* ALT_USB_HOST_HCFG */
volatile ALT_USB_HOST_HFIR_t hfir; /* ALT_USB_HOST_HFIR */
volatile ALT_USB_HOST_HFNUM_t hfnum; /* ALT_USB_HOST_HFNUM */
volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
volatile ALT_USB_HOST_HPTXSTS_t hptxsts; /* ALT_USB_HOST_HPTXSTS */
volatile ALT_USB_HOST_HAINT_t haint; /* ALT_USB_HOST_HAINT */
volatile ALT_USB_HOST_HAINTMSK_t haintmsk; /* ALT_USB_HOST_HAINTMSK */
volatile ALT_USB_HOST_HFLBADDR_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */
volatile uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */
volatile ALT_USB_HOST_HPRT_t hprt; /* ALT_USB_HOST_HPRT */
volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCCHAR0_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */
volatile ALT_USB_HOST_HCSPLT0_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */
volatile ALT_USB_HOST_HCINT0_t hcint0; /* ALT_USB_HOST_HCINT0 */
volatile ALT_USB_HOST_HCINTMSK0_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */
volatile ALT_USB_HOST_HCTSIZ0_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */
volatile ALT_USB_HOST_HCDMA0_t hcdma0; /* ALT_USB_HOST_HCDMA0 */
volatile uint32_t _pad_0x118_0x11b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB0_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */
volatile ALT_USB_HOST_HCCHAR1_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */
volatile ALT_USB_HOST_HCSPLT1_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */
volatile ALT_USB_HOST_HCINT1_t hcint1; /* ALT_USB_HOST_HCINT1 */
volatile ALT_USB_HOST_HCINTMSK1_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */
volatile ALT_USB_HOST_HCTSIZ1_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */
volatile ALT_USB_HOST_HCDMA1_t hcdma1; /* ALT_USB_HOST_HCDMA1 */
volatile uint32_t _pad_0x138_0x13b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB1_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */
volatile ALT_USB_HOST_HCCHAR2_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */
volatile ALT_USB_HOST_HCSPLT2_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */
volatile ALT_USB_HOST_HCINT2_t hcint2; /* ALT_USB_HOST_HCINT2 */
volatile ALT_USB_HOST_HCINTMSK2_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */
volatile ALT_USB_HOST_HCTSIZ2_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */
volatile ALT_USB_HOST_HCDMA2_t hcdma2; /* ALT_USB_HOST_HCDMA2 */
volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB2_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */
volatile ALT_USB_HOST_HCCHAR3_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */
volatile ALT_USB_HOST_HCSPLT3_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */
volatile ALT_USB_HOST_HCINT3_t hcint3; /* ALT_USB_HOST_HCINT3 */
volatile ALT_USB_HOST_HCINTMSK3_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */
volatile ALT_USB_HOST_HCTSIZ3_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */
volatile ALT_USB_HOST_HCDMA3_t hcdma3; /* ALT_USB_HOST_HCDMA3 */
volatile uint32_t _pad_0x178_0x17b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB3_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */
volatile ALT_USB_HOST_HCCHAR4_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */
volatile ALT_USB_HOST_HCSPLT4_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */
volatile ALT_USB_HOST_HCINT4_t hcint4; /* ALT_USB_HOST_HCINT4 */
volatile ALT_USB_HOST_HCINTMSK4_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */
volatile ALT_USB_HOST_HCTSIZ4_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */
volatile ALT_USB_HOST_HCDMA4_t hcdma4; /* ALT_USB_HOST_HCDMA4 */
volatile uint32_t _pad_0x198_0x19b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB4_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */
volatile ALT_USB_HOST_HCCHAR5_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */
volatile ALT_USB_HOST_HCSPLT5_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */
volatile ALT_USB_HOST_HCINT5_t hcint5; /* ALT_USB_HOST_HCINT5 */
volatile ALT_USB_HOST_HCINTMSK5_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */
volatile ALT_USB_HOST_HCTSIZ5_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */
volatile ALT_USB_HOST_HCDMA5_t hcdma5; /* ALT_USB_HOST_HCDMA5 */
volatile uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB5_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */
volatile ALT_USB_HOST_HCCHAR6_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */
volatile ALT_USB_HOST_HCSPLT6_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */
volatile ALT_USB_HOST_HCINT6_t hcint6; /* ALT_USB_HOST_HCINT6 */
volatile ALT_USB_HOST_HCINTMSK6_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */
volatile ALT_USB_HOST_HCTSIZ6_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */
volatile ALT_USB_HOST_HCDMA6_t hcdma6; /* ALT_USB_HOST_HCDMA6 */
volatile uint32_t _pad_0x1d8_0x1db; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB6_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */
volatile ALT_USB_HOST_HCCHAR7_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */
volatile ALT_USB_HOST_HCSPLT7_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */
volatile ALT_USB_HOST_HCINT7_t hcint7; /* ALT_USB_HOST_HCINT7 */
volatile ALT_USB_HOST_HCINTMSK7_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */
volatile ALT_USB_HOST_HCTSIZ7_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */
volatile ALT_USB_HOST_HCDMA7_t hcdma7; /* ALT_USB_HOST_HCDMA7 */
volatile uint32_t _pad_0x1f8_0x1fb; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB7_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */
volatile ALT_USB_HOST_HCCHAR8_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */
volatile ALT_USB_HOST_HCSPLT8_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */
volatile ALT_USB_HOST_HCINT8_t hcint8; /* ALT_USB_HOST_HCINT8 */
volatile ALT_USB_HOST_HCINTMSK8_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */
volatile ALT_USB_HOST_HCTSIZ8_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */
volatile ALT_USB_HOST_HCDMA8_t hcdma8; /* ALT_USB_HOST_HCDMA8 */
volatile uint32_t _pad_0x218_0x21b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB8_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */
volatile ALT_USB_HOST_HCCHAR9_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */
volatile ALT_USB_HOST_HCSPLT9_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */
volatile ALT_USB_HOST_HCINT9_t hcint9; /* ALT_USB_HOST_HCINT9 */
volatile ALT_USB_HOST_HCINTMSK9_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */
volatile ALT_USB_HOST_HCTSIZ9_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */
volatile ALT_USB_HOST_HCDMA9_t hcdma9; /* ALT_USB_HOST_HCDMA9 */
volatile uint32_t _pad_0x238_0x23b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB9_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */
volatile ALT_USB_HOST_HCCHAR10_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */
volatile ALT_USB_HOST_HCSPLT10_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */
volatile ALT_USB_HOST_HCINT10_t hcint10; /* ALT_USB_HOST_HCINT10 */
volatile ALT_USB_HOST_HCINTMSK10_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */
volatile ALT_USB_HOST_HCTSIZ10_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */
volatile ALT_USB_HOST_HCDMA10_t hcdma10; /* ALT_USB_HOST_HCDMA10 */
volatile uint32_t _pad_0x258_0x25b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB10_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */
volatile ALT_USB_HOST_HCCHAR11_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */
volatile ALT_USB_HOST_HCSPLT11_t hcsplt11; /* ALT_USB_HOST_HCSPLT11 */
volatile ALT_USB_HOST_HCINT11_t hcint11; /* ALT_USB_HOST_HCINT11 */
volatile ALT_USB_HOST_HCINTMSK11_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */
volatile ALT_USB_HOST_HCTSIZ11_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */
volatile ALT_USB_HOST_HCDMA11_t hcdma11; /* ALT_USB_HOST_HCDMA11 */
volatile uint32_t _pad_0x278_0x27b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB11_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */
volatile ALT_USB_HOST_HCCHAR12_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */
volatile ALT_USB_HOST_HCSPLT12_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */
volatile ALT_USB_HOST_HCINT12_t hcint12; /* ALT_USB_HOST_HCINT12 */
volatile ALT_USB_HOST_HCINTMSK12_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */
volatile ALT_USB_HOST_HCTSIZ12_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */
volatile ALT_USB_HOST_HCDMA12_t hcdma12; /* ALT_USB_HOST_HCDMA12 */
volatile uint32_t _pad_0x298_0x29b; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB12_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */
volatile ALT_USB_HOST_HCCHAR13_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */
volatile ALT_USB_HOST_HCSPLT13_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */
volatile ALT_USB_HOST_HCINT13_t hcint13; /* ALT_USB_HOST_HCINT13 */
volatile ALT_USB_HOST_HCINTMSK13_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */
volatile ALT_USB_HOST_HCTSIZ13_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */
volatile ALT_USB_HOST_HCDMA13_t hcdma13; /* ALT_USB_HOST_HCDMA13 */
volatile uint32_t _pad_0x2b8_0x2bb; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB13_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */
volatile ALT_USB_HOST_HCCHAR14_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */
volatile ALT_USB_HOST_HCSPLT14_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */
volatile ALT_USB_HOST_HCINT14_t hcint14; /* ALT_USB_HOST_HCINT14 */
volatile ALT_USB_HOST_HCINTMSK14_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */
volatile ALT_USB_HOST_HCTSIZ14_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */
volatile ALT_USB_HOST_HCDMA14_t hcdma14; /* ALT_USB_HOST_HCDMA14 */
volatile uint32_t _pad_0x2d8_0x2db; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB14_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */
volatile ALT_USB_HOST_HCCHAR15_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */
volatile ALT_USB_HOST_HCSPLT15_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */
volatile ALT_USB_HOST_HCINT15_t hcint15; /* ALT_USB_HOST_HCINT15 */
volatile ALT_USB_HOST_HCINTMSK15_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */
volatile ALT_USB_HOST_HCTSIZ15_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */
volatile ALT_USB_HOST_HCDMA15_t hcdma15; /* ALT_USB_HOST_HCDMA15 */
volatile uint32_t _pad_0x2f8_0x2fb; /* *UNDEFINED* */
volatile ALT_USB_HOST_HCDMAB15_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */
};
/* The typedef declaration for register group ALT_USB_HOST. */
typedef volatile struct ALT_USB_HOST_s ALT_USB_HOST_t;
/* The struct declaration for the raw register contents of register group ALT_USB_HOST. */
struct ALT_USB_HOST_raw_s
{
volatile uint32_t hcfg; /* ALT_USB_HOST_HCFG */
volatile uint32_t hfir; /* ALT_USB_HOST_HFIR */
volatile uint32_t hfnum; /* ALT_USB_HOST_HFNUM */
volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
volatile uint32_t hptxsts; /* ALT_USB_HOST_HPTXSTS */
volatile uint32_t haint; /* ALT_USB_HOST_HAINT */
volatile uint32_t haintmsk; /* ALT_USB_HOST_HAINTMSK */
volatile uint32_t hflbaddr; /* ALT_USB_HOST_HFLBADDR */
volatile uint32_t _pad_0x20_0x3f[8]; /* *UNDEFINED* */
volatile uint32_t hprt; /* ALT_USB_HOST_HPRT */
volatile uint32_t _pad_0x44_0xff[47]; /* *UNDEFINED* */
volatile uint32_t hcchar0; /* ALT_USB_HOST_HCCHAR0 */
volatile uint32_t hcsplt0; /* ALT_USB_HOST_HCSPLT0 */
volatile uint32_t hcint0; /* ALT_USB_HOST_HCINT0 */
volatile uint32_t hcintmsk0; /* ALT_USB_HOST_HCINTMSK0 */
volatile uint32_t hctsiz0; /* ALT_USB_HOST_HCTSIZ0 */
volatile uint32_t hcdma0; /* ALT_USB_HOST_HCDMA0 */
volatile uint32_t _pad_0x118_0x11b; /* *UNDEFINED* */
volatile uint32_t hcdmab0; /* ALT_USB_HOST_HCDMAB0 */
volatile uint32_t hcchar1; /* ALT_USB_HOST_HCCHAR1 */
volatile uint32_t hcsplt1; /* ALT_USB_HOST_HCSPLT1 */
volatile uint32_t hcint1; /* ALT_USB_HOST_HCINT1 */
volatile uint32_t hcintmsk1; /* ALT_USB_HOST_HCINTMSK1 */
volatile uint32_t hctsiz1; /* ALT_USB_HOST_HCTSIZ1 */
volatile uint32_t hcdma1; /* ALT_USB_HOST_HCDMA1 */
volatile uint32_t _pad_0x138_0x13b; /* *UNDEFINED* */
volatile uint32_t hcdmab1; /* ALT_USB_HOST_HCDMAB1 */
volatile uint32_t hcchar2; /* ALT_USB_HOST_HCCHAR2 */
volatile uint32_t hcsplt2; /* ALT_USB_HOST_HCSPLT2 */
volatile uint32_t hcint2; /* ALT_USB_HOST_HCINT2 */
volatile uint32_t hcintmsk2; /* ALT_USB_HOST_HCINTMSK2 */
volatile uint32_t hctsiz2; /* ALT_USB_HOST_HCTSIZ2 */
volatile uint32_t hcdma2; /* ALT_USB_HOST_HCDMA2 */
volatile uint32_t _pad_0x158_0x15b; /* *UNDEFINED* */
volatile uint32_t hcdmab2; /* ALT_USB_HOST_HCDMAB2 */
volatile uint32_t hcchar3; /* ALT_USB_HOST_HCCHAR3 */
volatile uint32_t hcsplt3; /* ALT_USB_HOST_HCSPLT3 */
volatile uint32_t hcint3; /* ALT_USB_HOST_HCINT3 */
volatile uint32_t hcintmsk3; /* ALT_USB_HOST_HCINTMSK3 */
volatile uint32_t hctsiz3; /* ALT_USB_HOST_HCTSIZ3 */
volatile uint32_t hcdma3; /* ALT_USB_HOST_HCDMA3 */
volatile uint32_t _pad_0x178_0x17b; /* *UNDEFINED* */
volatile uint32_t hcdmab3; /* ALT_USB_HOST_HCDMAB3 */
volatile uint32_t hcchar4; /* ALT_USB_HOST_HCCHAR4 */
volatile uint32_t hcsplt4; /* ALT_USB_HOST_HCSPLT4 */
volatile uint32_t hcint4; /* ALT_USB_HOST_HCINT4 */
volatile uint32_t hcintmsk4; /* ALT_USB_HOST_HCINTMSK4 */
volatile uint32_t hctsiz4; /* ALT_USB_HOST_HCTSIZ4 */
volatile uint32_t hcdma4; /* ALT_USB_HOST_HCDMA4 */
volatile uint32_t _pad_0x198_0x19b; /* *UNDEFINED* */
volatile uint32_t hcdmab4; /* ALT_USB_HOST_HCDMAB4 */
volatile uint32_t hcchar5; /* ALT_USB_HOST_HCCHAR5 */
volatile uint32_t hcsplt5; /* ALT_USB_HOST_HCSPLT5 */
volatile uint32_t hcint5; /* ALT_USB_HOST_HCINT5 */
volatile uint32_t hcintmsk5; /* ALT_USB_HOST_HCINTMSK5 */
volatile uint32_t hctsiz5; /* ALT_USB_HOST_HCTSIZ5 */
volatile uint32_t hcdma5; /* ALT_USB_HOST_HCDMA5 */
volatile uint32_t _pad_0x1b8_0x1bb; /* *UNDEFINED* */
volatile uint32_t hcdmab5; /* ALT_USB_HOST_HCDMAB5 */
volatile uint32_t hcchar6; /* ALT_USB_HOST_HCCHAR6 */
volatile uint32_t hcsplt6; /* ALT_USB_HOST_HCSPLT6 */
volatile uint32_t hcint6; /* ALT_USB_HOST_HCINT6 */
volatile uint32_t hcintmsk6; /* ALT_USB_HOST_HCINTMSK6 */
volatile uint32_t hctsiz6; /* ALT_USB_HOST_HCTSIZ6 */
volatile uint32_t hcdma6; /* ALT_USB_HOST_HCDMA6 */
volatile uint32_t _pad_0x1d8_0x1db; /* *UNDEFINED* */
volatile uint32_t hcdmab6; /* ALT_USB_HOST_HCDMAB6 */
volatile uint32_t hcchar7; /* ALT_USB_HOST_HCCHAR7 */
volatile uint32_t hcsplt7; /* ALT_USB_HOST_HCSPLT7 */
volatile uint32_t hcint7; /* ALT_USB_HOST_HCINT7 */
volatile uint32_t hcintmsk7; /* ALT_USB_HOST_HCINTMSK7 */
volatile uint32_t hctsiz7; /* ALT_USB_HOST_HCTSIZ7 */
volatile uint32_t hcdma7; /* ALT_USB_HOST_HCDMA7 */
volatile uint32_t _pad_0x1f8_0x1fb; /* *UNDEFINED* */
volatile uint32_t hcdmab7; /* ALT_USB_HOST_HCDMAB7 */
volatile uint32_t hcchar8; /* ALT_USB_HOST_HCCHAR8 */
volatile uint32_t hcsplt8; /* ALT_USB_HOST_HCSPLT8 */
volatile uint32_t hcint8; /* ALT_USB_HOST_HCINT8 */
volatile uint32_t hcintmsk8; /* ALT_USB_HOST_HCINTMSK8 */
volatile uint32_t hctsiz8; /* ALT_USB_HOST_HCTSIZ8 */
volatile uint32_t hcdma8; /* ALT_USB_HOST_HCDMA8 */
volatile uint32_t _pad_0x218_0x21b; /* *UNDEFINED* */
volatile uint32_t hcdmab8; /* ALT_USB_HOST_HCDMAB8 */
volatile uint32_t hcchar9; /* ALT_USB_HOST_HCCHAR9 */
volatile uint32_t hcsplt9; /* ALT_USB_HOST_HCSPLT9 */
volatile uint32_t hcint9; /* ALT_USB_HOST_HCINT9 */
volatile uint32_t hcintmsk9; /* ALT_USB_HOST_HCINTMSK9 */
volatile uint32_t hctsiz9; /* ALT_USB_HOST_HCTSIZ9 */
volatile uint32_t hcdma9; /* ALT_USB_HOST_HCDMA9 */
volatile uint32_t _pad_0x238_0x23b; /* *UNDEFINED* */
volatile uint32_t hcdmab9; /* ALT_USB_HOST_HCDMAB9 */
volatile uint32_t hcchar10; /* ALT_USB_HOST_HCCHAR10 */
volatile uint32_t hcsplt10; /* ALT_USB_HOST_HCSPLT10 */
volatile uint32_t hcint10; /* ALT_USB_HOST_HCINT10 */
volatile uint32_t hcintmsk10; /* ALT_USB_HOST_HCINTMSK10 */
volatile uint32_t hctsiz10; /* ALT_USB_HOST_HCTSIZ10 */
volatile uint32_t hcdma10; /* ALT_USB_HOST_HCDMA10 */
volatile uint32_t _pad_0x258_0x25b; /* *UNDEFINED* */
volatile uint32_t hcdmab10; /* ALT_USB_HOST_HCDMAB10 */
volatile uint32_t hcchar11; /* ALT_USB_HOST_HCCHAR11 */
volatile uint32_t hcsplt11; /* ALT_USB_HOST_HCSPLT11 */
volatile uint32_t hcint11; /* ALT_USB_HOST_HCINT11 */
volatile uint32_t hcintmsk11; /* ALT_USB_HOST_HCINTMSK11 */
volatile uint32_t hctsiz11; /* ALT_USB_HOST_HCTSIZ11 */
volatile uint32_t hcdma11; /* ALT_USB_HOST_HCDMA11 */
volatile uint32_t _pad_0x278_0x27b; /* *UNDEFINED* */
volatile uint32_t hcdmab11; /* ALT_USB_HOST_HCDMAB11 */
volatile uint32_t hcchar12; /* ALT_USB_HOST_HCCHAR12 */
volatile uint32_t hcsplt12; /* ALT_USB_HOST_HCSPLT12 */
volatile uint32_t hcint12; /* ALT_USB_HOST_HCINT12 */
volatile uint32_t hcintmsk12; /* ALT_USB_HOST_HCINTMSK12 */
volatile uint32_t hctsiz12; /* ALT_USB_HOST_HCTSIZ12 */
volatile uint32_t hcdma12; /* ALT_USB_HOST_HCDMA12 */
volatile uint32_t _pad_0x298_0x29b; /* *UNDEFINED* */
volatile uint32_t hcdmab12; /* ALT_USB_HOST_HCDMAB12 */
volatile uint32_t hcchar13; /* ALT_USB_HOST_HCCHAR13 */
volatile uint32_t hcsplt13; /* ALT_USB_HOST_HCSPLT13 */
volatile uint32_t hcint13; /* ALT_USB_HOST_HCINT13 */
volatile uint32_t hcintmsk13; /* ALT_USB_HOST_HCINTMSK13 */
volatile uint32_t hctsiz13; /* ALT_USB_HOST_HCTSIZ13 */
volatile uint32_t hcdma13; /* ALT_USB_HOST_HCDMA13 */
volatile uint32_t _pad_0x2b8_0x2bb; /* *UNDEFINED* */
volatile uint32_t hcdmab13; /* ALT_USB_HOST_HCDMAB13 */
volatile uint32_t hcchar14; /* ALT_USB_HOST_HCCHAR14 */
volatile uint32_t hcsplt14; /* ALT_USB_HOST_HCSPLT14 */
volatile uint32_t hcint14; /* ALT_USB_HOST_HCINT14 */
volatile uint32_t hcintmsk14; /* ALT_USB_HOST_HCINTMSK14 */
volatile uint32_t hctsiz14; /* ALT_USB_HOST_HCTSIZ14 */
volatile uint32_t hcdma14; /* ALT_USB_HOST_HCDMA14 */
volatile uint32_t _pad_0x2d8_0x2db; /* *UNDEFINED* */
volatile uint32_t hcdmab14; /* ALT_USB_HOST_HCDMAB14 */
volatile uint32_t hcchar15; /* ALT_USB_HOST_HCCHAR15 */
volatile uint32_t hcsplt15; /* ALT_USB_HOST_HCSPLT15 */
volatile uint32_t hcint15; /* ALT_USB_HOST_HCINT15 */
volatile uint32_t hcintmsk15; /* ALT_USB_HOST_HCINTMSK15 */
volatile uint32_t hctsiz15; /* ALT_USB_HOST_HCTSIZ15 */
volatile uint32_t hcdma15; /* ALT_USB_HOST_HCDMA15 */
volatile uint32_t _pad_0x2f8_0x2fb; /* *UNDEFINED* */
volatile uint32_t hcdmab15; /* ALT_USB_HOST_HCDMAB15 */
};
/* The typedef declaration for the raw register contents of register group ALT_USB_HOST. */
typedef volatile struct ALT_USB_HOST_raw_s ALT_USB_HOST_raw_t;
#endif /* __ASSEMBLY__ */
/*
* Component : ALT_USB_DEV
*
*/
/*
* Register : dcfg
*
* Device Configuration Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [1:0] | RW | 0x0 | ALT_USB_DEV_DCFG_DEVSPD
* [2] | RW | 0x0 | ALT_USB_DEV_DCFG_NZSTSOUTHSHK
* [3] | RW | 0x0 | ALT_USB_DEV_DCFG_ENA32KHZSUSP
* [10:4] | RW | 0x0 | ALT_USB_DEV_DCFG_DEVADDR
* [12:11] | RW | 0x0 | ALT_USB_DEV_DCFG_PERFRINT
* [13] | RW | 0x0 | ALT_USB_DEV_DCFG_ENDEVOUTNAK
* [14] | RW | 0x0 | ALT_USB_DEV_DCFG_XCVRDLY
* [15] | RW | 0x0 | ALT_USB_DEV_DCFG_ERRATICINTMSK
* [22:16] | ??? | 0x20 | *UNDEFINED*
* [23] | RW | 0x0 | ALT_USB_DEV_DCFG_DESCDMA
* [25:24] | RW | 0x0 | ALT_USB_DEV_DCFG_PERSCHINTVL
* [31:26] | RW | 0x2 | ALT_USB_DEV_DCFG_RESVALID
*
*/
/*
* Field : devspd
*
* Device Speed (DevSpd)
*
* Indicates the speed at which the application requires the core to
*
* enumerate, or the maximum speed the application can support.
*
* However, the actual bus speed is determined only after the chirp
*
* sequence is completed, and is based on the speed of the USB
*
* host to which the core is connected. See “Device Initialization”
*
* .
*
* 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
*
* 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
*
* 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
*
* you select 6 MHz LS mode, you must do a soft reset.
*
* 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 | 0x0 | High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
* ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 | 0x1 | Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
* ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 | 0x2 | Low speed USB 1.1 transceiver clock is 6 MHz
* ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 | 0x3 | Full speed USB 1.1 transceiver clock is 48 MHz
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
*
* High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
*/
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
*
* Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
*/
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
*
* Low speed USB 1.1 transceiver clock is 6 MHz
*/
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD
*
* Full speed USB 1.1 transceiver clock is 48 MHz
*/
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_MSB 1
/* The width in bits of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DCFG_DEVSPD register field value. */
#define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK 0x00000003
/* The mask used to clear the ALT_USB_DEV_DCFG_DEVSPD register field value. */
#define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK 0xfffffffc
/* The reset value of the ALT_USB_DEV_DCFG_DEVSPD register field. */
#define ALT_USB_DEV_DCFG_DEVSPD_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_DEVSPD field value from a register. */
#define ALT_USB_DEV_DCFG_DEVSPD_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DCFG_DEVSPD register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DEVSPD_SET(value) (((value) << 0) & 0x00000003)
/*
* Field : nzstsouthshk
*
* Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
*
* The application can use this field to select the handshake the
*
* core sends on receiving a nonzero-length data packet during the
*
* OUT transaction of a control transfer's Status stage.
*
* 1'b1: Send a STALL handshake on a nonzero-length status
*
* OUT transaction and do not send the received OUT packet to
*
* the application.
*
* 1'b0: Send the received OUT packet to the application (zerolength
*
* or nonzero-length) and send a handshake based on
*
* the NAK and STALL bits For the endpoint in the Device
*
* Endpoint Control register.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT | 0x0 | Send the received OUT packet to the application
* : | | zerolength
* ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL | 0x1 | Send a STALL handshake on a nonzero-length
* : | | status OUT transaction and do not send the
* : | | received OUT packet to the application
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
*
* Send the received OUT packet to the application zerolength
*/
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK
*
* Send a STALL handshake on a nonzero-length status OUT transaction and do not
* send the received OUT packet to the application
*/
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB 2
/* The width in bits of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_NZSTSOUTHSHK field value from a register. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : ena32khzsusp
*
* Enable 32 KHz Suspend mode (Ena32KHzSusp)
*
* This bit can be set only if FS PHY interface is selected. Else,
*
* this bit needs to be set to zero. When FS PHY interface is chosen
*
* and this bit is set, the core expects that the PHY clock during
*
* Suspend is switched from 48 MHz to 32 KHz.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD | 0x0 | USB 1.1 Full-Speed Serial Transceiver not
* : | | selected
* ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END | 0x1 | USB 1.1 Full-Speed Serial Transceiver Interface
* : | | selected
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
*
* USB 1.1 Full-Speed Serial Transceiver not selected
*/
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP
*
* USB 1.1 Full-Speed Serial Transceiver Interface selected
*/
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB 3
/* The width in bits of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_ENA32KHZSUSP field value from a register. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : devaddr
*
* Device Address (DevAddr)
*
* The application must program this field after every SetAddress
*
* control command.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_MSB 10
/* The width in bits of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_WIDTH 7
/* The mask used to set the ALT_USB_DEV_DCFG_DEVADDR register field value. */
#define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK 0x000007f0
/* The mask used to clear the ALT_USB_DEV_DCFG_DEVADDR register field value. */
#define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK 0xfffff80f
/* The reset value of the ALT_USB_DEV_DCFG_DEVADDR register field. */
#define ALT_USB_DEV_DCFG_DEVADDR_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_DEVADDR field value from a register. */
#define ALT_USB_DEV_DCFG_DEVADDR_GET(value) (((value) & 0x000007f0) >> 4)
/* Produces a ALT_USB_DEV_DCFG_DEVADDR register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DEVADDR_SET(value) (((value) << 4) & 0x000007f0)
/*
* Field : perfrint
*
* Periodic Frame Interval (PerFrInt)
*
* Indicates the time within a (micro)frame at which the application
*
* must be notified using the End Of Periodic Frame Interrupt. This
*
* can be used to determine If all the isochronous traffic For that
*
* (micro)frame is complete.
*
* 2'b00: 80% of the (micro)frame interval
*
* 2'b01: 85%
*
* 2'b10: 90%
*
* 2'b11: 95%
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------
* ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 | 0x0 | 80% of the (micro)frame interval
* ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 | 0x1 | 85% of the (micro)frame interval
* ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 | 0x2 | 90% of the (micro)frame interval
* ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 | 0x3 | 95% of the (micro)frame interval
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
*
* 80% of the (micro)frame interval
*/
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
*
* 85% of the (micro)frame interval
*/
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
*
* 90% of the (micro)frame interval
*/
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT
*
* 95% of the (micro)frame interval
*/
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_MSB 12
/* The width in bits of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DCFG_PERFRINT register field value. */
#define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK 0x00001800
/* The mask used to clear the ALT_USB_DEV_DCFG_PERFRINT register field value. */
#define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK 0xffffe7ff
/* The reset value of the ALT_USB_DEV_DCFG_PERFRINT register field. */
#define ALT_USB_DEV_DCFG_PERFRINT_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_PERFRINT field value from a register. */
#define ALT_USB_DEV_DCFG_PERFRINT_GET(value) (((value) & 0x00001800) >> 11)
/* Produces a ALT_USB_DEV_DCFG_PERFRINT register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_PERFRINT_SET(value) (((value) << 11) & 0x00001800)
/*
* Field : endevoutnak
*
* Enable Device OUT NAK (EnDevOutNak)
*
* This bit enables setting NAK for Bulk OUT endpoints after the transfer is
* completed
*
* for Device mode Descriptor DMA
*
* 1'b0 : The core does not set NAK after Bulk OUT transfer complete
*
* 1'b1 : The core sets NAK after Bulk OUT transfer complete
*
* It is one time
*
* programmable after reset like any other DCFG register bits.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------------------
* ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD | 0x0 | The core does not set NAK after Bulk OUT
* : | | transfer complete
* ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END | 0x1 | The core sets NAK after Bulk OUT transfer
* : | | complete
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
*
* The core does not set NAK after Bulk OUT transfer complete
*/
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK
*
* The core sets NAK after Bulk OUT transfer complete
*/
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB 13
/* The width in bits of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_ENDEVOUTNAK field value from a register. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : xcvrdly
*
* 1'b1: Enable delay between xcvr_sel and txvalid during Device chirp
*
* 1'b0: No delay between xcvr_sel and txvalid during Device chirp
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
#define ALT_USB_DEV_DCFG_XCVRDLY_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
#define ALT_USB_DEV_DCFG_XCVRDLY_MSB 14
/* The width in bits of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
#define ALT_USB_DEV_DCFG_XCVRDLY_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_XCVRDLY register field value. */
#define ALT_USB_DEV_DCFG_XCVRDLY_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DCFG_XCVRDLY register field value. */
#define ALT_USB_DEV_DCFG_XCVRDLY_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DCFG_XCVRDLY register field. */
#define ALT_USB_DEV_DCFG_XCVRDLY_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_XCVRDLY field value from a register. */
#define ALT_USB_DEV_DCFG_XCVRDLY_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DCFG_XCVRDLY register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_XCVRDLY_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : erraticintmsk
*
* Erratic Error Interrupt Mask
*
* 1'b1: Mask early suspend interrupt on erratic error
*
* 1'b0: Early suspend interrupt is generated on erratic error
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_MSB 15
/* The width in bits of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_ERRATICINTMSK register field value. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DCFG_ERRATICINTMSK register field value. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DCFG_ERRATICINTMSK register field. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_ERRATICINTMSK field value from a register. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DCFG_ERRATICINTMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_ERRATICINTMSK_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : descdma
*
* Enable Scatter/gather DMA in device mode (DescDMA).
*
* When the Scatter/Gather DMA option selected during
*
* configuration of the RTL, the application can Set this bit during
*
* initialization to enable the Scatter/Gather DMA operation.
*
* NOTE: This bit must be modified only once after a reset.
*
* The following combinations are available For programming:
*
* GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode
*
* GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid
*
* GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA
*
* mode
*
* GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =>
*
* Scatter/Gather DMA mode
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:---------------------------
* ALT_USB_DEV_DCFG_DESCDMA_E_DISD | 0x0 | Disable Scatter gather DMA
* ALT_USB_DEV_DCFG_DESCDMA_E_END | 0x1 | Enable Scatter gather DMA
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
*
* Disable Scatter gather DMA
*/
#define ALT_USB_DEV_DCFG_DESCDMA_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA
*
* Enable Scatter gather DMA
*/
#define ALT_USB_DEV_DCFG_DESCDMA_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_MSB 23
/* The width in bits of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCFG_DESCDMA register field value. */
#define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_DEV_DCFG_DESCDMA register field value. */
#define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_DEV_DCFG_DESCDMA register field. */
#define ALT_USB_DEV_DCFG_DESCDMA_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_DESCDMA field value from a register. */
#define ALT_USB_DEV_DCFG_DESCDMA_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DCFG_DESCDMA register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_DESCDMA_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : perschintvl
*
* Periodic Scheduling Interval (PerSchIntvl)
*
* PerSchIntvl must be programmed only For Scatter/Gather DMA
*
* mode.
*
* Description: This field specifies the amount of time the Internal
*
* DMA engine must allocate For fetching periodic IN endpoint data.
*
* Based on the number of periodic endpoints, this value must be
*
* specified as 25,50 or 75% of (micro)frame.
*
* When any periodic endpoints are active, the internal DMA
*
* engine allocates the specified amount of time in fetching
*
* periodic IN endpoint data .
*
* When no periodic endpoints are active, Then the internal
*
* DMA engine services non-periodic endpoints, ignoring this
*
* field.
*
* After the specified time within a (micro)frame, the DMA switches
*
* to fetching For non-periodic endpoints.
*
* 2'b00: 25% of (micro)frame.
*
* 2'b01: 50% of (micro)frame.
*
* 2'b10: 75% of (micro)frame.
*
* 2'b11: Reserved.
*
* Reset: 2'b00
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 | 0x0 | 25% of (micro)frame
* ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 | 0x1 | 50% of (micro)frame
* ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 | 0x2 | 75% of (micro)frame
* ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD | 0x3 | Reserved
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
*
* 25% of (micro)frame
*/
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
*
* 50% of (micro)frame
*/
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
*
* 75% of (micro)frame
*/
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL
*
* Reserved
*/
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB 25
/* The width in bits of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK 0x03000000
/* The mask used to clear the ALT_USB_DEV_DCFG_PERSCHINTVL register field value. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK 0xfcffffff
/* The reset value of the ALT_USB_DEV_DCFG_PERSCHINTVL register field. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET 0x0
/* Extracts the ALT_USB_DEV_DCFG_PERSCHINTVL field value from a register. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_GET(value) (((value) & 0x03000000) >> 24)
/* Produces a ALT_USB_DEV_DCFG_PERSCHINTVL register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET(value) (((value) << 24) & 0x03000000)
/*
* Field : resvalid
*
* Resume Validation Period (ResValid)
*
* This field is effective only when DCFG.Ena32KHzSusp is set.
*
* It will control the resume period when the core resumes from
*
* suspend. The core counts for “ResValid” number of clock cycles
*
* to detect a valid resume when this is set
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_MSB 31
/* The width in bits of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_WIDTH 6
/* The mask used to set the ALT_USB_DEV_DCFG_RESVALID register field value. */
#define ALT_USB_DEV_DCFG_RESVALID_SET_MSK 0xfc000000
/* The mask used to clear the ALT_USB_DEV_DCFG_RESVALID register field value. */
#define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK 0x03ffffff
/* The reset value of the ALT_USB_DEV_DCFG_RESVALID register field. */
#define ALT_USB_DEV_DCFG_RESVALID_RESET 0x2
/* Extracts the ALT_USB_DEV_DCFG_RESVALID field value from a register. */
#define ALT_USB_DEV_DCFG_RESVALID_GET(value) (((value) & 0xfc000000) >> 26)
/* Produces a ALT_USB_DEV_DCFG_RESVALID register field value suitable for setting the register. */
#define ALT_USB_DEV_DCFG_RESVALID_SET(value) (((value) << 26) & 0xfc000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DCFG.
*/
struct ALT_USB_DEV_DCFG_s
{
uint32_t devspd : 2; /* ALT_USB_DEV_DCFG_DEVSPD */
uint32_t nzstsouthshk : 1; /* ALT_USB_DEV_DCFG_NZSTSOUTHSHK */
uint32_t ena32khzsusp : 1; /* ALT_USB_DEV_DCFG_ENA32KHZSUSP */
uint32_t devaddr : 7; /* ALT_USB_DEV_DCFG_DEVADDR */
uint32_t perfrint : 2; /* ALT_USB_DEV_DCFG_PERFRINT */
uint32_t endevoutnak : 1; /* ALT_USB_DEV_DCFG_ENDEVOUTNAK */
uint32_t xcvrdly : 1; /* ALT_USB_DEV_DCFG_XCVRDLY */
uint32_t erraticintmsk : 1; /* ALT_USB_DEV_DCFG_ERRATICINTMSK */
uint32_t : 7; /* *UNDEFINED* */
uint32_t descdma : 1; /* ALT_USB_DEV_DCFG_DESCDMA */
uint32_t perschintvl : 2; /* ALT_USB_DEV_DCFG_PERSCHINTVL */
uint32_t resvalid : 6; /* ALT_USB_DEV_DCFG_RESVALID */
};
/* The typedef declaration for register ALT_USB_DEV_DCFG. */
typedef volatile struct ALT_USB_DEV_DCFG_s ALT_USB_DEV_DCFG_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DCFG register. */
#define ALT_USB_DEV_DCFG_RESET 0x08200000
/* The byte offset of the ALT_USB_DEV_DCFG register from the beginning of the component. */
#define ALT_USB_DEV_DCFG_OFST 0x0
/* The address of the ALT_USB_DEV_DCFG register. */
#define ALT_USB_DEV_DCFG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST))
/*
* Register : dctl
*
* Device Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DCTL_RMTWKUPSIG
* [1] | RW | 0x1 | ALT_USB_DEV_DCTL_SFTDISCON
* [2] | R | 0x0 | ALT_USB_DEV_DCTL_GNPINNAKSTS
* [3] | R | 0x0 | ALT_USB_DEV_DCTL_GOUTNAKSTS
* [6:4] | RW | 0x0 | ALT_USB_DEV_DCTL_TSTCTL
* [7] | W | 0x0 | ALT_USB_DEV_DCTL_SGNPINNAK
* [8] | W | 0x0 | ALT_USB_DEV_DCTL_CGNPINNAK
* [9] | W | 0x0 | ALT_USB_DEV_DCTL_SGOUTNAK
* [10] | W | 0x0 | ALT_USB_DEV_DCTL_CGOUTNAK
* [11] | RW | 0x0 | ALT_USB_DEV_DCTL_PWRONPRGDONE
* [12] | ??? | 0x0 | *UNDEFINED*
* [14:13] | RW | 0x0 | ALT_USB_DEV_DCTL_GMC
* [15] | RW | 0x0 | ALT_USB_DEV_DCTL_IGNRFRMNUM
* [16] | RW | 0x0 | ALT_USB_DEV_DCTL_NAKONBBLE
* [17] | RW | 0x0 | ALT_USB_DEV_DCTL_ENCONTONBNA
* [31:18] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : rmtwkupsig
*
* Remote Wakeup Signaling (RmtWkUpSig)
*
* When the application sets this bit, the core initiates remote
*
* signaling to wake up the USB host. The application must Set this
*
* bit to instruct the core to exit the Suspend state. As specified in
*
* the USB 2.0 specification, the application must clear this bit
*
* 1-15 ms after setting it.
*
* Remote Wakeup Signaling (RmtWkUpSig) When LPM is enabled,
*
* In L1 state the behavior of this bit is as follows:
*
* When the application sets this bit, the core initiates L1 remote signaling to
*
* wake up the USB host. The application must set this bit to instruct the core
*
* to exit the Sleep state. As specified in the LPM specification,
*
* the hardware will automatically clear this bit after a time of 50 micro sec
* (TL1DevDrvResume)
*
* after set by application. Application should not set this bit when GLPMCFG
* bRemoteWake
*
* from the previous LPM transaction was zero.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------
* ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT | 0x0 | No exit suspend state
* ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT | 0x1 | Exit Suspend State
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
*
* No exit suspend state
*/
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_NOEXIT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_RMTWKUPSIG
*
* Exit Suspend State
*/
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_E_EXIT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_MSB 0
/* The width in bits of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DCTL_RMTWKUPSIG register field value. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DCTL_RMTWKUPSIG register field. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_RMTWKUPSIG field value from a register. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DCTL_RMTWKUPSIG register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_RMTWKUPSIG_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : sftdiscon
*
* Soft Disconnect (SftDiscon)
*
* The application uses this bit to signal the DWC_otg core to do a
*
* soft disconnect. As long as this bit is Set, the host does not see
*
* that the device is connected, and the device does not receive
*
* signals on the USB. The core stays in the disconnected state
*
* until the application clears this bit.
*
* The minimum duration For which the core must keep this bit Set
*
* is specified in Table 5-46.
*
* 1'b0: Normal operation. When this bit is cleared after a soft
*
* disconnect, the core drives the phy_opmode_o signal on the
*
* UTMI+ to 2'b00, which generates a device connect event to
*
* the USB host. When the device is reconnected, the USB host
*
* restarts device enumeration.
*
* 1'b1: The core drives the phy_opmode_o signal on the
*
* UTMI+ to 2'b01, which generates a device disconnect event
*
* to the USB host.
*
* Note: This bit can be also used for ULPI/FS Serial interfaces.
*
* Note: This bit is not impacted by a soft reset.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-----------------------------------------------
* ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT | 0x0 | Normal operation
* ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT | 0x1 | The core drives the phy_opmode_o signal on the
* : | | ULPI
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
*
* Normal operation
*/
#define ALT_USB_DEV_DCTL_SFTDISCON_E_NODISCONNECT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SFTDISCON
*
* The core drives the phy_opmode_o signal on the ULPI
*/
#define ALT_USB_DEV_DCTL_SFTDISCON_E_DISCONNECT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_MSB 1
/* The width in bits of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
#define ALT_USB_DEV_DCTL_SFTDISCON_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DCTL_SFTDISCON register field value. */
#define ALT_USB_DEV_DCTL_SFTDISCON_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DCTL_SFTDISCON register field. */
#define ALT_USB_DEV_DCTL_SFTDISCON_RESET 0x1
/* Extracts the ALT_USB_DEV_DCTL_SFTDISCON field value from a register. */
#define ALT_USB_DEV_DCTL_SFTDISCON_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DCTL_SFTDISCON register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SFTDISCON_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : gnpinnaksts
*
* Global Non-periodic IN NAK Status (GNPINNakSts)
*
* 1'b0: A handshake is sent out based on the data availability
*
* in the transmit FIFO.
*
* 1'b1: A NAK handshake is sent out on all non-periodic IN
*
* endpoints, irrespective of the data availability in the transmit
*
* FIFO.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT | 0x0 | A handshake is sent out based on the data
* : | | availability in the transmit FIFO
* ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT | 0x1 | A NAK handshake is sent out on all non-periodic
* : | | IN endpoints, irrespective of the data
* : | | availability in the transmit FIFO.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
*
* A handshake is sent out based on the data availability in the transmit FIFO
*/
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GNPINNAKSTS
*
* A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of
* the data availability in the transmit FIFO.
*/
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_MSB 2
/* The width in bits of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DCTL_GNPINNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DCTL_GNPINNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_GNPINNAKSTS field value from a register. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DCTL_GNPINNAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GNPINNAKSTS_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : goutnaksts
*
* Global OUT NAK Status (GOUTNakSts)
*
* 1'b0: A handshake is sent based on the FIFO Status and the
*
* NAK and STALL bit settings.
*
* 1'b1: No data is written to the RxFIFO, irrespective of space
*
* availability. Sends a NAK handshake on all packets, except
*
* on SETUP transactions. All isochronous OUT packets are
*
* dropped.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------------------------------
* ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT | 0x0 | A handshake is sent based on the FIFO Status and
* : | | the NAK and STALL bit settings.
* ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT | 0x1 | No data is written to the RxFIFO, irrespective
* : | | of space availability. Sends a NAK handshake on
* : | | all packets, except on SETUP transactions. All
* : | | isochronous OUT packets are dropped.
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
*
* A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
*/
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GOUTNAKSTS
*
* No data is written to the RxFIFO, irrespective of space availability. Sends a
* NAK handshake on all packets, except on SETUP transactions. All isochronous OUT
* packets are dropped.
*/
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_MSB 3
/* The width in bits of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DCTL_GOUTNAKSTS register field value. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DCTL_GOUTNAKSTS register field. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_GOUTNAKSTS field value from a register. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DCTL_GOUTNAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GOUTNAKSTS_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : tstctl
*
* Test Control (TstCtl)
*
* 3'b000: Test mode disabled
*
* 3'b001: Test_J mode
*
* 3'b010: Test_K mode
*
* 3'b011: Test_SE0_NAK mode
*
* 3'b100: Test_Packet mode
*
* 3'b101: Test_Force_Enable
*
* Others: Reserved
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-------------------
* ALT_USB_DEV_DCTL_TSTCTL_E_DISD | 0x0 | Test mode disabled
* ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ | 0x1 | Test_J mode
* ALT_USB_DEV_DCTL_TSTCTL_E_TESTK | 0x2 | Test_K mode
* ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN | 0x3 | Test_SE0_NAK mode
* ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM | 0x4 | Test_Packet mode
* ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE | 0x5 | Test_force_Enable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test mode disabled
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test_J mode
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTJ 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test_K mode
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test_SE0_NAK mode
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTSN 0x3
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test_Packet mode
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTPM 0x4
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_TSTCTL
*
* Test_force_Enable
*/
#define ALT_USB_DEV_DCTL_TSTCTL_E_TESTFE 0x5
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_MSB 6
/* The width in bits of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_WIDTH 3
/* The mask used to set the ALT_USB_DEV_DCTL_TSTCTL register field value. */
#define ALT_USB_DEV_DCTL_TSTCTL_SET_MSK 0x00000070
/* The mask used to clear the ALT_USB_DEV_DCTL_TSTCTL register field value. */
#define ALT_USB_DEV_DCTL_TSTCTL_CLR_MSK 0xffffff8f
/* The reset value of the ALT_USB_DEV_DCTL_TSTCTL register field. */
#define ALT_USB_DEV_DCTL_TSTCTL_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_TSTCTL field value from a register. */
#define ALT_USB_DEV_DCTL_TSTCTL_GET(value) (((value) & 0x00000070) >> 4)
/* Produces a ALT_USB_DEV_DCTL_TSTCTL register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_TSTCTL_SET(value) (((value) << 4) & 0x00000070)
/*
* Field : sgnpinnak
*
* Set Global Non-periodic IN NAK (SGNPInNak)
*
* A write to this field sets the Global Non-periodic IN NAK.The
*
* application uses this bit to send a NAK handshake on all nonperiodic
*
* IN endpoints. The core can also Set this bit when a
*
* timeout condition is detected on a non-periodic endpoint in
*
* shared FIFO operation.
*
* The application must Set this bit only after making sure that the
*
* Global IN NAK Effective bit in the Core Interrupt Register
*
* (GINTSTS.GINNakEff) is cleared
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------------
* ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD | 0x0 | Disable Global Non-periodic IN NAK
* ALT_USB_DEV_DCTL_SGNPINNAK_E_END | 0x1 | Global Non-periodic IN NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
*
* Disable Global Non-periodic IN NAK
*/
#define ALT_USB_DEV_DCTL_SGNPINNAK_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SGNPINNAK
*
* Global Non-periodic IN NAK
*/
#define ALT_USB_DEV_DCTL_SGNPINNAK_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_MSB 7
/* The width in bits of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DCTL_SGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DCTL_SGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_SGNPINNAK field value from a register. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DCTL_SGNPINNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SGNPINNAK_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : cgnpinnak
*
* Clear Global Non-periodic IN NAK (CGNPInNak)
*
* A write to this field clears the Global Non-periodic IN NAK.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------------
* ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS | 0x0 | Disable Global Non-periodic IN NAK
* ALT_USB_DEV_DCTL_CGNPINNAK_E_EN | 0x1 | Clear Global Non-periodic IN NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
*
* Disable Global Non-periodic IN NAK
*/
#define ALT_USB_DEV_DCTL_CGNPINNAK_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_CGNPINNAK
*
* Clear Global Non-periodic IN NAK
*/
#define ALT_USB_DEV_DCTL_CGNPINNAK_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_MSB 8
/* The width in bits of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DCTL_CGNPINNAK register field value. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DCTL_CGNPINNAK register field. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_CGNPINNAK field value from a register. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DCTL_CGNPINNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_CGNPINNAK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : sgoutnak
*
* Set Global OUT NAK (SGOUTNak)
*
* A write to this field sets the Global OUT NAK.
*
* The application uses this bit to send a NAK handshake on all
*
* OUT endpoints.
*
* The application must Set the this bit only after making sure that
*
* the Global OUT NAK Effective bit in the Core Interrupt Register
*
* (GINTSTS.GOUTNakEff) is cleared.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------
* ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD | 0x0 | Disable Global OUT NAK
* ALT_USB_DEV_DCTL_SGOUTNAK_E_END | 0x1 | Global OUT NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
*
* Disable Global OUT NAK
*/
#define ALT_USB_DEV_DCTL_SGOUTNAK_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_SGOUTNAK
*
* Global OUT NAK
*/
#define ALT_USB_DEV_DCTL_SGOUTNAK_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_MSB 9
/* The width in bits of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DCTL_SGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DCTL_SGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_SGOUTNAK field value from a register. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DCTL_SGOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_SGOUTNAK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : cgoutnak
*
* Clear Global OUT NAK (CGOUTNak)
*
* A write to this field clears the Global OUT NAK.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD | 0x0 | Disable Clear Global OUT NAK
* ALT_USB_DEV_DCTL_CGOUTNAK_E_END | 0x1 | Clear Global OUT NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
*
* Disable Clear Global OUT NAK
*/
#define ALT_USB_DEV_DCTL_CGOUTNAK_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_CGOUTNAK
*
* Clear Global OUT NAK
*/
#define ALT_USB_DEV_DCTL_CGOUTNAK_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_MSB 10
/* The width in bits of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_DEV_DCTL_CGOUTNAK register field value. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_DEV_DCTL_CGOUTNAK register field. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_CGOUTNAK field value from a register. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DCTL_CGOUTNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_CGOUTNAK_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : pwronprgdone
*
* Power-On Programming Done (PWROnPrgDone)
*
* The application uses this bit to indicate that register
*
* programming is completed after a wake-up from Power Down
*
* mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE | 0x0 | Power-On Programming not done
* ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE | 0x1 | Power-On Programming Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
*
* Power-On Programming not done
*/
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_NOTDONE 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_PWRONPRGDONE
*
* Power-On Programming Done
*/
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_E_DONE 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_MSB 11
/* The width in bits of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DCTL_PWRONPRGDONE register field value. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DCTL_PWRONPRGDONE register field. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_PWRONPRGDONE field value from a register. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DCTL_PWRONPRGDONE register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_PWRONPRGDONE_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : gmc
*
* Global Multi Count (GMC)
*
* GMC must be programmed only once after initialization.
*
* Applicable only For Scatter/Gather DMA mode. This indicates the
*
* number of packets to be serviced For that end point before
*
* moving to the next end point. It is only For non-periodic end
*
* points.
*
* 2'b00: Invalid.
*
* 2'b01: 1 packet.
*
* 2'b10: 2 packets.
*
* 2'b11: 3 packets.
*
* When Scatter/Gather DMA mode is disabled, this field is
*
* reserved. and reads 2'b00.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:------------
* ALT_USB_DEV_DCTL_GMC_E_NOTVALID | 0x0 | Invalid
* ALT_USB_DEV_DCTL_GMC_E_ONEPKT | 0x1 | 1 packet
* ALT_USB_DEV_DCTL_GMC_E_TWOPKT | 0x2 | 2 packets
* ALT_USB_DEV_DCTL_GMC_E_THREEPKT | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GMC
*
* Invalid
*/
#define ALT_USB_DEV_DCTL_GMC_E_NOTVALID 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GMC
*
* 1 packet
*/
#define ALT_USB_DEV_DCTL_GMC_E_ONEPKT 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GMC
*
* 2 packets
*/
#define ALT_USB_DEV_DCTL_GMC_E_TWOPKT 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_GMC
*
* 3 packets
*/
#define ALT_USB_DEV_DCTL_GMC_E_THREEPKT 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_MSB 14
/* The width in bits of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DCTL_GMC register field value. */
#define ALT_USB_DEV_DCTL_GMC_SET_MSK 0x00006000
/* The mask used to clear the ALT_USB_DEV_DCTL_GMC register field value. */
#define ALT_USB_DEV_DCTL_GMC_CLR_MSK 0xffff9fff
/* The reset value of the ALT_USB_DEV_DCTL_GMC register field. */
#define ALT_USB_DEV_DCTL_GMC_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_GMC field value from a register. */
#define ALT_USB_DEV_DCTL_GMC_GET(value) (((value) & 0x00006000) >> 13)
/* Produces a ALT_USB_DEV_DCTL_GMC register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_GMC_SET(value) (((value) << 13) & 0x00006000)
/*
* Field : ignrfrmnum
*
* Ignore Frame number For Isochronous End points (IgnrFrmNum)
*
* Do NOT program IgnrFrmNum bit to 1'b1 when the core is
*
* operating in threshold mode.
*
* Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to
* High Speed, High bandwidth transfers. When this bit is enabled, there must be
* only one packet per descriptor.
*
* 0: The core transmits the packets only in the frame number in which they are
* intended to be transmitted.
*
* 1: The core ignores the frame number, sending packets immediately as the packets
* are ready.
*
* In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed
* when a ISOC IN token is received for an elapsed frame.
*
* When Scatter/Gather DMA mode is disabled, this field is used by the application
* to enable periodic transfer interrupt. The application can program periodic
* endpoint transfers for multiple (micro)frames.
*
* 0: periodic transfer interrupt feature is disabled, application needs to program
* transfers for periodic endpoints every (micro)frame
*
* 1: periodic transfer interrupt feature is enabled, application can program
* transfers for multiple (micro)frames for periodic endpoints.
*
* In non Scatter/Gather DMA mode the application will receive transfer complete
* interrupt after transfers for multiple (micro)frames are completed.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------------------------------
* ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD | 0x0 | The core transmits the packets only in the frame
* : | | number in which they are intended to be
* : | | transmitted
* ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END | 0x1 | The core ignores the frame number, sending
* : | | packets immediately as the packets are ready
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
*
* The core transmits the packets only in the frame number in which they are
* intended to be transmitted
*/
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_IGNRFRMNUM
*
* The core ignores the frame number, sending packets immediately as the packets
* are ready
*/
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_MSB 15
/* The width in bits of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DCTL_IGNRFRMNUM register field value. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DCTL_IGNRFRMNUM register field. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_IGNRFRMNUM field value from a register. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DCTL_IGNRFRMNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_IGNRFRMNUM_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : nakonbble
*
* NAK on Babble Error (NakOnBble)
*
* Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for
* the
*
* endpoint on which babble is received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD | 0x0 | Disable NAK on Babble Error
* ALT_USB_DEV_DCTL_NAKONBBLE_E_END | 0x1 | NAK on Babble Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
*
* Disable NAK on Babble Error
*/
#define ALT_USB_DEV_DCTL_NAKONBBLE_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DCTL_NAKONBBLE
*
* NAK on Babble Error
*/
#define ALT_USB_DEV_DCTL_NAKONBBLE_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_MSB 16
/* The width in bits of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DCTL_NAKONBBLE register field value. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DCTL_NAKONBBLE register field. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_NAKONBBLE field value from a register. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DCTL_NAKONBBLE register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_NAKONBBLE_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : encontonbna
*
* Enable Continue on BNA (EnContOnBNA)
*
* This bit enables the DWC_otg core to continue on BNA for Bulk OUT endpoints.
*
* With this feature enabled, when a Bulk OUT endpoint receives a BNA interrupt
*
* the core starts processing the descriptor that caused the BNA interrupt after
*
* the endpoint re-enables the endpoint.
*
* 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the
*
* endpoint is re-enabled by the application,the core starts processing from
*
* the DOEPDMA descriptor.
*
* 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the
*
* endpoint is re-enabled by the application, the core starts processing from
*
* the descriptor that received the BNA interrupt. This bit is valid only when
*
* OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like
*
* any other DCTL register bits.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_MSB 17
/* The width in bits of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DCTL_ENCONTONBNA register field value. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DCTL_ENCONTONBNA register field value. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DCTL_ENCONTONBNA register field. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_RESET 0x0
/* Extracts the ALT_USB_DEV_DCTL_ENCONTONBNA field value from a register. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DCTL_ENCONTONBNA register field value suitable for setting the register. */
#define ALT_USB_DEV_DCTL_ENCONTONBNA_SET(value) (((value) << 17) & 0x00020000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DCTL.
*/
struct ALT_USB_DEV_DCTL_s
{
uint32_t rmtwkupsig : 1; /* ALT_USB_DEV_DCTL_RMTWKUPSIG */
uint32_t sftdiscon : 1; /* ALT_USB_DEV_DCTL_SFTDISCON */
const uint32_t gnpinnaksts : 1; /* ALT_USB_DEV_DCTL_GNPINNAKSTS */
const uint32_t goutnaksts : 1; /* ALT_USB_DEV_DCTL_GOUTNAKSTS */
uint32_t tstctl : 3; /* ALT_USB_DEV_DCTL_TSTCTL */
uint32_t sgnpinnak : 1; /* ALT_USB_DEV_DCTL_SGNPINNAK */
uint32_t cgnpinnak : 1; /* ALT_USB_DEV_DCTL_CGNPINNAK */
uint32_t sgoutnak : 1; /* ALT_USB_DEV_DCTL_SGOUTNAK */
uint32_t cgoutnak : 1; /* ALT_USB_DEV_DCTL_CGOUTNAK */
uint32_t pwronprgdone : 1; /* ALT_USB_DEV_DCTL_PWRONPRGDONE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t gmc : 2; /* ALT_USB_DEV_DCTL_GMC */
uint32_t ignrfrmnum : 1; /* ALT_USB_DEV_DCTL_IGNRFRMNUM */
uint32_t nakonbble : 1; /* ALT_USB_DEV_DCTL_NAKONBBLE */
uint32_t encontonbna : 1; /* ALT_USB_DEV_DCTL_ENCONTONBNA */
uint32_t : 14; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DCTL. */
typedef volatile struct ALT_USB_DEV_DCTL_s ALT_USB_DEV_DCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DCTL register. */
#define ALT_USB_DEV_DCTL_RESET 0x00000002
/* The byte offset of the ALT_USB_DEV_DCTL register from the beginning of the component. */
#define ALT_USB_DEV_DCTL_OFST 0x4
/* The address of the ALT_USB_DEV_DCTL register. */
#define ALT_USB_DEV_DCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCTL_OFST))
/*
* Register : dsts
*
* Device Status Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------
* [0] | R | 0x0 | ALT_USB_DEV_DSTS_SUSPSTS
* [2:1] | R | 0x1 | ALT_USB_DEV_DSTS_ENUMSPD
* [3] | R | 0x0 | ALT_USB_DEV_DSTS_ERRTICERR
* [7:4] | ??? | 0x0 | *UNDEFINED*
* [21:8] | R | 0x0 | ALT_USB_DEV_DSTS_SOFFN
* [23:22] | R | 0x0 | ALT_USB_DEV_DSTS_DEVLNSTS
* [31:24] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : suspsts
*
* Suspend Status (SuspSts)
*
* In Device mode, this bit is Set as long as a Suspend condition is
*
* detected on the USB. The core enters the Suspended state
*
* when there is no activity on the phy_line_state_i signal For an
*
* extended period of time. The core comes out of the suspend:
*
* When there is any activity on the phy_line_state_i signal
*
* When the application writes to the Remote Wakeup Signaling
*
* bit in the Device Control register (DCTL.RmtWkUpSig).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:-----------------
* ALT_USB_DEV_DSTS_SUSPSTS_E_INACT | 0x0 | No suspend state
* ALT_USB_DEV_DSTS_SUSPSTS_E_ACT | 0x1 | Suspend state
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
*
* No suspend state
*/
#define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS
*
* Suspend state
*/
#define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_MSB 0
/* The width in bits of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
#define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DSTS_SUSPSTS register field value. */
#define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DSTS_SUSPSTS register field. */
#define ALT_USB_DEV_DSTS_SUSPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DSTS_SUSPSTS field value from a register. */
#define ALT_USB_DEV_DSTS_SUSPSTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DSTS_SUSPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_SUSPSTS_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : enumspd
*
* Enumerated Speed (EnumSpd)
*
* Indicates the speed at which the DWC_otg core has come up
*
* after speed detection through a chirp sequence.
*
* 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
*
* 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
*
* 2'b10: Low speed (PHY clock is running at 6 MHz)
*
* 2'b11: Full speed (PHY clock is running at 48 MHz)
*
* Low speed is not supported For devices using a UTMI+ PHY.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 | 0x0 | High speed (PHY clock is running at 30 or 60
* : | | MHz)
* ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 | 0x1 | Full speed (PHY clock is running at 30 or 60
* : | | MHz)
* ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 | 0x2 | Low speed (PHY clock is running at 6 MHz)
* ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 | 0x3 | Full speed (PHY clock is running at 48 MHz)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
*
* High speed (PHY clock is running at 30 or 60 MHz)
*/
#define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
*
* Full speed (PHY clock is running at 30 or 60 MHz)
*/
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
*
* Low speed (PHY clock is running at 6 MHz)
*/
#define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD
*
* Full speed (PHY clock is running at 48 MHz)
*/
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_MSB 2
/* The width in bits of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
#define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK 0x00000006
/* The mask used to clear the ALT_USB_DEV_DSTS_ENUMSPD register field value. */
#define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK 0xfffffff9
/* The reset value of the ALT_USB_DEV_DSTS_ENUMSPD register field. */
#define ALT_USB_DEV_DSTS_ENUMSPD_RESET 0x1
/* Extracts the ALT_USB_DEV_DSTS_ENUMSPD field value from a register. */
#define ALT_USB_DEV_DSTS_ENUMSPD_GET(value) (((value) & 0x00000006) >> 1)
/* Produces a ALT_USB_DEV_DSTS_ENUMSPD register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_ENUMSPD_SET(value) (((value) << 1) & 0x00000006)
/*
* Field : errticerr
*
* Erratic Error (ErrticErr)
*
* The core sets this bit to report any erratic errors
*
* (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted For at
*
* least 2 ms, due to PHY error) seen on the UTMI+ .
*
* Due to erratic errors, the DWC_otg core goes into Suspended
*
* state and an interrupt is generated to the application with Early
*
* Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
*
* If the early suspend is asserted due to an erratic error, the
*
* application can only perform a soft disconnect recover.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------
* ALT_USB_DEV_DSTS_ERRTICERR_E_INACT | 0x0 | No Erratic Error
* ALT_USB_DEV_DSTS_ERRTICERR_E_ACT | 0x1 | Erratic Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
*
* No Erratic Error
*/
#define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR
*
* Erratic Error
*/
#define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_MSB 3
/* The width in bits of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
#define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DSTS_ERRTICERR register field value. */
#define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DSTS_ERRTICERR register field. */
#define ALT_USB_DEV_DSTS_ERRTICERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DSTS_ERRTICERR field value from a register. */
#define ALT_USB_DEV_DSTS_ERRTICERR_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DSTS_ERRTICERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_ERRTICERR_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : soffn
*
* Frame or Microframe Number of the Received SOF (SOFFN)
*
* When the core is operating at high speed, this field contains a
*
* microframe number. When the core is operating at full or low
*
* speed, this field contains a Frame number.
*
* Note: This register may return a non zero value if read immediately after power
* on reset.
*
* In case the register bit reads non zero immediately after power on reset it does
* not
*
* indicate that SOF has been received from the host. The read value of this
* interrupt is
*
* valid only after a valid connection between host and device is established.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_MSB 21
/* The width in bits of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_WIDTH 14
/* The mask used to set the ALT_USB_DEV_DSTS_SOFFN register field value. */
#define ALT_USB_DEV_DSTS_SOFFN_SET_MSK 0x003fff00
/* The mask used to clear the ALT_USB_DEV_DSTS_SOFFN register field value. */
#define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK 0xffc000ff
/* The reset value of the ALT_USB_DEV_DSTS_SOFFN register field. */
#define ALT_USB_DEV_DSTS_SOFFN_RESET 0x0
/* Extracts the ALT_USB_DEV_DSTS_SOFFN field value from a register. */
#define ALT_USB_DEV_DSTS_SOFFN_GET(value) (((value) & 0x003fff00) >> 8)
/* Produces a ALT_USB_DEV_DSTS_SOFFN register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_SOFFN_SET(value) (((value) << 8) & 0x003fff00)
/*
* Field : devlnsts
*
* Device Line Status (DevLnSts)
*
* Indicates the current logic level USB data lines
*
* DevLnSts[1]: Logic level of D+
*
* DevLnSts[0]: Logic level of D-
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_MSB 23
/* The width in bits of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DSTS_DEVLNSTS register field value. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_SET_MSK 0x00c00000
/* The mask used to clear the ALT_USB_DEV_DSTS_DEVLNSTS register field value. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_CLR_MSK 0xff3fffff
/* The reset value of the ALT_USB_DEV_DSTS_DEVLNSTS register field. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DSTS_DEVLNSTS field value from a register. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_GET(value) (((value) & 0x00c00000) >> 22)
/* Produces a ALT_USB_DEV_DSTS_DEVLNSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DSTS_DEVLNSTS_SET(value) (((value) << 22) & 0x00c00000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DSTS.
*/
struct ALT_USB_DEV_DSTS_s
{
const uint32_t suspsts : 1; /* ALT_USB_DEV_DSTS_SUSPSTS */
const uint32_t enumspd : 2; /* ALT_USB_DEV_DSTS_ENUMSPD */
const uint32_t errticerr : 1; /* ALT_USB_DEV_DSTS_ERRTICERR */
uint32_t : 4; /* *UNDEFINED* */
const uint32_t soffn : 14; /* ALT_USB_DEV_DSTS_SOFFN */
const uint32_t devlnsts : 2; /* ALT_USB_DEV_DSTS_DEVLNSTS */
uint32_t : 8; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DSTS. */
typedef volatile struct ALT_USB_DEV_DSTS_s ALT_USB_DEV_DSTS_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DSTS register. */
#define ALT_USB_DEV_DSTS_RESET 0x00000002
/* The byte offset of the ALT_USB_DEV_DSTS register from the beginning of the component. */
#define ALT_USB_DEV_DSTS_OFST 0x8
/* The address of the ALT_USB_DEV_DSTS register. */
#define ALT_USB_DEV_DSTS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST))
/*
* Register : diepmsk
*
* Device IN Endpoint Common Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_TMOMSK
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_BNAININTRMSK
* [12:10] | ??? | 0x0 | *UNDEFINED*
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPMSK_NAKMSK
* [31:14] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Interrupt Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------
* ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt
* ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
*
* Mask Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK
*
* No Mask Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbldmsk
*
* Endpoint Disabled Interrupt Mask (EPDisbldMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt
* ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
*
* Mask Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_EPDISBLDMSK
*
* No Mask Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_EPDISBLDMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error Mask (AHBErrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt
* ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
*
* Mask AHB Error Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_AHBERRMSK
*
* No Mask AHB Error Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_AHBERRMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPMSK_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeoutmsk
*
* Timeout Condition Mask (TimeOUTMsk)
*
* (Non-isochronous endpoints)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK | 0x0 | Mask Timeout Condition Interrupt
* ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK | 0x1 | No Mask Timeout Condition Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
*
* Mask Timeout Condition Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_TMOMSK
*
* No Mask Timeout Condition Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_TMOMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TMOMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPMSK_TMOMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_TMOMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPMSK_TMOMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_TMOMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfempmsk
*
* IN Token Received When TxFIFO Empty Mask
*
* (INTknTXFEmpMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------------------
* ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK | 0x0 | Mask IN Token Received When TxFIFO Empty
* : | | Interrupt
* ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK | 0x1 | No Mask IN Token Received When TxFIFO Empty
* : | | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
*
* Mask IN Token Received When TxFIFO Empty Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK
*
* No Mask IN Token Received When TxFIFO Empty Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmismsk
*
* IN Token received with EP Mismatch Mask (INTknEPMisMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK | 0x0 | Mask IN Token received with EP Mismatch
* : | | Interrupt
* ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK | 0x1 | No Mask IN Token received with EP Mismatch
* : | | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
*
* Mask IN Token received with EP Mismatch Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK
*
* No Mask IN Token received with EP Mismatch Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeffmsk
*
* IN Endpoint NAK Effective Mask (INEPNakEffMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:--------------------------------------------
* ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK | 0x0 | Mask IN Endpoint NAK Effective Interrupt
* ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK | 0x1 | No Mask IN Endpoint NAK Effective Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
*
* Mask IN Endpoint NAK Effective Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK
*
* No Mask IN Endpoint NAK Effective Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfifoundrnmsk
*
* Fifo Underrun Mask (TxfifoUndrnMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------
* ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK | 0x0 | Mask Fifo Underrun Interrupt
* ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK | 0x1 | No Mask Fifo Underrun Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
*
* Mask Fifo Underrun Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK
*
* No Mask Fifo Underrun Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnainintrmsk
*
* BNA interrupt Mask (BNAInIntrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------
* ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK | 0x0 | Mask BNA Interrupt
* ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
*
* Mask BNA Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_BNAININTRMSK
*
* No Mask BNA Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_BNAININTRMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPMSK_BNAININTRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_BNAININTRMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : nakmsk
*
* NAK interrupt Mask (NAKMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------
* ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt
* ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
*
* Mask NAK Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPMSK_NAKMSK
*
* No Mask NAK Interrupt
*/
#define ALT_USB_DEV_DIEPMSK_NAKMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPMSK_NAKMSK field value from a register. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPMSK_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPMSK.
*/
struct ALT_USB_DEV_DIEPMSK_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_DEV_DIEPMSK_XFERCOMPLMSK */
uint32_t epdisbldmsk : 1; /* ALT_USB_DEV_DIEPMSK_EPDISBLDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_DEV_DIEPMSK_AHBERRMSK */
uint32_t timeoutmsk : 1; /* ALT_USB_DEV_DIEPMSK_TMOMSK */
uint32_t intkntxfempmsk : 1; /* ALT_USB_DEV_DIEPMSK_INTKNTXFEMPMSK */
uint32_t intknepmismsk : 1; /* ALT_USB_DEV_DIEPMSK_INTKNEPMISMSK */
uint32_t inepnakeffmsk : 1; /* ALT_USB_DEV_DIEPMSK_INEPNAKEFFMSK */
uint32_t : 1; /* *UNDEFINED* */
uint32_t txfifoundrnmsk : 1; /* ALT_USB_DEV_DIEPMSK_TXFIFOUNDRNMSK */
uint32_t bnainintrmsk : 1; /* ALT_USB_DEV_DIEPMSK_BNAININTRMSK */
uint32_t : 3; /* *UNDEFINED* */
uint32_t nakmsk : 1; /* ALT_USB_DEV_DIEPMSK_NAKMSK */
uint32_t : 18; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPMSK. */
typedef volatile struct ALT_USB_DEV_DIEPMSK_s ALT_USB_DEV_DIEPMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPMSK register. */
#define ALT_USB_DEV_DIEPMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DIEPMSK_OFST 0x10
/* The address of the ALT_USB_DEV_DIEPMSK register. */
#define ALT_USB_DEV_DIEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPMSK_OFST))
/*
* Register : doepmsk
*
* Device OUT Endpoint Common Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_AHBERRMSK
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_SETUPMSK
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
* [11:10] | ??? | 0x0 | *UNDEFINED*
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_BBLEERRMSK
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_NAKMSK
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPMSK_NYETMSK
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercomplmsk
*
* Transfer Completed Interrupt Mask (XferComplMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------
* ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK | 0x0 | Mask Transfer Completed Interrupt
* ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK | 0x1 | No Mask Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
*
* Mask Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK
*
* No Mask Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbldmsk
*
* Endpoint Disabled Interrupt Mask (EPDisbldMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK | 0x0 | Mask Endpoint Disabled Interrupt
* ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK | 0x1 | No Mask Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
*
* Mask Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_EPDISBLDMSK
*
* No Mask Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_EPDISBLDMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPMSK_EPDISBLDMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_EPDISBLDMSK_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberrmsk
*
* AHB Error (AHBErrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK | 0x0 | Mask AHB Error Interrupt
* ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK | 0x1 | No Mask AHB Error Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
*
* Mask AHB Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_AHBERRMSK
*
* No Mask AHB Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPMSK_AHBERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_AHBERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPMSK_AHBERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_AHBERRMSK_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setupmsk
*
* SETUP Phase Done Mask (SetUPMsk)
*
* Applies to control endpoints only.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------------------
* ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK | 0x0 | Mask SETUP Phase Done Interrupt
* ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK | 0x1 | No Mask SETUP Phase Done Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
*
* Mask SETUP Phase Done Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_SETUPMSK
*
* No Mask SETUP Phase Done Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_SETUPMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPMSK_SETUPMSK register field. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_SETUPMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPMSK_SETUPMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_SETUPMSK_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdismsk
*
* OUT Token Received when Endpoint Disabled Mask
*
* (OUTTknEPdisMsk)
*
* Applies to control OUT endpoints only.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:-----------------------------------------------
* ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK | 0x0 | Mask OUT Token Received when Endpoint Disabled
* : | | Interrupt
* ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK | 0x1 | No Mask OUT Token Received when Endpoint
* : | | Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
*
* Mask OUT Token Received when Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK
*
* No Mask OUT Token Received when Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvdmsk
*
* Status Phase Received Mask
*
* (StsPhseRcvdMsk)
*
* Applies to control OUT endpoints only.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received Mask
*
* (Back2BackSETup)
*
* Applies to control OUT endpoints only.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------------------------------
* ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK | 0x0 | Mask Back-to-Back SETUP Packets Received
* : | | Interrupt
* ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK | 0x1 | No Mask Back-to-Back SETUP Packets Received
* : | | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
*
* Mask Back-to-Back SETUP Packets Received Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP
*
* No Mask Back-to-Back SETUP Packets Received Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterrmsk
*
* OUT Packet Error Mask (OutPktErrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-----------------------------------
* ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK | 0x0 | Mask OUT Packet Error Interrupt
* ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK | 0x1 | No Mask OUT Packet Error Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
*
* Mask OUT Packet Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK
*
* No Mask OUT Packet Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaoutintrmsk
*
* BNA interrupt Mask (BnaOutIntrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------
* ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK | 0x0 | Mask BNA Interrupt
* ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK | 0x1 | No Mask BNA Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
*
* Mask BNA Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK
*
* No Mask BNA Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : bbleerrmsk
*
* Babble Error interrupt Mask (BbleErrMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK | 0x0 | Mask Babble Error Interrupt
* ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK | 0x1 | No Mask Babble Error Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
*
* Mask Babble Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_BBLEERRMSK
*
* No Mask Babble Error Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_BBLEERRMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPMSK_BBLEERRMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_BBLEERRMSK_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakmsk
*
* NAK interrupt Mask (NAKMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------
* ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK | 0x0 | Mask NAK Interrupt
* ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK | 0x1 | No Mask NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
*
* Mask NAK Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_NAKMSK
*
* No Mask NAK Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_NAKMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NAKMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPMSK_NAKMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_NAKMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPMSK_NAKMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_NAKMSK_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetmsk
*
* NYET interrupt Mask (NYETMsk)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK | 0x0 | Mask NYET Interrupt
* ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK | 0x1 | No Mask NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
*
* Mask NYET Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPMSK_NYETMSK
*
* No Mask NYET Interrupt
*/
#define ALT_USB_DEV_DOEPMSK_NYETMSK_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPMSK_NYETMSK register field value. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPMSK_NYETMSK register field. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPMSK_NYETMSK field value from a register. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPMSK_NYETMSK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPMSK_NYETMSK_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPMSK.
*/
struct ALT_USB_DEV_DOEPMSK_s
{
uint32_t xfercomplmsk : 1; /* ALT_USB_DEV_DOEPMSK_XFERCOMPLMSK */
uint32_t epdisbldmsk : 1; /* ALT_USB_DEV_DOEPMSK_EPDISBLDMSK */
uint32_t ahberrmsk : 1; /* ALT_USB_DEV_DOEPMSK_AHBERRMSK */
uint32_t setupmsk : 1; /* ALT_USB_DEV_DOEPMSK_SETUPMSK */
uint32_t outtknepdismsk : 1; /* ALT_USB_DEV_DOEPMSK_OUTTKNEPDISMSK */
uint32_t stsphsercvdmsk : 1; /* ALT_USB_DEV_DOEPMSK_STSPHSERCVDMSK */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPMSK_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterrmsk : 1; /* ALT_USB_DEV_DOEPMSK_OUTPKTERRMSK */
uint32_t bnaoutintrmsk : 1; /* ALT_USB_DEV_DOEPMSK_BNAOUTINTRMSK */
uint32_t : 2; /* *UNDEFINED* */
uint32_t bbleerrmsk : 1; /* ALT_USB_DEV_DOEPMSK_BBLEERRMSK */
uint32_t nakmsk : 1; /* ALT_USB_DEV_DOEPMSK_NAKMSK */
uint32_t nyetmsk : 1; /* ALT_USB_DEV_DOEPMSK_NYETMSK */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPMSK. */
typedef volatile struct ALT_USB_DEV_DOEPMSK_s ALT_USB_DEV_DOEPMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPMSK register. */
#define ALT_USB_DEV_DOEPMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DOEPMSK_OFST 0x14
/* The address of the ALT_USB_DEV_DOEPMSK register. */
#define ALT_USB_DEV_DOEPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPMSK_OFST))
/*
* Register : daint
*
* Device All Endpoints Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-----|:-------|:------|:-----------------------------
* [0] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT0
* [1] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT1
* [2] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT2
* [3] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT3
* [4] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT4
* [5] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT5
* [6] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT6
* [7] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT7
* [8] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT8
* [9] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT9
* [10] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT10
* [11] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT11
* [12] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT12
* [13] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT13
* [14] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT14
* [15] | R | 0x0 | ALT_USB_DEV_DAINT_INEPINT15
* [16] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT0
* [17] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT1
* [18] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT2
* [19] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT3
* [20] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT4
* [21] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT5
* [22] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT6
* [23] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT7
* [24] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT8
* [25] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT9
* [26] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT10
* [27] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT11
* [28] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT12
* [29] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT13
* [30] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT14
* [31] | R | 0x0 | ALT_USB_DEV_DAINT_OUTEPINT15
*
*/
/*
* Field : inepint0
*
* IN Endpoint 0 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT0_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT0_E_ACT | 0x1 | IN Endpoint 0 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT0_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT0
*
* IN Endpoint 0 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT0_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_MSB 0
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT0_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT0_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT0 register field. */
#define ALT_USB_DEV_DAINT_INEPINT0_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT0 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DAINT_INEPINT0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT0_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : inepint1
*
* IN Endpoint 1 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT1_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT1_E_ACT | 0x1 | IN Endpoint 1 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT1_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT1
*
* IN Endpoint 1 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT1_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_MSB 1
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT1_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT1_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT1 register field. */
#define ALT_USB_DEV_DAINT_INEPINT1_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT1 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DAINT_INEPINT1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT1_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : inepint2
*
* IN Endpoint 2 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT2_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT2_E_ACT | 0x1 | IN Endpoint 2 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT2_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT2
*
* IN Endpoint 2 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT2_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_MSB 2
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT2_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT2_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT2 register field. */
#define ALT_USB_DEV_DAINT_INEPINT2_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT2 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DAINT_INEPINT2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT2_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : inepint3
*
* IN Endpoint 3 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT3_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT3_E_ACT | 0x1 | IN Endpoint 3 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT3_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT3
*
* IN Endpoint 3 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT3_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_MSB 3
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT3_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT3_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT3 register field. */
#define ALT_USB_DEV_DAINT_INEPINT3_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT3 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DAINT_INEPINT3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT3_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : inepint4
*
* IN Endpoint 4 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT4_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT4_E_ACT | 0x1 | IN Endpoint 4 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT4_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT4
*
* IN Endpoint 4 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT4_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_MSB 4
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT4_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT4_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT4 register field. */
#define ALT_USB_DEV_DAINT_INEPINT4_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT4 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DAINT_INEPINT4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT4_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : inepint5
*
* IN Endpoint 5 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT5_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT5_E_ACT | 0x1 | IN Endpoint 5 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT5_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT5
*
* IN Endpoint 5 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT5_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_MSB 5
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT5_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT5_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT5 register field. */
#define ALT_USB_DEV_DAINT_INEPINT5_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT5 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DAINT_INEPINT5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT5_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepint6
*
* IN Endpoint 6 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT6_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT6_E_ACT | 0x1 | IN Endpoint 6 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT6_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT6
*
* IN Endpoint 6 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT6_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_MSB 6
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT6_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT6_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT6 register field. */
#define ALT_USB_DEV_DAINT_INEPINT6_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT6 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DAINT_INEPINT6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT6_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : inepint7
*
* IN Endpoint 7 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT7_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT7_E_ACT | 0x1 | IN Endpoint 7 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT7_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT7
*
* IN Endpoint 7 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT7_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_MSB 7
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT7_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT7_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT7 register field. */
#define ALT_USB_DEV_DAINT_INEPINT7_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT7 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DAINT_INEPINT7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT7_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : inepint8
*
* IN Endpoint 8 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT8_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT8_E_ACT | 0x1 | IN Endpoint 8 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT8_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT8
*
* IN Endpoint 8 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT8_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_MSB 8
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT8_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT8_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT8 register field. */
#define ALT_USB_DEV_DAINT_INEPINT8_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT8 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DAINT_INEPINT8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT8_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : inepint9
*
* IN Endpoint 9 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------------------
* ALT_USB_DEV_DAINT_INEPINT9_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT9_E_ACT | 0x1 | IN Endpoint 9 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT9_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT9
*
* IN Endpoint 9 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT9_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_MSB 9
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT9_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT9_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT9 register field. */
#define ALT_USB_DEV_DAINT_INEPINT9_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT9 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DAINT_INEPINT9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT9_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : inepint10
*
* IN Endpoint 10 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT10_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT10_E_ACT | 0x1 | IN Endpoint 10 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT10_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT10
*
* IN Endpoint 10 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT10_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_MSB 10
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT10_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT10_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT10 register field. */
#define ALT_USB_DEV_DAINT_INEPINT10_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT10 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DAINT_INEPINT10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT10_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : inepint11
*
* IN Endpoint 11 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT11_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT11_E_ACT | 0x1 | IN Endpoint 11 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT11_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT11
*
* IN Endpoint 11 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT11_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_MSB 11
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT11_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT11_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT11 register field. */
#define ALT_USB_DEV_DAINT_INEPINT11_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT11 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DAINT_INEPINT11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT11_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : inepint12
*
* IN Endpoint 12 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT12_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT12_E_ACT | 0x1 | IN Endpoint 12 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT12_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT12
*
* IN Endpoint 12 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT12_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_MSB 12
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT12_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT12_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT12 register field. */
#define ALT_USB_DEV_DAINT_INEPINT12_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT12 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DAINT_INEPINT12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT12_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : inepint13
*
* IN Endpoint 13 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT13_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT13_E_ACT | 0x1 | IN Endpoint 13 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT13_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT13
*
* IN Endpoint 13 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT13_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_MSB 13
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT13_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT13_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT13 register field. */
#define ALT_USB_DEV_DAINT_INEPINT13_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT13 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DAINT_INEPINT13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT13_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : inepint14
*
* IN Endpoint 14 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT14_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT14_E_ACT | 0x1 | IN Endpoint 14 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT14_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT14
*
* IN Endpoint 14 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT14_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_MSB 14
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT14_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT14_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT14 register field. */
#define ALT_USB_DEV_DAINT_INEPINT14_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT14 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DAINT_INEPINT14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT14_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : inepint15
*
* IN Endpoint 15 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_INEPINT15_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_INEPINT15_E_ACT | 0x1 | IN Endpoint 15 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT15_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_INEPINT15
*
* IN Endpoint 15 Interrupt
*/
#define ALT_USB_DEV_DAINT_INEPINT15_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_MSB 15
/* The width in bits of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT15_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DAINT_INEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_INEPINT15_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DAINT_INEPINT15 register field. */
#define ALT_USB_DEV_DAINT_INEPINT15_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_INEPINT15 field value from a register. */
#define ALT_USB_DEV_DAINT_INEPINT15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DAINT_INEPINT15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_INEPINT15_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : outepint0
*
* OUT Endpoint 0 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT | 0x1 | OUT Endpoint 0 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT0_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT0
*
* OUT Endpoint 0 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT0_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_MSB 16
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT0 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT0 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT0 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT0_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : outepint1
*
* OUT Endpoint 1 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT | 0x1 | OUT Endpoint 1 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT1_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT1
*
* OUT Endpoint 1 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT1_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_MSB 17
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT1 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT1 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT1 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT1_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : outepint2
*
* OUT Endpoint 2 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT | 0x1 | OUT Endpoint 2 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT2_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT2
*
* OUT Endpoint 2 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT2_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_MSB 18
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT2 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT2 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT2 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT2_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : outepint3
*
* OUT Endpoint 3 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT | 0x1 | OUT Endpoint 3 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT3_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT3
*
* OUT Endpoint 3 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT3_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_MSB 19
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT3 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT3 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT3 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT3_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : outepint4
*
* OUT Endpoint 4 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT | 0x1 | OUT Endpoint 4 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT4_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT4
*
* OUT Endpoint 4 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT4_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_MSB 20
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT4 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT4 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT4 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT4_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : outepint5
*
* OUT Endpoint 5 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT | 0x1 | OUT Endpoint 5 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT5_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT5
*
* OUT Endpoint 5 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT5_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_MSB 21
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT5 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT5 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT5 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT5_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : outepint6
*
* OUT Endpoint 6 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT | 0x1 | OUT Endpoint 6 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT6_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT6
*
* OUT Endpoint 6 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT6_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_MSB 22
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT6 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT6 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT6 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT6_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : outepint7
*
* OUT Endpoint 7 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT | 0x1 | OUT Endpoint 7 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT7_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT7
*
* OUT Endpoint 7 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT7_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_MSB 23
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT7 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT7 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT7 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT7_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : outepint8
*
* OUT Endpoint 8 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT | 0x1 | OUT Endpoint 8 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT8_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT8
*
* OUT Endpoint 8 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT8_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_MSB 24
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT8 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT8 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT8 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT8_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : outepint9
*
* OUT Endpoint 9 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT | 0x1 | OUT Endpoint 9 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT9_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT9
*
* OUT Endpoint 9 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT9_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_MSB 25
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT9 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT9 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT9 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT9_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : outepint10
*
* OUT Endpoint 10 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT | 0x1 | OUT Endpoint 10 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT10_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT10
*
* OUT Endpoint 10 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT10_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_MSB 26
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT10 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT10 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT10 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT10_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : outepint11
*
* OUT Endpoint 11 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT | 0x1 | OUT Endpoint 11 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT11_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT11
*
* OUT Endpoint 11 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT11_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_MSB 27
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT11 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT11 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT11 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT11_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : outepint12
*
* OUT Endpoint 12 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT | 0x1 | OUT Endpoint 12 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT12_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT12
*
* OUT Endpoint 12 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT12_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_MSB 28
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT12 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT12 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT12 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT12_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : outepint13
*
* OUT Endpoint 13 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT | 0x1 | OUT Endpoint 13 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT13_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT13
*
* OUT Endpoint 13 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT13_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_MSB 29
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT13 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT13 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT13 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT13_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : outepint14
*
* OUT Endpoint 14 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT | 0x1 | OUT Endpoint 14 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT14_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT14
*
* OUT Endpoint 14 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT14_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_MSB 30
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT14 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT14 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT14 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT14_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : outepint15
*
* OUT Endpoint 15 Interrupt Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------------
* ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT | 0x1 | OUT Endpoint 15 Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
*
* No Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT15_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINT_OUTEPINT15
*
* OUT Endpoint 15 Interrupt
*/
#define ALT_USB_DEV_DAINT_OUTEPINT15_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_MSB 31
/* The width in bits of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DAINT_OUTEPINT15 register field value. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DAINT_OUTEPINT15 register field. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINT_OUTEPINT15 field value from a register. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DAINT_OUTEPINT15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINT_OUTEPINT15_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DAINT.
*/
struct ALT_USB_DEV_DAINT_s
{
const uint32_t inepint0 : 1; /* ALT_USB_DEV_DAINT_INEPINT0 */
const uint32_t inepint1 : 1; /* ALT_USB_DEV_DAINT_INEPINT1 */
const uint32_t inepint2 : 1; /* ALT_USB_DEV_DAINT_INEPINT2 */
const uint32_t inepint3 : 1; /* ALT_USB_DEV_DAINT_INEPINT3 */
const uint32_t inepint4 : 1; /* ALT_USB_DEV_DAINT_INEPINT4 */
const uint32_t inepint5 : 1; /* ALT_USB_DEV_DAINT_INEPINT5 */
const uint32_t inepint6 : 1; /* ALT_USB_DEV_DAINT_INEPINT6 */
const uint32_t inepint7 : 1; /* ALT_USB_DEV_DAINT_INEPINT7 */
const uint32_t inepint8 : 1; /* ALT_USB_DEV_DAINT_INEPINT8 */
const uint32_t inepint9 : 1; /* ALT_USB_DEV_DAINT_INEPINT9 */
const uint32_t inepint10 : 1; /* ALT_USB_DEV_DAINT_INEPINT10 */
const uint32_t inepint11 : 1; /* ALT_USB_DEV_DAINT_INEPINT11 */
const uint32_t inepint12 : 1; /* ALT_USB_DEV_DAINT_INEPINT12 */
const uint32_t inepint13 : 1; /* ALT_USB_DEV_DAINT_INEPINT13 */
const uint32_t inepint14 : 1; /* ALT_USB_DEV_DAINT_INEPINT14 */
const uint32_t inepint15 : 1; /* ALT_USB_DEV_DAINT_INEPINT15 */
const uint32_t outepint0 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT0 */
const uint32_t outepint1 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT1 */
const uint32_t outepint2 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT2 */
const uint32_t outepint3 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT3 */
const uint32_t outepint4 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT4 */
const uint32_t outepint5 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT5 */
const uint32_t outepint6 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT6 */
const uint32_t outepint7 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT7 */
const uint32_t outepint8 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT8 */
const uint32_t outepint9 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT9 */
const uint32_t outepint10 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT10 */
const uint32_t outepint11 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT11 */
const uint32_t outepint12 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT12 */
const uint32_t outepint13 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT13 */
const uint32_t outepint14 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT14 */
const uint32_t outepint15 : 1; /* ALT_USB_DEV_DAINT_OUTEPINT15 */
};
/* The typedef declaration for register ALT_USB_DEV_DAINT. */
typedef volatile struct ALT_USB_DEV_DAINT_s ALT_USB_DEV_DAINT_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DAINT register. */
#define ALT_USB_DEV_DAINT_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DAINT register from the beginning of the component. */
#define ALT_USB_DEV_DAINT_OFST 0x18
/* The address of the ALT_USB_DEV_DAINT register. */
#define ALT_USB_DEV_DAINT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINT_OFST))
/*
* Register : daintmsk
*
* Device All Endpoints Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-----|:-------|:------|:--------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK0
* [1] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK1
* [2] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK2
* [3] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK3
* [4] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK4
* [5] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK5
* [6] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK6
* [7] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK7
* [8] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK8
* [9] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK9
* [10] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK10
* [11] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK11
* [12] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK12
* [13] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK13
* [14] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK14
* [15] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_INEPMSK15
* [16] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK0
* [17] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK1
* [18] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK2
* [19] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK3
* [20] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK4
* [21] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK5
* [22] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK6
* [23] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK7
* [24] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK8
* [25] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK9
* [26] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK10
* [27] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK11
* [28] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK12
* [29] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK13
* [30] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK14
* [31] | RW | 0x0 | ALT_USB_DEV_DAINTMSK_OUTEPMSK15
*
*/
/*
* Field : inepmsk0
*
* IN Endpoint 0 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
*
* IN Endpoint 0 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK0
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_MSB 0
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK0 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK0_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : inepmsk1
*
* IN Endpoint 1 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK | 0x0 | IN Endpoint 1 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
*
* IN Endpoint 1 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK1
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_MSB 1
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK1 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK1_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : inepmsk2
*
* IN Endpoint 2 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK | 0x0 | IN Endpoint 2 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
*
* IN Endpoint 2 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK2
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_MSB 2
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK2 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK2_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : inepmsk3
*
* IN Endpoint 3 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK | 0x0 | IN Endpoint 3 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
*
* IN Endpoint 3 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK3
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_MSB 3
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK3 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK3_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : inepmsk4
*
* IN Endpoint 4 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK | 0x0 | IN Endpoint 4 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
*
* IN Endpoint 4 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK4
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_MSB 4
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK4 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK4_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : inepmsk5
*
* IN Endpoint 5 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK | 0x0 | IN Endpoint 5 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
*
* IN Endpoint 5 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK5
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_MSB 5
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK5 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK5_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepmsk6
*
* IN Endpoint 6 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK | 0x0 | IN Endpoint 6 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
*
* IN Endpoint 6 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK6
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_MSB 6
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK6 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK6_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : inepmsk7
*
* IN Endpoint 7 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK | 0x0 | IN Endpoint 7 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
*
* IN Endpoint 7 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK7
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_MSB 7
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK7 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK7_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : inepmsk8
*
* IN Endpoint 8 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK | 0x0 | IN Endpoint 8 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
*
* IN Endpoint 8 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK8
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_MSB 8
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK8 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK8_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : inepmsk9
*
* IN Endpoint 9 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK | 0x0 | IN Endpoint 0 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
*
* IN Endpoint 0 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK9
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_MSB 9
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK9 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK9_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : inepmsk10
*
* IN Endpoint 10 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK | 0x0 | IN Endpoint 10 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
*
* IN Endpoint 10 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK10
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_MSB 10
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK10 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK10_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : inepmsk11
*
* IN Endpoint 11 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK | 0x0 | IN Endpoint 11 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
*
* IN Endpoint 11 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK11
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_MSB 11
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK11 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK11_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : inepmsk12
*
* IN Endpoint 12 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK | 0x0 | IN Endpoint 12 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
*
* IN Endpoint 12 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK12
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_MSB 12
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK12 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK12_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : inepmsk13
*
* IN Endpoint 13 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK | 0x0 | IN Endpoint 13 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
*
* IN Endpoint 13 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK13
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_MSB 13
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK13 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK13_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : inepmsk14
*
* IN Endpoint 14 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK | 0x0 | IN Endpoint 14 Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
*
* IN Endpoint 14 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK14
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_MSB 14
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK14 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK14_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : inepmsk15
*
* IN Endpoint 15 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT | 0x0 | No Interrupt mask
* ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT | 0x1 | IN Endpoint 0 Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_INEPMSK15
*
* IN Endpoint 0 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_MSB 15
/* The width in bits of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DAINTMSK_INEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_INEPMSK15 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DAINTMSK_INEPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_INEPMSK15_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : outepmsk0
*
* OUT Endpoint 0 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK | 0x0 | OUT Endpoint 0 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
*
* OUT Endpoint 0 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK0
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_MSB 16
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK0 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK0_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : outepmsk1
*
* OUT Endpoint 1 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK | 0x0 | OUT Endpoint 1 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
*
* OUT Endpoint 1 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK1
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_MSB 17
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK1 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK1_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : outepmsk2
*
* OUT Endpoint 2 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK | 0x0 | OUT Endpoint 2 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
*
* OUT Endpoint 2 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK2
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_MSB 18
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET_MSK 0x00040000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_CLR_MSK 0xfffbffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK2 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK2_SET(value) (((value) << 18) & 0x00040000)
/*
* Field : outepmsk3
*
* OUT Endpoint 3 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK | 0x0 | OUT Endpoint 3 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
*
* OUT Endpoint 3 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK3
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_MSB 19
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK3 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK3_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : outepmsk4
*
* OUT Endpoint 4 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK | 0x0 | OUT Endpoint 4 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
*
* OUT Endpoint 4 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK4
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_MSB 20
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK4 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK4_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : outepmsk5
*
* OUT Endpoint 5 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK | 0x0 | OUT Endpoint 5 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
*
* OUT Endpoint 5 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK5
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_MSB 21
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK5 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK5_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : outepmsk6
*
* OUT Endpoint 6 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK | 0x0 | OUT Endpoint 6 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
*
* OUT Endpoint 6 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK6
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_MSB 22
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET_MSK 0x00400000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_CLR_MSK 0xffbfffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK6 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK6_SET(value) (((value) << 22) & 0x00400000)
/*
* Field : outepmsk7
*
* OUT Endpoint 7 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK | 0x0 | OUT Endpoint 7 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
*
* OUT Endpoint 7 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK7
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_LSB 23
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_MSB 23
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET_MSK 0x00800000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_CLR_MSK 0xff7fffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK7 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK7_SET(value) (((value) << 23) & 0x00800000)
/*
* Field : outepmsk8
*
* OUT Endpoint 8 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK | 0x0 | OUT Endpoint 8 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
*
* OUT Endpoint 8 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK8
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_LSB 24
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_MSB 24
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET_MSK 0x01000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_CLR_MSK 0xfeffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK8 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK8_SET(value) (((value) << 24) & 0x01000000)
/*
* Field : outepmsk9
*
* OUT Endpoint 9 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK | 0x0 | OUT Endpoint 9 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
*
* OUT Endpoint 9 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK9
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_LSB 25
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_MSB 25
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET_MSK 0x02000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_CLR_MSK 0xfdffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK9 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK9_SET(value) (((value) << 25) & 0x02000000)
/*
* Field : outepmsk10
*
* OUT Endpoint 10 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK | 0x0 | OUT Endpoint 10 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
*
* OUT Endpoint 10 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK10
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_MSB 26
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK10 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK10_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : outepmsk11
*
* OUT Endpoint 11 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK | 0x0 | OUT Endpoint 11 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
*
* OUT Endpoint 11 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK11
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_MSB 27
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK11 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK11_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : outepmsk12
*
* OUT Endpoint 12 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK | 0x0 | OUT Endpoint 12 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
*
* OUT Endpoint 12 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK12
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_MSB 28
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK12 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK12_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : outepmsk13
*
* OUT Endpoint 13 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK | 0x0 | OUT Endpoint 13 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
*
* OUT Endpoint 13 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK13
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_MSB 29
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK13 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK13_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : outepmsk14
*
* OUT Endpoint 14 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK | 0x0 | OUT Endpoint 14 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
*
* OUT Endpoint 14 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK14
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_MSB 30
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK14 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK14_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : outepmsk15
*
* OUT Endpoint 15 Interrupt mask Bit
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-------------------------------
* ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK | 0x0 | OUT Endpoint 15 Interrupt mask
* ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK | 0x1 | No Interrupt mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
*
* OUT Endpoint 15 Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DAINTMSK_OUTEPMSK15
*
* No Interrupt mask
*/
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_MSB 31
/* The width in bits of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_RESET 0x0
/* Extracts the ALT_USB_DEV_DAINTMSK_OUTEPMSK15 field value from a register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DAINTMSK_OUTEPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DAINTMSK_OUTEPMSK15_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DAINTMSK.
*/
struct ALT_USB_DEV_DAINTMSK_s
{
uint32_t inepmsk0 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK0 */
uint32_t inepmsk1 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK1 */
uint32_t inepmsk2 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK2 */
uint32_t inepmsk3 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK3 */
uint32_t inepmsk4 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK4 */
uint32_t inepmsk5 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK5 */
uint32_t inepmsk6 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK6 */
uint32_t inepmsk7 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK7 */
uint32_t inepmsk8 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK8 */
uint32_t inepmsk9 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK9 */
uint32_t inepmsk10 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK10 */
uint32_t inepmsk11 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK11 */
uint32_t inepmsk12 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK12 */
uint32_t inepmsk13 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK13 */
uint32_t inepmsk14 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK14 */
uint32_t inepmsk15 : 1; /* ALT_USB_DEV_DAINTMSK_INEPMSK15 */
uint32_t outepmsk0 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK0 */
uint32_t outepmsk1 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK1 */
uint32_t outepmsk2 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK2 */
uint32_t outepmsk3 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK3 */
uint32_t outepmsk4 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK4 */
uint32_t outepmsk5 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK5 */
uint32_t outepmsk6 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK6 */
uint32_t outepmsk7 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK7 */
uint32_t outepmsk8 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK8 */
uint32_t outepmsk9 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK9 */
uint32_t outepmsk10 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK10 */
uint32_t outepmsk11 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK11 */
uint32_t outepmsk12 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK12 */
uint32_t outepmsk13 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK13 */
uint32_t outepmsk14 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK14 */
uint32_t outepmsk15 : 1; /* ALT_USB_DEV_DAINTMSK_OUTEPMSK15 */
};
/* The typedef declaration for register ALT_USB_DEV_DAINTMSK. */
typedef volatile struct ALT_USB_DEV_DAINTMSK_s ALT_USB_DEV_DAINTMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DAINTMSK register. */
#define ALT_USB_DEV_DAINTMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DAINTMSK register from the beginning of the component. */
#define ALT_USB_DEV_DAINTMSK_OFST 0x1c
/* The address of the ALT_USB_DEV_DAINTMSK register. */
#define ALT_USB_DEV_DAINTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DAINTMSK_OFST))
/*
* Register : dvbusdis
*
* Device VBUS Discharge Time Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:------------------------------
* [15:0] | RW | 0x17d7 | ALT_USB_DEV_DVBUSDIS_DVBUSDIS
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : dvbusdis
*
* Device VBUS Discharge Time (DVBUSDis)
*
* Specifies the VBUS discharge time after VBUS pulsing during
*
* SRP. This value equals:
*
* VBUS discharge time in PHY clocks / 1, 024
*
* The value you use depends whether the PHY is operating at
*
* 30 MHz (16-bit data width) or 60 MHz (8-bit data width).
*
* Depending on your VBUS load, this value can need
*
* adjustment.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_MSB 15
/* The width in bits of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_RESET 0x17d7
/* Extracts the ALT_USB_DEV_DVBUSDIS_DVBUSDIS field value from a register. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DVBUSDIS_DVBUSDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DVBUSDIS_DVBUSDIS_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DVBUSDIS.
*/
struct ALT_USB_DEV_DVBUSDIS_s
{
uint32_t dvbusdis : 16; /* ALT_USB_DEV_DVBUSDIS_DVBUSDIS */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DVBUSDIS. */
typedef volatile struct ALT_USB_DEV_DVBUSDIS_s ALT_USB_DEV_DVBUSDIS_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DVBUSDIS register. */
#define ALT_USB_DEV_DVBUSDIS_RESET 0x000017d7
/* The byte offset of the ALT_USB_DEV_DVBUSDIS register from the beginning of the component. */
#define ALT_USB_DEV_DVBUSDIS_OFST 0x28
/* The address of the ALT_USB_DEV_DVBUSDIS register. */
#define ALT_USB_DEV_DVBUSDIS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSDIS_OFST))
/*
* Register : dvbuspulse
*
* Device VBUS Pulsing Time Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [11:0] | RW | 0x5b8 | ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE
* [31:12] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : dvbuspulse
*
* Device VBUS Pulsing Time (DVBUSPulse)
*
* Specifies the VBUS pulsing time during SRP. This value equals:
*
* VBUS pulsing time in PHY clocks / 1, 024
*
* The value you use depends whether the PHY is operating at 30
*
* MHz (16-bit data width) or 60 MHz (8-bit data width).
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_MSB 11
/* The width in bits of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_WIDTH 12
/* The mask used to set the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET_MSK 0x00000fff
/* The mask used to clear the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_CLR_MSK 0xfffff000
/* The reset value of the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_RESET 0x5b8
/* Extracts the ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE field value from a register. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_GET(value) (((value) & 0x00000fff) >> 0)
/* Produces a ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE register field value suitable for setting the register. */
#define ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE_SET(value) (((value) << 0) & 0x00000fff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DVBUSPULSE.
*/
struct ALT_USB_DEV_DVBUSPULSE_s
{
uint32_t dvbuspulse : 12; /* ALT_USB_DEV_DVBUSPULSE_DVBUSPULSE */
uint32_t : 20; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DVBUSPULSE. */
typedef volatile struct ALT_USB_DEV_DVBUSPULSE_s ALT_USB_DEV_DVBUSPULSE_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DVBUSPULSE register. */
#define ALT_USB_DEV_DVBUSPULSE_RESET 0x000005b8
/* The byte offset of the ALT_USB_DEV_DVBUSPULSE register from the beginning of the component. */
#define ALT_USB_DEV_DVBUSPULSE_OFST 0x2c
/* The address of the ALT_USB_DEV_DVBUSPULSE register. */
#define ALT_USB_DEV_DVBUSPULSE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DVBUSPULSE_OFST))
/*
* Register : dthrctl
*
* Device Threshold Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_NONISOTHREN
* [1] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_ISOTHREN
* [10:2] | RW | 0x8 | ALT_USB_DEV_DTHRCTL_TXTHRLEN
* [12:11] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
* [15:13] | ??? | 0x0 | *UNDEFINED*
* [16] | RW | 0x0 | ALT_USB_DEV_DTHRCTL_RXTHREN
* [25:17] | RW | 0x8 | ALT_USB_DEV_DTHRCTL_RXTHRLEN
* [26] | ??? | 0x1 | *UNDEFINED*
* [27] | RW | 0x1 | ALT_USB_DEV_DTHRCTL_ARBPRKEN
* [31:28] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : nonisothren
*
* Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)
*
* When this bit is Set, the core enables thresholding For Non Isochronous IN
*
* endpoints.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD | 0x0 | No thresholding
* ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END | 0x1 | Enable thresholding
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
*
* No thresholding
*/
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_NONISOTHREN
*
* Enable thresholding
*/
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_MSB 0
/* The width in bits of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DTHRCTL_NONISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_RESET 0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_NONISOTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DTHRCTL_NONISOTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_NONISOTHREN_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : isothren
*
* ISO IN Endpoints Threshold Enable. (ISOThrEn)
*
* When this bit is Set, the core enables thresholding For isochronous IN
*
* endpoints.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:---------------------
* ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD | 0x0 | No thresholding
* ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END | 0x1 | Enables thresholding
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
*
* No thresholding
*/
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_ISOTHREN
*
* Enables thresholding
*/
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_MSB 1
/* The width in bits of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ISOTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DTHRCTL_ISOTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_RESET 0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_ISOTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DTHRCTL_ISOTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_ISOTHREN_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : txthrlen
*
* Transmit Threshold Length (TxThrLen)
*
* This field specifies Transmit thresholding size in DWORDS. This also forms
*
* the MAC threshold and specifies the amount of data in bytes to be in the
*
* corresponding endpoint transmit FIFO, before the core can start transmit
*
* on the USB. The threshold length has to be at least eight DWORDS when the
*
* value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the
*
* application needs to ensure that the AHB Threshold value does not go below
*
* the recommended eight DWORD. This field controls both isochronous and
*
* non-isochronous IN endpoint thresholds. The recommended value for ThrLen
*
* is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_MSB 10
/* The width in bits of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_WIDTH 9
/* The mask used to set the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET_MSK 0x000007fc
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_CLR_MSK 0xfffff803
/* The reset value of the ALT_USB_DEV_DTHRCTL_TXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_RESET 0x8
/* Extracts the ALT_USB_DEV_DTHRCTL_TXTHRLEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_GET(value) (((value) & 0x000007fc) >> 2)
/* Produces a ALT_USB_DEV_DTHRCTL_TXTHRLEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_TXTHRLEN_SET(value) (((value) << 2) & 0x000007fc)
/*
* Field : ahbthrratio
*
* AHB Threshold Ratio (AHBThrRatio)
*
* These bits define the ratio between the AHB threshold and the MAC threshold for
* the
*
* transmit path only. The AHB threshold always remains less than or equal to the
* USB
*
* threshold, because this does not increase overhead. Both the AHB and the MAC
*
* threshold must be DWORD-aligned. The application needs to program TxThrLen and
* the
*
* AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold
*
* value is not DWORD aligned, the core might not behave correctly. When
* programming
*
* the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB
*
* threshold value does not go below 8 DWORDS to meet the USB turnaround time
*
* requirements.
*
* 2'b00: AHB threshold = MAC threshold
*
* 2'b01: AHB threshold = MAC threshold / 2
*
* 2'b10: AHB threshold = MAC threshold / 4
*
* 2'b11: AHB threshold = MAC threshold / 8
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------
* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO | 0x0 | AHB threshold = MAC threshold
* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE | 0x1 | AHB threshold = MAC threshold /2
* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO | 0x2 | AHB threshold = MAC threshold /4
* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE | 0x3 | AHB threshold = MAC threshold /
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
*
* AHB threshold = MAC threshold
*/
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESZERO 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
*
* AHB threshold = MAC threshold /2
*/
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
*
* AHB threshold = MAC threshold /4
*/
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_AHBTHRRATIO
*
* AHB threshold = MAC threshold /
*/
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_E_THRESTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_MSB 12
/* The width in bits of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET_MSK 0x00001800
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_CLR_MSK 0xffffe7ff
/* The reset value of the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_RESET 0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_AHBTHRRATIO field value from a register. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_GET(value) (((value) & 0x00001800) >> 11)
/* Produces a ALT_USB_DEV_DTHRCTL_AHBTHRRATIO register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_AHBTHRRATIO_SET(value) (((value) << 11) & 0x00001800)
/*
* Field : rxthren
*
* Receive Threshold Enable (RxThrEn)
*
* When this bit is Set, the core enables thresholding in the receive direction.
*
* Note: We recommends that you do not enable RxThrEn, because it may cause
*
* issues in the RxFIFO especially during error conditions such as RxError and
* Babble.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD | 0x0 | Disable thresholding
* ALT_USB_DEV_DTHRCTL_RXTHREN_E_END | 0x1 | Enable thresholding in the receive direction
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
*
* Disable thresholding
*/
#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_RXTHREN
*
* Enable thresholding in the receive direction
*/
#define ALT_USB_DEV_DTHRCTL_RXTHREN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_MSB 16
/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHREN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHREN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_RESET 0x0
/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHREN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DTHRCTL_RXTHREN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_RXTHREN_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : rxthrlen
*
* Receive Threshold Length (RxThrLen)
*
* This field specifies Receive thresholding size in DWORDS.
*
* This field also specifies the amount of data received on the USB before the
*
* core can start transmitting on the AHB.
*
* The threshold length has to be at least eight DWORDS.
*
* The recommended value For ThrLen is to be the same as the programmed
*
* AHB Burst Length (GAHBCFG.HBstLen).
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_MSB 25
/* The width in bits of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_WIDTH 9
/* The mask used to set the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET_MSK 0x03fe0000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_CLR_MSK 0xfc01ffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_RXTHRLEN register field. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_RESET 0x8
/* Extracts the ALT_USB_DEV_DTHRCTL_RXTHRLEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_GET(value) (((value) & 0x03fe0000) >> 17)
/* Produces a ALT_USB_DEV_DTHRCTL_RXTHRLEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_RXTHRLEN_SET(value) (((value) << 17) & 0x03fe0000)
/*
* Field : arbprken
*
* Arbiter Parking Enable (ArbPrkEn)
*
* This bit controls internal DMA arbiter parking For IN endpoints. When
*
* thresholding is enabled and this bit is Set to one, Then the arbiter parks on
* the
*
* IN endpoint For which there is a token received on the USB. This is done to
*
* avoid getting into underrun conditions. By Default the parking is enabled.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------------------------------
* ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD | 0x0 | Disable DMA arbiter parking
* ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END | 0x1 | Enable DMA arbiter parking for IN endpoints
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
*
* Disable DMA arbiter parking
*/
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DTHRCTL_ARBPRKEN
*
* Enable DMA arbiter parking for IN endpoints
*/
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_MSB 27
/* The width in bits of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DTHRCTL_ARBPRKEN register field. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_RESET 0x1
/* Extracts the ALT_USB_DEV_DTHRCTL_ARBPRKEN field value from a register. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DTHRCTL_ARBPRKEN register field value suitable for setting the register. */
#define ALT_USB_DEV_DTHRCTL_ARBPRKEN_SET(value) (((value) << 27) & 0x08000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTHRCTL.
*/
struct ALT_USB_DEV_DTHRCTL_s
{
uint32_t nonisothren : 1; /* ALT_USB_DEV_DTHRCTL_NONISOTHREN */
uint32_t isothren : 1; /* ALT_USB_DEV_DTHRCTL_ISOTHREN */
uint32_t txthrlen : 9; /* ALT_USB_DEV_DTHRCTL_TXTHRLEN */
uint32_t ahbthrratio : 2; /* ALT_USB_DEV_DTHRCTL_AHBTHRRATIO */
uint32_t : 3; /* *UNDEFINED* */
uint32_t rxthren : 1; /* ALT_USB_DEV_DTHRCTL_RXTHREN */
uint32_t rxthrlen : 9; /* ALT_USB_DEV_DTHRCTL_RXTHRLEN */
uint32_t : 1; /* *UNDEFINED* */
uint32_t arbprken : 1; /* ALT_USB_DEV_DTHRCTL_ARBPRKEN */
uint32_t : 4; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTHRCTL. */
typedef volatile struct ALT_USB_DEV_DTHRCTL_s ALT_USB_DEV_DTHRCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTHRCTL register. */
#define ALT_USB_DEV_DTHRCTL_RESET 0x0c100020
/* The byte offset of the ALT_USB_DEV_DTHRCTL register from the beginning of the component. */
#define ALT_USB_DEV_DTHRCTL_OFST 0x30
/* The address of the ALT_USB_DEV_DTHRCTL register. */
#define ALT_USB_DEV_DTHRCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTHRCTL_OFST))
/*
* Register : diepempmsk
*
* Device IN Endpoint FIFO Empty Interrupt Mask Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------------
* [0] | RW | 0x0 | IN EP 0 Tx FIFO Empty Interrupt Mask Bits
* [1] | RW | 0x0 | IN EP 1 Tx FIFO Empty Interrupt Mask Bits
* [2] | RW | 0x0 | IN EP 2 Tx FIFO Empty Interrupt Mask Bits
* [3] | RW | 0x0 | IN EP 3 Tx FIFO Empty Interrupt Mask Bits
* [4] | RW | 0x0 | IN EP 4 Tx FIFO Empty Interrupt Mask Bits
* [5] | RW | 0x0 | IN EP 5 Tx FIFO Empty Interrupt Mask Bits
* [6] | RW | 0x0 | IN EP 6 Tx FIFO Empty Interrupt Mask Bits
* [7] | RW | 0x0 | IN EP 7 Tx FIFO Empty Interrupt Mask Bits
* [8] | RW | 0x0 | IN EP 8 Tx FIFO Empty Interrupt Mask Bits
* [9] | RW | 0x0 | IN EP 9 Tx FIFO Empty Interrupt Mask Bits
* [10] | RW | 0x0 | IN EP 10 Tx FIFO Empty Interrupt Mask Bits
* [11] | RW | 0x0 | IN EP 11 Tx FIFO Empty Interrupt Mask Bits
* [12] | RW | 0x0 | IN EP 12 Tx FIFO Empty Interrupt Mask Bits
* [13] | RW | 0x0 | IN EP 13 Tx FIFO Empty Interrupt Mask Bits
* [14] | RW | 0x0 | IN EP 14 Tx FIFO Empty Interrupt Mask Bits
* [15] | RW | 0x0 | IN EP 15 Tx FIFO Empty Interrupt Mask Bits
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : IN EP 0 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk0
*
* This bit acts as mask bits for DIEPINT0.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK | 0x0 | Mask End point 0 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
*
* Mask End point 0 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK0_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : IN EP 1 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk1
*
* This bit acts as mask bits for DIEPINT1.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK | 0x0 | Mask End point 1 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
*
* Mask End point 1 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK1_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : IN EP 2 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk2
*
* This bit acts as mask bits for DIEPINT2.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK | 0x0 | Mask End point 2 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
*
* Mask End point 2 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK2_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : IN EP 3 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk3
*
* This bit acts as mask bits for DIEPINT3.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK | 0x0 | Mask End point 3 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
*
* Mask End point 3 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK3_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : IN EP 4 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk4
*
* This bit acts as mask bits for DIEPINT4.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK | 0x0 | Mask End point 4 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
*
* Mask End point 4 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK4_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : IN EP 5 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk5
*
* This bit acts as mask bits for DIEPINT5.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK | 0x0 | Mask End point 5 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
*
* Mask End point 5 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK5_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : IN EP 6 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk6
*
* This bit acts as mask bits for DIEPINT6.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK | 0x0 | Mask End point 6 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
*
* Mask End point 6 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK6_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : IN EP 7 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk7
*
* This bit acts as mask bits for DIEPINT7.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK | 0x0 | Mask End point 7 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
*
* Mask End point 7 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK7_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : IN EP 8 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk8
*
* This bit acts as mask bits for DIEPINT8.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK | 0x0 | Mask End point 8 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
*
* Mask End point 8 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK8_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : IN EP 9 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk9
*
* This bit acts as mask bits for DIEPINT9.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------------|:------|:---------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK | 0x0 | Mask End point 9 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
*
* Mask End point 9 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK9_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : IN EP 10 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk10
*
* This bit acts as mask bits for DIEPINT10.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK | 0x0 | Mask End point 10 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
*
* Mask End point 10 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_LSB 10
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET_MSK 0x00000400
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_CLR_MSK 0xfffffbff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK10_SET(value) (((value) << 10) & 0x00000400)
/*
* Field : IN EP 11 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk11
*
* This bit acts as mask bits for DIEPINT11.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK | 0x0 | Mask End point 11 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
*
* Mask End point 11 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK11_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : IN EP 12 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk12
*
* This bit acts as mask bits for DIEPINT12.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK | 0x0 | Mask End point 12 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
*
* Mask End point 12 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK12_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : IN EP 13 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk13
*
* This bit acts as mask bits for DIEPINT13.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK | 0x0 | Mask End point 12 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
*
* Mask End point 12 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK13_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : IN EP 14 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk14
*
* This bit acts as mask bits for DIEPINT14.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK | 0x0 | Mask End point 14 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
*
* Mask End point 14 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK14_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : IN EP 15 Tx FIFO Empty Interrupt Mask Bits - ineptxfempmsk15
*
* This bit acts as mask bits for DIEPINT15.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK | 0x0 | Mask End point 15 interrupt
* ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK | 0x1 | No mask
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
*
* Mask End point 15 interrupt
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_MSK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15
*
* No mask
*/
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_E_NOMSK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 field value from a register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPEMPMSK_INEPTXFEMPMSK15_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPEMPMSK.
*/
struct ALT_USB_DEV_DIEPEMPMSK_s
{
uint32_t ineptxfempmsk0 : 1; /* IN EP 0 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk1 : 1; /* IN EP 1 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk2 : 1; /* IN EP 2 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk3 : 1; /* IN EP 3 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk4 : 1; /* IN EP 4 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk5 : 1; /* IN EP 5 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk6 : 1; /* IN EP 6 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk7 : 1; /* IN EP 7 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk8 : 1; /* IN EP 8 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk9 : 1; /* IN EP 9 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk10 : 1; /* IN EP 10 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk11 : 1; /* IN EP 11 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk12 : 1; /* IN EP 12 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk13 : 1; /* IN EP 13 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk14 : 1; /* IN EP 14 Tx FIFO Empty Interrupt Mask Bits */
uint32_t ineptxfempmsk15 : 1; /* IN EP 15 Tx FIFO Empty Interrupt Mask Bits */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPEMPMSK. */
typedef volatile struct ALT_USB_DEV_DIEPEMPMSK_s ALT_USB_DEV_DIEPEMPMSK_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPEMPMSK register. */
#define ALT_USB_DEV_DIEPEMPMSK_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPEMPMSK register from the beginning of the component. */
#define ALT_USB_DEV_DIEPEMPMSK_OFST 0x34
/* The address of the ALT_USB_DEV_DIEPEMPMSK register. */
#define ALT_USB_DEV_DIEPEMPMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPEMPMSK_OFST))
/*
* Register : diepctl0
*
* Device Control IN Endpoint 0 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [1:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL0_MPS
* [14:2] | ??? | 0x0 | *UNDEFINED*
* [15] | R | 0x1 | ALT_USB_DEV_DIEPCTL0_USBACTEP
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL0_NAKSTS
* [19:18] | R | 0x0 | ALT_USB_DEV_DIEPCTL0_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL0_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL0_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL0_SNAK
* [29:28] | ??? | 0x0 | *UNDEFINED*
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL0_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* Applies to IN and OUT endpoints.
*
* The application must program this field with the maximum packet size For
*
* the current logical endpoint.
*
* 2'b00: 64 bytes
*
* 2'b01: 32 bytes
*
* 2'b10: 16 bytes
*
* 2'b11: 8 bytes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 | 0x0 | 64 bytes
* ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 | 0x1 | 32 bytes
* ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 | 0x2 | 16 bytes
* ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 | 0x3 | 8 bytes
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
*
* 64 bytes
*/
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES64 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
*
* 32 bytes
*/
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES32 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
*
* 16 bytes
*/
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES16 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_MPS
*
* 8 bytes
*/
#define ALT_USB_DEV_DIEPCTL0_MPS_E_BYTES8 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL0_MPS_SET_MSK 0x00000003
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL0_MPS_CLR_MSK 0xfffffffc
/* The reset value of the ALT_USB_DEV_DIEPCTL0_MPS register field. */
#define ALT_USB_DEV_DIEPCTL0_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL0_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* This bit is always SET to 1, indicating that control endpoint 0 is always
*
* active in all configurations and interfaces.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------------
* ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 | 0x1 | Control endpoint is always active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_USBACTEP
*
* Control endpoint is always active
*/
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_E_ACT0 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPCTL0_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL0_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the
*
* FIFO status
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When this bit is Set, either by the application or core, the core stops
*
* transmitting data, even If there is data available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
*
* packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL0_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Hardcoded to 00 For control.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPTYPE
*
* Endpoint Control 0
*/
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_E_ACT 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* The application can only Set this bit, and the core clears it, when a
*
* SETUP token is received For this endpoint. If a NAK bit, Global Nonperiodic
*
* IN NAK, or Global OUT NAK is Set along with this bit, the STALL
*
* bit takes priority.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_DEV_DIEPCTL0_STALL_E_INACT | 0x0 | No Stall
* ALT_USB_DEV_DIEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
*
* No Stall
*/
#define ALT_USB_DEV_DIEPCTL0_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_STALL
*
* Stall Handshake
*/
#define ALT_USB_DEV_DIEPCTL0_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL0_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL0_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_STALL register field. */
#define ALT_USB_DEV_DIEPCTL0_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL0_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* For Shared FIFO operation, this value is always Set to 0, indicating
*
* that control IN endpoint 0 data is always written in the Non-Periodic
*
* Transmit FIFO.
*
* For Dedicated FIFO operation, this value is Set to the FIFO number
*
* that is assigned to IN Endpoint 0.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL0_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR | 0x0 | No action
* ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
*
* No action
*/
#define ALT_USB_DEV_DIEPCTL0_CNAK_E_NOCLR 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL0_CNAK_E_CLR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL0_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET | 0x0 | No action
* ALT_USB_DEV_DIEPCTL0_SNAK_E_SET | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
*
* No action
*/
#define ALT_USB_DEV_DIEPCTL0_SNAK_E_NOSET 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL0_SNAK_E_SET 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL0_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* The application sets this bit to stop transmitting data on an endpoint,
*
* even before the transfer For that endpoint is complete. The application
*
* must wait For the Endpoint Disabled interrupt before treating the endpoint
*
* as disabled. The core clears this bit before setting the Endpoint Disabled
*
* Interrupt. The application must Set this bit only If Endpoint Enable is
*
* already Set For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------------
* ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT | 0x0 | No action
* ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT | 0x1 | Stop transmitting data on endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
*
* No action
*/
#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPDIS
*
* Stop transmitting data on endpoint
*/
#define ALT_USB_DEV_DIEPCTL0_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* When Scatter/Gather DMA mode is enabled, For IN endpoints this bit
*
* indicates that the descriptor structure and data buffer with data ready
*
* to transmit is setup.
*
* When Scatter/Gather DMA mode is disabled such as in buffer pointer
*
* based DMA mode this bit indicates that data is ready to be
*
* transmitted on the endpoint.
*
* The core clears this bit before setting the following interrupts on this
*
* endpoint:
*
* Endpoint Disabled
*
* Transfer Completed
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------
* ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT | 0x0 | No action
* ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
*
* No action
*/
#define ALT_USB_DEV_DIEPCTL0_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL0_EPENA
*
* Endpoint Enabled
*/
#define ALT_USB_DEV_DIEPCTL0_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL0_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL0_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL0.
*/
struct ALT_USB_DEV_DIEPCTL0_s
{
uint32_t mps : 2; /* ALT_USB_DEV_DIEPCTL0_MPS */
uint32_t : 13; /* *UNDEFINED* */
const uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL0_USBACTEP */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL0_NAKSTS */
const uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL0_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL0_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL0_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL0_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL0_SNAK */
uint32_t : 2; /* *UNDEFINED* */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL0_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL0_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL0. */
typedef volatile struct ALT_USB_DEV_DIEPCTL0_s ALT_USB_DEV_DIEPCTL0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL0 register. */
#define ALT_USB_DEV_DIEPCTL0_RESET 0x00008000
/* The byte offset of the ALT_USB_DEV_DIEPCTL0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL0_OFST 0x100
/* The address of the ALT_USB_DEV_DIEPCTL0 register. */
#define ALT_USB_DEV_DIEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL0_OFST))
/*
* Register : diepint0
*
* Device IN Endpoint 0 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT0_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT0_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT0_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT0_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT0_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT0_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TMO register field value. */
#define ALT_USB_DEV_DIEPINT0_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TMO register field value. */
#define ALT_USB_DEV_DIEPINT0_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT0_TMO register field. */
#define ALT_USB_DEV_DIEPINT0_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT0_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT0_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT0_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT0_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT0_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT0_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT0_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* The core generates this interrupt when it detects a transmit FIFO
*
* underrun condition in threshold mode For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT0_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT0_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT0_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT0_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT0_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT0_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT0_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT0_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT0.
*/
struct ALT_USB_DEV_DIEPINT0_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT0_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT0_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT0_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT0_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT0_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT0_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT0_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT0_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT0_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT0_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT0_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT0_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT0_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT0_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT0. */
typedef volatile struct ALT_USB_DEV_DIEPINT0_s ALT_USB_DEV_DIEPINT0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT0 register. */
#define ALT_USB_DEV_DIEPINT0_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT0_OFST 0x108
/* The address of the ALT_USB_DEV_DIEPINT0 register. */
#define ALT_USB_DEV_DIEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT0_OFST))
/*
* Register : dieptsiz0
*
* Device IN Endpoint 0 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ0_XFERSIZE
* [18:7] | ??? | 0x0 | *UNDEFINED*
* [20:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ0_PKTCNT
* [31:21] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* This field contains the transfer size in bytes for the current endpoint. The
* transfer size
*
* (XferSize) = Sum of buffer sizes across all descriptors in the list for the
* endpoint.
*
* In Buffer DMA, the core only interrupts the application after it has exhausted
* the transfer
*
* size amount of data. The transfer size can be set to the maximum packet size of
* the
*
* endpoint, to be interrupted at the end of each packet.
*
* IN Endpoints: The core decrements this field every time a packet from the
* external
*
* memory is written to the TxFIFO.
*
* OUT Endpoints: The core decrements this field every time a packet is read from
* the
*
* RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_WIDTH 7
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* In Endpoints : This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* OUT Endpoints: This field is decremented every time a packet (maximum size or
*
* short packet) is written to the RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_MSB 20
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET_MSK 0x00180000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_CLR_MSK 0xffe7ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00180000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00180000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ0.
*/
struct ALT_USB_DEV_DIEPTSIZ0_s
{
uint32_t xfersize : 7; /* ALT_USB_DEV_DIEPTSIZ0_XFERSIZE */
uint32_t : 12; /* *UNDEFINED* */
uint32_t pktcnt : 2; /* ALT_USB_DEV_DIEPTSIZ0_PKTCNT */
uint32_t : 11; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ0. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ0_s ALT_USB_DEV_DIEPTSIZ0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ0 register. */
#define ALT_USB_DEV_DIEPTSIZ0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ0_OFST 0x110
/* The address of the ALT_USB_DEV_DIEPTSIZ0 register. */
#define ALT_USB_DEV_DIEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ0_OFST))
/*
* Register : diepdma0
*
* Device IN Endpoint 0 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA0_DIEPDMA0
*
*/
/*
* Field : diepdma0
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA0_DIEPDMA0 field value from a register. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA0_DIEPDMA0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA0_DIEPDMA0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA0.
*/
struct ALT_USB_DEV_DIEPDMA0_s
{
uint32_t diepdma0 : 32; /* ALT_USB_DEV_DIEPDMA0_DIEPDMA0 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA0. */
typedef volatile struct ALT_USB_DEV_DIEPDMA0_s ALT_USB_DEV_DIEPDMA0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA0 register. */
#define ALT_USB_DEV_DIEPDMA0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA0_OFST 0x114
/* The address of the ALT_USB_DEV_DIEPDMA0 register. */
#define ALT_USB_DEV_DIEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA0_OFST))
/*
* Register : dtxfsts0
*
* Device IN Endpoint Transmit FIFO Status Register 0
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS0.
*/
struct ALT_USB_DEV_DTXFSTS0_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS0_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS0. */
typedef volatile struct ALT_USB_DEV_DTXFSTS0_s ALT_USB_DEV_DTXFSTS0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS0 register. */
#define ALT_USB_DEV_DTXFSTS0_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS0 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS0_OFST 0x118
/* The address of the ALT_USB_DEV_DTXFSTS0 register. */
#define ALT_USB_DEV_DTXFSTS0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS0_OFST))
/*
* Register : diepdmab0
*
* Device IN Endpoint 16 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0
*
*/
/*
* Field : diepdmab0
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB0.
*/
struct ALT_USB_DEV_DIEPDMAB0_s
{
const uint32_t diepdmab0 : 32; /* ALT_USB_DEV_DIEPDMAB0_DIEPDMAB0 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB0. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB0_s ALT_USB_DEV_DIEPDMAB0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB0 register. */
#define ALT_USB_DEV_DIEPDMAB0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB0 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB0_OFST 0x11c
/* The address of the ALT_USB_DEV_DIEPDMAB0 register. */
#define ALT_USB_DEV_DIEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB0_OFST))
/*
* Register : diepctl1
*
* Device Control IN Endpoint 1 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL1_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL1_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL1_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL1_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL1_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL1_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL1_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL1_MPS register field. */
#define ALT_USB_DEV_DIEPCTL1_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL1_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL1_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL1_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL1_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL1_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL1_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_DPID register field. */
#define ALT_USB_DEV_DIEPCTL1_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL1_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL1_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL1_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL1_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL1_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL1_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_STALL register field. */
#define ALT_USB_DEV_DIEPCTL1_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL1_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL1_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL1_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL1_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL1_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL1_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL1_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL1_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL1_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL1_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL1_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL1_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL1_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL1_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL1_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL1_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL1.
*/
struct ALT_USB_DEV_DIEPCTL1_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL1_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL1_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL1_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL1_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL1_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL1_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL1_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL1_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL1_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL1_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL1_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL1_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL1_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL1. */
typedef volatile struct ALT_USB_DEV_DIEPCTL1_s ALT_USB_DEV_DIEPCTL1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL1 register. */
#define ALT_USB_DEV_DIEPCTL1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL1_OFST 0x120
/* The address of the ALT_USB_DEV_DIEPCTL1 register. */
#define ALT_USB_DEV_DIEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL1_OFST))
/*
* Register : diepint1
*
* Device IN Endpoint 1 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT1_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT1_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT1_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT1_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT1_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT1_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TMO register field value. */
#define ALT_USB_DEV_DIEPINT1_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TMO register field value. */
#define ALT_USB_DEV_DIEPINT1_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT1_TMO register field. */
#define ALT_USB_DEV_DIEPINT1_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT1_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT1_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT1_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT1_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT1_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT1_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT1_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT1_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT1_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT1_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT1_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT1_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT1_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT1_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT1_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT1.
*/
struct ALT_USB_DEV_DIEPINT1_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT1_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT1_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT1_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT1_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT1_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT1_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT1_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT1_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT1_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT1_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT1_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT1_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT1_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT1_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT1. */
typedef volatile struct ALT_USB_DEV_DIEPINT1_s ALT_USB_DEV_DIEPINT1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT1 register. */
#define ALT_USB_DEV_DIEPINT1_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT1_OFST 0x128
/* The address of the ALT_USB_DEV_DIEPINT1 register. */
#define ALT_USB_DEV_DIEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT1_OFST))
/*
* Register : dieptsiz1
*
* Device IN Endpoint 1 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ1_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ1_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ1_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ1_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ1_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ1_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ1_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ1.
*/
struct ALT_USB_DEV_DIEPTSIZ1_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ1_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ1_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ1_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ1. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ1_s ALT_USB_DEV_DIEPTSIZ1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ1 register. */
#define ALT_USB_DEV_DIEPTSIZ1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ1_OFST 0x130
/* The address of the ALT_USB_DEV_DIEPTSIZ1 register. */
#define ALT_USB_DEV_DIEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ1_OFST))
/*
* Register : diepdma1
*
* Device IN Endpoint 1 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA1_DIEPDMA1
*
*/
/*
* Field : diepdma1
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA1_DIEPDMA1 field value from a register. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA1_DIEPDMA1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA1_DIEPDMA1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA1.
*/
struct ALT_USB_DEV_DIEPDMA1_s
{
uint32_t diepdma1 : 32; /* ALT_USB_DEV_DIEPDMA1_DIEPDMA1 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA1. */
typedef volatile struct ALT_USB_DEV_DIEPDMA1_s ALT_USB_DEV_DIEPDMA1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA1 register. */
#define ALT_USB_DEV_DIEPDMA1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA1_OFST 0x134
/* The address of the ALT_USB_DEV_DIEPDMA1 register. */
#define ALT_USB_DEV_DIEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA1_OFST))
/*
* Register : dtxfsts1
*
* Device IN Endpoint Transmit FIFO Status Register 1
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS1.
*/
struct ALT_USB_DEV_DTXFSTS1_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS1_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS1. */
typedef volatile struct ALT_USB_DEV_DTXFSTS1_s ALT_USB_DEV_DTXFSTS1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS1 register. */
#define ALT_USB_DEV_DTXFSTS1_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS1 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS1_OFST 0x138
/* The address of the ALT_USB_DEV_DTXFSTS1 register. */
#define ALT_USB_DEV_DTXFSTS1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS1_OFST))
/*
* Register : diepdmab1
*
* Device IN Endpoint 1 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1
*
*/
/*
* Field : diepdmab1
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB1.
*/
struct ALT_USB_DEV_DIEPDMAB1_s
{
const uint32_t diepdmab1 : 32; /* ALT_USB_DEV_DIEPDMAB1_DIEPDMAB1 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB1. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB1_s ALT_USB_DEV_DIEPDMAB1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB1 register. */
#define ALT_USB_DEV_DIEPDMAB1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB1 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB1_OFST 0x13c
/* The address of the ALT_USB_DEV_DIEPDMAB1 register. */
#define ALT_USB_DEV_DIEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB1_OFST))
/*
* Register : diepctl2
*
* Device Control IN Endpoint 2 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL2_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL2_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL2_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL2_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL2_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL2_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL2_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL2_MPS register field. */
#define ALT_USB_DEV_DIEPCTL2_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL2_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL2_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL2_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL2_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL2_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL2_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_DPID register field. */
#define ALT_USB_DEV_DIEPCTL2_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL2_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL2_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL2_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL2_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL2_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL2_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_STALL register field. */
#define ALT_USB_DEV_DIEPCTL2_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL2_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL2_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL2_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL2_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL2_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL2_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL2_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL2_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL2_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL2_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL2_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL2_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL2_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL2_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL2_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL2_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL2.
*/
struct ALT_USB_DEV_DIEPCTL2_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL2_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL2_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL2_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL2_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL2_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL2_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL2_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL2_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL2_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL2_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL2_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL2_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL2_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL2. */
typedef volatile struct ALT_USB_DEV_DIEPCTL2_s ALT_USB_DEV_DIEPCTL2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL2 register. */
#define ALT_USB_DEV_DIEPCTL2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL2_OFST 0x140
/* The address of the ALT_USB_DEV_DIEPCTL2 register. */
#define ALT_USB_DEV_DIEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL2_OFST))
/*
* Register : diepint2
*
* Device IN Endpoint 2 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT2_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT2_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT2_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT2_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT2_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT2_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TMO register field value. */
#define ALT_USB_DEV_DIEPINT2_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TMO register field value. */
#define ALT_USB_DEV_DIEPINT2_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT2_TMO register field. */
#define ALT_USB_DEV_DIEPINT2_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT2_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT2_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT2_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT2_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT2_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT2_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT2_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT2_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT2_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT2_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT2_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT2_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT2_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT2_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT2_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT2.
*/
struct ALT_USB_DEV_DIEPINT2_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT2_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT2_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT2_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT2_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT2_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT2_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT2_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT2_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT2_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT2_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT2_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT2_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT2_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT2_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT2. */
typedef volatile struct ALT_USB_DEV_DIEPINT2_s ALT_USB_DEV_DIEPINT2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT2 register. */
#define ALT_USB_DEV_DIEPINT2_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT2_OFST 0x148
/* The address of the ALT_USB_DEV_DIEPINT2 register. */
#define ALT_USB_DEV_DIEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT2_OFST))
/*
* Register : dieptsiz2
*
* Device IN Endpoint 2 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ2_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ2_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ2_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ2_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ2_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ2_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ2_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ2.
*/
struct ALT_USB_DEV_DIEPTSIZ2_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ2_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ2_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ2_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ2. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ2_s ALT_USB_DEV_DIEPTSIZ2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ2 register. */
#define ALT_USB_DEV_DIEPTSIZ2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ2_OFST 0x150
/* The address of the ALT_USB_DEV_DIEPTSIZ2 register. */
#define ALT_USB_DEV_DIEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ2_OFST))
/*
* Register : diepdma2
*
* Device IN Endpoint 2 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA2_DIEPDMA2
*
*/
/*
* Field : diepdma2
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA2_DIEPDMA2 field value from a register. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA2_DIEPDMA2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA2_DIEPDMA2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA2.
*/
struct ALT_USB_DEV_DIEPDMA2_s
{
uint32_t diepdma2 : 32; /* ALT_USB_DEV_DIEPDMA2_DIEPDMA2 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA2. */
typedef volatile struct ALT_USB_DEV_DIEPDMA2_s ALT_USB_DEV_DIEPDMA2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA2 register. */
#define ALT_USB_DEV_DIEPDMA2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA2_OFST 0x154
/* The address of the ALT_USB_DEV_DIEPDMA2 register. */
#define ALT_USB_DEV_DIEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA2_OFST))
/*
* Register : dtxfsts2
*
* Device IN Endpoint Transmit FIFO Status Register 2
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS2.
*/
struct ALT_USB_DEV_DTXFSTS2_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS2_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS2. */
typedef volatile struct ALT_USB_DEV_DTXFSTS2_s ALT_USB_DEV_DTXFSTS2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS2 register. */
#define ALT_USB_DEV_DTXFSTS2_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS2 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS2_OFST 0x158
/* The address of the ALT_USB_DEV_DTXFSTS2 register. */
#define ALT_USB_DEV_DTXFSTS2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS2_OFST))
/*
* Register : diepdmab2
*
* Device IN Endpoint 2 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2
*
*/
/*
* Field : diepdmab2
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB2.
*/
struct ALT_USB_DEV_DIEPDMAB2_s
{
const uint32_t diepdmab2 : 32; /* ALT_USB_DEV_DIEPDMAB2_DIEPDMAB2 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB2. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB2_s ALT_USB_DEV_DIEPDMAB2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB2 register. */
#define ALT_USB_DEV_DIEPDMAB2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB2 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB2_OFST 0x15c
/* The address of the ALT_USB_DEV_DIEPDMAB2 register. */
#define ALT_USB_DEV_DIEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB2_OFST))
/*
* Register : diepctl3
*
* Device Control IN Endpoint 3 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL3_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL3_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL3_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL3_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL3_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL3_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL3_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL3_MPS register field. */
#define ALT_USB_DEV_DIEPCTL3_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL3_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL3_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL3_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL3_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL3_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL3_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_DPID register field. */
#define ALT_USB_DEV_DIEPCTL3_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL3_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL3_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL3_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL3_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL3_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL3_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_STALL register field. */
#define ALT_USB_DEV_DIEPCTL3_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL3_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL3_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL3_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL3_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL3_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL3_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL3_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL3_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL3_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL3_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL3_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL3_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL3_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL3_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL3_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL3_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL3.
*/
struct ALT_USB_DEV_DIEPCTL3_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL3_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL3_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL3_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL3_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL3_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL3_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL3_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL3_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL3_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL3_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL3_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL3_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL3_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL3. */
typedef volatile struct ALT_USB_DEV_DIEPCTL3_s ALT_USB_DEV_DIEPCTL3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL3 register. */
#define ALT_USB_DEV_DIEPCTL3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL3_OFST 0x160
/* The address of the ALT_USB_DEV_DIEPCTL3 register. */
#define ALT_USB_DEV_DIEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL3_OFST))
/*
* Register : diepint3
*
* Device IN Endpoint 3 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT3_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT3_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT3_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT3_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT3_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT3_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TMO register field value. */
#define ALT_USB_DEV_DIEPINT3_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TMO register field value. */
#define ALT_USB_DEV_DIEPINT3_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT3_TMO register field. */
#define ALT_USB_DEV_DIEPINT3_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT3_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT3_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT3_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT3_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT3_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT3_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT3_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT3_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT3_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT3_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT3_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT3_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT3_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT3_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT3_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT3.
*/
struct ALT_USB_DEV_DIEPINT3_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT3_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT3_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT3_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT3_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT3_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT3_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT3_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT3_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT3_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT3_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT3_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT3_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT3_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT3_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT3. */
typedef volatile struct ALT_USB_DEV_DIEPINT3_s ALT_USB_DEV_DIEPINT3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT3 register. */
#define ALT_USB_DEV_DIEPINT3_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT3_OFST 0x168
/* The address of the ALT_USB_DEV_DIEPINT3 register. */
#define ALT_USB_DEV_DIEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT3_OFST))
/*
* Register : dieptsiz3
*
* Device IN Endpoint 3 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ3_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ3_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ3_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ3_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ3_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ3_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ3_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ3.
*/
struct ALT_USB_DEV_DIEPTSIZ3_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ3_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ3_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ3_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ3. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ3_s ALT_USB_DEV_DIEPTSIZ3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ3 register. */
#define ALT_USB_DEV_DIEPTSIZ3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ3_OFST 0x170
/* The address of the ALT_USB_DEV_DIEPTSIZ3 register. */
#define ALT_USB_DEV_DIEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ3_OFST))
/*
* Register : diepdma3
*
* Device IN Endpoint 3 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA3_DIEPDMA3
*
*/
/*
* Field : diepdma3
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA3_DIEPDMA3 field value from a register. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA3_DIEPDMA3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA3_DIEPDMA3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA3.
*/
struct ALT_USB_DEV_DIEPDMA3_s
{
uint32_t diepdma3 : 32; /* ALT_USB_DEV_DIEPDMA3_DIEPDMA3 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA3. */
typedef volatile struct ALT_USB_DEV_DIEPDMA3_s ALT_USB_DEV_DIEPDMA3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA3 register. */
#define ALT_USB_DEV_DIEPDMA3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA3_OFST 0x174
/* The address of the ALT_USB_DEV_DIEPDMA3 register. */
#define ALT_USB_DEV_DIEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA3_OFST))
/*
* Register : dtxfsts3
*
* Device IN Endpoint Transmit FIFO Status Register 3
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS3.
*/
struct ALT_USB_DEV_DTXFSTS3_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS3_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS3. */
typedef volatile struct ALT_USB_DEV_DTXFSTS3_s ALT_USB_DEV_DTXFSTS3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS3 register. */
#define ALT_USB_DEV_DTXFSTS3_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS3 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS3_OFST 0x178
/* The address of the ALT_USB_DEV_DTXFSTS3 register. */
#define ALT_USB_DEV_DTXFSTS3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS3_OFST))
/*
* Register : diepdmab3
*
* Device IN Endpoint 3 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3
*
*/
/*
* Field : diepdmab3
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB3.
*/
struct ALT_USB_DEV_DIEPDMAB3_s
{
const uint32_t diepdmab3 : 32; /* ALT_USB_DEV_DIEPDMAB3_DIEPDMAB3 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB3. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB3_s ALT_USB_DEV_DIEPDMAB3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB3 register. */
#define ALT_USB_DEV_DIEPDMAB3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB3 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB3_OFST 0x17c
/* The address of the ALT_USB_DEV_DIEPDMAB3 register. */
#define ALT_USB_DEV_DIEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB3_OFST))
/*
* Register : diepctl4
*
* Device Control IN Endpoint 4 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL4_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL4_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL4_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL4_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL4_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL4_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL4_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL4_MPS register field. */
#define ALT_USB_DEV_DIEPCTL4_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL4_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL4_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL4_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL4_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL4_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL4_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_DPID register field. */
#define ALT_USB_DEV_DIEPCTL4_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL4_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL4_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL4_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL4_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL4_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL4_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_STALL register field. */
#define ALT_USB_DEV_DIEPCTL4_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL4_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL4_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL4_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL4_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL4_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL4_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL4_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL4_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL4_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL4_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL4_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL4_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL4_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL4_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL4_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL4_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL4.
*/
struct ALT_USB_DEV_DIEPCTL4_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL4_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL4_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL4_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL4_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL4_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL4_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL4_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL4_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL4_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL4_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL4_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL4_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL4_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL4. */
typedef volatile struct ALT_USB_DEV_DIEPCTL4_s ALT_USB_DEV_DIEPCTL4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL4 register. */
#define ALT_USB_DEV_DIEPCTL4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL4_OFST 0x180
/* The address of the ALT_USB_DEV_DIEPCTL4 register. */
#define ALT_USB_DEV_DIEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL4_OFST))
/*
* Register : diepint4
*
* Device IN Endpoint 4 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT4_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT4_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT4_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT4_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT4_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT4_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TMO register field value. */
#define ALT_USB_DEV_DIEPINT4_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TMO register field value. */
#define ALT_USB_DEV_DIEPINT4_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT4_TMO register field. */
#define ALT_USB_DEV_DIEPINT4_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT4_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT4_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT4_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT4_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT4_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT4_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT4_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT4_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT4_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT4_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT4_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT4_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT4_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT4_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT4_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT4.
*/
struct ALT_USB_DEV_DIEPINT4_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT4_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT4_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT4_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT4_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT4_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT4_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT4_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT4_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT4_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT4_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT4_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT4_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT4_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT4_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT4. */
typedef volatile struct ALT_USB_DEV_DIEPINT4_s ALT_USB_DEV_DIEPINT4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT4 register. */
#define ALT_USB_DEV_DIEPINT4_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT4_OFST 0x188
/* The address of the ALT_USB_DEV_DIEPINT4 register. */
#define ALT_USB_DEV_DIEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT4_OFST))
/*
* Register : dieptsiz4
*
* Device IN Endpoint 4 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ4_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ4_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ4_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ4_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ4_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ4_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ4_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ4.
*/
struct ALT_USB_DEV_DIEPTSIZ4_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ4_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ4_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ4_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ4. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ4_s ALT_USB_DEV_DIEPTSIZ4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ4 register. */
#define ALT_USB_DEV_DIEPTSIZ4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ4_OFST 0x190
/* The address of the ALT_USB_DEV_DIEPTSIZ4 register. */
#define ALT_USB_DEV_DIEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ4_OFST))
/*
* Register : diepdma4
*
* Device IN Endpoint 4 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA4_DIEPDMA4
*
*/
/*
* Field : diepdma4
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA4_DIEPDMA4 field value from a register. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA4_DIEPDMA4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA4_DIEPDMA4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA4.
*/
struct ALT_USB_DEV_DIEPDMA4_s
{
uint32_t diepdma4 : 32; /* ALT_USB_DEV_DIEPDMA4_DIEPDMA4 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA4. */
typedef volatile struct ALT_USB_DEV_DIEPDMA4_s ALT_USB_DEV_DIEPDMA4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA4 register. */
#define ALT_USB_DEV_DIEPDMA4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA4_OFST 0x194
/* The address of the ALT_USB_DEV_DIEPDMA4 register. */
#define ALT_USB_DEV_DIEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA4_OFST))
/*
* Register : dtxfsts4
*
* Device IN Endpoint Transmit FIFO Status Register 4
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS4.
*/
struct ALT_USB_DEV_DTXFSTS4_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS4_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS4. */
typedef volatile struct ALT_USB_DEV_DTXFSTS4_s ALT_USB_DEV_DTXFSTS4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS4 register. */
#define ALT_USB_DEV_DTXFSTS4_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS4 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS4_OFST 0x198
/* The address of the ALT_USB_DEV_DTXFSTS4 register. */
#define ALT_USB_DEV_DTXFSTS4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS4_OFST))
/*
* Register : diepdmab4
*
* Device IN Endpoint 4 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4
*
*/
/*
* Field : diepdmab4
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB4.
*/
struct ALT_USB_DEV_DIEPDMAB4_s
{
const uint32_t diepdmab4 : 32; /* ALT_USB_DEV_DIEPDMAB4_DIEPDMAB4 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB4. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB4_s ALT_USB_DEV_DIEPDMAB4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB4 register. */
#define ALT_USB_DEV_DIEPDMAB4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB4 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB4_OFST 0x19c
/* The address of the ALT_USB_DEV_DIEPDMAB4 register. */
#define ALT_USB_DEV_DIEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB4_OFST))
/*
* Register : diepctl5
*
* Device Control IN Endpoint 5 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL5_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL5_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL5_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL5_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL5_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL5_MPS register field. */
#define ALT_USB_DEV_DIEPCTL5_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL5_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL5_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_DPID register field. */
#define ALT_USB_DEV_DIEPCTL5_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL5_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL5_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_STALL register field. */
#define ALT_USB_DEV_DIEPCTL5_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL5_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL5_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL5_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL5_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL5_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL5_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL5_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL5_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL5.
*/
struct ALT_USB_DEV_DIEPCTL5_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL5_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL5_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL5_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL5_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL5_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL5_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL5_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL5_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL5_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL5_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL5_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL5_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL5_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL5. */
typedef volatile struct ALT_USB_DEV_DIEPCTL5_s ALT_USB_DEV_DIEPCTL5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL5 register. */
#define ALT_USB_DEV_DIEPCTL5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL5_OFST 0x1a0
/* The address of the ALT_USB_DEV_DIEPCTL5 register. */
#define ALT_USB_DEV_DIEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST))
/*
* Register : diepint5
*
* Device IN Endpoint 5 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT5_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT5_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT5_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT5_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT5_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT5_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TMO register field value. */
#define ALT_USB_DEV_DIEPINT5_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TMO register field value. */
#define ALT_USB_DEV_DIEPINT5_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT5_TMO register field. */
#define ALT_USB_DEV_DIEPINT5_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT5_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT5_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT5_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT5_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT5_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT5_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT5_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT5_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT5_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT5_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT5_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT5_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT5_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT5_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT5_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT5.
*/
struct ALT_USB_DEV_DIEPINT5_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT5_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT5_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT5_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT5_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT5_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT5_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT5_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT5_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT5_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT5_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT5_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT5_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT5_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT5_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT5. */
typedef volatile struct ALT_USB_DEV_DIEPINT5_s ALT_USB_DEV_DIEPINT5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT5 register. */
#define ALT_USB_DEV_DIEPINT5_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT5_OFST 0x1a8
/* The address of the ALT_USB_DEV_DIEPINT5 register. */
#define ALT_USB_DEV_DIEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT5_OFST))
/*
* Register : dieptsiz5
*
* Device IN Endpoint 5 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ5_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ5_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ5_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ5_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ5_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ5_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ5_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ5.
*/
struct ALT_USB_DEV_DIEPTSIZ5_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ5_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ5_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ5_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ5. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ5_s ALT_USB_DEV_DIEPTSIZ5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ5 register. */
#define ALT_USB_DEV_DIEPTSIZ5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ5_OFST 0x1b0
/* The address of the ALT_USB_DEV_DIEPTSIZ5 register. */
#define ALT_USB_DEV_DIEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ5_OFST))
/*
* Register : diepdma5
*
* Device IN Endpoint 5 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA5_DIEPDMA5
*
*/
/*
* Field : diepdma5
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA5_DIEPDMA5 field value from a register. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA5_DIEPDMA5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA5_DIEPDMA5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA5.
*/
struct ALT_USB_DEV_DIEPDMA5_s
{
uint32_t diepdma5 : 32; /* ALT_USB_DEV_DIEPDMA5_DIEPDMA5 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA5. */
typedef volatile struct ALT_USB_DEV_DIEPDMA5_s ALT_USB_DEV_DIEPDMA5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA5 register. */
#define ALT_USB_DEV_DIEPDMA5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA5_OFST 0x1b4
/* The address of the ALT_USB_DEV_DIEPDMA5 register. */
#define ALT_USB_DEV_DIEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA5_OFST))
/*
* Register : dtxfsts5
*
* Device IN Endpoint Transmit FIFO Status Register 5
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS5.
*/
struct ALT_USB_DEV_DTXFSTS5_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS5_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS5. */
typedef volatile struct ALT_USB_DEV_DTXFSTS5_s ALT_USB_DEV_DTXFSTS5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS5 register. */
#define ALT_USB_DEV_DTXFSTS5_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS5 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS5_OFST 0x1b8
/* The address of the ALT_USB_DEV_DTXFSTS5 register. */
#define ALT_USB_DEV_DTXFSTS5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS5_OFST))
/*
* Register : diepdmab5
*
* Device IN Endpoint 5 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5
*
*/
/*
* Field : diepdmab5
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB5.
*/
struct ALT_USB_DEV_DIEPDMAB5_s
{
const uint32_t diepdmab5 : 32; /* ALT_USB_DEV_DIEPDMAB5_DIEPDMAB5 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB5. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB5_s ALT_USB_DEV_DIEPDMAB5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB5 register. */
#define ALT_USB_DEV_DIEPDMAB5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB5 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB5_OFST 0x1bc
/* The address of the ALT_USB_DEV_DIEPDMAB5 register. */
#define ALT_USB_DEV_DIEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB5_OFST))
/*
* Register : diepctl6
*
* Device Control IN Endpoint 6 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL6_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL6_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL6_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL6_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL6_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL6_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL6_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL6_MPS register field. */
#define ALT_USB_DEV_DIEPCTL6_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL6_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL6_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL6_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL6_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL6_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL6_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_DPID register field. */
#define ALT_USB_DEV_DIEPCTL6_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL6_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL6_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL6_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL6_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL6_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL6_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_STALL register field. */
#define ALT_USB_DEV_DIEPCTL6_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL6_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL6_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL6_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL6_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL6_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL6_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL6_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL6_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL6_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL6_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL6_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL6_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL6_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL6_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL6_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL6_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL6.
*/
struct ALT_USB_DEV_DIEPCTL6_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL6_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL6_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL6_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL6_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL6_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL6_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL6_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL6_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL6_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL6_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL6_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL6_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL6_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL6. */
typedef volatile struct ALT_USB_DEV_DIEPCTL6_s ALT_USB_DEV_DIEPCTL6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL6 register. */
#define ALT_USB_DEV_DIEPCTL6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL6_OFST 0x1c0
/* The address of the ALT_USB_DEV_DIEPCTL6 register. */
#define ALT_USB_DEV_DIEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL6_OFST))
/*
* Register : diepint6
*
* Device IN Endpoint 6 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT6_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT6_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT6_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT6_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT6_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT6_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TMO register field value. */
#define ALT_USB_DEV_DIEPINT6_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TMO register field value. */
#define ALT_USB_DEV_DIEPINT6_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT6_TMO register field. */
#define ALT_USB_DEV_DIEPINT6_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT6_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT6_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT6_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT6_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT6_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT6_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT6_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT6_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT6_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT6_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT6_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT6_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT6_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT6_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT6_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT6.
*/
struct ALT_USB_DEV_DIEPINT6_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT6_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT6_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT6_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT6_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT6_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT6_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT6_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT6_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT6_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT6_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT6_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT6_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT6_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT6_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT6. */
typedef volatile struct ALT_USB_DEV_DIEPINT6_s ALT_USB_DEV_DIEPINT6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT6 register. */
#define ALT_USB_DEV_DIEPINT6_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT6_OFST 0x1c8
/* The address of the ALT_USB_DEV_DIEPINT6 register. */
#define ALT_USB_DEV_DIEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT6_OFST))
/*
* Register : dieptsiz6
*
* Device IN Endpoint 6 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ6_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ6_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ6_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ6_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ6_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ6_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ6_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ6.
*/
struct ALT_USB_DEV_DIEPTSIZ6_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ6_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ6_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ6_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ6. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ6_s ALT_USB_DEV_DIEPTSIZ6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ6 register. */
#define ALT_USB_DEV_DIEPTSIZ6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ6_OFST 0x1d0
/* The address of the ALT_USB_DEV_DIEPTSIZ6 register. */
#define ALT_USB_DEV_DIEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ6_OFST))
/*
* Register : diepdma6
*
* Device IN Endpoint 6 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA6_DIEPDMA6
*
*/
/*
* Field : diepdma6
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA6_DIEPDMA6 field value from a register. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA6_DIEPDMA6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA6_DIEPDMA6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA6.
*/
struct ALT_USB_DEV_DIEPDMA6_s
{
uint32_t diepdma6 : 32; /* ALT_USB_DEV_DIEPDMA6_DIEPDMA6 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA6. */
typedef volatile struct ALT_USB_DEV_DIEPDMA6_s ALT_USB_DEV_DIEPDMA6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA6 register. */
#define ALT_USB_DEV_DIEPDMA6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA6_OFST 0x1d4
/* The address of the ALT_USB_DEV_DIEPDMA6 register. */
#define ALT_USB_DEV_DIEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA6_OFST))
/*
* Register : dtxfsts6
*
* Device IN Endpoint Transmit FIFO Status Register 6
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS6.
*/
struct ALT_USB_DEV_DTXFSTS6_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS6_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS6. */
typedef volatile struct ALT_USB_DEV_DTXFSTS6_s ALT_USB_DEV_DTXFSTS6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS6 register. */
#define ALT_USB_DEV_DTXFSTS6_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS6 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS6_OFST 0x1d8
/* The address of the ALT_USB_DEV_DTXFSTS6 register. */
#define ALT_USB_DEV_DTXFSTS6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS6_OFST))
/*
* Register : diepdmab6
*
* Device IN Endpoint 6 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6
*
*/
/*
* Field : diepdmab6
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB6.
*/
struct ALT_USB_DEV_DIEPDMAB6_s
{
const uint32_t diepdmab6 : 32; /* ALT_USB_DEV_DIEPDMAB6_DIEPDMAB6 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB6. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB6_s ALT_USB_DEV_DIEPDMAB6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB6 register. */
#define ALT_USB_DEV_DIEPDMAB6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB6 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB6_OFST 0x1dc
/* The address of the ALT_USB_DEV_DIEPDMAB6 register. */
#define ALT_USB_DEV_DIEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB6_OFST))
/*
* Register : diepctl7
*
* Device Control IN Endpoint 7 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL7_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL7_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL7_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL7_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL7_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL7_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL7_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL7_MPS register field. */
#define ALT_USB_DEV_DIEPCTL7_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL7_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL7_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL7_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL7_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL7_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL7_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_DPID register field. */
#define ALT_USB_DEV_DIEPCTL7_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL7_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL7_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL7_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL7_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL7_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL7_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_STALL register field. */
#define ALT_USB_DEV_DIEPCTL7_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL7_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL7_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL7_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL7_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL7_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL7_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL7_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL7_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL7_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL7_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL7_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL7_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL7_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL7_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL7_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL7_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL7.
*/
struct ALT_USB_DEV_DIEPCTL7_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL7_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL7_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL7_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL7_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL7_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL7_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL7_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL7_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL7_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL7_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL7_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL7_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL7_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL7. */
typedef volatile struct ALT_USB_DEV_DIEPCTL7_s ALT_USB_DEV_DIEPCTL7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL7 register. */
#define ALT_USB_DEV_DIEPCTL7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL7_OFST 0x1e0
/* The address of the ALT_USB_DEV_DIEPCTL7 register. */
#define ALT_USB_DEV_DIEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL7_OFST))
/*
* Register : diepint7
*
* Device IN Endpoint 7 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT7_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT7_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT7_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT7_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT7_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT7_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TMO register field value. */
#define ALT_USB_DEV_DIEPINT7_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TMO register field value. */
#define ALT_USB_DEV_DIEPINT7_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT7_TMO register field. */
#define ALT_USB_DEV_DIEPINT7_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT7_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT7_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT7_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT7_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT7_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT7_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT7_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT7_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT7_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT7_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT7_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT7_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT7_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT7_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT7_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT7.
*/
struct ALT_USB_DEV_DIEPINT7_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT7_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT7_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT7_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT7_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT7_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT7_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT7_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT7_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT7_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT7_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT7_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT7_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT7_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT7_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT7. */
typedef volatile struct ALT_USB_DEV_DIEPINT7_s ALT_USB_DEV_DIEPINT7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT7 register. */
#define ALT_USB_DEV_DIEPINT7_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT7_OFST 0x1e8
/* The address of the ALT_USB_DEV_DIEPINT7 register. */
#define ALT_USB_DEV_DIEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT7_OFST))
/*
* Register : dieptsiz7
*
* Device IN Endpoint 7 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ7_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ7_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ7_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ7_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ7_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ7_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ7_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ7.
*/
struct ALT_USB_DEV_DIEPTSIZ7_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ7_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ7_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ7_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ7. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ7_s ALT_USB_DEV_DIEPTSIZ7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ7 register. */
#define ALT_USB_DEV_DIEPTSIZ7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ7_OFST 0x1f0
/* The address of the ALT_USB_DEV_DIEPTSIZ7 register. */
#define ALT_USB_DEV_DIEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ7_OFST))
/*
* Register : diepdma7
*
* Device IN Endpoint 7 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA7_DIEPDMA7
*
*/
/*
* Field : diepdma7
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA7_DIEPDMA7 field value from a register. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA7_DIEPDMA7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA7_DIEPDMA7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA7.
*/
struct ALT_USB_DEV_DIEPDMA7_s
{
uint32_t diepdma7 : 32; /* ALT_USB_DEV_DIEPDMA7_DIEPDMA7 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA7. */
typedef volatile struct ALT_USB_DEV_DIEPDMA7_s ALT_USB_DEV_DIEPDMA7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA7 register. */
#define ALT_USB_DEV_DIEPDMA7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA7_OFST 0x1f4
/* The address of the ALT_USB_DEV_DIEPDMA7 register. */
#define ALT_USB_DEV_DIEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA7_OFST))
/*
* Register : dtxfsts7
*
* Device IN Endpoint Transmit FIFO Status Register 7
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS7.
*/
struct ALT_USB_DEV_DTXFSTS7_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS7_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS7. */
typedef volatile struct ALT_USB_DEV_DTXFSTS7_s ALT_USB_DEV_DTXFSTS7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS7 register. */
#define ALT_USB_DEV_DTXFSTS7_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS7 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS7_OFST 0x1f8
/* The address of the ALT_USB_DEV_DTXFSTS7 register. */
#define ALT_USB_DEV_DTXFSTS7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS7_OFST))
/*
* Register : diepdmab7
*
* Device IN Endpoint 7 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7
*
*/
/*
* Field : diepdmab7
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB7.
*/
struct ALT_USB_DEV_DIEPDMAB7_s
{
const uint32_t diepdmab7 : 32; /* ALT_USB_DEV_DIEPDMAB7_DIEPDMAB7 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB7. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB7_s ALT_USB_DEV_DIEPDMAB7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB7 register. */
#define ALT_USB_DEV_DIEPDMAB7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB7 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB7_OFST 0x1fc
/* The address of the ALT_USB_DEV_DIEPDMAB7 register. */
#define ALT_USB_DEV_DIEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB7_OFST))
/*
* Register : diepctl8
*
* Device Control IN Endpoint 8 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL8_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL8_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL8_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL8_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL8_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL8_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL8_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL8_MPS register field. */
#define ALT_USB_DEV_DIEPCTL8_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL8_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL8_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL8_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL8_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL8_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL8_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_DPID register field. */
#define ALT_USB_DEV_DIEPCTL8_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL8_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL8_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL8_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL8_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL8_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL8_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_STALL register field. */
#define ALT_USB_DEV_DIEPCTL8_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL8_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL8_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL8_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL8_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL8_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL8_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL8_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL8_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL8_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL8_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL8_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL8_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL8_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL8_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL8_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL8_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL8.
*/
struct ALT_USB_DEV_DIEPCTL8_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL8_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL8_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL8_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL8_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL8_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL8_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL8_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL8_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL8_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL8_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL8_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL8_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL8_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL8. */
typedef volatile struct ALT_USB_DEV_DIEPCTL8_s ALT_USB_DEV_DIEPCTL8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL8 register. */
#define ALT_USB_DEV_DIEPCTL8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL8_OFST 0x200
/* The address of the ALT_USB_DEV_DIEPCTL8 register. */
#define ALT_USB_DEV_DIEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL8_OFST))
/*
* Register : diepint8
*
* Device IN Endpoint 8 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT8_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT8_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT8_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT8_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT8_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT8_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TMO register field value. */
#define ALT_USB_DEV_DIEPINT8_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TMO register field value. */
#define ALT_USB_DEV_DIEPINT8_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT8_TMO register field. */
#define ALT_USB_DEV_DIEPINT8_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT8_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT8_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT8_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT8_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT8_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT8_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT8_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT8_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT8_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT8_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT8_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT8_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT8_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT8_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT8_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT8.
*/
struct ALT_USB_DEV_DIEPINT8_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT8_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT8_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT8_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT8_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT8_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT8_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT8_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT8_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT8_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT8_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT8_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT8_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT8_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT8_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT8. */
typedef volatile struct ALT_USB_DEV_DIEPINT8_s ALT_USB_DEV_DIEPINT8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT8 register. */
#define ALT_USB_DEV_DIEPINT8_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT8_OFST 0x208
/* The address of the ALT_USB_DEV_DIEPINT8 register. */
#define ALT_USB_DEV_DIEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT8_OFST))
/*
* Register : dieptsiz8
*
* Device IN Endpoint 8 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ8_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ8_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ8_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ8_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ8_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ8_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ8_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ8.
*/
struct ALT_USB_DEV_DIEPTSIZ8_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ8_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ8_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ8_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ8. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ8_s ALT_USB_DEV_DIEPTSIZ8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ8 register. */
#define ALT_USB_DEV_DIEPTSIZ8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ8_OFST 0x210
/* The address of the ALT_USB_DEV_DIEPTSIZ8 register. */
#define ALT_USB_DEV_DIEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ8_OFST))
/*
* Register : diepdma8
*
* Device IN Endpoint 8 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA8_DIEPDMA8
*
*/
/*
* Field : diepdma8
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA8_DIEPDMA8 field value from a register. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA8_DIEPDMA8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA8_DIEPDMA8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA8.
*/
struct ALT_USB_DEV_DIEPDMA8_s
{
uint32_t diepdma8 : 32; /* ALT_USB_DEV_DIEPDMA8_DIEPDMA8 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA8. */
typedef volatile struct ALT_USB_DEV_DIEPDMA8_s ALT_USB_DEV_DIEPDMA8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA8 register. */
#define ALT_USB_DEV_DIEPDMA8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA8_OFST 0x214
/* The address of the ALT_USB_DEV_DIEPDMA8 register. */
#define ALT_USB_DEV_DIEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA8_OFST))
/*
* Register : dtxfsts8
*
* Device IN Endpoint Transmit FIFO Status Register 8
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS8.
*/
struct ALT_USB_DEV_DTXFSTS8_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS8_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS8. */
typedef volatile struct ALT_USB_DEV_DTXFSTS8_s ALT_USB_DEV_DTXFSTS8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS8 register. */
#define ALT_USB_DEV_DTXFSTS8_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS8 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS8_OFST 0x218
/* The address of the ALT_USB_DEV_DTXFSTS8 register. */
#define ALT_USB_DEV_DTXFSTS8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS8_OFST))
/*
* Register : diepdmab8
*
* Device IN Endpoint 8 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8
*
*/
/*
* Field : diepdmab8
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB8.
*/
struct ALT_USB_DEV_DIEPDMAB8_s
{
const uint32_t diepdmab8 : 32; /* ALT_USB_DEV_DIEPDMAB8_DIEPDMAB8 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB8. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB8_s ALT_USB_DEV_DIEPDMAB8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB8 register. */
#define ALT_USB_DEV_DIEPDMAB8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB8 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB8_OFST 0x21c
/* The address of the ALT_USB_DEV_DIEPDMAB8 register. */
#define ALT_USB_DEV_DIEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB8_OFST))
/*
* Register : diepctl9
*
* Device Control IN Endpoint 9 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL9_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL9_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL9_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL9_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL9_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL9_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL9_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL9_MPS register field. */
#define ALT_USB_DEV_DIEPCTL9_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL9_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL9_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL9_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL9_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL9_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL9_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_DPID register field. */
#define ALT_USB_DEV_DIEPCTL9_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL9_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL9_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL9_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL9_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL9_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL9_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_STALL register field. */
#define ALT_USB_DEV_DIEPCTL9_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL9_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL9_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL9_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL9_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL9_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL9_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL9_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL9_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL9_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL9_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL9_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL9_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL9_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL9_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL9_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL9_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL9.
*/
struct ALT_USB_DEV_DIEPCTL9_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL9_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL9_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL9_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL9_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL9_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL9_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL9_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL9_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL9_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL9_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL9_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL9_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL9_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL9. */
typedef volatile struct ALT_USB_DEV_DIEPCTL9_s ALT_USB_DEV_DIEPCTL9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL9 register. */
#define ALT_USB_DEV_DIEPCTL9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL9_OFST 0x220
/* The address of the ALT_USB_DEV_DIEPCTL9 register. */
#define ALT_USB_DEV_DIEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL9_OFST))
/*
* Register : diepint9
*
* Device IN Endpoint 9 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:---------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT9_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT9_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT9_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT9_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT9_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT9_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TMO register field value. */
#define ALT_USB_DEV_DIEPINT9_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TMO register field value. */
#define ALT_USB_DEV_DIEPINT9_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT9_TMO register field. */
#define ALT_USB_DEV_DIEPINT9_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT9_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT9_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT9_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT9_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT9_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT9_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT9_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT9_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT9_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT9_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT9_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT9_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT9_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT9_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT9_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT9.
*/
struct ALT_USB_DEV_DIEPINT9_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT9_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT9_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT9_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT9_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT9_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT9_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT9_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT9_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT9_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT9_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT9_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT9_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT9_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT9_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT9. */
typedef volatile struct ALT_USB_DEV_DIEPINT9_s ALT_USB_DEV_DIEPINT9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT9 register. */
#define ALT_USB_DEV_DIEPINT9_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT9_OFST 0x228
/* The address of the ALT_USB_DEV_DIEPINT9 register. */
#define ALT_USB_DEV_DIEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT9_OFST))
/*
* Register : dieptsiz9
*
* Device IN Endpoint 9 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ9_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ9_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ9_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ9_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ9_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ9_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ9_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ9.
*/
struct ALT_USB_DEV_DIEPTSIZ9_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ9_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ9_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ9_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ9. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ9_s ALT_USB_DEV_DIEPTSIZ9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ9 register. */
#define ALT_USB_DEV_DIEPTSIZ9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ9_OFST 0x230
/* The address of the ALT_USB_DEV_DIEPTSIZ9 register. */
#define ALT_USB_DEV_DIEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ9_OFST))
/*
* Register : diepdma9
*
* Device IN Endpoint 9 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA9_DIEPDMA9
*
*/
/*
* Field : diepdma9
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA9_DIEPDMA9 field value from a register. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA9_DIEPDMA9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA9_DIEPDMA9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA9.
*/
struct ALT_USB_DEV_DIEPDMA9_s
{
uint32_t diepdma9 : 32; /* ALT_USB_DEV_DIEPDMA9_DIEPDMA9 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA9. */
typedef volatile struct ALT_USB_DEV_DIEPDMA9_s ALT_USB_DEV_DIEPDMA9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA9 register. */
#define ALT_USB_DEV_DIEPDMA9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA9_OFST 0x234
/* The address of the ALT_USB_DEV_DIEPDMA9 register. */
#define ALT_USB_DEV_DIEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA9_OFST))
/*
* Register : dtxfsts9
*
* Device IN Endpoint Transmit FIFO Status Register 9
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:-------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS9.
*/
struct ALT_USB_DEV_DTXFSTS9_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS9_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS9. */
typedef volatile struct ALT_USB_DEV_DTXFSTS9_s ALT_USB_DEV_DTXFSTS9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS9 register. */
#define ALT_USB_DEV_DTXFSTS9_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS9 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS9_OFST 0x238
/* The address of the ALT_USB_DEV_DTXFSTS9 register. */
#define ALT_USB_DEV_DTXFSTS9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS9_OFST))
/*
* Register : diepdmab9
*
* Device IN Endpoint 9 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9
*
*/
/*
* Field : diepdmab9
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB9.
*/
struct ALT_USB_DEV_DIEPDMAB9_s
{
const uint32_t diepdmab9 : 32; /* ALT_USB_DEV_DIEPDMAB9_DIEPDMAB9 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB9. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB9_s ALT_USB_DEV_DIEPDMAB9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB9 register. */
#define ALT_USB_DEV_DIEPDMAB9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB9 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB9_OFST 0x23c
/* The address of the ALT_USB_DEV_DIEPDMAB9 register. */
#define ALT_USB_DEV_DIEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB9_OFST))
/*
* Register : diepctl10
*
* Device Control IN Endpoint 10 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL10_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL10_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL10_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL10_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL10_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL10_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL10_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL10_MPS register field. */
#define ALT_USB_DEV_DIEPCTL10_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL10_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL10_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL10_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL10_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL10_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL10_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_DPID register field. */
#define ALT_USB_DEV_DIEPCTL10_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL10_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL10_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL10_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL10_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL10_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL10_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_STALL register field. */
#define ALT_USB_DEV_DIEPCTL10_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL10_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL10_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL10_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL10_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL10_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL10_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL10_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL10_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL10_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL10_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL10_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL10_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL10_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL10_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL10_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL10_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL10.
*/
struct ALT_USB_DEV_DIEPCTL10_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL10_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL10_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL10_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL10_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL10_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL10_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL10_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL10_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL10_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL10_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL10_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL10_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL10_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL10. */
typedef volatile struct ALT_USB_DEV_DIEPCTL10_s ALT_USB_DEV_DIEPCTL10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL10 register. */
#define ALT_USB_DEV_DIEPCTL10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL10_OFST 0x240
/* The address of the ALT_USB_DEV_DIEPCTL10 register. */
#define ALT_USB_DEV_DIEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL10_OFST))
/*
* Register : diepint10
*
* Device IN Endpoint 10 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT10_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT10_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT10_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT10_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT10_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT10_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TMO register field value. */
#define ALT_USB_DEV_DIEPINT10_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TMO register field value. */
#define ALT_USB_DEV_DIEPINT10_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT10_TMO register field. */
#define ALT_USB_DEV_DIEPINT10_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT10_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT10_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT10_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT10_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT10_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT10_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT10_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT10_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT10_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT10_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT10_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT10_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT10_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT10_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT10_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT10.
*/
struct ALT_USB_DEV_DIEPINT10_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT10_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT10_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT10_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT10_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT10_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT10_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT10_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT10_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT10_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT10_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT10_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT10_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT10_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT10_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT10. */
typedef volatile struct ALT_USB_DEV_DIEPINT10_s ALT_USB_DEV_DIEPINT10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT10 register. */
#define ALT_USB_DEV_DIEPINT10_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT10_OFST 0x248
/* The address of the ALT_USB_DEV_DIEPINT10 register. */
#define ALT_USB_DEV_DIEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT10_OFST))
/*
* Register : dieptsiz10
*
* Device IN Endpoint 10 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ10_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ10_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ10_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ10_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ10_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ10_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ10_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ10.
*/
struct ALT_USB_DEV_DIEPTSIZ10_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ10_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ10_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ10_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ10. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ10_s ALT_USB_DEV_DIEPTSIZ10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ10 register. */
#define ALT_USB_DEV_DIEPTSIZ10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ10_OFST 0x250
/* The address of the ALT_USB_DEV_DIEPTSIZ10 register. */
#define ALT_USB_DEV_DIEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ10_OFST))
/*
* Register : diepdma10
*
* Device IN Endpoint 10 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA10_DIEPDMA10
*
*/
/*
* Field : diepdma10
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA10_DIEPDMA10 field value from a register. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA10_DIEPDMA10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA10_DIEPDMA10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA10.
*/
struct ALT_USB_DEV_DIEPDMA10_s
{
uint32_t diepdma10 : 32; /* ALT_USB_DEV_DIEPDMA10_DIEPDMA10 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA10. */
typedef volatile struct ALT_USB_DEV_DIEPDMA10_s ALT_USB_DEV_DIEPDMA10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA10 register. */
#define ALT_USB_DEV_DIEPDMA10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA10_OFST 0x254
/* The address of the ALT_USB_DEV_DIEPDMA10 register. */
#define ALT_USB_DEV_DIEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA10_OFST))
/*
* Register : dtxfsts10
*
* Device IN Endpoint Transmit FIFO Status Register 10
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS10.
*/
struct ALT_USB_DEV_DTXFSTS10_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS10_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS10. */
typedef volatile struct ALT_USB_DEV_DTXFSTS10_s ALT_USB_DEV_DTXFSTS10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS10 register. */
#define ALT_USB_DEV_DTXFSTS10_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS10 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS10_OFST 0x258
/* The address of the ALT_USB_DEV_DTXFSTS10 register. */
#define ALT_USB_DEV_DTXFSTS10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS10_OFST))
/*
* Register : diepdmab10
*
* Device IN Endpoint 10 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10
*
*/
/*
* Field : diepdmab10
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB10.
*/
struct ALT_USB_DEV_DIEPDMAB10_s
{
const uint32_t diepdmab10 : 32; /* ALT_USB_DEV_DIEPDMAB10_DIEPDMAB10 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB10. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB10_s ALT_USB_DEV_DIEPDMAB10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB10 register. */
#define ALT_USB_DEV_DIEPDMAB10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB10 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB10_OFST 0x25c
/* The address of the ALT_USB_DEV_DIEPDMAB10 register. */
#define ALT_USB_DEV_DIEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB10_OFST))
/*
* Register : diepctl11
*
* Device Control IN Endpoint 11 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL11_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL11_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL11_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL11_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL11_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL11_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL11_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL11_MPS register field. */
#define ALT_USB_DEV_DIEPCTL11_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL11_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL11_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL11_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL11_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL11_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL11_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_DPID register field. */
#define ALT_USB_DEV_DIEPCTL11_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL11_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL11_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL11_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL11_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL11_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL11_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_STALL register field. */
#define ALT_USB_DEV_DIEPCTL11_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL11_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL11_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL11_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL11_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL11_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL11_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL11_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL11_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL11_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL11_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL11_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL11_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL11_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL11_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL11_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL11_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL11.
*/
struct ALT_USB_DEV_DIEPCTL11_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL11_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL11_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL11_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL11_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL11_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL11_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL11_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL11_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL11_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL11_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL11_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL11_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL11_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL11. */
typedef volatile struct ALT_USB_DEV_DIEPCTL11_s ALT_USB_DEV_DIEPCTL11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL11 register. */
#define ALT_USB_DEV_DIEPCTL11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL11_OFST 0x260
/* The address of the ALT_USB_DEV_DIEPCTL11 register. */
#define ALT_USB_DEV_DIEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL11_OFST))
/*
* Register : diepint11
*
* Device IN Endpoint 11 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT11_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT11_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT11_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT11_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT11_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT11_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TMO register field value. */
#define ALT_USB_DEV_DIEPINT11_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TMO register field value. */
#define ALT_USB_DEV_DIEPINT11_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT11_TMO register field. */
#define ALT_USB_DEV_DIEPINT11_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT11_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT11_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT11_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT11_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT11_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT11_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT11_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT11_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT11_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT11_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT11_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT11_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT11_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT11_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT11_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT11.
*/
struct ALT_USB_DEV_DIEPINT11_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT11_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT11_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT11_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT11_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT11_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT11_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT11_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT11_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT11_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT11_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT11_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT11_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT11_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT11_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT11. */
typedef volatile struct ALT_USB_DEV_DIEPINT11_s ALT_USB_DEV_DIEPINT11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT11 register. */
#define ALT_USB_DEV_DIEPINT11_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT11_OFST 0x268
/* The address of the ALT_USB_DEV_DIEPINT11 register. */
#define ALT_USB_DEV_DIEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT11_OFST))
/*
* Register : dieptsiz11
*
* Device IN Endpoint 11 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ11_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ11_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ11_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ11_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ11_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ11_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ11_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ11.
*/
struct ALT_USB_DEV_DIEPTSIZ11_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ11_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ11_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ11_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ11. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ11_s ALT_USB_DEV_DIEPTSIZ11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ11 register. */
#define ALT_USB_DEV_DIEPTSIZ11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ11_OFST 0x270
/* The address of the ALT_USB_DEV_DIEPTSIZ11 register. */
#define ALT_USB_DEV_DIEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ11_OFST))
/*
* Register : diepdma11
*
* Device IN Endpoint 11 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA11_DIEPDMA11
*
*/
/*
* Field : diepdma11
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA11_DIEPDMA11 field value from a register. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA11_DIEPDMA11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA11_DIEPDMA11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA11.
*/
struct ALT_USB_DEV_DIEPDMA11_s
{
uint32_t diepdma11 : 32; /* ALT_USB_DEV_DIEPDMA11_DIEPDMA11 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA11. */
typedef volatile struct ALT_USB_DEV_DIEPDMA11_s ALT_USB_DEV_DIEPDMA11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA11 register. */
#define ALT_USB_DEV_DIEPDMA11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA11_OFST 0x274
/* The address of the ALT_USB_DEV_DIEPDMA11 register. */
#define ALT_USB_DEV_DIEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA11_OFST))
/*
* Register : dtxfsts11
*
* Device IN Endpoint Transmit FIFO Status Register 11
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS11.
*/
struct ALT_USB_DEV_DTXFSTS11_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS11_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS11. */
typedef volatile struct ALT_USB_DEV_DTXFSTS11_s ALT_USB_DEV_DTXFSTS11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS11 register. */
#define ALT_USB_DEV_DTXFSTS11_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS11 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS11_OFST 0x278
/* The address of the ALT_USB_DEV_DTXFSTS11 register. */
#define ALT_USB_DEV_DTXFSTS11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS11_OFST))
/*
* Register : diepdmab11
*
* Device IN Endpoint 11 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11
*
*/
/*
* Field : diepdmab11
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB11.
*/
struct ALT_USB_DEV_DIEPDMAB11_s
{
const uint32_t diepdmab11 : 32; /* ALT_USB_DEV_DIEPDMAB11_DIEPDMAB11 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB11. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB11_s ALT_USB_DEV_DIEPDMAB11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB11 register. */
#define ALT_USB_DEV_DIEPDMAB11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB11 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB11_OFST 0x27c
/* The address of the ALT_USB_DEV_DIEPDMAB11 register. */
#define ALT_USB_DEV_DIEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB11_OFST))
/*
* Register : diepctl12
*
* Device Control IN Endpoint 12 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL12_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL12_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL12_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL12_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL12_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL12_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL12_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL12_MPS register field. */
#define ALT_USB_DEV_DIEPCTL12_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL12_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL12_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL12_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL12_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL12_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL12_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_DPID register field. */
#define ALT_USB_DEV_DIEPCTL12_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL12_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL12_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL12_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL12_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL12_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL12_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_STALL register field. */
#define ALT_USB_DEV_DIEPCTL12_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL12_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL12_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL12_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL12_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL12_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL12_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL12_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL12_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL12_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL12_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL12_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL12_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL12_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL12_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL12_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL12_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL12.
*/
struct ALT_USB_DEV_DIEPCTL12_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL12_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL12_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL12_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL12_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL12_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL12_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL12_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL12_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL12_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL12_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL12_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL12_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL12_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL12. */
typedef volatile struct ALT_USB_DEV_DIEPCTL12_s ALT_USB_DEV_DIEPCTL12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL12 register. */
#define ALT_USB_DEV_DIEPCTL12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL12_OFST 0x280
/* The address of the ALT_USB_DEV_DIEPCTL12 register. */
#define ALT_USB_DEV_DIEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL12_OFST))
/*
* Register : diepint12
*
* Device IN Endpoint 12 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT12_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT12_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT12_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT12_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT12_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT12_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TMO register field value. */
#define ALT_USB_DEV_DIEPINT12_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TMO register field value. */
#define ALT_USB_DEV_DIEPINT12_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT12_TMO register field. */
#define ALT_USB_DEV_DIEPINT12_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT12_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT12_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT12_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT12_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT12_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT12_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT12_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT12_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT12_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT12_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT12_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT12_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT12_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT12_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT12_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT12.
*/
struct ALT_USB_DEV_DIEPINT12_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT12_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT12_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT12_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT12_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT12_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT12_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT12_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT12_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT12_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT12_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT12_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT12_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT12_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT12_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT12. */
typedef volatile struct ALT_USB_DEV_DIEPINT12_s ALT_USB_DEV_DIEPINT12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT12 register. */
#define ALT_USB_DEV_DIEPINT12_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT12_OFST 0x288
/* The address of the ALT_USB_DEV_DIEPINT12 register. */
#define ALT_USB_DEV_DIEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT12_OFST))
/*
* Register : dieptsiz12
*
* Device IN Endpoint 12 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ12_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ12_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ12_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ12_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ12_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ12_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ12_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ12.
*/
struct ALT_USB_DEV_DIEPTSIZ12_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ12_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ12_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ12_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ12. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ12_s ALT_USB_DEV_DIEPTSIZ12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ12 register. */
#define ALT_USB_DEV_DIEPTSIZ12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ12_OFST 0x290
/* The address of the ALT_USB_DEV_DIEPTSIZ12 register. */
#define ALT_USB_DEV_DIEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ12_OFST))
/*
* Register : diepdma12
*
* Device IN Endpoint 12 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA12_DIEPDMA12
*
*/
/*
* Field : diepdma12
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA12_DIEPDMA12 field value from a register. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA12_DIEPDMA12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA12_DIEPDMA12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA12.
*/
struct ALT_USB_DEV_DIEPDMA12_s
{
uint32_t diepdma12 : 32; /* ALT_USB_DEV_DIEPDMA12_DIEPDMA12 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA12. */
typedef volatile struct ALT_USB_DEV_DIEPDMA12_s ALT_USB_DEV_DIEPDMA12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA12 register. */
#define ALT_USB_DEV_DIEPDMA12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA12_OFST 0x294
/* The address of the ALT_USB_DEV_DIEPDMA12 register. */
#define ALT_USB_DEV_DIEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA12_OFST))
/*
* Register : dtxfsts12
*
* Device IN Endpoint Transmit FIFO Status Register 12
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS12.
*/
struct ALT_USB_DEV_DTXFSTS12_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS12_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS12. */
typedef volatile struct ALT_USB_DEV_DTXFSTS12_s ALT_USB_DEV_DTXFSTS12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS12 register. */
#define ALT_USB_DEV_DTXFSTS12_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS12 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS12_OFST 0x298
/* The address of the ALT_USB_DEV_DTXFSTS12 register. */
#define ALT_USB_DEV_DTXFSTS12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS12_OFST))
/*
* Register : diepdmab12
*
* Device IN Endpoint 12 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12
*
*/
/*
* Field : diepdmab12
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB12.
*/
struct ALT_USB_DEV_DIEPDMAB12_s
{
const uint32_t diepdmab12 : 32; /* ALT_USB_DEV_DIEPDMAB12_DIEPDMAB12 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB12. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB12_s ALT_USB_DEV_DIEPDMAB12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB12 register. */
#define ALT_USB_DEV_DIEPDMAB12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB12 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB12_OFST 0x29c
/* The address of the ALT_USB_DEV_DIEPDMAB12 register. */
#define ALT_USB_DEV_DIEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB12_OFST))
/*
* Register : diepctl13
*
* Device Control IN Endpoint 13 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL13_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL13_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL13_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL13_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL13_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL13_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL13_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL13_MPS register field. */
#define ALT_USB_DEV_DIEPCTL13_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL13_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL13_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL13_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL13_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL13_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL13_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_DPID register field. */
#define ALT_USB_DEV_DIEPCTL13_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL13_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL13_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL13_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL13_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL13_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL13_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_STALL register field. */
#define ALT_USB_DEV_DIEPCTL13_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL13_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL13_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL13_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL13_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL13_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL13_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL13_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL13_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL13_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL13_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL13_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL13_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL13_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL13_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL13_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL13_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL13.
*/
struct ALT_USB_DEV_DIEPCTL13_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL13_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL13_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL13_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL13_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL13_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL13_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL13_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL13_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL13_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL13_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL13_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL13_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL13_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL13. */
typedef volatile struct ALT_USB_DEV_DIEPCTL13_s ALT_USB_DEV_DIEPCTL13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL13 register. */
#define ALT_USB_DEV_DIEPCTL13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL13_OFST 0x2a0
/* The address of the ALT_USB_DEV_DIEPCTL13 register. */
#define ALT_USB_DEV_DIEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL13_OFST))
/*
* Register : diepint13
*
* Device IN Endpoint 13 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT13_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT13_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT13_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT13_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT13_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT13_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TMO register field value. */
#define ALT_USB_DEV_DIEPINT13_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TMO register field value. */
#define ALT_USB_DEV_DIEPINT13_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT13_TMO register field. */
#define ALT_USB_DEV_DIEPINT13_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT13_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT13_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT13_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT13_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT13_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT13_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT13_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT13_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT13_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT13_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT13_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT13_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT13_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT13_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT13_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT13.
*/
struct ALT_USB_DEV_DIEPINT13_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT13_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT13_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT13_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT13_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT13_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT13_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT13_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT13_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT13_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT13_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT13_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT13_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT13_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT13_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT13. */
typedef volatile struct ALT_USB_DEV_DIEPINT13_s ALT_USB_DEV_DIEPINT13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT13 register. */
#define ALT_USB_DEV_DIEPINT13_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT13_OFST 0x2a8
/* The address of the ALT_USB_DEV_DIEPINT13 register. */
#define ALT_USB_DEV_DIEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT13_OFST))
/*
* Register : dieptsiz13
*
* Device IN Endpoint 13 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ13_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ13_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ13_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ13_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ13_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ13_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ13_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ13.
*/
struct ALT_USB_DEV_DIEPTSIZ13_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ13_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ13_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ13_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ13. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ13_s ALT_USB_DEV_DIEPTSIZ13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ13 register. */
#define ALT_USB_DEV_DIEPTSIZ13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ13_OFST 0x2b0
/* The address of the ALT_USB_DEV_DIEPTSIZ13 register. */
#define ALT_USB_DEV_DIEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ13_OFST))
/*
* Register : diepdma13
*
* Device IN Endpoint 13 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA13_DIEPDMA13
*
*/
/*
* Field : diepdma13
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA13_DIEPDMA13 field value from a register. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA13_DIEPDMA13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA13_DIEPDMA13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA13.
*/
struct ALT_USB_DEV_DIEPDMA13_s
{
uint32_t diepdma13 : 32; /* ALT_USB_DEV_DIEPDMA13_DIEPDMA13 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA13. */
typedef volatile struct ALT_USB_DEV_DIEPDMA13_s ALT_USB_DEV_DIEPDMA13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA13 register. */
#define ALT_USB_DEV_DIEPDMA13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA13_OFST 0x2b4
/* The address of the ALT_USB_DEV_DIEPDMA13 register. */
#define ALT_USB_DEV_DIEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA13_OFST))
/*
* Register : dtxfsts13
*
* Device IN Endpoint Transmit FIFO Status Register 13
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS13.
*/
struct ALT_USB_DEV_DTXFSTS13_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS13_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS13. */
typedef volatile struct ALT_USB_DEV_DTXFSTS13_s ALT_USB_DEV_DTXFSTS13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS13 register. */
#define ALT_USB_DEV_DTXFSTS13_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS13 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS13_OFST 0x2b8
/* The address of the ALT_USB_DEV_DTXFSTS13 register. */
#define ALT_USB_DEV_DTXFSTS13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS13_OFST))
/*
* Register : diepdmab13
*
* Device IN Endpoint 13 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13
*
*/
/*
* Field : diepdmab13
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB13.
*/
struct ALT_USB_DEV_DIEPDMAB13_s
{
const uint32_t diepdmab13 : 32; /* ALT_USB_DEV_DIEPDMAB13_DIEPDMAB13 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB13. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB13_s ALT_USB_DEV_DIEPDMAB13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB13 register. */
#define ALT_USB_DEV_DIEPDMAB13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB13 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB13_OFST 0x2bc
/* The address of the ALT_USB_DEV_DIEPDMAB13 register. */
#define ALT_USB_DEV_DIEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB13_OFST))
/*
* Register : diepctl14
*
* Device Control IN Endpoint 14 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL14_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL14_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL14_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL14_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL14_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL14_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL14_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL14_MPS register field. */
#define ALT_USB_DEV_DIEPCTL14_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL14_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL14_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL14_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL14_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL14_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL14_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_DPID register field. */
#define ALT_USB_DEV_DIEPCTL14_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL14_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL14_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL14_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL14_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL14_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL14_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_STALL register field. */
#define ALT_USB_DEV_DIEPCTL14_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL14_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL14_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL14_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL14_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL14_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL14_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL14_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL14_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL14_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL14_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL14_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL14_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL14_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL14_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL14_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL14_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL14.
*/
struct ALT_USB_DEV_DIEPCTL14_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL14_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL14_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL14_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL14_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL14_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL14_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL14_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL14_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL14_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL14_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL14_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL14_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL14_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL14. */
typedef volatile struct ALT_USB_DEV_DIEPCTL14_s ALT_USB_DEV_DIEPCTL14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL14 register. */
#define ALT_USB_DEV_DIEPCTL14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL14_OFST 0x2c0
/* The address of the ALT_USB_DEV_DIEPCTL14 register. */
#define ALT_USB_DEV_DIEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL14_OFST))
/*
* Register : diepint14
*
* Device IN Endpoint 14 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT14_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT14_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT14_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT14_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT14_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT14_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TMO register field value. */
#define ALT_USB_DEV_DIEPINT14_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TMO register field value. */
#define ALT_USB_DEV_DIEPINT14_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT14_TMO register field. */
#define ALT_USB_DEV_DIEPINT14_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT14_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT14_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT14_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT14_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT14_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT14_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT14_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT14_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT14_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT14_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT14_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT14_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT14_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT14_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT14_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT14.
*/
struct ALT_USB_DEV_DIEPINT14_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT14_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT14_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT14_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT14_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT14_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT14_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT14_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT14_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT14_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT14_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT14_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT14_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT14_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT14_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT14. */
typedef volatile struct ALT_USB_DEV_DIEPINT14_s ALT_USB_DEV_DIEPINT14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT14 register. */
#define ALT_USB_DEV_DIEPINT14_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT14_OFST 0x2c8
/* The address of the ALT_USB_DEV_DIEPINT14 register. */
#define ALT_USB_DEV_DIEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT14_OFST))
/*
* Register : dieptsiz14
*
* Device IN Endpoint 14 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ14_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ14_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ14_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ14_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ14_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ14_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ14_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ14.
*/
struct ALT_USB_DEV_DIEPTSIZ14_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ14_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ14_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ14_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ14. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ14_s ALT_USB_DEV_DIEPTSIZ14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ14 register. */
#define ALT_USB_DEV_DIEPTSIZ14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ14_OFST 0x2d0
/* The address of the ALT_USB_DEV_DIEPTSIZ14 register. */
#define ALT_USB_DEV_DIEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ14_OFST))
/*
* Register : diepdma14
*
* Device IN Endpoint 14 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA14_DIEPDMA14
*
*/
/*
* Field : diepdma14
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA14_DIEPDMA14 field value from a register. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA14_DIEPDMA14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA14_DIEPDMA14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA14.
*/
struct ALT_USB_DEV_DIEPDMA14_s
{
uint32_t diepdma14 : 32; /* ALT_USB_DEV_DIEPDMA14_DIEPDMA14 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA14. */
typedef volatile struct ALT_USB_DEV_DIEPDMA14_s ALT_USB_DEV_DIEPDMA14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA14 register. */
#define ALT_USB_DEV_DIEPDMA14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA14_OFST 0x2d4
/* The address of the ALT_USB_DEV_DIEPDMA14 register. */
#define ALT_USB_DEV_DIEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA14_OFST))
/*
* Register : dtxfsts14
*
* Device IN Endpoint Transmit FIFO Status Register 14
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS14.
*/
struct ALT_USB_DEV_DTXFSTS14_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS14_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS14. */
typedef volatile struct ALT_USB_DEV_DTXFSTS14_s ALT_USB_DEV_DTXFSTS14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS14 register. */
#define ALT_USB_DEV_DTXFSTS14_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS14 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS14_OFST 0x2d8
/* The address of the ALT_USB_DEV_DTXFSTS14 register. */
#define ALT_USB_DEV_DTXFSTS14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS14_OFST))
/*
* Register : diepdmab14
*
* Device IN Endpoint 14 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14
*
*/
/*
* Field : diepdmab14
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB14.
*/
struct ALT_USB_DEV_DIEPDMAB14_s
{
const uint32_t diepdmab14 : 32; /* ALT_USB_DEV_DIEPDMAB14_DIEPDMAB14 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB14. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB14_s ALT_USB_DEV_DIEPDMAB14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB14 register. */
#define ALT_USB_DEV_DIEPDMAB14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB14 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB14_OFST 0x2dc
/* The address of the ALT_USB_DEV_DIEPDMAB14 register. */
#define ALT_USB_DEV_DIEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB14_OFST))
/*
* Register : diepctl15
*
* Device Control IN Endpoint 15 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_EPTYPE
* [20] | ??? | 0x0 | *UNDEFINED*
* [21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_STALL
* [25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_TXFNUM
* [26] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DIEPCTL15_MPS register field. */
#define ALT_USB_DEV_DIEPCTL15_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_MPS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DIEPCTL15_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_USBACTEP field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DIEPCTL15_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DIEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DIEPCTL15_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DIEPCTL15_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_DPID register field. */
#define ALT_USB_DEV_DIEPCTL15_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_DPID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DIEPCTL15_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_NAKSTS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DIEPCTL15_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPTYPE field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DIEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DIEPCTL15_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_STALL register field. */
#define ALT_USB_DEV_DIEPCTL15_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_STALL field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DIEPCTL15_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : txfnum
*
* TxFIFO Number (TxFNum)
*
* Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic
*
* endpoints must map this to the corresponding Periodic TxFIFO number.
*
* 4'h0: Non-Periodic TxFIFO
*
* Others: Specified Periodic TxFIFO.number
*
* Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for
*
* applications such as mass storage. The core treats an IN endpoint as a non-
* periodic
*
* endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO
* must be
*
* allocated for an interrupt IN endpoint, and the number of this
*
* FIFO must be programmed into the TxFNum field. Configuring an interrupt IN
*
* endpoint as a non-periodic endpoint saves the extra periodic FIFO area.
*
* Dedicated FIFO Operationthese bits specify the FIFO number associated with this
*
* endpoint. Each active IN endpoint must be programmed to a separate FIFO number.
*
* This field is valid only for IN endpoints.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB 22
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB 25
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH 4
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK 0x03c00000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK 0xfc3fffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_TXFNUM field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22)
/* Produces a ALT_USB_DEV_DIEPCTL15_TXFNUM register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET(value) (((value) << 22) & 0x03c00000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_CNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DIEPCTL15_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SNAK field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DIEPCTL15_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD0PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DIEPCTL15_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_SETD1PID field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPCTL15_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPDIS field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DIEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPCTL15_EPENA field value from a register. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DIEPCTL15_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPCTL15.
*/
struct ALT_USB_DEV_DIEPCTL15_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DIEPCTL15_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DIEPCTL15_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DIEPCTL15_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DIEPCTL15_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DIEPCTL15_EPTYPE */
uint32_t : 1; /* *UNDEFINED* */
uint32_t stall : 1; /* ALT_USB_DEV_DIEPCTL15_STALL */
uint32_t txfnum : 4; /* ALT_USB_DEV_DIEPCTL15_TXFNUM */
uint32_t cnak : 1; /* ALT_USB_DEV_DIEPCTL15_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DIEPCTL15_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DIEPCTL15_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DIEPCTL15_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DIEPCTL15_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DIEPCTL15_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPCTL15. */
typedef volatile struct ALT_USB_DEV_DIEPCTL15_s ALT_USB_DEV_DIEPCTL15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPCTL15 register. */
#define ALT_USB_DEV_DIEPCTL15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPCTL15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPCTL15_OFST 0x2e0
/* The address of the ALT_USB_DEV_DIEPCTL15 register. */
#define ALT_USB_DEV_DIEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST))
/*
* Register : diepint15
*
* Device IN Endpoint 15 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:----------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_TMO
* [4] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
* [5] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INTKNEPMIS
* [6] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_INEPNAKEFF
* [7] | R | 0x1 | ALT_USB_DEV_DIEPINT15_TXFEMP
* [8] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
* [9] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DIEPINT15_NYETINTRPT
* [31:15] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DIEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DIEPINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DIEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DIEPINT15_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DIEPINT15_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DIEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_AHBERR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DIEPINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : timeout
*
* Timeout Condition (TimeOUT)
*
* In shared TX FIFO mode, applies to non-isochronous IN
*
* endpoints only.
*
* In dedicated FIFO mode, applies only to Control IN
*
* endpoints.
*
* In Scatter/Gather DMA mode, the TimeOUT interrupt is not
*
* asserted.
*
* Indicates that the core has detected a timeout condition on the
*
* USB For the last IN token on this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT15_TMO_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_TMO_E_ACT | 0x1 | Timeout interrupy
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_TMO_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TMO
*
* Timeout interrupy
*/
#define ALT_USB_DEV_DIEPINT15_TMO_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_MSB 3
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TMO register field value. */
#define ALT_USB_DEV_DIEPINT15_TMO_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TMO register field value. */
#define ALT_USB_DEV_DIEPINT15_TMO_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DIEPINT15_TMO register field. */
#define ALT_USB_DEV_DIEPINT15_TMO_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_TMO field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TMO_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DIEPINT15_TMO register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TMO_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : intkntxfemp
*
* IN Token Received When TxFIFO is Empty (INTknTXFEmp)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that an IN token was received when the associated
*
* TxFIFO (periodic/non-periodic) was empty. This interrupt is
*
* asserted on the endpoint For which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT | 0x1 | IN Token Received Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNTXFEMP
*
* IN Token Received Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_MSB 4
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNTXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DIEPINT15_INTKNTXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INTKNTXFEMP_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : intknepmis
*
* IN Token Received with EP Mismatch (INTknEPMis)
*
* Applies to non-periodic IN endpoints only.
*
* Indicates that the data in the top of the non-periodic TxFIFO
*
* belongs to an endpoint other than the one For which the IN token
*
* was received. This interrupt is asserted on the endpoint For
*
* which the IN token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT | 0x1 | IN Token Received with EP Mismatch interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INTKNEPMIS
*
* IN Token Received with EP Mismatch interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_MSB 5
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INTKNEPMIS field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DIEPINT15_INTKNEPMIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INTKNEPMIS_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : inepnakeff
*
* IN Endpoint NAK Effective (INEPNakEff)
*
* Applies to periodic IN endpoints only.
*
* This bit can be cleared when the application clears the IN
*
* endpoint NAK by writing to DIEPCTLn.CNAK.
*
* This interrupt indicates that the core has sampled the NAK bit
*
* Set (either by the application or by the core). The interrupt
*
* indicates that the IN endpoint NAK bit Set by the application has
*
* taken effect in the core.
*
* This interrupt does not guarantee that a NAK handshake is sent
*
* on the USB. A STALL bit takes priority over a NAK bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT | 0x1 | IN Endpoint NAK Effective interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_INEPNAKEFF
*
* IN Endpoint NAK Effective interrupt
*/
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_MSB 6
/* The width in bits of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_INEPNAKEFF field value from a register. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DIEPINT15_INEPNAKEFF register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_INEPNAKEFF_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : txfemp
*
* Transmit FIFO Empty (TxFEmp)
*
* This bit is valid only For IN Endpoints
*
* This interrupt is asserted when the TxFIFO For this endpoint is
*
* either half or completely empty. The half or completely empty
*
* status is determined by the TxFIFO Empty Level bit in the Core
*
* AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------
* ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT | 0x1 | Transmit FIFO Empty interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFEMP
*
* Transmit FIFO Empty interrupt
*/
#define ALT_USB_DEV_DIEPINT15_TXFEMP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_MSB 7
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFEMP register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFEMP register field. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_RESET 0x1
/* Extracts the ALT_USB_DEV_DIEPINT15_TXFEMP field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_DEV_DIEPINT15_TXFEMP register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TXFEMP_SET(value) (((value) << 7) & 0x00000080)
/*
* Field : txfifoundrn
*
* Fifo Underrun (TxfifoUndrn)
*
* Applies to IN endpoints Only
*
* This bit is valid only If thresholding is enabled. The core generates this
* interrupt when
*
* it detects a transmit FIFO underrun condition For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------------------
* ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT | 0x1 | Fifo Underrun interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN
*
* Fifo Underrun interrupt
*/
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_MSB 8
/* The width in bits of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN field value from a register. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DIEPINT15_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DIEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_BNAINTR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DIEPINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DIEPINT15_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DIEPINT15_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DIEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_BBLEERR field value from a register. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DIEPINT15_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DIEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DIEPINT15_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DIEPINT15_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DIEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPINT15_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DIEPINT15_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPINT15.
*/
struct ALT_USB_DEV_DIEPINT15_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DIEPINT15_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DIEPINT15_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DIEPINT15_AHBERR */
uint32_t timeout : 1; /* ALT_USB_DEV_DIEPINT15_TMO */
uint32_t intkntxfemp : 1; /* ALT_USB_DEV_DIEPINT15_INTKNTXFEMP */
uint32_t intknepmis : 1; /* ALT_USB_DEV_DIEPINT15_INTKNEPMIS */
uint32_t inepnakeff : 1; /* ALT_USB_DEV_DIEPINT15_INEPNAKEFF */
const uint32_t txfemp : 1; /* ALT_USB_DEV_DIEPINT15_TXFEMP */
uint32_t txfifoundrn : 1; /* ALT_USB_DEV_DIEPINT15_TXFIFOUNDRN */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DIEPINT15_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DIEPINT15_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DIEPINT15_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DIEPINT15_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DIEPINT15_NYETINTRPT */
uint32_t : 17; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPINT15. */
typedef volatile struct ALT_USB_DEV_DIEPINT15_s ALT_USB_DEV_DIEPINT15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPINT15 register. */
#define ALT_USB_DEV_DIEPINT15_RESET 0x00000080
/* The byte offset of the ALT_USB_DEV_DIEPINT15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPINT15_OFST 0x2e8
/* The address of the ALT_USB_DEV_DIEPINT15 register. */
#define ALT_USB_DEV_DIEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPINT15_OFST))
/*
* Register : dieptsiz15
*
* Device IN Endpoint 15 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_PKTCNT
* [30:29] | RW | 0x0 | ALT_USB_DEV_DIEPTSIZ15_MC
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet from the
*
* external memory is written to the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* Indicates the total number of USB packets that constitute the
*
* Transfer Size amount of data For endpoint 0.
*
* This field is decremented every time a packet (maximum size or
*
* short packet) is read from the TxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : mc
*
* Applies to IN endpoints only.
*
* For periodic IN endpoints, this field indicates the number of packets that must
* be transmitted per microframe on the USB. The core uses this field to calculate
* the data PID for isochronous IN endpoints.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It
* specifies the number of packets the core must fetchfor an IN endpoint before it
* switches to the endpoint pointed to by the Next Endpoint field of the Device
* Endpoint-n Control register (DIEPCTLn.NextEp)
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------
* ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE | 0x1 | 1 packet
* ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO | 0x2 | 2 packets
* ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
*
* 1 packet
*/
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTONE 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
*
* 2 packets
*/
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTWO 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DIEPTSIZ15_MC
*
* 3 packets
*/
#define ALT_USB_DEV_DIEPTSIZ15_MC_E_PKTTHREE 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_MSB 30
/* The width in bits of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DIEPTSIZ15_MC register field value. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15_MC register field. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPTSIZ15_MC field value from a register. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DIEPTSIZ15_MC register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPTSIZ15_MC_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPTSIZ15.
*/
struct ALT_USB_DEV_DIEPTSIZ15_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DIEPTSIZ15_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DIEPTSIZ15_PKTCNT */
uint32_t mc : 2; /* ALT_USB_DEV_DIEPTSIZ15_MC */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPTSIZ15. */
typedef volatile struct ALT_USB_DEV_DIEPTSIZ15_s ALT_USB_DEV_DIEPTSIZ15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPTSIZ15 register. */
#define ALT_USB_DEV_DIEPTSIZ15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPTSIZ15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPTSIZ15_OFST 0x2f0
/* The address of the ALT_USB_DEV_DIEPTSIZ15 register. */
#define ALT_USB_DEV_DIEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPTSIZ15_OFST))
/*
* Register : diepdma15
*
* Device IN Endpoint 15 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DIEPDMA15_DIEPDMA15
*
*/
/*
* Field : diepdma15
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMA15_DIEPDMA15 field value from a register. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMA15_DIEPDMA15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMA15_DIEPDMA15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMA15.
*/
struct ALT_USB_DEV_DIEPDMA15_s
{
uint32_t diepdma15 : 32; /* ALT_USB_DEV_DIEPDMA15_DIEPDMA15 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMA15. */
typedef volatile struct ALT_USB_DEV_DIEPDMA15_s ALT_USB_DEV_DIEPDMA15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMA15 register. */
#define ALT_USB_DEV_DIEPDMA15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMA15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMA15_OFST 0x2f4
/* The address of the ALT_USB_DEV_DIEPDMA15 register. */
#define ALT_USB_DEV_DIEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMA15_OFST))
/*
* Register : dtxfsts15
*
* Device IN Endpoint Transmit FIFO Status Register 15
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:-------|:--------------------------------------
* [15:0] | R | 0x2000 | ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : ineptxfspcavail
*
* IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)
*
* Indicates the amount of free space available in the Endpoint
*
* TxFIFO.
*
* Values are in terms of 32-bit words.
*
* 16'h0: Endpoint TxFIFO is full
*
* 16'h1: 1 word available
*
* 16'h2: 2 words available
*
* 16'hn: n words available (where 0 n 32,768)
*
* 16'h8000: 32,768 words available
*
* Others: Reserved
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_MSB 15
/* The width in bits of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_WIDTH 16
/* The mask used to set the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET_MSK 0x0000ffff
/* The mask used to clear the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_CLR_MSK 0xffff0000
/* The reset value of the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_RESET 0x2000
/* Extracts the ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL field value from a register. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL register field value suitable for setting the register. */
#define ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL_SET(value) (((value) << 0) & 0x0000ffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DTXFSTS15.
*/
struct ALT_USB_DEV_DTXFSTS15_s
{
const uint32_t ineptxfspcavail : 16; /* ALT_USB_DEV_DTXFSTS15_INEPTXFSPCAVAIL */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DTXFSTS15. */
typedef volatile struct ALT_USB_DEV_DTXFSTS15_s ALT_USB_DEV_DTXFSTS15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DTXFSTS15 register. */
#define ALT_USB_DEV_DTXFSTS15_RESET 0x00002000
/* The byte offset of the ALT_USB_DEV_DTXFSTS15 register from the beginning of the component. */
#define ALT_USB_DEV_DTXFSTS15_OFST 0x2f8
/* The address of the ALT_USB_DEV_DTXFSTS15 register. */
#define ALT_USB_DEV_DTXFSTS15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DTXFSTS15_OFST))
/*
* Register : diepdmab15
*
* Device IN Endpoint 15 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15
*
*/
/*
* Field : diepdmab15
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_MSB 31
/* The width in bits of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field is UNKNOWN. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_RESET 0x0
/* Extracts the ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 field value from a register. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DIEPDMAB15.
*/
struct ALT_USB_DEV_DIEPDMAB15_s
{
const uint32_t diepdmab15 : 32; /* ALT_USB_DEV_DIEPDMAB15_DIEPDMAB15 */
};
/* The typedef declaration for register ALT_USB_DEV_DIEPDMAB15. */
typedef volatile struct ALT_USB_DEV_DIEPDMAB15_s ALT_USB_DEV_DIEPDMAB15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DIEPDMAB15 register. */
#define ALT_USB_DEV_DIEPDMAB15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DIEPDMAB15 register from the beginning of the component. */
#define ALT_USB_DEV_DIEPDMAB15_OFST 0x2fc
/* The address of the ALT_USB_DEV_DIEPDMAB15 register. */
#define ALT_USB_DEV_DIEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPDMAB15_OFST))
/*
* Register : doepctl0
*
* Device Control OUT Endpoint 0 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [1:0] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_MPS
* [14:2] | ??? | 0x0 | *UNDEFINED*
* [15] | R | 0x1 | ALT_USB_DEV_DOEPCTL0_USBACTEP
* [16] | ??? | 0x0 | *UNDEFINED*
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_NAKSTS
* [19:18] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL0_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL0_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL0_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL0_SNAK
* [29:28] | ??? | 0x0 | *UNDEFINED*
* [30] | R | 0x0 | ALT_USB_DEV_DOEPCTL0_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL0_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The maximum packet size For control OUT endpoint 0 is the
*
* same as what is programmed in control IN Endpoint 0.
*
* 2'b00: 64 bytes
*
* 2'b01: 32 bytes
*
* 2'b10: 16 bytes
*
* 2'b11: 8 bytes
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 | 0x0 | 64 bytes
* ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 | 0x1 | 32 bytes
* ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 | 0x2 | 16 bytes
* ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 | 0x3 | 8 bytes
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
*
* 64 bytes
*/
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE64 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
*
* 32 bytes
*/
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE32 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
*
* 16 bytes
*/
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE16 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_MPS
*
* 8 bytes
*/
#define ALT_USB_DEV_DOEPCTL0_MPS_E_BYTE8 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL0_MPS_SET_MSK 0x00000003
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL0_MPS_CLR_MSK 0xfffffffc
/* The reset value of the ALT_USB_DEV_DOEPCTL0_MPS register field. */
#define ALT_USB_DEV_DOEPCTL0_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_MPS_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL0_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_MPS_SET(value) (((value) << 0) & 0x00000003)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* This bit is always Set to 1, indicating that a control endpoint 0 is
*
* always active in all configurations and interfaces.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------
* ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT | 0x1 | USB Active Endpoint 0
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_USBACTEP
*
* USB Active Endpoint 0
*/
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_RESET 0x1
/* Extracts the ALT_USB_DEV_DOEPCTL0_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL0_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based
*
* on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this
*
* endpoint.
*
* When either the application or the core sets this bit, the core
*
* stops receiving data, even If there is space in the RxFIFO to
*
* accommodate the incoming packet. Irrespective of this bit's
*
* setting, the core always responds to SETUP data packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL0_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* Hardcoded to 2'b00 For control.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT | 0x0 | Endpoint Control 0
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPTYPE
*
* Endpoint Control 0
*/
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_E_ACT 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* This bit configures the endpoint to Snoop mode. In Snoop mode,
*
* the core does not check the correctness of OUT packets before
*
* transferring them to application memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL0_SNP_E_DISD | 0x0 | Snoop Mode disabled
* ALT_USB_DEV_DOEPCTL0_SNP_E_END | 0x1 | Snoop Mode enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
*
* Snoop Mode disabled
*/
#define ALT_USB_DEV_DOEPCTL0_SNP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNP
*
* Snoop Mode enabled
*/
#define ALT_USB_DEV_DOEPCTL0_SNP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNP register field. */
#define ALT_USB_DEV_DOEPCTL0_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL0_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* The application can only Set this bit, and the core clears it, when
*
* a SETUP token is received For this endpoint. If a NAK bit or
*
* Global OUT NAK is Set along with this bit, the STALL bit takes
*
* priority. Irrespective of this bit's setting, the core always
*
* responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------
* ALT_USB_DEV_DOEPCTL0_STALL_E_INACT | 0x0 | No Stall
* ALT_USB_DEV_DOEPCTL0_STALL_E_ACT | 0x1 | Stall Handshake
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
*
* No Stall
*/
#define ALT_USB_DEV_DOEPCTL0_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_STALL
*
* Stall Handshake
*/
#define ALT_USB_DEV_DOEPCTL0_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL0_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL0_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_STALL register field. */
#define ALT_USB_DEV_DOEPCTL0_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL0_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR | 0x0 | No action
* ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
*
* No action
*/
#define ALT_USB_DEV_DOEPCTL0_CNAK_E_NOCLR 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL0_CNAK_E_CLR 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL0_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of
*
* NAK handshakes on an endpoint. The core can also Set bit on a
*
* Transfer Completed interrupt, or after a SETUP is received on
*
* the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET | 0x0 | No action
* ALT_USB_DEV_DOEPCTL0_SNAK_E_SET | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
*
* No action
*/
#define ALT_USB_DEV_DOEPCTL0_SNAK_E_NOSET 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL0_SNAK_E_SET 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL0_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* The application cannot disable control OUT endpoint 0.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT | 0x0 | No Endpoint disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPDIS
*
* No Endpoint disable
*/
#define ALT_USB_DEV_DOEPCTL0_EPDIS_E_INACT 0x0
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* When Scatter/Gather DMA mode is enabled, For OUT
*
* endpoints this bit indicates that the descriptor structure and
*
* data buffer to receive data is setup.
*
* When Scatter/Gather DMA mode is disabled(such as For
*
* buffer-pointer based DMA mode)this bit indicates that the
*
* application has allocated the memory to start receiving data
*
* from the USB.
*
* The core clears this bit before setting any of the following
*
* interrupts on this endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: In DMA mode, this bit must be Set For the core to transfer
*
* SETUP data packets into memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------
* ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT | 0x0 | No action
* ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT | 0x1 | Endpoint Enabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
*
* No action
*/
#define ALT_USB_DEV_DOEPCTL0_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL0_EPENA
*
* Endpoint Enabled
*/
#define ALT_USB_DEV_DOEPCTL0_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL0_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL0_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL0_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL0_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL0_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL0.
*/
struct ALT_USB_DEV_DOEPCTL0_s
{
const uint32_t mps : 2; /* ALT_USB_DEV_DOEPCTL0_MPS */
uint32_t : 13; /* *UNDEFINED* */
const uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL0_USBACTEP */
uint32_t : 1; /* *UNDEFINED* */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL0_NAKSTS */
const uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL0_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL0_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL0_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL0_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL0_SNAK */
uint32_t : 2; /* *UNDEFINED* */
const uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL0_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL0_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL0. */
typedef volatile struct ALT_USB_DEV_DOEPCTL0_s ALT_USB_DEV_DOEPCTL0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL0 register. */
#define ALT_USB_DEV_DOEPCTL0_RESET 0x00008000
/* The byte offset of the ALT_USB_DEV_DOEPCTL0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL0_OFST 0x300
/* The address of the ALT_USB_DEV_DOEPCTL0 register. */
#define ALT_USB_DEV_DOEPCTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL0_OFST))
/*
* Register : doepint0
*
* Device OUT Endpoint 0 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT0_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT0_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT0_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT0_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT0_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT0_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT0_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT0_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT0_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT0_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT0_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT0_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT0_SETUP register field. */
#define ALT_USB_DEV_DOEPINT0_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT0_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT0_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT0_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled.
*
* This interrupt is asserted when the core detects an overflow
*
* or a CRC error For non-Isochronous OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT0_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT0_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT0_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT0_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT0_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT0_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT0_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT0_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT0_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT0_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT0_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT0_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT0_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT0_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT0_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT0_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT0_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT0.
*/
struct ALT_USB_DEV_DOEPINT0_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT0_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT0_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT0_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT0_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT0_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT0_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT0_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT0_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT0_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT0_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT0_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT0_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT0_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT0_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT0. */
typedef volatile struct ALT_USB_DEV_DOEPINT0_s ALT_USB_DEV_DOEPINT0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT0 register. */
#define ALT_USB_DEV_DOEPINT0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT0_OFST 0x308
/* The address of the ALT_USB_DEV_DOEPINT0 register. */
#define ALT_USB_DEV_DOEPINT0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT0_OFST))
/*
* Register : doeptsiz0
*
* Device OUT Endpoint 0 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [6:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_XFERSIZE
* [18:7] | ??? | 0x0 | *UNDEFINED*
* [19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_PKTCNT
* [28:20] | ??? | 0x0 | *UNDEFINED*
* [30:29] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ0_SUPCNT
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_WIDTH 7
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET_MSK 0x0000007f
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_CLR_MSK 0xffffff80
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_GET(value) (((value) & 0x0000007f) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_XFERSIZE_SET(value) (((value) << 0) & 0x0000007f)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET_MSK 0x00080000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_CLR_MSK 0xfff7ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_PKTCNT_SET(value) (((value) << 19) & 0x00080000)
/*
* Field : supcnt
*
* SETUP Packet Count (SUPCnt)
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT | 0x1 | 1 packet
* ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT | 0x2 | 2 packets
* ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT | 0x3 | 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
*
* 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_ONEPKT 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
*
* 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_TWOPKT 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ0_SUPCNT
*
* 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_E_THREEPKT 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ0_SUPCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ0_SUPCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ0_SUPCNT_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ0.
*/
struct ALT_USB_DEV_DOEPTSIZ0_s
{
uint32_t xfersize : 7; /* ALT_USB_DEV_DOEPTSIZ0_XFERSIZE */
uint32_t : 12; /* *UNDEFINED* */
uint32_t pktcnt : 1; /* ALT_USB_DEV_DOEPTSIZ0_PKTCNT */
uint32_t : 9; /* *UNDEFINED* */
uint32_t supcnt : 2; /* ALT_USB_DEV_DOEPTSIZ0_SUPCNT */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ0. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ0_s ALT_USB_DEV_DOEPTSIZ0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ0 register. */
#define ALT_USB_DEV_DOEPTSIZ0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ0_OFST 0x310
/* The address of the ALT_USB_DEV_DOEPTSIZ0 register. */
#define ALT_USB_DEV_DOEPTSIZ0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ0_OFST))
/*
* Register : doepdma0
*
* Device OUT Endpoint 0 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA0_DOEPDMA0
*
*/
/*
* Field : doepdma0
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA0_DOEPDMA0 field value from a register. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA0_DOEPDMA0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA0_DOEPDMA0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA0.
*/
struct ALT_USB_DEV_DOEPDMA0_s
{
uint32_t doepdma0 : 32; /* ALT_USB_DEV_DOEPDMA0_DOEPDMA0 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA0. */
typedef volatile struct ALT_USB_DEV_DOEPDMA0_s ALT_USB_DEV_DOEPDMA0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA0 register. */
#define ALT_USB_DEV_DOEPDMA0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA0_OFST 0x314
/* The address of the ALT_USB_DEV_DOEPDMA0 register. */
#define ALT_USB_DEV_DOEPDMA0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA0_OFST))
/*
* Register : doepdmab0
*
* Device OUT Endpoint 16 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0
*
*/
/*
* Field : doepdmab0
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB0.
*/
struct ALT_USB_DEV_DOEPDMAB0_s
{
const uint32_t doepdmab0 : 32; /* ALT_USB_DEV_DOEPDMAB0_DOEPDMAB0 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB0. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB0_s ALT_USB_DEV_DOEPDMAB0_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB0 register. */
#define ALT_USB_DEV_DOEPDMAB0_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB0 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB0_OFST 0x31c
/* The address of the ALT_USB_DEV_DOEPDMAB0 register. */
#define ALT_USB_DEV_DOEPDMAB0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB0_OFST))
/*
* Register : doepctl1
*
* Device Control OUT Endpoint 1 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL1_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL1_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL1_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL1_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL1_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL1_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL1_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL1_MPS register field. */
#define ALT_USB_DEV_DOEPCTL1_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL1_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL1_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL1_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL1_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL1_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL1_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL1_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL1_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_DPID register field. */
#define ALT_USB_DEV_DOEPCTL1_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL1_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL1_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL1_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL1_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL1_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL1_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNP register field. */
#define ALT_USB_DEV_DOEPCTL1_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL1_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL1_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL1_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL1_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL1_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL1_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL1_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_STALL register field. */
#define ALT_USB_DEV_DOEPCTL1_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL1_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL1_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL1_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL1_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL1_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL1_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL1_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL1_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL1_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL1_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL1_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL1_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL1_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL1_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL1_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL1_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL1_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL1_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL1.
*/
struct ALT_USB_DEV_DOEPCTL1_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL1_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL1_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL1_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL1_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL1_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL1_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL1_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL1_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL1_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL1_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL1_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL1_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL1_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL1. */
typedef volatile struct ALT_USB_DEV_DOEPCTL1_s ALT_USB_DEV_DOEPCTL1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL1 register. */
#define ALT_USB_DEV_DOEPCTL1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL1_OFST 0x320
/* The address of the ALT_USB_DEV_DOEPCTL1 register. */
#define ALT_USB_DEV_DOEPCTL1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL1_OFST))
/*
* Register : doepint1
*
* Device OUT Endpoint 1 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT1_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT1_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT1_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT1_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT1_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT1_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT1_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT1_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT1_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT1_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT1_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT1_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT1_SETUP register field. */
#define ALT_USB_DEV_DOEPINT1_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT1_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT1_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT1_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT1_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT1_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT1_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT1_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT1_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT1_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT1_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT1_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT1_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT1_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT1_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT1_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT1_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT1_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT1_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT1_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT1_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT1.
*/
struct ALT_USB_DEV_DOEPINT1_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT1_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT1_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT1_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT1_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT1_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT1_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT1_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT1_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT1_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT1_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT1_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT1_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT1_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT1_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT1. */
typedef volatile struct ALT_USB_DEV_DOEPINT1_s ALT_USB_DEV_DOEPINT1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT1 register. */
#define ALT_USB_DEV_DOEPINT1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT1_OFST 0x328
/* The address of the ALT_USB_DEV_DOEPINT1 register. */
#define ALT_USB_DEV_DOEPINT1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT1_OFST))
/*
* Register : doeptsiz1
*
* Device OUT Endpoint 1 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ1_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ1_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ1_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ1_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ1_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ1_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ1_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ1.
*/
struct ALT_USB_DEV_DOEPTSIZ1_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ1_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ1_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ1_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ1. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ1_s ALT_USB_DEV_DOEPTSIZ1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ1 register. */
#define ALT_USB_DEV_DOEPTSIZ1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ1_OFST 0x330
/* The address of the ALT_USB_DEV_DOEPTSIZ1 register. */
#define ALT_USB_DEV_DOEPTSIZ1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ1_OFST))
/*
* Register : doepdma1
*
* Device OUT Endpoint 1 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA1_DOEPDMA1
*
*/
/*
* Field : doepdma1
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA1_DOEPDMA1 field value from a register. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA1_DOEPDMA1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA1_DOEPDMA1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA1.
*/
struct ALT_USB_DEV_DOEPDMA1_s
{
uint32_t doepdma1 : 32; /* ALT_USB_DEV_DOEPDMA1_DOEPDMA1 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA1. */
typedef volatile struct ALT_USB_DEV_DOEPDMA1_s ALT_USB_DEV_DOEPDMA1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA1 register. */
#define ALT_USB_DEV_DOEPDMA1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA1_OFST 0x334
/* The address of the ALT_USB_DEV_DOEPDMA1 register. */
#define ALT_USB_DEV_DOEPDMA1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA1_OFST))
/*
* Register : doepdmab1
*
* Device OUT Endpoint 1 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1
*
*/
/*
* Field : doepdmab1
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB1.
*/
struct ALT_USB_DEV_DOEPDMAB1_s
{
const uint32_t doepdmab1 : 32; /* ALT_USB_DEV_DOEPDMAB1_DOEPDMAB1 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB1. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB1_s ALT_USB_DEV_DOEPDMAB1_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB1 register. */
#define ALT_USB_DEV_DOEPDMAB1_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB1 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB1_OFST 0x33c
/* The address of the ALT_USB_DEV_DOEPDMAB1 register. */
#define ALT_USB_DEV_DOEPDMAB1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB1_OFST))
/*
* Register : doepctl2
*
* Device Control OUT Endpoint 2 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL2_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL2_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL2_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL2_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL2_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL2_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL2_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL2_MPS register field. */
#define ALT_USB_DEV_DOEPCTL2_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL2_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL2_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL2_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL2_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL2_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL2_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL2_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL2_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_DPID register field. */
#define ALT_USB_DEV_DOEPCTL2_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL2_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL2_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL2_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL2_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL2_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL2_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNP register field. */
#define ALT_USB_DEV_DOEPCTL2_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL2_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL2_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL2_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL2_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL2_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL2_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL2_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_STALL register field. */
#define ALT_USB_DEV_DOEPCTL2_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL2_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL2_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL2_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL2_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL2_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL2_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL2_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL2_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL2_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL2_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL2_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL2_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL2_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL2_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL2_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL2_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL2_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL2_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL2.
*/
struct ALT_USB_DEV_DOEPCTL2_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL2_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL2_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL2_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL2_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL2_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL2_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL2_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL2_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL2_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL2_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL2_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL2_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL2_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL2. */
typedef volatile struct ALT_USB_DEV_DOEPCTL2_s ALT_USB_DEV_DOEPCTL2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL2 register. */
#define ALT_USB_DEV_DOEPCTL2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL2_OFST 0x340
/* The address of the ALT_USB_DEV_DOEPCTL2 register. */
#define ALT_USB_DEV_DOEPCTL2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL2_OFST))
/*
* Register : doepint2
*
* Device OUT Endpoint 2 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT2_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT2_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT2_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT2_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT2_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT2_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT2_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT2_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT2_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT2_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT2_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT2_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT2_SETUP register field. */
#define ALT_USB_DEV_DOEPINT2_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT2_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT2_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT2_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT2_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT2_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT2_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT2_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT2_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT2_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT2_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT2_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT2_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT2_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT2_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT2_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT2_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT2_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT2_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT2_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT2_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT2.
*/
struct ALT_USB_DEV_DOEPINT2_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT2_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT2_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT2_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT2_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT2_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT2_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT2_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT2_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT2_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT2_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT2_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT2_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT2_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT2_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT2. */
typedef volatile struct ALT_USB_DEV_DOEPINT2_s ALT_USB_DEV_DOEPINT2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT2 register. */
#define ALT_USB_DEV_DOEPINT2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT2_OFST 0x348
/* The address of the ALT_USB_DEV_DOEPINT2 register. */
#define ALT_USB_DEV_DOEPINT2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT2_OFST))
/*
* Register : doeptsiz2
*
* Device OUT Endpoint 2 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ2_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ2_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ2_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ2_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ2_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ2_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ2_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ2.
*/
struct ALT_USB_DEV_DOEPTSIZ2_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ2_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ2_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ2_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ2. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ2_s ALT_USB_DEV_DOEPTSIZ2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ2 register. */
#define ALT_USB_DEV_DOEPTSIZ2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ2_OFST 0x350
/* The address of the ALT_USB_DEV_DOEPTSIZ2 register. */
#define ALT_USB_DEV_DOEPTSIZ2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ2_OFST))
/*
* Register : doepdma2
*
* Device OUT Endpoint 2 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA2_DOEPDMA2
*
*/
/*
* Field : doepdma2
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA2_DOEPDMA2 field value from a register. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA2_DOEPDMA2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA2_DOEPDMA2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA2.
*/
struct ALT_USB_DEV_DOEPDMA2_s
{
uint32_t doepdma2 : 32; /* ALT_USB_DEV_DOEPDMA2_DOEPDMA2 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA2. */
typedef volatile struct ALT_USB_DEV_DOEPDMA2_s ALT_USB_DEV_DOEPDMA2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA2 register. */
#define ALT_USB_DEV_DOEPDMA2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA2_OFST 0x354
/* The address of the ALT_USB_DEV_DOEPDMA2 register. */
#define ALT_USB_DEV_DOEPDMA2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA2_OFST))
/*
* Register : doepdmab2
*
* Device OUT Endpoint 2 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2
*
*/
/*
* Field : doepdmab2
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB2.
*/
struct ALT_USB_DEV_DOEPDMAB2_s
{
const uint32_t doepdmab2 : 32; /* ALT_USB_DEV_DOEPDMAB2_DOEPDMAB2 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB2. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB2_s ALT_USB_DEV_DOEPDMAB2_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB2 register. */
#define ALT_USB_DEV_DOEPDMAB2_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB2 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB2_OFST 0x35c
/* The address of the ALT_USB_DEV_DOEPDMAB2 register. */
#define ALT_USB_DEV_DOEPDMAB2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB2_OFST))
/*
* Register : doepctl3
*
* Device Control OUT Endpoint 3 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL3_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL3_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL3_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL3_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL3_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL3_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL3_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL3_MPS register field. */
#define ALT_USB_DEV_DOEPCTL3_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL3_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL3_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL3_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL3_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL3_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL3_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL3_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL3_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_DPID register field. */
#define ALT_USB_DEV_DOEPCTL3_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL3_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL3_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL3_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL3_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL3_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL3_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNP register field. */
#define ALT_USB_DEV_DOEPCTL3_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL3_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL3_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL3_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL3_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL3_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL3_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL3_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_STALL register field. */
#define ALT_USB_DEV_DOEPCTL3_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL3_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL3_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL3_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL3_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL3_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL3_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL3_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL3_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL3_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL3_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL3_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL3_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL3_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL3_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL3_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL3_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL3_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL3_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL3.
*/
struct ALT_USB_DEV_DOEPCTL3_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL3_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL3_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL3_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL3_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL3_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL3_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL3_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL3_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL3_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL3_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL3_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL3_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL3_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL3. */
typedef volatile struct ALT_USB_DEV_DOEPCTL3_s ALT_USB_DEV_DOEPCTL3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL3 register. */
#define ALT_USB_DEV_DOEPCTL3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL3_OFST 0x360
/* The address of the ALT_USB_DEV_DOEPCTL3 register. */
#define ALT_USB_DEV_DOEPCTL3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL3_OFST))
/*
* Register : doepint3
*
* Device OUT Endpoint 3 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT3_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT3_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT3_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT3_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT3_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT3_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT3_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT3_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT3_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT3_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT3_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT3_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT3_SETUP register field. */
#define ALT_USB_DEV_DOEPINT3_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT3_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT3_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT3_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT3_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT3_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT3_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT3_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT3_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT3_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT3_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT3_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT3_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT3_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT3_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT3_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT3_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT3_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT3_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT3_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT3_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT3.
*/
struct ALT_USB_DEV_DOEPINT3_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT3_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT3_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT3_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT3_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT3_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT3_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT3_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT3_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT3_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT3_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT3_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT3_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT3_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT3_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT3. */
typedef volatile struct ALT_USB_DEV_DOEPINT3_s ALT_USB_DEV_DOEPINT3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT3 register. */
#define ALT_USB_DEV_DOEPINT3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT3_OFST 0x368
/* The address of the ALT_USB_DEV_DOEPINT3 register. */
#define ALT_USB_DEV_DOEPINT3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT3_OFST))
/*
* Register : doeptsiz3
*
* Device OUT Endpoint 3 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ3_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ3_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ3_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ3_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ3_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ3_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ3_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ3.
*/
struct ALT_USB_DEV_DOEPTSIZ3_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ3_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ3_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ3_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ3. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ3_s ALT_USB_DEV_DOEPTSIZ3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ3 register. */
#define ALT_USB_DEV_DOEPTSIZ3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ3_OFST 0x370
/* The address of the ALT_USB_DEV_DOEPTSIZ3 register. */
#define ALT_USB_DEV_DOEPTSIZ3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ3_OFST))
/*
* Register : doepdma3
*
* Device OUT Endpoint 3 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA3_DOEPDMA3
*
*/
/*
* Field : doepdma3
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA3_DOEPDMA3 field value from a register. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA3_DOEPDMA3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA3_DOEPDMA3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA3.
*/
struct ALT_USB_DEV_DOEPDMA3_s
{
uint32_t doepdma3 : 32; /* ALT_USB_DEV_DOEPDMA3_DOEPDMA3 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA3. */
typedef volatile struct ALT_USB_DEV_DOEPDMA3_s ALT_USB_DEV_DOEPDMA3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA3 register. */
#define ALT_USB_DEV_DOEPDMA3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA3_OFST 0x374
/* The address of the ALT_USB_DEV_DOEPDMA3 register. */
#define ALT_USB_DEV_DOEPDMA3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA3_OFST))
/*
* Register : doepdmab3
*
* Device OUT Endpoint 3 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3
*
*/
/*
* Field : doepdmab3
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB3.
*/
struct ALT_USB_DEV_DOEPDMAB3_s
{
const uint32_t doepdmab3 : 32; /* ALT_USB_DEV_DOEPDMAB3_DOEPDMAB3 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB3. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB3_s ALT_USB_DEV_DOEPDMAB3_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB3 register. */
#define ALT_USB_DEV_DOEPDMAB3_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB3 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB3_OFST 0x37c
/* The address of the ALT_USB_DEV_DOEPDMAB3 register. */
#define ALT_USB_DEV_DOEPDMAB3_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB3_OFST))
/*
* Register : doepctl4
*
* Device Control OUT Endpoint 4 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL4_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL4_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL4_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL4_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL4_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL4_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL4_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL4_MPS register field. */
#define ALT_USB_DEV_DOEPCTL4_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL4_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL4_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL4_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL4_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL4_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL4_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL4_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL4_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_DPID register field. */
#define ALT_USB_DEV_DOEPCTL4_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL4_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL4_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL4_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL4_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL4_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL4_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNP register field. */
#define ALT_USB_DEV_DOEPCTL4_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL4_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL4_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL4_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL4_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL4_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL4_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL4_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_STALL register field. */
#define ALT_USB_DEV_DOEPCTL4_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL4_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL4_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL4_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL4_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL4_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL4_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL4_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL4_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL4_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL4_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL4_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL4_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL4_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL4_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL4_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL4_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL4_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL4_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL4.
*/
struct ALT_USB_DEV_DOEPCTL4_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL4_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL4_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL4_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL4_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL4_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL4_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL4_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL4_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL4_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL4_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL4_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL4_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL4_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL4. */
typedef volatile struct ALT_USB_DEV_DOEPCTL4_s ALT_USB_DEV_DOEPCTL4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL4 register. */
#define ALT_USB_DEV_DOEPCTL4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL4_OFST 0x380
/* The address of the ALT_USB_DEV_DOEPCTL4 register. */
#define ALT_USB_DEV_DOEPCTL4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL4_OFST))
/*
* Register : doepint4
*
* Device OUT Endpoint 4 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT4_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT4_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT4_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT4_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT4_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT4_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT4_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT4_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT4_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT4_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT4_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT4_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT4_SETUP register field. */
#define ALT_USB_DEV_DOEPINT4_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT4_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT4_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT4_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT4_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT4_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT4_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT4_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT4_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT4_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT4_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT4_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT4_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT4_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT4_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT4_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT4_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT4_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT4_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT4_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT4_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT4.
*/
struct ALT_USB_DEV_DOEPINT4_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT4_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT4_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT4_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT4_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT4_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT4_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT4_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT4_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT4_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT4_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT4_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT4_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT4_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT4_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT4. */
typedef volatile struct ALT_USB_DEV_DOEPINT4_s ALT_USB_DEV_DOEPINT4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT4 register. */
#define ALT_USB_DEV_DOEPINT4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT4_OFST 0x388
/* The address of the ALT_USB_DEV_DOEPINT4 register. */
#define ALT_USB_DEV_DOEPINT4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT4_OFST))
/*
* Register : doeptsiz4
*
* Device OUT Endpoint 4 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ4_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ4_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ4_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ4_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ4_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ4_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ4_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ4.
*/
struct ALT_USB_DEV_DOEPTSIZ4_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ4_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ4_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ4_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ4. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ4_s ALT_USB_DEV_DOEPTSIZ4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ4 register. */
#define ALT_USB_DEV_DOEPTSIZ4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ4_OFST 0x390
/* The address of the ALT_USB_DEV_DOEPTSIZ4 register. */
#define ALT_USB_DEV_DOEPTSIZ4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ4_OFST))
/*
* Register : doepdma4
*
* Device OUT Endpoint 4 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA4_DOEPDMA4
*
*/
/*
* Field : doepdma4
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA4_DOEPDMA4 field value from a register. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA4_DOEPDMA4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA4_DOEPDMA4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA4.
*/
struct ALT_USB_DEV_DOEPDMA4_s
{
uint32_t doepdma4 : 32; /* ALT_USB_DEV_DOEPDMA4_DOEPDMA4 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA4. */
typedef volatile struct ALT_USB_DEV_DOEPDMA4_s ALT_USB_DEV_DOEPDMA4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA4 register. */
#define ALT_USB_DEV_DOEPDMA4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA4_OFST 0x394
/* The address of the ALT_USB_DEV_DOEPDMA4 register. */
#define ALT_USB_DEV_DOEPDMA4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA4_OFST))
/*
* Register : doepdmab4
*
* Device OUT Endpoint 4 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4
*
*/
/*
* Field : doepdmab4
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB4.
*/
struct ALT_USB_DEV_DOEPDMAB4_s
{
const uint32_t doepdmab4 : 32; /* ALT_USB_DEV_DOEPDMAB4_DOEPDMAB4 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB4. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB4_s ALT_USB_DEV_DOEPDMAB4_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB4 register. */
#define ALT_USB_DEV_DOEPDMAB4_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB4 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB4_OFST 0x39c
/* The address of the ALT_USB_DEV_DOEPDMAB4 register. */
#define ALT_USB_DEV_DOEPDMAB4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB4_OFST))
/*
* Register : doepctl5
*
* Device Control OUT Endpoint 5 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL5_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL5_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL5_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL5_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL5_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL5_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL5_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL5_MPS register field. */
#define ALT_USB_DEV_DOEPCTL5_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL5_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL5_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL5_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL5_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL5_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL5_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL5_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL5_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_DPID register field. */
#define ALT_USB_DEV_DOEPCTL5_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL5_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL5_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL5_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL5_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL5_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL5_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNP register field. */
#define ALT_USB_DEV_DOEPCTL5_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL5_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL5_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL5_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL5_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL5_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL5_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL5_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_STALL register field. */
#define ALT_USB_DEV_DOEPCTL5_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL5_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL5_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL5_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL5_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL5_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL5_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL5_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL5_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL5_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL5_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL5_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL5_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL5_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL5_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL5_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL5_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL5_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL5_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL5.
*/
struct ALT_USB_DEV_DOEPCTL5_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL5_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL5_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL5_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL5_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL5_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL5_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL5_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL5_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL5_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL5_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL5_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL5_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL5_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL5. */
typedef volatile struct ALT_USB_DEV_DOEPCTL5_s ALT_USB_DEV_DOEPCTL5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL5 register. */
#define ALT_USB_DEV_DOEPCTL5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL5_OFST 0x3a0
/* The address of the ALT_USB_DEV_DOEPCTL5 register. */
#define ALT_USB_DEV_DOEPCTL5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL5_OFST))
/*
* Register : doepint5
*
* Device OUT Endpoint 5 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT5_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT5_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT5_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT5_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT5_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT5_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT5_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT5_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT5_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT5_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT5_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT5_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT5_SETUP register field. */
#define ALT_USB_DEV_DOEPINT5_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT5_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT5_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT5_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT5_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT5_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT5_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT5_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT5_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT5_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT5_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT5_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT5_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT5_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT5_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT5_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT5_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT5_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT5_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT5_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT5_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT5.
*/
struct ALT_USB_DEV_DOEPINT5_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT5_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT5_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT5_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT5_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT5_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT5_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT5_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT5_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT5_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT5_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT5_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT5_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT5_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT5_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT5. */
typedef volatile struct ALT_USB_DEV_DOEPINT5_s ALT_USB_DEV_DOEPINT5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT5 register. */
#define ALT_USB_DEV_DOEPINT5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT5_OFST 0x3a8
/* The address of the ALT_USB_DEV_DOEPINT5 register. */
#define ALT_USB_DEV_DOEPINT5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT5_OFST))
/*
* Register : doeptsiz5
*
* Device OUT Endpoint 5 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ5_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ5_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ5_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ5_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ5_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ5_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ5_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ5.
*/
struct ALT_USB_DEV_DOEPTSIZ5_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ5_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ5_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ5_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ5. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ5_s ALT_USB_DEV_DOEPTSIZ5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ5 register. */
#define ALT_USB_DEV_DOEPTSIZ5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ5_OFST 0x3b0
/* The address of the ALT_USB_DEV_DOEPTSIZ5 register. */
#define ALT_USB_DEV_DOEPTSIZ5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ5_OFST))
/*
* Register : doepdma5
*
* Device OUT Endpoint 5 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA5_DOEPDMA5
*
*/
/*
* Field : doepdma5
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA5_DOEPDMA5 field value from a register. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA5_DOEPDMA5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA5_DOEPDMA5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA5.
*/
struct ALT_USB_DEV_DOEPDMA5_s
{
uint32_t doepdma5 : 32; /* ALT_USB_DEV_DOEPDMA5_DOEPDMA5 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA5. */
typedef volatile struct ALT_USB_DEV_DOEPDMA5_s ALT_USB_DEV_DOEPDMA5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA5 register. */
#define ALT_USB_DEV_DOEPDMA5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA5_OFST 0x3b4
/* The address of the ALT_USB_DEV_DOEPDMA5 register. */
#define ALT_USB_DEV_DOEPDMA5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA5_OFST))
/*
* Register : doepdmab5
*
* Device OUT Endpoint 5 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5
*
*/
/*
* Field : doepdmab5
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB5.
*/
struct ALT_USB_DEV_DOEPDMAB5_s
{
const uint32_t doepdmab5 : 32; /* ALT_USB_DEV_DOEPDMAB5_DOEPDMAB5 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB5. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB5_s ALT_USB_DEV_DOEPDMAB5_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB5 register. */
#define ALT_USB_DEV_DOEPDMAB5_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB5 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB5_OFST 0x3bc
/* The address of the ALT_USB_DEV_DOEPDMAB5 register. */
#define ALT_USB_DEV_DOEPDMAB5_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB5_OFST))
/*
* Register : doepctl6
*
* Device Control OUT Endpoint 6 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL6_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL6_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL6_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL6_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL6_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL6_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL6_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL6_MPS register field. */
#define ALT_USB_DEV_DOEPCTL6_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL6_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL6_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL6_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL6_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL6_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL6_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL6_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL6_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_DPID register field. */
#define ALT_USB_DEV_DOEPCTL6_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL6_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL6_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL6_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL6_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL6_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL6_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNP register field. */
#define ALT_USB_DEV_DOEPCTL6_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL6_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL6_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL6_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL6_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL6_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL6_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL6_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_STALL register field. */
#define ALT_USB_DEV_DOEPCTL6_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL6_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL6_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL6_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL6_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL6_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL6_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL6_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL6_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL6_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL6_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL6_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL6_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL6_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL6_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL6_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL6_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL6_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL6_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL6.
*/
struct ALT_USB_DEV_DOEPCTL6_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL6_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL6_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL6_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL6_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL6_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL6_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL6_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL6_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL6_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL6_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL6_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL6_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL6_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL6. */
typedef volatile struct ALT_USB_DEV_DOEPCTL6_s ALT_USB_DEV_DOEPCTL6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL6 register. */
#define ALT_USB_DEV_DOEPCTL6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL6_OFST 0x3c0
/* The address of the ALT_USB_DEV_DOEPCTL6 register. */
#define ALT_USB_DEV_DOEPCTL6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL6_OFST))
/*
* Register : doepint6
*
* Device OUT Endpoint 6 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT6_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT6_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT6_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT6_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT6_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT6_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT6_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT6_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT6_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT6_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT6_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT6_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT6_SETUP register field. */
#define ALT_USB_DEV_DOEPINT6_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT6_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT6_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT6_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT6_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT6_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT6_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT6_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT6_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT6_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT6_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT6_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT6_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT6_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT6_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT6_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT6_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT6_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT6_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT6_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT6_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT6.
*/
struct ALT_USB_DEV_DOEPINT6_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT6_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT6_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT6_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT6_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT6_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT6_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT6_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT6_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT6_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT6_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT6_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT6_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT6_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT6_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT6. */
typedef volatile struct ALT_USB_DEV_DOEPINT6_s ALT_USB_DEV_DOEPINT6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT6 register. */
#define ALT_USB_DEV_DOEPINT6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT6_OFST 0x3c8
/* The address of the ALT_USB_DEV_DOEPINT6 register. */
#define ALT_USB_DEV_DOEPINT6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT6_OFST))
/*
* Register : doeptsiz6
*
* Device OUT Endpoint 6 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ6_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ6_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ6_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ6_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ6_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ6_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ6_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ6.
*/
struct ALT_USB_DEV_DOEPTSIZ6_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ6_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ6_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ6_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ6. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ6_s ALT_USB_DEV_DOEPTSIZ6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ6 register. */
#define ALT_USB_DEV_DOEPTSIZ6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ6_OFST 0x3d0
/* The address of the ALT_USB_DEV_DOEPTSIZ6 register. */
#define ALT_USB_DEV_DOEPTSIZ6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ6_OFST))
/*
* Register : doepdma6
*
* Device OUT Endpoint 6 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA6_DOEPDMA6
*
*/
/*
* Field : doepdma6
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA6_DOEPDMA6 field value from a register. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA6_DOEPDMA6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA6_DOEPDMA6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA6.
*/
struct ALT_USB_DEV_DOEPDMA6_s
{
uint32_t doepdma6 : 32; /* ALT_USB_DEV_DOEPDMA6_DOEPDMA6 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA6. */
typedef volatile struct ALT_USB_DEV_DOEPDMA6_s ALT_USB_DEV_DOEPDMA6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA6 register. */
#define ALT_USB_DEV_DOEPDMA6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA6_OFST 0x3d4
/* The address of the ALT_USB_DEV_DOEPDMA6 register. */
#define ALT_USB_DEV_DOEPDMA6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA6_OFST))
/*
* Register : doepdmab6
*
* Device OUT Endpoint 6 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6
*
*/
/*
* Field : doepdmab6
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB6.
*/
struct ALT_USB_DEV_DOEPDMAB6_s
{
const uint32_t doepdmab6 : 32; /* ALT_USB_DEV_DOEPDMAB6_DOEPDMAB6 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB6. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB6_s ALT_USB_DEV_DOEPDMAB6_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB6 register. */
#define ALT_USB_DEV_DOEPDMAB6_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB6 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB6_OFST 0x3dc
/* The address of the ALT_USB_DEV_DOEPDMAB6 register. */
#define ALT_USB_DEV_DOEPDMAB6_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB6_OFST))
/*
* Register : doepctl7
*
* Device Control OUT Endpoint 7 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL7_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL7_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL7_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL7_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL7_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL7_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL7_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL7_MPS register field. */
#define ALT_USB_DEV_DOEPCTL7_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL7_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL7_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL7_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL7_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL7_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL7_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL7_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL7_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_DPID register field. */
#define ALT_USB_DEV_DOEPCTL7_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL7_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL7_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
#define ALT_USB_DEV_DOEPCTL7_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
#define ALT_USB_DEV_DOEPCTL7_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
#define ALT_USB_DEV_DOEPCTL7_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SNP register field. */
#define ALT_USB_DEV_DOEPCTL7_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL7_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL7_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL7_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL7_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL7_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL7_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL7_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_STALL register field. */
#define ALT_USB_DEV_DOEPCTL7_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL7_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL7_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL7_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL7_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL7_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL7_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL7_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END | 0x1 | Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD0PID
*
* Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL7_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL7_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL7_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL7_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL7_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL7_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL7_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL7_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL7_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL7_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL7_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL7.
*/
struct ALT_USB_DEV_DOEPCTL7_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL7_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL7_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL7_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL7_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL7_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL7_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL7_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL7_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL7_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL7_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL7_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL7_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL7_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL7. */
typedef volatile struct ALT_USB_DEV_DOEPCTL7_s ALT_USB_DEV_DOEPCTL7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL7 register. */
#define ALT_USB_DEV_DOEPCTL7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL7_OFST 0x3e0
/* The address of the ALT_USB_DEV_DOEPCTL7 register. */
#define ALT_USB_DEV_DOEPCTL7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL7_OFST))
/*
* Register : doepint7
*
* Device OUT Endpoint 7 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT7_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT7_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT7_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT7_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT7_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT7_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT7_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT7_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT7_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT7_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT7_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT7_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT7_SETUP register field. */
#define ALT_USB_DEV_DOEPINT7_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT7_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT7_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT7_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT7_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT7_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT7_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT7_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT7_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT7_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT7_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT7_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT7_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT7_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT7_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT7_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT7_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT7_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT7_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT7_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT7_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT7.
*/
struct ALT_USB_DEV_DOEPINT7_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT7_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT7_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT7_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT7_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT7_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT7_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT7_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT7_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT7_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT7_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT7_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT7_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT7_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT7_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT7. */
typedef volatile struct ALT_USB_DEV_DOEPINT7_s ALT_USB_DEV_DOEPINT7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT7 register. */
#define ALT_USB_DEV_DOEPINT7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT7_OFST 0x3e8
/* The address of the ALT_USB_DEV_DOEPINT7 register. */
#define ALT_USB_DEV_DOEPINT7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT7_OFST))
/*
* Register : doeptsiz7
*
* Device OUT Endpoint 7 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ7_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ7_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ7_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ7_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ7_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ7_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ7_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ7.
*/
struct ALT_USB_DEV_DOEPTSIZ7_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ7_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ7_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ7_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ7. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ7_s ALT_USB_DEV_DOEPTSIZ7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ7 register. */
#define ALT_USB_DEV_DOEPTSIZ7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ7_OFST 0x3f0
/* The address of the ALT_USB_DEV_DOEPTSIZ7 register. */
#define ALT_USB_DEV_DOEPTSIZ7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ7_OFST))
/*
* Register : doepdma7
*
* Device OUT Endpoint 7 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA7_DOEPDMA7
*
*/
/*
* Field : doepdma7
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA7_DOEPDMA7 field value from a register. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA7_DOEPDMA7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA7_DOEPDMA7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA7.
*/
struct ALT_USB_DEV_DOEPDMA7_s
{
uint32_t doepdma7 : 32; /* ALT_USB_DEV_DOEPDMA7_DOEPDMA7 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA7. */
typedef volatile struct ALT_USB_DEV_DOEPDMA7_s ALT_USB_DEV_DOEPDMA7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA7 register. */
#define ALT_USB_DEV_DOEPDMA7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA7_OFST 0x3f4
/* The address of the ALT_USB_DEV_DOEPDMA7 register. */
#define ALT_USB_DEV_DOEPDMA7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA7_OFST))
/*
* Register : doepdmab7
*
* Device OUT Endpoint 7 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7
*
*/
/*
* Field : doepdmab7
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB7.
*/
struct ALT_USB_DEV_DOEPDMAB7_s
{
const uint32_t doepdmab7 : 32; /* ALT_USB_DEV_DOEPDMAB7_DOEPDMAB7 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB7. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB7_s ALT_USB_DEV_DOEPDMAB7_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB7 register. */
#define ALT_USB_DEV_DOEPDMAB7_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB7 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB7_OFST 0x3fc
/* The address of the ALT_USB_DEV_DOEPDMAB7 register. */
#define ALT_USB_DEV_DOEPDMAB7_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB7_OFST))
/*
* Register : doepctl8
*
* Device Control OUT Endpoint 8 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL8_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL8_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL8_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL8_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL8_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL8_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL8_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL8_MPS register field. */
#define ALT_USB_DEV_DOEPCTL8_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL8_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL8_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL8_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL8_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL8_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL8_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL8_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL8_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_DPID register field. */
#define ALT_USB_DEV_DOEPCTL8_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL8_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL8_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL8_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL8_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL8_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL8_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNP register field. */
#define ALT_USB_DEV_DOEPCTL8_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL8_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL8_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL8_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL8_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL8_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL8_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL8_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_STALL register field. */
#define ALT_USB_DEV_DOEPCTL8_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL8_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL8_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL8_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL8_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL8_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL8_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL8_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL8_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL8_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL8_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL8_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL8_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL8_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL8_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL8_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL8_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL8_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL8_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL8.
*/
struct ALT_USB_DEV_DOEPCTL8_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL8_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL8_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL8_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL8_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL8_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL8_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL8_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL8_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL8_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL8_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL8_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL8_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL8_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL8. */
typedef volatile struct ALT_USB_DEV_DOEPCTL8_s ALT_USB_DEV_DOEPCTL8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL8 register. */
#define ALT_USB_DEV_DOEPCTL8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL8_OFST 0x400
/* The address of the ALT_USB_DEV_DOEPCTL8 register. */
#define ALT_USB_DEV_DOEPCTL8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL8_OFST))
/*
* Register : doepint8
*
* Device OUT Endpoint 8 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT8_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT8_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT8_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT8_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT8_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT8_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT8_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT8_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT8_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT8_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT8_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT8_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT8_SETUP register field. */
#define ALT_USB_DEV_DOEPINT8_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT8_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT8_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT8_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT8_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT8_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT8_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT8_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT8_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT8_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT8_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT8_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT8_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT8_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT8_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT8_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT8_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT8_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT8_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT8_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT8_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT8.
*/
struct ALT_USB_DEV_DOEPINT8_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT8_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT8_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT8_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT8_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT8_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT8_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT8_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT8_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT8_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT8_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT8_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT8_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT8_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT8_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT8. */
typedef volatile struct ALT_USB_DEV_DOEPINT8_s ALT_USB_DEV_DOEPINT8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT8 register. */
#define ALT_USB_DEV_DOEPINT8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT8_OFST 0x408
/* The address of the ALT_USB_DEV_DOEPINT8 register. */
#define ALT_USB_DEV_DOEPINT8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT8_OFST))
/*
* Register : doeptsiz8
*
* Device OUT Endpoint 8 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ8_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ8_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ8_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ8_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ8_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ8_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ8_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ8.
*/
struct ALT_USB_DEV_DOEPTSIZ8_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ8_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ8_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ8_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ8. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ8_s ALT_USB_DEV_DOEPTSIZ8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ8 register. */
#define ALT_USB_DEV_DOEPTSIZ8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ8_OFST 0x410
/* The address of the ALT_USB_DEV_DOEPTSIZ8 register. */
#define ALT_USB_DEV_DOEPTSIZ8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ8_OFST))
/*
* Register : doepdma8
*
* Device OUT Endpoint 8 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA8_DOEPDMA8
*
*/
/*
* Field : doepdma8
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA8_DOEPDMA8 field value from a register. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA8_DOEPDMA8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA8_DOEPDMA8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA8.
*/
struct ALT_USB_DEV_DOEPDMA8_s
{
uint32_t doepdma8 : 32; /* ALT_USB_DEV_DOEPDMA8_DOEPDMA8 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA8. */
typedef volatile struct ALT_USB_DEV_DOEPDMA8_s ALT_USB_DEV_DOEPDMA8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA8 register. */
#define ALT_USB_DEV_DOEPDMA8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA8_OFST 0x414
/* The address of the ALT_USB_DEV_DOEPDMA8 register. */
#define ALT_USB_DEV_DOEPDMA8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA8_OFST))
/*
* Register : doepdmab8
*
* Device OUT Endpoint 8 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8
*
*/
/*
* Field : doepdmab8
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB8.
*/
struct ALT_USB_DEV_DOEPDMAB8_s
{
const uint32_t doepdmab8 : 32; /* ALT_USB_DEV_DOEPDMAB8_DOEPDMAB8 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB8. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB8_s ALT_USB_DEV_DOEPDMAB8_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB8 register. */
#define ALT_USB_DEV_DOEPDMAB8_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB8 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB8_OFST 0x41c
/* The address of the ALT_USB_DEV_DOEPDMAB8 register. */
#define ALT_USB_DEV_DOEPDMAB8_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB8_OFST))
/*
* Register : doepctl9
*
* Device Control OUT Endpoint 9 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL9_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL9_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL9_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL9_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL9_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL9_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL9_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL9_MPS register field. */
#define ALT_USB_DEV_DOEPCTL9_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL9_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL9_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL9_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL9_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL9_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL9_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL9_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL9_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_DPID register field. */
#define ALT_USB_DEV_DOEPCTL9_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL9_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL9_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL9_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL9_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL9_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL9_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNP register field. */
#define ALT_USB_DEV_DOEPCTL9_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL9_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL9_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL9_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL9_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL9_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL9_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL9_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_STALL register field. */
#define ALT_USB_DEV_DOEPCTL9_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL9_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL9_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL9_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL9_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL9_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL9_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL9_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL9_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL9_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL9_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL9_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL9_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL9_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL9_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL9_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL9_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL9_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL9_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL9.
*/
struct ALT_USB_DEV_DOEPCTL9_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL9_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL9_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL9_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL9_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL9_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL9_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL9_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL9_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL9_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL9_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL9_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL9_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL9_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL9. */
typedef volatile struct ALT_USB_DEV_DOEPCTL9_s ALT_USB_DEV_DOEPCTL9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL9 register. */
#define ALT_USB_DEV_DOEPCTL9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL9_OFST 0x420
/* The address of the ALT_USB_DEV_DOEPCTL9 register. */
#define ALT_USB_DEV_DOEPCTL9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL9_OFST))
/*
* Register : doepint9
*
* Device OUT Endpoint 9 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT9_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT9_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT9_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT9_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT9_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT9_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT9_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT9_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT9_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT9_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT9_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT9_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT9_SETUP register field. */
#define ALT_USB_DEV_DOEPINT9_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT9_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT9_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT9_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT9_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT9_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT9_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT9_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT9_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT9_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT9_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT9_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT9_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT9_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT9_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT9_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT9_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT9_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT9_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT9_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT9_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT9.
*/
struct ALT_USB_DEV_DOEPINT9_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT9_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT9_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT9_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT9_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT9_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT9_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT9_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT9_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT9_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT9_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT9_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT9_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT9_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT9_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT9. */
typedef volatile struct ALT_USB_DEV_DOEPINT9_s ALT_USB_DEV_DOEPINT9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT9 register. */
#define ALT_USB_DEV_DOEPINT9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT9_OFST 0x428
/* The address of the ALT_USB_DEV_DOEPINT9 register. */
#define ALT_USB_DEV_DOEPINT9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT9_OFST))
/*
* Register : doeptsiz9
*
* Device OUT Endpoint 9 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ9_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ9_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ9_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ9_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ9_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ9_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ9_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ9.
*/
struct ALT_USB_DEV_DOEPTSIZ9_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ9_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ9_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ9_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ9. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ9_s ALT_USB_DEV_DOEPTSIZ9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ9 register. */
#define ALT_USB_DEV_DOEPTSIZ9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ9_OFST 0x430
/* The address of the ALT_USB_DEV_DOEPTSIZ9 register. */
#define ALT_USB_DEV_DOEPTSIZ9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ9_OFST))
/*
* Register : doepdma9
*
* Device OUT Endpoint 9 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA9_DOEPDMA9
*
*/
/*
* Field : doepdma9
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA9_DOEPDMA9 field value from a register. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA9_DOEPDMA9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA9_DOEPDMA9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA9.
*/
struct ALT_USB_DEV_DOEPDMA9_s
{
uint32_t doepdma9 : 32; /* ALT_USB_DEV_DOEPDMA9_DOEPDMA9 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA9. */
typedef volatile struct ALT_USB_DEV_DOEPDMA9_s ALT_USB_DEV_DOEPDMA9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA9 register. */
#define ALT_USB_DEV_DOEPDMA9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA9_OFST 0x434
/* The address of the ALT_USB_DEV_DOEPDMA9 register. */
#define ALT_USB_DEV_DOEPDMA9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA9_OFST))
/*
* Register : doepdmab9
*
* Device OUT Endpoint 9 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9
*
*/
/*
* Field : doepdmab9
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB9.
*/
struct ALT_USB_DEV_DOEPDMAB9_s
{
const uint32_t doepdmab9 : 32; /* ALT_USB_DEV_DOEPDMAB9_DOEPDMAB9 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB9. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB9_s ALT_USB_DEV_DOEPDMAB9_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB9 register. */
#define ALT_USB_DEV_DOEPDMAB9_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB9 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB9_OFST 0x43c
/* The address of the ALT_USB_DEV_DOEPDMAB9 register. */
#define ALT_USB_DEV_DOEPDMAB9_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB9_OFST))
/*
* Register : doepctl10
*
* Device Control OUT Endpoint 10 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL10_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL10_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL10_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL10_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL10_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL10_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL10_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL10_MPS register field. */
#define ALT_USB_DEV_DOEPCTL10_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL10_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL10_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL10_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL10_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL10_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL10_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL10_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL10_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_DPID register field. */
#define ALT_USB_DEV_DOEPCTL10_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL10_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL10_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL10_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL10_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL10_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL10_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNP register field. */
#define ALT_USB_DEV_DOEPCTL10_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL10_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL10_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL10_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL10_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL10_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL10_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL10_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_STALL register field. */
#define ALT_USB_DEV_DOEPCTL10_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL10_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL10_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL10_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL10_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL10_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL10_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL10_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL10_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL10_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL10_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL10_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL10_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL10_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL10_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL10_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL10_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL10_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL10_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL10.
*/
struct ALT_USB_DEV_DOEPCTL10_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL10_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL10_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL10_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL10_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL10_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL10_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL10_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL10_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL10_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL10_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL10_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL10_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL10_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL10. */
typedef volatile struct ALT_USB_DEV_DOEPCTL10_s ALT_USB_DEV_DOEPCTL10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL10 register. */
#define ALT_USB_DEV_DOEPCTL10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL10_OFST 0x440
/* The address of the ALT_USB_DEV_DOEPCTL10 register. */
#define ALT_USB_DEV_DOEPCTL10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL10_OFST))
/*
* Register : doepint10
*
* Device OUT Endpoint 10 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT10_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT10_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT10_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT10_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT10_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT10_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT10_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT10_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT10_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT10_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT10_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT10_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT10_SETUP register field. */
#define ALT_USB_DEV_DOEPINT10_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT10_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT10_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT10_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT10_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT10_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT10_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT10_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT10_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT10_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT10_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT10_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT10_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT10_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT10_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT10_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT10_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT10_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT10_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT10_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT10_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT10.
*/
struct ALT_USB_DEV_DOEPINT10_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT10_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT10_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT10_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT10_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT10_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT10_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT10_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT10_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT10_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT10_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT10_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT10_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT10_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT10_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT10. */
typedef volatile struct ALT_USB_DEV_DOEPINT10_s ALT_USB_DEV_DOEPINT10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT10 register. */
#define ALT_USB_DEV_DOEPINT10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT10_OFST 0x448
/* The address of the ALT_USB_DEV_DOEPINT10 register. */
#define ALT_USB_DEV_DOEPINT10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT10_OFST))
/*
* Register : doeptsiz10
*
* Device OUT Endpoint 10 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ10_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ10_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ10_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ10_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ10_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ10_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ10_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ10.
*/
struct ALT_USB_DEV_DOEPTSIZ10_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ10_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ10_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ10_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ10. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ10_s ALT_USB_DEV_DOEPTSIZ10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ10 register. */
#define ALT_USB_DEV_DOEPTSIZ10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ10_OFST 0x450
/* The address of the ALT_USB_DEV_DOEPTSIZ10 register. */
#define ALT_USB_DEV_DOEPTSIZ10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ10_OFST))
/*
* Register : doepdma10
*
* Device OUT Endpoint 10 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA10_DOEPDMA10
*
*/
/*
* Field : doepdma10
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA10_DOEPDMA10 field value from a register. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA10_DOEPDMA10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA10_DOEPDMA10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA10.
*/
struct ALT_USB_DEV_DOEPDMA10_s
{
uint32_t doepdma10 : 32; /* ALT_USB_DEV_DOEPDMA10_DOEPDMA10 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA10. */
typedef volatile struct ALT_USB_DEV_DOEPDMA10_s ALT_USB_DEV_DOEPDMA10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA10 register. */
#define ALT_USB_DEV_DOEPDMA10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA10_OFST 0x454
/* The address of the ALT_USB_DEV_DOEPDMA10 register. */
#define ALT_USB_DEV_DOEPDMA10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA10_OFST))
/*
* Register : doepdmab10
*
* Device OUT Endpoint 10 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10
*
*/
/*
* Field : doepdmab10
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB10.
*/
struct ALT_USB_DEV_DOEPDMAB10_s
{
const uint32_t doepdmab10 : 32; /* ALT_USB_DEV_DOEPDMAB10_DOEPDMAB10 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB10. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB10_s ALT_USB_DEV_DOEPDMAB10_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB10 register. */
#define ALT_USB_DEV_DOEPDMAB10_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB10 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB10_OFST 0x45c
/* The address of the ALT_USB_DEV_DOEPDMAB10 register. */
#define ALT_USB_DEV_DOEPDMAB10_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB10_OFST))
/*
* Register : doepctl11
*
* Device Control OUT Endpoint 11 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL11_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL11_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL11_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL11_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL11_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL11_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL11_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL11_MPS register field. */
#define ALT_USB_DEV_DOEPCTL11_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL11_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL11_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL11_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL11_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL11_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL11_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL11_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL11_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_DPID register field. */
#define ALT_USB_DEV_DOEPCTL11_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL11_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL11_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL11_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL11_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL11_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL11_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNP register field. */
#define ALT_USB_DEV_DOEPCTL11_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL11_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL11_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL11_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL11_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL11_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL11_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL11_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_STALL register field. */
#define ALT_USB_DEV_DOEPCTL11_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL11_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL11_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL11_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL11_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL11_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL11_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL11_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL11_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL11_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL11_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL11_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL11_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL11_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL11_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL11_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL11_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL11_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL11_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL11.
*/
struct ALT_USB_DEV_DOEPCTL11_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL11_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL11_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL11_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL11_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL11_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL11_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL11_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL11_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL11_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL11_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL11_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL11_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL11_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL11. */
typedef volatile struct ALT_USB_DEV_DOEPCTL11_s ALT_USB_DEV_DOEPCTL11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL11 register. */
#define ALT_USB_DEV_DOEPCTL11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL11_OFST 0x460
/* The address of the ALT_USB_DEV_DOEPCTL11 register. */
#define ALT_USB_DEV_DOEPCTL11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL11_OFST))
/*
* Register : doepint11
*
* Device OUT Endpoint 11 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT11_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT11_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT11_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT11_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT11_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT11_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT11_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT11_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT11_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT11_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT11_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT11_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT11_SETUP register field. */
#define ALT_USB_DEV_DOEPINT11_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT11_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT11_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT11_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT11_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT11_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT11_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT11_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT11_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT11_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT11_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT11_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT11_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT11_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT11_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT11_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT11_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT11_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT11_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT11_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT11_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT11.
*/
struct ALT_USB_DEV_DOEPINT11_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT11_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT11_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT11_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT11_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT11_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT11_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT11_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT11_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT11_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT11_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT11_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT11_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT11_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT11_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT11. */
typedef volatile struct ALT_USB_DEV_DOEPINT11_s ALT_USB_DEV_DOEPINT11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT11 register. */
#define ALT_USB_DEV_DOEPINT11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT11_OFST 0x468
/* The address of the ALT_USB_DEV_DOEPINT11 register. */
#define ALT_USB_DEV_DOEPINT11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT11_OFST))
/*
* Register : doeptsiz11
*
* Device OUT Endpoint 11 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ11_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ11_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ11_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ11_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ11_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ11_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ11_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ11.
*/
struct ALT_USB_DEV_DOEPTSIZ11_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ11_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ11_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ11_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ11. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ11_s ALT_USB_DEV_DOEPTSIZ11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ11 register. */
#define ALT_USB_DEV_DOEPTSIZ11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ11_OFST 0x470
/* The address of the ALT_USB_DEV_DOEPTSIZ11 register. */
#define ALT_USB_DEV_DOEPTSIZ11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ11_OFST))
/*
* Register : doepdma11
*
* Device OUT Endpoint 11 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA11_DOEPDMA11
*
*/
/*
* Field : doepdma11
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA11_DOEPDMA11 field value from a register. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA11_DOEPDMA11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA11_DOEPDMA11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA11.
*/
struct ALT_USB_DEV_DOEPDMA11_s
{
uint32_t doepdma11 : 32; /* ALT_USB_DEV_DOEPDMA11_DOEPDMA11 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA11. */
typedef volatile struct ALT_USB_DEV_DOEPDMA11_s ALT_USB_DEV_DOEPDMA11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA11 register. */
#define ALT_USB_DEV_DOEPDMA11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA11_OFST 0x474
/* The address of the ALT_USB_DEV_DOEPDMA11 register. */
#define ALT_USB_DEV_DOEPDMA11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA11_OFST))
/*
* Register : doepdmab11
*
* Device OUT Endpoint 11 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11
*
*/
/*
* Field : doepdmab11
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB11.
*/
struct ALT_USB_DEV_DOEPDMAB11_s
{
const uint32_t doepdmab11 : 32; /* ALT_USB_DEV_DOEPDMAB11_DOEPDMAB11 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB11. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB11_s ALT_USB_DEV_DOEPDMAB11_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB11 register. */
#define ALT_USB_DEV_DOEPDMAB11_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB11 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB11_OFST 0x47c
/* The address of the ALT_USB_DEV_DOEPDMAB11 register. */
#define ALT_USB_DEV_DOEPDMAB11_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB11_OFST))
/*
* Register : doepctl12
*
* Device Control OUT Endpoint 12 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL12_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL12_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL12_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL12_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL12_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL12_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL12_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL12_MPS register field. */
#define ALT_USB_DEV_DOEPCTL12_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL12_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL12_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL12_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL12_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL12_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL12_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL12_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL12_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_DPID register field. */
#define ALT_USB_DEV_DOEPCTL12_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL12_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL12_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL12_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL12_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL12_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL12_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNP register field. */
#define ALT_USB_DEV_DOEPCTL12_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL12_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL12_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL12_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL12_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL12_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL12_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL12_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_STALL register field. */
#define ALT_USB_DEV_DOEPCTL12_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL12_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL12_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL12_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL12_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL12_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL12_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL12_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL12_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL12_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL12_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL12_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL12_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL12_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL12_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL12_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL12_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL12_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL12_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL12.
*/
struct ALT_USB_DEV_DOEPCTL12_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL12_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL12_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL12_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL12_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL12_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL12_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL12_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL12_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL12_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL12_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL12_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL12_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL12_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL12. */
typedef volatile struct ALT_USB_DEV_DOEPCTL12_s ALT_USB_DEV_DOEPCTL12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL12 register. */
#define ALT_USB_DEV_DOEPCTL12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL12_OFST 0x480
/* The address of the ALT_USB_DEV_DOEPCTL12 register. */
#define ALT_USB_DEV_DOEPCTL12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL12_OFST))
/*
* Register : doepint12
*
* Device OUT Endpoint 12 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT12_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT12_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT12_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT12_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT12_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT12_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT12_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT12_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT12_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT12_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT12_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT12_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT12_SETUP register field. */
#define ALT_USB_DEV_DOEPINT12_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT12_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT12_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT12_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT12_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT12_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT12_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT12_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT12_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT12_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT12_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT12_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT12_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT12_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT12_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT12_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT12_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT12_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT12_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT12_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT12_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT12.
*/
struct ALT_USB_DEV_DOEPINT12_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT12_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT12_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT12_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT12_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT12_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT12_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT12_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT12_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT12_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT12_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT12_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT12_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT12_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT12_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT12. */
typedef volatile struct ALT_USB_DEV_DOEPINT12_s ALT_USB_DEV_DOEPINT12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT12 register. */
#define ALT_USB_DEV_DOEPINT12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT12_OFST 0x488
/* The address of the ALT_USB_DEV_DOEPINT12 register. */
#define ALT_USB_DEV_DOEPINT12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT12_OFST))
/*
* Register : doeptsiz12
*
* Device OUT Endpoint 12 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ12_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ12_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ12_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ12_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ12_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ12_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ12_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ12.
*/
struct ALT_USB_DEV_DOEPTSIZ12_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ12_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ12_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ12_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ12. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ12_s ALT_USB_DEV_DOEPTSIZ12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ12 register. */
#define ALT_USB_DEV_DOEPTSIZ12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ12_OFST 0x490
/* The address of the ALT_USB_DEV_DOEPTSIZ12 register. */
#define ALT_USB_DEV_DOEPTSIZ12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ12_OFST))
/*
* Register : doepdma12
*
* Device OUT Endpoint 12 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA12_DOEPDMA12
*
*/
/*
* Field : doepdma12
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA12_DOEPDMA12 field value from a register. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA12_DOEPDMA12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA12_DOEPDMA12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA12.
*/
struct ALT_USB_DEV_DOEPDMA12_s
{
uint32_t doepdma12 : 32; /* ALT_USB_DEV_DOEPDMA12_DOEPDMA12 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA12. */
typedef volatile struct ALT_USB_DEV_DOEPDMA12_s ALT_USB_DEV_DOEPDMA12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA12 register. */
#define ALT_USB_DEV_DOEPDMA12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA12_OFST 0x494
/* The address of the ALT_USB_DEV_DOEPDMA12 register. */
#define ALT_USB_DEV_DOEPDMA12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA12_OFST))
/*
* Register : doepdmab12
*
* Device OUT Endpoint 12 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12
*
*/
/*
* Field : doepdmab12
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB12.
*/
struct ALT_USB_DEV_DOEPDMAB12_s
{
const uint32_t doepdmab12 : 32; /* ALT_USB_DEV_DOEPDMAB12_DOEPDMAB12 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB12. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB12_s ALT_USB_DEV_DOEPDMAB12_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB12 register. */
#define ALT_USB_DEV_DOEPDMAB12_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB12 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB12_OFST 0x49c
/* The address of the ALT_USB_DEV_DOEPDMAB12 register. */
#define ALT_USB_DEV_DOEPDMAB12_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB12_OFST))
/*
* Register : doepctl13
*
* Device Control OUT Endpoint 13 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL13_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL13_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL13_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL13_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL13_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL13_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL13_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL13_MPS register field. */
#define ALT_USB_DEV_DOEPCTL13_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL13_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL13_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL13_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL13_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL13_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL13_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL13_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL13_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_DPID register field. */
#define ALT_USB_DEV_DOEPCTL13_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL13_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL13_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL13_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL13_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL13_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL13_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNP register field. */
#define ALT_USB_DEV_DOEPCTL13_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL13_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL13_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL13_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL13_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL13_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL13_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL13_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_STALL register field. */
#define ALT_USB_DEV_DOEPCTL13_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL13_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL13_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL13_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL13_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL13_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL13_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL13_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL13_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL13_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL13_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL13_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL13_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL13_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL13_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL13_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL13_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL13_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL13_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL13.
*/
struct ALT_USB_DEV_DOEPCTL13_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL13_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL13_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL13_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL13_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL13_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL13_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL13_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL13_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL13_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL13_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL13_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL13_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL13_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL13. */
typedef volatile struct ALT_USB_DEV_DOEPCTL13_s ALT_USB_DEV_DOEPCTL13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL13 register. */
#define ALT_USB_DEV_DOEPCTL13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL13_OFST 0x4a0
/* The address of the ALT_USB_DEV_DOEPCTL13 register. */
#define ALT_USB_DEV_DOEPCTL13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL13_OFST))
/*
* Register : doepint13
*
* Device OUT Endpoint 13 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT13_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT13_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT13_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT13_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT13_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT13_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT13_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT13_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT13_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT13_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT13_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT13_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT13_SETUP register field. */
#define ALT_USB_DEV_DOEPINT13_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT13_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT13_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT13_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT13_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT13_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT13_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT13_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT13_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT13_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT13_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT13_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT13_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT13_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT13_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT13_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT13_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT13_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT13_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT13_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT13_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT13.
*/
struct ALT_USB_DEV_DOEPINT13_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT13_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT13_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT13_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT13_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT13_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT13_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT13_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT13_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT13_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT13_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT13_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT13_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT13_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT13_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT13. */
typedef volatile struct ALT_USB_DEV_DOEPINT13_s ALT_USB_DEV_DOEPINT13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT13 register. */
#define ALT_USB_DEV_DOEPINT13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT13_OFST 0x4a8
/* The address of the ALT_USB_DEV_DOEPINT13 register. */
#define ALT_USB_DEV_DOEPINT13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT13_OFST))
/*
* Register : doeptsiz13
*
* Device OUT Endpoint 13 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ13_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ13_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ13_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ13_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ13_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ13_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ13_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ13.
*/
struct ALT_USB_DEV_DOEPTSIZ13_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ13_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ13_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ13_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ13. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ13_s ALT_USB_DEV_DOEPTSIZ13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ13 register. */
#define ALT_USB_DEV_DOEPTSIZ13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ13_OFST 0x4b0
/* The address of the ALT_USB_DEV_DOEPTSIZ13 register. */
#define ALT_USB_DEV_DOEPTSIZ13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ13_OFST))
/*
* Register : doepdma13
*
* Device OUT Endpoint 13 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA13_DOEPDMA13
*
*/
/*
* Field : doepdma13
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA13_DOEPDMA13 field value from a register. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA13_DOEPDMA13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA13_DOEPDMA13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA13.
*/
struct ALT_USB_DEV_DOEPDMA13_s
{
uint32_t doepdma13 : 32; /* ALT_USB_DEV_DOEPDMA13_DOEPDMA13 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA13. */
typedef volatile struct ALT_USB_DEV_DOEPDMA13_s ALT_USB_DEV_DOEPDMA13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA13 register. */
#define ALT_USB_DEV_DOEPDMA13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA13_OFST 0x4b4
/* The address of the ALT_USB_DEV_DOEPDMA13 register. */
#define ALT_USB_DEV_DOEPDMA13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA13_OFST))
/*
* Register : doepdmab13
*
* Device OUT Endpoint 13 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13
*
*/
/*
* Field : doepdmab13
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB13.
*/
struct ALT_USB_DEV_DOEPDMAB13_s
{
const uint32_t doepdmab13 : 32; /* ALT_USB_DEV_DOEPDMAB13_DOEPDMAB13 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB13. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB13_s ALT_USB_DEV_DOEPDMAB13_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB13 register. */
#define ALT_USB_DEV_DOEPDMAB13_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB13 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB13_OFST 0x4bc
/* The address of the ALT_USB_DEV_DOEPDMAB13 register. */
#define ALT_USB_DEV_DOEPDMAB13_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB13_OFST))
/*
* Register : doepctl14
*
* Device Control OUT Endpoint 14 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL14_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL14_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL14_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL14_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL14_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL14_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL14_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL14_MPS register field. */
#define ALT_USB_DEV_DOEPCTL14_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL14_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL14_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL14_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL14_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL14_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL14_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL14_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL14_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_DPID register field. */
#define ALT_USB_DEV_DOEPCTL14_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL14_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL14_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL14_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL14_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL14_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL14_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNP register field. */
#define ALT_USB_DEV_DOEPCTL14_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL14_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL14_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL14_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL14_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL14_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL14_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL14_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_STALL register field. */
#define ALT_USB_DEV_DOEPCTL14_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL14_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL14_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL14_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL14_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL14_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL14_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL14_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL14_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL14_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL14_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL14_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL14_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL14_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL14_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL14_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL14_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL14_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL14_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL14.
*/
struct ALT_USB_DEV_DOEPCTL14_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL14_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL14_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL14_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL14_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL14_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL14_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL14_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL14_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL14_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL14_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL14_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL14_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL14_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL14. */
typedef volatile struct ALT_USB_DEV_DOEPCTL14_s ALT_USB_DEV_DOEPCTL14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL14 register. */
#define ALT_USB_DEV_DOEPCTL14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL14_OFST 0x4c0
/* The address of the ALT_USB_DEV_DOEPCTL14 register. */
#define ALT_USB_DEV_DOEPCTL14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL14_OFST))
/*
* Register : doepint14
*
* Device OUT Endpoint 14 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT14_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT14_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT14_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT14_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT14_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT14_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT14_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT14_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT14_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT14_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT14_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT14_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT14_SETUP register field. */
#define ALT_USB_DEV_DOEPINT14_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT14_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT14_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT14_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT14_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT14_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT14_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT14_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT14_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT14_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT14_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT14_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT14_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT14_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT14_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT14_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT14_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT14_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT14_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT14_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT14_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT14.
*/
struct ALT_USB_DEV_DOEPINT14_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT14_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT14_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT14_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT14_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT14_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT14_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT14_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT14_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT14_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT14_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT14_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT14_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT14_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT14_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT14. */
typedef volatile struct ALT_USB_DEV_DOEPINT14_s ALT_USB_DEV_DOEPINT14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT14 register. */
#define ALT_USB_DEV_DOEPINT14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT14_OFST 0x4c8
/* The address of the ALT_USB_DEV_DOEPINT14 register. */
#define ALT_USB_DEV_DOEPINT14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT14_OFST))
/*
* Register : doeptsiz14
*
* Device OUT Endpoint 14 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ14_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ14_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ14_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ14_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ14_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ14_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ14_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ14.
*/
struct ALT_USB_DEV_DOEPTSIZ14_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ14_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ14_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ14_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ14. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ14_s ALT_USB_DEV_DOEPTSIZ14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ14 register. */
#define ALT_USB_DEV_DOEPTSIZ14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ14_OFST 0x4d0
/* The address of the ALT_USB_DEV_DOEPTSIZ14 register. */
#define ALT_USB_DEV_DOEPTSIZ14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ14_OFST))
/*
* Register : doepdma14
*
* Device OUT Endpoint 14 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA14_DOEPDMA14
*
*/
/*
* Field : doepdma14
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA14_DOEPDMA14 field value from a register. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA14_DOEPDMA14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA14_DOEPDMA14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA14.
*/
struct ALT_USB_DEV_DOEPDMA14_s
{
uint32_t doepdma14 : 32; /* ALT_USB_DEV_DOEPDMA14_DOEPDMA14 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA14. */
typedef volatile struct ALT_USB_DEV_DOEPDMA14_s ALT_USB_DEV_DOEPDMA14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA14 register. */
#define ALT_USB_DEV_DOEPDMA14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA14_OFST 0x4d4
/* The address of the ALT_USB_DEV_DOEPDMA14 register. */
#define ALT_USB_DEV_DOEPDMA14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA14_OFST))
/*
* Register : doepdmab14
*
* Device OUT Endpoint 14 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14
*
*/
/*
* Field : doepdmab14
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB14.
*/
struct ALT_USB_DEV_DOEPDMAB14_s
{
const uint32_t doepdmab14 : 32; /* ALT_USB_DEV_DOEPDMAB14_DOEPDMAB14 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB14. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB14_s ALT_USB_DEV_DOEPDMAB14_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB14 register. */
#define ALT_USB_DEV_DOEPDMAB14_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB14 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB14_OFST 0x4dc
/* The address of the ALT_USB_DEV_DOEPDMAB14 register. */
#define ALT_USB_DEV_DOEPDMAB14_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB14_OFST))
/*
* Register : doepctl15
*
* Device Control OUT Endpoint 15 Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:---------|:------|:-------------------------------
* [10:0] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_MPS
* [14:11] | ??? | 0x0 | *UNDEFINED*
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_USBACTEP
* [16] | R | 0x0 | ALT_USB_DEV_DOEPCTL15_DPID
* [17] | R | 0x0 | ALT_USB_DEV_DOEPCTL15_NAKSTS
* [19:18] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_EPTYPE
* [20] | RW | 0x0 | ALT_USB_DEV_DOEPCTL15_SNP
* [21] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_STALL
* [25:22] | ??? | 0x0 | *UNDEFINED*
* [26] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_CNAK
* [27] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SNAK
* [28] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SETD0PID
* [29] | W | 0x0 | ALT_USB_DEV_DOEPCTL15_SETD1PID
* [30] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_EPDIS
* [31] | R-W once | 0x0 | ALT_USB_DEV_DOEPCTL15_EPENA
*
*/
/*
* Field : mps
*
* Maximum Packet Size (MPS)
*
* The application must program this field with the maximum packet size for the
* current
*
* logical endpoint. This value is in bytes.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_MSB 10
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_WIDTH 11
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL15_MPS_SET_MSK 0x000007ff
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_MPS register field value. */
#define ALT_USB_DEV_DOEPCTL15_MPS_CLR_MSK 0xfffff800
/* The reset value of the ALT_USB_DEV_DOEPCTL15_MPS register field. */
#define ALT_USB_DEV_DOEPCTL15_MPS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_MPS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0)
/* Produces a ALT_USB_DEV_DOEPCTL15_MPS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff)
/*
* Field : usbactep
*
* USB Active Endpoint (USBActEP)
*
* Indicates whether this endpoint is active in the current configuration and
* interface. The
*
* core clears this bit for all endpoints (other than EP 0) after detecting a USB
* reset. After
*
* receiving the SetConfiguration and SetInterface commands, the application must
*
* program endpoint registers accordingly and set this bit.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD | 0x0 | Not Active
* ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END | 0x1 | USB Active Endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
*
* Not Active
*/
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_USBACTEP
*
* USB Active Endpoint
*/
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_USBACTEP register field value. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_USBACTEP register field. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_USBACTEP field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPCTL15_USBACTEP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000)
/*
* Field : dpid
*
* Endpoint Data PID (DPID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Contains the PID of the packet to be received or transmitted on this endpoint.
* The
*
* application must program the PID of the first packet to be received or
* transmitted on
*
* this endpoint, after the endpoint is activated. The applications use the
* SetD1PID and
*
* SetD0PID fields of this register to program either DATA0 or DATA1 PID.
*
* 1'b0: DATA0
*
* 1'b1: DATA1
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 RO
*
* Even/Odd (Micro)Frame (EO_FrNum)
*
* In non-Scatter/Gather DMA mode:
*
* Applies to isochronous IN and OUT endpoints only.
*
* Indicates the (micro)frame number in which the core transmits/receives
* isochronous
*
* data for this endpoint. The application must program the even/odd (micro) frame
*
* number in which it intends to transmit/receive isochronous data for this
* endpoint using
*
* the SetEvnFr and SetOddFr fields in this register.
*
* 1'b0: Even (micro)frame
*
* 1'b1: Odd (micro)frame
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is provided in the transmit descriptor structure. The
* frame in
*
* which data is received is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPCTL15_DPID_E_INACT | 0x0 | Endpoint Data PID not active
* ALT_USB_DEV_DOEPCTL15_DPID_E_ACT | 0x1 | Endpoint Data PID active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
*
* Endpoint Data PID not active
*/
#define ALT_USB_DEV_DOEPCTL15_DPID_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_DPID
*
* Endpoint Data PID active
*/
#define ALT_USB_DEV_DOEPCTL15_DPID_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_LSB 16
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_MSB 16
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL15_DPID_SET_MSK 0x00010000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_DPID register field value. */
#define ALT_USB_DEV_DOEPCTL15_DPID_CLR_MSK 0xfffeffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_DPID register field. */
#define ALT_USB_DEV_DOEPCTL15_DPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_DPID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_USB_DEV_DOEPCTL15_DPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000)
/*
* Field : naksts
*
* NAK Status (NAKSts)
*
* Indicates the following:
*
* 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.
*
* 1'b1: The core is transmitting NAK handshakes on this endpoint.
*
* When either the application or the core sets this bit:
*
* The core stops receiving any data on an OUT endpoint, even if there is space in
*
* the RxFIFO to accommodate the incoming packet.
*
* For non-isochronous IN endpoints: The core stops transmitting any data on an IN
*
* endpoint, even if there data is available in the TxFIFO.
*
* For isochronous IN endpoints: The core sends out a zero-length data packet, even
*
* if there data is available in the TxFIFO.
*
* Irrespective of this bit's setting, the core always responds to SETUP data
* packets with
*
* an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------------------
* ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK | 0x0 | The core is transmitting non-NAK handshakes
* : | | based on the FIFO status
* ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK | 0x1 | The core is transmitting NAK handshakes on this
* : | | endpoint
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
*
* The core is transmitting non-NAK handshakes based on the FIFO status
*/
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NONNAK 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_NAKSTS
*
* The core is transmitting NAK handshakes on this endpoint
*/
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_E_NAK 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_LSB 17
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_MSB 17
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET_MSK 0x00020000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_NAKSTS register field value. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_CLR_MSK 0xfffdffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_NAKSTS register field. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_NAKSTS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_USB_DEV_DOEPCTL15_NAKSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000)
/*
* Field : eptype
*
* Endpoint Type (EPType)
*
* This is the transfer type supported by this logical endpoint.
*
* 2'b00: Control
*
* 2'b01: Isochronous
*
* 2'b10: Bulk
*
* 2'b11: Interrupt
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL | 0x0 | Control
* ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS | 0x1 | Isochronous
* ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK | 0x2 | Bulk
* ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP | 0x3 | Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
*
* Control
*/
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_CTL 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
*
* Isochronous
*/
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
*
* Bulk
*/
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_BULK 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPTYPE
*
* Interrupt
*/
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_E_INTERRUP 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_LSB 18
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_MSB 19
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET_MSK 0x000c0000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPTYPE register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPTYPE register field. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPTYPE field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_GET(value) (((value) & 0x000c0000) >> 18)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPTYPE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPTYPE_SET(value) (((value) << 18) & 0x000c0000)
/*
* Field : snp
*
* Snoop Mode (Snp)
*
* Applies to OUT endpoints only.
*
* This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not
*
* check the correctness of OUT packets before transferring them to application
* memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPCTL15_SNP_E_DIS | 0x0 | Disable Snoop Mode
* ALT_USB_DEV_DOEPCTL15_SNP_E_EN | 0x1 | Enable Snoop Mode
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
*
* Disable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL15_SNP_E_DIS 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNP
*
* Enable Snoop Mode
*/
#define ALT_USB_DEV_DOEPCTL15_SNP_E_EN 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_LSB 20
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_MSB 20
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNP_SET_MSK 0x00100000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNP register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNP_CLR_MSK 0xffefffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNP register field. */
#define ALT_USB_DEV_DOEPCTL15_SNP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SNP field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SNP_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_USB_DEV_DOEPCTL15_SNP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SNP_SET(value) (((value) << 20) & 0x00100000)
/*
* Field : stall
*
* STALL Handshake (Stall)
*
* Applies to non-control, non-isochronous IN and OUT endpoints only.
*
* The application sets this bit to stall all tokens from the USB host to this
* endpoint. If a
*
* NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this
* bit, the
*
* STALL bit takes priority. Only the application can clear this bit, never the
* core.
*
* 1'b0 R_W
*
* Applies to control endpoints only.
*
* The application can only set this bit, and the core clears it, when a SETUP
* token is
*
* received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global
* OUT
*
* NAK is set along with this bit, the STALL bit takes priority. Irrespective of
* this bit's
*
* setting, the core always responds to SETUP data packets with an ACK handshake.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPCTL15_STALL_E_INACT | 0x0 | STALL All Tokens not active
* ALT_USB_DEV_DOEPCTL15_STALL_E_ACT | 0x1 | STALL All Tokens active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
*
* STALL All Tokens not active
*/
#define ALT_USB_DEV_DOEPCTL15_STALL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_STALL
*
* STALL All Tokens active
*/
#define ALT_USB_DEV_DOEPCTL15_STALL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_LSB 21
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_MSB 21
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL15_STALL_SET_MSK 0x00200000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_STALL register field value. */
#define ALT_USB_DEV_DOEPCTL15_STALL_CLR_MSK 0xffdfffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_STALL register field. */
#define ALT_USB_DEV_DOEPCTL15_STALL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_STALL field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_USB_DEV_DOEPCTL15_STALL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000)
/*
* Field : cnak
*
* Clear NAK (CNAK)
*
* A write to this bit clears the NAK bit For the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:-------------
* ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT | 0x0 | No Clear NAK
* ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT | 0x1 | Clear NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
*
* No Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL15_CNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_CNAK
*
* Clear NAK
*/
#define ALT_USB_DEV_DOEPCTL15_CNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_LSB 26
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_MSB 26
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_SET_MSK 0x04000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_CNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_CLR_MSK 0xfbffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_CNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_CNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_USB_DEV_DOEPCTL15_CNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000)
/*
* Field : snak
*
* Set NAK (SNAK)
*
* A write to this bit sets the NAK bit For the endpoint.
*
* Using this bit, the application can control the transmission of NAK
*
* handshakes on an endpoint. The core can also Set this bit For an
*
* endpoint after a SETUP packet is received on that endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------|:------|:------------
* ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT | 0x0 | No Set NAK
* ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT | 0x1 | Set NAK
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
*
* No Set NAK
*/
#define ALT_USB_DEV_DOEPCTL15_SNAK_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SNAK
*
* Set NAK
*/
#define ALT_USB_DEV_DOEPCTL15_SNAK_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_LSB 27
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_MSB 27
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_SET_MSK 0x08000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SNAK register field value. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_CLR_MSK 0xf7ffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SNAK register field. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SNAK field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_USB_DEV_DOEPCTL15_SNAK register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000)
/*
* Field : setd0pid
*
* Set DATA0 PID (SetD0PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA0.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* 1'b0 WO
*
* In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even
* (micro)
*
* frame.
*
* When Scatter/Gather DMA mode is enabled, this field is reserved. The frame
* number
*
* in which to send data is in the transmit descriptor structure. The frame in
* which to
*
* receive data is updated in receive descriptor structure.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------------------------
* ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD | 0x0 | Disables Set DATA0 PID
* ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END | 0x1 | Enables Endpoint Data PID to DATA0)
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
*
* Disables Set DATA0 PID
*/
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD0PID
*
* Enables Endpoint Data PID to DATA0)
*/
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_LSB 28
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET_MSK 0x10000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD0PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_CLR_MSK 0xefffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD0PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD0PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_USB_DEV_DOEPCTL15_SETD0PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000)
/*
* Field : setd1pid
*
* Set DATA1 PID (SetD1PID)
*
* Applies to interrupt/bulk IN and OUT endpoints only.
*
* Writing to this field sets the Endpoint Data PID (DPID) field in this register
* to DATA1.
*
* This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather
*
* DMA mode.
*
* Set Odd (micro)frame (SetOddFr)
*
* Applies to isochronous IN and OUT endpoints only.
*
* Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd
*
* (micro)frame.
*
* This field is not applicable for Scatter/Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:-----------------------
* ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD | 0x0 | Disables Set DATA1 PID
* ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END | 0x1 | Enables Set DATA1 PID
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
*
* Disables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_SETD1PID
*
* Enables Set DATA1 PID
*/
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_MSB 29
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET_MSK 0x20000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_SETD1PID register field value. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_CLR_MSK 0xdfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_SETD1PID register field. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_SETD1PID field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPCTL15_SETD1PID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000)
/*
* Field : epdis
*
* Endpoint Disable (EPDis)
*
* Applies to IN and OUT endpoints.
*
* The application sets this bit to stop transmitting/receiving data on an
* endpoint, even
*
* before the transfer for that endpoint is complete. The application must wait for
* the
*
* Endpoint Disabled interrupt before treating the endpoint as disabled. The core
* clears
*
* this bit before setting the Endpoint Disabled interrupt. The application must
* set this bit
*
* only if Endpoint Enable is already set for this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT | 0x0 | No Endpoint Disable
* ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT | 0x1 | Endpoint Disable
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
*
* No Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPDIS
*
* Endpoint Disable
*/
#define ALT_USB_DEV_DOEPCTL15_EPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_LSB 30
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET_MSK 0x40000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPDIS register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_CLR_MSK 0xbfffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPDIS register field. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPDIS field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000)
/*
* Field : epena
*
* Endpoint Enable (EPEna)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled,
*
* For IN endpoints this bit indicates that the descriptor structure and data
* buffer with
*
* data ready to transmit is setup.
*
* For OUT endpoint it indicates that the descriptor structure and data buffer to
*
* receive data is setup.
*
* When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based
*
* DMA mode:
*
* * For IN endpoints, this bit indicates that data is ready to be transmitted on
* the
*
* endpoint.
*
* * For OUT endpoints, this bit indicates that the application has allocated the
*
* memory to start receiving data from the USB.
*
* * The core clears this bit before setting any of the following interrupts on
* this
*
* endpoint:
*
* SETUP Phase Done
*
* Endpoint Disabled
*
* Transfer Completed
*
* Note: For control endpoints in DMA mode, this bit must be set to be able to
* transfer
*
* SETUP data packets in memory.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:-------------------------
* ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT | 0x0 | Endpoint Enable inactive
* ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT | 0x1 | Endpoint Enable active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
*
* Endpoint Enable inactive
*/
#define ALT_USB_DEV_DOEPCTL15_EPENA_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPCTL15_EPENA
*
* Endpoint Enable active
*/
#define ALT_USB_DEV_DOEPCTL15_EPENA_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_LSB 31
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_SET_MSK 0x80000000
/* The mask used to clear the ALT_USB_DEV_DOEPCTL15_EPENA register field value. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_CLR_MSK 0x7fffffff
/* The reset value of the ALT_USB_DEV_DOEPCTL15_EPENA register field. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPCTL15_EPENA field value from a register. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_USB_DEV_DOEPCTL15_EPENA register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPCTL15.
*/
struct ALT_USB_DEV_DOEPCTL15_s
{
uint32_t mps : 11; /* ALT_USB_DEV_DOEPCTL15_MPS */
uint32_t : 4; /* *UNDEFINED* */
uint32_t usbactep : 1; /* ALT_USB_DEV_DOEPCTL15_USBACTEP */
const uint32_t dpid : 1; /* ALT_USB_DEV_DOEPCTL15_DPID */
const uint32_t naksts : 1; /* ALT_USB_DEV_DOEPCTL15_NAKSTS */
uint32_t eptype : 2; /* ALT_USB_DEV_DOEPCTL15_EPTYPE */
uint32_t snp : 1; /* ALT_USB_DEV_DOEPCTL15_SNP */
uint32_t stall : 1; /* ALT_USB_DEV_DOEPCTL15_STALL */
uint32_t : 4; /* *UNDEFINED* */
uint32_t cnak : 1; /* ALT_USB_DEV_DOEPCTL15_CNAK */
uint32_t snak : 1; /* ALT_USB_DEV_DOEPCTL15_SNAK */
uint32_t setd0pid : 1; /* ALT_USB_DEV_DOEPCTL15_SETD0PID */
uint32_t setd1pid : 1; /* ALT_USB_DEV_DOEPCTL15_SETD1PID */
uint32_t epdis : 1; /* ALT_USB_DEV_DOEPCTL15_EPDIS */
uint32_t epena : 1; /* ALT_USB_DEV_DOEPCTL15_EPENA */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPCTL15. */
typedef volatile struct ALT_USB_DEV_DOEPCTL15_s ALT_USB_DEV_DOEPCTL15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPCTL15 register. */
#define ALT_USB_DEV_DOEPCTL15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPCTL15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPCTL15_OFST 0x4e0
/* The address of the ALT_USB_DEV_DOEPCTL15 register. */
#define ALT_USB_DEV_DOEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPCTL15_OFST))
/*
* Register : doepint15
*
* Device OUT Endpoint 15 Interrupt Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_XFERCOMPL
* [1] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_EPDISBLD
* [2] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_AHBERR
* [3] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_SETUP
* [4] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
* [5] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_STSPHSERCVD
* [6] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
* [7] | ??? | 0x0 | *UNDEFINED*
* [8] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_OUTPKTERR
* [9] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BNAINTR
* [10] | ??? | 0x0 | *UNDEFINED*
* [11] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_PKTDRPSTS
* [12] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_BBLEERR
* [13] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_NAKINTRPT
* [14] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_NYETINTRPT
* [15] | RW | 0x0 | ALT_USB_DEV_DOEPINT15_STUPPKTRCVD
* [31:16] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfercompl
*
* Transfer Completed Interrupt (XferCompl)
*
* Applies to IN and OUT endpoints.
*
* When Scatter/Gather DMA mode is enabled
*
* * For IN endpoint this field indicates that the requested data
*
* from the descriptor is moved from external system memory
*
* to internal FIFO.
*
* * For OUT endpoint this field indicates that the requested
*
* data from the internal FIFO is moved to external system
*
* memory. This interrupt is generated only when the
*
* corresponding endpoint descriptor is closed, and the IOC
*
* bit For the corresponding descriptor is Set.
*
* When Scatter/Gather DMA mode is disabled, this field
*
* indicates that the programmed transfer is complete on the
*
* AHB as well as on the USB, For this endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT | 0x1 | Transfer Completed Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_XFERCOMPL
*
* Transfer Completed Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_MSB 0
/* The width in bits of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_DEV_DOEPINT15_XFERCOMPL register field. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_XFERCOMPL field value from a register. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_DEV_DOEPINT15_XFERCOMPL register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_XFERCOMPL_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : epdisbld
*
* Endpoint Disabled Interrupt (EPDisbld)
*
* Applies to IN and OUT endpoints.
*
* This bit indicates that the endpoint is disabled per the
*
* application's request.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:----------------------------
* ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT | 0x1 | Endpoint Disabled Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_EPDISBLD
*
* Endpoint Disabled Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_LSB 1
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_MSB 1
/* The width in bits of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET_MSK 0x00000002
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_EPDISBLD register field value. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_CLR_MSK 0xfffffffd
/* The reset value of the ALT_USB_DEV_DOEPINT15_EPDISBLD register field. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_EPDISBLD field value from a register. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_USB_DEV_DOEPINT15_EPDISBLD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_EPDISBLD_SET(value) (((value) << 1) & 0x00000002)
/*
* Field : ahberr
*
* AHB Error (AHBErr)
*
* Applies to IN and OUT endpoints.
*
* This is generated only in Internal DMA mode when there is an
*
* AHB error during an AHB read/write. The application can read
*
* the corresponding endpoint DMA address register to get the
*
* error address.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT | 0x0 | No Interrupt
* ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT | 0x1 | AHB Error interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
*
* No Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_AHBERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_AHBERR
*
* AHB Error interrupt
*/
#define ALT_USB_DEV_DOEPINT15_AHBERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_LSB 2
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_MSB 2
/* The width in bits of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_SET_MSK 0x00000004
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_AHBERR register field value. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_CLR_MSK 0xfffffffb
/* The reset value of the ALT_USB_DEV_DOEPINT15_AHBERR register field. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_AHBERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_USB_DEV_DOEPINT15_AHBERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_AHBERR_SET(value) (((value) << 2) & 0x00000004)
/*
* Field : setup
*
* SETUP Phase Done (SetUp)
*
* Applies to control OUT endpoints only.
*
* Indicates that the SETUP phase For the control endpoint is
*
* complete and no more back-to-back SETUP packets were
*
* received For the current control transfer. On this interrupt, the
*
* application can decode the received SETUP data packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT15_SETUP_E_INACT | 0x0 | No SETUP Phase Done
* ALT_USB_DEV_DOEPINT15_SETUP_E_ACT | 0x1 | SETUP Phase Done
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
*
* No SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT15_SETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_SETUP
*
* SETUP Phase Done
*/
#define ALT_USB_DEV_DOEPINT15_SETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_MSB 3
/* The width in bits of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_SETUP_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_SETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_SETUP_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_DEV_DOEPINT15_SETUP register field. */
#define ALT_USB_DEV_DOEPINT15_SETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_SETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT15_SETUP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_DEV_DOEPINT15_SETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_SETUP_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : outtknepdis
*
* OUT Token Received When Endpoint Disabled (OUTTknEPdis)
*
* Applies only to control OUT endpoints.
*
* Indicates that an OUT token was received when the endpoint
*
* was not yet enabled. This interrupt is asserted on the endpoint
*
* For which the OUT token was received.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:---------------------------------------------
* ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT | 0x0 | No OUT Token Received When Endpoint Disabled
* ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT | 0x1 | OUT Token Received When Endpoint Disabled
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
*
* No OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS
*
* OUT Token Received When Endpoint Disabled
*/
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_LSB 4
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_MSB 4
/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET_MSK 0x00000010
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_CLR_MSK 0xffffffef
/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS field value from a register. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS_SET(value) (((value) << 4) & 0x00000010)
/*
* Field : stsphsercvd
*
* Status Phase Received For Control Write (StsPhseRcvd)
*
* This interrupt is valid only For Control OUT endpoints and only in
*
* Scatter Gather DMA mode.
*
* This interrupt is generated only after the core has transferred all
*
* the data that the host has sent during the data phase of a control
*
* write transfer, to the system memory buffer.
*
* The interrupt indicates to the application that the host has
*
* switched from data phase to the status phase of a Control Write
*
* transfer. The application can use this interrupt to ACK or STALL
*
* the Status phase, after it has decoded the data phase. This is
*
* applicable only in Case of Scatter Gather DMA mode.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------------------------------
* ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT | 0x0 | No Status Phase Received for Control Write
* ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT | 0x1 | Status Phase Received for Control Write
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
*
* No Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_STSPHSERCVD
*
* Status Phase Received for Control Write
*/
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_LSB 5
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_MSB 5
/* The width in bits of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET_MSK 0x00000020
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_CLR_MSK 0xffffffdf
/* The reset value of the ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_STSPHSERCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_USB_DEV_DOEPINT15_STSPHSERCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_STSPHSERCVD_SET(value) (((value) << 5) & 0x00000020)
/*
* Field : back2backsetup
*
* Back-to-Back SETUP Packets Received (Back2BackSETup)
*
* Applies to Control OUT endpoints only.
*
* This bit indicates that the core has received more than three
*
* back-to-back SETUP packets For this particular endpoint. For
*
* information about handling this interrupt,
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------------|:------|:---------------------------------------
* ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT | 0x0 | No Back-to-Back SETUP Packets Received
* ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT | 0x1 | Back-to-Back SETUP Packets Received
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
*
* No Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP
*
* Back-to-Back SETUP Packets Received
*/
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_MSB 6
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : outpkterr
*
* OUT Packet Error (OutPktErr)
*
* Applies to OUT endpoints Only
*
* This interrupt is valid only when thresholding is enabled. This interrupt is
* asserted when the
*
* core detects an overflow or a CRC error For non-Isochronous
*
* OUT packet.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------------
* ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT | 0x0 | No OUT Packet Error
* ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT | 0x1 | OUT Packet Error
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
*
* No OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_OUTPKTERR
*
* OUT Packet Error
*/
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_LSB 8
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_MSB 8
/* The width in bits of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET_MSK 0x00000100
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_CLR_MSK 0xfffffeff
/* The reset value of the ALT_USB_DEV_DOEPINT15_OUTPKTERR register field. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_OUTPKTERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_USB_DEV_DOEPINT15_OUTPKTERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_OUTPKTERR_SET(value) (((value) << 8) & 0x00000100)
/*
* Field : bnaintr
*
* BNA (Buffer Not Available) Interrupt (BNAIntr)
*
* This bit is valid only when Scatter/Gather DMA mode is enabled.
*
* The core generates this interrupt when the descriptor accessed
*
* is not ready For the Core to process, such as Host busy or DMA
*
* done
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT | 0x1 | BNA interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BNAINTR
*
* BNA interrupt
*/
#define ALT_USB_DEV_DOEPINT15_BNAINTR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_LSB 9
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_MSB 9
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET_MSK 0x00000200
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BNAINTR register field value. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_CLR_MSK 0xfffffdff
/* The reset value of the ALT_USB_DEV_DOEPINT15_BNAINTR register field. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BNAINTR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_USB_DEV_DOEPINT15_BNAINTR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BNAINTR_SET(value) (((value) << 9) & 0x00000200)
/*
* Field : pktdrpsts
*
* Packet Drop Status (PktDrpSts)
*
* This bit indicates to the application that an ISOC OUT packet has been dropped.
* This
*
* bit does not have an associated mask bit and does not generate an interrupt.
*
* Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic
* transfer
*
* interrupt feature is selected.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:-----------------------------
* ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT | 0x1 | Packet Drop Status interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_PKTDRPSTS
*
* Packet Drop Status interrupt
*/
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_LSB 11
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_MSB 11
/* The width in bits of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET_MSK 0x00000800
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_CLR_MSK 0xfffff7ff
/* The reset value of the ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_PKTDRPSTS field value from a register. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_USB_DEV_DOEPINT15_PKTDRPSTS register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_PKTDRPSTS_SET(value) (((value) << 11) & 0x00000800)
/*
* Field : bbleerr
*
* NAK Interrupt (BbleErr)
*
* The core generates this interrupt when babble is received for the endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :--------------------------------------|:------|:------------------
* ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT | 0x1 | BbleErr interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_BBLEERR
*
* BbleErr interrupt
*/
#define ALT_USB_DEV_DOEPINT15_BBLEERR_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_LSB 12
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_MSB 12
/* The width in bits of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET_MSK 0x00001000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_BBLEERR register field value. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_CLR_MSK 0xffffefff
/* The reset value of the ALT_USB_DEV_DOEPINT15_BBLEERR register field. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_BBLEERR field value from a register. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_USB_DEV_DOEPINT15_BBLEERR register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_BBLEERR_SET(value) (((value) << 12) & 0x00001000)
/*
* Field : nakintrpt
*
* NAK Interrupt (NAKInterrupt)
*
* The core generates this interrupt when a NAK is transmitted or received by the
* device.
*
* In case of isochronous IN endpoints the interrupt gets generated when a zero
* length
*
* packet is transmitted due to un-availability of data in the TXFifo.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:--------------
* ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT | 0x1 | NAK Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_NAKINTRPT
*
* NAK Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_LSB 13
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_MSB 13
/* The width in bits of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET_MSK 0x00002000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_CLR_MSK 0xffffdfff
/* The reset value of the ALT_USB_DEV_DOEPINT15_NAKINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_NAKINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_USB_DEV_DOEPINT15_NAKINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_NAKINTRPT_SET(value) (((value) << 13) & 0x00002000)
/*
* Field : nyetintrpt
*
* NYET Interrupt (NYETIntrpt)
*
* The core generates this interrupt when a NYET response is transmitted for a non
* isochronous OUT endpoint.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-----------------------------------------|:------|:---------------
* ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT | 0x0 | No interrupt
* ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT | 0x1 | NYET Interrupt
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
*
* No interrupt
*/
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPINT15_NYETINTRPT
*
* NYET Interrupt
*/
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_LSB 14
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_MSB 14
/* The width in bits of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET_MSK 0x00004000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_CLR_MSK 0xffffbfff
/* The reset value of the ALT_USB_DEV_DOEPINT15_NYETINTRPT register field. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_NYETINTRPT field value from a register. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_USB_DEV_DOEPINT15_NYETINTRPT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_NYETINTRPT_SET(value) (((value) << 14) & 0x00004000)
/*
* Field : stuppktrcvd
*
* Setup Packet Received
*
* Applicable for Control OUT Endpoints in only in the Buffer DMA Mode
*
* Set by the DWC_otg core, this bit indicates that this buffer holds 8 bytes of
*
* setup data. There is only one Setup packet per buffer. On receiving a
*
* Setup packet, the DWC_otg core closes the buffer and disables the
*
* corresponding endpoint. The application has to re-enable the endpoint to
*
* receive any OUT data for the Control Transfer and reprogram the buffer
*
* start address.
*
* Note: Because of the above behavior, the DWC_otg core can receive any
*
* number of back to back setup packets and one buffer for every setup
*
* packet is used.
*
* 1'b0: No Setup packet received
*
* 1'b1: Setup packet received
*
* Reset: 1’b0
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_LSB 15
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_MSB 15
/* The width in bits of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_WIDTH 1
/* The mask used to set the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_SET_MSK 0x00008000
/* The mask used to clear the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_CLR_MSK 0xffff7fff
/* The reset value of the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPINT15_STUPPKTRCVD field value from a register. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_USB_DEV_DOEPINT15_STUPPKTRCVD register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPINT15_STUPPKTRCVD_SET(value) (((value) << 15) & 0x00008000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPINT15.
*/
struct ALT_USB_DEV_DOEPINT15_s
{
uint32_t xfercompl : 1; /* ALT_USB_DEV_DOEPINT15_XFERCOMPL */
uint32_t epdisbld : 1; /* ALT_USB_DEV_DOEPINT15_EPDISBLD */
uint32_t ahberr : 1; /* ALT_USB_DEV_DOEPINT15_AHBERR */
uint32_t setup : 1; /* ALT_USB_DEV_DOEPINT15_SETUP */
uint32_t outtknepdis : 1; /* ALT_USB_DEV_DOEPINT15_OUTTKNEPDIS */
uint32_t stsphsercvd : 1; /* ALT_USB_DEV_DOEPINT15_STSPHSERCVD */
uint32_t back2backsetup : 1; /* ALT_USB_DEV_DOEPINT15_BACK2BACKSETUP */
uint32_t : 1; /* *UNDEFINED* */
uint32_t outpkterr : 1; /* ALT_USB_DEV_DOEPINT15_OUTPKTERR */
uint32_t bnaintr : 1; /* ALT_USB_DEV_DOEPINT15_BNAINTR */
uint32_t : 1; /* *UNDEFINED* */
uint32_t pktdrpsts : 1; /* ALT_USB_DEV_DOEPINT15_PKTDRPSTS */
uint32_t bbleerr : 1; /* ALT_USB_DEV_DOEPINT15_BBLEERR */
uint32_t nakintrpt : 1; /* ALT_USB_DEV_DOEPINT15_NAKINTRPT */
uint32_t nyetintrpt : 1; /* ALT_USB_DEV_DOEPINT15_NYETINTRPT */
uint32_t stuppktrcvd : 1; /* ALT_USB_DEV_DOEPINT15_STUPPKTRCVD */
uint32_t : 16; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPINT15. */
typedef volatile struct ALT_USB_DEV_DOEPINT15_s ALT_USB_DEV_DOEPINT15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPINT15 register. */
#define ALT_USB_DEV_DOEPINT15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPINT15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPINT15_OFST 0x4e8
/* The address of the ALT_USB_DEV_DOEPINT15 register. */
#define ALT_USB_DEV_DOEPINT15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPINT15_OFST))
/*
* Register : doeptsiz15
*
* Device OUT Endpoint 15 Transfer Size Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :--------|:-------|:------|:--------------------------------
* [18:0] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ15_XFERSIZE
* [28:19] | RW | 0x0 | ALT_USB_DEV_DOEPTSIZ15_PKTCNT
* [30:29] | R | 0x0 | ALT_USB_DEV_DOEPTSIZ15_RXDPID
* [31] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : xfersize
*
* Transfer Size (XferSize)
*
* Indicates the transfer size in bytes For endpoint 0. The core
*
* interrupts the application only after it has exhausted the transfer
*
* size amount of data. The transfer size can be Set to the
*
* maximum packet size of the endpoint, to be interrupted at the
*
* end of each packet.
*
* The core decrements this field every time a packet is read from
*
* the RxFIFO and written to the external memory.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_MSB 18
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_WIDTH 19
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET_MSK 0x0007ffff
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_CLR_MSK 0xfff80000
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_XFERSIZE field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_GET(value) (((value) & 0x0007ffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_XFERSIZE register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_XFERSIZE_SET(value) (((value) << 0) & 0x0007ffff)
/*
* Field : pktcnt
*
* Packet Count (PktCnt)
*
* This field is decremented to zero after a packet is written into the
*
* RxFIFO.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_LSB 19
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_MSB 28
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_WIDTH 10
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET_MSK 0x1ff80000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_CLR_MSK 0xe007ffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_PKTCNT field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_GET(value) (((value) & 0x1ff80000) >> 19)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_PKTCNT register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_PKTCNT_SET(value) (((value) << 19) & 0x1ff80000)
/*
* Field : rxdpid
*
* Applies to isochronous OUT endpoints only.
*
* This is the data PID received in the last packet for this endpoint.
*
* 2'b00: DATA0
*
* 2'b01: DATA2
*
* 2'b10: DATA1
*
* 2'b11: MDATA
*
* SETUP Packet Count (SUPCnt)
*
* Applies to control OUT Endpoints only.
*
* This field specifies the number of back-to-back SETUP data
*
* packets the endpoint can receive.
*
* 2'b01: 1 packet
*
* 2'b10: 2 packets
*
* 2'b11: 3 packets
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :------------------------------------------|:------|:-------------------
* ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 | 0x0 | DATA0
* ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 | 0x1 | DATA2 or 1 packet
* ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 | 0x2 | DATA1 or 2 packets
* ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 | 0x3 | MDATA or 3 packets
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
*
* DATA0
*/
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA0 0x0
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
*
* DATA2 or 1 packet
*/
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA2PKT1 0x1
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
*
* DATA1 or 2 packets
*/
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_DATA1PKT2 0x2
/*
* Enumerated value for register field ALT_USB_DEV_DOEPTSIZ15_RXDPID
*
* MDATA or 3 packets
*/
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_E_MDATAPKT3 0x3
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_LSB 29
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_MSB 30
/* The width in bits of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_WIDTH 2
/* The mask used to set the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET_MSK 0x60000000
/* The mask used to clear the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_CLR_MSK 0x9fffffff
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15_RXDPID register field. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPTSIZ15_RXDPID field value from a register. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_GET(value) (((value) & 0x60000000) >> 29)
/* Produces a ALT_USB_DEV_DOEPTSIZ15_RXDPID register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPTSIZ15_RXDPID_SET(value) (((value) << 29) & 0x60000000)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPTSIZ15.
*/
struct ALT_USB_DEV_DOEPTSIZ15_s
{
uint32_t xfersize : 19; /* ALT_USB_DEV_DOEPTSIZ15_XFERSIZE */
uint32_t pktcnt : 10; /* ALT_USB_DEV_DOEPTSIZ15_PKTCNT */
const uint32_t rxdpid : 2; /* ALT_USB_DEV_DOEPTSIZ15_RXDPID */
uint32_t : 1; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPTSIZ15. */
typedef volatile struct ALT_USB_DEV_DOEPTSIZ15_s ALT_USB_DEV_DOEPTSIZ15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPTSIZ15 register. */
#define ALT_USB_DEV_DOEPTSIZ15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPTSIZ15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPTSIZ15_OFST 0x4f0
/* The address of the ALT_USB_DEV_DOEPTSIZ15 register. */
#define ALT_USB_DEV_DOEPTSIZ15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPTSIZ15_OFST))
/*
* Register : doepdma15
*
* Device OUT Endpoint 15 DMA Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:--------------------------------
* [31:0] | RW | Unknown | ALT_USB_DEV_DOEPDMA15_DOEPDMA15
*
*/
/*
* Field : doepdma15
*
* Holds the start address of the external memory for storing or fetching endpoint
*
* data.
*
* Note: For control endpoints, this field stores control OUT data packets as well
* as
*
* SETUP transaction data packets. When more than three SETUP packets are
*
* received back-to-back, the SETUP data packet in the memory is overwritten.
*
* This register is incremented on every AHB transaction. The application can give
*
* only a DWORD-aligned address.
*
* When Scatter/Gather DMA mode is not enabled, the application programs the
*
* start address value in this field.
*
* When Scatter/Gather DMA mode is enabled, this field indicates the base
*
* pointer for the descriptor list.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMA15_DOEPDMA15 field value from a register. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMA15_DOEPDMA15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMA15_DOEPDMA15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMA15.
*/
struct ALT_USB_DEV_DOEPDMA15_s
{
uint32_t doepdma15 : 32; /* ALT_USB_DEV_DOEPDMA15_DOEPDMA15 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMA15. */
typedef volatile struct ALT_USB_DEV_DOEPDMA15_s ALT_USB_DEV_DOEPDMA15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMA15 register. */
#define ALT_USB_DEV_DOEPDMA15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMA15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMA15_OFST 0x4f4
/* The address of the ALT_USB_DEV_DOEPDMA15 register. */
#define ALT_USB_DEV_DOEPDMA15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMA15_OFST))
/*
* Register : doepdmab15
*
* Device OUT Endpoint 15 Buffer Address Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:--------|:----------------------------------
* [31:0] | R | Unknown | ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15
*
*/
/*
* Field : doepdmab15
*
* Holds the current buffer address.This register is updated as and when the data
*
* transfer for the corresponding end point is in progress.
*
* This register is present only in Scatter/Gather DMA mode. Otherwise this field
* is
*
* reserved.
*
* Field Access Macros:
*
*/
/* The Least Significant Bit (LSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_MSB 31
/* The width in bits of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_WIDTH 32
/* The mask used to set the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET_MSK 0xffffffff
/* The mask used to clear the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_CLR_MSK 0x00000000
/* The reset value of the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field is UNKNOWN. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_RESET 0x0
/* Extracts the ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 field value from a register. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 register field value suitable for setting the register. */
#define ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15_SET(value) (((value) << 0) & 0xffffffff)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_DEV_DOEPDMAB15.
*/
struct ALT_USB_DEV_DOEPDMAB15_s
{
const uint32_t doepdmab15 : 32; /* ALT_USB_DEV_DOEPDMAB15_DOEPDMAB15 */
};
/* The typedef declaration for register ALT_USB_DEV_DOEPDMAB15. */
typedef volatile struct ALT_USB_DEV_DOEPDMAB15_s ALT_USB_DEV_DOEPDMAB15_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_DEV_DOEPDMAB15 register. */
#define ALT_USB_DEV_DOEPDMAB15_RESET 0x00000000
/* The byte offset of the ALT_USB_DEV_DOEPDMAB15 register from the beginning of the component. */
#define ALT_USB_DEV_DOEPDMAB15_OFST 0x4fc
/* The address of the ALT_USB_DEV_DOEPDMAB15 register. */
#define ALT_USB_DEV_DOEPDMAB15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DOEPDMAB15_OFST))
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_USB_DEV.
*/
struct ALT_USB_DEV_s
{
volatile ALT_USB_DEV_DCFG_t dcfg; /* ALT_USB_DEV_DCFG */
volatile ALT_USB_DEV_DCTL_t dctl; /* ALT_USB_DEV_DCTL */
volatile ALT_USB_DEV_DSTS_t dsts; /* ALT_USB_DEV_DSTS */
volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPMSK_t diepmsk; /* ALT_USB_DEV_DIEPMSK */
volatile ALT_USB_DEV_DOEPMSK_t doepmsk; /* ALT_USB_DEV_DOEPMSK */
volatile ALT_USB_DEV_DAINT_t daint; /* ALT_USB_DEV_DAINT */
volatile ALT_USB_DEV_DAINTMSK_t daintmsk; /* ALT_USB_DEV_DAINTMSK */
volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
volatile ALT_USB_DEV_DVBUSDIS_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */
volatile ALT_USB_DEV_DVBUSPULSE_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */
volatile ALT_USB_DEV_DTHRCTL_t dthrctl; /* ALT_USB_DEV_DTHRCTL */
volatile ALT_USB_DEV_DIEPEMPMSK_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */
volatile uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPCTL0_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */
volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT0_t diepint0; /* ALT_USB_DEV_DIEPINT0 */
volatile uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ0_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */
volatile ALT_USB_DEV_DIEPDMA0_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */
volatile ALT_USB_DEV_DTXFSTS0_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */
volatile ALT_USB_DEV_DIEPDMAB0_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */
volatile ALT_USB_DEV_DIEPCTL1_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */
volatile uint32_t _pad_0x124_0x127; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT1_t diepint1; /* ALT_USB_DEV_DIEPINT1 */
volatile uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ1_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */
volatile ALT_USB_DEV_DIEPDMA1_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */
volatile ALT_USB_DEV_DTXFSTS1_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */
volatile ALT_USB_DEV_DIEPDMAB1_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */
volatile ALT_USB_DEV_DIEPCTL2_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */
volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT2_t diepint2; /* ALT_USB_DEV_DIEPINT2 */
volatile uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ2_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */
volatile ALT_USB_DEV_DIEPDMA2_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */
volatile ALT_USB_DEV_DTXFSTS2_t dtxfsts2; /* ALT_USB_DEV_DTXFSTS2 */
volatile ALT_USB_DEV_DIEPDMAB2_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */
volatile ALT_USB_DEV_DIEPCTL3_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */
volatile uint32_t _pad_0x164_0x167; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT3_t diepint3; /* ALT_USB_DEV_DIEPINT3 */
volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ3_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */
volatile ALT_USB_DEV_DIEPDMA3_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */
volatile ALT_USB_DEV_DTXFSTS3_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */
volatile ALT_USB_DEV_DIEPDMAB3_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */
volatile ALT_USB_DEV_DIEPCTL4_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */
volatile uint32_t _pad_0x184_0x187; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT4_t diepint4; /* ALT_USB_DEV_DIEPINT4 */
volatile uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ4_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */
volatile ALT_USB_DEV_DIEPDMA4_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */
volatile ALT_USB_DEV_DTXFSTS4_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */
volatile ALT_USB_DEV_DIEPDMAB4_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */
volatile ALT_USB_DEV_DIEPCTL5_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */
volatile uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT5_t diepint5; /* ALT_USB_DEV_DIEPINT5 */
volatile uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ5_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */
volatile ALT_USB_DEV_DIEPDMA5_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */
volatile ALT_USB_DEV_DTXFSTS5_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */
volatile ALT_USB_DEV_DIEPDMAB5_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */
volatile ALT_USB_DEV_DIEPCTL6_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */
volatile uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT6_t diepint6; /* ALT_USB_DEV_DIEPINT6 */
volatile uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ6_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */
volatile ALT_USB_DEV_DIEPDMA6_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */
volatile ALT_USB_DEV_DTXFSTS6_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */
volatile ALT_USB_DEV_DIEPDMAB6_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */
volatile ALT_USB_DEV_DIEPCTL7_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */
volatile uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT7_t diepint7; /* ALT_USB_DEV_DIEPINT7 */
volatile uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ7_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */
volatile ALT_USB_DEV_DIEPDMA7_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */
volatile ALT_USB_DEV_DTXFSTS7_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */
volatile ALT_USB_DEV_DIEPDMAB7_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */
volatile ALT_USB_DEV_DIEPCTL8_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */
volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT8_t diepint8; /* ALT_USB_DEV_DIEPINT8 */
volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ8_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */
volatile ALT_USB_DEV_DIEPDMA8_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */
volatile ALT_USB_DEV_DTXFSTS8_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */
volatile ALT_USB_DEV_DIEPDMAB8_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */
volatile ALT_USB_DEV_DIEPCTL9_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */
volatile uint32_t _pad_0x224_0x227; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT9_t diepint9; /* ALT_USB_DEV_DIEPINT9 */
volatile uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ9_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */
volatile ALT_USB_DEV_DIEPDMA9_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */
volatile ALT_USB_DEV_DTXFSTS9_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */
volatile ALT_USB_DEV_DIEPDMAB9_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */
volatile ALT_USB_DEV_DIEPCTL10_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */
volatile uint32_t _pad_0x244_0x247; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT10_t diepint10; /* ALT_USB_DEV_DIEPINT10 */
volatile uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ10_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */
volatile ALT_USB_DEV_DIEPDMA10_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */
volatile ALT_USB_DEV_DTXFSTS10_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */
volatile ALT_USB_DEV_DIEPDMAB10_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */
volatile ALT_USB_DEV_DIEPCTL11_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */
volatile uint32_t _pad_0x264_0x267; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT11_t diepint11; /* ALT_USB_DEV_DIEPINT11 */
volatile uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ11_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */
volatile ALT_USB_DEV_DIEPDMA11_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */
volatile ALT_USB_DEV_DTXFSTS11_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */
volatile ALT_USB_DEV_DIEPDMAB11_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */
volatile ALT_USB_DEV_DIEPCTL12_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */
volatile uint32_t _pad_0x284_0x287; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT12_t diepint12; /* ALT_USB_DEV_DIEPINT12 */
volatile uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ12_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */
volatile ALT_USB_DEV_DIEPDMA12_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */
volatile ALT_USB_DEV_DTXFSTS12_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */
volatile ALT_USB_DEV_DIEPDMAB12_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */
volatile ALT_USB_DEV_DIEPCTL13_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */
volatile uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT13_t diepint13; /* ALT_USB_DEV_DIEPINT13 */
volatile uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ13_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */
volatile ALT_USB_DEV_DIEPDMA13_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */
volatile ALT_USB_DEV_DTXFSTS13_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */
volatile ALT_USB_DEV_DIEPDMAB13_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */
volatile ALT_USB_DEV_DIEPCTL14_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */
volatile uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT14_t diepint14; /* ALT_USB_DEV_DIEPINT14 */
volatile uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ14_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */
volatile ALT_USB_DEV_DIEPDMA14_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */
volatile ALT_USB_DEV_DTXFSTS14_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */
volatile ALT_USB_DEV_DIEPDMAB14_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */
volatile ALT_USB_DEV_DIEPCTL15_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */
volatile uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPINT15_t diepint15; /* ALT_USB_DEV_DIEPINT15 */
volatile uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */
volatile ALT_USB_DEV_DIEPTSIZ15_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */
volatile ALT_USB_DEV_DIEPDMA15_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */
volatile ALT_USB_DEV_DTXFSTS15_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */
volatile ALT_USB_DEV_DIEPDMAB15_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */
volatile ALT_USB_DEV_DOEPCTL0_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */
volatile uint32_t _pad_0x304_0x307; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT0_t doepint0; /* ALT_USB_DEV_DOEPINT0 */
volatile uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ0_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */
volatile ALT_USB_DEV_DOEPDMA0_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */
volatile uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB0_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */
volatile ALT_USB_DEV_DOEPCTL1_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */
volatile uint32_t _pad_0x324_0x327; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT1_t doepint1; /* ALT_USB_DEV_DOEPINT1 */
volatile uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ1_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */
volatile ALT_USB_DEV_DOEPDMA1_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */
volatile uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB1_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */
volatile ALT_USB_DEV_DOEPCTL2_t doepctl2; /* ALT_USB_DEV_DOEPCTL2 */
volatile uint32_t _pad_0x344_0x347; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT2_t doepint2; /* ALT_USB_DEV_DOEPINT2 */
volatile uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ2_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */
volatile ALT_USB_DEV_DOEPDMA2_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */
volatile uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB2_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */
volatile ALT_USB_DEV_DOEPCTL3_t doepctl3; /* ALT_USB_DEV_DOEPCTL3 */
volatile uint32_t _pad_0x364_0x367; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT3_t doepint3; /* ALT_USB_DEV_DOEPINT3 */
volatile uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ3_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */
volatile ALT_USB_DEV_DOEPDMA3_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */
volatile uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB3_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */
volatile ALT_USB_DEV_DOEPCTL4_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */
volatile uint32_t _pad_0x384_0x387; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT4_t doepint4; /* ALT_USB_DEV_DOEPINT4 */
volatile uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ4_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */
volatile ALT_USB_DEV_DOEPDMA4_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */
volatile uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB4_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */
volatile ALT_USB_DEV_DOEPCTL5_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */
volatile uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT5_t doepint5; /* ALT_USB_DEV_DOEPINT5 */
volatile uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ5_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */
volatile ALT_USB_DEV_DOEPDMA5_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */
volatile uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB5_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */
volatile ALT_USB_DEV_DOEPCTL6_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */
volatile uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT6_t doepint6; /* ALT_USB_DEV_DOEPINT6 */
volatile uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ6_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */
volatile ALT_USB_DEV_DOEPDMA6_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */
volatile uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB6_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */
volatile ALT_USB_DEV_DOEPCTL7_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */
volatile uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT7_t doepint7; /* ALT_USB_DEV_DOEPINT7 */
volatile uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ7_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */
volatile ALT_USB_DEV_DOEPDMA7_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */
volatile uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB7_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */
volatile ALT_USB_DEV_DOEPCTL8_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */
volatile uint32_t _pad_0x404_0x407; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT8_t doepint8; /* ALT_USB_DEV_DOEPINT8 */
volatile uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ8_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */
volatile ALT_USB_DEV_DOEPDMA8_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */
volatile uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB8_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */
volatile ALT_USB_DEV_DOEPCTL9_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */
volatile uint32_t _pad_0x424_0x427; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT9_t doepint9; /* ALT_USB_DEV_DOEPINT9 */
volatile uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ9_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */
volatile ALT_USB_DEV_DOEPDMA9_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */
volatile uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB9_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */
volatile ALT_USB_DEV_DOEPCTL10_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */
volatile uint32_t _pad_0x444_0x447; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT10_t doepint10; /* ALT_USB_DEV_DOEPINT10 */
volatile uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ10_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */
volatile ALT_USB_DEV_DOEPDMA10_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */
volatile uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB10_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */
volatile ALT_USB_DEV_DOEPCTL11_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */
volatile uint32_t _pad_0x464_0x467; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT11_t doepint11; /* ALT_USB_DEV_DOEPINT11 */
volatile uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ11_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */
volatile ALT_USB_DEV_DOEPDMA11_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */
volatile uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB11_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */
volatile ALT_USB_DEV_DOEPCTL12_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */
volatile uint32_t _pad_0x484_0x487; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT12_t doepint12; /* ALT_USB_DEV_DOEPINT12 */
volatile uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ12_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */
volatile ALT_USB_DEV_DOEPDMA12_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */
volatile uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB12_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */
volatile ALT_USB_DEV_DOEPCTL13_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */
volatile uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT13_t doepint13; /* ALT_USB_DEV_DOEPINT13 */
volatile uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ13_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */
volatile ALT_USB_DEV_DOEPDMA13_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */
volatile uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB13_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */
volatile ALT_USB_DEV_DOEPCTL14_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */
volatile uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT14_t doepint14; /* ALT_USB_DEV_DOEPINT14 */
volatile uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ14_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */
volatile ALT_USB_DEV_DOEPDMA14_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */
volatile uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB14_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */
volatile ALT_USB_DEV_DOEPCTL15_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */
volatile uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPINT15_t doepint15; /* ALT_USB_DEV_DOEPINT15 */
volatile uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPTSIZ15_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */
volatile ALT_USB_DEV_DOEPDMA15_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */
volatile uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */
volatile ALT_USB_DEV_DOEPDMAB15_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */
};
/* The typedef declaration for register group ALT_USB_DEV. */
typedef volatile struct ALT_USB_DEV_s ALT_USB_DEV_t;
/* The struct declaration for the raw register contents of register group ALT_USB_DEV. */
struct ALT_USB_DEV_raw_s
{
volatile uint32_t dcfg; /* ALT_USB_DEV_DCFG */
volatile uint32_t dctl; /* ALT_USB_DEV_DCTL */
volatile uint32_t dsts; /* ALT_USB_DEV_DSTS */
volatile uint32_t _pad_0xc_0xf; /* *UNDEFINED* */
volatile uint32_t diepmsk; /* ALT_USB_DEV_DIEPMSK */
volatile uint32_t doepmsk; /* ALT_USB_DEV_DOEPMSK */
volatile uint32_t daint; /* ALT_USB_DEV_DAINT */
volatile uint32_t daintmsk; /* ALT_USB_DEV_DAINTMSK */
volatile uint32_t _pad_0x20_0x27[2]; /* *UNDEFINED* */
volatile uint32_t dvbusdis; /* ALT_USB_DEV_DVBUSDIS */
volatile uint32_t dvbuspulse; /* ALT_USB_DEV_DVBUSPULSE */
volatile uint32_t dthrctl; /* ALT_USB_DEV_DTHRCTL */
volatile uint32_t diepempmsk; /* ALT_USB_DEV_DIEPEMPMSK */
volatile uint32_t _pad_0x38_0xff[50]; /* *UNDEFINED* */
volatile uint32_t diepctl0; /* ALT_USB_DEV_DIEPCTL0 */
volatile uint32_t _pad_0x104_0x107; /* *UNDEFINED* */
volatile uint32_t diepint0; /* ALT_USB_DEV_DIEPINT0 */
volatile uint32_t _pad_0x10c_0x10f; /* *UNDEFINED* */
volatile uint32_t dieptsiz0; /* ALT_USB_DEV_DIEPTSIZ0 */
volatile uint32_t diepdma0; /* ALT_USB_DEV_DIEPDMA0 */
volatile uint32_t dtxfsts0; /* ALT_USB_DEV_DTXFSTS0 */
volatile uint32_t diepdmab0; /* ALT_USB_DEV_DIEPDMAB0 */
volatile uint32_t diepctl1; /* ALT_USB_DEV_DIEPCTL1 */
volatile uint32_t _pad_0x124_0x127; /* *UNDEFINED* */
volatile uint32_t diepint1; /* ALT_USB_DEV_DIEPINT1 */
volatile uint32_t _pad_0x12c_0x12f; /* *UNDEFINED* */
volatile uint32_t dieptsiz1; /* ALT_USB_DEV_DIEPTSIZ1 */
volatile uint32_t diepdma1; /* ALT_USB_DEV_DIEPDMA1 */
volatile uint32_t dtxfsts1; /* ALT_USB_DEV_DTXFSTS1 */
volatile uint32_t diepdmab1; /* ALT_USB_DEV_DIEPDMAB1 */
volatile uint32_t diepctl2; /* ALT_USB_DEV_DIEPCTL2 */
volatile uint32_t _pad_0x144_0x147; /* *UNDEFINED* */
volatile uint32_t diepint2; /* ALT_USB_DEV_DIEPINT2 */
volatile uint32_t _pad_0x14c_0x14f; /* *UNDEFINED* */
volatile uint32_t dieptsiz2; /* ALT_USB_DEV_DIEPTSIZ2 */
volatile uint32_t diepdma2; /* ALT_USB_DEV_DIEPDMA2 */
volatile uint32_t dtxfsts2; /* ALT_USB_DEV_DTXFSTS2 */
volatile uint32_t diepdmab2; /* ALT_USB_DEV_DIEPDMAB2 */
volatile uint32_t diepctl3; /* ALT_USB_DEV_DIEPCTL3 */
volatile uint32_t _pad_0x164_0x167; /* *UNDEFINED* */
volatile uint32_t diepint3; /* ALT_USB_DEV_DIEPINT3 */
volatile uint32_t _pad_0x16c_0x16f; /* *UNDEFINED* */
volatile uint32_t dieptsiz3; /* ALT_USB_DEV_DIEPTSIZ3 */
volatile uint32_t diepdma3; /* ALT_USB_DEV_DIEPDMA3 */
volatile uint32_t dtxfsts3; /* ALT_USB_DEV_DTXFSTS3 */
volatile uint32_t diepdmab3; /* ALT_USB_DEV_DIEPDMAB3 */
volatile uint32_t diepctl4; /* ALT_USB_DEV_DIEPCTL4 */
volatile uint32_t _pad_0x184_0x187; /* *UNDEFINED* */
volatile uint32_t diepint4; /* ALT_USB_DEV_DIEPINT4 */
volatile uint32_t _pad_0x18c_0x18f; /* *UNDEFINED* */
volatile uint32_t dieptsiz4; /* ALT_USB_DEV_DIEPTSIZ4 */
volatile uint32_t diepdma4; /* ALT_USB_DEV_DIEPDMA4 */
volatile uint32_t dtxfsts4; /* ALT_USB_DEV_DTXFSTS4 */
volatile uint32_t diepdmab4; /* ALT_USB_DEV_DIEPDMAB4 */
volatile uint32_t diepctl5; /* ALT_USB_DEV_DIEPCTL5 */
volatile uint32_t _pad_0x1a4_0x1a7; /* *UNDEFINED* */
volatile uint32_t diepint5; /* ALT_USB_DEV_DIEPINT5 */
volatile uint32_t _pad_0x1ac_0x1af; /* *UNDEFINED* */
volatile uint32_t dieptsiz5; /* ALT_USB_DEV_DIEPTSIZ5 */
volatile uint32_t diepdma5; /* ALT_USB_DEV_DIEPDMA5 */
volatile uint32_t dtxfsts5; /* ALT_USB_DEV_DTXFSTS5 */
volatile uint32_t diepdmab5; /* ALT_USB_DEV_DIEPDMAB5 */
volatile uint32_t diepctl6; /* ALT_USB_DEV_DIEPCTL6 */
volatile uint32_t _pad_0x1c4_0x1c7; /* *UNDEFINED* */
volatile uint32_t diepint6; /* ALT_USB_DEV_DIEPINT6 */
volatile uint32_t _pad_0x1cc_0x1cf; /* *UNDEFINED* */
volatile uint32_t dieptsiz6; /* ALT_USB_DEV_DIEPTSIZ6 */
volatile uint32_t diepdma6; /* ALT_USB_DEV_DIEPDMA6 */
volatile uint32_t dtxfsts6; /* ALT_USB_DEV_DTXFSTS6 */
volatile uint32_t diepdmab6; /* ALT_USB_DEV_DIEPDMAB6 */
volatile uint32_t diepctl7; /* ALT_USB_DEV_DIEPCTL7 */
volatile uint32_t _pad_0x1e4_0x1e7; /* *UNDEFINED* */
volatile uint32_t diepint7; /* ALT_USB_DEV_DIEPINT7 */
volatile uint32_t _pad_0x1ec_0x1ef; /* *UNDEFINED* */
volatile uint32_t dieptsiz7; /* ALT_USB_DEV_DIEPTSIZ7 */
volatile uint32_t diepdma7; /* ALT_USB_DEV_DIEPDMA7 */
volatile uint32_t dtxfsts7; /* ALT_USB_DEV_DTXFSTS7 */
volatile uint32_t diepdmab7; /* ALT_USB_DEV_DIEPDMAB7 */
volatile uint32_t diepctl8; /* ALT_USB_DEV_DIEPCTL8 */
volatile uint32_t _pad_0x204_0x207; /* *UNDEFINED* */
volatile uint32_t diepint8; /* ALT_USB_DEV_DIEPINT8 */
volatile uint32_t _pad_0x20c_0x20f; /* *UNDEFINED* */
volatile uint32_t dieptsiz8; /* ALT_USB_DEV_DIEPTSIZ8 */
volatile uint32_t diepdma8; /* ALT_USB_DEV_DIEPDMA8 */
volatile uint32_t dtxfsts8; /* ALT_USB_DEV_DTXFSTS8 */
volatile uint32_t diepdmab8; /* ALT_USB_DEV_DIEPDMAB8 */
volatile uint32_t diepctl9; /* ALT_USB_DEV_DIEPCTL9 */
volatile uint32_t _pad_0x224_0x227; /* *UNDEFINED* */
volatile uint32_t diepint9; /* ALT_USB_DEV_DIEPINT9 */
volatile uint32_t _pad_0x22c_0x22f; /* *UNDEFINED* */
volatile uint32_t dieptsiz9; /* ALT_USB_DEV_DIEPTSIZ9 */
volatile uint32_t diepdma9; /* ALT_USB_DEV_DIEPDMA9 */
volatile uint32_t dtxfsts9; /* ALT_USB_DEV_DTXFSTS9 */
volatile uint32_t diepdmab9; /* ALT_USB_DEV_DIEPDMAB9 */
volatile uint32_t diepctl10; /* ALT_USB_DEV_DIEPCTL10 */
volatile uint32_t _pad_0x244_0x247; /* *UNDEFINED* */
volatile uint32_t diepint10; /* ALT_USB_DEV_DIEPINT10 */
volatile uint32_t _pad_0x24c_0x24f; /* *UNDEFINED* */
volatile uint32_t dieptsiz10; /* ALT_USB_DEV_DIEPTSIZ10 */
volatile uint32_t diepdma10; /* ALT_USB_DEV_DIEPDMA10 */
volatile uint32_t dtxfsts10; /* ALT_USB_DEV_DTXFSTS10 */
volatile uint32_t diepdmab10; /* ALT_USB_DEV_DIEPDMAB10 */
volatile uint32_t diepctl11; /* ALT_USB_DEV_DIEPCTL11 */
volatile uint32_t _pad_0x264_0x267; /* *UNDEFINED* */
volatile uint32_t diepint11; /* ALT_USB_DEV_DIEPINT11 */
volatile uint32_t _pad_0x26c_0x26f; /* *UNDEFINED* */
volatile uint32_t dieptsiz11; /* ALT_USB_DEV_DIEPTSIZ11 */
volatile uint32_t diepdma11; /* ALT_USB_DEV_DIEPDMA11 */
volatile uint32_t dtxfsts11; /* ALT_USB_DEV_DTXFSTS11 */
volatile uint32_t diepdmab11; /* ALT_USB_DEV_DIEPDMAB11 */
volatile uint32_t diepctl12; /* ALT_USB_DEV_DIEPCTL12 */
volatile uint32_t _pad_0x284_0x287; /* *UNDEFINED* */
volatile uint32_t diepint12; /* ALT_USB_DEV_DIEPINT12 */
volatile uint32_t _pad_0x28c_0x28f; /* *UNDEFINED* */
volatile uint32_t dieptsiz12; /* ALT_USB_DEV_DIEPTSIZ12 */
volatile uint32_t diepdma12; /* ALT_USB_DEV_DIEPDMA12 */
volatile uint32_t dtxfsts12; /* ALT_USB_DEV_DTXFSTS12 */
volatile uint32_t diepdmab12; /* ALT_USB_DEV_DIEPDMAB12 */
volatile uint32_t diepctl13; /* ALT_USB_DEV_DIEPCTL13 */
volatile uint32_t _pad_0x2a4_0x2a7; /* *UNDEFINED* */
volatile uint32_t diepint13; /* ALT_USB_DEV_DIEPINT13 */
volatile uint32_t _pad_0x2ac_0x2af; /* *UNDEFINED* */
volatile uint32_t dieptsiz13; /* ALT_USB_DEV_DIEPTSIZ13 */
volatile uint32_t diepdma13; /* ALT_USB_DEV_DIEPDMA13 */
volatile uint32_t dtxfsts13; /* ALT_USB_DEV_DTXFSTS13 */
volatile uint32_t diepdmab13; /* ALT_USB_DEV_DIEPDMAB13 */
volatile uint32_t diepctl14; /* ALT_USB_DEV_DIEPCTL14 */
volatile uint32_t _pad_0x2c4_0x2c7; /* *UNDEFINED* */
volatile uint32_t diepint14; /* ALT_USB_DEV_DIEPINT14 */
volatile uint32_t _pad_0x2cc_0x2cf; /* *UNDEFINED* */
volatile uint32_t dieptsiz14; /* ALT_USB_DEV_DIEPTSIZ14 */
volatile uint32_t diepdma14; /* ALT_USB_DEV_DIEPDMA14 */
volatile uint32_t dtxfsts14; /* ALT_USB_DEV_DTXFSTS14 */
volatile uint32_t diepdmab14; /* ALT_USB_DEV_DIEPDMAB14 */
volatile uint32_t diepctl15; /* ALT_USB_DEV_DIEPCTL15 */
volatile uint32_t _pad_0x2e4_0x2e7; /* *UNDEFINED* */
volatile uint32_t diepint15; /* ALT_USB_DEV_DIEPINT15 */
volatile uint32_t _pad_0x2ec_0x2ef; /* *UNDEFINED* */
volatile uint32_t dieptsiz15; /* ALT_USB_DEV_DIEPTSIZ15 */
volatile uint32_t diepdma15; /* ALT_USB_DEV_DIEPDMA15 */
volatile uint32_t dtxfsts15; /* ALT_USB_DEV_DTXFSTS15 */
volatile uint32_t diepdmab15; /* ALT_USB_DEV_DIEPDMAB15 */
volatile uint32_t doepctl0; /* ALT_USB_DEV_DOEPCTL0 */
volatile uint32_t _pad_0x304_0x307; /* *UNDEFINED* */
volatile uint32_t doepint0; /* ALT_USB_DEV_DOEPINT0 */
volatile uint32_t _pad_0x30c_0x30f; /* *UNDEFINED* */
volatile uint32_t doeptsiz0; /* ALT_USB_DEV_DOEPTSIZ0 */
volatile uint32_t doepdma0; /* ALT_USB_DEV_DOEPDMA0 */
volatile uint32_t _pad_0x318_0x31b; /* *UNDEFINED* */
volatile uint32_t doepdmab0; /* ALT_USB_DEV_DOEPDMAB0 */
volatile uint32_t doepctl1; /* ALT_USB_DEV_DOEPCTL1 */
volatile uint32_t _pad_0x324_0x327; /* *UNDEFINED* */
volatile uint32_t doepint1; /* ALT_USB_DEV_DOEPINT1 */
volatile uint32_t _pad_0x32c_0x32f; /* *UNDEFINED* */
volatile uint32_t doeptsiz1; /* ALT_USB_DEV_DOEPTSIZ1 */
volatile uint32_t doepdma1; /* ALT_USB_DEV_DOEPDMA1 */
volatile uint32_t _pad_0x338_0x33b; /* *UNDEFINED* */
volatile uint32_t doepdmab1; /* ALT_USB_DEV_DOEPDMAB1 */
volatile uint32_t doepctl2; /* ALT_USB_DEV_DOEPCTL2 */
volatile uint32_t _pad_0x344_0x347; /* *UNDEFINED* */
volatile uint32_t doepint2; /* ALT_USB_DEV_DOEPINT2 */
volatile uint32_t _pad_0x34c_0x34f; /* *UNDEFINED* */
volatile uint32_t doeptsiz2; /* ALT_USB_DEV_DOEPTSIZ2 */
volatile uint32_t doepdma2; /* ALT_USB_DEV_DOEPDMA2 */
volatile uint32_t _pad_0x358_0x35b; /* *UNDEFINED* */
volatile uint32_t doepdmab2; /* ALT_USB_DEV_DOEPDMAB2 */
volatile uint32_t doepctl3; /* ALT_USB_DEV_DOEPCTL3 */
volatile uint32_t _pad_0x364_0x367; /* *UNDEFINED* */
volatile uint32_t doepint3; /* ALT_USB_DEV_DOEPINT3 */
volatile uint32_t _pad_0x36c_0x36f; /* *UNDEFINED* */
volatile uint32_t doeptsiz3; /* ALT_USB_DEV_DOEPTSIZ3 */
volatile uint32_t doepdma3; /* ALT_USB_DEV_DOEPDMA3 */
volatile uint32_t _pad_0x378_0x37b; /* *UNDEFINED* */
volatile uint32_t doepdmab3; /* ALT_USB_DEV_DOEPDMAB3 */
volatile uint32_t doepctl4; /* ALT_USB_DEV_DOEPCTL4 */
volatile uint32_t _pad_0x384_0x387; /* *UNDEFINED* */
volatile uint32_t doepint4; /* ALT_USB_DEV_DOEPINT4 */
volatile uint32_t _pad_0x38c_0x38f; /* *UNDEFINED* */
volatile uint32_t doeptsiz4; /* ALT_USB_DEV_DOEPTSIZ4 */
volatile uint32_t doepdma4; /* ALT_USB_DEV_DOEPDMA4 */
volatile uint32_t _pad_0x398_0x39b; /* *UNDEFINED* */
volatile uint32_t doepdmab4; /* ALT_USB_DEV_DOEPDMAB4 */
volatile uint32_t doepctl5; /* ALT_USB_DEV_DOEPCTL5 */
volatile uint32_t _pad_0x3a4_0x3a7; /* *UNDEFINED* */
volatile uint32_t doepint5; /* ALT_USB_DEV_DOEPINT5 */
volatile uint32_t _pad_0x3ac_0x3af; /* *UNDEFINED* */
volatile uint32_t doeptsiz5; /* ALT_USB_DEV_DOEPTSIZ5 */
volatile uint32_t doepdma5; /* ALT_USB_DEV_DOEPDMA5 */
volatile uint32_t _pad_0x3b8_0x3bb; /* *UNDEFINED* */
volatile uint32_t doepdmab5; /* ALT_USB_DEV_DOEPDMAB5 */
volatile uint32_t doepctl6; /* ALT_USB_DEV_DOEPCTL6 */
volatile uint32_t _pad_0x3c4_0x3c7; /* *UNDEFINED* */
volatile uint32_t doepint6; /* ALT_USB_DEV_DOEPINT6 */
volatile uint32_t _pad_0x3cc_0x3cf; /* *UNDEFINED* */
volatile uint32_t doeptsiz6; /* ALT_USB_DEV_DOEPTSIZ6 */
volatile uint32_t doepdma6; /* ALT_USB_DEV_DOEPDMA6 */
volatile uint32_t _pad_0x3d8_0x3db; /* *UNDEFINED* */
volatile uint32_t doepdmab6; /* ALT_USB_DEV_DOEPDMAB6 */
volatile uint32_t doepctl7; /* ALT_USB_DEV_DOEPCTL7 */
volatile uint32_t _pad_0x3e4_0x3e7; /* *UNDEFINED* */
volatile uint32_t doepint7; /* ALT_USB_DEV_DOEPINT7 */
volatile uint32_t _pad_0x3ec_0x3ef; /* *UNDEFINED* */
volatile uint32_t doeptsiz7; /* ALT_USB_DEV_DOEPTSIZ7 */
volatile uint32_t doepdma7; /* ALT_USB_DEV_DOEPDMA7 */
volatile uint32_t _pad_0x3f8_0x3fb; /* *UNDEFINED* */
volatile uint32_t doepdmab7; /* ALT_USB_DEV_DOEPDMAB7 */
volatile uint32_t doepctl8; /* ALT_USB_DEV_DOEPCTL8 */
volatile uint32_t _pad_0x404_0x407; /* *UNDEFINED* */
volatile uint32_t doepint8; /* ALT_USB_DEV_DOEPINT8 */
volatile uint32_t _pad_0x40c_0x40f; /* *UNDEFINED* */
volatile uint32_t doeptsiz8; /* ALT_USB_DEV_DOEPTSIZ8 */
volatile uint32_t doepdma8; /* ALT_USB_DEV_DOEPDMA8 */
volatile uint32_t _pad_0x418_0x41b; /* *UNDEFINED* */
volatile uint32_t doepdmab8; /* ALT_USB_DEV_DOEPDMAB8 */
volatile uint32_t doepctl9; /* ALT_USB_DEV_DOEPCTL9 */
volatile uint32_t _pad_0x424_0x427; /* *UNDEFINED* */
volatile uint32_t doepint9; /* ALT_USB_DEV_DOEPINT9 */
volatile uint32_t _pad_0x42c_0x42f; /* *UNDEFINED* */
volatile uint32_t doeptsiz9; /* ALT_USB_DEV_DOEPTSIZ9 */
volatile uint32_t doepdma9; /* ALT_USB_DEV_DOEPDMA9 */
volatile uint32_t _pad_0x438_0x43b; /* *UNDEFINED* */
volatile uint32_t doepdmab9; /* ALT_USB_DEV_DOEPDMAB9 */
volatile uint32_t doepctl10; /* ALT_USB_DEV_DOEPCTL10 */
volatile uint32_t _pad_0x444_0x447; /* *UNDEFINED* */
volatile uint32_t doepint10; /* ALT_USB_DEV_DOEPINT10 */
volatile uint32_t _pad_0x44c_0x44f; /* *UNDEFINED* */
volatile uint32_t doeptsiz10; /* ALT_USB_DEV_DOEPTSIZ10 */
volatile uint32_t doepdma10; /* ALT_USB_DEV_DOEPDMA10 */
volatile uint32_t _pad_0x458_0x45b; /* *UNDEFINED* */
volatile uint32_t doepdmab10; /* ALT_USB_DEV_DOEPDMAB10 */
volatile uint32_t doepctl11; /* ALT_USB_DEV_DOEPCTL11 */
volatile uint32_t _pad_0x464_0x467; /* *UNDEFINED* */
volatile uint32_t doepint11; /* ALT_USB_DEV_DOEPINT11 */
volatile uint32_t _pad_0x46c_0x46f; /* *UNDEFINED* */
volatile uint32_t doeptsiz11; /* ALT_USB_DEV_DOEPTSIZ11 */
volatile uint32_t doepdma11; /* ALT_USB_DEV_DOEPDMA11 */
volatile uint32_t _pad_0x478_0x47b; /* *UNDEFINED* */
volatile uint32_t doepdmab11; /* ALT_USB_DEV_DOEPDMAB11 */
volatile uint32_t doepctl12; /* ALT_USB_DEV_DOEPCTL12 */
volatile uint32_t _pad_0x484_0x487; /* *UNDEFINED* */
volatile uint32_t doepint12; /* ALT_USB_DEV_DOEPINT12 */
volatile uint32_t _pad_0x48c_0x48f; /* *UNDEFINED* */
volatile uint32_t doeptsiz12; /* ALT_USB_DEV_DOEPTSIZ12 */
volatile uint32_t doepdma12; /* ALT_USB_DEV_DOEPDMA12 */
volatile uint32_t _pad_0x498_0x49b; /* *UNDEFINED* */
volatile uint32_t doepdmab12; /* ALT_USB_DEV_DOEPDMAB12 */
volatile uint32_t doepctl13; /* ALT_USB_DEV_DOEPCTL13 */
volatile uint32_t _pad_0x4a4_0x4a7; /* *UNDEFINED* */
volatile uint32_t doepint13; /* ALT_USB_DEV_DOEPINT13 */
volatile uint32_t _pad_0x4ac_0x4af; /* *UNDEFINED* */
volatile uint32_t doeptsiz13; /* ALT_USB_DEV_DOEPTSIZ13 */
volatile uint32_t doepdma13; /* ALT_USB_DEV_DOEPDMA13 */
volatile uint32_t _pad_0x4b8_0x4bb; /* *UNDEFINED* */
volatile uint32_t doepdmab13; /* ALT_USB_DEV_DOEPDMAB13 */
volatile uint32_t doepctl14; /* ALT_USB_DEV_DOEPCTL14 */
volatile uint32_t _pad_0x4c4_0x4c7; /* *UNDEFINED* */
volatile uint32_t doepint14; /* ALT_USB_DEV_DOEPINT14 */
volatile uint32_t _pad_0x4cc_0x4cf; /* *UNDEFINED* */
volatile uint32_t doeptsiz14; /* ALT_USB_DEV_DOEPTSIZ14 */
volatile uint32_t doepdma14; /* ALT_USB_DEV_DOEPDMA14 */
volatile uint32_t _pad_0x4d8_0x4db; /* *UNDEFINED* */
volatile uint32_t doepdmab14; /* ALT_USB_DEV_DOEPDMAB14 */
volatile uint32_t doepctl15; /* ALT_USB_DEV_DOEPCTL15 */
volatile uint32_t _pad_0x4e4_0x4e7; /* *UNDEFINED* */
volatile uint32_t doepint15; /* ALT_USB_DEV_DOEPINT15 */
volatile uint32_t _pad_0x4ec_0x4ef; /* *UNDEFINED* */
volatile uint32_t doeptsiz15; /* ALT_USB_DEV_DOEPTSIZ15 */
volatile uint32_t doepdma15; /* ALT_USB_DEV_DOEPDMA15 */
volatile uint32_t _pad_0x4f8_0x4fb; /* *UNDEFINED* */
volatile uint32_t doepdmab15; /* ALT_USB_DEV_DOEPDMAB15 */
};
/* The typedef declaration for the raw register contents of register group ALT_USB_DEV. */
typedef volatile struct ALT_USB_DEV_raw_s ALT_USB_DEV_raw_t;
#endif /* __ASSEMBLY__ */
/*
* Component : ALT_USB_PWRCLK
*
*/
/*
* Register : pcgcctl
*
* Power and Clock Gating Control Register
*
* Register Layout
*
* Bits | Access | Reset | Description
* :-------|:-------|:------|:-------------------------------------
* [0] | RW | 0x0 | ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
* [2:1] | ??? | 0x0 | *UNDEFINED*
* [3] | RW | 0x0 | ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
* [5:4] | ??? | 0x0 | *UNDEFINED*
* [6] | R | 0x0 | ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
* [7] | R | 0x0 | ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
* [31:8] | ??? | 0x0 | *UNDEFINED*
*
*/
/*
* Field : stoppclk
*
* Stop Pclk (StopPclk)
*
* The application sets this bit to stop the PHY clock (phy_clk)
*
* when the USB is suspended, the session is not valid, or the
*
* device is disconnected. The application clears this bit when the
*
* USB is resumed or a new session starts.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :---------------------------------------|:------|:------------------
* ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD | 0x0 | Disable Stop Pclk
* ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END | 0x1 | Enable Stop Pclk
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
*
* Disable Stop Pclk
*/
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD 0x0
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK
*
* Enable Stop Pclk
*/
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB 0
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB 0
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH 1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK 0x00000001
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK 0xfffffffe
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET 0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET(value) (((value) << 0) & 0x00000001)
/*
* Field : rstpdwnmodule
*
* Reset Power-Down Modules (RstPdwnModule)
*
* This bit is valid only in Partial Power-Down mode. The
*
* application sets this bit when the power is turned off. The
*
* application clears this bit after the power is turned on and the
*
* PHY clock is up.Note: The R/W of all core registers are possible only when this
* bit is
*
* set to 1b0.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:--------------------
* ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON | 0x0 | Power is turned on
* ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF | 0x1 | Power is turned off
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
*
* Power is turned on
*/
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON 0x0
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE
*
* Power is turned off
*/
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB 3
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB 3
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH 1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK 0x00000008
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK 0xfffffff7
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET 0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET(value) (((value) << 3) & 0x00000008)
/*
* Field : physleep
*
* PHY In Sleep
*
* Indicates that the PHY is in Sleep State.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :----------------------------------------|:------|:----------------
* ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT | 0x0 | Phy non-sleep
* ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT | 0x1 | Phy sleep state
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
*
* Phy non-sleep
*/
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP
*
* Phy sleep state
*/
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB 6
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB 6
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH 1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK 0x00000040
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK 0xffffffbf
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET 0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET(value) (((value) << 6) & 0x00000040)
/*
* Field : l1suspended
*
* L1 Deep Sleep
*
* Indicates that the PHY is in deep sleep when in L1 state.
*
* Field Enumeration Values:
*
* Enum | Value | Description
* :-------------------------------------------|:------|:------------------
* ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT | 0x0 | Non Deep Sleep
* ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT | 0x1 | Deep Sleep active
*
* Field Access Macros:
*
*/
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
*
* Non Deep Sleep
*/
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT 0x0
/*
* Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED
*
* Deep Sleep active
*/
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT 0x1
/* The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB 7
/* The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB 7
/* The width in bits of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH 1
/* The mask used to set the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK 0x00000080
/* The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK 0xffffff7f
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET 0x0
/* Extracts the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED field value from a register. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value suitable for setting the register. */
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET(value) (((value) << 7) & 0x00000080)
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register ALT_USB_PWRCLK_PCGCCTL.
*/
struct ALT_USB_PWRCLK_PCGCCTL_s
{
uint32_t stoppclk : 1; /* ALT_USB_PWRCLK_PCGCCTL_STOPPCLK */
uint32_t : 2; /* *UNDEFINED* */
uint32_t rstpdwnmodule : 1; /* ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE */
uint32_t : 2; /* *UNDEFINED* */
const uint32_t physleep : 1; /* ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP */
const uint32_t l1suspended : 1; /* ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED */
uint32_t : 24; /* *UNDEFINED* */
};
/* The typedef declaration for register ALT_USB_PWRCLK_PCGCCTL. */
typedef volatile struct ALT_USB_PWRCLK_PCGCCTL_s ALT_USB_PWRCLK_PCGCCTL_t;
#endif /* __ASSEMBLY__ */
/* The reset value of the ALT_USB_PWRCLK_PCGCCTL register. */
#define ALT_USB_PWRCLK_PCGCCTL_RESET 0x00000000
/* The byte offset of the ALT_USB_PWRCLK_PCGCCTL register from the beginning of the component. */
#define ALT_USB_PWRCLK_PCGCCTL_OFST 0x0
/* The address of the ALT_USB_PWRCLK_PCGCCTL register. */
#define ALT_USB_PWRCLK_PCGCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST))
#ifndef __ASSEMBLY__
/*
* WARNING: The C register and register group struct declarations are provided for
* convenience and illustrative purposes. They should, however, be used with
* caution as the C language standard provides no guarantees about the alignment or
* atomicity of device memory accesses. The recommended practice for writing
* hardware drivers is to use the SoCAL access macros and alt_read_word() and
* alt_write_word() functions.
*
* The struct declaration for register group ALT_USB_PWRCLK.
*/
struct ALT_USB_PWRCLK_s
{
volatile ALT_USB_PWRCLK_PCGCCTL_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */
};
/* The typedef declaration for register group ALT_USB_PWRCLK. */
typedef volatile struct ALT_USB_PWRCLK_s ALT_USB_PWRCLK_t;
/* The struct declaration for the raw register contents of register group ALT_USB_PWRCLK. */
struct ALT_USB_PWRCLK_raw_s
{
volatile uint32_t pcgcctl; /* ALT_USB_PWRCLK_PCGCCTL */
};
/* The typedef declaration for the raw register contents of register group ALT_USB_PWRCLK. */
typedef volatile struct ALT_USB_PWRCLK_raw_s ALT_USB_PWRCLK_raw_t;
#endif /* __ASSEMBLY__ */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_SOCAL_USB_H__ */
| [
"leslie.cheng5@gmail.com"
] | leslie.cheng5@gmail.com |
f98d4370aeb9bed2b930cf4aa2180b1c888327bd | dcc66b4fa7cc1f6e3ce92bca934da24fc43edb98 | /sholland_oilDeposits.cpp | 60354b015ac211ca43b02e27896d5f7cd08c08aa | [] | no_license | spholland/UVa | 37dc8057b704786e3d0542a4f3fd99c2619fae30 | 728ecfd3ff6bbfa312ebd214980fb17b987c0e9c | refs/heads/master | 2020-04-05T23:41:03.230089 | 2015-05-02T06:22:10 | 2015-05-02T06:22:10 | 34,937,869 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 2,176 | cpp | // Steven Holland
//UVa #572 Oil Deposits
// To solve this problem I used a resursive flood-fill algorithm.
#include <iostream>
#include <fstream>
#include <algorithm>
#include <list>
using namespace std;
char graph[105][105];
list <int> location;
void floodFill() {
int column = location.front();
location.pop_front();
int row = location.front();
location.pop_front();
graph[row][column] = '*';
// Check diagonal top left
if (graph[row - 1][column - 1] == '@') {
location.push_front(row - 1);
location.push_front(column - 1);
}
// Check up
if (graph[row - 1][column] == '@') {
location.push_front(row - 1);
location.push_front(column);
}
// Check diagonal top right
if (graph[row - 1][column + 1] == '@') {
location.push_front(row - 1);
location.push_front(column + 1);
}
// Check right
if (graph[row][column + 1] == '@') {
location.push_front(row);
location.push_front(column + 1);
}
// Check diagonal bottom right
if (graph[row + 1][column + 1] == '@') {
location.push_front(row + 1);
location.push_front(column + 1);
}
// Check down
if (graph[row + 1][column] == '@') {
location.push_front(row + 1);
location.push_front(column);
}
//Check diagonal bottom left
if (graph[row + 1][column - 1] == '@') {
location.push_front(row + 1);
location.push_front(column - 1);
}
// Check left
if (graph[row][column - 1] == '@') {
location.push_front(row);
location.push_front(column - 1);
}
}
int main() {
freopen("in.txt", "r", stdin);
int m, n;
while (cin >> m >> n) {
if (m == 0) {
return 0;
}
// Initialize the graph
location.clear();
int i, j;
for (i = 0; i < 105; i++){
for (j = 0; j < 105; j++) {
graph[i][j] = '.';
}
}
// Get all the input for the graph
for (i = 1; i <= m; i++) {
for (j = 1; j <= n; j++) {
cin >> graph[i][j];
}
}
// Recursive step
int result = 0;
for (i = 1; i <= m; i++) {
for (j = 1; j <= n; j++) {
if (graph[i][j] == '@') {
result++;
location.push_front(i);
location.push_front(j);
while (location.size()) {
floodFill();
}
}
}
}
cout << result << endl;
}
return 0;
} | [
"sholland@linfield.edu"
] | sholland@linfield.edu |
b7b9656f0650d723e550ac5dd47915906be91c32 | fcdcac090c1f92526b484da3df47eb1e8e249bbc | /include/pangolin/handler.h | 6f71b9077a0338b9b70cb45bbc7ae7c035274f36 | [
"MIT"
] | permissive | faradazerage/Pangolin | 1165e3f839ad28cae69f39bed85b15d55b8ac78d | 840aca4b1689441d9b61525b50e41277cd792757 | refs/heads/master | 2021-01-17T21:37:46.161533 | 2013-08-09T20:37:16 | 2013-08-09T20:37:16 | 9,749,828 | 1 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 4,755 | h | /* This file is part of the Pangolin Project.
* http://github.com/stevenlovegrove/Pangolin
*
* Copyright (c) 2013 Steven Lovegrove
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef PANGOLIN_HANDLER_H
#define PANGOLIN_HANDLER_H
#include "opengl_render_state.h"
namespace pangolin
{
// Forward declarations
struct View;
// Supported Key modifiers for GlobalKeyPressCallback.
// e.g. PANGO_CTRL + 'r', PANGO_SPECIAL + GLUT_KEY_RIGHT, etc.
const int PANGO_SPECIAL = 128;
const int PANGO_CTRL = -96;
const int PANGO_OPTN = 132;
// Special Keys (same as GLUT_ defines)
const int PANGO_KEY_F1 = 1;
const int PANGO_KEY_F2 = 2;
const int PANGO_KEY_F3 = 3;
const int PANGO_KEY_F4 = 4;
const int PANGO_KEY_F5 = 5;
const int PANGO_KEY_F6 = 6;
const int PANGO_KEY_F7 = 7;
const int PANGO_KEY_F8 = 8;
const int PANGO_KEY_F9 = 9;
const int PANGO_KEY_F10 = 10;
const int PANGO_KEY_F11 = 11;
const int PANGO_KEY_F12 = 12;
const int PANGO_KEY_LEFT = 100;
const int PANGO_KEY_UP = 101;
const int PANGO_KEY_RIGHT = 102;
const int PANGO_KEY_DOWN = 103;
const int PANGO_KEY_PAGE_UP = 104;
const int PANGO_KEY_PAGE_DOWN = 105;
const int PANGO_KEY_HOME = 106;
const int PANGO_KEY_END = 107;
const int PANGO_KEY_INSERT = 108;
enum MouseButton
{
MouseButtonLeft = 1,
MouseButtonMiddle = 2,
MouseButtonRight = 4,
MouseWheelUp = 8,
MouseWheelDown = 16
};
enum KeyModifier
{
KeyModifierShift = 1<<16,
KeyModifierCtrl = 1<<17,
KeyModifierAlt = 1<<18,
KeyModifierCmd = 1<<19
};
enum InputSpecial
{
InputSpecialScroll,
InputSpecialZoom,
InputSpecialRotate,
InputSpecialTablet
};
//! @brief Input Handler base class with virtual methods which recurse
//! into sub-displays
struct Handler
{
virtual ~Handler() {}
virtual void Keyboard(View&, unsigned char key, int x, int y, bool pressed);
virtual void Mouse(View&, MouseButton button, int x, int y, bool pressed, int button_state);
virtual void MouseMotion(View&, int x, int y, int button_state);
virtual void PassiveMouseMotion(View&, int x, int y, int button_state);
virtual void Special(View&, InputSpecial inType, float x, float y, float p1, float p2, float p3, float p4, int button_state);
};
struct HandlerScroll : Handler
{
void Mouse(View&, MouseButton button, int x, int y, bool pressed, int button_state);
void Special(View&, InputSpecial inType, float x, float y, float p1, float p2, float p3, float p4, int button_state);
};
struct Handler3D : Handler
{
Handler3D(OpenGlRenderState& cam_state, AxisDirection enforce_up=AxisNone, float trans_scale=0.01f, float zoom_fraction=1.0f/50.0f);
virtual void GetPosNormal(View& view, int x, int y, GLdouble p[3], GLdouble Pw[3], GLdouble Pc[3], GLdouble n[3], GLdouble default_z = 1.0);
void Keyboard(View&, unsigned char key, int x, int y, bool pressed);
void Mouse(View&, MouseButton button, int x, int y, bool pressed, int button_state);
void MouseMotion(View&, int x, int y, int button_state);
void Special(View&, InputSpecial inType, float x, float y, float p1, float p2, float p3, float p4, int button_state);
protected:
OpenGlRenderState* cam_state;
const static int hwin = 8;
AxisDirection enforce_up;
float tf; // translation factor
float zf; // zoom fraction
CameraSpec cameraspec;
GLfloat last_z;
GLint last_pos[2];
GLdouble rot_center[3];
GLdouble p[3];
GLdouble Pw[3];
GLdouble Pc[3];
GLdouble n[3];
};
static Handler StaticHandler;
static HandlerScroll StaticHandlerScroll;
}
#endif // PANGOLIN_HANDLER_H
| [
"stevenlovegrove@gmail.com"
] | stevenlovegrove@gmail.com |
5fa4fe7567a9df2f7122b19567e15373917b5ee2 | cbb0bd995f5ecb64f93a30d5f1dcd106e3241214 | /Processor/OfflineMachine.hpp | e18c47b5f103834bda9cbb6506d545b5c334a8bd | [
"BSD-3-Clause",
"BSD-2-Clause"
] | permissive | data61/MP-SPDZ | 324010a4caaa403f64d769a276d58931e0ed274e | 5c26feece05e13387fc9bd2ef3f09b2735d6ea4b | refs/heads/master | 2023-08-10T01:25:33.653174 | 2023-08-09T02:13:34 | 2023-08-09T02:13:34 | 152,511,277 | 724 | 277 | NOASSERTION | 2023-07-21T04:43:18 | 2018-10-11T01:16:16 | C++ | UTF-8 | C++ | false | false | 5,925 | hpp | /*
* DishonestMajorityOfflineMachine.hpp
*
*/
#ifndef PROCESSOR_OFFLINEMACHINE_HPP_
#define PROCESSOR_OFFLINEMACHINE_HPP_
#include "OfflineMachine.h"
#include "Protocols/mac_key.hpp"
#include "Tools/Buffer.h"
template<class W>
template<class V>
OfflineMachine<W>::OfflineMachine(int argc, const char** argv,
ez::ezOptionParser& opt, OnlineOptions& online_opts, V,
int nplayers) :
W(argc, argv, opt, online_opts, V(), nplayers), playerNames(
W::playerNames), P(*this->new_player("machine"))
{
machine.load_schedule(online_opts.progname, false);
Program program(playerNames.num_players());
program.parse(machine.bc_filenames[0]);
if (program.usage_unknown())
{
cerr << "Preprocessing might be insufficient "
<< "due to unknown requirements" << endl;
}
usage = program.get_offline_data_used();
n_threads = machine.nthreads;
}
template<class W>
OfflineMachine<W>::~OfflineMachine()
{
delete &P;
}
template<class W>
template<class T, class U>
int OfflineMachine<W>::run()
{
T::clear::init_default(this->online_opts.prime_length());
Machine<T, U>::init_binary_domains(this->online_opts.security_parameter,
this->lg2);
auto binary_mac_key = read_generate_write_mac_key<
typename T::bit_type::part_type>(P);
typename T::bit_type::LivePrep bit_prep(usage);
GC::ShareThread<typename T::bit_type> thread(bit_prep, P, binary_mac_key);
// setup before generation to fix prime
T::LivePrep::basic_setup(P);
T::MAC_Check::setup(P);
T::bit_type::MAC_Check::setup(P);
U::MAC_Check::setup(P);
generate<T>();
generate<typename T::bit_type::part_type>();
generate<U>();
thread.MC->Check(P);
T::MAC_Check::teardown();
T::bit_type::MAC_Check::teardown();
U::MAC_Check::teardown();
return 0;
}
template<class W>
int OfflineMachine<W>::buffered_total(size_t required, size_t batch)
{
return DIV_CEIL(required, batch) * batch + (n_threads - 1) * batch;
}
template<class W>
template<class T>
void OfflineMachine<W>::generate()
{
T::clear::next::template init<typename T::clear>(false);
T::clear::template write_setup<T>(P.num_players());
auto mac_key = read_generate_write_mac_key<T>(P);
DataPositions generated;
generated.set_num_players(P.num_players());
typename T::MAC_Check output(mac_key);
typename T::LivePrep preprocessing(0, generated);
SubProcessor<T> processor(output, preprocessing, P);
auto& domain_usage = usage.files[T::clear::field_type()];
for (unsigned i = 0; i < domain_usage.size(); i++)
{
auto my_usage = domain_usage[i];
Dtype dtype = Dtype(i);
string filename = Sub_Data_Files<T>::get_filename(playerNames, dtype,
0);
if (my_usage > 0)
{
ofstream out(filename, iostream::out | iostream::binary);
file_signature<T>().output(out);
if (i == DATA_DABIT)
{
for (long long j = 0;
j < buffered_total(my_usage, BUFFER_SIZE); j++)
{
T a;
typename T::bit_type b;
preprocessing.get_dabit(a, b);
dabit<T>(a, b).output(out, false);
}
}
else if (not (i == DATA_RANDOM or i == DATA_OPEN))
{
vector<T> tuple(DataPositions::tuple_size[i]);
for (long long j = 0;
j < buffered_total(my_usage, BUFFER_SIZE); j++)
{
preprocessing.get(dtype, tuple.data());
for (auto& x : tuple)
x.output(out, false);
}
}
}
else
remove(filename.c_str());
}
long additional_inputs = Sub_Data_Files<T>::additional_inputs(usage);
for (int i = 0; i < P.num_players(); i++)
{
auto n_inputs = usage.inputs[i][T::clear::field_type()]
+ additional_inputs;
string filename = Sub_Data_Files<T>::get_input_filename(playerNames, i, 0);
if (n_inputs > 0)
{
ofstream out(filename, iostream::out | iostream::binary);
file_signature<T>().output(out);
InputTuple<T> tuple;
for (long long j = 0;
j < buffered_total(n_inputs, BUFFER_SIZE); j++)
{
preprocessing.get_input(tuple.share, tuple.value, i);
tuple.share.output(out, false);
if (i == P.my_num())
tuple.value.output(out, false);
}
}
else
remove(filename.c_str());
}
if (T::clear::field_type() == DATA_INT)
{
int max_n_bits = 0;
for (auto& x : usage.edabits)
max_n_bits = max(max_n_bits, x.first.second);
for (int n_bits = 1; n_bits < max(100, max_n_bits); n_bits++)
{
int batch = edabitvec<T>::MAX_SIZE;
int total = usage.edabits[{false, n_bits}] +
usage.edabits[{true, n_bits}];
string filename = Sub_Data_Files<T>::get_edabit_filename(playerNames,
n_bits, 0);
if (total > 0)
{
ofstream out(filename, ios::binary);
file_signature<T>().output(out);
auto& opts = OnlineOptions::singleton;
opts.batch_size = DIV_CEIL(opts.batch_size, batch) * batch;
for (int i = 0; i < buffered_total(total, batch) / batch; i++)
preprocessing.get_edabitvec(true, n_bits).output(n_bits,
out);
}
else
remove(filename.c_str());
}
}
output.Check(P);
}
#endif /* PROCESSOR_OFFLINEMACHINE_HPP_ */
| [
"mks.keller@gmail.com"
] | mks.keller@gmail.com |
b18a1bc49ef57e09174973b7757f1cbde4632f4b | 5e1afd243b9972138591b43149dc9dbb3a017879 | /Content/C++/math/NewtonRootFinding.h | b53f1df30439c86e55c88791c407f7f2fe8123d0 | [] | no_license | pidddgy/Resources | 47bfd6fe019a3c59ac8468bb04c114b4e4679e07 | 624b2fcde28abe035cf7b54087c839bdabc623f8 | refs/heads/master | 2022-12-28T15:31:41.243316 | 2020-09-30T05:38:07 | 2020-09-30T05:38:07 | 300,311,262 | 0 | 0 | null | 2020-10-01T14:35:43 | 2020-10-01T14:35:42 | null | UTF-8 | C++ | false | false | 388 | h | #pragma once
#include <bits/stdc++.h>
using namespace std;
// Find the root of a function using Newton's Method, given an initial guess x0
// Time Complexity: iters * cost to compute f(x)
template <class T, class F> T newton(T x0, F f, F df, int iters) {
T cur = x0, next = x0;
for (int it = 0; it < iters; it++) { cur = next; next = cur - f(cur) / df(cur); }
return next;
}
| [
"wesley.a.leung@gmail.com"
] | wesley.a.leung@gmail.com |
974e09696d49aa1c1e53648e4c87b28473e78c09 | c7b984a6ae69a7fb06401561ce8f1bee0e7d5dea | /basetest/testuv/src/plugin.cpp | 4a9292074ee16ae175d1902012b33bc1bb69c68f | [
"MIT"
] | permissive | yaoyansi/mymagicbox | 1efa5b616c0d5c8344b97acc0b84394ca7348c88 | 1e4cb0d44273a06807a49938702b4f00d271c2a9 | refs/heads/master | 2021-01-01T19:34:27.730487 | 2014-12-03T13:54:28 | 2014-12-03T13:54:28 | 22,371,287 | 2 | 1 | null | null | null | null | UTF-8 | C++ | false | false | 1,025 | cpp | #include <maya/MFnPlugin.h>
#include <maya/MStatus.h>
#include "testuvCmd.h"
#include "peltOverlapCmd.h"
// These methods load and unload the plugin, registerNode registers the
// new node type with maya
//
MStatus initializePlugin( MObject obj )
{
printf("\nplugin %s is loaded -----------------------\n", TestUVCmd::cCmdName().asChar() );
MFnPlugin plugin( obj, "yaoyu", "1.0.0", "Any" );
CHECK_MSTATUS(plugin.registerCommand(
TestUVCmd::cCmdName(),
TestUVCmd::creator)
);
CHECK_MSTATUS(plugin.registerCommand(peltOverlap::cCmdName(),
peltOverlap::creator,
peltOverlap::newSyntax)
);
return MS::kSuccess;
}
MStatus uninitializePlugin( MObject obj )
{
MFnPlugin plugin( obj );
CHECK_MSTATUS(plugin.deregisterCommand(peltOverlap::cCmdName()));
CHECK_MSTATUS(plugin.deregisterCommand(TestUVCmd::cCmdName()));
return MS::kSuccess;
}
| [
"yaoyansi@aliyun.com"
] | yaoyansi@aliyun.com |
c147d6976329a33427b1254cb0e532d85ba6cbea | 0456635b3ea96105c8f6bc0635829dce4ab0b3fd | /Locking_Branching_Operator/brop/solution1/syn/systemc/sha256_transform_1.cpp | b2cb6388618dc8ea0e812afd5a73ee79555b214f | [] | no_license | ambuj2911/Impact_of_RTL_Locking | 3fe3d5d88b194970b0e763d75d00fe17e1187251 | cf4d13ce3ee3498f23accb9360f73464b1a6e036 | refs/heads/master | 2023-04-07T08:16:08.263848 | 2021-04-11T16:56:08 | 2021-04-11T16:56:08 | 356,877,699 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 380,116 | cpp | #include "sha256_transform.h"
#include "AESL_pkg.h"
using namespace std;
namespace ap_rtl {
const sc_logic sha256_transform::ap_const_logic_1 = sc_dt::Log_1;
const sc_logic sha256_transform::ap_const_logic_0 = sc_dt::Log_0;
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage0 = "1";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage1 = "10";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage2 = "100";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage3 = "1000";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage4 = "10000";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage5 = "100000";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage6 = "1000000";
const sc_lv<8> sha256_transform::ap_ST_fsm_pp0_stage7 = "10000000";
const bool sha256_transform::ap_const_boolean_1 = true;
const sc_lv<32> sha256_transform::ap_const_lv32_0 = "00000000000000000000000000000000";
const bool sha256_transform::ap_const_boolean_0 = false;
const sc_lv<32> sha256_transform::ap_const_lv32_7 = "111";
const sc_lv<32> sha256_transform::ap_const_lv32_3 = "11";
const sc_lv<32> sha256_transform::ap_const_lv32_5 = "101";
const sc_lv<32> sha256_transform::ap_const_lv32_4 = "100";
const sc_lv<32> sha256_transform::ap_const_lv32_6 = "110";
const sc_lv<32> sha256_transform::ap_const_lv32_2 = "10";
const sc_lv<32> sha256_transform::ap_const_lv32_1 = "1";
const sc_lv<64> sha256_transform::ap_const_lv64_0 = "0000000000000000000000000000000000000000000000000000000000000000";
const sc_lv<64> sha256_transform::ap_const_lv64_1 = "1";
const sc_lv<64> sha256_transform::ap_const_lv64_2 = "10";
const sc_lv<64> sha256_transform::ap_const_lv64_3 = "11";
const sc_lv<64> sha256_transform::ap_const_lv64_4 = "100";
const sc_lv<64> sha256_transform::ap_const_lv64_5 = "101";
const sc_lv<64> sha256_transform::ap_const_lv64_6 = "110";
const sc_lv<64> sha256_transform::ap_const_lv64_7 = "111";
const sc_lv<64> sha256_transform::ap_const_lv64_8 = "1000";
const sc_lv<64> sha256_transform::ap_const_lv64_9 = "1001";
const sc_lv<64> sha256_transform::ap_const_lv64_A = "1010";
const sc_lv<64> sha256_transform::ap_const_lv64_B = "1011";
const sc_lv<64> sha256_transform::ap_const_lv64_C = "1100";
const sc_lv<64> sha256_transform::ap_const_lv64_D = "1101";
const sc_lv<64> sha256_transform::ap_const_lv64_E = "1110";
const sc_lv<64> sha256_transform::ap_const_lv64_F = "1111";
const sc_lv<32> sha256_transform::ap_const_lv32_428A2F98 = "1000010100010100010111110011000";
const sc_lv<32> sha256_transform::ap_const_lv32_71374491 = "1110001001101110100010010010001";
const sc_lv<32> sha256_transform::ap_const_lv32_B5C0FBCF = "10110101110000001111101111001111";
const sc_lv<32> sha256_transform::ap_const_lv32_E9B5DBA5 = "11101001101101011101101110100101";
const sc_lv<32> sha256_transform::ap_const_lv32_3956C25B = "111001010101101100001001011011";
const sc_lv<32> sha256_transform::ap_const_lv32_59F111F1 = "1011001111100010001000111110001";
const sc_lv<32> sha256_transform::ap_const_lv32_923F82A4 = "10010010001111111000001010100100";
const sc_lv<32> sha256_transform::ap_const_lv32_AB1C5ED5 = "10101011000111000101111011010101";
const sc_lv<32> sha256_transform::ap_const_lv32_D807AA98 = "11011000000001111010101010011000";
const sc_lv<32> sha256_transform::ap_const_lv32_12835B01 = "10010100000110101101100000001";
const sc_lv<32> sha256_transform::ap_const_lv32_243185BE = "100100001100011000010110111110";
const sc_lv<32> sha256_transform::ap_const_lv32_550C7DC3 = "1010101000011000111110111000011";
const sc_lv<32> sha256_transform::ap_const_lv32_72BE5D74 = "1110010101111100101110101110100";
const sc_lv<32> sha256_transform::ap_const_lv32_80DEB1FE = "10000000110111101011000111111110";
const sc_lv<32> sha256_transform::ap_const_lv32_9BDC06A7 = "10011011110111000000011010100111";
const sc_lv<32> sha256_transform::ap_const_lv32_C19BF174 = "11000001100110111111000101110100";
const sc_lv<32> sha256_transform::ap_const_lv32_E49B69C1 = "11100100100110110110100111000001";
const sc_lv<32> sha256_transform::ap_const_lv32_EFBE4786 = "11101111101111100100011110000110";
const sc_lv<32> sha256_transform::ap_const_lv32_FC19DC6 = "1111110000011001110111000110";
const sc_lv<32> sha256_transform::ap_const_lv32_240CA1CC = "100100000011001010000111001100";
const sc_lv<32> sha256_transform::ap_const_lv32_2DE92C6F = "101101111010010010110001101111";
const sc_lv<32> sha256_transform::ap_const_lv32_4A7484AA = "1001010011101001000010010101010";
const sc_lv<32> sha256_transform::ap_const_lv32_5CB0A9DC = "1011100101100001010100111011100";
const sc_lv<32> sha256_transform::ap_const_lv32_76F988DA = "1110110111110011000100011011010";
const sc_lv<32> sha256_transform::ap_const_lv32_983E5152 = "10011000001111100101000101010010";
const sc_lv<32> sha256_transform::ap_const_lv32_A831C66D = "10101000001100011100011001101101";
const sc_lv<32> sha256_transform::ap_const_lv32_B00327C8 = "10110000000000110010011111001000";
const sc_lv<32> sha256_transform::ap_const_lv32_BF597FC7 = "10111111010110010111111111000111";
const sc_lv<32> sha256_transform::ap_const_lv32_C6E00BF3 = "11000110111000000000101111110011";
const sc_lv<32> sha256_transform::ap_const_lv32_D5A79147 = "11010101101001111001000101000111";
const sc_lv<32> sha256_transform::ap_const_lv32_6CA6351 = "110110010100110001101010001";
const sc_lv<32> sha256_transform::ap_const_lv32_14292967 = "10100001010010010100101100111";
const sc_lv<32> sha256_transform::ap_const_lv32_27B70A85 = "100111101101110000101010000101";
const sc_lv<32> sha256_transform::ap_const_lv32_2E1B2138 = "101110000110110010000100111000";
const sc_lv<32> sha256_transform::ap_const_lv32_4D2C6DFC = "1001101001011000110110111111100";
const sc_lv<32> sha256_transform::ap_const_lv32_53380D13 = "1010011001110000000110100010011";
const sc_lv<32> sha256_transform::ap_const_lv32_650A7354 = "1100101000010100111001101010100";
const sc_lv<32> sha256_transform::ap_const_lv32_766A0ABB = "1110110011010100000101010111011";
const sc_lv<32> sha256_transform::ap_const_lv32_81C2C92E = "10000001110000101100100100101110";
const sc_lv<32> sha256_transform::ap_const_lv32_92722C85 = "10010010011100100010110010000101";
const sc_lv<32> sha256_transform::ap_const_lv32_A2BFE8A1 = "10100010101111111110100010100001";
const sc_lv<32> sha256_transform::ap_const_lv32_A81A664B = "10101000000110100110011001001011";
const sc_lv<32> sha256_transform::ap_const_lv32_C24B8B70 = "11000010010010111000101101110000";
const sc_lv<32> sha256_transform::ap_const_lv32_C76C51A3 = "11000111011011000101000110100011";
const sc_lv<32> sha256_transform::ap_const_lv32_D192E819 = "11010001100100101110100000011001";
const sc_lv<32> sha256_transform::ap_const_lv32_D6990624 = "11010110100110010000011000100100";
const sc_lv<32> sha256_transform::ap_const_lv32_F40E3585 = "11110100000011100011010110000101";
const sc_lv<32> sha256_transform::ap_const_lv32_106AA070 = "10000011010101010000001110000";
const sc_lv<32> sha256_transform::ap_const_lv32_C67178F2 = "11000110011100010111100011110010";
const sc_lv<32> sha256_transform::ap_const_lv32_19A4C116 = "11001101001001100000100010110";
const sc_lv<32> sha256_transform::ap_const_lv32_1E376C08 = "11110001101110110110000001000";
const sc_lv<32> sha256_transform::ap_const_lv32_2748774C = "100111010010000111011101001100";
const sc_lv<32> sha256_transform::ap_const_lv32_34B0BCB5 = "110100101100001011110010110101";
const sc_lv<32> sha256_transform::ap_const_lv32_391C0CB3 = "111001000111000000110010110011";
const sc_lv<32> sha256_transform::ap_const_lv32_4ED8AA4A = "1001110110110001010101001001010";
const sc_lv<32> sha256_transform::ap_const_lv32_5B9CCA4F = "1011011100111001100101001001111";
const sc_lv<32> sha256_transform::ap_const_lv32_682E6FF3 = "1101000001011100110111111110011";
const sc_lv<32> sha256_transform::ap_const_lv32_748F82EE = "1110100100011111000001011101110";
const sc_lv<32> sha256_transform::ap_const_lv32_78A5636F = "1111000101001010110001101101111";
const sc_lv<32> sha256_transform::ap_const_lv32_84C87814 = "10000100110010000111100000010100";
const sc_lv<32> sha256_transform::ap_const_lv32_8CC70208 = "10001100110001110000001000001000";
const sc_lv<32> sha256_transform::ap_const_lv32_90BEFFFA = "10010000101111101111111111111010";
const sc_lv<32> sha256_transform::ap_const_lv32_A4506CEB = "10100100010100000110110011101011";
const sc_lv<32> sha256_transform::ap_const_lv32_BEF9A3F7 = "10111110111110011010001111110111";
sha256_transform::sha256_transform(sc_module_name name) : sc_module(name), mVcdFile(0) {
grp_MAJ_fu_864 = new MAJ("grp_MAJ_fu_864");
grp_MAJ_fu_864->ap_ready(grp_MAJ_fu_864_ap_ready);
grp_MAJ_fu_864->x(grp_MAJ_fu_864_x);
grp_MAJ_fu_864->y(grp_MAJ_fu_864_y);
grp_MAJ_fu_864->z(grp_MAJ_fu_864_z);
grp_MAJ_fu_864->rtl_key_r(grp_MAJ_fu_864_rtl_key_r);
grp_MAJ_fu_864->ap_return(grp_MAJ_fu_864_ap_return);
grp_MAJ_fu_876 = new MAJ("grp_MAJ_fu_876");
grp_MAJ_fu_876->ap_ready(grp_MAJ_fu_876_ap_ready);
grp_MAJ_fu_876->x(grp_MAJ_fu_876_x);
grp_MAJ_fu_876->y(grp_MAJ_fu_876_y);
grp_MAJ_fu_876->z(grp_MAJ_fu_876_z);
grp_MAJ_fu_876->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_876->ap_return(grp_MAJ_fu_876_ap_return);
grp_MAJ_fu_885 = new MAJ("grp_MAJ_fu_885");
grp_MAJ_fu_885->ap_ready(grp_MAJ_fu_885_ap_ready);
grp_MAJ_fu_885->x(grp_MAJ_fu_885_x);
grp_MAJ_fu_885->y(grp_MAJ_fu_885_y);
grp_MAJ_fu_885->z(grp_MAJ_fu_885_z);
grp_MAJ_fu_885->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_885->ap_return(grp_MAJ_fu_885_ap_return);
grp_MAJ_fu_894 = new MAJ("grp_MAJ_fu_894");
grp_MAJ_fu_894->ap_ready(grp_MAJ_fu_894_ap_ready);
grp_MAJ_fu_894->x(grp_MAJ_fu_894_x);
grp_MAJ_fu_894->y(grp_MAJ_fu_894_y);
grp_MAJ_fu_894->z(grp_MAJ_fu_894_z);
grp_MAJ_fu_894->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_894->ap_return(grp_MAJ_fu_894_ap_return);
grp_MAJ_fu_903 = new MAJ("grp_MAJ_fu_903");
grp_MAJ_fu_903->ap_ready(grp_MAJ_fu_903_ap_ready);
grp_MAJ_fu_903->x(grp_MAJ_fu_903_x);
grp_MAJ_fu_903->y(grp_MAJ_fu_903_y);
grp_MAJ_fu_903->z(grp_MAJ_fu_903_z);
grp_MAJ_fu_903->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_903->ap_return(grp_MAJ_fu_903_ap_return);
grp_MAJ_fu_912 = new MAJ("grp_MAJ_fu_912");
grp_MAJ_fu_912->ap_ready(grp_MAJ_fu_912_ap_ready);
grp_MAJ_fu_912->x(grp_MAJ_fu_912_x);
grp_MAJ_fu_912->y(grp_MAJ_fu_912_y);
grp_MAJ_fu_912->z(grp_MAJ_fu_912_z);
grp_MAJ_fu_912->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_912->ap_return(grp_MAJ_fu_912_ap_return);
grp_MAJ_fu_921 = new MAJ("grp_MAJ_fu_921");
grp_MAJ_fu_921->ap_ready(grp_MAJ_fu_921_ap_ready);
grp_MAJ_fu_921->x(grp_MAJ_fu_921_x);
grp_MAJ_fu_921->y(grp_MAJ_fu_921_y);
grp_MAJ_fu_921->z(grp_MAJ_fu_921_z);
grp_MAJ_fu_921->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_921->ap_return(grp_MAJ_fu_921_ap_return);
grp_MAJ_fu_930 = new MAJ("grp_MAJ_fu_930");
grp_MAJ_fu_930->ap_ready(grp_MAJ_fu_930_ap_ready);
grp_MAJ_fu_930->x(grp_MAJ_fu_930_x);
grp_MAJ_fu_930->y(grp_MAJ_fu_930_y);
grp_MAJ_fu_930->z(grp_MAJ_fu_930_z);
grp_MAJ_fu_930->rtl_key_r(ap_port_reg_rtl_key_r);
grp_MAJ_fu_930->ap_return(grp_MAJ_fu_930_ap_return);
grp_EP1_fu_939 = new EP1("grp_EP1_fu_939");
grp_EP1_fu_939->ap_ready(grp_EP1_fu_939_ap_ready);
grp_EP1_fu_939->x(grp_EP1_fu_939_x);
grp_EP1_fu_939->rtl_key_r(grp_EP1_fu_939_rtl_key_r);
grp_EP1_fu_939->ap_return(grp_EP1_fu_939_ap_return);
grp_EP1_fu_947 = new EP1("grp_EP1_fu_947");
grp_EP1_fu_947->ap_ready(grp_EP1_fu_947_ap_ready);
grp_EP1_fu_947->x(grp_EP1_fu_947_x);
grp_EP1_fu_947->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_947->ap_return(grp_EP1_fu_947_ap_return);
grp_EP1_fu_954 = new EP1("grp_EP1_fu_954");
grp_EP1_fu_954->ap_ready(grp_EP1_fu_954_ap_ready);
grp_EP1_fu_954->x(grp_EP1_fu_954_x);
grp_EP1_fu_954->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_954->ap_return(grp_EP1_fu_954_ap_return);
grp_EP1_fu_961 = new EP1("grp_EP1_fu_961");
grp_EP1_fu_961->ap_ready(grp_EP1_fu_961_ap_ready);
grp_EP1_fu_961->x(grp_EP1_fu_961_x);
grp_EP1_fu_961->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_961->ap_return(grp_EP1_fu_961_ap_return);
grp_EP1_fu_968 = new EP1("grp_EP1_fu_968");
grp_EP1_fu_968->ap_ready(grp_EP1_fu_968_ap_ready);
grp_EP1_fu_968->x(grp_EP1_fu_968_x);
grp_EP1_fu_968->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_968->ap_return(grp_EP1_fu_968_ap_return);
grp_EP1_fu_975 = new EP1("grp_EP1_fu_975");
grp_EP1_fu_975->ap_ready(grp_EP1_fu_975_ap_ready);
grp_EP1_fu_975->x(grp_EP1_fu_975_x);
grp_EP1_fu_975->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_975->ap_return(grp_EP1_fu_975_ap_return);
grp_EP1_fu_982 = new EP1("grp_EP1_fu_982");
grp_EP1_fu_982->ap_ready(grp_EP1_fu_982_ap_ready);
grp_EP1_fu_982->x(grp_EP1_fu_982_x);
grp_EP1_fu_982->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_982->ap_return(grp_EP1_fu_982_ap_return);
grp_EP1_fu_989 = new EP1("grp_EP1_fu_989");
grp_EP1_fu_989->ap_ready(grp_EP1_fu_989_ap_ready);
grp_EP1_fu_989->x(grp_EP1_fu_989_x);
grp_EP1_fu_989->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP1_fu_989->ap_return(grp_EP1_fu_989_ap_return);
grp_EP0_fu_996 = new EP0("grp_EP0_fu_996");
grp_EP0_fu_996->ap_ready(grp_EP0_fu_996_ap_ready);
grp_EP0_fu_996->x(grp_EP0_fu_996_x);
grp_EP0_fu_996->rtl_key_r(grp_EP0_fu_996_rtl_key_r);
grp_EP0_fu_996->ap_return(grp_EP0_fu_996_ap_return);
grp_EP0_fu_1004 = new EP0("grp_EP0_fu_1004");
grp_EP0_fu_1004->ap_ready(grp_EP0_fu_1004_ap_ready);
grp_EP0_fu_1004->x(grp_EP0_fu_1004_x);
grp_EP0_fu_1004->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1004->ap_return(grp_EP0_fu_1004_ap_return);
grp_EP0_fu_1011 = new EP0("grp_EP0_fu_1011");
grp_EP0_fu_1011->ap_ready(grp_EP0_fu_1011_ap_ready);
grp_EP0_fu_1011->x(grp_EP0_fu_1011_x);
grp_EP0_fu_1011->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1011->ap_return(grp_EP0_fu_1011_ap_return);
grp_EP0_fu_1018 = new EP0("grp_EP0_fu_1018");
grp_EP0_fu_1018->ap_ready(grp_EP0_fu_1018_ap_ready);
grp_EP0_fu_1018->x(grp_EP0_fu_1018_x);
grp_EP0_fu_1018->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1018->ap_return(grp_EP0_fu_1018_ap_return);
grp_EP0_fu_1025 = new EP0("grp_EP0_fu_1025");
grp_EP0_fu_1025->ap_ready(grp_EP0_fu_1025_ap_ready);
grp_EP0_fu_1025->x(grp_EP0_fu_1025_x);
grp_EP0_fu_1025->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1025->ap_return(grp_EP0_fu_1025_ap_return);
grp_EP0_fu_1032 = new EP0("grp_EP0_fu_1032");
grp_EP0_fu_1032->ap_ready(grp_EP0_fu_1032_ap_ready);
grp_EP0_fu_1032->x(grp_EP0_fu_1032_x);
grp_EP0_fu_1032->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1032->ap_return(grp_EP0_fu_1032_ap_return);
grp_EP0_fu_1039 = new EP0("grp_EP0_fu_1039");
grp_EP0_fu_1039->ap_ready(grp_EP0_fu_1039_ap_ready);
grp_EP0_fu_1039->x(grp_EP0_fu_1039_x);
grp_EP0_fu_1039->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1039->ap_return(grp_EP0_fu_1039_ap_return);
grp_EP0_fu_1046 = new EP0("grp_EP0_fu_1046");
grp_EP0_fu_1046->ap_ready(grp_EP0_fu_1046_ap_ready);
grp_EP0_fu_1046->x(grp_EP0_fu_1046_x);
grp_EP0_fu_1046->rtl_key_r(ap_port_reg_rtl_key_r);
grp_EP0_fu_1046->ap_return(grp_EP0_fu_1046_ap_return);
grp_SIG1_fu_1053 = new SIG1("grp_SIG1_fu_1053");
grp_SIG1_fu_1053->ap_ready(grp_SIG1_fu_1053_ap_ready);
grp_SIG1_fu_1053->x(grp_SIG1_fu_1053_x);
grp_SIG1_fu_1053->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1053->ap_return(grp_SIG1_fu_1053_ap_return);
grp_SIG1_fu_1060 = new SIG1("grp_SIG1_fu_1060");
grp_SIG1_fu_1060->ap_ready(grp_SIG1_fu_1060_ap_ready);
grp_SIG1_fu_1060->x(grp_SIG1_fu_1060_x);
grp_SIG1_fu_1060->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1060->ap_return(grp_SIG1_fu_1060_ap_return);
grp_SIG1_fu_1067 = new SIG1("grp_SIG1_fu_1067");
grp_SIG1_fu_1067->ap_ready(grp_SIG1_fu_1067_ap_ready);
grp_SIG1_fu_1067->x(grp_SIG1_fu_1067_x);
grp_SIG1_fu_1067->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1067->ap_return(grp_SIG1_fu_1067_ap_return);
grp_SIG1_fu_1074 = new SIG1("grp_SIG1_fu_1074");
grp_SIG1_fu_1074->ap_ready(grp_SIG1_fu_1074_ap_ready);
grp_SIG1_fu_1074->x(grp_SIG1_fu_1074_x);
grp_SIG1_fu_1074->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1074->ap_return(grp_SIG1_fu_1074_ap_return);
grp_SIG1_fu_1081 = new SIG1("grp_SIG1_fu_1081");
grp_SIG1_fu_1081->ap_ready(grp_SIG1_fu_1081_ap_ready);
grp_SIG1_fu_1081->x(grp_SIG1_fu_1081_x);
grp_SIG1_fu_1081->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1081->ap_return(grp_SIG1_fu_1081_ap_return);
grp_SIG1_fu_1088 = new SIG1("grp_SIG1_fu_1088");
grp_SIG1_fu_1088->ap_ready(grp_SIG1_fu_1088_ap_ready);
grp_SIG1_fu_1088->x(grp_SIG1_fu_1088_x);
grp_SIG1_fu_1088->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG1_fu_1088->ap_return(grp_SIG1_fu_1088_ap_return);
grp_SIG0_fu_1095 = new SIG0("grp_SIG0_fu_1095");
grp_SIG0_fu_1095->ap_ready(grp_SIG0_fu_1095_ap_ready);
grp_SIG0_fu_1095->x(grp_SIG0_fu_1095_x);
grp_SIG0_fu_1095->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1095->ap_return(grp_SIG0_fu_1095_ap_return);
grp_SIG0_fu_1102 = new SIG0("grp_SIG0_fu_1102");
grp_SIG0_fu_1102->ap_ready(grp_SIG0_fu_1102_ap_ready);
grp_SIG0_fu_1102->x(grp_SIG0_fu_1102_x);
grp_SIG0_fu_1102->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1102->ap_return(grp_SIG0_fu_1102_ap_return);
grp_SIG0_fu_1109 = new SIG0("grp_SIG0_fu_1109");
grp_SIG0_fu_1109->ap_ready(grp_SIG0_fu_1109_ap_ready);
grp_SIG0_fu_1109->x(grp_SIG0_fu_1109_x);
grp_SIG0_fu_1109->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1109->ap_return(grp_SIG0_fu_1109_ap_return);
grp_SIG0_fu_1116 = new SIG0("grp_SIG0_fu_1116");
grp_SIG0_fu_1116->ap_ready(grp_SIG0_fu_1116_ap_ready);
grp_SIG0_fu_1116->x(grp_SIG0_fu_1116_x);
grp_SIG0_fu_1116->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1116->ap_return(grp_SIG0_fu_1116_ap_return);
grp_SIG0_fu_1123 = new SIG0("grp_SIG0_fu_1123");
grp_SIG0_fu_1123->ap_ready(grp_SIG0_fu_1123_ap_ready);
grp_SIG0_fu_1123->x(grp_SIG0_fu_1123_x);
grp_SIG0_fu_1123->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1123->ap_return(grp_SIG0_fu_1123_ap_return);
grp_SIG0_fu_1130 = new SIG0("grp_SIG0_fu_1130");
grp_SIG0_fu_1130->ap_ready(grp_SIG0_fu_1130_ap_ready);
grp_SIG0_fu_1130->x(grp_SIG0_fu_1130_x);
grp_SIG0_fu_1130->rtl_key_r(ap_port_reg_rtl_key_r);
grp_SIG0_fu_1130->ap_return(grp_SIG0_fu_1130_ap_return);
grp_CH_fu_1137 = new CH("grp_CH_fu_1137");
grp_CH_fu_1137->ap_ready(grp_CH_fu_1137_ap_ready);
grp_CH_fu_1137->x(grp_CH_fu_1137_x);
grp_CH_fu_1137->y(grp_CH_fu_1137_y);
grp_CH_fu_1137->z(grp_CH_fu_1137_z);
grp_CH_fu_1137->rtl_key_r(grp_CH_fu_1137_rtl_key_r);
grp_CH_fu_1137->ap_return(grp_CH_fu_1137_ap_return);
grp_CH_fu_1149 = new CH("grp_CH_fu_1149");
grp_CH_fu_1149->ap_ready(grp_CH_fu_1149_ap_ready);
grp_CH_fu_1149->x(grp_CH_fu_1149_x);
grp_CH_fu_1149->y(grp_CH_fu_1149_y);
grp_CH_fu_1149->z(grp_CH_fu_1149_z);
grp_CH_fu_1149->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1149->ap_return(grp_CH_fu_1149_ap_return);
grp_CH_fu_1158 = new CH("grp_CH_fu_1158");
grp_CH_fu_1158->ap_ready(grp_CH_fu_1158_ap_ready);
grp_CH_fu_1158->x(grp_CH_fu_1158_x);
grp_CH_fu_1158->y(grp_CH_fu_1158_y);
grp_CH_fu_1158->z(grp_CH_fu_1158_z);
grp_CH_fu_1158->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1158->ap_return(grp_CH_fu_1158_ap_return);
grp_CH_fu_1167 = new CH("grp_CH_fu_1167");
grp_CH_fu_1167->ap_ready(grp_CH_fu_1167_ap_ready);
grp_CH_fu_1167->x(grp_CH_fu_1167_x);
grp_CH_fu_1167->y(grp_CH_fu_1167_y);
grp_CH_fu_1167->z(grp_CH_fu_1167_z);
grp_CH_fu_1167->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1167->ap_return(grp_CH_fu_1167_ap_return);
grp_CH_fu_1176 = new CH("grp_CH_fu_1176");
grp_CH_fu_1176->ap_ready(grp_CH_fu_1176_ap_ready);
grp_CH_fu_1176->x(grp_CH_fu_1176_x);
grp_CH_fu_1176->y(grp_CH_fu_1176_y);
grp_CH_fu_1176->z(grp_CH_fu_1176_z);
grp_CH_fu_1176->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1176->ap_return(grp_CH_fu_1176_ap_return);
grp_CH_fu_1185 = new CH("grp_CH_fu_1185");
grp_CH_fu_1185->ap_ready(grp_CH_fu_1185_ap_ready);
grp_CH_fu_1185->x(grp_CH_fu_1185_x);
grp_CH_fu_1185->y(grp_CH_fu_1185_y);
grp_CH_fu_1185->z(grp_CH_fu_1185_z);
grp_CH_fu_1185->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1185->ap_return(grp_CH_fu_1185_ap_return);
grp_CH_fu_1194 = new CH("grp_CH_fu_1194");
grp_CH_fu_1194->ap_ready(grp_CH_fu_1194_ap_ready);
grp_CH_fu_1194->x(grp_CH_fu_1194_x);
grp_CH_fu_1194->y(grp_CH_fu_1194_y);
grp_CH_fu_1194->z(grp_CH_fu_1194_z);
grp_CH_fu_1194->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1194->ap_return(grp_CH_fu_1194_ap_return);
grp_CH_fu_1203 = new CH("grp_CH_fu_1203");
grp_CH_fu_1203->ap_ready(grp_CH_fu_1203_ap_ready);
grp_CH_fu_1203->x(grp_CH_fu_1203_x);
grp_CH_fu_1203->y(grp_CH_fu_1203_y);
grp_CH_fu_1203->z(grp_CH_fu_1203_z);
grp_CH_fu_1203->rtl_key_r(ap_port_reg_rtl_key_r);
grp_CH_fu_1203->ap_return(grp_CH_fu_1203_ap_return);
SC_METHOD(thread_ap_clk_no_reset_);
dont_initialize();
sensitive << ( ap_clk.pos() );
SC_METHOD(thread_add_ln259_100_fu_2485_p2);
sensitive << ( m_33_reg_5839 );
sensitive << ( m_42_reg_6053 );
SC_METHOD(thread_add_ln259_102_fu_2558_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_33_reg_5900 );
SC_METHOD(thread_add_ln259_103_fu_2539_p2);
sensitive << ( m_34_reg_5871 );
sensitive << ( m_43_reg_6060 );
SC_METHOD(thread_add_ln259_105_fu_2569_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_34_reg_5947 );
SC_METHOD(thread_add_ln259_106_fu_2543_p2);
sensitive << ( m_35_reg_5878 );
sensitive << ( m_44_reg_6105 );
SC_METHOD(thread_add_ln259_108_fu_2615_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_35_reg_5952 );
SC_METHOD(thread_add_ln259_109_fu_2580_p2);
sensitive << ( m_36_reg_5923 );
sensitive << ( m_45_reg_6112 );
SC_METHOD(thread_add_ln259_10_fu_1731_p2);
sensitive << ( m_3_reg_4961 );
sensitive << ( m_12_reg_5332 );
SC_METHOD(thread_add_ln259_111_fu_2626_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_36_reg_5986 );
SC_METHOD(thread_add_ln259_112_fu_2584_p2);
sensitive << ( m_37_reg_5930 );
sensitive << ( m_46_reg_6144 );
SC_METHOD(thread_add_ln259_114_fu_2655_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_37_reg_5991 );
SC_METHOD(thread_add_ln259_115_fu_2637_p2);
sensitive << ( m_38_reg_5962 );
sensitive << ( m_47_reg_6151 );
SC_METHOD(thread_add_ln259_117_fu_2666_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_38_reg_6038 );
SC_METHOD(thread_add_ln259_118_fu_2641_p2);
sensitive << ( m_39_reg_5969 );
sensitive << ( m_48_reg_6196 );
SC_METHOD(thread_add_ln259_120_fu_2713_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_39_reg_6043 );
SC_METHOD(thread_add_ln259_121_fu_2677_p2);
sensitive << ( m_40_reg_6014 );
sensitive << ( m_49_reg_6202 );
SC_METHOD(thread_add_ln259_123_fu_2724_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_40_reg_6077 );
SC_METHOD(thread_add_ln259_124_fu_2681_p2);
sensitive << ( m_41_reg_6021 );
sensitive << ( m_50_reg_6228 );
SC_METHOD(thread_add_ln259_126_fu_2753_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_41_reg_6082 );
SC_METHOD(thread_add_ln259_127_fu_2735_p2);
sensitive << ( m_42_reg_6053 );
sensitive << ( m_51_reg_6234 );
SC_METHOD(thread_add_ln259_129_fu_2764_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_42_reg_6129 );
SC_METHOD(thread_add_ln259_12_fu_1802_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_4_reg_5092 );
SC_METHOD(thread_add_ln259_130_fu_2739_p2);
sensitive << ( m_43_reg_6060 );
sensitive << ( m_52_reg_6268 );
SC_METHOD(thread_add_ln259_132_fu_2811_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_43_reg_6134 );
SC_METHOD(thread_add_ln259_133_fu_2775_p2);
sensitive << ( m_44_reg_6105 );
sensitive << ( m_53_reg_6274 );
SC_METHOD(thread_add_ln259_135_fu_2822_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_44_reg_6168 );
SC_METHOD(thread_add_ln259_136_fu_2779_p2);
sensitive << ( m_45_reg_6112 );
sensitive << ( m_54_reg_6295 );
SC_METHOD(thread_add_ln259_13_fu_1770_p2);
sensitive << ( m_4_reg_5035 );
sensitive << ( m_13_reg_5339 );
SC_METHOD(thread_add_ln259_15_fu_1814_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_5_reg_5154 );
SC_METHOD(thread_add_ln259_16_fu_1774_p2);
sensitive << ( m_5_reg_5041 );
sensitive << ( m_14_reg_5401 );
SC_METHOD(thread_add_ln259_18_fu_1845_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_6_reg_5159 );
SC_METHOD(thread_add_ln259_19_fu_1826_p2);
sensitive << ( m_6_reg_5102 );
sensitive << ( m_15_reg_5408 );
SC_METHOD(thread_add_ln259_1_fu_1668_p2);
sensitive << ( m_0_reg_4884 );
sensitive << ( m_9_reg_5188 );
SC_METHOD(thread_add_ln259_21_fu_1857_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_7_reg_5235 );
SC_METHOD(thread_add_ln259_22_fu_1830_p2);
sensitive << ( m_7_reg_5108 );
sensitive << ( m_16_reg_5453 );
SC_METHOD(thread_add_ln259_24_fu_1904_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_8_reg_5240 );
SC_METHOD(thread_add_ln259_25_fu_1869_p2);
sensitive << ( m_8_reg_5182 );
sensitive << ( m_17_reg_5460 );
SC_METHOD(thread_add_ln259_27_fu_1916_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_9_reg_5304 );
SC_METHOD(thread_add_ln259_28_fu_1873_p2);
sensitive << ( m_9_reg_5188 );
sensitive << ( m_18_reg_5507 );
SC_METHOD(thread_add_ln259_30_fu_1946_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_s_reg_5309 );
SC_METHOD(thread_add_ln259_31_fu_1928_p2);
sensitive << ( m_10_reg_5250 );
sensitive << ( m_19_reg_5514 );
SC_METHOD(thread_add_ln259_33_fu_1958_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_10_reg_5386 );
SC_METHOD(thread_add_ln259_34_fu_1932_p2);
sensitive << ( m_11_reg_5257 );
sensitive << ( m_20_reg_5559 );
SC_METHOD(thread_add_ln259_36_fu_2006_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_11_reg_5391 );
SC_METHOD(thread_add_ln259_37_fu_1970_p2);
sensitive << ( m_12_reg_5332 );
sensitive << ( m_21_reg_5566 );
SC_METHOD(thread_add_ln259_39_fu_2018_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_12_reg_5425 );
SC_METHOD(thread_add_ln259_3_fu_1715_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_1_reg_5007 );
SC_METHOD(thread_add_ln259_40_fu_1974_p2);
sensitive << ( m_13_reg_5339 );
sensitive << ( m_22_reg_5598 );
SC_METHOD(thread_add_ln259_42_fu_2048_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_13_reg_5430 );
SC_METHOD(thread_add_ln259_43_fu_2030_p2);
sensitive << ( m_14_reg_5401 );
sensitive << ( m_23_reg_5605 );
SC_METHOD(thread_add_ln259_45_fu_2060_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_14_reg_5477 );
SC_METHOD(thread_add_ln259_46_fu_2034_p2);
sensitive << ( m_15_reg_5408 );
sensitive << ( m_24_reg_5650 );
SC_METHOD(thread_add_ln259_48_fu_2108_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_15_reg_5482 );
SC_METHOD(thread_add_ln259_49_fu_2072_p2);
sensitive << ( m_16_reg_5453 );
sensitive << ( m_25_reg_5657 );
SC_METHOD(thread_add_ln259_4_fu_1672_p2);
sensitive << ( m_1_reg_4889 );
sensitive << ( m_10_reg_5250 );
SC_METHOD(thread_add_ln259_51_fu_2120_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_16_reg_5531 );
SC_METHOD(thread_add_ln259_52_fu_2076_p2);
sensitive << ( m_17_reg_5460 );
sensitive << ( m_26_reg_5689 );
SC_METHOD(thread_add_ln259_54_fu_2151_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_17_reg_5536 );
SC_METHOD(thread_add_ln259_55_fu_2132_p2);
sensitive << ( m_18_reg_5507 );
sensitive << ( m_27_reg_5696 );
SC_METHOD(thread_add_ln259_57_fu_2163_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_18_reg_5583 );
SC_METHOD(thread_add_ln259_58_fu_2136_p2);
sensitive << ( m_19_reg_5514 );
sensitive << ( m_28_reg_5741 );
SC_METHOD(thread_add_ln259_60_fu_2210_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_19_reg_5588 );
SC_METHOD(thread_add_ln259_61_fu_2175_p2);
sensitive << ( m_20_reg_5559 );
sensitive << ( m_29_reg_5748 );
SC_METHOD(thread_add_ln259_63_fu_2222_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_20_reg_5622 );
SC_METHOD(thread_add_ln259_64_fu_2179_p2);
sensitive << ( m_21_reg_5566 );
sensitive << ( m_30_reg_5780 );
SC_METHOD(thread_add_ln259_66_fu_2253_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_21_reg_5627 );
SC_METHOD(thread_add_ln259_67_fu_2234_p2);
sensitive << ( m_22_reg_5598 );
sensitive << ( m_31_reg_5787 );
SC_METHOD(thread_add_ln259_69_fu_2265_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_22_reg_5674 );
SC_METHOD(thread_add_ln259_6_fu_1746_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_2_reg_5012 );
SC_METHOD(thread_add_ln259_70_fu_2238_p2);
sensitive << ( m_23_reg_5605 );
sensitive << ( m_32_reg_5832 );
SC_METHOD(thread_add_ln259_72_fu_2312_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_23_reg_5679 );
SC_METHOD(thread_add_ln259_73_fu_2277_p2);
sensitive << ( m_24_reg_5650 );
sensitive << ( m_33_reg_5839 );
SC_METHOD(thread_add_ln259_75_fu_2324_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_24_reg_5713 );
SC_METHOD(thread_add_ln259_76_fu_2281_p2);
sensitive << ( m_25_reg_5657 );
sensitive << ( m_34_reg_5871 );
SC_METHOD(thread_add_ln259_78_fu_2355_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_25_reg_5718 );
SC_METHOD(thread_add_ln259_79_fu_2336_p2);
sensitive << ( m_26_reg_5689 );
sensitive << ( m_35_reg_5878 );
SC_METHOD(thread_add_ln259_7_fu_1727_p2);
sensitive << ( m_2_reg_4955 );
sensitive << ( m_11_reg_5257 );
SC_METHOD(thread_add_ln259_81_fu_2367_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_26_reg_5765 );
SC_METHOD(thread_add_ln259_82_fu_2340_p2);
sensitive << ( m_27_reg_5696 );
sensitive << ( m_36_reg_5923 );
SC_METHOD(thread_add_ln259_84_fu_2414_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_27_reg_5770 );
SC_METHOD(thread_add_ln259_85_fu_2379_p2);
sensitive << ( m_28_reg_5741 );
sensitive << ( m_37_reg_5930 );
SC_METHOD(thread_add_ln259_87_fu_2426_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_28_reg_5804 );
SC_METHOD(thread_add_ln259_88_fu_2383_p2);
sensitive << ( m_29_reg_5748 );
sensitive << ( m_38_reg_5962 );
SC_METHOD(thread_add_ln259_90_fu_2457_p2);
sensitive << ( reg_1244 );
sensitive << ( tmp_1_29_reg_5809 );
SC_METHOD(thread_add_ln259_91_fu_2438_p2);
sensitive << ( m_30_reg_5780 );
sensitive << ( m_39_reg_5969 );
SC_METHOD(thread_add_ln259_93_fu_2469_p2);
sensitive << ( reg_1248 );
sensitive << ( tmp_1_30_reg_5856 );
SC_METHOD(thread_add_ln259_94_fu_2442_p2);
sensitive << ( m_31_reg_5787 );
sensitive << ( m_40_reg_6014 );
SC_METHOD(thread_add_ln259_96_fu_2516_p2);
sensitive << ( reg_1264 );
sensitive << ( tmp_1_31_reg_5861 );
SC_METHOD(thread_add_ln259_97_fu_2481_p2);
sensitive << ( m_32_reg_5832 );
sensitive << ( m_41_reg_6021 );
SC_METHOD(thread_add_ln259_99_fu_2528_p2);
sensitive << ( reg_1268 );
sensitive << ( tmp_1_32_reg_5895 );
SC_METHOD(thread_add_ln259_9_fu_1758_p2);
sensitive << ( reg_1228 );
sensitive << ( tmp_1_3_reg_5087 );
SC_METHOD(thread_add_ln259_fu_1703_p2);
sensitive << ( reg_1224 );
sensitive << ( tmp_1_reg_4935 );
SC_METHOD(thread_add_ln274_100_fu_3238_p2);
sensitive << ( reg_1308 );
SC_METHOD(thread_add_ln274_101_fu_3228_p2);
sensitive << ( m_25_reg_5657_pp0_iter5_reg );
sensitive << ( grp_EP1_fu_982_ap_return );
SC_METHOD(thread_add_ln274_102_fu_3233_p2);
sensitive << ( add_ln280_21_reg_6562 );
sensitive << ( add_ln274_101_fu_3228_p2 );
SC_METHOD(thread_add_ln274_103_fu_3244_p2);
sensitive << ( add_ln274_102_reg_6649 );
sensitive << ( add_ln274_100_fu_3238_p2 );
SC_METHOD(thread_add_ln274_104_fu_3276_p2);
sensitive << ( reg_1308 );
SC_METHOD(thread_add_ln274_105_fu_3266_p2);
sensitive << ( m_26_reg_5689_pp0_iter5_reg );
sensitive << ( grp_EP1_fu_982_ap_return );
SC_METHOD(thread_add_ln274_106_fu_3271_p2);
sensitive << ( add_ln280_22_reg_6585 );
sensitive << ( add_ln274_105_fu_3266_p2 );
SC_METHOD(thread_add_ln274_107_fu_3282_p2);
sensitive << ( add_ln274_106_reg_6672 );
sensitive << ( add_ln274_104_fu_3276_p2 );
SC_METHOD(thread_add_ln274_108_fu_3314_p2);
sensitive << ( reg_1308 );
SC_METHOD(thread_add_ln274_109_fu_3304_p2);
sensitive << ( m_27_reg_5696_pp0_iter6_reg );
sensitive << ( grp_EP1_fu_982_ap_return );
SC_METHOD(thread_add_ln274_10_fu_1544_p2);
sensitive << ( ctx_state_5_read_1_reg_4803 );
sensitive << ( add_ln274_9_fu_1539_p2 );
SC_METHOD(thread_add_ln274_110_fu_3309_p2);
sensitive << ( add_ln280_23_reg_6608 );
sensitive << ( add_ln274_109_fu_3304_p2 );
SC_METHOD(thread_add_ln274_111_fu_3320_p2);
sensitive << ( add_ln274_110_reg_6695 );
sensitive << ( add_ln274_108_fu_3314_p2 );
SC_METHOD(thread_add_ln274_112_fu_3353_p2);
sensitive << ( reg_1308 );
sensitive << ( add_ln280_24_reg_6631 );
SC_METHOD(thread_add_ln274_113_fu_3342_p2);
sensitive << ( m_28_reg_5741_pp0_iter6_reg );
SC_METHOD(thread_add_ln274_114_fu_3347_p2);
sensitive << ( grp_EP1_fu_982_ap_return );
sensitive << ( add_ln274_113_fu_3342_p2 );
SC_METHOD(thread_add_ln274_115_fu_3358_p2);
sensitive << ( add_ln274_114_reg_6718 );
sensitive << ( add_ln274_112_fu_3353_p2 );
SC_METHOD(thread_add_ln274_116_fu_3391_p2);
sensitive << ( reg_1320 );
sensitive << ( add_ln280_25_reg_6654 );
SC_METHOD(thread_add_ln274_117_fu_3380_p2);
sensitive << ( m_29_reg_5748_pp0_iter6_reg );
SC_METHOD(thread_add_ln274_118_fu_3385_p2);
sensitive << ( grp_EP1_fu_989_ap_return );
sensitive << ( add_ln274_117_fu_3380_p2 );
SC_METHOD(thread_add_ln274_119_fu_3396_p2);
sensitive << ( add_ln274_118_reg_6741 );
sensitive << ( add_ln274_116_fu_3391_p2 );
SC_METHOD(thread_add_ln274_11_fu_1581_p2);
sensitive << ( add_ln274_10_reg_5245 );
sensitive << ( add_ln274_8_fu_1575_p2 );
SC_METHOD(thread_add_ln274_120_fu_3429_p2);
sensitive << ( reg_1320 );
sensitive << ( add_ln280_26_reg_6677 );
SC_METHOD(thread_add_ln274_121_fu_3418_p2);
sensitive << ( m_30_reg_5780_pp0_iter7_reg );
SC_METHOD(thread_add_ln274_122_fu_3423_p2);
sensitive << ( grp_EP1_fu_989_ap_return );
sensitive << ( add_ln274_121_fu_3418_p2 );
SC_METHOD(thread_add_ln274_123_fu_3434_p2);
sensitive << ( add_ln274_122_reg_6764 );
sensitive << ( add_ln274_120_fu_3429_p2 );
SC_METHOD(thread_add_ln274_124_fu_3467_p2);
sensitive << ( reg_1320 );
sensitive << ( add_ln280_27_reg_6700 );
SC_METHOD(thread_add_ln274_125_fu_3456_p2);
sensitive << ( m_31_reg_5787_pp0_iter7_reg );
SC_METHOD(thread_add_ln274_126_fu_3461_p2);
sensitive << ( grp_EP1_fu_989_ap_return );
sensitive << ( add_ln274_125_fu_3456_p2 );
SC_METHOD(thread_add_ln274_127_fu_3472_p2);
sensitive << ( add_ln274_126_reg_6787 );
sensitive << ( add_ln274_124_fu_3467_p2 );
SC_METHOD(thread_add_ln274_128_fu_3505_p2);
sensitive << ( reg_1320 );
sensitive << ( add_ln280_28_reg_6723 );
SC_METHOD(thread_add_ln274_129_fu_3494_p2);
sensitive << ( m_32_reg_5832_pp0_iter7_reg );
SC_METHOD(thread_add_ln274_12_fu_1676_p2);
sensitive << ( reg_1212 );
sensitive << ( ctx_state_4_read_1_reg_4810 );
SC_METHOD(thread_add_ln274_130_fu_3499_p2);
sensitive << ( grp_EP1_fu_989_ap_return );
sensitive << ( add_ln274_129_fu_3494_p2 );
SC_METHOD(thread_add_ln274_131_fu_3510_p2);
sensitive << ( add_ln274_130_reg_6810 );
sensitive << ( add_ln274_128_fu_3505_p2 );
SC_METHOD(thread_add_ln274_132_fu_3543_p2);
sensitive << ( reg_1212 );
sensitive << ( add_ln280_29_reg_6746_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_133_fu_3532_p2);
sensitive << ( m_33_reg_5839_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_134_fu_3537_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_133_fu_3532_p2 );
SC_METHOD(thread_add_ln274_135_fu_3548_p2);
sensitive << ( add_ln274_134_reg_6833 );
sensitive << ( add_ln274_132_fu_3543_p2 );
SC_METHOD(thread_add_ln274_136_fu_3581_p2);
sensitive << ( reg_1212 );
sensitive << ( add_ln280_30_reg_6769_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_137_fu_3570_p2);
sensitive << ( m_34_reg_5871_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_138_fu_3575_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_137_fu_3570_p2 );
SC_METHOD(thread_add_ln274_139_fu_3586_p2);
sensitive << ( add_ln274_138_reg_6856 );
sensitive << ( add_ln274_136_fu_3581_p2 );
SC_METHOD(thread_add_ln274_13_fu_1629_p2);
sensitive << ( m_3_reg_4961 );
SC_METHOD(thread_add_ln274_140_fu_3619_p2);
sensitive << ( reg_1232 );
sensitive << ( add_ln280_31_reg_6792_pp0_iter9_reg );
SC_METHOD(thread_add_ln274_141_fu_3608_p2);
sensitive << ( m_35_reg_5878_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_142_fu_3613_p2);
sensitive << ( grp_EP1_fu_947_ap_return );
sensitive << ( add_ln274_141_fu_3608_p2 );
SC_METHOD(thread_add_ln274_143_fu_3624_p2);
sensitive << ( add_ln274_142_reg_6879 );
sensitive << ( add_ln274_140_fu_3619_p2 );
SC_METHOD(thread_add_ln274_144_fu_3657_p2);
sensitive << ( reg_1212 );
sensitive << ( add_ln280_32_reg_6815_pp0_iter9_reg );
SC_METHOD(thread_add_ln274_145_fu_3646_p2);
sensitive << ( m_36_reg_5923_pp0_iter8_reg );
SC_METHOD(thread_add_ln274_146_fu_3651_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_145_fu_3646_p2 );
SC_METHOD(thread_add_ln274_147_fu_3662_p2);
sensitive << ( add_ln274_146_reg_6902 );
sensitive << ( add_ln274_144_fu_3657_p2 );
SC_METHOD(thread_add_ln274_148_fu_3695_p2);
sensitive << ( reg_1232 );
sensitive << ( add_ln280_33_reg_6838 );
SC_METHOD(thread_add_ln274_149_fu_3684_p2);
sensitive << ( m_37_reg_5930_pp0_iter9_reg );
SC_METHOD(thread_add_ln274_14_fu_1634_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_13_fu_1629_p2 );
SC_METHOD(thread_add_ln274_150_fu_3689_p2);
sensitive << ( grp_EP1_fu_947_ap_return );
sensitive << ( add_ln274_149_fu_3684_p2 );
SC_METHOD(thread_add_ln274_151_fu_3700_p2);
sensitive << ( add_ln274_150_reg_6925 );
sensitive << ( add_ln274_148_fu_3695_p2 );
SC_METHOD(thread_add_ln274_152_fu_3732_p2);
sensitive << ( reg_1232 );
SC_METHOD(thread_add_ln274_153_fu_3722_p2);
sensitive << ( m_38_reg_5962_pp0_iter9_reg );
sensitive << ( grp_EP1_fu_947_ap_return );
SC_METHOD(thread_add_ln274_154_fu_3727_p2);
sensitive << ( add_ln280_34_reg_6861 );
sensitive << ( add_ln274_153_fu_3722_p2 );
SC_METHOD(thread_add_ln274_155_fu_3738_p2);
sensitive << ( add_ln274_154_reg_6948 );
sensitive << ( add_ln274_152_fu_3732_p2 );
SC_METHOD(thread_add_ln274_156_fu_3770_p2);
sensitive << ( reg_1252 );
SC_METHOD(thread_add_ln274_157_fu_3760_p2);
sensitive << ( m_39_reg_5969_pp0_iter9_reg );
sensitive << ( grp_EP1_fu_954_ap_return );
SC_METHOD(thread_add_ln274_158_fu_3765_p2);
sensitive << ( add_ln280_35_reg_6884 );
sensitive << ( add_ln274_157_fu_3760_p2 );
SC_METHOD(thread_add_ln274_159_fu_3776_p2);
sensitive << ( add_ln274_158_reg_6971 );
sensitive << ( add_ln274_156_fu_3770_p2 );
SC_METHOD(thread_add_ln274_15_fu_1681_p2);
sensitive << ( add_ln274_14_reg_5396 );
sensitive << ( add_ln274_12_fu_1676_p2 );
SC_METHOD(thread_add_ln274_160_fu_3808_p2);
sensitive << ( reg_1232 );
SC_METHOD(thread_add_ln274_161_fu_3798_p2);
sensitive << ( m_40_reg_6014_pp0_iter9_reg );
sensitive << ( grp_EP1_fu_947_ap_return );
SC_METHOD(thread_add_ln274_162_fu_3803_p2);
sensitive << ( add_ln280_36_reg_6907 );
sensitive << ( add_ln274_161_fu_3798_p2 );
SC_METHOD(thread_add_ln274_163_fu_3814_p2);
sensitive << ( add_ln274_162_reg_6994 );
sensitive << ( add_ln274_160_fu_3808_p2 );
SC_METHOD(thread_add_ln274_164_fu_3846_p2);
sensitive << ( reg_1252 );
SC_METHOD(thread_add_ln274_165_fu_3836_p2);
sensitive << ( m_41_reg_6021_pp0_iter9_reg );
sensitive << ( grp_EP1_fu_954_ap_return );
SC_METHOD(thread_add_ln274_166_fu_3841_p2);
sensitive << ( add_ln280_37_reg_6930 );
sensitive << ( add_ln274_165_fu_3836_p2 );
SC_METHOD(thread_add_ln274_167_fu_3852_p2);
sensitive << ( add_ln274_166_reg_7017 );
sensitive << ( add_ln274_164_fu_3846_p2 );
SC_METHOD(thread_add_ln274_168_fu_3885_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_38_reg_6953 );
SC_METHOD(thread_add_ln274_169_fu_3874_p2);
sensitive << ( m_42_reg_6053_pp0_iter9_reg );
SC_METHOD(thread_add_ln274_16_fu_1778_p2);
sensitive << ( add_ln280_reg_5017 );
sensitive << ( tmp_3_0_4_reg_5487 );
SC_METHOD(thread_add_ln274_170_fu_3879_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_169_fu_3874_p2 );
SC_METHOD(thread_add_ln274_171_fu_3890_p2);
sensitive << ( add_ln274_170_reg_7040 );
sensitive << ( add_ln274_168_fu_3885_p2 );
SC_METHOD(thread_add_ln274_172_fu_3923_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_39_reg_6976 );
SC_METHOD(thread_add_ln274_173_fu_3912_p2);
sensitive << ( m_43_reg_6060_pp0_iter10_reg );
SC_METHOD(thread_add_ln274_174_fu_3917_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_173_fu_3912_p2 );
SC_METHOD(thread_add_ln274_175_fu_3928_p2);
sensitive << ( add_ln274_174_reg_7063 );
sensitive << ( add_ln274_172_fu_3923_p2 );
SC_METHOD(thread_add_ln274_176_fu_3961_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_40_reg_6999 );
SC_METHOD(thread_add_ln274_177_fu_3950_p2);
sensitive << ( m_44_reg_6105_pp0_iter10_reg );
SC_METHOD(thread_add_ln274_178_fu_3955_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_177_fu_3950_p2 );
SC_METHOD(thread_add_ln274_179_fu_3966_p2);
sensitive << ( add_ln274_178_reg_7086 );
sensitive << ( add_ln274_176_fu_3961_p2 );
SC_METHOD(thread_add_ln274_17_fu_1735_p2);
sensitive << ( m_4_reg_5035 );
SC_METHOD(thread_add_ln274_180_fu_3999_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_41_reg_7022 );
SC_METHOD(thread_add_ln274_181_fu_3988_p2);
sensitive << ( m_45_reg_6112_pp0_iter10_reg );
SC_METHOD(thread_add_ln274_182_fu_3993_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_181_fu_3988_p2 );
SC_METHOD(thread_add_ln274_183_fu_4004_p2);
sensitive << ( add_ln274_182_reg_7109 );
sensitive << ( add_ln274_180_fu_3999_p2 );
SC_METHOD(thread_add_ln274_184_fu_4037_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_42_reg_7045 );
SC_METHOD(thread_add_ln274_185_fu_4026_p2);
sensitive << ( m_46_reg_6144_pp0_iter11_reg );
SC_METHOD(thread_add_ln274_186_fu_4031_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_185_fu_4026_p2 );
SC_METHOD(thread_add_ln274_187_fu_4042_p2);
sensitive << ( add_ln274_186_reg_7132 );
sensitive << ( add_ln274_184_fu_4037_p2 );
SC_METHOD(thread_add_ln274_188_fu_4090_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_43_reg_7068 );
SC_METHOD(thread_add_ln274_189_fu_4064_p2);
sensitive << ( m_47_reg_6151_pp0_iter11_reg );
SC_METHOD(thread_add_ln274_18_fu_1740_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_17_fu_1735_p2 );
SC_METHOD(thread_add_ln274_190_fu_4069_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_189_fu_4064_p2 );
SC_METHOD(thread_add_ln274_191_fu_4095_p2);
sensitive << ( add_ln274_190_reg_7155 );
sensitive << ( add_ln274_188_fu_4090_p2 );
SC_METHOD(thread_add_ln274_192_fu_4128_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_44_reg_7091 );
SC_METHOD(thread_add_ln274_193_fu_4117_p2);
sensitive << ( m_48_reg_6196_pp0_iter12_reg );
SC_METHOD(thread_add_ln274_194_fu_4122_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_193_fu_4117_p2 );
SC_METHOD(thread_add_ln274_195_fu_4133_p2);
sensitive << ( add_ln274_194_reg_7183 );
sensitive << ( add_ln274_192_fu_4128_p2 );
SC_METHOD(thread_add_ln274_196_fu_4166_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_45_reg_7114 );
SC_METHOD(thread_add_ln274_197_fu_4155_p2);
sensitive << ( m_49_reg_6202_pp0_iter12_reg );
SC_METHOD(thread_add_ln274_198_fu_4160_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_197_fu_4155_p2 );
SC_METHOD(thread_add_ln274_199_fu_4171_p2);
sensitive << ( add_ln274_198_reg_7206 );
sensitive << ( add_ln274_196_fu_4166_p2 );
SC_METHOD(thread_add_ln274_19_fu_1782_p2);
sensitive << ( add_ln274_18_reg_5492 );
sensitive << ( add_ln274_16_fu_1778_p2 );
SC_METHOD(thread_add_ln274_1_fu_1357_p2);
sensitive << ( m_0_fu_1332_p5 );
SC_METHOD(thread_add_ln274_200_fu_4204_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_46_reg_7137 );
SC_METHOD(thread_add_ln274_201_fu_4193_p2);
sensitive << ( m_50_reg_6228_pp0_iter12_reg );
SC_METHOD(thread_add_ln274_202_fu_4198_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_201_fu_4193_p2 );
SC_METHOD(thread_add_ln274_203_fu_4209_p2);
sensitive << ( add_ln274_202_reg_7229 );
sensitive << ( add_ln274_200_fu_4204_p2 );
SC_METHOD(thread_add_ln274_204_fu_4242_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_47_reg_7165 );
SC_METHOD(thread_add_ln274_205_fu_4231_p2);
sensitive << ( m_51_reg_6234_pp0_iter12_reg );
SC_METHOD(thread_add_ln274_206_fu_4236_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_205_fu_4231_p2 );
SC_METHOD(thread_add_ln274_207_fu_4247_p2);
sensitive << ( add_ln274_206_reg_7252 );
sensitive << ( add_ln274_204_fu_4242_p2 );
SC_METHOD(thread_add_ln274_208_fu_4280_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_48_reg_7188 );
SC_METHOD(thread_add_ln274_209_fu_4269_p2);
sensitive << ( m_52_reg_6268_pp0_iter12_reg );
SC_METHOD(thread_add_ln274_20_fu_1877_p2);
sensitive << ( reg_1232 );
sensitive << ( add_ln280_1_reg_5164 );
SC_METHOD(thread_add_ln274_210_fu_4274_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_209_fu_4269_p2 );
SC_METHOD(thread_add_ln274_211_fu_4285_p2);
sensitive << ( add_ln274_210_reg_7275 );
sensitive << ( add_ln274_208_fu_4280_p2 );
SC_METHOD(thread_add_ln274_212_fu_4318_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_49_reg_7211 );
SC_METHOD(thread_add_ln274_213_fu_4307_p2);
sensitive << ( m_53_reg_6274_pp0_iter13_reg );
SC_METHOD(thread_add_ln274_214_fu_4312_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_213_fu_4307_p2 );
SC_METHOD(thread_add_ln274_215_fu_4323_p2);
sensitive << ( add_ln274_214_reg_7298 );
sensitive << ( add_ln274_212_fu_4318_p2 );
SC_METHOD(thread_add_ln274_216_fu_4356_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_50_reg_7234 );
SC_METHOD(thread_add_ln274_217_fu_4345_p2);
sensitive << ( m_54_reg_6295_pp0_iter13_reg );
SC_METHOD(thread_add_ln274_218_fu_4350_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_217_fu_4345_p2 );
SC_METHOD(thread_add_ln274_219_fu_4361_p2);
sensitive << ( add_ln274_218_reg_7321 );
sensitive << ( add_ln274_216_fu_4356_p2 );
SC_METHOD(thread_add_ln274_21_fu_1834_p2);
sensitive << ( m_5_reg_5041 );
SC_METHOD(thread_add_ln274_220_fu_4394_p2);
sensitive << ( reg_1308 );
sensitive << ( add_ln280_51_reg_7257 );
SC_METHOD(thread_add_ln274_221_fu_4383_p2);
sensitive << ( m_55_reg_6301_pp0_iter13_reg );
SC_METHOD(thread_add_ln274_222_fu_4388_p2);
sensitive << ( grp_EP1_fu_982_ap_return );
sensitive << ( add_ln274_221_fu_4383_p2 );
SC_METHOD(thread_add_ln274_223_fu_4399_p2);
sensitive << ( add_ln274_222_reg_7344 );
sensitive << ( add_ln274_220_fu_4394_p2 );
SC_METHOD(thread_add_ln274_224_fu_4432_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_52_reg_7280 );
SC_METHOD(thread_add_ln274_225_fu_4421_p2);
sensitive << ( m_56_reg_6335_pp0_iter13_reg );
SC_METHOD(thread_add_ln274_226_fu_4426_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_225_fu_4421_p2 );
SC_METHOD(thread_add_ln274_227_fu_4437_p2);
sensitive << ( add_ln274_226_reg_7367 );
sensitive << ( add_ln274_224_fu_4432_p2 );
SC_METHOD(thread_add_ln274_228_fu_4470_p2);
sensitive << ( reg_1308 );
sensitive << ( add_ln280_53_reg_7303 );
SC_METHOD(thread_add_ln274_229_fu_4459_p2);
sensitive << ( m_57_reg_6341_pp0_iter13_reg );
SC_METHOD(thread_add_ln274_22_fu_1839_p2);
sensitive << ( grp_EP1_fu_947_ap_return );
sensitive << ( add_ln274_21_fu_1834_p2 );
SC_METHOD(thread_add_ln274_230_fu_4464_p2);
sensitive << ( grp_EP1_fu_982_ap_return );
sensitive << ( add_ln274_229_fu_4459_p2 );
SC_METHOD(thread_add_ln274_231_fu_4475_p2);
sensitive << ( add_ln274_230_reg_7390 );
sensitive << ( add_ln274_228_fu_4470_p2 );
SC_METHOD(thread_add_ln274_232_fu_4507_p2);
sensitive << ( reg_1308 );
SC_METHOD(thread_add_ln274_233_fu_4497_p2);
sensitive << ( m_58_reg_6361_pp0_iter13_reg );
sensitive << ( grp_EP1_fu_982_ap_return );
SC_METHOD(thread_add_ln274_234_fu_4502_p2);
sensitive << ( add_ln280_54_reg_7326 );
sensitive << ( add_ln274_233_fu_4497_p2 );
SC_METHOD(thread_add_ln274_235_fu_4513_p2);
sensitive << ( add_ln274_234_reg_7413 );
sensitive << ( add_ln274_232_fu_4507_p2 );
SC_METHOD(thread_add_ln274_236_fu_4545_p2);
sensitive << ( reg_1320 );
SC_METHOD(thread_add_ln274_237_fu_4535_p2);
sensitive << ( m_59_reg_6366_pp0_iter14_reg );
sensitive << ( grp_EP1_fu_989_ap_return );
SC_METHOD(thread_add_ln274_238_fu_4540_p2);
sensitive << ( add_ln280_55_reg_7349 );
sensitive << ( add_ln274_237_fu_4535_p2 );
SC_METHOD(thread_add_ln274_239_fu_4551_p2);
sensitive << ( add_ln274_238_reg_7436 );
sensitive << ( add_ln274_236_fu_4545_p2 );
SC_METHOD(thread_add_ln274_23_fu_1882_p2);
sensitive << ( add_ln274_22_reg_5593 );
sensitive << ( add_ln274_20_fu_1877_p2 );
SC_METHOD(thread_add_ln274_240_fu_4583_p2);
sensitive << ( reg_1308 );
SC_METHOD(thread_add_ln274_241_fu_4573_p2);
sensitive << ( m_60_reg_6399_pp0_iter14_reg );
sensitive << ( grp_EP1_fu_982_ap_return );
SC_METHOD(thread_add_ln274_242_fu_4578_p2);
sensitive << ( add_ln280_56_reg_7372 );
sensitive << ( add_ln274_241_fu_4573_p2 );
SC_METHOD(thread_add_ln274_243_fu_4589_p2);
sensitive << ( add_ln274_242_reg_7459 );
sensitive << ( add_ln274_240_fu_4583_p2 );
SC_METHOD(thread_add_ln274_244_fu_4621_p2);
sensitive << ( reg_1320 );
SC_METHOD(thread_add_ln274_245_fu_4611_p2);
sensitive << ( m_61_reg_6404_pp0_iter14_reg );
sensitive << ( grp_EP1_fu_989_ap_return );
SC_METHOD(thread_add_ln274_246_fu_4616_p2);
sensitive << ( add_ln280_57_reg_7395 );
sensitive << ( add_ln274_245_fu_4611_p2 );
SC_METHOD(thread_add_ln274_247_fu_4627_p2);
sensitive << ( add_ln274_246_reg_7482 );
sensitive << ( add_ln274_244_fu_4621_p2 );
SC_METHOD(thread_add_ln274_248_fu_4649_p2);
sensitive << ( grp_CH_fu_1203_ap_return );
SC_METHOD(thread_add_ln274_249_fu_4655_p2);
sensitive << ( add_ln280_58_reg_7418 );
sensitive << ( grp_EP1_fu_989_ap_return );
SC_METHOD(thread_add_ln274_24_fu_1978_p2);
sensitive << ( reg_1232 );
SC_METHOD(thread_add_ln274_250_fu_4660_p2);
sensitive << ( add_ln274_248_reg_7503 );
sensitive << ( add_ln274_249_reg_7508 );
SC_METHOD(thread_add_ln274_251_fu_4664_p2);
sensitive << ( add_ln274_254_reg_6437_pp0_iter15_reg );
sensitive << ( add_ln274_250_fu_4660_p2 );
SC_METHOD(thread_add_ln274_252_fu_2871_p2);
sensitive << ( reg_1264 );
sensitive << ( m_55_reg_6301 );
SC_METHOD(thread_add_ln274_253_fu_2876_p2);
sensitive << ( m_46_reg_6144 );
sensitive << ( tmp_1_45_reg_6173 );
SC_METHOD(thread_add_ln274_254_fu_2880_p2);
sensitive << ( add_ln274_253_fu_2876_p2 );
sensitive << ( add_ln274_252_fu_2871_p2 );
SC_METHOD(thread_add_ln274_255_fu_4729_p2);
sensitive << ( add_ln274_261_reg_7160_pp0_iter16_reg );
sensitive << ( add_ln274_258_fu_4725_p2 );
SC_METHOD(thread_add_ln274_256_fu_4686_p2);
sensitive << ( grp_CH_fu_1203_ap_return );
sensitive << ( add_ln280_59_reg_7441_pp0_iter16_reg );
SC_METHOD(thread_add_ln274_257_fu_4691_p2);
sensitive << ( tmp_47_reg_6409_pp0_iter15_reg );
sensitive << ( grp_EP1_fu_989_ap_return );
SC_METHOD(thread_add_ln274_258_fu_4725_p2);
sensitive << ( add_ln274_256_reg_7527 );
sensitive << ( add_ln274_257_reg_7532 );
SC_METHOD(thread_add_ln274_259_fu_4075_p2);
sensitive << ( m_47_reg_6151_pp0_iter11_reg );
sensitive << ( m_56_reg_6335_pp0_iter11_reg );
SC_METHOD(thread_add_ln274_25_fu_1936_p2);
sensitive << ( m_6_reg_5102_pp0_iter1_reg );
sensitive << ( grp_EP1_fu_947_ap_return );
SC_METHOD(thread_add_ln274_260_fu_4079_p2);
sensitive << ( tmp_1_46_reg_6218_pp0_iter11_reg );
SC_METHOD(thread_add_ln274_261_fu_4084_p2);
sensitive << ( add_ln274_260_fu_4079_p2 );
sensitive << ( add_ln274_259_fu_4075_p2 );
SC_METHOD(thread_add_ln274_26_fu_1941_p2);
sensitive << ( add_ln280_2_reg_5314 );
sensitive << ( add_ln274_25_fu_1936_p2 );
SC_METHOD(thread_add_ln274_27_fu_1984_p2);
sensitive << ( add_ln274_26_reg_5684 );
sensitive << ( add_ln274_24_fu_1978_p2 );
SC_METHOD(thread_add_ln274_28_fu_2080_p2);
sensitive << ( reg_1232 );
SC_METHOD(thread_add_ln274_29_fu_2038_p2);
sensitive << ( m_7_reg_5108_pp0_iter1_reg );
sensitive << ( grp_EP1_fu_947_ap_return );
SC_METHOD(thread_add_ln274_2_fu_1363_p2);
sensitive << ( tmp_48_reg_4879 );
sensitive << ( add_ln274_1_fu_1357_p2 );
SC_METHOD(thread_add_ln274_30_fu_2043_p2);
sensitive << ( add_ln280_3_reg_5435 );
sensitive << ( add_ln274_29_fu_2038_p2 );
SC_METHOD(thread_add_ln274_31_fu_2086_p2);
sensitive << ( add_ln274_30_reg_5775 );
sensitive << ( add_ln274_28_fu_2080_p2 );
SC_METHOD(thread_add_ln274_32_fu_2183_p2);
sensitive << ( reg_1232 );
sensitive << ( add_ln280_4_reg_5541 );
SC_METHOD(thread_add_ln274_33_fu_2140_p2);
sensitive << ( m_8_reg_5182_pp0_iter1_reg );
SC_METHOD(thread_add_ln274_34_fu_2145_p2);
sensitive << ( grp_EP1_fu_947_ap_return );
sensitive << ( add_ln274_33_fu_2140_p2 );
SC_METHOD(thread_add_ln274_35_fu_2188_p2);
sensitive << ( add_ln274_34_reg_5866 );
sensitive << ( add_ln274_32_fu_2183_p2 );
SC_METHOD(thread_add_ln274_36_fu_2285_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_5_reg_5632 );
SC_METHOD(thread_add_ln274_37_fu_2242_p2);
sensitive << ( m_9_reg_5188_pp0_iter1_reg );
SC_METHOD(thread_add_ln274_38_fu_2247_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_37_fu_2242_p2 );
SC_METHOD(thread_add_ln274_39_fu_2290_p2);
sensitive << ( add_ln274_38_reg_5957 );
sensitive << ( add_ln274_36_fu_2285_p2 );
SC_METHOD(thread_add_ln274_3_fu_1400_p2);
sensitive << ( add_ln274_2_reg_4940 );
sensitive << ( add_ln274_fu_1394_p2 );
SC_METHOD(thread_add_ln274_40_fu_2387_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_6_reg_5723 );
SC_METHOD(thread_add_ln274_41_fu_2344_p2);
sensitive << ( m_10_reg_5250_pp0_iter1_reg );
SC_METHOD(thread_add_ln274_42_fu_2349_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_41_fu_2344_p2 );
SC_METHOD(thread_add_ln274_43_fu_2392_p2);
sensitive << ( add_ln274_42_reg_6048 );
sensitive << ( add_ln274_40_fu_2387_p2 );
SC_METHOD(thread_add_ln274_44_fu_2489_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_7_reg_5814 );
SC_METHOD(thread_add_ln274_45_fu_2446_p2);
sensitive << ( m_11_reg_5257_pp0_iter2_reg );
SC_METHOD(thread_add_ln274_46_fu_2451_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_45_fu_2446_p2 );
SC_METHOD(thread_add_ln274_47_fu_2494_p2);
sensitive << ( add_ln274_46_reg_6139 );
sensitive << ( add_ln274_44_fu_2489_p2 );
SC_METHOD(thread_add_ln274_48_fu_2588_p2);
sensitive << ( reg_1252 );
sensitive << ( add_ln280_8_reg_5905 );
SC_METHOD(thread_add_ln274_49_fu_2547_p2);
sensitive << ( m_12_reg_5332_pp0_iter2_reg );
SC_METHOD(thread_add_ln274_4_fu_1486_p2);
sensitive << ( reg_1212 );
sensitive << ( ctx_state_6_read_1_reg_4797 );
SC_METHOD(thread_add_ln274_50_fu_2552_p2);
sensitive << ( grp_EP1_fu_954_ap_return );
sensitive << ( add_ln274_49_fu_2547_p2 );
SC_METHOD(thread_add_ln274_51_fu_2593_p2);
sensitive << ( add_ln274_50_reg_6223 );
sensitive << ( add_ln274_48_fu_2588_p2 );
SC_METHOD(thread_add_ln274_52_fu_2685_p2);
sensitive << ( reg_1272 );
SC_METHOD(thread_add_ln274_53_fu_2645_p2);
sensitive << ( m_13_reg_5339_pp0_iter2_reg );
sensitive << ( grp_EP1_fu_961_ap_return );
SC_METHOD(thread_add_ln274_54_fu_2650_p2);
sensitive << ( add_ln280_9_reg_5996 );
sensitive << ( add_ln274_53_fu_2645_p2 );
SC_METHOD(thread_add_ln274_55_fu_2691_p2);
sensitive << ( add_ln274_54_reg_6290 );
sensitive << ( add_ln274_52_fu_2685_p2 );
SC_METHOD(thread_add_ln274_56_fu_2783_p2);
sensitive << ( reg_1272 );
SC_METHOD(thread_add_ln274_57_fu_2743_p2);
sensitive << ( m_14_reg_5401_pp0_iter3_reg );
sensitive << ( grp_EP1_fu_961_ap_return );
SC_METHOD(thread_add_ln274_58_fu_2748_p2);
sensitive << ( add_ln280_10_reg_6087 );
sensitive << ( add_ln274_57_fu_2743_p2 );
SC_METHOD(thread_add_ln274_59_fu_2789_p2);
sensitive << ( add_ln274_58_reg_6356 );
sensitive << ( add_ln274_56_fu_2783_p2 );
SC_METHOD(thread_add_ln274_5_fu_1449_p2);
sensitive << ( m_1_reg_4889 );
SC_METHOD(thread_add_ln274_60_fu_2844_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_11_reg_6178 );
SC_METHOD(thread_add_ln274_61_fu_2833_p2);
sensitive << ( m_15_reg_5408_pp0_iter3_reg );
SC_METHOD(thread_add_ln274_62_fu_2838_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_61_fu_2833_p2 );
SC_METHOD(thread_add_ln274_63_fu_2849_p2);
sensitive << ( add_ln274_62_reg_6414 );
sensitive << ( add_ln274_60_fu_2844_p2 );
SC_METHOD(thread_add_ln274_64_fu_2897_p2);
sensitive << ( reg_1272 );
sensitive << ( add_ln280_12_reg_6250 );
SC_METHOD(thread_add_ln274_65_fu_2886_p2);
sensitive << ( m_16_reg_5453_pp0_iter3_reg );
SC_METHOD(thread_add_ln274_66_fu_2891_p2);
sensitive << ( grp_EP1_fu_961_ap_return );
sensitive << ( add_ln274_65_fu_2886_p2 );
SC_METHOD(thread_add_ln274_67_fu_2902_p2);
sensitive << ( add_ln274_66_reg_6442 );
sensitive << ( add_ln274_64_fu_2897_p2 );
SC_METHOD(thread_add_ln274_68_fu_2935_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_13_reg_6317 );
SC_METHOD(thread_add_ln274_69_fu_2924_p2);
sensitive << ( m_17_reg_5460_pp0_iter4_reg );
SC_METHOD(thread_add_ln274_6_fu_1454_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( add_ln274_5_fu_1449_p2 );
SC_METHOD(thread_add_ln274_70_fu_2929_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_69_fu_2924_p2 );
SC_METHOD(thread_add_ln274_71_fu_2940_p2);
sensitive << ( add_ln274_70_reg_6465 );
sensitive << ( add_ln274_68_fu_2935_p2 );
SC_METHOD(thread_add_ln274_72_fu_2973_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_14_reg_6381 );
SC_METHOD(thread_add_ln274_73_fu_2962_p2);
sensitive << ( m_18_reg_5507_pp0_iter4_reg );
SC_METHOD(thread_add_ln274_74_fu_2967_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_73_fu_2962_p2 );
SC_METHOD(thread_add_ln274_75_fu_2978_p2);
sensitive << ( add_ln274_74_reg_6488 );
sensitive << ( add_ln274_72_fu_2973_p2 );
SC_METHOD(thread_add_ln274_76_fu_3011_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_15_reg_6419 );
SC_METHOD(thread_add_ln274_77_fu_3000_p2);
sensitive << ( m_19_reg_5514_pp0_iter4_reg );
SC_METHOD(thread_add_ln274_78_fu_3005_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_77_fu_3000_p2 );
SC_METHOD(thread_add_ln274_79_fu_3016_p2);
sensitive << ( add_ln274_78_reg_6511 );
sensitive << ( add_ln274_76_fu_3011_p2 );
SC_METHOD(thread_add_ln274_7_fu_1491_p2);
sensitive << ( add_ln274_6_reg_5097 );
sensitive << ( add_ln274_4_fu_1486_p2 );
SC_METHOD(thread_add_ln274_80_fu_3049_p2);
sensitive << ( reg_1284 );
sensitive << ( add_ln280_16_reg_6447 );
SC_METHOD(thread_add_ln274_81_fu_3038_p2);
sensitive << ( m_20_reg_5559_pp0_iter4_reg );
SC_METHOD(thread_add_ln274_82_fu_3043_p2);
sensitive << ( grp_EP1_fu_968_ap_return );
sensitive << ( add_ln274_81_fu_3038_p2 );
SC_METHOD(thread_add_ln274_83_fu_3054_p2);
sensitive << ( add_ln274_82_reg_6534 );
sensitive << ( add_ln274_80_fu_3049_p2 );
SC_METHOD(thread_add_ln274_84_fu_3087_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_17_reg_6470 );
SC_METHOD(thread_add_ln274_85_fu_3076_p2);
sensitive << ( m_21_reg_5566_pp0_iter4_reg );
SC_METHOD(thread_add_ln274_86_fu_3081_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_85_fu_3076_p2 );
SC_METHOD(thread_add_ln274_87_fu_3092_p2);
sensitive << ( add_ln274_86_reg_6557 );
sensitive << ( add_ln274_84_fu_3087_p2 );
SC_METHOD(thread_add_ln274_88_fu_3125_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_18_reg_6493 );
SC_METHOD(thread_add_ln274_89_fu_3114_p2);
sensitive << ( m_22_reg_5598_pp0_iter5_reg );
SC_METHOD(thread_add_ln274_8_fu_1575_p2);
sensitive << ( reg_1212 );
SC_METHOD(thread_add_ln274_90_fu_3119_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_89_fu_3114_p2 );
SC_METHOD(thread_add_ln274_91_fu_3130_p2);
sensitive << ( add_ln274_90_reg_6580 );
sensitive << ( add_ln274_88_fu_3125_p2 );
SC_METHOD(thread_add_ln274_92_fu_3163_p2);
sensitive << ( reg_1296 );
sensitive << ( add_ln280_19_reg_6516 );
SC_METHOD(thread_add_ln274_93_fu_3152_p2);
sensitive << ( m_23_reg_5605_pp0_iter5_reg );
SC_METHOD(thread_add_ln274_94_fu_3157_p2);
sensitive << ( grp_EP1_fu_975_ap_return );
sensitive << ( add_ln274_93_fu_3152_p2 );
SC_METHOD(thread_add_ln274_95_fu_3168_p2);
sensitive << ( add_ln274_94_reg_6603 );
sensitive << ( add_ln274_92_fu_3163_p2 );
SC_METHOD(thread_add_ln274_96_fu_3200_p2);
sensitive << ( reg_1296 );
SC_METHOD(thread_add_ln274_97_fu_3190_p2);
sensitive << ( m_24_reg_5650_pp0_iter5_reg );
sensitive << ( grp_EP1_fu_975_ap_return );
SC_METHOD(thread_add_ln274_98_fu_3195_p2);
sensitive << ( add_ln280_20_reg_6539 );
sensitive << ( add_ln274_97_fu_3190_p2 );
SC_METHOD(thread_add_ln274_99_fu_3206_p2);
sensitive << ( add_ln274_98_reg_6626 );
sensitive << ( add_ln274_96_fu_3200_p2 );
SC_METHOD(thread_add_ln274_9_fu_1539_p2);
sensitive << ( grp_EP1_fu_939_ap_return );
sensitive << ( m_2_reg_4955 );
SC_METHOD(thread_add_ln274_fu_1394_p2);
sensitive << ( reg_1212 );
sensitive << ( ap_port_reg_ctx_state_7_read );
SC_METHOD(thread_add_ln280_10_fu_2397_p2);
sensitive << ( add_ln284_6_reg_5732 );
sensitive << ( add_ln274_43_fu_2392_p2 );
SC_METHOD(thread_add_ln280_11_fu_2499_p2);
sensitive << ( add_ln284_7_reg_5823 );
sensitive << ( add_ln274_47_fu_2494_p2 );
SC_METHOD(thread_add_ln280_12_fu_2598_p2);
sensitive << ( add_ln284_8_reg_5914 );
sensitive << ( add_ln274_51_fu_2593_p2 );
SC_METHOD(thread_add_ln280_13_fu_2696_p2);
sensitive << ( add_ln284_9_reg_6005 );
sensitive << ( add_ln274_55_fu_2691_p2 );
SC_METHOD(thread_add_ln280_14_fu_2794_p2);
sensitive << ( add_ln284_10_reg_6096 );
sensitive << ( add_ln274_59_fu_2789_p2 );
SC_METHOD(thread_add_ln280_15_fu_2854_p2);
sensitive << ( add_ln284_11_reg_6187 );
sensitive << ( add_ln274_63_fu_2849_p2 );
SC_METHOD(thread_add_ln280_16_fu_2907_p2);
sensitive << ( add_ln284_12_reg_6259 );
sensitive << ( add_ln274_67_fu_2902_p2 );
SC_METHOD(thread_add_ln280_17_fu_2945_p2);
sensitive << ( add_ln284_13_reg_6326 );
sensitive << ( add_ln274_71_fu_2940_p2 );
SC_METHOD(thread_add_ln280_18_fu_2983_p2);
sensitive << ( add_ln284_14_reg_6390 );
sensitive << ( add_ln274_75_fu_2978_p2 );
SC_METHOD(thread_add_ln280_19_fu_3021_p2);
sensitive << ( add_ln284_15_reg_6428 );
sensitive << ( add_ln274_79_fu_3016_p2 );
SC_METHOD(thread_add_ln280_1_fu_1496_p2);
sensitive << ( ctx_state_2_read_1_reg_4818 );
sensitive << ( add_ln274_7_fu_1491_p2 );
SC_METHOD(thread_add_ln280_20_fu_3059_p2);
sensitive << ( add_ln284_16_reg_6456 );
sensitive << ( add_ln274_83_fu_3054_p2 );
SC_METHOD(thread_add_ln280_21_fu_3097_p2);
sensitive << ( add_ln284_17_reg_6479 );
sensitive << ( add_ln274_87_fu_3092_p2 );
SC_METHOD(thread_add_ln280_22_fu_3135_p2);
sensitive << ( add_ln284_18_reg_6502 );
sensitive << ( add_ln274_91_fu_3130_p2 );
SC_METHOD(thread_add_ln280_23_fu_3173_p2);
sensitive << ( add_ln284_19_reg_6525 );
sensitive << ( add_ln274_95_fu_3168_p2 );
SC_METHOD(thread_add_ln280_24_fu_3211_p2);
sensitive << ( add_ln284_20_reg_6548 );
sensitive << ( add_ln274_99_fu_3206_p2 );
SC_METHOD(thread_add_ln280_25_fu_3249_p2);
sensitive << ( add_ln284_21_reg_6571 );
sensitive << ( add_ln274_103_fu_3244_p2 );
SC_METHOD(thread_add_ln280_26_fu_3287_p2);
sensitive << ( add_ln284_22_reg_6594 );
sensitive << ( add_ln274_107_fu_3282_p2 );
SC_METHOD(thread_add_ln280_27_fu_3325_p2);
sensitive << ( add_ln284_23_reg_6617 );
sensitive << ( add_ln274_111_fu_3320_p2 );
SC_METHOD(thread_add_ln280_28_fu_3363_p2);
sensitive << ( add_ln284_24_reg_6640 );
sensitive << ( add_ln274_115_fu_3358_p2 );
SC_METHOD(thread_add_ln280_29_fu_3401_p2);
sensitive << ( add_ln284_25_reg_6663 );
sensitive << ( add_ln274_119_fu_3396_p2 );
SC_METHOD(thread_add_ln280_2_fu_1586_p2);
sensitive << ( ctx_state_1_read_1_reg_4824 );
sensitive << ( add_ln274_11_fu_1581_p2 );
SC_METHOD(thread_add_ln280_30_fu_3439_p2);
sensitive << ( add_ln284_26_reg_6686 );
sensitive << ( add_ln274_123_fu_3434_p2 );
SC_METHOD(thread_add_ln280_31_fu_3477_p2);
sensitive << ( add_ln284_27_reg_6709 );
sensitive << ( add_ln274_127_fu_3472_p2 );
SC_METHOD(thread_add_ln280_32_fu_3515_p2);
sensitive << ( add_ln284_28_reg_6732 );
sensitive << ( add_ln274_131_fu_3510_p2 );
SC_METHOD(thread_add_ln280_33_fu_3553_p2);
sensitive << ( add_ln284_29_reg_6755_pp0_iter8_reg );
sensitive << ( add_ln274_135_fu_3548_p2 );
SC_METHOD(thread_add_ln280_34_fu_3591_p2);
sensitive << ( add_ln284_30_reg_6778_pp0_iter8_reg );
sensitive << ( add_ln274_139_fu_3586_p2 );
SC_METHOD(thread_add_ln280_35_fu_3629_p2);
sensitive << ( add_ln284_31_reg_6801_pp0_iter9_reg );
sensitive << ( add_ln274_143_fu_3624_p2 );
SC_METHOD(thread_add_ln280_36_fu_3667_p2);
sensitive << ( add_ln284_32_reg_6824_pp0_iter9_reg );
sensitive << ( add_ln274_147_fu_3662_p2 );
SC_METHOD(thread_add_ln280_37_fu_3705_p2);
sensitive << ( add_ln284_33_reg_6847 );
sensitive << ( add_ln274_151_fu_3700_p2 );
SC_METHOD(thread_add_ln280_38_fu_3743_p2);
sensitive << ( add_ln284_34_reg_6870 );
sensitive << ( add_ln274_155_fu_3738_p2 );
SC_METHOD(thread_add_ln280_39_fu_3781_p2);
sensitive << ( add_ln284_35_reg_6893 );
sensitive << ( add_ln274_159_fu_3776_p2 );
SC_METHOD(thread_add_ln280_3_fu_1686_p2);
sensitive << ( ctx_state_0_read_1_reg_4831 );
sensitive << ( add_ln274_15_fu_1681_p2 );
SC_METHOD(thread_add_ln280_40_fu_3819_p2);
sensitive << ( add_ln284_36_reg_6916 );
sensitive << ( add_ln274_163_fu_3814_p2 );
SC_METHOD(thread_add_ln280_41_fu_3857_p2);
sensitive << ( add_ln284_37_reg_6939 );
sensitive << ( add_ln274_167_fu_3852_p2 );
SC_METHOD(thread_add_ln280_42_fu_3895_p2);
sensitive << ( add_ln284_38_reg_6962 );
sensitive << ( add_ln274_171_fu_3890_p2 );
SC_METHOD(thread_add_ln280_43_fu_3933_p2);
sensitive << ( add_ln284_39_reg_6985 );
sensitive << ( add_ln274_175_fu_3928_p2 );
SC_METHOD(thread_add_ln280_44_fu_3971_p2);
sensitive << ( add_ln284_40_reg_7008 );
sensitive << ( add_ln274_179_fu_3966_p2 );
SC_METHOD(thread_add_ln280_45_fu_4009_p2);
sensitive << ( add_ln284_41_reg_7031 );
sensitive << ( add_ln274_183_fu_4004_p2 );
SC_METHOD(thread_add_ln280_46_fu_4047_p2);
sensitive << ( add_ln284_42_reg_7054 );
sensitive << ( add_ln274_187_fu_4042_p2 );
SC_METHOD(thread_add_ln280_47_fu_4100_p2);
sensitive << ( add_ln284_43_reg_7077 );
sensitive << ( add_ln274_191_fu_4095_p2 );
SC_METHOD(thread_add_ln280_48_fu_4138_p2);
sensitive << ( add_ln284_44_reg_7100 );
sensitive << ( add_ln274_195_fu_4133_p2 );
SC_METHOD(thread_add_ln280_49_fu_4176_p2);
sensitive << ( add_ln284_45_reg_7123 );
sensitive << ( add_ln274_199_fu_4171_p2 );
SC_METHOD(thread_add_ln280_4_fu_1787_p2);
sensitive << ( add_ln284_reg_5026 );
sensitive << ( add_ln274_19_fu_1782_p2 );
SC_METHOD(thread_add_ln280_50_fu_4214_p2);
sensitive << ( add_ln284_46_reg_7146 );
sensitive << ( add_ln274_203_fu_4209_p2 );
SC_METHOD(thread_add_ln280_51_fu_4252_p2);
sensitive << ( add_ln284_47_reg_7174 );
sensitive << ( add_ln274_207_fu_4247_p2 );
SC_METHOD(thread_add_ln280_52_fu_4290_p2);
sensitive << ( add_ln284_48_reg_7197 );
sensitive << ( add_ln274_211_fu_4285_p2 );
SC_METHOD(thread_add_ln280_53_fu_4328_p2);
sensitive << ( add_ln284_49_reg_7220 );
sensitive << ( add_ln274_215_fu_4323_p2 );
SC_METHOD(thread_add_ln280_54_fu_4366_p2);
sensitive << ( add_ln284_50_reg_7243 );
sensitive << ( add_ln274_219_fu_4361_p2 );
SC_METHOD(thread_add_ln280_55_fu_4404_p2);
sensitive << ( add_ln284_51_reg_7266 );
sensitive << ( add_ln274_223_fu_4399_p2 );
SC_METHOD(thread_add_ln280_56_fu_4442_p2);
sensitive << ( add_ln284_52_reg_7289 );
sensitive << ( add_ln274_227_fu_4437_p2 );
SC_METHOD(thread_add_ln280_57_fu_4480_p2);
sensitive << ( add_ln284_53_reg_7312 );
sensitive << ( add_ln274_231_fu_4475_p2 );
SC_METHOD(thread_add_ln280_58_fu_4518_p2);
sensitive << ( add_ln284_54_reg_7335 );
sensitive << ( add_ln274_235_fu_4513_p2 );
SC_METHOD(thread_add_ln280_59_fu_4556_p2);
sensitive << ( add_ln284_55_reg_7358 );
sensitive << ( add_ln274_239_fu_4551_p2 );
SC_METHOD(thread_add_ln280_5_fu_1887_p2);
sensitive << ( add_ln284_1_reg_5173 );
sensitive << ( add_ln274_23_fu_1882_p2 );
SC_METHOD(thread_add_ln280_60_fu_4594_p2);
sensitive << ( add_ln284_56_reg_7381 );
sensitive << ( add_ln274_243_fu_4589_p2 );
SC_METHOD(thread_add_ln280_61_fu_4632_p2);
sensitive << ( add_ln284_57_reg_7404 );
sensitive << ( add_ln274_247_fu_4627_p2 );
SC_METHOD(thread_add_ln280_62_fu_4669_p2);
sensitive << ( add_ln284_58_reg_7427 );
sensitive << ( add_ln274_251_fu_4664_p2 );
SC_METHOD(thread_add_ln280_6_fu_1989_p2);
sensitive << ( add_ln284_2_reg_5323 );
sensitive << ( add_ln274_27_fu_1984_p2 );
SC_METHOD(thread_add_ln280_7_fu_2091_p2);
sensitive << ( add_ln284_3_reg_5444 );
sensitive << ( add_ln274_31_fu_2086_p2 );
SC_METHOD(thread_add_ln280_8_fu_2193_p2);
sensitive << ( add_ln284_4_reg_5550 );
sensitive << ( add_ln274_35_fu_2188_p2 );
SC_METHOD(thread_add_ln280_9_fu_2295_p2);
sensitive << ( add_ln284_5_reg_5641 );
sensitive << ( add_ln274_39_fu_2290_p2 );
SC_METHOD(thread_add_ln280_fu_1405_p2);
sensitive << ( ap_port_reg_ctx_state_3_read );
sensitive << ( add_ln274_3_fu_1400_p2 );
SC_METHOD(thread_add_ln284_100_fu_3710_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_151_fu_3700_p2 );
SC_METHOD(thread_add_ln284_101_fu_3748_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_155_fu_3738_p2 );
SC_METHOD(thread_add_ln284_102_fu_3786_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_159_fu_3776_p2 );
SC_METHOD(thread_add_ln284_103_fu_3824_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_163_fu_3814_p2 );
SC_METHOD(thread_add_ln284_104_fu_3862_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_167_fu_3852_p2 );
SC_METHOD(thread_add_ln284_105_fu_3900_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_171_fu_3890_p2 );
SC_METHOD(thread_add_ln284_106_fu_3938_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_175_fu_3928_p2 );
SC_METHOD(thread_add_ln284_107_fu_3976_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_179_fu_3966_p2 );
SC_METHOD(thread_add_ln284_108_fu_4014_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_183_fu_4004_p2 );
SC_METHOD(thread_add_ln284_109_fu_4052_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_187_fu_4042_p2 );
SC_METHOD(thread_add_ln284_10_fu_2408_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_73_fu_2402_p2 );
SC_METHOD(thread_add_ln284_110_fu_4105_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_191_fu_4095_p2 );
SC_METHOD(thread_add_ln284_111_fu_4143_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_195_fu_4133_p2 );
SC_METHOD(thread_add_ln284_112_fu_4181_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_199_fu_4171_p2 );
SC_METHOD(thread_add_ln284_113_fu_4219_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_203_fu_4209_p2 );
SC_METHOD(thread_add_ln284_114_fu_4257_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_207_fu_4247_p2 );
SC_METHOD(thread_add_ln284_115_fu_4295_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_211_fu_4285_p2 );
SC_METHOD(thread_add_ln284_116_fu_4333_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_215_fu_4323_p2 );
SC_METHOD(thread_add_ln284_117_fu_4371_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_219_fu_4361_p2 );
SC_METHOD(thread_add_ln284_118_fu_4409_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_223_fu_4399_p2 );
SC_METHOD(thread_add_ln284_119_fu_4447_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_227_fu_4437_p2 );
SC_METHOD(thread_add_ln284_11_fu_2510_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_74_fu_2504_p2 );
SC_METHOD(thread_add_ln284_120_fu_4485_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_231_fu_4475_p2 );
SC_METHOD(thread_add_ln284_121_fu_4523_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_235_fu_4513_p2 );
SC_METHOD(thread_add_ln284_122_fu_4561_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_239_fu_4551_p2 );
SC_METHOD(thread_add_ln284_123_fu_4599_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_243_fu_4589_p2 );
SC_METHOD(thread_add_ln284_124_fu_4637_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_247_fu_4627_p2 );
SC_METHOD(thread_add_ln284_125_fu_4674_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_251_fu_4664_p2 );
SC_METHOD(thread_add_ln284_12_fu_2609_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_75_fu_2603_p2 );
SC_METHOD(thread_add_ln284_13_fu_2707_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_76_fu_2701_p2 );
SC_METHOD(thread_add_ln284_14_fu_2805_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_77_fu_2799_p2 );
SC_METHOD(thread_add_ln284_15_fu_2865_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_78_fu_2859_p2 );
SC_METHOD(thread_add_ln284_16_fu_2918_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_79_fu_2912_p2 );
SC_METHOD(thread_add_ln284_17_fu_2956_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_80_fu_2950_p2 );
SC_METHOD(thread_add_ln284_18_fu_2994_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_81_fu_2988_p2 );
SC_METHOD(thread_add_ln284_19_fu_3032_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_82_fu_3026_p2 );
SC_METHOD(thread_add_ln284_1_fu_1507_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_64_fu_1501_p2 );
SC_METHOD(thread_add_ln284_20_fu_3070_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_83_fu_3064_p2 );
SC_METHOD(thread_add_ln284_21_fu_3108_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_84_fu_3102_p2 );
SC_METHOD(thread_add_ln284_22_fu_3146_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_85_fu_3140_p2 );
SC_METHOD(thread_add_ln284_23_fu_3184_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_86_fu_3178_p2 );
SC_METHOD(thread_add_ln284_24_fu_3222_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_87_fu_3216_p2 );
SC_METHOD(thread_add_ln284_25_fu_3260_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_88_fu_3254_p2 );
SC_METHOD(thread_add_ln284_26_fu_3298_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_89_fu_3292_p2 );
SC_METHOD(thread_add_ln284_27_fu_3336_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_90_fu_3330_p2 );
SC_METHOD(thread_add_ln284_28_fu_3374_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_91_fu_3368_p2 );
SC_METHOD(thread_add_ln284_29_fu_3412_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_92_fu_3406_p2 );
SC_METHOD(thread_add_ln284_2_fu_1597_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_65_fu_1591_p2 );
SC_METHOD(thread_add_ln284_30_fu_3450_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_93_fu_3444_p2 );
SC_METHOD(thread_add_ln284_31_fu_3488_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_94_fu_3482_p2 );
SC_METHOD(thread_add_ln284_32_fu_3526_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_95_fu_3520_p2 );
SC_METHOD(thread_add_ln284_33_fu_3564_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_96_fu_3558_p2 );
SC_METHOD(thread_add_ln284_34_fu_3602_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_97_fu_3596_p2 );
SC_METHOD(thread_add_ln284_35_fu_3640_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_98_fu_3634_p2 );
SC_METHOD(thread_add_ln284_36_fu_3678_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_99_fu_3672_p2 );
SC_METHOD(thread_add_ln284_37_fu_3716_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_100_fu_3710_p2 );
SC_METHOD(thread_add_ln284_38_fu_3754_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_101_fu_3748_p2 );
SC_METHOD(thread_add_ln284_39_fu_3792_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_102_fu_3786_p2 );
SC_METHOD(thread_add_ln284_3_fu_1697_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_66_fu_1691_p2 );
SC_METHOD(thread_add_ln284_40_fu_3830_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_103_fu_3824_p2 );
SC_METHOD(thread_add_ln284_41_fu_3868_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_104_fu_3862_p2 );
SC_METHOD(thread_add_ln284_42_fu_3906_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_105_fu_3900_p2 );
SC_METHOD(thread_add_ln284_43_fu_3944_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_106_fu_3938_p2 );
SC_METHOD(thread_add_ln284_44_fu_3982_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_107_fu_3976_p2 );
SC_METHOD(thread_add_ln284_45_fu_4020_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_108_fu_4014_p2 );
SC_METHOD(thread_add_ln284_46_fu_4058_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_109_fu_4052_p2 );
SC_METHOD(thread_add_ln284_47_fu_4111_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_110_fu_4105_p2 );
SC_METHOD(thread_add_ln284_48_fu_4149_p2);
sensitive << ( reg_1276 );
sensitive << ( add_ln284_111_fu_4143_p2 );
SC_METHOD(thread_add_ln284_49_fu_4187_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_112_fu_4181_p2 );
SC_METHOD(thread_add_ln284_4_fu_1797_p2);
sensitive << ( tmp_4_0_4_reg_5497 );
sensitive << ( add_ln284_67_fu_1792_p2 );
SC_METHOD(thread_add_ln284_50_fu_4225_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_113_fu_4219_p2 );
SC_METHOD(thread_add_ln284_51_fu_4263_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_114_fu_4257_p2 );
SC_METHOD(thread_add_ln284_52_fu_4301_p2);
sensitive << ( reg_1288 );
sensitive << ( add_ln284_115_fu_4295_p2 );
SC_METHOD(thread_add_ln284_53_fu_4339_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_116_fu_4333_p2 );
SC_METHOD(thread_add_ln284_54_fu_4377_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_117_fu_4371_p2 );
SC_METHOD(thread_add_ln284_55_fu_4415_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_118_fu_4409_p2 );
SC_METHOD(thread_add_ln284_56_fu_4453_p2);
sensitive << ( reg_1300 );
sensitive << ( add_ln284_119_fu_4447_p2 );
SC_METHOD(thread_add_ln284_57_fu_4491_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_120_fu_4485_p2 );
SC_METHOD(thread_add_ln284_58_fu_4529_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_121_fu_4523_p2 );
SC_METHOD(thread_add_ln284_59_fu_4567_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_122_fu_4561_p2 );
SC_METHOD(thread_add_ln284_5_fu_1898_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_68_fu_1892_p2 );
SC_METHOD(thread_add_ln284_60_fu_4605_p2);
sensitive << ( reg_1312 );
sensitive << ( add_ln284_123_fu_4599_p2 );
SC_METHOD(thread_add_ln284_61_fu_4643_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_124_fu_4637_p2 );
SC_METHOD(thread_add_ln284_62_fu_4680_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln284_125_fu_4674_p2 );
SC_METHOD(thread_add_ln284_63_fu_1411_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_3_fu_1400_p2 );
SC_METHOD(thread_add_ln284_64_fu_1501_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_7_fu_1491_p2 );
SC_METHOD(thread_add_ln284_65_fu_1591_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_11_fu_1581_p2 );
SC_METHOD(thread_add_ln284_66_fu_1691_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_15_fu_1681_p2 );
SC_METHOD(thread_add_ln284_67_fu_1792_p2);
sensitive << ( tmp_5_0_4_reg_5502 );
sensitive << ( add_ln274_19_fu_1782_p2 );
SC_METHOD(thread_add_ln284_68_fu_1892_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_23_fu_1882_p2 );
SC_METHOD(thread_add_ln284_69_fu_1994_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_27_fu_1984_p2 );
SC_METHOD(thread_add_ln284_6_fu_2000_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_69_fu_1994_p2 );
SC_METHOD(thread_add_ln284_70_fu_2096_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_31_fu_2086_p2 );
SC_METHOD(thread_add_ln284_71_fu_2198_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_35_fu_2188_p2 );
SC_METHOD(thread_add_ln284_72_fu_2300_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_39_fu_2290_p2 );
SC_METHOD(thread_add_ln284_73_fu_2402_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_43_fu_2392_p2 );
SC_METHOD(thread_add_ln284_74_fu_2504_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_47_fu_2494_p2 );
SC_METHOD(thread_add_ln284_75_fu_2603_p2);
sensitive << ( reg_1260 );
sensitive << ( add_ln274_51_fu_2593_p2 );
SC_METHOD(thread_add_ln284_76_fu_2701_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_55_fu_2691_p2 );
SC_METHOD(thread_add_ln284_77_fu_2799_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_59_fu_2789_p2 );
SC_METHOD(thread_add_ln284_78_fu_2859_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_63_fu_2849_p2 );
SC_METHOD(thread_add_ln284_79_fu_2912_p2);
sensitive << ( reg_1280 );
sensitive << ( add_ln274_67_fu_2902_p2 );
SC_METHOD(thread_add_ln284_7_fu_2102_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_70_fu_2096_p2 );
SC_METHOD(thread_add_ln284_80_fu_2950_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_71_fu_2940_p2 );
SC_METHOD(thread_add_ln284_81_fu_2988_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_75_fu_2978_p2 );
SC_METHOD(thread_add_ln284_82_fu_3026_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_79_fu_3016_p2 );
SC_METHOD(thread_add_ln284_83_fu_3064_p2);
sensitive << ( reg_1292 );
sensitive << ( add_ln274_83_fu_3054_p2 );
SC_METHOD(thread_add_ln284_84_fu_3102_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_87_fu_3092_p2 );
SC_METHOD(thread_add_ln284_85_fu_3140_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_91_fu_3130_p2 );
SC_METHOD(thread_add_ln284_86_fu_3178_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_95_fu_3168_p2 );
SC_METHOD(thread_add_ln284_87_fu_3216_p2);
sensitive << ( reg_1304 );
sensitive << ( add_ln274_99_fu_3206_p2 );
SC_METHOD(thread_add_ln284_88_fu_3254_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_103_fu_3244_p2 );
SC_METHOD(thread_add_ln284_89_fu_3292_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_107_fu_3282_p2 );
SC_METHOD(thread_add_ln284_8_fu_2204_p2);
sensitive << ( reg_1236 );
sensitive << ( add_ln284_71_fu_2198_p2 );
SC_METHOD(thread_add_ln284_90_fu_3330_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_111_fu_3320_p2 );
SC_METHOD(thread_add_ln284_91_fu_3368_p2);
sensitive << ( reg_1316 );
sensitive << ( add_ln274_115_fu_3358_p2 );
SC_METHOD(thread_add_ln284_92_fu_3406_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_119_fu_3396_p2 );
SC_METHOD(thread_add_ln284_93_fu_3444_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_123_fu_3434_p2 );
SC_METHOD(thread_add_ln284_94_fu_3482_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_127_fu_3472_p2 );
SC_METHOD(thread_add_ln284_95_fu_3520_p2);
sensitive << ( reg_1328 );
sensitive << ( add_ln274_131_fu_3510_p2 );
SC_METHOD(thread_add_ln284_96_fu_3558_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_135_fu_3548_p2 );
SC_METHOD(thread_add_ln284_97_fu_3596_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_139_fu_3586_p2 );
SC_METHOD(thread_add_ln284_98_fu_3634_p2);
sensitive << ( reg_1240 );
sensitive << ( add_ln274_143_fu_3624_p2 );
SC_METHOD(thread_add_ln284_99_fu_3672_p2);
sensitive << ( reg_1220 );
sensitive << ( add_ln274_147_fu_3662_p2 );
SC_METHOD(thread_add_ln284_9_fu_2306_p2);
sensitive << ( reg_1256 );
sensitive << ( add_ln284_72_fu_2300_p2 );
SC_METHOD(thread_add_ln284_fu_1417_p2);
sensitive << ( reg_1216 );
sensitive << ( add_ln284_63_fu_1411_p2 );
SC_METHOD(thread_add_ln288_1_fu_4734_p2);
sensitive << ( reg_1324 );
sensitive << ( add_ln274_255_fu_4729_p2 );
SC_METHOD(thread_add_ln288_2_fu_4696_p2);
sensitive << ( grp_MAJ_fu_930_ap_return );
sensitive << ( ctx_state_0_read_1_reg_4831_pp0_iter16_reg );
SC_METHOD(thread_add_ln288_fu_4740_p2);
sensitive << ( add_ln288_2_reg_7537 );
sensitive << ( add_ln288_1_fu_4734_p2 );
SC_METHOD(thread_add_ln289_fu_4701_p2);
sensitive << ( ctx_state_1_read_1_reg_4824_pp0_iter16_reg );
sensitive << ( add_ln284_62_reg_7520 );
SC_METHOD(thread_add_ln290_fu_4705_p2);
sensitive << ( ctx_state_2_read_1_reg_4818_pp0_iter16_reg );
sensitive << ( add_ln284_61_reg_7495 );
SC_METHOD(thread_add_ln291_fu_4709_p2);
sensitive << ( ctx_state_3_read_1_reg_4950_pp0_iter15_reg );
sensitive << ( add_ln284_60_reg_7473 );
SC_METHOD(thread_add_ln292_1_fu_4745_p2);
sensitive << ( ctx_state_4_read_1_reg_4810_pp0_iter16_reg );
sensitive << ( add_ln284_59_reg_7450_pp0_iter16_reg );
SC_METHOD(thread_add_ln292_fu_4749_p2);
sensitive << ( add_ln274_255_fu_4729_p2 );
sensitive << ( add_ln292_1_fu_4745_p2 );
SC_METHOD(thread_add_ln293_fu_4713_p2);
sensitive << ( ctx_state_5_read_1_reg_4803_pp0_iter16_reg );
sensitive << ( add_ln280_62_reg_7513 );
SC_METHOD(thread_add_ln294_fu_4717_p2);
sensitive << ( ctx_state_6_read_1_reg_4797_pp0_iter16_reg );
sensitive << ( add_ln280_61_reg_7487 );
SC_METHOD(thread_add_ln295_fu_4721_p2);
sensitive << ( ctx_state_7_read_1_reg_4945_pp0_iter15_reg );
sensitive << ( add_ln280_60_reg_7464 );
SC_METHOD(thread_ap_CS_fsm_pp0_stage0);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage1);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage2);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage3);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage4);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage5);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage6);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_CS_fsm_pp0_stage7);
sensitive << ( ap_CS_fsm );
SC_METHOD(thread_ap_block_pp0_stage0);
SC_METHOD(thread_ap_block_pp0_stage0_11001);
sensitive << ( ap_start );
sensitive << ( ap_enable_reg_pp0_iter0 );
SC_METHOD(thread_ap_block_pp0_stage0_subdone);
sensitive << ( ap_start );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage1);
SC_METHOD(thread_ap_block_pp0_stage1_11001);
SC_METHOD(thread_ap_block_pp0_stage1_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage2);
SC_METHOD(thread_ap_block_pp0_stage2_11001);
SC_METHOD(thread_ap_block_pp0_stage2_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage3);
SC_METHOD(thread_ap_block_pp0_stage3_11001);
SC_METHOD(thread_ap_block_pp0_stage3_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage4);
SC_METHOD(thread_ap_block_pp0_stage4_11001);
SC_METHOD(thread_ap_block_pp0_stage4_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage5);
SC_METHOD(thread_ap_block_pp0_stage5_11001);
SC_METHOD(thread_ap_block_pp0_stage5_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage6);
SC_METHOD(thread_ap_block_pp0_stage6_11001);
SC_METHOD(thread_ap_block_pp0_stage6_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_pp0_stage7);
SC_METHOD(thread_ap_block_pp0_stage7_11001);
SC_METHOD(thread_ap_block_pp0_stage7_subdone);
sensitive << ( ap_ce );
SC_METHOD(thread_ap_block_state100_pp0_stage3_iter12);
SC_METHOD(thread_ap_block_state101_pp0_stage4_iter12);
SC_METHOD(thread_ap_block_state102_pp0_stage5_iter12);
SC_METHOD(thread_ap_block_state103_pp0_stage6_iter12);
SC_METHOD(thread_ap_block_state104_pp0_stage7_iter12);
SC_METHOD(thread_ap_block_state105_pp0_stage0_iter13);
SC_METHOD(thread_ap_block_state106_pp0_stage1_iter13);
SC_METHOD(thread_ap_block_state107_pp0_stage2_iter13);
SC_METHOD(thread_ap_block_state108_pp0_stage3_iter13);
SC_METHOD(thread_ap_block_state109_pp0_stage4_iter13);
SC_METHOD(thread_ap_block_state10_pp0_stage1_iter1);
SC_METHOD(thread_ap_block_state110_pp0_stage5_iter13);
SC_METHOD(thread_ap_block_state111_pp0_stage6_iter13);
SC_METHOD(thread_ap_block_state112_pp0_stage7_iter13);
SC_METHOD(thread_ap_block_state113_pp0_stage0_iter14);
SC_METHOD(thread_ap_block_state114_pp0_stage1_iter14);
SC_METHOD(thread_ap_block_state115_pp0_stage2_iter14);
SC_METHOD(thread_ap_block_state116_pp0_stage3_iter14);
SC_METHOD(thread_ap_block_state117_pp0_stage4_iter14);
SC_METHOD(thread_ap_block_state118_pp0_stage5_iter14);
SC_METHOD(thread_ap_block_state119_pp0_stage6_iter14);
SC_METHOD(thread_ap_block_state11_pp0_stage2_iter1);
SC_METHOD(thread_ap_block_state120_pp0_stage7_iter14);
SC_METHOD(thread_ap_block_state121_pp0_stage0_iter15);
SC_METHOD(thread_ap_block_state122_pp0_stage1_iter15);
SC_METHOD(thread_ap_block_state123_pp0_stage2_iter15);
SC_METHOD(thread_ap_block_state124_pp0_stage3_iter15);
SC_METHOD(thread_ap_block_state125_pp0_stage4_iter15);
SC_METHOD(thread_ap_block_state126_pp0_stage5_iter15);
SC_METHOD(thread_ap_block_state127_pp0_stage6_iter15);
SC_METHOD(thread_ap_block_state128_pp0_stage7_iter15);
SC_METHOD(thread_ap_block_state129_pp0_stage0_iter16);
SC_METHOD(thread_ap_block_state12_pp0_stage3_iter1);
SC_METHOD(thread_ap_block_state130_pp0_stage1_iter16);
SC_METHOD(thread_ap_block_state131_pp0_stage2_iter16);
SC_METHOD(thread_ap_block_state132_pp0_stage3_iter16);
SC_METHOD(thread_ap_block_state13_pp0_stage4_iter1);
SC_METHOD(thread_ap_block_state14_pp0_stage5_iter1);
SC_METHOD(thread_ap_block_state15_pp0_stage6_iter1);
SC_METHOD(thread_ap_block_state16_pp0_stage7_iter1);
SC_METHOD(thread_ap_block_state17_pp0_stage0_iter2);
SC_METHOD(thread_ap_block_state18_pp0_stage1_iter2);
SC_METHOD(thread_ap_block_state19_pp0_stage2_iter2);
SC_METHOD(thread_ap_block_state1_pp0_stage0_iter0);
sensitive << ( ap_start );
SC_METHOD(thread_ap_block_state20_pp0_stage3_iter2);
SC_METHOD(thread_ap_block_state21_pp0_stage4_iter2);
SC_METHOD(thread_ap_block_state22_pp0_stage5_iter2);
SC_METHOD(thread_ap_block_state23_pp0_stage6_iter2);
SC_METHOD(thread_ap_block_state24_pp0_stage7_iter2);
SC_METHOD(thread_ap_block_state25_pp0_stage0_iter3);
SC_METHOD(thread_ap_block_state26_pp0_stage1_iter3);
SC_METHOD(thread_ap_block_state27_pp0_stage2_iter3);
SC_METHOD(thread_ap_block_state28_pp0_stage3_iter3);
SC_METHOD(thread_ap_block_state29_pp0_stage4_iter3);
SC_METHOD(thread_ap_block_state2_pp0_stage1_iter0);
SC_METHOD(thread_ap_block_state30_pp0_stage5_iter3);
SC_METHOD(thread_ap_block_state31_pp0_stage6_iter3);
SC_METHOD(thread_ap_block_state32_pp0_stage7_iter3);
SC_METHOD(thread_ap_block_state33_pp0_stage0_iter4);
SC_METHOD(thread_ap_block_state34_pp0_stage1_iter4);
SC_METHOD(thread_ap_block_state35_pp0_stage2_iter4);
SC_METHOD(thread_ap_block_state36_pp0_stage3_iter4);
SC_METHOD(thread_ap_block_state37_pp0_stage4_iter4);
SC_METHOD(thread_ap_block_state38_pp0_stage5_iter4);
SC_METHOD(thread_ap_block_state39_pp0_stage6_iter4);
SC_METHOD(thread_ap_block_state3_pp0_stage2_iter0);
SC_METHOD(thread_ap_block_state40_pp0_stage7_iter4);
SC_METHOD(thread_ap_block_state41_pp0_stage0_iter5);
SC_METHOD(thread_ap_block_state42_pp0_stage1_iter5);
SC_METHOD(thread_ap_block_state43_pp0_stage2_iter5);
SC_METHOD(thread_ap_block_state44_pp0_stage3_iter5);
SC_METHOD(thread_ap_block_state45_pp0_stage4_iter5);
SC_METHOD(thread_ap_block_state46_pp0_stage5_iter5);
SC_METHOD(thread_ap_block_state47_pp0_stage6_iter5);
SC_METHOD(thread_ap_block_state48_pp0_stage7_iter5);
SC_METHOD(thread_ap_block_state49_pp0_stage0_iter6);
SC_METHOD(thread_ap_block_state4_pp0_stage3_iter0);
SC_METHOD(thread_ap_block_state50_pp0_stage1_iter6);
SC_METHOD(thread_ap_block_state51_pp0_stage2_iter6);
SC_METHOD(thread_ap_block_state52_pp0_stage3_iter6);
SC_METHOD(thread_ap_block_state53_pp0_stage4_iter6);
SC_METHOD(thread_ap_block_state54_pp0_stage5_iter6);
SC_METHOD(thread_ap_block_state55_pp0_stage6_iter6);
SC_METHOD(thread_ap_block_state56_pp0_stage7_iter6);
SC_METHOD(thread_ap_block_state57_pp0_stage0_iter7);
SC_METHOD(thread_ap_block_state58_pp0_stage1_iter7);
SC_METHOD(thread_ap_block_state59_pp0_stage2_iter7);
SC_METHOD(thread_ap_block_state5_pp0_stage4_iter0);
SC_METHOD(thread_ap_block_state60_pp0_stage3_iter7);
SC_METHOD(thread_ap_block_state61_pp0_stage4_iter7);
SC_METHOD(thread_ap_block_state62_pp0_stage5_iter7);
SC_METHOD(thread_ap_block_state63_pp0_stage6_iter7);
SC_METHOD(thread_ap_block_state64_pp0_stage7_iter7);
SC_METHOD(thread_ap_block_state65_pp0_stage0_iter8);
SC_METHOD(thread_ap_block_state66_pp0_stage1_iter8);
SC_METHOD(thread_ap_block_state67_pp0_stage2_iter8);
SC_METHOD(thread_ap_block_state68_pp0_stage3_iter8);
SC_METHOD(thread_ap_block_state69_pp0_stage4_iter8);
SC_METHOD(thread_ap_block_state6_pp0_stage5_iter0);
SC_METHOD(thread_ap_block_state70_pp0_stage5_iter8);
SC_METHOD(thread_ap_block_state71_pp0_stage6_iter8);
SC_METHOD(thread_ap_block_state72_pp0_stage7_iter8);
SC_METHOD(thread_ap_block_state73_pp0_stage0_iter9);
SC_METHOD(thread_ap_block_state74_pp0_stage1_iter9);
SC_METHOD(thread_ap_block_state75_pp0_stage2_iter9);
SC_METHOD(thread_ap_block_state76_pp0_stage3_iter9);
SC_METHOD(thread_ap_block_state77_pp0_stage4_iter9);
SC_METHOD(thread_ap_block_state78_pp0_stage5_iter9);
SC_METHOD(thread_ap_block_state79_pp0_stage6_iter9);
SC_METHOD(thread_ap_block_state7_pp0_stage6_iter0);
SC_METHOD(thread_ap_block_state80_pp0_stage7_iter9);
SC_METHOD(thread_ap_block_state81_pp0_stage0_iter10);
SC_METHOD(thread_ap_block_state82_pp0_stage1_iter10);
SC_METHOD(thread_ap_block_state83_pp0_stage2_iter10);
SC_METHOD(thread_ap_block_state84_pp0_stage3_iter10);
SC_METHOD(thread_ap_block_state85_pp0_stage4_iter10);
SC_METHOD(thread_ap_block_state86_pp0_stage5_iter10);
SC_METHOD(thread_ap_block_state87_pp0_stage6_iter10);
SC_METHOD(thread_ap_block_state88_pp0_stage7_iter10);
SC_METHOD(thread_ap_block_state89_pp0_stage0_iter11);
SC_METHOD(thread_ap_block_state8_pp0_stage7_iter0);
SC_METHOD(thread_ap_block_state90_pp0_stage1_iter11);
SC_METHOD(thread_ap_block_state91_pp0_stage2_iter11);
SC_METHOD(thread_ap_block_state92_pp0_stage3_iter11);
SC_METHOD(thread_ap_block_state93_pp0_stage4_iter11);
SC_METHOD(thread_ap_block_state94_pp0_stage5_iter11);
SC_METHOD(thread_ap_block_state95_pp0_stage6_iter11);
SC_METHOD(thread_ap_block_state96_pp0_stage7_iter11);
SC_METHOD(thread_ap_block_state97_pp0_stage0_iter12);
SC_METHOD(thread_ap_block_state98_pp0_stage1_iter12);
SC_METHOD(thread_ap_block_state99_pp0_stage2_iter12);
SC_METHOD(thread_ap_block_state9_pp0_stage0_iter1);
SC_METHOD(thread_ap_done);
sensitive << ( ap_start );
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
SC_METHOD(thread_ap_enable_pp0);
sensitive << ( ap_idle_pp0 );
SC_METHOD(thread_ap_enable_reg_pp0_iter0);
sensitive << ( ap_start );
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0_reg );
SC_METHOD(thread_ap_idle);
sensitive << ( ap_start );
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_idle_pp0 );
SC_METHOD(thread_ap_idle_pp0);
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
SC_METHOD(thread_ap_idle_pp0_0to15);
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
SC_METHOD(thread_ap_idle_pp0_1to16);
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
SC_METHOD(thread_ap_ready);
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
SC_METHOD(thread_ap_reset_idle_pp0);
sensitive << ( ap_start );
sensitive << ( ap_idle_pp0_0to15 );
SC_METHOD(thread_ap_return_0);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln288_fu_4740_p2 );
SC_METHOD(thread_ap_return_1);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln289_reg_7542 );
SC_METHOD(thread_ap_return_2);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln290_reg_7547 );
SC_METHOD(thread_ap_return_3);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln291_reg_7552 );
SC_METHOD(thread_ap_return_4);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln292_fu_4749_p2 );
SC_METHOD(thread_ap_return_5);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln293_reg_7557 );
SC_METHOD(thread_ap_return_6);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln294_reg_7562 );
SC_METHOD(thread_ap_return_7);
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_ce );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( add_ln295_reg_7567 );
SC_METHOD(thread_data_0_address0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_0_address1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_0_ce0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_0_ce1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_1_address0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_1_address1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_1_ce0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_1_ce1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_2_address0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_2_address1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_2_ce0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_2_ce1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_3_address0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_3_address1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_data_3_ce0);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_data_3_ce1);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_block_pp0_stage7_11001 );
sensitive << ( ap_ce );
sensitive << ( ap_block_pp0_stage0_11001 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_block_pp0_stage3_11001 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_block_pp0_stage5_11001 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_block_pp0_stage4_11001 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_block_pp0_stage6_11001 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_block_pp0_stage2_11001 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_block_pp0_stage1_11001 );
SC_METHOD(thread_grp_CH_fu_1137_rtl_key_r);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( rtl_key_r );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_port_reg_rtl_key_r );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1137_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_4_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_reg_5017 );
sensitive << ( add_ln280_1_reg_5164 );
sensitive << ( add_ln280_2_reg_5314 );
sensitive << ( add_ln280_3_reg_5435 );
sensitive << ( add_ln280_32_reg_6815 );
sensitive << ( add_ln280_33_reg_6838 );
sensitive << ( add_ln280_35_reg_6884 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1137_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_5_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ctx_state_4_read_1_reg_4810 );
sensitive << ( add_ln280_reg_5017 );
sensitive << ( add_ln280_1_reg_5164 );
sensitive << ( add_ln280_2_reg_5314 );
sensitive << ( add_ln280_31_reg_6792 );
sensitive << ( add_ln280_32_reg_6815 );
sensitive << ( add_ln280_34_reg_6861 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1137_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_6_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ctx_state_5_read_1_reg_4803 );
sensitive << ( ctx_state_4_read_1_reg_4810 );
sensitive << ( add_ln280_reg_5017 );
sensitive << ( add_ln280_1_reg_5164 );
sensitive << ( add_ln280_30_reg_6769 );
sensitive << ( add_ln280_31_reg_6792 );
sensitive << ( add_ln280_33_reg_6838 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1149_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_4_reg_5541 );
sensitive << ( add_ln280_5_reg_5632 );
sensitive << ( add_ln280_6_reg_5723 );
sensitive << ( add_ln280_7_reg_5814 );
sensitive << ( add_ln280_34_reg_6861 );
sensitive << ( add_ln280_36_reg_6907 );
sensitive << ( add_ln280_37_reg_6930 );
sensitive << ( add_ln280_39_reg_6976 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1149_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_3_reg_5435 );
sensitive << ( add_ln280_4_reg_5541 );
sensitive << ( add_ln280_5_reg_5632 );
sensitive << ( add_ln280_6_reg_5723 );
sensitive << ( add_ln280_33_reg_6838 );
sensitive << ( add_ln280_35_reg_6884 );
sensitive << ( add_ln280_36_reg_6907 );
sensitive << ( add_ln280_38_reg_6953 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1149_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_2_reg_5314 );
sensitive << ( add_ln280_3_reg_5435 );
sensitive << ( add_ln280_4_reg_5541 );
sensitive << ( add_ln280_5_reg_5632 );
sensitive << ( add_ln280_32_reg_6815 );
sensitive << ( add_ln280_34_reg_6861 );
sensitive << ( add_ln280_35_reg_6884 );
sensitive << ( add_ln280_37_reg_6930 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1158_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_8_reg_5905 );
sensitive << ( add_ln280_9_reg_5996 );
sensitive << ( add_ln280_10_reg_6087 );
sensitive << ( add_ln280_11_reg_6178 );
sensitive << ( add_ln280_38_reg_6953 );
sensitive << ( add_ln280_40_reg_6999 );
sensitive << ( add_ln280_41_reg_7022 );
sensitive << ( add_ln280_43_reg_7068 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1158_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_7_reg_5814 );
sensitive << ( add_ln280_8_reg_5905 );
sensitive << ( add_ln280_9_reg_5996 );
sensitive << ( add_ln280_10_reg_6087 );
sensitive << ( add_ln280_37_reg_6930 );
sensitive << ( add_ln280_39_reg_6976 );
sensitive << ( add_ln280_40_reg_6999 );
sensitive << ( add_ln280_42_reg_7045 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1158_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_6_reg_5723 );
sensitive << ( add_ln280_7_reg_5814 );
sensitive << ( add_ln280_8_reg_5905 );
sensitive << ( add_ln280_9_reg_5996 );
sensitive << ( add_ln280_36_reg_6907 );
sensitive << ( add_ln280_38_reg_6953 );
sensitive << ( add_ln280_39_reg_6976 );
sensitive << ( add_ln280_41_reg_7022 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1167_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_12_reg_6250 );
sensitive << ( add_ln280_13_reg_6317 );
sensitive << ( add_ln280_14_reg_6381 );
sensitive << ( add_ln280_15_reg_6419 );
sensitive << ( add_ln280_42_reg_7045 );
sensitive << ( add_ln280_44_reg_7091 );
sensitive << ( add_ln280_45_reg_7114 );
sensitive << ( add_ln280_47_reg_7165 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1167_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_11_reg_6178 );
sensitive << ( add_ln280_12_reg_6250 );
sensitive << ( add_ln280_13_reg_6317 );
sensitive << ( add_ln280_14_reg_6381 );
sensitive << ( add_ln280_41_reg_7022 );
sensitive << ( add_ln280_43_reg_7068 );
sensitive << ( add_ln280_44_reg_7091 );
sensitive << ( add_ln280_46_reg_7137 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1167_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_10_reg_6087 );
sensitive << ( add_ln280_11_reg_6178 );
sensitive << ( add_ln280_12_reg_6250 );
sensitive << ( add_ln280_13_reg_6317 );
sensitive << ( add_ln280_40_reg_6999 );
sensitive << ( add_ln280_42_reg_7045 );
sensitive << ( add_ln280_43_reg_7068 );
sensitive << ( add_ln280_45_reg_7114 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1176_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_16_reg_6447 );
sensitive << ( add_ln280_17_reg_6470 );
sensitive << ( add_ln280_18_reg_6493 );
sensitive << ( add_ln280_19_reg_6516 );
sensitive << ( add_ln280_46_reg_7137 );
sensitive << ( add_ln280_48_reg_7188 );
sensitive << ( add_ln280_49_reg_7211 );
sensitive << ( add_ln280_51_reg_7257 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1176_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_15_reg_6419 );
sensitive << ( add_ln280_16_reg_6447 );
sensitive << ( add_ln280_17_reg_6470 );
sensitive << ( add_ln280_18_reg_6493 );
sensitive << ( add_ln280_45_reg_7114 );
sensitive << ( add_ln280_47_reg_7165 );
sensitive << ( add_ln280_48_reg_7188 );
sensitive << ( add_ln280_50_reg_7234 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1176_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_14_reg_6381 );
sensitive << ( add_ln280_15_reg_6419 );
sensitive << ( add_ln280_16_reg_6447 );
sensitive << ( add_ln280_17_reg_6470 );
sensitive << ( add_ln280_44_reg_7091 );
sensitive << ( add_ln280_46_reg_7137 );
sensitive << ( add_ln280_47_reg_7165 );
sensitive << ( add_ln280_49_reg_7211 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1185_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_20_reg_6539 );
sensitive << ( add_ln280_21_reg_6562 );
sensitive << ( add_ln280_22_reg_6585 );
sensitive << ( add_ln280_23_reg_6608 );
sensitive << ( add_ln280_50_reg_7234 );
sensitive << ( add_ln280_52_reg_7280 );
sensitive << ( add_ln280_53_reg_7303 );
sensitive << ( add_ln280_55_reg_7349 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1185_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_19_reg_6516 );
sensitive << ( add_ln280_20_reg_6539 );
sensitive << ( add_ln280_21_reg_6562 );
sensitive << ( add_ln280_22_reg_6585 );
sensitive << ( add_ln280_49_reg_7211 );
sensitive << ( add_ln280_51_reg_7257 );
sensitive << ( add_ln280_52_reg_7280 );
sensitive << ( add_ln280_54_reg_7326 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1185_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_18_reg_6493 );
sensitive << ( add_ln280_19_reg_6516 );
sensitive << ( add_ln280_20_reg_6539 );
sensitive << ( add_ln280_21_reg_6562 );
sensitive << ( add_ln280_48_reg_7188 );
sensitive << ( add_ln280_50_reg_7234 );
sensitive << ( add_ln280_51_reg_7257 );
sensitive << ( add_ln280_53_reg_7303 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1194_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_24_reg_6631 );
sensitive << ( add_ln280_25_reg_6654 );
sensitive << ( add_ln280_26_reg_6677 );
sensitive << ( add_ln280_27_reg_6700 );
sensitive << ( add_ln280_54_reg_7326 );
sensitive << ( add_ln280_56_reg_7372 );
sensitive << ( add_ln280_57_reg_7395 );
sensitive << ( add_ln280_59_reg_7441 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1194_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_23_reg_6608 );
sensitive << ( add_ln280_24_reg_6631 );
sensitive << ( add_ln280_25_reg_6654 );
sensitive << ( add_ln280_26_reg_6677 );
sensitive << ( add_ln280_53_reg_7303 );
sensitive << ( add_ln280_55_reg_7349 );
sensitive << ( add_ln280_56_reg_7372 );
sensitive << ( add_ln280_58_reg_7418 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1194_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_22_reg_6585 );
sensitive << ( add_ln280_23_reg_6608 );
sensitive << ( add_ln280_24_reg_6631 );
sensitive << ( add_ln280_25_reg_6654 );
sensitive << ( add_ln280_52_reg_7280 );
sensitive << ( add_ln280_54_reg_7326 );
sensitive << ( add_ln280_55_reg_7349 );
sensitive << ( add_ln280_57_reg_7395 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1203_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_28_reg_6723 );
sensitive << ( add_ln280_29_reg_6746 );
sensitive << ( add_ln280_30_reg_6769 );
sensitive << ( add_ln280_31_reg_6792 );
sensitive << ( add_ln280_58_reg_7418 );
sensitive << ( add_ln280_60_reg_7464 );
sensitive << ( add_ln280_61_reg_7487 );
sensitive << ( add_ln280_62_reg_7513 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1203_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_27_reg_6700 );
sensitive << ( add_ln280_28_reg_6723 );
sensitive << ( add_ln280_29_reg_6746 );
sensitive << ( add_ln280_30_reg_6769 );
sensitive << ( add_ln280_57_reg_7395 );
sensitive << ( add_ln280_59_reg_7441 );
sensitive << ( add_ln280_60_reg_7464 );
sensitive << ( add_ln280_61_reg_7487 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_CH_fu_1203_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_26_reg_6677 );
sensitive << ( add_ln280_27_reg_6700 );
sensitive << ( add_ln280_28_reg_6723 );
sensitive << ( add_ln280_29_reg_6746 );
sensitive << ( add_ln280_56_reg_7372 );
sensitive << ( add_ln280_58_reg_7418 );
sensitive << ( add_ln280_59_reg_7441 );
sensitive << ( add_ln280_60_reg_7464 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1004_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_4_reg_5550 );
sensitive << ( add_ln284_5_reg_5641 );
sensitive << ( add_ln284_6_reg_5732 );
sensitive << ( add_ln284_7_reg_5823 );
sensitive << ( add_ln284_34_reg_6870 );
sensitive << ( add_ln284_36_reg_6916 );
sensitive << ( add_ln284_37_reg_6939 );
sensitive << ( add_ln284_39_reg_6985 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1011_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_8_reg_5914 );
sensitive << ( add_ln284_9_reg_6005 );
sensitive << ( add_ln284_10_reg_6096 );
sensitive << ( add_ln284_11_reg_6187 );
sensitive << ( add_ln284_38_reg_6962 );
sensitive << ( add_ln284_40_reg_7008 );
sensitive << ( add_ln284_41_reg_7031 );
sensitive << ( add_ln284_43_reg_7077 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1018_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_12_reg_6259 );
sensitive << ( add_ln284_13_reg_6326 );
sensitive << ( add_ln284_14_reg_6390 );
sensitive << ( add_ln284_15_reg_6428 );
sensitive << ( add_ln284_42_reg_7054 );
sensitive << ( add_ln284_44_reg_7100 );
sensitive << ( add_ln284_45_reg_7123 );
sensitive << ( add_ln284_47_reg_7174 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1025_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_16_reg_6456 );
sensitive << ( add_ln284_17_reg_6479 );
sensitive << ( add_ln284_18_reg_6502 );
sensitive << ( add_ln284_19_reg_6525 );
sensitive << ( add_ln284_46_reg_7146 );
sensitive << ( add_ln284_48_reg_7197 );
sensitive << ( add_ln284_49_reg_7220 );
sensitive << ( add_ln284_51_reg_7266 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1032_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_20_reg_6548 );
sensitive << ( add_ln284_21_reg_6571 );
sensitive << ( add_ln284_22_reg_6594 );
sensitive << ( add_ln284_23_reg_6617 );
sensitive << ( add_ln284_50_reg_7243 );
sensitive << ( add_ln284_52_reg_7289 );
sensitive << ( add_ln284_53_reg_7312 );
sensitive << ( add_ln284_55_reg_7358 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1039_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_24_reg_6640 );
sensitive << ( add_ln284_25_reg_6663 );
sensitive << ( add_ln284_26_reg_6686 );
sensitive << ( add_ln284_27_reg_6709 );
sensitive << ( add_ln284_54_reg_7335 );
sensitive << ( add_ln284_56_reg_7381 );
sensitive << ( add_ln284_57_reg_7404 );
sensitive << ( add_ln284_59_reg_7450 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_1046_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_28_reg_6732 );
sensitive << ( add_ln284_29_reg_6755 );
sensitive << ( add_ln284_30_reg_6778 );
sensitive << ( add_ln284_31_reg_6801 );
sensitive << ( add_ln284_58_reg_7427 );
sensitive << ( add_ln284_60_reg_7473 );
sensitive << ( add_ln284_61_reg_7495 );
sensitive << ( add_ln284_62_reg_7520 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_996_rtl_key_r);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( rtl_key_r );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_port_reg_rtl_key_r );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP0_fu_996_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_0_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_reg_5026 );
sensitive << ( add_ln284_1_reg_5173 );
sensitive << ( add_ln284_2_reg_5323 );
sensitive << ( add_ln284_3_reg_5444 );
sensitive << ( add_ln284_32_reg_6824 );
sensitive << ( add_ln284_33_reg_6847 );
sensitive << ( add_ln284_35_reg_6893 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_939_rtl_key_r);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( rtl_key_r );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_port_reg_rtl_key_r );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_939_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_4_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_reg_5017 );
sensitive << ( add_ln280_1_reg_5164 );
sensitive << ( add_ln280_2_reg_5314 );
sensitive << ( add_ln280_3_reg_5435 );
sensitive << ( add_ln280_32_reg_6815 );
sensitive << ( add_ln280_33_reg_6838 );
sensitive << ( add_ln280_35_reg_6884 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_947_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_4_reg_5541 );
sensitive << ( add_ln280_5_reg_5632 );
sensitive << ( add_ln280_6_reg_5723 );
sensitive << ( add_ln280_7_reg_5814 );
sensitive << ( add_ln280_34_reg_6861 );
sensitive << ( add_ln280_36_reg_6907 );
sensitive << ( add_ln280_37_reg_6930 );
sensitive << ( add_ln280_39_reg_6976 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_954_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_8_reg_5905 );
sensitive << ( add_ln280_9_reg_5996 );
sensitive << ( add_ln280_10_reg_6087 );
sensitive << ( add_ln280_11_reg_6178 );
sensitive << ( add_ln280_38_reg_6953 );
sensitive << ( add_ln280_40_reg_6999 );
sensitive << ( add_ln280_41_reg_7022 );
sensitive << ( add_ln280_43_reg_7068 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_961_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_12_reg_6250 );
sensitive << ( add_ln280_13_reg_6317 );
sensitive << ( add_ln280_14_reg_6381 );
sensitive << ( add_ln280_15_reg_6419 );
sensitive << ( add_ln280_42_reg_7045 );
sensitive << ( add_ln280_44_reg_7091 );
sensitive << ( add_ln280_45_reg_7114 );
sensitive << ( add_ln280_47_reg_7165 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_968_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_16_reg_6447 );
sensitive << ( add_ln280_17_reg_6470 );
sensitive << ( add_ln280_18_reg_6493 );
sensitive << ( add_ln280_19_reg_6516 );
sensitive << ( add_ln280_46_reg_7137 );
sensitive << ( add_ln280_48_reg_7188 );
sensitive << ( add_ln280_49_reg_7211 );
sensitive << ( add_ln280_51_reg_7257 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_975_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_20_reg_6539 );
sensitive << ( add_ln280_21_reg_6562 );
sensitive << ( add_ln280_22_reg_6585 );
sensitive << ( add_ln280_23_reg_6608 );
sensitive << ( add_ln280_50_reg_7234 );
sensitive << ( add_ln280_52_reg_7280 );
sensitive << ( add_ln280_53_reg_7303 );
sensitive << ( add_ln280_55_reg_7349 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_982_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_24_reg_6631 );
sensitive << ( add_ln280_25_reg_6654 );
sensitive << ( add_ln280_26_reg_6677 );
sensitive << ( add_ln280_27_reg_6700 );
sensitive << ( add_ln280_54_reg_7326 );
sensitive << ( add_ln280_56_reg_7372 );
sensitive << ( add_ln280_57_reg_7395 );
sensitive << ( add_ln280_59_reg_7441 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_EP1_fu_989_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln280_28_reg_6723 );
sensitive << ( add_ln280_29_reg_6746 );
sensitive << ( add_ln280_30_reg_6769 );
sensitive << ( add_ln280_31_reg_6792 );
sensitive << ( add_ln280_58_reg_7418 );
sensitive << ( add_ln280_60_reg_7464 );
sensitive << ( add_ln280_61_reg_7487 );
sensitive << ( add_ln280_62_reg_7513 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_864_rtl_key_r);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( rtl_key_r );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ap_port_reg_rtl_key_r );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_864_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_0_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_reg_5026 );
sensitive << ( add_ln284_1_reg_5173 );
sensitive << ( add_ln284_2_reg_5323 );
sensitive << ( add_ln284_3_reg_5444 );
sensitive << ( add_ln284_32_reg_6824 );
sensitive << ( add_ln284_33_reg_6847 );
sensitive << ( add_ln284_35_reg_6893 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_864_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_1_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ctx_state_0_read_1_reg_4831 );
sensitive << ( add_ln284_reg_5026 );
sensitive << ( add_ln284_1_reg_5173 );
sensitive << ( add_ln284_2_reg_5323 );
sensitive << ( add_ln284_31_reg_6801 );
sensitive << ( add_ln284_32_reg_6824 );
sensitive << ( add_ln284_34_reg_6870 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_864_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ctx_state_2_read );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( ctx_state_1_read_1_reg_4824 );
sensitive << ( ctx_state_0_read_1_reg_4831 );
sensitive << ( add_ln284_reg_5026 );
sensitive << ( add_ln284_1_reg_5173 );
sensitive << ( add_ln284_30_reg_6778 );
sensitive << ( add_ln284_31_reg_6801 );
sensitive << ( add_ln284_33_reg_6847 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_876_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_4_reg_5550 );
sensitive << ( add_ln284_5_reg_5641 );
sensitive << ( add_ln284_6_reg_5732 );
sensitive << ( add_ln284_7_reg_5823 );
sensitive << ( add_ln284_34_reg_6870 );
sensitive << ( add_ln284_36_reg_6916 );
sensitive << ( add_ln284_37_reg_6939 );
sensitive << ( add_ln284_39_reg_6985 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_876_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_3_reg_5444 );
sensitive << ( add_ln284_4_reg_5550 );
sensitive << ( add_ln284_5_reg_5641 );
sensitive << ( add_ln284_6_reg_5732 );
sensitive << ( add_ln284_33_reg_6847 );
sensitive << ( add_ln284_35_reg_6893 );
sensitive << ( add_ln284_36_reg_6916 );
sensitive << ( add_ln284_38_reg_6962 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_876_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter9 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_2_reg_5323 );
sensitive << ( add_ln284_3_reg_5444 );
sensitive << ( add_ln284_4_reg_5550 );
sensitive << ( add_ln284_5_reg_5641 );
sensitive << ( add_ln284_32_reg_6824 );
sensitive << ( add_ln284_34_reg_6870 );
sensitive << ( add_ln284_35_reg_6893 );
sensitive << ( add_ln284_37_reg_6939 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_885_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_8_reg_5914 );
sensitive << ( add_ln284_9_reg_6005 );
sensitive << ( add_ln284_10_reg_6096 );
sensitive << ( add_ln284_11_reg_6187 );
sensitive << ( add_ln284_38_reg_6962 );
sensitive << ( add_ln284_40_reg_7008 );
sensitive << ( add_ln284_41_reg_7031 );
sensitive << ( add_ln284_43_reg_7077 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_885_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_7_reg_5823 );
sensitive << ( add_ln284_8_reg_5914 );
sensitive << ( add_ln284_9_reg_6005 );
sensitive << ( add_ln284_10_reg_6096 );
sensitive << ( add_ln284_37_reg_6939 );
sensitive << ( add_ln284_39_reg_6985 );
sensitive << ( add_ln284_40_reg_7008 );
sensitive << ( add_ln284_42_reg_7054 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_885_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter10 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_6_reg_5732 );
sensitive << ( add_ln284_7_reg_5823 );
sensitive << ( add_ln284_8_reg_5914 );
sensitive << ( add_ln284_9_reg_6005 );
sensitive << ( add_ln284_36_reg_6916 );
sensitive << ( add_ln284_38_reg_6962 );
sensitive << ( add_ln284_39_reg_6985 );
sensitive << ( add_ln284_41_reg_7031 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_894_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_12_reg_6259 );
sensitive << ( add_ln284_13_reg_6326 );
sensitive << ( add_ln284_14_reg_6390 );
sensitive << ( add_ln284_15_reg_6428 );
sensitive << ( add_ln284_42_reg_7054 );
sensitive << ( add_ln284_44_reg_7100 );
sensitive << ( add_ln284_45_reg_7123 );
sensitive << ( add_ln284_47_reg_7174 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_894_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_11_reg_6187 );
sensitive << ( add_ln284_12_reg_6259 );
sensitive << ( add_ln284_13_reg_6326 );
sensitive << ( add_ln284_14_reg_6390 );
sensitive << ( add_ln284_41_reg_7031 );
sensitive << ( add_ln284_43_reg_7077 );
sensitive << ( add_ln284_44_reg_7100 );
sensitive << ( add_ln284_46_reg_7146 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_894_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter11 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_10_reg_6096 );
sensitive << ( add_ln284_11_reg_6187 );
sensitive << ( add_ln284_12_reg_6259 );
sensitive << ( add_ln284_13_reg_6326 );
sensitive << ( add_ln284_40_reg_7008 );
sensitive << ( add_ln284_42_reg_7054 );
sensitive << ( add_ln284_43_reg_7077 );
sensitive << ( add_ln284_45_reg_7123 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_903_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_16_reg_6456 );
sensitive << ( add_ln284_17_reg_6479 );
sensitive << ( add_ln284_18_reg_6502 );
sensitive << ( add_ln284_19_reg_6525 );
sensitive << ( add_ln284_46_reg_7146 );
sensitive << ( add_ln284_48_reg_7197 );
sensitive << ( add_ln284_49_reg_7220 );
sensitive << ( add_ln284_51_reg_7266 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_903_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_15_reg_6428 );
sensitive << ( add_ln284_16_reg_6456 );
sensitive << ( add_ln284_17_reg_6479 );
sensitive << ( add_ln284_18_reg_6502 );
sensitive << ( add_ln284_45_reg_7123 );
sensitive << ( add_ln284_47_reg_7174 );
sensitive << ( add_ln284_48_reg_7197 );
sensitive << ( add_ln284_50_reg_7243 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_903_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter4 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter12 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_14_reg_6390 );
sensitive << ( add_ln284_15_reg_6428 );
sensitive << ( add_ln284_16_reg_6456 );
sensitive << ( add_ln284_17_reg_6479 );
sensitive << ( add_ln284_44_reg_7100 );
sensitive << ( add_ln284_46_reg_7146 );
sensitive << ( add_ln284_47_reg_7174 );
sensitive << ( add_ln284_49_reg_7220 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_912_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_20_reg_6548 );
sensitive << ( add_ln284_21_reg_6571 );
sensitive << ( add_ln284_22_reg_6594 );
sensitive << ( add_ln284_23_reg_6617 );
sensitive << ( add_ln284_50_reg_7243 );
sensitive << ( add_ln284_52_reg_7289 );
sensitive << ( add_ln284_53_reg_7312 );
sensitive << ( add_ln284_55_reg_7358 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_912_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_19_reg_6525 );
sensitive << ( add_ln284_20_reg_6548 );
sensitive << ( add_ln284_21_reg_6571 );
sensitive << ( add_ln284_22_reg_6594 );
sensitive << ( add_ln284_49_reg_7220 );
sensitive << ( add_ln284_51_reg_7266 );
sensitive << ( add_ln284_52_reg_7289 );
sensitive << ( add_ln284_54_reg_7335 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_912_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter5 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter13 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_18_reg_6502 );
sensitive << ( add_ln284_19_reg_6525 );
sensitive << ( add_ln284_20_reg_6548 );
sensitive << ( add_ln284_21_reg_6571 );
sensitive << ( add_ln284_48_reg_7197 );
sensitive << ( add_ln284_50_reg_7243 );
sensitive << ( add_ln284_51_reg_7266 );
sensitive << ( add_ln284_53_reg_7312 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_921_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_24_reg_6640 );
sensitive << ( add_ln284_25_reg_6663 );
sensitive << ( add_ln284_26_reg_6686 );
sensitive << ( add_ln284_27_reg_6709 );
sensitive << ( add_ln284_54_reg_7335 );
sensitive << ( add_ln284_56_reg_7381 );
sensitive << ( add_ln284_57_reg_7404 );
sensitive << ( add_ln284_59_reg_7450 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_921_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_23_reg_6617 );
sensitive << ( add_ln284_24_reg_6640 );
sensitive << ( add_ln284_25_reg_6663 );
sensitive << ( add_ln284_26_reg_6686 );
sensitive << ( add_ln284_53_reg_7312 );
sensitive << ( add_ln284_55_reg_7358 );
sensitive << ( add_ln284_56_reg_7381 );
sensitive << ( add_ln284_58_reg_7427 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_921_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter6 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter14 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_22_reg_6594 );
sensitive << ( add_ln284_23_reg_6617 );
sensitive << ( add_ln284_24_reg_6640 );
sensitive << ( add_ln284_25_reg_6663 );
sensitive << ( add_ln284_52_reg_7289 );
sensitive << ( add_ln284_54_reg_7335 );
sensitive << ( add_ln284_55_reg_7358 );
sensitive << ( add_ln284_57_reg_7404 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_930_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_28_reg_6732 );
sensitive << ( add_ln284_29_reg_6755 );
sensitive << ( add_ln284_30_reg_6778 );
sensitive << ( add_ln284_31_reg_6801 );
sensitive << ( add_ln284_58_reg_7427 );
sensitive << ( add_ln284_60_reg_7473 );
sensitive << ( add_ln284_61_reg_7495 );
sensitive << ( add_ln284_62_reg_7520 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_930_y);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_27_reg_6709 );
sensitive << ( add_ln284_28_reg_6732 );
sensitive << ( add_ln284_29_reg_6755 );
sensitive << ( add_ln284_30_reg_6778 );
sensitive << ( add_ln284_57_reg_7404 );
sensitive << ( add_ln284_59_reg_7450 );
sensitive << ( add_ln284_60_reg_7473 );
sensitive << ( add_ln284_61_reg_7495 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_MAJ_fu_930_z);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter7 );
sensitive << ( ap_enable_reg_pp0_iter8 );
sensitive << ( ap_enable_reg_pp0_iter15 );
sensitive << ( ap_enable_reg_pp0_iter16 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( add_ln284_26_reg_6686 );
sensitive << ( add_ln284_27_reg_6709 );
sensitive << ( add_ln284_28_reg_6732 );
sensitive << ( add_ln284_29_reg_6755 );
sensitive << ( add_ln284_56_reg_7381 );
sensitive << ( add_ln284_58_reg_7427 );
sensitive << ( add_ln284_59_reg_7450 );
sensitive << ( add_ln284_60_reg_7473 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1095_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_1_fu_1344_p5 );
sensitive << ( m_2_fu_1368_p5 );
sensitive << ( m_4_fu_1423_p5 );
sensitive << ( m_6_fu_1460_p5 );
sensitive << ( m_8_fu_1513_p5 );
sensitive << ( m_10_fu_1549_p5 );
sensitive << ( m_12_fu_1603_p5 );
sensitive << ( m_14_fu_1640_p5 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1102_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_3_fu_1381_p5 );
sensitive << ( m_5_fu_1436_p5 );
sensitive << ( m_7_fu_1473_p5 );
sensitive << ( m_9_fu_1526_p5 );
sensitive << ( m_11_fu_1562_p5 );
sensitive << ( m_13_fu_1616_p5 );
sensitive << ( m_15_fu_1654_p5 );
sensitive << ( m_16_fu_1708_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1109_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_17_fu_1720_p2 );
sensitive << ( m_18_fu_1751_p2 );
sensitive << ( m_20_fu_1807_p2 );
sensitive << ( m_22_fu_1850_p2 );
sensitive << ( m_24_fu_1909_p2 );
sensitive << ( m_26_fu_1951_p2 );
sensitive << ( m_28_fu_2011_p2 );
sensitive << ( m_30_fu_2053_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1116_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_19_fu_1763_p2 );
sensitive << ( m_21_fu_1819_p2 );
sensitive << ( m_23_fu_1862_p2 );
sensitive << ( m_25_fu_1921_p2 );
sensitive << ( m_27_fu_1963_p2 );
sensitive << ( m_29_fu_2023_p2 );
sensitive << ( m_31_fu_2065_p2 );
sensitive << ( m_32_fu_2113_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1123_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_33_fu_2125_p2 );
sensitive << ( m_34_fu_2156_p2 );
sensitive << ( m_36_fu_2215_p2 );
sensitive << ( m_38_fu_2258_p2 );
sensitive << ( m_40_fu_2317_p2 );
sensitive << ( m_42_fu_2360_p2 );
sensitive << ( m_44_fu_2419_p2 );
sensitive << ( m_46_fu_2462_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG0_fu_1130_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_35_fu_2168_p2 );
sensitive << ( m_37_fu_2227_p2 );
sensitive << ( m_39_fu_2270_p2 );
sensitive << ( m_41_fu_2329_p2 );
sensitive << ( m_43_fu_2372_p2 );
sensitive << ( m_45_fu_2431_p2 );
sensitive << ( m_47_fu_2474_p2 );
sensitive << ( m_48_fu_2521_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1053_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_14_fu_1640_p5 );
sensitive << ( m_16_fu_1708_p2 );
sensitive << ( m_18_fu_1751_p2 );
sensitive << ( m_20_fu_1807_p2 );
sensitive << ( m_22_fu_1850_p2 );
sensitive << ( m_24_fu_1909_p2 );
sensitive << ( m_26_fu_1951_p2 );
sensitive << ( m_28_fu_2011_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1060_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter1 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_15_fu_1654_p5 );
sensitive << ( m_17_fu_1720_p2 );
sensitive << ( m_19_fu_1763_p2 );
sensitive << ( m_21_fu_1819_p2 );
sensitive << ( m_23_fu_1862_p2 );
sensitive << ( m_25_fu_1921_p2 );
sensitive << ( m_27_fu_1963_p2 );
sensitive << ( m_29_fu_2023_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1067_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_30_fu_2053_p2 );
sensitive << ( m_32_fu_2113_p2 );
sensitive << ( m_34_fu_2156_p2 );
sensitive << ( m_36_fu_2215_p2 );
sensitive << ( m_38_fu_2258_p2 );
sensitive << ( m_40_fu_2317_p2 );
sensitive << ( m_42_fu_2360_p2 );
sensitive << ( m_44_fu_2419_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1074_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter2 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_31_fu_2065_p2 );
sensitive << ( m_33_fu_2125_p2 );
sensitive << ( m_35_fu_2168_p2 );
sensitive << ( m_37_fu_2227_p2 );
sensitive << ( m_39_fu_2270_p2 );
sensitive << ( m_41_fu_2329_p2 );
sensitive << ( m_43_fu_2372_p2 );
sensitive << ( m_45_fu_2431_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1081_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_46_fu_2462_p2 );
sensitive << ( m_48_fu_2521_p2 );
sensitive << ( m_50_fu_2563_p2 );
sensitive << ( m_52_fu_2620_p2 );
sensitive << ( m_54_fu_2660_p2 );
sensitive << ( m_56_fu_2718_p2 );
sensitive << ( m_58_fu_2758_p2 );
sensitive << ( m_60_fu_2816_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_grp_SIG1_fu_1088_x);
sensitive << ( ap_CS_fsm_pp0_stage0 );
sensitive << ( ap_block_pp0_stage0 );
sensitive << ( ap_enable_reg_pp0_iter3 );
sensitive << ( ap_CS_fsm_pp0_stage7 );
sensitive << ( ap_CS_fsm_pp0_stage3 );
sensitive << ( ap_CS_fsm_pp0_stage5 );
sensitive << ( ap_CS_fsm_pp0_stage4 );
sensitive << ( ap_CS_fsm_pp0_stage6 );
sensitive << ( ap_CS_fsm_pp0_stage2 );
sensitive << ( ap_CS_fsm_pp0_stage1 );
sensitive << ( m_47_fu_2474_p2 );
sensitive << ( m_49_fu_2533_p2 );
sensitive << ( m_51_fu_2574_p2 );
sensitive << ( m_53_fu_2631_p2 );
sensitive << ( m_55_fu_2671_p2 );
sensitive << ( m_57_fu_2729_p2 );
sensitive << ( m_59_fu_2769_p2 );
sensitive << ( m_61_fu_2827_p2 );
sensitive << ( ap_block_pp0_stage3 );
sensitive << ( ap_block_pp0_stage5 );
sensitive << ( ap_block_pp0_stage7 );
sensitive << ( ap_block_pp0_stage1 );
sensitive << ( ap_block_pp0_stage4 );
sensitive << ( ap_block_pp0_stage6 );
sensitive << ( ap_block_pp0_stage2 );
SC_METHOD(thread_m_0_fu_1332_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_10_fu_1549_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_11_fu_1562_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_12_fu_1603_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_13_fu_1616_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_14_fu_1640_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_15_fu_1654_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_16_fu_1708_p2);
sensitive << ( add_ln259_1_reg_5415 );
sensitive << ( add_ln259_fu_1703_p2 );
SC_METHOD(thread_m_17_fu_1720_p2);
sensitive << ( add_ln259_4_reg_5420 );
sensitive << ( add_ln259_3_fu_1715_p2 );
SC_METHOD(thread_m_18_fu_1751_p2);
sensitive << ( add_ln259_7_reg_5467 );
sensitive << ( add_ln259_6_fu_1746_p2 );
SC_METHOD(thread_m_19_fu_1763_p2);
sensitive << ( add_ln259_10_reg_5472 );
sensitive << ( add_ln259_9_fu_1758_p2 );
SC_METHOD(thread_m_1_fu_1344_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_20_fu_1807_p2);
sensitive << ( add_ln259_13_reg_5521 );
sensitive << ( add_ln259_12_fu_1802_p2 );
SC_METHOD(thread_m_21_fu_1819_p2);
sensitive << ( add_ln259_16_reg_5526 );
sensitive << ( add_ln259_15_fu_1814_p2 );
SC_METHOD(thread_m_22_fu_1850_p2);
sensitive << ( add_ln259_19_reg_5573 );
sensitive << ( add_ln259_18_fu_1845_p2 );
SC_METHOD(thread_m_23_fu_1862_p2);
sensitive << ( add_ln259_22_reg_5578 );
sensitive << ( add_ln259_21_fu_1857_p2 );
SC_METHOD(thread_m_24_fu_1909_p2);
sensitive << ( add_ln259_25_reg_5612 );
sensitive << ( add_ln259_24_fu_1904_p2 );
SC_METHOD(thread_m_25_fu_1921_p2);
sensitive << ( add_ln259_28_reg_5617 );
sensitive << ( add_ln259_27_fu_1916_p2 );
SC_METHOD(thread_m_26_fu_1951_p2);
sensitive << ( add_ln259_31_reg_5664 );
sensitive << ( add_ln259_30_fu_1946_p2 );
SC_METHOD(thread_m_27_fu_1963_p2);
sensitive << ( add_ln259_34_reg_5669 );
sensitive << ( add_ln259_33_fu_1958_p2 );
SC_METHOD(thread_m_28_fu_2011_p2);
sensitive << ( add_ln259_37_reg_5703 );
sensitive << ( add_ln259_36_fu_2006_p2 );
SC_METHOD(thread_m_29_fu_2023_p2);
sensitive << ( add_ln259_40_reg_5708 );
sensitive << ( add_ln259_39_fu_2018_p2 );
SC_METHOD(thread_m_2_fu_1368_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_30_fu_2053_p2);
sensitive << ( add_ln259_43_reg_5755 );
sensitive << ( add_ln259_42_fu_2048_p2 );
SC_METHOD(thread_m_31_fu_2065_p2);
sensitive << ( add_ln259_46_reg_5760 );
sensitive << ( add_ln259_45_fu_2060_p2 );
SC_METHOD(thread_m_32_fu_2113_p2);
sensitive << ( add_ln259_49_reg_5794 );
sensitive << ( add_ln259_48_fu_2108_p2 );
SC_METHOD(thread_m_33_fu_2125_p2);
sensitive << ( add_ln259_52_reg_5799 );
sensitive << ( add_ln259_51_fu_2120_p2 );
SC_METHOD(thread_m_34_fu_2156_p2);
sensitive << ( add_ln259_55_reg_5846 );
sensitive << ( add_ln259_54_fu_2151_p2 );
SC_METHOD(thread_m_35_fu_2168_p2);
sensitive << ( add_ln259_58_reg_5851 );
sensitive << ( add_ln259_57_fu_2163_p2 );
SC_METHOD(thread_m_36_fu_2215_p2);
sensitive << ( add_ln259_61_reg_5885 );
sensitive << ( add_ln259_60_fu_2210_p2 );
SC_METHOD(thread_m_37_fu_2227_p2);
sensitive << ( add_ln259_64_reg_5890 );
sensitive << ( add_ln259_63_fu_2222_p2 );
SC_METHOD(thread_m_38_fu_2258_p2);
sensitive << ( add_ln259_67_reg_5937 );
sensitive << ( add_ln259_66_fu_2253_p2 );
SC_METHOD(thread_m_39_fu_2270_p2);
sensitive << ( add_ln259_70_reg_5942 );
sensitive << ( add_ln259_69_fu_2265_p2 );
SC_METHOD(thread_m_3_fu_1381_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_40_fu_2317_p2);
sensitive << ( add_ln259_73_reg_5976 );
sensitive << ( add_ln259_72_fu_2312_p2 );
SC_METHOD(thread_m_41_fu_2329_p2);
sensitive << ( add_ln259_76_reg_5981 );
sensitive << ( add_ln259_75_fu_2324_p2 );
SC_METHOD(thread_m_42_fu_2360_p2);
sensitive << ( add_ln259_79_reg_6028 );
sensitive << ( add_ln259_78_fu_2355_p2 );
SC_METHOD(thread_m_43_fu_2372_p2);
sensitive << ( add_ln259_82_reg_6033 );
sensitive << ( add_ln259_81_fu_2367_p2 );
SC_METHOD(thread_m_44_fu_2419_p2);
sensitive << ( add_ln259_85_reg_6067 );
sensitive << ( add_ln259_84_fu_2414_p2 );
SC_METHOD(thread_m_45_fu_2431_p2);
sensitive << ( add_ln259_88_reg_6072 );
sensitive << ( add_ln259_87_fu_2426_p2 );
SC_METHOD(thread_m_46_fu_2462_p2);
sensitive << ( add_ln259_91_reg_6119 );
sensitive << ( add_ln259_90_fu_2457_p2 );
SC_METHOD(thread_m_47_fu_2474_p2);
sensitive << ( add_ln259_94_reg_6124 );
sensitive << ( add_ln259_93_fu_2469_p2 );
SC_METHOD(thread_m_48_fu_2521_p2);
sensitive << ( add_ln259_97_reg_6158 );
sensitive << ( add_ln259_96_fu_2516_p2 );
SC_METHOD(thread_m_49_fu_2533_p2);
sensitive << ( add_ln259_100_reg_6163 );
sensitive << ( add_ln259_99_fu_2528_p2 );
SC_METHOD(thread_m_4_fu_1423_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_50_fu_2563_p2);
sensitive << ( add_ln259_103_reg_6208 );
sensitive << ( add_ln259_102_fu_2558_p2 );
SC_METHOD(thread_m_51_fu_2574_p2);
sensitive << ( add_ln259_106_reg_6213 );
sensitive << ( add_ln259_105_fu_2569_p2 );
SC_METHOD(thread_m_52_fu_2620_p2);
sensitive << ( add_ln259_109_reg_6240 );
sensitive << ( add_ln259_108_fu_2615_p2 );
SC_METHOD(thread_m_53_fu_2631_p2);
sensitive << ( add_ln259_112_reg_6245 );
sensitive << ( add_ln259_111_fu_2626_p2 );
SC_METHOD(thread_m_54_fu_2660_p2);
sensitive << ( add_ln259_115_reg_6280 );
sensitive << ( add_ln259_114_fu_2655_p2 );
SC_METHOD(thread_m_55_fu_2671_p2);
sensitive << ( add_ln259_118_reg_6285 );
sensitive << ( add_ln259_117_fu_2666_p2 );
SC_METHOD(thread_m_56_fu_2718_p2);
sensitive << ( add_ln259_121_reg_6307 );
sensitive << ( add_ln259_120_fu_2713_p2 );
SC_METHOD(thread_m_57_fu_2729_p2);
sensitive << ( add_ln259_124_reg_6312 );
sensitive << ( add_ln259_123_fu_2724_p2 );
SC_METHOD(thread_m_58_fu_2758_p2);
sensitive << ( add_ln259_127_reg_6346 );
sensitive << ( add_ln259_126_fu_2753_p2 );
SC_METHOD(thread_m_59_fu_2769_p2);
sensitive << ( add_ln259_130_reg_6351 );
sensitive << ( add_ln259_129_fu_2764_p2 );
SC_METHOD(thread_m_5_fu_1436_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_60_fu_2816_p2);
sensitive << ( add_ln259_133_reg_6371 );
sensitive << ( add_ln259_132_fu_2811_p2 );
SC_METHOD(thread_m_61_fu_2827_p2);
sensitive << ( add_ln259_136_reg_6376 );
sensitive << ( add_ln259_135_fu_2822_p2 );
SC_METHOD(thread_m_6_fu_1460_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_7_fu_1473_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_m_8_fu_1513_p5);
sensitive << ( data_0_q0 );
sensitive << ( data_1_q0 );
sensitive << ( data_2_q0 );
sensitive << ( data_3_q0 );
SC_METHOD(thread_m_9_fu_1526_p5);
sensitive << ( data_0_q1 );
sensitive << ( data_1_q1 );
sensitive << ( data_2_q1 );
sensitive << ( data_3_q1 );
SC_METHOD(thread_ap_NS_fsm);
sensitive << ( ap_start );
sensitive << ( ap_CS_fsm );
sensitive << ( ap_block_pp0_stage7_subdone );
sensitive << ( ap_block_pp0_stage3_subdone );
sensitive << ( ap_block_pp0_stage0_subdone );
sensitive << ( ap_idle_pp0_1to16 );
sensitive << ( ap_block_pp0_stage1_subdone );
sensitive << ( ap_block_pp0_stage2_subdone );
sensitive << ( ap_reset_idle_pp0 );
sensitive << ( ap_block_pp0_stage4_subdone );
sensitive << ( ap_block_pp0_stage5_subdone );
sensitive << ( ap_block_pp0_stage6_subdone );
ap_CS_fsm = "00000001";
ap_enable_reg_pp0_iter1 = SC_LOGIC_0;
ap_enable_reg_pp0_iter2 = SC_LOGIC_0;
ap_enable_reg_pp0_iter3 = SC_LOGIC_0;
ap_enable_reg_pp0_iter4 = SC_LOGIC_0;
ap_enable_reg_pp0_iter5 = SC_LOGIC_0;
ap_enable_reg_pp0_iter6 = SC_LOGIC_0;
ap_enable_reg_pp0_iter7 = SC_LOGIC_0;
ap_enable_reg_pp0_iter8 = SC_LOGIC_0;
ap_enable_reg_pp0_iter9 = SC_LOGIC_0;
ap_enable_reg_pp0_iter10 = SC_LOGIC_0;
ap_enable_reg_pp0_iter11 = SC_LOGIC_0;
ap_enable_reg_pp0_iter12 = SC_LOGIC_0;
ap_enable_reg_pp0_iter13 = SC_LOGIC_0;
ap_enable_reg_pp0_iter14 = SC_LOGIC_0;
ap_enable_reg_pp0_iter15 = SC_LOGIC_0;
ap_enable_reg_pp0_iter16 = SC_LOGIC_0;
ap_enable_reg_pp0_iter0_reg = SC_LOGIC_0;
static int apTFileNum = 0;
stringstream apTFilenSS;
apTFilenSS << "sha256_transform_sc_trace_" << apTFileNum ++;
string apTFn = apTFilenSS.str();
mVcdFile = sc_create_vcd_trace_file(apTFn.c_str());
mVcdFile->set_time_unit(1, SC_PS);
if (1) {
#ifdef __HLS_TRACE_LEVEL_PORT_HIER__
sc_trace(mVcdFile, ap_clk, "(port)ap_clk");
sc_trace(mVcdFile, ap_rst, "(port)ap_rst");
sc_trace(mVcdFile, ap_start, "(port)ap_start");
sc_trace(mVcdFile, ap_done, "(port)ap_done");
sc_trace(mVcdFile, ap_idle, "(port)ap_idle");
sc_trace(mVcdFile, ap_ready, "(port)ap_ready");
sc_trace(mVcdFile, ap_ce, "(port)ap_ce");
sc_trace(mVcdFile, ctx_state_0_read, "(port)ctx_state_0_read");
sc_trace(mVcdFile, ctx_state_1_read, "(port)ctx_state_1_read");
sc_trace(mVcdFile, ctx_state_2_read, "(port)ctx_state_2_read");
sc_trace(mVcdFile, ctx_state_3_read, "(port)ctx_state_3_read");
sc_trace(mVcdFile, ctx_state_4_read, "(port)ctx_state_4_read");
sc_trace(mVcdFile, ctx_state_5_read, "(port)ctx_state_5_read");
sc_trace(mVcdFile, ctx_state_6_read, "(port)ctx_state_6_read");
sc_trace(mVcdFile, ctx_state_7_read, "(port)ctx_state_7_read");
sc_trace(mVcdFile, data_0_address0, "(port)data_0_address0");
sc_trace(mVcdFile, data_0_ce0, "(port)data_0_ce0");
sc_trace(mVcdFile, data_0_q0, "(port)data_0_q0");
sc_trace(mVcdFile, data_0_address1, "(port)data_0_address1");
sc_trace(mVcdFile, data_0_ce1, "(port)data_0_ce1");
sc_trace(mVcdFile, data_0_q1, "(port)data_0_q1");
sc_trace(mVcdFile, data_1_address0, "(port)data_1_address0");
sc_trace(mVcdFile, data_1_ce0, "(port)data_1_ce0");
sc_trace(mVcdFile, data_1_q0, "(port)data_1_q0");
sc_trace(mVcdFile, data_1_address1, "(port)data_1_address1");
sc_trace(mVcdFile, data_1_ce1, "(port)data_1_ce1");
sc_trace(mVcdFile, data_1_q1, "(port)data_1_q1");
sc_trace(mVcdFile, data_2_address0, "(port)data_2_address0");
sc_trace(mVcdFile, data_2_ce0, "(port)data_2_ce0");
sc_trace(mVcdFile, data_2_q0, "(port)data_2_q0");
sc_trace(mVcdFile, data_2_address1, "(port)data_2_address1");
sc_trace(mVcdFile, data_2_ce1, "(port)data_2_ce1");
sc_trace(mVcdFile, data_2_q1, "(port)data_2_q1");
sc_trace(mVcdFile, data_3_address0, "(port)data_3_address0");
sc_trace(mVcdFile, data_3_ce0, "(port)data_3_ce0");
sc_trace(mVcdFile, data_3_q0, "(port)data_3_q0");
sc_trace(mVcdFile, data_3_address1, "(port)data_3_address1");
sc_trace(mVcdFile, data_3_ce1, "(port)data_3_ce1");
sc_trace(mVcdFile, data_3_q1, "(port)data_3_q1");
sc_trace(mVcdFile, rtl_key_r, "(port)rtl_key_r");
sc_trace(mVcdFile, ap_return_0, "(port)ap_return_0");
sc_trace(mVcdFile, ap_return_1, "(port)ap_return_1");
sc_trace(mVcdFile, ap_return_2, "(port)ap_return_2");
sc_trace(mVcdFile, ap_return_3, "(port)ap_return_3");
sc_trace(mVcdFile, ap_return_4, "(port)ap_return_4");
sc_trace(mVcdFile, ap_return_5, "(port)ap_return_5");
sc_trace(mVcdFile, ap_return_6, "(port)ap_return_6");
sc_trace(mVcdFile, ap_return_7, "(port)ap_return_7");
#endif
#ifdef __HLS_TRACE_LEVEL_INT__
sc_trace(mVcdFile, ap_CS_fsm, "ap_CS_fsm");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage0, "ap_CS_fsm_pp0_stage0");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter0, "ap_enable_reg_pp0_iter0");
sc_trace(mVcdFile, ap_block_pp0_stage0, "ap_block_pp0_stage0");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter1, "ap_enable_reg_pp0_iter1");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter2, "ap_enable_reg_pp0_iter2");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter3, "ap_enable_reg_pp0_iter3");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter4, "ap_enable_reg_pp0_iter4");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter5, "ap_enable_reg_pp0_iter5");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter6, "ap_enable_reg_pp0_iter6");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter7, "ap_enable_reg_pp0_iter7");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter8, "ap_enable_reg_pp0_iter8");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter9, "ap_enable_reg_pp0_iter9");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter10, "ap_enable_reg_pp0_iter10");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter11, "ap_enable_reg_pp0_iter11");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter12, "ap_enable_reg_pp0_iter12");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter13, "ap_enable_reg_pp0_iter13");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter14, "ap_enable_reg_pp0_iter14");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter15, "ap_enable_reg_pp0_iter15");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter16, "ap_enable_reg_pp0_iter16");
sc_trace(mVcdFile, ap_idle_pp0, "ap_idle_pp0");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage7, "ap_CS_fsm_pp0_stage7");
sc_trace(mVcdFile, ap_block_state8_pp0_stage7_iter0, "ap_block_state8_pp0_stage7_iter0");
sc_trace(mVcdFile, ap_block_state16_pp0_stage7_iter1, "ap_block_state16_pp0_stage7_iter1");
sc_trace(mVcdFile, ap_block_state24_pp0_stage7_iter2, "ap_block_state24_pp0_stage7_iter2");
sc_trace(mVcdFile, ap_block_state32_pp0_stage7_iter3, "ap_block_state32_pp0_stage7_iter3");
sc_trace(mVcdFile, ap_block_state40_pp0_stage7_iter4, "ap_block_state40_pp0_stage7_iter4");
sc_trace(mVcdFile, ap_block_state48_pp0_stage7_iter5, "ap_block_state48_pp0_stage7_iter5");
sc_trace(mVcdFile, ap_block_state56_pp0_stage7_iter6, "ap_block_state56_pp0_stage7_iter6");
sc_trace(mVcdFile, ap_block_state64_pp0_stage7_iter7, "ap_block_state64_pp0_stage7_iter7");
sc_trace(mVcdFile, ap_block_state72_pp0_stage7_iter8, "ap_block_state72_pp0_stage7_iter8");
sc_trace(mVcdFile, ap_block_state80_pp0_stage7_iter9, "ap_block_state80_pp0_stage7_iter9");
sc_trace(mVcdFile, ap_block_state88_pp0_stage7_iter10, "ap_block_state88_pp0_stage7_iter10");
sc_trace(mVcdFile, ap_block_state96_pp0_stage7_iter11, "ap_block_state96_pp0_stage7_iter11");
sc_trace(mVcdFile, ap_block_state104_pp0_stage7_iter12, "ap_block_state104_pp0_stage7_iter12");
sc_trace(mVcdFile, ap_block_state112_pp0_stage7_iter13, "ap_block_state112_pp0_stage7_iter13");
sc_trace(mVcdFile, ap_block_state120_pp0_stage7_iter14, "ap_block_state120_pp0_stage7_iter14");
sc_trace(mVcdFile, ap_block_state128_pp0_stage7_iter15, "ap_block_state128_pp0_stage7_iter15");
sc_trace(mVcdFile, ap_block_pp0_stage7_11001, "ap_block_pp0_stage7_11001");
sc_trace(mVcdFile, grp_CH_fu_1137_ap_return, "grp_CH_fu_1137_ap_return");
sc_trace(mVcdFile, reg_1212, "reg_1212");
sc_trace(mVcdFile, ap_block_state1_pp0_stage0_iter0, "ap_block_state1_pp0_stage0_iter0");
sc_trace(mVcdFile, ap_block_state9_pp0_stage0_iter1, "ap_block_state9_pp0_stage0_iter1");
sc_trace(mVcdFile, ap_block_state17_pp0_stage0_iter2, "ap_block_state17_pp0_stage0_iter2");
sc_trace(mVcdFile, ap_block_state25_pp0_stage0_iter3, "ap_block_state25_pp0_stage0_iter3");
sc_trace(mVcdFile, ap_block_state33_pp0_stage0_iter4, "ap_block_state33_pp0_stage0_iter4");
sc_trace(mVcdFile, ap_block_state41_pp0_stage0_iter5, "ap_block_state41_pp0_stage0_iter5");
sc_trace(mVcdFile, ap_block_state49_pp0_stage0_iter6, "ap_block_state49_pp0_stage0_iter6");
sc_trace(mVcdFile, ap_block_state57_pp0_stage0_iter7, "ap_block_state57_pp0_stage0_iter7");
sc_trace(mVcdFile, ap_block_state65_pp0_stage0_iter8, "ap_block_state65_pp0_stage0_iter8");
sc_trace(mVcdFile, ap_block_state73_pp0_stage0_iter9, "ap_block_state73_pp0_stage0_iter9");
sc_trace(mVcdFile, ap_block_state81_pp0_stage0_iter10, "ap_block_state81_pp0_stage0_iter10");
sc_trace(mVcdFile, ap_block_state89_pp0_stage0_iter11, "ap_block_state89_pp0_stage0_iter11");
sc_trace(mVcdFile, ap_block_state97_pp0_stage0_iter12, "ap_block_state97_pp0_stage0_iter12");
sc_trace(mVcdFile, ap_block_state105_pp0_stage0_iter13, "ap_block_state105_pp0_stage0_iter13");
sc_trace(mVcdFile, ap_block_state113_pp0_stage0_iter14, "ap_block_state113_pp0_stage0_iter14");
sc_trace(mVcdFile, ap_block_state121_pp0_stage0_iter15, "ap_block_state121_pp0_stage0_iter15");
sc_trace(mVcdFile, ap_block_state129_pp0_stage0_iter16, "ap_block_state129_pp0_stage0_iter16");
sc_trace(mVcdFile, ap_block_pp0_stage0_11001, "ap_block_pp0_stage0_11001");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage3, "ap_CS_fsm_pp0_stage3");
sc_trace(mVcdFile, ap_block_state4_pp0_stage3_iter0, "ap_block_state4_pp0_stage3_iter0");
sc_trace(mVcdFile, ap_block_state12_pp0_stage3_iter1, "ap_block_state12_pp0_stage3_iter1");
sc_trace(mVcdFile, ap_block_state20_pp0_stage3_iter2, "ap_block_state20_pp0_stage3_iter2");
sc_trace(mVcdFile, ap_block_state28_pp0_stage3_iter3, "ap_block_state28_pp0_stage3_iter3");
sc_trace(mVcdFile, ap_block_state36_pp0_stage3_iter4, "ap_block_state36_pp0_stage3_iter4");
sc_trace(mVcdFile, ap_block_state44_pp0_stage3_iter5, "ap_block_state44_pp0_stage3_iter5");
sc_trace(mVcdFile, ap_block_state52_pp0_stage3_iter6, "ap_block_state52_pp0_stage3_iter6");
sc_trace(mVcdFile, ap_block_state60_pp0_stage3_iter7, "ap_block_state60_pp0_stage3_iter7");
sc_trace(mVcdFile, ap_block_state68_pp0_stage3_iter8, "ap_block_state68_pp0_stage3_iter8");
sc_trace(mVcdFile, ap_block_state76_pp0_stage3_iter9, "ap_block_state76_pp0_stage3_iter9");
sc_trace(mVcdFile, ap_block_state84_pp0_stage3_iter10, "ap_block_state84_pp0_stage3_iter10");
sc_trace(mVcdFile, ap_block_state92_pp0_stage3_iter11, "ap_block_state92_pp0_stage3_iter11");
sc_trace(mVcdFile, ap_block_state100_pp0_stage3_iter12, "ap_block_state100_pp0_stage3_iter12");
sc_trace(mVcdFile, ap_block_state108_pp0_stage3_iter13, "ap_block_state108_pp0_stage3_iter13");
sc_trace(mVcdFile, ap_block_state116_pp0_stage3_iter14, "ap_block_state116_pp0_stage3_iter14");
sc_trace(mVcdFile, ap_block_state124_pp0_stage3_iter15, "ap_block_state124_pp0_stage3_iter15");
sc_trace(mVcdFile, ap_block_state132_pp0_stage3_iter16, "ap_block_state132_pp0_stage3_iter16");
sc_trace(mVcdFile, ap_block_pp0_stage3_11001, "ap_block_pp0_stage3_11001");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage5, "ap_CS_fsm_pp0_stage5");
sc_trace(mVcdFile, ap_block_state6_pp0_stage5_iter0, "ap_block_state6_pp0_stage5_iter0");
sc_trace(mVcdFile, ap_block_state14_pp0_stage5_iter1, "ap_block_state14_pp0_stage5_iter1");
sc_trace(mVcdFile, ap_block_state22_pp0_stage5_iter2, "ap_block_state22_pp0_stage5_iter2");
sc_trace(mVcdFile, ap_block_state30_pp0_stage5_iter3, "ap_block_state30_pp0_stage5_iter3");
sc_trace(mVcdFile, ap_block_state38_pp0_stage5_iter4, "ap_block_state38_pp0_stage5_iter4");
sc_trace(mVcdFile, ap_block_state46_pp0_stage5_iter5, "ap_block_state46_pp0_stage5_iter5");
sc_trace(mVcdFile, ap_block_state54_pp0_stage5_iter6, "ap_block_state54_pp0_stage5_iter6");
sc_trace(mVcdFile, ap_block_state62_pp0_stage5_iter7, "ap_block_state62_pp0_stage5_iter7");
sc_trace(mVcdFile, ap_block_state70_pp0_stage5_iter8, "ap_block_state70_pp0_stage5_iter8");
sc_trace(mVcdFile, ap_block_state78_pp0_stage5_iter9, "ap_block_state78_pp0_stage5_iter9");
sc_trace(mVcdFile, ap_block_state86_pp0_stage5_iter10, "ap_block_state86_pp0_stage5_iter10");
sc_trace(mVcdFile, ap_block_state94_pp0_stage5_iter11, "ap_block_state94_pp0_stage5_iter11");
sc_trace(mVcdFile, ap_block_state102_pp0_stage5_iter12, "ap_block_state102_pp0_stage5_iter12");
sc_trace(mVcdFile, ap_block_state110_pp0_stage5_iter13, "ap_block_state110_pp0_stage5_iter13");
sc_trace(mVcdFile, ap_block_state118_pp0_stage5_iter14, "ap_block_state118_pp0_stage5_iter14");
sc_trace(mVcdFile, ap_block_state126_pp0_stage5_iter15, "ap_block_state126_pp0_stage5_iter15");
sc_trace(mVcdFile, ap_block_pp0_stage5_11001, "ap_block_pp0_stage5_11001");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage4, "ap_CS_fsm_pp0_stage4");
sc_trace(mVcdFile, ap_block_state5_pp0_stage4_iter0, "ap_block_state5_pp0_stage4_iter0");
sc_trace(mVcdFile, ap_block_state13_pp0_stage4_iter1, "ap_block_state13_pp0_stage4_iter1");
sc_trace(mVcdFile, ap_block_state21_pp0_stage4_iter2, "ap_block_state21_pp0_stage4_iter2");
sc_trace(mVcdFile, ap_block_state29_pp0_stage4_iter3, "ap_block_state29_pp0_stage4_iter3");
sc_trace(mVcdFile, ap_block_state37_pp0_stage4_iter4, "ap_block_state37_pp0_stage4_iter4");
sc_trace(mVcdFile, ap_block_state45_pp0_stage4_iter5, "ap_block_state45_pp0_stage4_iter5");
sc_trace(mVcdFile, ap_block_state53_pp0_stage4_iter6, "ap_block_state53_pp0_stage4_iter6");
sc_trace(mVcdFile, ap_block_state61_pp0_stage4_iter7, "ap_block_state61_pp0_stage4_iter7");
sc_trace(mVcdFile, ap_block_state69_pp0_stage4_iter8, "ap_block_state69_pp0_stage4_iter8");
sc_trace(mVcdFile, ap_block_state77_pp0_stage4_iter9, "ap_block_state77_pp0_stage4_iter9");
sc_trace(mVcdFile, ap_block_state85_pp0_stage4_iter10, "ap_block_state85_pp0_stage4_iter10");
sc_trace(mVcdFile, ap_block_state93_pp0_stage4_iter11, "ap_block_state93_pp0_stage4_iter11");
sc_trace(mVcdFile, ap_block_state101_pp0_stage4_iter12, "ap_block_state101_pp0_stage4_iter12");
sc_trace(mVcdFile, ap_block_state109_pp0_stage4_iter13, "ap_block_state109_pp0_stage4_iter13");
sc_trace(mVcdFile, ap_block_state117_pp0_stage4_iter14, "ap_block_state117_pp0_stage4_iter14");
sc_trace(mVcdFile, ap_block_state125_pp0_stage4_iter15, "ap_block_state125_pp0_stage4_iter15");
sc_trace(mVcdFile, ap_block_pp0_stage4_11001, "ap_block_pp0_stage4_11001");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage6, "ap_CS_fsm_pp0_stage6");
sc_trace(mVcdFile, ap_block_state7_pp0_stage6_iter0, "ap_block_state7_pp0_stage6_iter0");
sc_trace(mVcdFile, ap_block_state15_pp0_stage6_iter1, "ap_block_state15_pp0_stage6_iter1");
sc_trace(mVcdFile, ap_block_state23_pp0_stage6_iter2, "ap_block_state23_pp0_stage6_iter2");
sc_trace(mVcdFile, ap_block_state31_pp0_stage6_iter3, "ap_block_state31_pp0_stage6_iter3");
sc_trace(mVcdFile, ap_block_state39_pp0_stage6_iter4, "ap_block_state39_pp0_stage6_iter4");
sc_trace(mVcdFile, ap_block_state47_pp0_stage6_iter5, "ap_block_state47_pp0_stage6_iter5");
sc_trace(mVcdFile, ap_block_state55_pp0_stage6_iter6, "ap_block_state55_pp0_stage6_iter6");
sc_trace(mVcdFile, ap_block_state63_pp0_stage6_iter7, "ap_block_state63_pp0_stage6_iter7");
sc_trace(mVcdFile, ap_block_state71_pp0_stage6_iter8, "ap_block_state71_pp0_stage6_iter8");
sc_trace(mVcdFile, ap_block_state79_pp0_stage6_iter9, "ap_block_state79_pp0_stage6_iter9");
sc_trace(mVcdFile, ap_block_state87_pp0_stage6_iter10, "ap_block_state87_pp0_stage6_iter10");
sc_trace(mVcdFile, ap_block_state95_pp0_stage6_iter11, "ap_block_state95_pp0_stage6_iter11");
sc_trace(mVcdFile, ap_block_state103_pp0_stage6_iter12, "ap_block_state103_pp0_stage6_iter12");
sc_trace(mVcdFile, ap_block_state111_pp0_stage6_iter13, "ap_block_state111_pp0_stage6_iter13");
sc_trace(mVcdFile, ap_block_state119_pp0_stage6_iter14, "ap_block_state119_pp0_stage6_iter14");
sc_trace(mVcdFile, ap_block_state127_pp0_stage6_iter15, "ap_block_state127_pp0_stage6_iter15");
sc_trace(mVcdFile, ap_block_pp0_stage6_11001, "ap_block_pp0_stage6_11001");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage2, "ap_CS_fsm_pp0_stage2");
sc_trace(mVcdFile, ap_block_state3_pp0_stage2_iter0, "ap_block_state3_pp0_stage2_iter0");
sc_trace(mVcdFile, ap_block_state11_pp0_stage2_iter1, "ap_block_state11_pp0_stage2_iter1");
sc_trace(mVcdFile, ap_block_state19_pp0_stage2_iter2, "ap_block_state19_pp0_stage2_iter2");
sc_trace(mVcdFile, ap_block_state27_pp0_stage2_iter3, "ap_block_state27_pp0_stage2_iter3");
sc_trace(mVcdFile, ap_block_state35_pp0_stage2_iter4, "ap_block_state35_pp0_stage2_iter4");
sc_trace(mVcdFile, ap_block_state43_pp0_stage2_iter5, "ap_block_state43_pp0_stage2_iter5");
sc_trace(mVcdFile, ap_block_state51_pp0_stage2_iter6, "ap_block_state51_pp0_stage2_iter6");
sc_trace(mVcdFile, ap_block_state59_pp0_stage2_iter7, "ap_block_state59_pp0_stage2_iter7");
sc_trace(mVcdFile, ap_block_state67_pp0_stage2_iter8, "ap_block_state67_pp0_stage2_iter8");
sc_trace(mVcdFile, ap_block_state75_pp0_stage2_iter9, "ap_block_state75_pp0_stage2_iter9");
sc_trace(mVcdFile, ap_block_state83_pp0_stage2_iter10, "ap_block_state83_pp0_stage2_iter10");
sc_trace(mVcdFile, ap_block_state91_pp0_stage2_iter11, "ap_block_state91_pp0_stage2_iter11");
sc_trace(mVcdFile, ap_block_state99_pp0_stage2_iter12, "ap_block_state99_pp0_stage2_iter12");
sc_trace(mVcdFile, ap_block_state107_pp0_stage2_iter13, "ap_block_state107_pp0_stage2_iter13");
sc_trace(mVcdFile, ap_block_state115_pp0_stage2_iter14, "ap_block_state115_pp0_stage2_iter14");
sc_trace(mVcdFile, ap_block_state123_pp0_stage2_iter15, "ap_block_state123_pp0_stage2_iter15");
sc_trace(mVcdFile, ap_block_state131_pp0_stage2_iter16, "ap_block_state131_pp0_stage2_iter16");
sc_trace(mVcdFile, ap_block_pp0_stage2_11001, "ap_block_pp0_stage2_11001");
sc_trace(mVcdFile, grp_EP0_fu_996_ap_return, "grp_EP0_fu_996_ap_return");
sc_trace(mVcdFile, reg_1216, "reg_1216");
sc_trace(mVcdFile, grp_MAJ_fu_864_ap_return, "grp_MAJ_fu_864_ap_return");
sc_trace(mVcdFile, reg_1220, "reg_1220");
sc_trace(mVcdFile, grp_SIG1_fu_1053_ap_return, "grp_SIG1_fu_1053_ap_return");
sc_trace(mVcdFile, reg_1224, "reg_1224");
sc_trace(mVcdFile, ap_CS_fsm_pp0_stage1, "ap_CS_fsm_pp0_stage1");
sc_trace(mVcdFile, ap_block_state2_pp0_stage1_iter0, "ap_block_state2_pp0_stage1_iter0");
sc_trace(mVcdFile, ap_block_state10_pp0_stage1_iter1, "ap_block_state10_pp0_stage1_iter1");
sc_trace(mVcdFile, ap_block_state18_pp0_stage1_iter2, "ap_block_state18_pp0_stage1_iter2");
sc_trace(mVcdFile, ap_block_state26_pp0_stage1_iter3, "ap_block_state26_pp0_stage1_iter3");
sc_trace(mVcdFile, ap_block_state34_pp0_stage1_iter4, "ap_block_state34_pp0_stage1_iter4");
sc_trace(mVcdFile, ap_block_state42_pp0_stage1_iter5, "ap_block_state42_pp0_stage1_iter5");
sc_trace(mVcdFile, ap_block_state50_pp0_stage1_iter6, "ap_block_state50_pp0_stage1_iter6");
sc_trace(mVcdFile, ap_block_state58_pp0_stage1_iter7, "ap_block_state58_pp0_stage1_iter7");
sc_trace(mVcdFile, ap_block_state66_pp0_stage1_iter8, "ap_block_state66_pp0_stage1_iter8");
sc_trace(mVcdFile, ap_block_state74_pp0_stage1_iter9, "ap_block_state74_pp0_stage1_iter9");
sc_trace(mVcdFile, ap_block_state82_pp0_stage1_iter10, "ap_block_state82_pp0_stage1_iter10");
sc_trace(mVcdFile, ap_block_state90_pp0_stage1_iter11, "ap_block_state90_pp0_stage1_iter11");
sc_trace(mVcdFile, ap_block_state98_pp0_stage1_iter12, "ap_block_state98_pp0_stage1_iter12");
sc_trace(mVcdFile, ap_block_state106_pp0_stage1_iter13, "ap_block_state106_pp0_stage1_iter13");
sc_trace(mVcdFile, ap_block_state114_pp0_stage1_iter14, "ap_block_state114_pp0_stage1_iter14");
sc_trace(mVcdFile, ap_block_state122_pp0_stage1_iter15, "ap_block_state122_pp0_stage1_iter15");
sc_trace(mVcdFile, ap_block_state130_pp0_stage1_iter16, "ap_block_state130_pp0_stage1_iter16");
sc_trace(mVcdFile, ap_block_pp0_stage1_11001, "ap_block_pp0_stage1_11001");
sc_trace(mVcdFile, grp_SIG1_fu_1060_ap_return, "grp_SIG1_fu_1060_ap_return");
sc_trace(mVcdFile, reg_1228, "reg_1228");
sc_trace(mVcdFile, grp_CH_fu_1149_ap_return, "grp_CH_fu_1149_ap_return");
sc_trace(mVcdFile, reg_1232, "reg_1232");
sc_trace(mVcdFile, grp_EP0_fu_1004_ap_return, "grp_EP0_fu_1004_ap_return");
sc_trace(mVcdFile, reg_1236, "reg_1236");
sc_trace(mVcdFile, grp_MAJ_fu_876_ap_return, "grp_MAJ_fu_876_ap_return");
sc_trace(mVcdFile, reg_1240, "reg_1240");
sc_trace(mVcdFile, grp_SIG1_fu_1067_ap_return, "grp_SIG1_fu_1067_ap_return");
sc_trace(mVcdFile, reg_1244, "reg_1244");
sc_trace(mVcdFile, grp_SIG1_fu_1074_ap_return, "grp_SIG1_fu_1074_ap_return");
sc_trace(mVcdFile, reg_1248, "reg_1248");
sc_trace(mVcdFile, grp_CH_fu_1158_ap_return, "grp_CH_fu_1158_ap_return");
sc_trace(mVcdFile, reg_1252, "reg_1252");
sc_trace(mVcdFile, grp_EP0_fu_1011_ap_return, "grp_EP0_fu_1011_ap_return");
sc_trace(mVcdFile, reg_1256, "reg_1256");
sc_trace(mVcdFile, grp_MAJ_fu_885_ap_return, "grp_MAJ_fu_885_ap_return");
sc_trace(mVcdFile, reg_1260, "reg_1260");
sc_trace(mVcdFile, grp_SIG1_fu_1081_ap_return, "grp_SIG1_fu_1081_ap_return");
sc_trace(mVcdFile, reg_1264, "reg_1264");
sc_trace(mVcdFile, grp_SIG1_fu_1088_ap_return, "grp_SIG1_fu_1088_ap_return");
sc_trace(mVcdFile, reg_1268, "reg_1268");
sc_trace(mVcdFile, grp_CH_fu_1167_ap_return, "grp_CH_fu_1167_ap_return");
sc_trace(mVcdFile, reg_1272, "reg_1272");
sc_trace(mVcdFile, grp_EP0_fu_1018_ap_return, "grp_EP0_fu_1018_ap_return");
sc_trace(mVcdFile, reg_1276, "reg_1276");
sc_trace(mVcdFile, grp_MAJ_fu_894_ap_return, "grp_MAJ_fu_894_ap_return");
sc_trace(mVcdFile, reg_1280, "reg_1280");
sc_trace(mVcdFile, grp_CH_fu_1176_ap_return, "grp_CH_fu_1176_ap_return");
sc_trace(mVcdFile, reg_1284, "reg_1284");
sc_trace(mVcdFile, grp_EP0_fu_1025_ap_return, "grp_EP0_fu_1025_ap_return");
sc_trace(mVcdFile, reg_1288, "reg_1288");
sc_trace(mVcdFile, grp_MAJ_fu_903_ap_return, "grp_MAJ_fu_903_ap_return");
sc_trace(mVcdFile, reg_1292, "reg_1292");
sc_trace(mVcdFile, grp_CH_fu_1185_ap_return, "grp_CH_fu_1185_ap_return");
sc_trace(mVcdFile, reg_1296, "reg_1296");
sc_trace(mVcdFile, grp_EP0_fu_1032_ap_return, "grp_EP0_fu_1032_ap_return");
sc_trace(mVcdFile, reg_1300, "reg_1300");
sc_trace(mVcdFile, grp_MAJ_fu_912_ap_return, "grp_MAJ_fu_912_ap_return");
sc_trace(mVcdFile, reg_1304, "reg_1304");
sc_trace(mVcdFile, grp_CH_fu_1194_ap_return, "grp_CH_fu_1194_ap_return");
sc_trace(mVcdFile, reg_1308, "reg_1308");
sc_trace(mVcdFile, grp_EP0_fu_1039_ap_return, "grp_EP0_fu_1039_ap_return");
sc_trace(mVcdFile, reg_1312, "reg_1312");
sc_trace(mVcdFile, grp_MAJ_fu_921_ap_return, "grp_MAJ_fu_921_ap_return");
sc_trace(mVcdFile, reg_1316, "reg_1316");
sc_trace(mVcdFile, grp_CH_fu_1203_ap_return, "grp_CH_fu_1203_ap_return");
sc_trace(mVcdFile, reg_1320, "reg_1320");
sc_trace(mVcdFile, grp_EP0_fu_1046_ap_return, "grp_EP0_fu_1046_ap_return");
sc_trace(mVcdFile, reg_1324, "reg_1324");
sc_trace(mVcdFile, grp_MAJ_fu_930_ap_return, "grp_MAJ_fu_930_ap_return");
sc_trace(mVcdFile, reg_1328, "reg_1328");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797, "ctx_state_6_read_1_reg_4797");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter1_reg, "ctx_state_6_read_1_reg_4797_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter2_reg, "ctx_state_6_read_1_reg_4797_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter3_reg, "ctx_state_6_read_1_reg_4797_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter4_reg, "ctx_state_6_read_1_reg_4797_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter5_reg, "ctx_state_6_read_1_reg_4797_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter6_reg, "ctx_state_6_read_1_reg_4797_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter7_reg, "ctx_state_6_read_1_reg_4797_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter8_reg, "ctx_state_6_read_1_reg_4797_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter9_reg, "ctx_state_6_read_1_reg_4797_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter10_reg, "ctx_state_6_read_1_reg_4797_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter11_reg, "ctx_state_6_read_1_reg_4797_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter12_reg, "ctx_state_6_read_1_reg_4797_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter13_reg, "ctx_state_6_read_1_reg_4797_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter14_reg, "ctx_state_6_read_1_reg_4797_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter15_reg, "ctx_state_6_read_1_reg_4797_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_6_read_1_reg_4797_pp0_iter16_reg, "ctx_state_6_read_1_reg_4797_pp0_iter16_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803, "ctx_state_5_read_1_reg_4803");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter1_reg, "ctx_state_5_read_1_reg_4803_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter2_reg, "ctx_state_5_read_1_reg_4803_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter3_reg, "ctx_state_5_read_1_reg_4803_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter4_reg, "ctx_state_5_read_1_reg_4803_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter5_reg, "ctx_state_5_read_1_reg_4803_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter6_reg, "ctx_state_5_read_1_reg_4803_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter7_reg, "ctx_state_5_read_1_reg_4803_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter8_reg, "ctx_state_5_read_1_reg_4803_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter9_reg, "ctx_state_5_read_1_reg_4803_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter10_reg, "ctx_state_5_read_1_reg_4803_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter11_reg, "ctx_state_5_read_1_reg_4803_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter12_reg, "ctx_state_5_read_1_reg_4803_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter13_reg, "ctx_state_5_read_1_reg_4803_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter14_reg, "ctx_state_5_read_1_reg_4803_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter15_reg, "ctx_state_5_read_1_reg_4803_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_5_read_1_reg_4803_pp0_iter16_reg, "ctx_state_5_read_1_reg_4803_pp0_iter16_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810, "ctx_state_4_read_1_reg_4810");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter1_reg, "ctx_state_4_read_1_reg_4810_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter2_reg, "ctx_state_4_read_1_reg_4810_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter3_reg, "ctx_state_4_read_1_reg_4810_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter4_reg, "ctx_state_4_read_1_reg_4810_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter5_reg, "ctx_state_4_read_1_reg_4810_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter6_reg, "ctx_state_4_read_1_reg_4810_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter7_reg, "ctx_state_4_read_1_reg_4810_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter8_reg, "ctx_state_4_read_1_reg_4810_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter9_reg, "ctx_state_4_read_1_reg_4810_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter10_reg, "ctx_state_4_read_1_reg_4810_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter11_reg, "ctx_state_4_read_1_reg_4810_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter12_reg, "ctx_state_4_read_1_reg_4810_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter13_reg, "ctx_state_4_read_1_reg_4810_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter14_reg, "ctx_state_4_read_1_reg_4810_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter15_reg, "ctx_state_4_read_1_reg_4810_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_4_read_1_reg_4810_pp0_iter16_reg, "ctx_state_4_read_1_reg_4810_pp0_iter16_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818, "ctx_state_2_read_1_reg_4818");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter1_reg, "ctx_state_2_read_1_reg_4818_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter2_reg, "ctx_state_2_read_1_reg_4818_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter3_reg, "ctx_state_2_read_1_reg_4818_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter4_reg, "ctx_state_2_read_1_reg_4818_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter5_reg, "ctx_state_2_read_1_reg_4818_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter6_reg, "ctx_state_2_read_1_reg_4818_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter7_reg, "ctx_state_2_read_1_reg_4818_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter8_reg, "ctx_state_2_read_1_reg_4818_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter9_reg, "ctx_state_2_read_1_reg_4818_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter10_reg, "ctx_state_2_read_1_reg_4818_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter11_reg, "ctx_state_2_read_1_reg_4818_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter12_reg, "ctx_state_2_read_1_reg_4818_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter13_reg, "ctx_state_2_read_1_reg_4818_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter14_reg, "ctx_state_2_read_1_reg_4818_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter15_reg, "ctx_state_2_read_1_reg_4818_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_2_read_1_reg_4818_pp0_iter16_reg, "ctx_state_2_read_1_reg_4818_pp0_iter16_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824, "ctx_state_1_read_1_reg_4824");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter1_reg, "ctx_state_1_read_1_reg_4824_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter2_reg, "ctx_state_1_read_1_reg_4824_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter3_reg, "ctx_state_1_read_1_reg_4824_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter4_reg, "ctx_state_1_read_1_reg_4824_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter5_reg, "ctx_state_1_read_1_reg_4824_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter6_reg, "ctx_state_1_read_1_reg_4824_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter7_reg, "ctx_state_1_read_1_reg_4824_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter8_reg, "ctx_state_1_read_1_reg_4824_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter9_reg, "ctx_state_1_read_1_reg_4824_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter10_reg, "ctx_state_1_read_1_reg_4824_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter11_reg, "ctx_state_1_read_1_reg_4824_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter12_reg, "ctx_state_1_read_1_reg_4824_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter13_reg, "ctx_state_1_read_1_reg_4824_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter14_reg, "ctx_state_1_read_1_reg_4824_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter15_reg, "ctx_state_1_read_1_reg_4824_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_1_read_1_reg_4824_pp0_iter16_reg, "ctx_state_1_read_1_reg_4824_pp0_iter16_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831, "ctx_state_0_read_1_reg_4831");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter1_reg, "ctx_state_0_read_1_reg_4831_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter2_reg, "ctx_state_0_read_1_reg_4831_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter3_reg, "ctx_state_0_read_1_reg_4831_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter4_reg, "ctx_state_0_read_1_reg_4831_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter5_reg, "ctx_state_0_read_1_reg_4831_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter6_reg, "ctx_state_0_read_1_reg_4831_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter7_reg, "ctx_state_0_read_1_reg_4831_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter8_reg, "ctx_state_0_read_1_reg_4831_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter9_reg, "ctx_state_0_read_1_reg_4831_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter10_reg, "ctx_state_0_read_1_reg_4831_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter11_reg, "ctx_state_0_read_1_reg_4831_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter12_reg, "ctx_state_0_read_1_reg_4831_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter13_reg, "ctx_state_0_read_1_reg_4831_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter14_reg, "ctx_state_0_read_1_reg_4831_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter15_reg, "ctx_state_0_read_1_reg_4831_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_0_read_1_reg_4831_pp0_iter16_reg, "ctx_state_0_read_1_reg_4831_pp0_iter16_reg");
sc_trace(mVcdFile, grp_EP1_fu_939_ap_return, "grp_EP1_fu_939_ap_return");
sc_trace(mVcdFile, tmp_48_reg_4879, "tmp_48_reg_4879");
sc_trace(mVcdFile, m_0_fu_1332_p5, "m_0_fu_1332_p5");
sc_trace(mVcdFile, m_0_reg_4884, "m_0_reg_4884");
sc_trace(mVcdFile, m_1_fu_1344_p5, "m_1_fu_1344_p5");
sc_trace(mVcdFile, m_1_reg_4889, "m_1_reg_4889");
sc_trace(mVcdFile, grp_SIG0_fu_1095_ap_return, "grp_SIG0_fu_1095_ap_return");
sc_trace(mVcdFile, tmp_1_reg_4935, "tmp_1_reg_4935");
sc_trace(mVcdFile, add_ln274_2_fu_1363_p2, "add_ln274_2_fu_1363_p2");
sc_trace(mVcdFile, add_ln274_2_reg_4940, "add_ln274_2_reg_4940");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945, "ctx_state_7_read_1_reg_4945");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter1_reg, "ctx_state_7_read_1_reg_4945_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter2_reg, "ctx_state_7_read_1_reg_4945_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter3_reg, "ctx_state_7_read_1_reg_4945_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter4_reg, "ctx_state_7_read_1_reg_4945_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter5_reg, "ctx_state_7_read_1_reg_4945_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter6_reg, "ctx_state_7_read_1_reg_4945_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter7_reg, "ctx_state_7_read_1_reg_4945_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter8_reg, "ctx_state_7_read_1_reg_4945_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter9_reg, "ctx_state_7_read_1_reg_4945_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter10_reg, "ctx_state_7_read_1_reg_4945_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter11_reg, "ctx_state_7_read_1_reg_4945_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter12_reg, "ctx_state_7_read_1_reg_4945_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter13_reg, "ctx_state_7_read_1_reg_4945_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter14_reg, "ctx_state_7_read_1_reg_4945_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_7_read_1_reg_4945_pp0_iter15_reg, "ctx_state_7_read_1_reg_4945_pp0_iter15_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950, "ctx_state_3_read_1_reg_4950");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter1_reg, "ctx_state_3_read_1_reg_4950_pp0_iter1_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter2_reg, "ctx_state_3_read_1_reg_4950_pp0_iter2_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter3_reg, "ctx_state_3_read_1_reg_4950_pp0_iter3_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter4_reg, "ctx_state_3_read_1_reg_4950_pp0_iter4_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter5_reg, "ctx_state_3_read_1_reg_4950_pp0_iter5_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter6_reg, "ctx_state_3_read_1_reg_4950_pp0_iter6_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter7_reg, "ctx_state_3_read_1_reg_4950_pp0_iter7_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter8_reg, "ctx_state_3_read_1_reg_4950_pp0_iter8_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter9_reg, "ctx_state_3_read_1_reg_4950_pp0_iter9_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter10_reg, "ctx_state_3_read_1_reg_4950_pp0_iter10_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter11_reg, "ctx_state_3_read_1_reg_4950_pp0_iter11_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter12_reg, "ctx_state_3_read_1_reg_4950_pp0_iter12_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter13_reg, "ctx_state_3_read_1_reg_4950_pp0_iter13_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter14_reg, "ctx_state_3_read_1_reg_4950_pp0_iter14_reg");
sc_trace(mVcdFile, ctx_state_3_read_1_reg_4950_pp0_iter15_reg, "ctx_state_3_read_1_reg_4950_pp0_iter15_reg");
sc_trace(mVcdFile, m_2_fu_1368_p5, "m_2_fu_1368_p5");
sc_trace(mVcdFile, m_2_reg_4955, "m_2_reg_4955");
sc_trace(mVcdFile, m_3_fu_1381_p5, "m_3_fu_1381_p5");
sc_trace(mVcdFile, m_3_reg_4961, "m_3_reg_4961");
sc_trace(mVcdFile, tmp_1_1_reg_5007, "tmp_1_1_reg_5007");
sc_trace(mVcdFile, grp_SIG0_fu_1102_ap_return, "grp_SIG0_fu_1102_ap_return");
sc_trace(mVcdFile, tmp_1_2_reg_5012, "tmp_1_2_reg_5012");
sc_trace(mVcdFile, add_ln280_fu_1405_p2, "add_ln280_fu_1405_p2");
sc_trace(mVcdFile, add_ln280_reg_5017, "add_ln280_reg_5017");
sc_trace(mVcdFile, add_ln284_fu_1417_p2, "add_ln284_fu_1417_p2");
sc_trace(mVcdFile, add_ln284_reg_5026, "add_ln284_reg_5026");
sc_trace(mVcdFile, m_4_fu_1423_p5, "m_4_fu_1423_p5");
sc_trace(mVcdFile, m_4_reg_5035, "m_4_reg_5035");
sc_trace(mVcdFile, m_5_fu_1436_p5, "m_5_fu_1436_p5");
sc_trace(mVcdFile, m_5_reg_5041, "m_5_reg_5041");
sc_trace(mVcdFile, tmp_1_3_reg_5087, "tmp_1_3_reg_5087");
sc_trace(mVcdFile, tmp_1_4_reg_5092, "tmp_1_4_reg_5092");
sc_trace(mVcdFile, add_ln274_6_fu_1454_p2, "add_ln274_6_fu_1454_p2");
sc_trace(mVcdFile, add_ln274_6_reg_5097, "add_ln274_6_reg_5097");
sc_trace(mVcdFile, m_6_fu_1460_p5, "m_6_fu_1460_p5");
sc_trace(mVcdFile, m_6_reg_5102, "m_6_reg_5102");
sc_trace(mVcdFile, m_6_reg_5102_pp0_iter1_reg, "m_6_reg_5102_pp0_iter1_reg");
sc_trace(mVcdFile, m_7_fu_1473_p5, "m_7_fu_1473_p5");
sc_trace(mVcdFile, m_7_reg_5108, "m_7_reg_5108");
sc_trace(mVcdFile, m_7_reg_5108_pp0_iter1_reg, "m_7_reg_5108_pp0_iter1_reg");
sc_trace(mVcdFile, tmp_1_5_reg_5154, "tmp_1_5_reg_5154");
sc_trace(mVcdFile, tmp_1_6_reg_5159, "tmp_1_6_reg_5159");
sc_trace(mVcdFile, add_ln280_1_fu_1496_p2, "add_ln280_1_fu_1496_p2");
sc_trace(mVcdFile, add_ln280_1_reg_5164, "add_ln280_1_reg_5164");
sc_trace(mVcdFile, add_ln284_1_fu_1507_p2, "add_ln284_1_fu_1507_p2");
sc_trace(mVcdFile, add_ln284_1_reg_5173, "add_ln284_1_reg_5173");
sc_trace(mVcdFile, m_8_fu_1513_p5, "m_8_fu_1513_p5");
sc_trace(mVcdFile, m_8_reg_5182, "m_8_reg_5182");
sc_trace(mVcdFile, m_8_reg_5182_pp0_iter1_reg, "m_8_reg_5182_pp0_iter1_reg");
sc_trace(mVcdFile, m_9_fu_1526_p5, "m_9_fu_1526_p5");
sc_trace(mVcdFile, m_9_reg_5188, "m_9_reg_5188");
sc_trace(mVcdFile, m_9_reg_5188_pp0_iter1_reg, "m_9_reg_5188_pp0_iter1_reg");
sc_trace(mVcdFile, tmp_1_7_reg_5235, "tmp_1_7_reg_5235");
sc_trace(mVcdFile, tmp_1_8_reg_5240, "tmp_1_8_reg_5240");
sc_trace(mVcdFile, add_ln274_10_fu_1544_p2, "add_ln274_10_fu_1544_p2");
sc_trace(mVcdFile, add_ln274_10_reg_5245, "add_ln274_10_reg_5245");
sc_trace(mVcdFile, m_10_fu_1549_p5, "m_10_fu_1549_p5");
sc_trace(mVcdFile, m_10_reg_5250, "m_10_reg_5250");
sc_trace(mVcdFile, m_10_reg_5250_pp0_iter1_reg, "m_10_reg_5250_pp0_iter1_reg");
sc_trace(mVcdFile, m_11_fu_1562_p5, "m_11_fu_1562_p5");
sc_trace(mVcdFile, m_11_reg_5257, "m_11_reg_5257");
sc_trace(mVcdFile, m_11_reg_5257_pp0_iter1_reg, "m_11_reg_5257_pp0_iter1_reg");
sc_trace(mVcdFile, m_11_reg_5257_pp0_iter2_reg, "m_11_reg_5257_pp0_iter2_reg");
sc_trace(mVcdFile, tmp_1_9_reg_5304, "tmp_1_9_reg_5304");
sc_trace(mVcdFile, tmp_1_s_reg_5309, "tmp_1_s_reg_5309");
sc_trace(mVcdFile, add_ln280_2_fu_1586_p2, "add_ln280_2_fu_1586_p2");
sc_trace(mVcdFile, add_ln280_2_reg_5314, "add_ln280_2_reg_5314");
sc_trace(mVcdFile, add_ln284_2_fu_1597_p2, "add_ln284_2_fu_1597_p2");
sc_trace(mVcdFile, add_ln284_2_reg_5323, "add_ln284_2_reg_5323");
sc_trace(mVcdFile, m_12_fu_1603_p5, "m_12_fu_1603_p5");
sc_trace(mVcdFile, m_12_reg_5332, "m_12_reg_5332");
sc_trace(mVcdFile, m_12_reg_5332_pp0_iter1_reg, "m_12_reg_5332_pp0_iter1_reg");
sc_trace(mVcdFile, m_12_reg_5332_pp0_iter2_reg, "m_12_reg_5332_pp0_iter2_reg");
sc_trace(mVcdFile, m_13_fu_1616_p5, "m_13_fu_1616_p5");
sc_trace(mVcdFile, m_13_reg_5339, "m_13_reg_5339");
sc_trace(mVcdFile, m_13_reg_5339_pp0_iter1_reg, "m_13_reg_5339_pp0_iter1_reg");
sc_trace(mVcdFile, m_13_reg_5339_pp0_iter2_reg, "m_13_reg_5339_pp0_iter2_reg");
sc_trace(mVcdFile, tmp_1_10_reg_5386, "tmp_1_10_reg_5386");
sc_trace(mVcdFile, tmp_1_11_reg_5391, "tmp_1_11_reg_5391");
sc_trace(mVcdFile, add_ln274_14_fu_1634_p2, "add_ln274_14_fu_1634_p2");
sc_trace(mVcdFile, add_ln274_14_reg_5396, "add_ln274_14_reg_5396");
sc_trace(mVcdFile, m_14_fu_1640_p5, "m_14_fu_1640_p5");
sc_trace(mVcdFile, m_14_reg_5401, "m_14_reg_5401");
sc_trace(mVcdFile, m_14_reg_5401_pp0_iter2_reg, "m_14_reg_5401_pp0_iter2_reg");
sc_trace(mVcdFile, m_14_reg_5401_pp0_iter3_reg, "m_14_reg_5401_pp0_iter3_reg");
sc_trace(mVcdFile, m_15_fu_1654_p5, "m_15_fu_1654_p5");
sc_trace(mVcdFile, m_15_reg_5408, "m_15_reg_5408");
sc_trace(mVcdFile, m_15_reg_5408_pp0_iter2_reg, "m_15_reg_5408_pp0_iter2_reg");
sc_trace(mVcdFile, m_15_reg_5408_pp0_iter3_reg, "m_15_reg_5408_pp0_iter3_reg");
sc_trace(mVcdFile, add_ln259_1_fu_1668_p2, "add_ln259_1_fu_1668_p2");
sc_trace(mVcdFile, add_ln259_1_reg_5415, "add_ln259_1_reg_5415");
sc_trace(mVcdFile, add_ln259_4_fu_1672_p2, "add_ln259_4_fu_1672_p2");
sc_trace(mVcdFile, add_ln259_4_reg_5420, "add_ln259_4_reg_5420");
sc_trace(mVcdFile, tmp_1_12_reg_5425, "tmp_1_12_reg_5425");
sc_trace(mVcdFile, tmp_1_13_reg_5430, "tmp_1_13_reg_5430");
sc_trace(mVcdFile, add_ln280_3_fu_1686_p2, "add_ln280_3_fu_1686_p2");
sc_trace(mVcdFile, add_ln280_3_reg_5435, "add_ln280_3_reg_5435");
sc_trace(mVcdFile, add_ln284_3_fu_1697_p2, "add_ln284_3_fu_1697_p2");
sc_trace(mVcdFile, add_ln284_3_reg_5444, "add_ln284_3_reg_5444");
sc_trace(mVcdFile, m_16_fu_1708_p2, "m_16_fu_1708_p2");
sc_trace(mVcdFile, m_16_reg_5453, "m_16_reg_5453");
sc_trace(mVcdFile, m_16_reg_5453_pp0_iter2_reg, "m_16_reg_5453_pp0_iter2_reg");
sc_trace(mVcdFile, m_16_reg_5453_pp0_iter3_reg, "m_16_reg_5453_pp0_iter3_reg");
sc_trace(mVcdFile, m_17_fu_1720_p2, "m_17_fu_1720_p2");
sc_trace(mVcdFile, m_17_reg_5460, "m_17_reg_5460");
sc_trace(mVcdFile, m_17_reg_5460_pp0_iter2_reg, "m_17_reg_5460_pp0_iter2_reg");
sc_trace(mVcdFile, m_17_reg_5460_pp0_iter3_reg, "m_17_reg_5460_pp0_iter3_reg");
sc_trace(mVcdFile, m_17_reg_5460_pp0_iter4_reg, "m_17_reg_5460_pp0_iter4_reg");
sc_trace(mVcdFile, add_ln259_7_fu_1727_p2, "add_ln259_7_fu_1727_p2");
sc_trace(mVcdFile, add_ln259_7_reg_5467, "add_ln259_7_reg_5467");
sc_trace(mVcdFile, add_ln259_10_fu_1731_p2, "add_ln259_10_fu_1731_p2");
sc_trace(mVcdFile, add_ln259_10_reg_5472, "add_ln259_10_reg_5472");
sc_trace(mVcdFile, tmp_1_14_reg_5477, "tmp_1_14_reg_5477");
sc_trace(mVcdFile, grp_SIG0_fu_1109_ap_return, "grp_SIG0_fu_1109_ap_return");
sc_trace(mVcdFile, tmp_1_15_reg_5482, "tmp_1_15_reg_5482");
sc_trace(mVcdFile, tmp_3_0_4_reg_5487, "tmp_3_0_4_reg_5487");
sc_trace(mVcdFile, add_ln274_18_fu_1740_p2, "add_ln274_18_fu_1740_p2");
sc_trace(mVcdFile, add_ln274_18_reg_5492, "add_ln274_18_reg_5492");
sc_trace(mVcdFile, tmp_4_0_4_reg_5497, "tmp_4_0_4_reg_5497");
sc_trace(mVcdFile, tmp_5_0_4_reg_5502, "tmp_5_0_4_reg_5502");
sc_trace(mVcdFile, m_18_fu_1751_p2, "m_18_fu_1751_p2");
sc_trace(mVcdFile, m_18_reg_5507, "m_18_reg_5507");
sc_trace(mVcdFile, m_18_reg_5507_pp0_iter2_reg, "m_18_reg_5507_pp0_iter2_reg");
sc_trace(mVcdFile, m_18_reg_5507_pp0_iter3_reg, "m_18_reg_5507_pp0_iter3_reg");
sc_trace(mVcdFile, m_18_reg_5507_pp0_iter4_reg, "m_18_reg_5507_pp0_iter4_reg");
sc_trace(mVcdFile, m_19_fu_1763_p2, "m_19_fu_1763_p2");
sc_trace(mVcdFile, m_19_reg_5514, "m_19_reg_5514");
sc_trace(mVcdFile, m_19_reg_5514_pp0_iter2_reg, "m_19_reg_5514_pp0_iter2_reg");
sc_trace(mVcdFile, m_19_reg_5514_pp0_iter3_reg, "m_19_reg_5514_pp0_iter3_reg");
sc_trace(mVcdFile, m_19_reg_5514_pp0_iter4_reg, "m_19_reg_5514_pp0_iter4_reg");
sc_trace(mVcdFile, add_ln259_13_fu_1770_p2, "add_ln259_13_fu_1770_p2");
sc_trace(mVcdFile, add_ln259_13_reg_5521, "add_ln259_13_reg_5521");
sc_trace(mVcdFile, add_ln259_16_fu_1774_p2, "add_ln259_16_fu_1774_p2");
sc_trace(mVcdFile, add_ln259_16_reg_5526, "add_ln259_16_reg_5526");
sc_trace(mVcdFile, tmp_1_16_reg_5531, "tmp_1_16_reg_5531");
sc_trace(mVcdFile, grp_SIG0_fu_1116_ap_return, "grp_SIG0_fu_1116_ap_return");
sc_trace(mVcdFile, tmp_1_17_reg_5536, "tmp_1_17_reg_5536");
sc_trace(mVcdFile, add_ln280_4_fu_1787_p2, "add_ln280_4_fu_1787_p2");
sc_trace(mVcdFile, add_ln280_4_reg_5541, "add_ln280_4_reg_5541");
sc_trace(mVcdFile, add_ln284_4_fu_1797_p2, "add_ln284_4_fu_1797_p2");
sc_trace(mVcdFile, add_ln284_4_reg_5550, "add_ln284_4_reg_5550");
sc_trace(mVcdFile, m_20_fu_1807_p2, "m_20_fu_1807_p2");
sc_trace(mVcdFile, m_20_reg_5559, "m_20_reg_5559");
sc_trace(mVcdFile, m_20_reg_5559_pp0_iter2_reg, "m_20_reg_5559_pp0_iter2_reg");
sc_trace(mVcdFile, m_20_reg_5559_pp0_iter3_reg, "m_20_reg_5559_pp0_iter3_reg");
sc_trace(mVcdFile, m_20_reg_5559_pp0_iter4_reg, "m_20_reg_5559_pp0_iter4_reg");
sc_trace(mVcdFile, m_21_fu_1819_p2, "m_21_fu_1819_p2");
sc_trace(mVcdFile, m_21_reg_5566, "m_21_reg_5566");
sc_trace(mVcdFile, m_21_reg_5566_pp0_iter2_reg, "m_21_reg_5566_pp0_iter2_reg");
sc_trace(mVcdFile, m_21_reg_5566_pp0_iter3_reg, "m_21_reg_5566_pp0_iter3_reg");
sc_trace(mVcdFile, m_21_reg_5566_pp0_iter4_reg, "m_21_reg_5566_pp0_iter4_reg");
sc_trace(mVcdFile, add_ln259_19_fu_1826_p2, "add_ln259_19_fu_1826_p2");
sc_trace(mVcdFile, add_ln259_19_reg_5573, "add_ln259_19_reg_5573");
sc_trace(mVcdFile, add_ln259_22_fu_1830_p2, "add_ln259_22_fu_1830_p2");
sc_trace(mVcdFile, add_ln259_22_reg_5578, "add_ln259_22_reg_5578");
sc_trace(mVcdFile, tmp_1_18_reg_5583, "tmp_1_18_reg_5583");
sc_trace(mVcdFile, tmp_1_19_reg_5588, "tmp_1_19_reg_5588");
sc_trace(mVcdFile, add_ln274_22_fu_1839_p2, "add_ln274_22_fu_1839_p2");
sc_trace(mVcdFile, add_ln274_22_reg_5593, "add_ln274_22_reg_5593");
sc_trace(mVcdFile, m_22_fu_1850_p2, "m_22_fu_1850_p2");
sc_trace(mVcdFile, m_22_reg_5598, "m_22_reg_5598");
sc_trace(mVcdFile, m_22_reg_5598_pp0_iter2_reg, "m_22_reg_5598_pp0_iter2_reg");
sc_trace(mVcdFile, m_22_reg_5598_pp0_iter3_reg, "m_22_reg_5598_pp0_iter3_reg");
sc_trace(mVcdFile, m_22_reg_5598_pp0_iter4_reg, "m_22_reg_5598_pp0_iter4_reg");
sc_trace(mVcdFile, m_22_reg_5598_pp0_iter5_reg, "m_22_reg_5598_pp0_iter5_reg");
sc_trace(mVcdFile, m_23_fu_1862_p2, "m_23_fu_1862_p2");
sc_trace(mVcdFile, m_23_reg_5605, "m_23_reg_5605");
sc_trace(mVcdFile, m_23_reg_5605_pp0_iter2_reg, "m_23_reg_5605_pp0_iter2_reg");
sc_trace(mVcdFile, m_23_reg_5605_pp0_iter3_reg, "m_23_reg_5605_pp0_iter3_reg");
sc_trace(mVcdFile, m_23_reg_5605_pp0_iter4_reg, "m_23_reg_5605_pp0_iter4_reg");
sc_trace(mVcdFile, m_23_reg_5605_pp0_iter5_reg, "m_23_reg_5605_pp0_iter5_reg");
sc_trace(mVcdFile, add_ln259_25_fu_1869_p2, "add_ln259_25_fu_1869_p2");
sc_trace(mVcdFile, add_ln259_25_reg_5612, "add_ln259_25_reg_5612");
sc_trace(mVcdFile, add_ln259_28_fu_1873_p2, "add_ln259_28_fu_1873_p2");
sc_trace(mVcdFile, add_ln259_28_reg_5617, "add_ln259_28_reg_5617");
sc_trace(mVcdFile, tmp_1_20_reg_5622, "tmp_1_20_reg_5622");
sc_trace(mVcdFile, tmp_1_21_reg_5627, "tmp_1_21_reg_5627");
sc_trace(mVcdFile, add_ln280_5_fu_1887_p2, "add_ln280_5_fu_1887_p2");
sc_trace(mVcdFile, add_ln280_5_reg_5632, "add_ln280_5_reg_5632");
sc_trace(mVcdFile, add_ln284_5_fu_1898_p2, "add_ln284_5_fu_1898_p2");
sc_trace(mVcdFile, add_ln284_5_reg_5641, "add_ln284_5_reg_5641");
sc_trace(mVcdFile, m_24_fu_1909_p2, "m_24_fu_1909_p2");
sc_trace(mVcdFile, m_24_reg_5650, "m_24_reg_5650");
sc_trace(mVcdFile, m_24_reg_5650_pp0_iter2_reg, "m_24_reg_5650_pp0_iter2_reg");
sc_trace(mVcdFile, m_24_reg_5650_pp0_iter3_reg, "m_24_reg_5650_pp0_iter3_reg");
sc_trace(mVcdFile, m_24_reg_5650_pp0_iter4_reg, "m_24_reg_5650_pp0_iter4_reg");
sc_trace(mVcdFile, m_24_reg_5650_pp0_iter5_reg, "m_24_reg_5650_pp0_iter5_reg");
sc_trace(mVcdFile, m_25_fu_1921_p2, "m_25_fu_1921_p2");
sc_trace(mVcdFile, m_25_reg_5657, "m_25_reg_5657");
sc_trace(mVcdFile, m_25_reg_5657_pp0_iter2_reg, "m_25_reg_5657_pp0_iter2_reg");
sc_trace(mVcdFile, m_25_reg_5657_pp0_iter3_reg, "m_25_reg_5657_pp0_iter3_reg");
sc_trace(mVcdFile, m_25_reg_5657_pp0_iter4_reg, "m_25_reg_5657_pp0_iter4_reg");
sc_trace(mVcdFile, m_25_reg_5657_pp0_iter5_reg, "m_25_reg_5657_pp0_iter5_reg");
sc_trace(mVcdFile, add_ln259_31_fu_1928_p2, "add_ln259_31_fu_1928_p2");
sc_trace(mVcdFile, add_ln259_31_reg_5664, "add_ln259_31_reg_5664");
sc_trace(mVcdFile, add_ln259_34_fu_1932_p2, "add_ln259_34_fu_1932_p2");
sc_trace(mVcdFile, add_ln259_34_reg_5669, "add_ln259_34_reg_5669");
sc_trace(mVcdFile, tmp_1_22_reg_5674, "tmp_1_22_reg_5674");
sc_trace(mVcdFile, tmp_1_23_reg_5679, "tmp_1_23_reg_5679");
sc_trace(mVcdFile, add_ln274_26_fu_1941_p2, "add_ln274_26_fu_1941_p2");
sc_trace(mVcdFile, add_ln274_26_reg_5684, "add_ln274_26_reg_5684");
sc_trace(mVcdFile, m_26_fu_1951_p2, "m_26_fu_1951_p2");
sc_trace(mVcdFile, m_26_reg_5689, "m_26_reg_5689");
sc_trace(mVcdFile, m_26_reg_5689_pp0_iter2_reg, "m_26_reg_5689_pp0_iter2_reg");
sc_trace(mVcdFile, m_26_reg_5689_pp0_iter3_reg, "m_26_reg_5689_pp0_iter3_reg");
sc_trace(mVcdFile, m_26_reg_5689_pp0_iter4_reg, "m_26_reg_5689_pp0_iter4_reg");
sc_trace(mVcdFile, m_26_reg_5689_pp0_iter5_reg, "m_26_reg_5689_pp0_iter5_reg");
sc_trace(mVcdFile, m_27_fu_1963_p2, "m_27_fu_1963_p2");
sc_trace(mVcdFile, m_27_reg_5696, "m_27_reg_5696");
sc_trace(mVcdFile, m_27_reg_5696_pp0_iter2_reg, "m_27_reg_5696_pp0_iter2_reg");
sc_trace(mVcdFile, m_27_reg_5696_pp0_iter3_reg, "m_27_reg_5696_pp0_iter3_reg");
sc_trace(mVcdFile, m_27_reg_5696_pp0_iter4_reg, "m_27_reg_5696_pp0_iter4_reg");
sc_trace(mVcdFile, m_27_reg_5696_pp0_iter5_reg, "m_27_reg_5696_pp0_iter5_reg");
sc_trace(mVcdFile, m_27_reg_5696_pp0_iter6_reg, "m_27_reg_5696_pp0_iter6_reg");
sc_trace(mVcdFile, add_ln259_37_fu_1970_p2, "add_ln259_37_fu_1970_p2");
sc_trace(mVcdFile, add_ln259_37_reg_5703, "add_ln259_37_reg_5703");
sc_trace(mVcdFile, add_ln259_40_fu_1974_p2, "add_ln259_40_fu_1974_p2");
sc_trace(mVcdFile, add_ln259_40_reg_5708, "add_ln259_40_reg_5708");
sc_trace(mVcdFile, tmp_1_24_reg_5713, "tmp_1_24_reg_5713");
sc_trace(mVcdFile, tmp_1_25_reg_5718, "tmp_1_25_reg_5718");
sc_trace(mVcdFile, add_ln280_6_fu_1989_p2, "add_ln280_6_fu_1989_p2");
sc_trace(mVcdFile, add_ln280_6_reg_5723, "add_ln280_6_reg_5723");
sc_trace(mVcdFile, add_ln284_6_fu_2000_p2, "add_ln284_6_fu_2000_p2");
sc_trace(mVcdFile, add_ln284_6_reg_5732, "add_ln284_6_reg_5732");
sc_trace(mVcdFile, m_28_fu_2011_p2, "m_28_fu_2011_p2");
sc_trace(mVcdFile, m_28_reg_5741, "m_28_reg_5741");
sc_trace(mVcdFile, m_28_reg_5741_pp0_iter2_reg, "m_28_reg_5741_pp0_iter2_reg");
sc_trace(mVcdFile, m_28_reg_5741_pp0_iter3_reg, "m_28_reg_5741_pp0_iter3_reg");
sc_trace(mVcdFile, m_28_reg_5741_pp0_iter4_reg, "m_28_reg_5741_pp0_iter4_reg");
sc_trace(mVcdFile, m_28_reg_5741_pp0_iter5_reg, "m_28_reg_5741_pp0_iter5_reg");
sc_trace(mVcdFile, m_28_reg_5741_pp0_iter6_reg, "m_28_reg_5741_pp0_iter6_reg");
sc_trace(mVcdFile, m_29_fu_2023_p2, "m_29_fu_2023_p2");
sc_trace(mVcdFile, m_29_reg_5748, "m_29_reg_5748");
sc_trace(mVcdFile, m_29_reg_5748_pp0_iter2_reg, "m_29_reg_5748_pp0_iter2_reg");
sc_trace(mVcdFile, m_29_reg_5748_pp0_iter3_reg, "m_29_reg_5748_pp0_iter3_reg");
sc_trace(mVcdFile, m_29_reg_5748_pp0_iter4_reg, "m_29_reg_5748_pp0_iter4_reg");
sc_trace(mVcdFile, m_29_reg_5748_pp0_iter5_reg, "m_29_reg_5748_pp0_iter5_reg");
sc_trace(mVcdFile, m_29_reg_5748_pp0_iter6_reg, "m_29_reg_5748_pp0_iter6_reg");
sc_trace(mVcdFile, add_ln259_43_fu_2030_p2, "add_ln259_43_fu_2030_p2");
sc_trace(mVcdFile, add_ln259_43_reg_5755, "add_ln259_43_reg_5755");
sc_trace(mVcdFile, add_ln259_46_fu_2034_p2, "add_ln259_46_fu_2034_p2");
sc_trace(mVcdFile, add_ln259_46_reg_5760, "add_ln259_46_reg_5760");
sc_trace(mVcdFile, tmp_1_26_reg_5765, "tmp_1_26_reg_5765");
sc_trace(mVcdFile, tmp_1_27_reg_5770, "tmp_1_27_reg_5770");
sc_trace(mVcdFile, add_ln274_30_fu_2043_p2, "add_ln274_30_fu_2043_p2");
sc_trace(mVcdFile, add_ln274_30_reg_5775, "add_ln274_30_reg_5775");
sc_trace(mVcdFile, m_30_fu_2053_p2, "m_30_fu_2053_p2");
sc_trace(mVcdFile, m_30_reg_5780, "m_30_reg_5780");
sc_trace(mVcdFile, m_30_reg_5780_pp0_iter3_reg, "m_30_reg_5780_pp0_iter3_reg");
sc_trace(mVcdFile, m_30_reg_5780_pp0_iter4_reg, "m_30_reg_5780_pp0_iter4_reg");
sc_trace(mVcdFile, m_30_reg_5780_pp0_iter5_reg, "m_30_reg_5780_pp0_iter5_reg");
sc_trace(mVcdFile, m_30_reg_5780_pp0_iter6_reg, "m_30_reg_5780_pp0_iter6_reg");
sc_trace(mVcdFile, m_30_reg_5780_pp0_iter7_reg, "m_30_reg_5780_pp0_iter7_reg");
sc_trace(mVcdFile, m_31_fu_2065_p2, "m_31_fu_2065_p2");
sc_trace(mVcdFile, m_31_reg_5787, "m_31_reg_5787");
sc_trace(mVcdFile, m_31_reg_5787_pp0_iter3_reg, "m_31_reg_5787_pp0_iter3_reg");
sc_trace(mVcdFile, m_31_reg_5787_pp0_iter4_reg, "m_31_reg_5787_pp0_iter4_reg");
sc_trace(mVcdFile, m_31_reg_5787_pp0_iter5_reg, "m_31_reg_5787_pp0_iter5_reg");
sc_trace(mVcdFile, m_31_reg_5787_pp0_iter6_reg, "m_31_reg_5787_pp0_iter6_reg");
sc_trace(mVcdFile, m_31_reg_5787_pp0_iter7_reg, "m_31_reg_5787_pp0_iter7_reg");
sc_trace(mVcdFile, add_ln259_49_fu_2072_p2, "add_ln259_49_fu_2072_p2");
sc_trace(mVcdFile, add_ln259_49_reg_5794, "add_ln259_49_reg_5794");
sc_trace(mVcdFile, add_ln259_52_fu_2076_p2, "add_ln259_52_fu_2076_p2");
sc_trace(mVcdFile, add_ln259_52_reg_5799, "add_ln259_52_reg_5799");
sc_trace(mVcdFile, tmp_1_28_reg_5804, "tmp_1_28_reg_5804");
sc_trace(mVcdFile, tmp_1_29_reg_5809, "tmp_1_29_reg_5809");
sc_trace(mVcdFile, add_ln280_7_fu_2091_p2, "add_ln280_7_fu_2091_p2");
sc_trace(mVcdFile, add_ln280_7_reg_5814, "add_ln280_7_reg_5814");
sc_trace(mVcdFile, add_ln284_7_fu_2102_p2, "add_ln284_7_fu_2102_p2");
sc_trace(mVcdFile, add_ln284_7_reg_5823, "add_ln284_7_reg_5823");
sc_trace(mVcdFile, m_32_fu_2113_p2, "m_32_fu_2113_p2");
sc_trace(mVcdFile, m_32_reg_5832, "m_32_reg_5832");
sc_trace(mVcdFile, m_32_reg_5832_pp0_iter3_reg, "m_32_reg_5832_pp0_iter3_reg");
sc_trace(mVcdFile, m_32_reg_5832_pp0_iter4_reg, "m_32_reg_5832_pp0_iter4_reg");
sc_trace(mVcdFile, m_32_reg_5832_pp0_iter5_reg, "m_32_reg_5832_pp0_iter5_reg");
sc_trace(mVcdFile, m_32_reg_5832_pp0_iter6_reg, "m_32_reg_5832_pp0_iter6_reg");
sc_trace(mVcdFile, m_32_reg_5832_pp0_iter7_reg, "m_32_reg_5832_pp0_iter7_reg");
sc_trace(mVcdFile, m_33_fu_2125_p2, "m_33_fu_2125_p2");
sc_trace(mVcdFile, m_33_reg_5839, "m_33_reg_5839");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter3_reg, "m_33_reg_5839_pp0_iter3_reg");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter4_reg, "m_33_reg_5839_pp0_iter4_reg");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter5_reg, "m_33_reg_5839_pp0_iter5_reg");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter6_reg, "m_33_reg_5839_pp0_iter6_reg");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter7_reg, "m_33_reg_5839_pp0_iter7_reg");
sc_trace(mVcdFile, m_33_reg_5839_pp0_iter8_reg, "m_33_reg_5839_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln259_55_fu_2132_p2, "add_ln259_55_fu_2132_p2");
sc_trace(mVcdFile, add_ln259_55_reg_5846, "add_ln259_55_reg_5846");
sc_trace(mVcdFile, add_ln259_58_fu_2136_p2, "add_ln259_58_fu_2136_p2");
sc_trace(mVcdFile, add_ln259_58_reg_5851, "add_ln259_58_reg_5851");
sc_trace(mVcdFile, tmp_1_30_reg_5856, "tmp_1_30_reg_5856");
sc_trace(mVcdFile, grp_SIG0_fu_1123_ap_return, "grp_SIG0_fu_1123_ap_return");
sc_trace(mVcdFile, tmp_1_31_reg_5861, "tmp_1_31_reg_5861");
sc_trace(mVcdFile, add_ln274_34_fu_2145_p2, "add_ln274_34_fu_2145_p2");
sc_trace(mVcdFile, add_ln274_34_reg_5866, "add_ln274_34_reg_5866");
sc_trace(mVcdFile, m_34_fu_2156_p2, "m_34_fu_2156_p2");
sc_trace(mVcdFile, m_34_reg_5871, "m_34_reg_5871");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter3_reg, "m_34_reg_5871_pp0_iter3_reg");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter4_reg, "m_34_reg_5871_pp0_iter4_reg");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter5_reg, "m_34_reg_5871_pp0_iter5_reg");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter6_reg, "m_34_reg_5871_pp0_iter6_reg");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter7_reg, "m_34_reg_5871_pp0_iter7_reg");
sc_trace(mVcdFile, m_34_reg_5871_pp0_iter8_reg, "m_34_reg_5871_pp0_iter8_reg");
sc_trace(mVcdFile, m_35_fu_2168_p2, "m_35_fu_2168_p2");
sc_trace(mVcdFile, m_35_reg_5878, "m_35_reg_5878");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter3_reg, "m_35_reg_5878_pp0_iter3_reg");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter4_reg, "m_35_reg_5878_pp0_iter4_reg");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter5_reg, "m_35_reg_5878_pp0_iter5_reg");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter6_reg, "m_35_reg_5878_pp0_iter6_reg");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter7_reg, "m_35_reg_5878_pp0_iter7_reg");
sc_trace(mVcdFile, m_35_reg_5878_pp0_iter8_reg, "m_35_reg_5878_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln259_61_fu_2175_p2, "add_ln259_61_fu_2175_p2");
sc_trace(mVcdFile, add_ln259_61_reg_5885, "add_ln259_61_reg_5885");
sc_trace(mVcdFile, add_ln259_64_fu_2179_p2, "add_ln259_64_fu_2179_p2");
sc_trace(mVcdFile, add_ln259_64_reg_5890, "add_ln259_64_reg_5890");
sc_trace(mVcdFile, tmp_1_32_reg_5895, "tmp_1_32_reg_5895");
sc_trace(mVcdFile, grp_SIG0_fu_1130_ap_return, "grp_SIG0_fu_1130_ap_return");
sc_trace(mVcdFile, tmp_1_33_reg_5900, "tmp_1_33_reg_5900");
sc_trace(mVcdFile, add_ln280_8_fu_2193_p2, "add_ln280_8_fu_2193_p2");
sc_trace(mVcdFile, add_ln280_8_reg_5905, "add_ln280_8_reg_5905");
sc_trace(mVcdFile, add_ln284_8_fu_2204_p2, "add_ln284_8_fu_2204_p2");
sc_trace(mVcdFile, add_ln284_8_reg_5914, "add_ln284_8_reg_5914");
sc_trace(mVcdFile, m_36_fu_2215_p2, "m_36_fu_2215_p2");
sc_trace(mVcdFile, m_36_reg_5923, "m_36_reg_5923");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter3_reg, "m_36_reg_5923_pp0_iter3_reg");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter4_reg, "m_36_reg_5923_pp0_iter4_reg");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter5_reg, "m_36_reg_5923_pp0_iter5_reg");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter6_reg, "m_36_reg_5923_pp0_iter6_reg");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter7_reg, "m_36_reg_5923_pp0_iter7_reg");
sc_trace(mVcdFile, m_36_reg_5923_pp0_iter8_reg, "m_36_reg_5923_pp0_iter8_reg");
sc_trace(mVcdFile, m_37_fu_2227_p2, "m_37_fu_2227_p2");
sc_trace(mVcdFile, m_37_reg_5930, "m_37_reg_5930");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter3_reg, "m_37_reg_5930_pp0_iter3_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter4_reg, "m_37_reg_5930_pp0_iter4_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter5_reg, "m_37_reg_5930_pp0_iter5_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter6_reg, "m_37_reg_5930_pp0_iter6_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter7_reg, "m_37_reg_5930_pp0_iter7_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter8_reg, "m_37_reg_5930_pp0_iter8_reg");
sc_trace(mVcdFile, m_37_reg_5930_pp0_iter9_reg, "m_37_reg_5930_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln259_67_fu_2234_p2, "add_ln259_67_fu_2234_p2");
sc_trace(mVcdFile, add_ln259_67_reg_5937, "add_ln259_67_reg_5937");
sc_trace(mVcdFile, add_ln259_70_fu_2238_p2, "add_ln259_70_fu_2238_p2");
sc_trace(mVcdFile, add_ln259_70_reg_5942, "add_ln259_70_reg_5942");
sc_trace(mVcdFile, tmp_1_34_reg_5947, "tmp_1_34_reg_5947");
sc_trace(mVcdFile, tmp_1_35_reg_5952, "tmp_1_35_reg_5952");
sc_trace(mVcdFile, add_ln274_38_fu_2247_p2, "add_ln274_38_fu_2247_p2");
sc_trace(mVcdFile, add_ln274_38_reg_5957, "add_ln274_38_reg_5957");
sc_trace(mVcdFile, m_38_fu_2258_p2, "m_38_fu_2258_p2");
sc_trace(mVcdFile, m_38_reg_5962, "m_38_reg_5962");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter3_reg, "m_38_reg_5962_pp0_iter3_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter4_reg, "m_38_reg_5962_pp0_iter4_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter5_reg, "m_38_reg_5962_pp0_iter5_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter6_reg, "m_38_reg_5962_pp0_iter6_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter7_reg, "m_38_reg_5962_pp0_iter7_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter8_reg, "m_38_reg_5962_pp0_iter8_reg");
sc_trace(mVcdFile, m_38_reg_5962_pp0_iter9_reg, "m_38_reg_5962_pp0_iter9_reg");
sc_trace(mVcdFile, m_39_fu_2270_p2, "m_39_fu_2270_p2");
sc_trace(mVcdFile, m_39_reg_5969, "m_39_reg_5969");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter3_reg, "m_39_reg_5969_pp0_iter3_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter4_reg, "m_39_reg_5969_pp0_iter4_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter5_reg, "m_39_reg_5969_pp0_iter5_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter6_reg, "m_39_reg_5969_pp0_iter6_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter7_reg, "m_39_reg_5969_pp0_iter7_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter8_reg, "m_39_reg_5969_pp0_iter8_reg");
sc_trace(mVcdFile, m_39_reg_5969_pp0_iter9_reg, "m_39_reg_5969_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln259_73_fu_2277_p2, "add_ln259_73_fu_2277_p2");
sc_trace(mVcdFile, add_ln259_73_reg_5976, "add_ln259_73_reg_5976");
sc_trace(mVcdFile, add_ln259_76_fu_2281_p2, "add_ln259_76_fu_2281_p2");
sc_trace(mVcdFile, add_ln259_76_reg_5981, "add_ln259_76_reg_5981");
sc_trace(mVcdFile, tmp_1_36_reg_5986, "tmp_1_36_reg_5986");
sc_trace(mVcdFile, tmp_1_37_reg_5991, "tmp_1_37_reg_5991");
sc_trace(mVcdFile, add_ln280_9_fu_2295_p2, "add_ln280_9_fu_2295_p2");
sc_trace(mVcdFile, add_ln280_9_reg_5996, "add_ln280_9_reg_5996");
sc_trace(mVcdFile, add_ln284_9_fu_2306_p2, "add_ln284_9_fu_2306_p2");
sc_trace(mVcdFile, add_ln284_9_reg_6005, "add_ln284_9_reg_6005");
sc_trace(mVcdFile, m_40_fu_2317_p2, "m_40_fu_2317_p2");
sc_trace(mVcdFile, m_40_reg_6014, "m_40_reg_6014");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter3_reg, "m_40_reg_6014_pp0_iter3_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter4_reg, "m_40_reg_6014_pp0_iter4_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter5_reg, "m_40_reg_6014_pp0_iter5_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter6_reg, "m_40_reg_6014_pp0_iter6_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter7_reg, "m_40_reg_6014_pp0_iter7_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter8_reg, "m_40_reg_6014_pp0_iter8_reg");
sc_trace(mVcdFile, m_40_reg_6014_pp0_iter9_reg, "m_40_reg_6014_pp0_iter9_reg");
sc_trace(mVcdFile, m_41_fu_2329_p2, "m_41_fu_2329_p2");
sc_trace(mVcdFile, m_41_reg_6021, "m_41_reg_6021");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter3_reg, "m_41_reg_6021_pp0_iter3_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter4_reg, "m_41_reg_6021_pp0_iter4_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter5_reg, "m_41_reg_6021_pp0_iter5_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter6_reg, "m_41_reg_6021_pp0_iter6_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter7_reg, "m_41_reg_6021_pp0_iter7_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter8_reg, "m_41_reg_6021_pp0_iter8_reg");
sc_trace(mVcdFile, m_41_reg_6021_pp0_iter9_reg, "m_41_reg_6021_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln259_79_fu_2336_p2, "add_ln259_79_fu_2336_p2");
sc_trace(mVcdFile, add_ln259_79_reg_6028, "add_ln259_79_reg_6028");
sc_trace(mVcdFile, add_ln259_82_fu_2340_p2, "add_ln259_82_fu_2340_p2");
sc_trace(mVcdFile, add_ln259_82_reg_6033, "add_ln259_82_reg_6033");
sc_trace(mVcdFile, tmp_1_38_reg_6038, "tmp_1_38_reg_6038");
sc_trace(mVcdFile, tmp_1_39_reg_6043, "tmp_1_39_reg_6043");
sc_trace(mVcdFile, add_ln274_42_fu_2349_p2, "add_ln274_42_fu_2349_p2");
sc_trace(mVcdFile, add_ln274_42_reg_6048, "add_ln274_42_reg_6048");
sc_trace(mVcdFile, m_42_fu_2360_p2, "m_42_fu_2360_p2");
sc_trace(mVcdFile, m_42_reg_6053, "m_42_reg_6053");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter3_reg, "m_42_reg_6053_pp0_iter3_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter4_reg, "m_42_reg_6053_pp0_iter4_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter5_reg, "m_42_reg_6053_pp0_iter5_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter6_reg, "m_42_reg_6053_pp0_iter6_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter7_reg, "m_42_reg_6053_pp0_iter7_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter8_reg, "m_42_reg_6053_pp0_iter8_reg");
sc_trace(mVcdFile, m_42_reg_6053_pp0_iter9_reg, "m_42_reg_6053_pp0_iter9_reg");
sc_trace(mVcdFile, m_43_fu_2372_p2, "m_43_fu_2372_p2");
sc_trace(mVcdFile, m_43_reg_6060, "m_43_reg_6060");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter3_reg, "m_43_reg_6060_pp0_iter3_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter4_reg, "m_43_reg_6060_pp0_iter4_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter5_reg, "m_43_reg_6060_pp0_iter5_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter6_reg, "m_43_reg_6060_pp0_iter6_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter7_reg, "m_43_reg_6060_pp0_iter7_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter8_reg, "m_43_reg_6060_pp0_iter8_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter9_reg, "m_43_reg_6060_pp0_iter9_reg");
sc_trace(mVcdFile, m_43_reg_6060_pp0_iter10_reg, "m_43_reg_6060_pp0_iter10_reg");
sc_trace(mVcdFile, add_ln259_85_fu_2379_p2, "add_ln259_85_fu_2379_p2");
sc_trace(mVcdFile, add_ln259_85_reg_6067, "add_ln259_85_reg_6067");
sc_trace(mVcdFile, add_ln259_88_fu_2383_p2, "add_ln259_88_fu_2383_p2");
sc_trace(mVcdFile, add_ln259_88_reg_6072, "add_ln259_88_reg_6072");
sc_trace(mVcdFile, tmp_1_40_reg_6077, "tmp_1_40_reg_6077");
sc_trace(mVcdFile, tmp_1_41_reg_6082, "tmp_1_41_reg_6082");
sc_trace(mVcdFile, add_ln280_10_fu_2397_p2, "add_ln280_10_fu_2397_p2");
sc_trace(mVcdFile, add_ln280_10_reg_6087, "add_ln280_10_reg_6087");
sc_trace(mVcdFile, add_ln284_10_fu_2408_p2, "add_ln284_10_fu_2408_p2");
sc_trace(mVcdFile, add_ln284_10_reg_6096, "add_ln284_10_reg_6096");
sc_trace(mVcdFile, m_44_fu_2419_p2, "m_44_fu_2419_p2");
sc_trace(mVcdFile, m_44_reg_6105, "m_44_reg_6105");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter3_reg, "m_44_reg_6105_pp0_iter3_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter4_reg, "m_44_reg_6105_pp0_iter4_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter5_reg, "m_44_reg_6105_pp0_iter5_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter6_reg, "m_44_reg_6105_pp0_iter6_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter7_reg, "m_44_reg_6105_pp0_iter7_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter8_reg, "m_44_reg_6105_pp0_iter8_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter9_reg, "m_44_reg_6105_pp0_iter9_reg");
sc_trace(mVcdFile, m_44_reg_6105_pp0_iter10_reg, "m_44_reg_6105_pp0_iter10_reg");
sc_trace(mVcdFile, m_45_fu_2431_p2, "m_45_fu_2431_p2");
sc_trace(mVcdFile, m_45_reg_6112, "m_45_reg_6112");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter3_reg, "m_45_reg_6112_pp0_iter3_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter4_reg, "m_45_reg_6112_pp0_iter4_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter5_reg, "m_45_reg_6112_pp0_iter5_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter6_reg, "m_45_reg_6112_pp0_iter6_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter7_reg, "m_45_reg_6112_pp0_iter7_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter8_reg, "m_45_reg_6112_pp0_iter8_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter9_reg, "m_45_reg_6112_pp0_iter9_reg");
sc_trace(mVcdFile, m_45_reg_6112_pp0_iter10_reg, "m_45_reg_6112_pp0_iter10_reg");
sc_trace(mVcdFile, add_ln259_91_fu_2438_p2, "add_ln259_91_fu_2438_p2");
sc_trace(mVcdFile, add_ln259_91_reg_6119, "add_ln259_91_reg_6119");
sc_trace(mVcdFile, add_ln259_94_fu_2442_p2, "add_ln259_94_fu_2442_p2");
sc_trace(mVcdFile, add_ln259_94_reg_6124, "add_ln259_94_reg_6124");
sc_trace(mVcdFile, tmp_1_42_reg_6129, "tmp_1_42_reg_6129");
sc_trace(mVcdFile, tmp_1_43_reg_6134, "tmp_1_43_reg_6134");
sc_trace(mVcdFile, add_ln274_46_fu_2451_p2, "add_ln274_46_fu_2451_p2");
sc_trace(mVcdFile, add_ln274_46_reg_6139, "add_ln274_46_reg_6139");
sc_trace(mVcdFile, m_46_fu_2462_p2, "m_46_fu_2462_p2");
sc_trace(mVcdFile, m_46_reg_6144, "m_46_reg_6144");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter4_reg, "m_46_reg_6144_pp0_iter4_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter5_reg, "m_46_reg_6144_pp0_iter5_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter6_reg, "m_46_reg_6144_pp0_iter6_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter7_reg, "m_46_reg_6144_pp0_iter7_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter8_reg, "m_46_reg_6144_pp0_iter8_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter9_reg, "m_46_reg_6144_pp0_iter9_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter10_reg, "m_46_reg_6144_pp0_iter10_reg");
sc_trace(mVcdFile, m_46_reg_6144_pp0_iter11_reg, "m_46_reg_6144_pp0_iter11_reg");
sc_trace(mVcdFile, m_47_fu_2474_p2, "m_47_fu_2474_p2");
sc_trace(mVcdFile, m_47_reg_6151, "m_47_reg_6151");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter4_reg, "m_47_reg_6151_pp0_iter4_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter5_reg, "m_47_reg_6151_pp0_iter5_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter6_reg, "m_47_reg_6151_pp0_iter6_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter7_reg, "m_47_reg_6151_pp0_iter7_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter8_reg, "m_47_reg_6151_pp0_iter8_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter9_reg, "m_47_reg_6151_pp0_iter9_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter10_reg, "m_47_reg_6151_pp0_iter10_reg");
sc_trace(mVcdFile, m_47_reg_6151_pp0_iter11_reg, "m_47_reg_6151_pp0_iter11_reg");
sc_trace(mVcdFile, add_ln259_97_fu_2481_p2, "add_ln259_97_fu_2481_p2");
sc_trace(mVcdFile, add_ln259_97_reg_6158, "add_ln259_97_reg_6158");
sc_trace(mVcdFile, add_ln259_100_fu_2485_p2, "add_ln259_100_fu_2485_p2");
sc_trace(mVcdFile, add_ln259_100_reg_6163, "add_ln259_100_reg_6163");
sc_trace(mVcdFile, tmp_1_44_reg_6168, "tmp_1_44_reg_6168");
sc_trace(mVcdFile, tmp_1_45_reg_6173, "tmp_1_45_reg_6173");
sc_trace(mVcdFile, add_ln280_11_fu_2499_p2, "add_ln280_11_fu_2499_p2");
sc_trace(mVcdFile, add_ln280_11_reg_6178, "add_ln280_11_reg_6178");
sc_trace(mVcdFile, add_ln284_11_fu_2510_p2, "add_ln284_11_fu_2510_p2");
sc_trace(mVcdFile, add_ln284_11_reg_6187, "add_ln284_11_reg_6187");
sc_trace(mVcdFile, m_48_fu_2521_p2, "m_48_fu_2521_p2");
sc_trace(mVcdFile, m_48_reg_6196, "m_48_reg_6196");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter4_reg, "m_48_reg_6196_pp0_iter4_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter5_reg, "m_48_reg_6196_pp0_iter5_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter6_reg, "m_48_reg_6196_pp0_iter6_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter7_reg, "m_48_reg_6196_pp0_iter7_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter8_reg, "m_48_reg_6196_pp0_iter8_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter9_reg, "m_48_reg_6196_pp0_iter9_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter10_reg, "m_48_reg_6196_pp0_iter10_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter11_reg, "m_48_reg_6196_pp0_iter11_reg");
sc_trace(mVcdFile, m_48_reg_6196_pp0_iter12_reg, "m_48_reg_6196_pp0_iter12_reg");
sc_trace(mVcdFile, m_49_fu_2533_p2, "m_49_fu_2533_p2");
sc_trace(mVcdFile, m_49_reg_6202, "m_49_reg_6202");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter4_reg, "m_49_reg_6202_pp0_iter4_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter5_reg, "m_49_reg_6202_pp0_iter5_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter6_reg, "m_49_reg_6202_pp0_iter6_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter7_reg, "m_49_reg_6202_pp0_iter7_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter8_reg, "m_49_reg_6202_pp0_iter8_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter9_reg, "m_49_reg_6202_pp0_iter9_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter10_reg, "m_49_reg_6202_pp0_iter10_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter11_reg, "m_49_reg_6202_pp0_iter11_reg");
sc_trace(mVcdFile, m_49_reg_6202_pp0_iter12_reg, "m_49_reg_6202_pp0_iter12_reg");
sc_trace(mVcdFile, add_ln259_103_fu_2539_p2, "add_ln259_103_fu_2539_p2");
sc_trace(mVcdFile, add_ln259_103_reg_6208, "add_ln259_103_reg_6208");
sc_trace(mVcdFile, add_ln259_106_fu_2543_p2, "add_ln259_106_fu_2543_p2");
sc_trace(mVcdFile, add_ln259_106_reg_6213, "add_ln259_106_reg_6213");
sc_trace(mVcdFile, tmp_1_46_reg_6218, "tmp_1_46_reg_6218");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter4_reg, "tmp_1_46_reg_6218_pp0_iter4_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter5_reg, "tmp_1_46_reg_6218_pp0_iter5_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter6_reg, "tmp_1_46_reg_6218_pp0_iter6_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter7_reg, "tmp_1_46_reg_6218_pp0_iter7_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter8_reg, "tmp_1_46_reg_6218_pp0_iter8_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter9_reg, "tmp_1_46_reg_6218_pp0_iter9_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter10_reg, "tmp_1_46_reg_6218_pp0_iter10_reg");
sc_trace(mVcdFile, tmp_1_46_reg_6218_pp0_iter11_reg, "tmp_1_46_reg_6218_pp0_iter11_reg");
sc_trace(mVcdFile, add_ln274_50_fu_2552_p2, "add_ln274_50_fu_2552_p2");
sc_trace(mVcdFile, add_ln274_50_reg_6223, "add_ln274_50_reg_6223");
sc_trace(mVcdFile, m_50_fu_2563_p2, "m_50_fu_2563_p2");
sc_trace(mVcdFile, m_50_reg_6228, "m_50_reg_6228");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter4_reg, "m_50_reg_6228_pp0_iter4_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter5_reg, "m_50_reg_6228_pp0_iter5_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter6_reg, "m_50_reg_6228_pp0_iter6_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter7_reg, "m_50_reg_6228_pp0_iter7_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter8_reg, "m_50_reg_6228_pp0_iter8_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter9_reg, "m_50_reg_6228_pp0_iter9_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter10_reg, "m_50_reg_6228_pp0_iter10_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter11_reg, "m_50_reg_6228_pp0_iter11_reg");
sc_trace(mVcdFile, m_50_reg_6228_pp0_iter12_reg, "m_50_reg_6228_pp0_iter12_reg");
sc_trace(mVcdFile, m_51_fu_2574_p2, "m_51_fu_2574_p2");
sc_trace(mVcdFile, m_51_reg_6234, "m_51_reg_6234");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter4_reg, "m_51_reg_6234_pp0_iter4_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter5_reg, "m_51_reg_6234_pp0_iter5_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter6_reg, "m_51_reg_6234_pp0_iter6_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter7_reg, "m_51_reg_6234_pp0_iter7_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter8_reg, "m_51_reg_6234_pp0_iter8_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter9_reg, "m_51_reg_6234_pp0_iter9_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter10_reg, "m_51_reg_6234_pp0_iter10_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter11_reg, "m_51_reg_6234_pp0_iter11_reg");
sc_trace(mVcdFile, m_51_reg_6234_pp0_iter12_reg, "m_51_reg_6234_pp0_iter12_reg");
sc_trace(mVcdFile, add_ln259_109_fu_2580_p2, "add_ln259_109_fu_2580_p2");
sc_trace(mVcdFile, add_ln259_109_reg_6240, "add_ln259_109_reg_6240");
sc_trace(mVcdFile, add_ln259_112_fu_2584_p2, "add_ln259_112_fu_2584_p2");
sc_trace(mVcdFile, add_ln259_112_reg_6245, "add_ln259_112_reg_6245");
sc_trace(mVcdFile, add_ln280_12_fu_2598_p2, "add_ln280_12_fu_2598_p2");
sc_trace(mVcdFile, add_ln280_12_reg_6250, "add_ln280_12_reg_6250");
sc_trace(mVcdFile, add_ln284_12_fu_2609_p2, "add_ln284_12_fu_2609_p2");
sc_trace(mVcdFile, add_ln284_12_reg_6259, "add_ln284_12_reg_6259");
sc_trace(mVcdFile, m_52_fu_2620_p2, "m_52_fu_2620_p2");
sc_trace(mVcdFile, m_52_reg_6268, "m_52_reg_6268");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter4_reg, "m_52_reg_6268_pp0_iter4_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter5_reg, "m_52_reg_6268_pp0_iter5_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter6_reg, "m_52_reg_6268_pp0_iter6_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter7_reg, "m_52_reg_6268_pp0_iter7_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter8_reg, "m_52_reg_6268_pp0_iter8_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter9_reg, "m_52_reg_6268_pp0_iter9_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter10_reg, "m_52_reg_6268_pp0_iter10_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter11_reg, "m_52_reg_6268_pp0_iter11_reg");
sc_trace(mVcdFile, m_52_reg_6268_pp0_iter12_reg, "m_52_reg_6268_pp0_iter12_reg");
sc_trace(mVcdFile, m_53_fu_2631_p2, "m_53_fu_2631_p2");
sc_trace(mVcdFile, m_53_reg_6274, "m_53_reg_6274");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter4_reg, "m_53_reg_6274_pp0_iter4_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter5_reg, "m_53_reg_6274_pp0_iter5_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter6_reg, "m_53_reg_6274_pp0_iter6_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter7_reg, "m_53_reg_6274_pp0_iter7_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter8_reg, "m_53_reg_6274_pp0_iter8_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter9_reg, "m_53_reg_6274_pp0_iter9_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter10_reg, "m_53_reg_6274_pp0_iter10_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter11_reg, "m_53_reg_6274_pp0_iter11_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter12_reg, "m_53_reg_6274_pp0_iter12_reg");
sc_trace(mVcdFile, m_53_reg_6274_pp0_iter13_reg, "m_53_reg_6274_pp0_iter13_reg");
sc_trace(mVcdFile, add_ln259_115_fu_2637_p2, "add_ln259_115_fu_2637_p2");
sc_trace(mVcdFile, add_ln259_115_reg_6280, "add_ln259_115_reg_6280");
sc_trace(mVcdFile, add_ln259_118_fu_2641_p2, "add_ln259_118_fu_2641_p2");
sc_trace(mVcdFile, add_ln259_118_reg_6285, "add_ln259_118_reg_6285");
sc_trace(mVcdFile, add_ln274_54_fu_2650_p2, "add_ln274_54_fu_2650_p2");
sc_trace(mVcdFile, add_ln274_54_reg_6290, "add_ln274_54_reg_6290");
sc_trace(mVcdFile, m_54_fu_2660_p2, "m_54_fu_2660_p2");
sc_trace(mVcdFile, m_54_reg_6295, "m_54_reg_6295");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter4_reg, "m_54_reg_6295_pp0_iter4_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter5_reg, "m_54_reg_6295_pp0_iter5_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter6_reg, "m_54_reg_6295_pp0_iter6_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter7_reg, "m_54_reg_6295_pp0_iter7_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter8_reg, "m_54_reg_6295_pp0_iter8_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter9_reg, "m_54_reg_6295_pp0_iter9_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter10_reg, "m_54_reg_6295_pp0_iter10_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter11_reg, "m_54_reg_6295_pp0_iter11_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter12_reg, "m_54_reg_6295_pp0_iter12_reg");
sc_trace(mVcdFile, m_54_reg_6295_pp0_iter13_reg, "m_54_reg_6295_pp0_iter13_reg");
sc_trace(mVcdFile, m_55_fu_2671_p2, "m_55_fu_2671_p2");
sc_trace(mVcdFile, m_55_reg_6301, "m_55_reg_6301");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter4_reg, "m_55_reg_6301_pp0_iter4_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter5_reg, "m_55_reg_6301_pp0_iter5_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter6_reg, "m_55_reg_6301_pp0_iter6_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter7_reg, "m_55_reg_6301_pp0_iter7_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter8_reg, "m_55_reg_6301_pp0_iter8_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter9_reg, "m_55_reg_6301_pp0_iter9_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter10_reg, "m_55_reg_6301_pp0_iter10_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter11_reg, "m_55_reg_6301_pp0_iter11_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter12_reg, "m_55_reg_6301_pp0_iter12_reg");
sc_trace(mVcdFile, m_55_reg_6301_pp0_iter13_reg, "m_55_reg_6301_pp0_iter13_reg");
sc_trace(mVcdFile, add_ln259_121_fu_2677_p2, "add_ln259_121_fu_2677_p2");
sc_trace(mVcdFile, add_ln259_121_reg_6307, "add_ln259_121_reg_6307");
sc_trace(mVcdFile, add_ln259_124_fu_2681_p2, "add_ln259_124_fu_2681_p2");
sc_trace(mVcdFile, add_ln259_124_reg_6312, "add_ln259_124_reg_6312");
sc_trace(mVcdFile, add_ln280_13_fu_2696_p2, "add_ln280_13_fu_2696_p2");
sc_trace(mVcdFile, add_ln280_13_reg_6317, "add_ln280_13_reg_6317");
sc_trace(mVcdFile, add_ln284_13_fu_2707_p2, "add_ln284_13_fu_2707_p2");
sc_trace(mVcdFile, add_ln284_13_reg_6326, "add_ln284_13_reg_6326");
sc_trace(mVcdFile, m_56_fu_2718_p2, "m_56_fu_2718_p2");
sc_trace(mVcdFile, m_56_reg_6335, "m_56_reg_6335");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter4_reg, "m_56_reg_6335_pp0_iter4_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter5_reg, "m_56_reg_6335_pp0_iter5_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter6_reg, "m_56_reg_6335_pp0_iter6_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter7_reg, "m_56_reg_6335_pp0_iter7_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter8_reg, "m_56_reg_6335_pp0_iter8_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter9_reg, "m_56_reg_6335_pp0_iter9_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter10_reg, "m_56_reg_6335_pp0_iter10_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter11_reg, "m_56_reg_6335_pp0_iter11_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter12_reg, "m_56_reg_6335_pp0_iter12_reg");
sc_trace(mVcdFile, m_56_reg_6335_pp0_iter13_reg, "m_56_reg_6335_pp0_iter13_reg");
sc_trace(mVcdFile, m_57_fu_2729_p2, "m_57_fu_2729_p2");
sc_trace(mVcdFile, m_57_reg_6341, "m_57_reg_6341");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter4_reg, "m_57_reg_6341_pp0_iter4_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter5_reg, "m_57_reg_6341_pp0_iter5_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter6_reg, "m_57_reg_6341_pp0_iter6_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter7_reg, "m_57_reg_6341_pp0_iter7_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter8_reg, "m_57_reg_6341_pp0_iter8_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter9_reg, "m_57_reg_6341_pp0_iter9_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter10_reg, "m_57_reg_6341_pp0_iter10_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter11_reg, "m_57_reg_6341_pp0_iter11_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter12_reg, "m_57_reg_6341_pp0_iter12_reg");
sc_trace(mVcdFile, m_57_reg_6341_pp0_iter13_reg, "m_57_reg_6341_pp0_iter13_reg");
sc_trace(mVcdFile, add_ln259_127_fu_2735_p2, "add_ln259_127_fu_2735_p2");
sc_trace(mVcdFile, add_ln259_127_reg_6346, "add_ln259_127_reg_6346");
sc_trace(mVcdFile, add_ln259_130_fu_2739_p2, "add_ln259_130_fu_2739_p2");
sc_trace(mVcdFile, add_ln259_130_reg_6351, "add_ln259_130_reg_6351");
sc_trace(mVcdFile, add_ln274_58_fu_2748_p2, "add_ln274_58_fu_2748_p2");
sc_trace(mVcdFile, add_ln274_58_reg_6356, "add_ln274_58_reg_6356");
sc_trace(mVcdFile, m_58_fu_2758_p2, "m_58_fu_2758_p2");
sc_trace(mVcdFile, m_58_reg_6361, "m_58_reg_6361");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter4_reg, "m_58_reg_6361_pp0_iter4_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter5_reg, "m_58_reg_6361_pp0_iter5_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter6_reg, "m_58_reg_6361_pp0_iter6_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter7_reg, "m_58_reg_6361_pp0_iter7_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter8_reg, "m_58_reg_6361_pp0_iter8_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter9_reg, "m_58_reg_6361_pp0_iter9_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter10_reg, "m_58_reg_6361_pp0_iter10_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter11_reg, "m_58_reg_6361_pp0_iter11_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter12_reg, "m_58_reg_6361_pp0_iter12_reg");
sc_trace(mVcdFile, m_58_reg_6361_pp0_iter13_reg, "m_58_reg_6361_pp0_iter13_reg");
sc_trace(mVcdFile, m_59_fu_2769_p2, "m_59_fu_2769_p2");
sc_trace(mVcdFile, m_59_reg_6366, "m_59_reg_6366");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter4_reg, "m_59_reg_6366_pp0_iter4_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter5_reg, "m_59_reg_6366_pp0_iter5_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter6_reg, "m_59_reg_6366_pp0_iter6_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter7_reg, "m_59_reg_6366_pp0_iter7_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter8_reg, "m_59_reg_6366_pp0_iter8_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter9_reg, "m_59_reg_6366_pp0_iter9_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter10_reg, "m_59_reg_6366_pp0_iter10_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter11_reg, "m_59_reg_6366_pp0_iter11_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter12_reg, "m_59_reg_6366_pp0_iter12_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter13_reg, "m_59_reg_6366_pp0_iter13_reg");
sc_trace(mVcdFile, m_59_reg_6366_pp0_iter14_reg, "m_59_reg_6366_pp0_iter14_reg");
sc_trace(mVcdFile, add_ln259_133_fu_2775_p2, "add_ln259_133_fu_2775_p2");
sc_trace(mVcdFile, add_ln259_133_reg_6371, "add_ln259_133_reg_6371");
sc_trace(mVcdFile, add_ln259_136_fu_2779_p2, "add_ln259_136_fu_2779_p2");
sc_trace(mVcdFile, add_ln259_136_reg_6376, "add_ln259_136_reg_6376");
sc_trace(mVcdFile, add_ln280_14_fu_2794_p2, "add_ln280_14_fu_2794_p2");
sc_trace(mVcdFile, add_ln280_14_reg_6381, "add_ln280_14_reg_6381");
sc_trace(mVcdFile, add_ln284_14_fu_2805_p2, "add_ln284_14_fu_2805_p2");
sc_trace(mVcdFile, add_ln284_14_reg_6390, "add_ln284_14_reg_6390");
sc_trace(mVcdFile, m_60_fu_2816_p2, "m_60_fu_2816_p2");
sc_trace(mVcdFile, m_60_reg_6399, "m_60_reg_6399");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter4_reg, "m_60_reg_6399_pp0_iter4_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter5_reg, "m_60_reg_6399_pp0_iter5_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter6_reg, "m_60_reg_6399_pp0_iter6_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter7_reg, "m_60_reg_6399_pp0_iter7_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter8_reg, "m_60_reg_6399_pp0_iter8_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter9_reg, "m_60_reg_6399_pp0_iter9_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter10_reg, "m_60_reg_6399_pp0_iter10_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter11_reg, "m_60_reg_6399_pp0_iter11_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter12_reg, "m_60_reg_6399_pp0_iter12_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter13_reg, "m_60_reg_6399_pp0_iter13_reg");
sc_trace(mVcdFile, m_60_reg_6399_pp0_iter14_reg, "m_60_reg_6399_pp0_iter14_reg");
sc_trace(mVcdFile, m_61_fu_2827_p2, "m_61_fu_2827_p2");
sc_trace(mVcdFile, m_61_reg_6404, "m_61_reg_6404");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter4_reg, "m_61_reg_6404_pp0_iter4_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter5_reg, "m_61_reg_6404_pp0_iter5_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter6_reg, "m_61_reg_6404_pp0_iter6_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter7_reg, "m_61_reg_6404_pp0_iter7_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter8_reg, "m_61_reg_6404_pp0_iter8_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter9_reg, "m_61_reg_6404_pp0_iter9_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter10_reg, "m_61_reg_6404_pp0_iter10_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter11_reg, "m_61_reg_6404_pp0_iter11_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter12_reg, "m_61_reg_6404_pp0_iter12_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter13_reg, "m_61_reg_6404_pp0_iter13_reg");
sc_trace(mVcdFile, m_61_reg_6404_pp0_iter14_reg, "m_61_reg_6404_pp0_iter14_reg");
sc_trace(mVcdFile, tmp_47_reg_6409, "tmp_47_reg_6409");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter4_reg, "tmp_47_reg_6409_pp0_iter4_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter5_reg, "tmp_47_reg_6409_pp0_iter5_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter6_reg, "tmp_47_reg_6409_pp0_iter6_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter7_reg, "tmp_47_reg_6409_pp0_iter7_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter8_reg, "tmp_47_reg_6409_pp0_iter8_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter9_reg, "tmp_47_reg_6409_pp0_iter9_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter10_reg, "tmp_47_reg_6409_pp0_iter10_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter11_reg, "tmp_47_reg_6409_pp0_iter11_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter12_reg, "tmp_47_reg_6409_pp0_iter12_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter13_reg, "tmp_47_reg_6409_pp0_iter13_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter14_reg, "tmp_47_reg_6409_pp0_iter14_reg");
sc_trace(mVcdFile, tmp_47_reg_6409_pp0_iter15_reg, "tmp_47_reg_6409_pp0_iter15_reg");
sc_trace(mVcdFile, add_ln274_62_fu_2838_p2, "add_ln274_62_fu_2838_p2");
sc_trace(mVcdFile, add_ln274_62_reg_6414, "add_ln274_62_reg_6414");
sc_trace(mVcdFile, add_ln280_15_fu_2854_p2, "add_ln280_15_fu_2854_p2");
sc_trace(mVcdFile, add_ln280_15_reg_6419, "add_ln280_15_reg_6419");
sc_trace(mVcdFile, add_ln284_15_fu_2865_p2, "add_ln284_15_fu_2865_p2");
sc_trace(mVcdFile, add_ln284_15_reg_6428, "add_ln284_15_reg_6428");
sc_trace(mVcdFile, add_ln274_254_fu_2880_p2, "add_ln274_254_fu_2880_p2");
sc_trace(mVcdFile, add_ln274_254_reg_6437, "add_ln274_254_reg_6437");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter5_reg, "add_ln274_254_reg_6437_pp0_iter5_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter6_reg, "add_ln274_254_reg_6437_pp0_iter6_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter7_reg, "add_ln274_254_reg_6437_pp0_iter7_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter8_reg, "add_ln274_254_reg_6437_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter9_reg, "add_ln274_254_reg_6437_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter10_reg, "add_ln274_254_reg_6437_pp0_iter10_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter11_reg, "add_ln274_254_reg_6437_pp0_iter11_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter12_reg, "add_ln274_254_reg_6437_pp0_iter12_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter13_reg, "add_ln274_254_reg_6437_pp0_iter13_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter14_reg, "add_ln274_254_reg_6437_pp0_iter14_reg");
sc_trace(mVcdFile, add_ln274_254_reg_6437_pp0_iter15_reg, "add_ln274_254_reg_6437_pp0_iter15_reg");
sc_trace(mVcdFile, add_ln274_66_fu_2891_p2, "add_ln274_66_fu_2891_p2");
sc_trace(mVcdFile, add_ln274_66_reg_6442, "add_ln274_66_reg_6442");
sc_trace(mVcdFile, add_ln280_16_fu_2907_p2, "add_ln280_16_fu_2907_p2");
sc_trace(mVcdFile, add_ln280_16_reg_6447, "add_ln280_16_reg_6447");
sc_trace(mVcdFile, add_ln284_16_fu_2918_p2, "add_ln284_16_fu_2918_p2");
sc_trace(mVcdFile, add_ln284_16_reg_6456, "add_ln284_16_reg_6456");
sc_trace(mVcdFile, add_ln274_70_fu_2929_p2, "add_ln274_70_fu_2929_p2");
sc_trace(mVcdFile, add_ln274_70_reg_6465, "add_ln274_70_reg_6465");
sc_trace(mVcdFile, add_ln280_17_fu_2945_p2, "add_ln280_17_fu_2945_p2");
sc_trace(mVcdFile, add_ln280_17_reg_6470, "add_ln280_17_reg_6470");
sc_trace(mVcdFile, add_ln284_17_fu_2956_p2, "add_ln284_17_fu_2956_p2");
sc_trace(mVcdFile, add_ln284_17_reg_6479, "add_ln284_17_reg_6479");
sc_trace(mVcdFile, add_ln274_74_fu_2967_p2, "add_ln274_74_fu_2967_p2");
sc_trace(mVcdFile, add_ln274_74_reg_6488, "add_ln274_74_reg_6488");
sc_trace(mVcdFile, add_ln280_18_fu_2983_p2, "add_ln280_18_fu_2983_p2");
sc_trace(mVcdFile, add_ln280_18_reg_6493, "add_ln280_18_reg_6493");
sc_trace(mVcdFile, add_ln284_18_fu_2994_p2, "add_ln284_18_fu_2994_p2");
sc_trace(mVcdFile, add_ln284_18_reg_6502, "add_ln284_18_reg_6502");
sc_trace(mVcdFile, add_ln274_78_fu_3005_p2, "add_ln274_78_fu_3005_p2");
sc_trace(mVcdFile, add_ln274_78_reg_6511, "add_ln274_78_reg_6511");
sc_trace(mVcdFile, add_ln280_19_fu_3021_p2, "add_ln280_19_fu_3021_p2");
sc_trace(mVcdFile, add_ln280_19_reg_6516, "add_ln280_19_reg_6516");
sc_trace(mVcdFile, add_ln284_19_fu_3032_p2, "add_ln284_19_fu_3032_p2");
sc_trace(mVcdFile, add_ln284_19_reg_6525, "add_ln284_19_reg_6525");
sc_trace(mVcdFile, add_ln274_82_fu_3043_p2, "add_ln274_82_fu_3043_p2");
sc_trace(mVcdFile, add_ln274_82_reg_6534, "add_ln274_82_reg_6534");
sc_trace(mVcdFile, add_ln280_20_fu_3059_p2, "add_ln280_20_fu_3059_p2");
sc_trace(mVcdFile, add_ln280_20_reg_6539, "add_ln280_20_reg_6539");
sc_trace(mVcdFile, add_ln284_20_fu_3070_p2, "add_ln284_20_fu_3070_p2");
sc_trace(mVcdFile, add_ln284_20_reg_6548, "add_ln284_20_reg_6548");
sc_trace(mVcdFile, add_ln274_86_fu_3081_p2, "add_ln274_86_fu_3081_p2");
sc_trace(mVcdFile, add_ln274_86_reg_6557, "add_ln274_86_reg_6557");
sc_trace(mVcdFile, add_ln280_21_fu_3097_p2, "add_ln280_21_fu_3097_p2");
sc_trace(mVcdFile, add_ln280_21_reg_6562, "add_ln280_21_reg_6562");
sc_trace(mVcdFile, add_ln284_21_fu_3108_p2, "add_ln284_21_fu_3108_p2");
sc_trace(mVcdFile, add_ln284_21_reg_6571, "add_ln284_21_reg_6571");
sc_trace(mVcdFile, add_ln274_90_fu_3119_p2, "add_ln274_90_fu_3119_p2");
sc_trace(mVcdFile, add_ln274_90_reg_6580, "add_ln274_90_reg_6580");
sc_trace(mVcdFile, add_ln280_22_fu_3135_p2, "add_ln280_22_fu_3135_p2");
sc_trace(mVcdFile, add_ln280_22_reg_6585, "add_ln280_22_reg_6585");
sc_trace(mVcdFile, add_ln284_22_fu_3146_p2, "add_ln284_22_fu_3146_p2");
sc_trace(mVcdFile, add_ln284_22_reg_6594, "add_ln284_22_reg_6594");
sc_trace(mVcdFile, add_ln274_94_fu_3157_p2, "add_ln274_94_fu_3157_p2");
sc_trace(mVcdFile, add_ln274_94_reg_6603, "add_ln274_94_reg_6603");
sc_trace(mVcdFile, add_ln280_23_fu_3173_p2, "add_ln280_23_fu_3173_p2");
sc_trace(mVcdFile, add_ln280_23_reg_6608, "add_ln280_23_reg_6608");
sc_trace(mVcdFile, add_ln284_23_fu_3184_p2, "add_ln284_23_fu_3184_p2");
sc_trace(mVcdFile, add_ln284_23_reg_6617, "add_ln284_23_reg_6617");
sc_trace(mVcdFile, add_ln274_98_fu_3195_p2, "add_ln274_98_fu_3195_p2");
sc_trace(mVcdFile, add_ln274_98_reg_6626, "add_ln274_98_reg_6626");
sc_trace(mVcdFile, add_ln280_24_fu_3211_p2, "add_ln280_24_fu_3211_p2");
sc_trace(mVcdFile, add_ln280_24_reg_6631, "add_ln280_24_reg_6631");
sc_trace(mVcdFile, add_ln284_24_fu_3222_p2, "add_ln284_24_fu_3222_p2");
sc_trace(mVcdFile, add_ln284_24_reg_6640, "add_ln284_24_reg_6640");
sc_trace(mVcdFile, add_ln274_102_fu_3233_p2, "add_ln274_102_fu_3233_p2");
sc_trace(mVcdFile, add_ln274_102_reg_6649, "add_ln274_102_reg_6649");
sc_trace(mVcdFile, add_ln280_25_fu_3249_p2, "add_ln280_25_fu_3249_p2");
sc_trace(mVcdFile, add_ln280_25_reg_6654, "add_ln280_25_reg_6654");
sc_trace(mVcdFile, add_ln284_25_fu_3260_p2, "add_ln284_25_fu_3260_p2");
sc_trace(mVcdFile, add_ln284_25_reg_6663, "add_ln284_25_reg_6663");
sc_trace(mVcdFile, add_ln274_106_fu_3271_p2, "add_ln274_106_fu_3271_p2");
sc_trace(mVcdFile, add_ln274_106_reg_6672, "add_ln274_106_reg_6672");
sc_trace(mVcdFile, add_ln280_26_fu_3287_p2, "add_ln280_26_fu_3287_p2");
sc_trace(mVcdFile, add_ln280_26_reg_6677, "add_ln280_26_reg_6677");
sc_trace(mVcdFile, add_ln284_26_fu_3298_p2, "add_ln284_26_fu_3298_p2");
sc_trace(mVcdFile, add_ln284_26_reg_6686, "add_ln284_26_reg_6686");
sc_trace(mVcdFile, add_ln274_110_fu_3309_p2, "add_ln274_110_fu_3309_p2");
sc_trace(mVcdFile, add_ln274_110_reg_6695, "add_ln274_110_reg_6695");
sc_trace(mVcdFile, add_ln280_27_fu_3325_p2, "add_ln280_27_fu_3325_p2");
sc_trace(mVcdFile, add_ln280_27_reg_6700, "add_ln280_27_reg_6700");
sc_trace(mVcdFile, add_ln284_27_fu_3336_p2, "add_ln284_27_fu_3336_p2");
sc_trace(mVcdFile, add_ln284_27_reg_6709, "add_ln284_27_reg_6709");
sc_trace(mVcdFile, add_ln274_114_fu_3347_p2, "add_ln274_114_fu_3347_p2");
sc_trace(mVcdFile, add_ln274_114_reg_6718, "add_ln274_114_reg_6718");
sc_trace(mVcdFile, add_ln280_28_fu_3363_p2, "add_ln280_28_fu_3363_p2");
sc_trace(mVcdFile, add_ln280_28_reg_6723, "add_ln280_28_reg_6723");
sc_trace(mVcdFile, add_ln284_28_fu_3374_p2, "add_ln284_28_fu_3374_p2");
sc_trace(mVcdFile, add_ln284_28_reg_6732, "add_ln284_28_reg_6732");
sc_trace(mVcdFile, add_ln274_118_fu_3385_p2, "add_ln274_118_fu_3385_p2");
sc_trace(mVcdFile, add_ln274_118_reg_6741, "add_ln274_118_reg_6741");
sc_trace(mVcdFile, add_ln280_29_fu_3401_p2, "add_ln280_29_fu_3401_p2");
sc_trace(mVcdFile, add_ln280_29_reg_6746, "add_ln280_29_reg_6746");
sc_trace(mVcdFile, add_ln280_29_reg_6746_pp0_iter8_reg, "add_ln280_29_reg_6746_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln284_29_fu_3412_p2, "add_ln284_29_fu_3412_p2");
sc_trace(mVcdFile, add_ln284_29_reg_6755, "add_ln284_29_reg_6755");
sc_trace(mVcdFile, add_ln284_29_reg_6755_pp0_iter8_reg, "add_ln284_29_reg_6755_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln274_122_fu_3423_p2, "add_ln274_122_fu_3423_p2");
sc_trace(mVcdFile, add_ln274_122_reg_6764, "add_ln274_122_reg_6764");
sc_trace(mVcdFile, add_ln280_30_fu_3439_p2, "add_ln280_30_fu_3439_p2");
sc_trace(mVcdFile, add_ln280_30_reg_6769, "add_ln280_30_reg_6769");
sc_trace(mVcdFile, add_ln280_30_reg_6769_pp0_iter8_reg, "add_ln280_30_reg_6769_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln284_30_fu_3450_p2, "add_ln284_30_fu_3450_p2");
sc_trace(mVcdFile, add_ln284_30_reg_6778, "add_ln284_30_reg_6778");
sc_trace(mVcdFile, add_ln284_30_reg_6778_pp0_iter8_reg, "add_ln284_30_reg_6778_pp0_iter8_reg");
sc_trace(mVcdFile, add_ln274_126_fu_3461_p2, "add_ln274_126_fu_3461_p2");
sc_trace(mVcdFile, add_ln274_126_reg_6787, "add_ln274_126_reg_6787");
sc_trace(mVcdFile, add_ln280_31_fu_3477_p2, "add_ln280_31_fu_3477_p2");
sc_trace(mVcdFile, add_ln280_31_reg_6792, "add_ln280_31_reg_6792");
sc_trace(mVcdFile, add_ln280_31_reg_6792_pp0_iter9_reg, "add_ln280_31_reg_6792_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln284_31_fu_3488_p2, "add_ln284_31_fu_3488_p2");
sc_trace(mVcdFile, add_ln284_31_reg_6801, "add_ln284_31_reg_6801");
sc_trace(mVcdFile, add_ln284_31_reg_6801_pp0_iter9_reg, "add_ln284_31_reg_6801_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln274_130_fu_3499_p2, "add_ln274_130_fu_3499_p2");
sc_trace(mVcdFile, add_ln274_130_reg_6810, "add_ln274_130_reg_6810");
sc_trace(mVcdFile, add_ln280_32_fu_3515_p2, "add_ln280_32_fu_3515_p2");
sc_trace(mVcdFile, add_ln280_32_reg_6815, "add_ln280_32_reg_6815");
sc_trace(mVcdFile, add_ln280_32_reg_6815_pp0_iter9_reg, "add_ln280_32_reg_6815_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln284_32_fu_3526_p2, "add_ln284_32_fu_3526_p2");
sc_trace(mVcdFile, add_ln284_32_reg_6824, "add_ln284_32_reg_6824");
sc_trace(mVcdFile, add_ln284_32_reg_6824_pp0_iter9_reg, "add_ln284_32_reg_6824_pp0_iter9_reg");
sc_trace(mVcdFile, add_ln274_134_fu_3537_p2, "add_ln274_134_fu_3537_p2");
sc_trace(mVcdFile, add_ln274_134_reg_6833, "add_ln274_134_reg_6833");
sc_trace(mVcdFile, add_ln280_33_fu_3553_p2, "add_ln280_33_fu_3553_p2");
sc_trace(mVcdFile, add_ln280_33_reg_6838, "add_ln280_33_reg_6838");
sc_trace(mVcdFile, add_ln284_33_fu_3564_p2, "add_ln284_33_fu_3564_p2");
sc_trace(mVcdFile, add_ln284_33_reg_6847, "add_ln284_33_reg_6847");
sc_trace(mVcdFile, add_ln274_138_fu_3575_p2, "add_ln274_138_fu_3575_p2");
sc_trace(mVcdFile, add_ln274_138_reg_6856, "add_ln274_138_reg_6856");
sc_trace(mVcdFile, add_ln280_34_fu_3591_p2, "add_ln280_34_fu_3591_p2");
sc_trace(mVcdFile, add_ln280_34_reg_6861, "add_ln280_34_reg_6861");
sc_trace(mVcdFile, add_ln284_34_fu_3602_p2, "add_ln284_34_fu_3602_p2");
sc_trace(mVcdFile, add_ln284_34_reg_6870, "add_ln284_34_reg_6870");
sc_trace(mVcdFile, add_ln274_142_fu_3613_p2, "add_ln274_142_fu_3613_p2");
sc_trace(mVcdFile, add_ln274_142_reg_6879, "add_ln274_142_reg_6879");
sc_trace(mVcdFile, add_ln280_35_fu_3629_p2, "add_ln280_35_fu_3629_p2");
sc_trace(mVcdFile, add_ln280_35_reg_6884, "add_ln280_35_reg_6884");
sc_trace(mVcdFile, add_ln284_35_fu_3640_p2, "add_ln284_35_fu_3640_p2");
sc_trace(mVcdFile, add_ln284_35_reg_6893, "add_ln284_35_reg_6893");
sc_trace(mVcdFile, add_ln274_146_fu_3651_p2, "add_ln274_146_fu_3651_p2");
sc_trace(mVcdFile, add_ln274_146_reg_6902, "add_ln274_146_reg_6902");
sc_trace(mVcdFile, add_ln280_36_fu_3667_p2, "add_ln280_36_fu_3667_p2");
sc_trace(mVcdFile, add_ln280_36_reg_6907, "add_ln280_36_reg_6907");
sc_trace(mVcdFile, add_ln284_36_fu_3678_p2, "add_ln284_36_fu_3678_p2");
sc_trace(mVcdFile, add_ln284_36_reg_6916, "add_ln284_36_reg_6916");
sc_trace(mVcdFile, add_ln274_150_fu_3689_p2, "add_ln274_150_fu_3689_p2");
sc_trace(mVcdFile, add_ln274_150_reg_6925, "add_ln274_150_reg_6925");
sc_trace(mVcdFile, add_ln280_37_fu_3705_p2, "add_ln280_37_fu_3705_p2");
sc_trace(mVcdFile, add_ln280_37_reg_6930, "add_ln280_37_reg_6930");
sc_trace(mVcdFile, add_ln284_37_fu_3716_p2, "add_ln284_37_fu_3716_p2");
sc_trace(mVcdFile, add_ln284_37_reg_6939, "add_ln284_37_reg_6939");
sc_trace(mVcdFile, add_ln274_154_fu_3727_p2, "add_ln274_154_fu_3727_p2");
sc_trace(mVcdFile, add_ln274_154_reg_6948, "add_ln274_154_reg_6948");
sc_trace(mVcdFile, add_ln280_38_fu_3743_p2, "add_ln280_38_fu_3743_p2");
sc_trace(mVcdFile, add_ln280_38_reg_6953, "add_ln280_38_reg_6953");
sc_trace(mVcdFile, add_ln284_38_fu_3754_p2, "add_ln284_38_fu_3754_p2");
sc_trace(mVcdFile, add_ln284_38_reg_6962, "add_ln284_38_reg_6962");
sc_trace(mVcdFile, add_ln274_158_fu_3765_p2, "add_ln274_158_fu_3765_p2");
sc_trace(mVcdFile, add_ln274_158_reg_6971, "add_ln274_158_reg_6971");
sc_trace(mVcdFile, add_ln280_39_fu_3781_p2, "add_ln280_39_fu_3781_p2");
sc_trace(mVcdFile, add_ln280_39_reg_6976, "add_ln280_39_reg_6976");
sc_trace(mVcdFile, add_ln284_39_fu_3792_p2, "add_ln284_39_fu_3792_p2");
sc_trace(mVcdFile, add_ln284_39_reg_6985, "add_ln284_39_reg_6985");
sc_trace(mVcdFile, add_ln274_162_fu_3803_p2, "add_ln274_162_fu_3803_p2");
sc_trace(mVcdFile, add_ln274_162_reg_6994, "add_ln274_162_reg_6994");
sc_trace(mVcdFile, add_ln280_40_fu_3819_p2, "add_ln280_40_fu_3819_p2");
sc_trace(mVcdFile, add_ln280_40_reg_6999, "add_ln280_40_reg_6999");
sc_trace(mVcdFile, add_ln284_40_fu_3830_p2, "add_ln284_40_fu_3830_p2");
sc_trace(mVcdFile, add_ln284_40_reg_7008, "add_ln284_40_reg_7008");
sc_trace(mVcdFile, add_ln274_166_fu_3841_p2, "add_ln274_166_fu_3841_p2");
sc_trace(mVcdFile, add_ln274_166_reg_7017, "add_ln274_166_reg_7017");
sc_trace(mVcdFile, add_ln280_41_fu_3857_p2, "add_ln280_41_fu_3857_p2");
sc_trace(mVcdFile, add_ln280_41_reg_7022, "add_ln280_41_reg_7022");
sc_trace(mVcdFile, add_ln284_41_fu_3868_p2, "add_ln284_41_fu_3868_p2");
sc_trace(mVcdFile, add_ln284_41_reg_7031, "add_ln284_41_reg_7031");
sc_trace(mVcdFile, add_ln274_170_fu_3879_p2, "add_ln274_170_fu_3879_p2");
sc_trace(mVcdFile, add_ln274_170_reg_7040, "add_ln274_170_reg_7040");
sc_trace(mVcdFile, add_ln280_42_fu_3895_p2, "add_ln280_42_fu_3895_p2");
sc_trace(mVcdFile, add_ln280_42_reg_7045, "add_ln280_42_reg_7045");
sc_trace(mVcdFile, add_ln284_42_fu_3906_p2, "add_ln284_42_fu_3906_p2");
sc_trace(mVcdFile, add_ln284_42_reg_7054, "add_ln284_42_reg_7054");
sc_trace(mVcdFile, add_ln274_174_fu_3917_p2, "add_ln274_174_fu_3917_p2");
sc_trace(mVcdFile, add_ln274_174_reg_7063, "add_ln274_174_reg_7063");
sc_trace(mVcdFile, add_ln280_43_fu_3933_p2, "add_ln280_43_fu_3933_p2");
sc_trace(mVcdFile, add_ln280_43_reg_7068, "add_ln280_43_reg_7068");
sc_trace(mVcdFile, add_ln284_43_fu_3944_p2, "add_ln284_43_fu_3944_p2");
sc_trace(mVcdFile, add_ln284_43_reg_7077, "add_ln284_43_reg_7077");
sc_trace(mVcdFile, add_ln274_178_fu_3955_p2, "add_ln274_178_fu_3955_p2");
sc_trace(mVcdFile, add_ln274_178_reg_7086, "add_ln274_178_reg_7086");
sc_trace(mVcdFile, add_ln280_44_fu_3971_p2, "add_ln280_44_fu_3971_p2");
sc_trace(mVcdFile, add_ln280_44_reg_7091, "add_ln280_44_reg_7091");
sc_trace(mVcdFile, add_ln284_44_fu_3982_p2, "add_ln284_44_fu_3982_p2");
sc_trace(mVcdFile, add_ln284_44_reg_7100, "add_ln284_44_reg_7100");
sc_trace(mVcdFile, add_ln274_182_fu_3993_p2, "add_ln274_182_fu_3993_p2");
sc_trace(mVcdFile, add_ln274_182_reg_7109, "add_ln274_182_reg_7109");
sc_trace(mVcdFile, add_ln280_45_fu_4009_p2, "add_ln280_45_fu_4009_p2");
sc_trace(mVcdFile, add_ln280_45_reg_7114, "add_ln280_45_reg_7114");
sc_trace(mVcdFile, add_ln284_45_fu_4020_p2, "add_ln284_45_fu_4020_p2");
sc_trace(mVcdFile, add_ln284_45_reg_7123, "add_ln284_45_reg_7123");
sc_trace(mVcdFile, add_ln274_186_fu_4031_p2, "add_ln274_186_fu_4031_p2");
sc_trace(mVcdFile, add_ln274_186_reg_7132, "add_ln274_186_reg_7132");
sc_trace(mVcdFile, add_ln280_46_fu_4047_p2, "add_ln280_46_fu_4047_p2");
sc_trace(mVcdFile, add_ln280_46_reg_7137, "add_ln280_46_reg_7137");
sc_trace(mVcdFile, add_ln284_46_fu_4058_p2, "add_ln284_46_fu_4058_p2");
sc_trace(mVcdFile, add_ln284_46_reg_7146, "add_ln284_46_reg_7146");
sc_trace(mVcdFile, add_ln274_190_fu_4069_p2, "add_ln274_190_fu_4069_p2");
sc_trace(mVcdFile, add_ln274_190_reg_7155, "add_ln274_190_reg_7155");
sc_trace(mVcdFile, add_ln274_261_fu_4084_p2, "add_ln274_261_fu_4084_p2");
sc_trace(mVcdFile, add_ln274_261_reg_7160, "add_ln274_261_reg_7160");
sc_trace(mVcdFile, add_ln274_261_reg_7160_pp0_iter13_reg, "add_ln274_261_reg_7160_pp0_iter13_reg");
sc_trace(mVcdFile, add_ln274_261_reg_7160_pp0_iter14_reg, "add_ln274_261_reg_7160_pp0_iter14_reg");
sc_trace(mVcdFile, add_ln274_261_reg_7160_pp0_iter15_reg, "add_ln274_261_reg_7160_pp0_iter15_reg");
sc_trace(mVcdFile, add_ln274_261_reg_7160_pp0_iter16_reg, "add_ln274_261_reg_7160_pp0_iter16_reg");
sc_trace(mVcdFile, add_ln280_47_fu_4100_p2, "add_ln280_47_fu_4100_p2");
sc_trace(mVcdFile, add_ln280_47_reg_7165, "add_ln280_47_reg_7165");
sc_trace(mVcdFile, add_ln284_47_fu_4111_p2, "add_ln284_47_fu_4111_p2");
sc_trace(mVcdFile, add_ln284_47_reg_7174, "add_ln284_47_reg_7174");
sc_trace(mVcdFile, add_ln274_194_fu_4122_p2, "add_ln274_194_fu_4122_p2");
sc_trace(mVcdFile, add_ln274_194_reg_7183, "add_ln274_194_reg_7183");
sc_trace(mVcdFile, add_ln280_48_fu_4138_p2, "add_ln280_48_fu_4138_p2");
sc_trace(mVcdFile, add_ln280_48_reg_7188, "add_ln280_48_reg_7188");
sc_trace(mVcdFile, add_ln284_48_fu_4149_p2, "add_ln284_48_fu_4149_p2");
sc_trace(mVcdFile, add_ln284_48_reg_7197, "add_ln284_48_reg_7197");
sc_trace(mVcdFile, add_ln274_198_fu_4160_p2, "add_ln274_198_fu_4160_p2");
sc_trace(mVcdFile, add_ln274_198_reg_7206, "add_ln274_198_reg_7206");
sc_trace(mVcdFile, add_ln280_49_fu_4176_p2, "add_ln280_49_fu_4176_p2");
sc_trace(mVcdFile, add_ln280_49_reg_7211, "add_ln280_49_reg_7211");
sc_trace(mVcdFile, add_ln284_49_fu_4187_p2, "add_ln284_49_fu_4187_p2");
sc_trace(mVcdFile, add_ln284_49_reg_7220, "add_ln284_49_reg_7220");
sc_trace(mVcdFile, add_ln274_202_fu_4198_p2, "add_ln274_202_fu_4198_p2");
sc_trace(mVcdFile, add_ln274_202_reg_7229, "add_ln274_202_reg_7229");
sc_trace(mVcdFile, add_ln280_50_fu_4214_p2, "add_ln280_50_fu_4214_p2");
sc_trace(mVcdFile, add_ln280_50_reg_7234, "add_ln280_50_reg_7234");
sc_trace(mVcdFile, add_ln284_50_fu_4225_p2, "add_ln284_50_fu_4225_p2");
sc_trace(mVcdFile, add_ln284_50_reg_7243, "add_ln284_50_reg_7243");
sc_trace(mVcdFile, add_ln274_206_fu_4236_p2, "add_ln274_206_fu_4236_p2");
sc_trace(mVcdFile, add_ln274_206_reg_7252, "add_ln274_206_reg_7252");
sc_trace(mVcdFile, add_ln280_51_fu_4252_p2, "add_ln280_51_fu_4252_p2");
sc_trace(mVcdFile, add_ln280_51_reg_7257, "add_ln280_51_reg_7257");
sc_trace(mVcdFile, add_ln284_51_fu_4263_p2, "add_ln284_51_fu_4263_p2");
sc_trace(mVcdFile, add_ln284_51_reg_7266, "add_ln284_51_reg_7266");
sc_trace(mVcdFile, add_ln274_210_fu_4274_p2, "add_ln274_210_fu_4274_p2");
sc_trace(mVcdFile, add_ln274_210_reg_7275, "add_ln274_210_reg_7275");
sc_trace(mVcdFile, add_ln280_52_fu_4290_p2, "add_ln280_52_fu_4290_p2");
sc_trace(mVcdFile, add_ln280_52_reg_7280, "add_ln280_52_reg_7280");
sc_trace(mVcdFile, add_ln284_52_fu_4301_p2, "add_ln284_52_fu_4301_p2");
sc_trace(mVcdFile, add_ln284_52_reg_7289, "add_ln284_52_reg_7289");
sc_trace(mVcdFile, add_ln274_214_fu_4312_p2, "add_ln274_214_fu_4312_p2");
sc_trace(mVcdFile, add_ln274_214_reg_7298, "add_ln274_214_reg_7298");
sc_trace(mVcdFile, add_ln280_53_fu_4328_p2, "add_ln280_53_fu_4328_p2");
sc_trace(mVcdFile, add_ln280_53_reg_7303, "add_ln280_53_reg_7303");
sc_trace(mVcdFile, add_ln284_53_fu_4339_p2, "add_ln284_53_fu_4339_p2");
sc_trace(mVcdFile, add_ln284_53_reg_7312, "add_ln284_53_reg_7312");
sc_trace(mVcdFile, add_ln274_218_fu_4350_p2, "add_ln274_218_fu_4350_p2");
sc_trace(mVcdFile, add_ln274_218_reg_7321, "add_ln274_218_reg_7321");
sc_trace(mVcdFile, add_ln280_54_fu_4366_p2, "add_ln280_54_fu_4366_p2");
sc_trace(mVcdFile, add_ln280_54_reg_7326, "add_ln280_54_reg_7326");
sc_trace(mVcdFile, add_ln284_54_fu_4377_p2, "add_ln284_54_fu_4377_p2");
sc_trace(mVcdFile, add_ln284_54_reg_7335, "add_ln284_54_reg_7335");
sc_trace(mVcdFile, add_ln274_222_fu_4388_p2, "add_ln274_222_fu_4388_p2");
sc_trace(mVcdFile, add_ln274_222_reg_7344, "add_ln274_222_reg_7344");
sc_trace(mVcdFile, add_ln280_55_fu_4404_p2, "add_ln280_55_fu_4404_p2");
sc_trace(mVcdFile, add_ln280_55_reg_7349, "add_ln280_55_reg_7349");
sc_trace(mVcdFile, add_ln284_55_fu_4415_p2, "add_ln284_55_fu_4415_p2");
sc_trace(mVcdFile, add_ln284_55_reg_7358, "add_ln284_55_reg_7358");
sc_trace(mVcdFile, add_ln274_226_fu_4426_p2, "add_ln274_226_fu_4426_p2");
sc_trace(mVcdFile, add_ln274_226_reg_7367, "add_ln274_226_reg_7367");
sc_trace(mVcdFile, add_ln280_56_fu_4442_p2, "add_ln280_56_fu_4442_p2");
sc_trace(mVcdFile, add_ln280_56_reg_7372, "add_ln280_56_reg_7372");
sc_trace(mVcdFile, add_ln284_56_fu_4453_p2, "add_ln284_56_fu_4453_p2");
sc_trace(mVcdFile, add_ln284_56_reg_7381, "add_ln284_56_reg_7381");
sc_trace(mVcdFile, add_ln274_230_fu_4464_p2, "add_ln274_230_fu_4464_p2");
sc_trace(mVcdFile, add_ln274_230_reg_7390, "add_ln274_230_reg_7390");
sc_trace(mVcdFile, add_ln280_57_fu_4480_p2, "add_ln280_57_fu_4480_p2");
sc_trace(mVcdFile, add_ln280_57_reg_7395, "add_ln280_57_reg_7395");
sc_trace(mVcdFile, add_ln284_57_fu_4491_p2, "add_ln284_57_fu_4491_p2");
sc_trace(mVcdFile, add_ln284_57_reg_7404, "add_ln284_57_reg_7404");
sc_trace(mVcdFile, add_ln274_234_fu_4502_p2, "add_ln274_234_fu_4502_p2");
sc_trace(mVcdFile, add_ln274_234_reg_7413, "add_ln274_234_reg_7413");
sc_trace(mVcdFile, add_ln280_58_fu_4518_p2, "add_ln280_58_fu_4518_p2");
sc_trace(mVcdFile, add_ln280_58_reg_7418, "add_ln280_58_reg_7418");
sc_trace(mVcdFile, add_ln284_58_fu_4529_p2, "add_ln284_58_fu_4529_p2");
sc_trace(mVcdFile, add_ln284_58_reg_7427, "add_ln284_58_reg_7427");
sc_trace(mVcdFile, add_ln274_238_fu_4540_p2, "add_ln274_238_fu_4540_p2");
sc_trace(mVcdFile, add_ln274_238_reg_7436, "add_ln274_238_reg_7436");
sc_trace(mVcdFile, add_ln280_59_fu_4556_p2, "add_ln280_59_fu_4556_p2");
sc_trace(mVcdFile, add_ln280_59_reg_7441, "add_ln280_59_reg_7441");
sc_trace(mVcdFile, add_ln280_59_reg_7441_pp0_iter16_reg, "add_ln280_59_reg_7441_pp0_iter16_reg");
sc_trace(mVcdFile, add_ln284_59_fu_4567_p2, "add_ln284_59_fu_4567_p2");
sc_trace(mVcdFile, add_ln284_59_reg_7450, "add_ln284_59_reg_7450");
sc_trace(mVcdFile, add_ln284_59_reg_7450_pp0_iter16_reg, "add_ln284_59_reg_7450_pp0_iter16_reg");
sc_trace(mVcdFile, add_ln274_242_fu_4578_p2, "add_ln274_242_fu_4578_p2");
sc_trace(mVcdFile, add_ln274_242_reg_7459, "add_ln274_242_reg_7459");
sc_trace(mVcdFile, add_ln280_60_fu_4594_p2, "add_ln280_60_fu_4594_p2");
sc_trace(mVcdFile, add_ln280_60_reg_7464, "add_ln280_60_reg_7464");
sc_trace(mVcdFile, add_ln284_60_fu_4605_p2, "add_ln284_60_fu_4605_p2");
sc_trace(mVcdFile, add_ln284_60_reg_7473, "add_ln284_60_reg_7473");
sc_trace(mVcdFile, add_ln274_246_fu_4616_p2, "add_ln274_246_fu_4616_p2");
sc_trace(mVcdFile, add_ln274_246_reg_7482, "add_ln274_246_reg_7482");
sc_trace(mVcdFile, add_ln280_61_fu_4632_p2, "add_ln280_61_fu_4632_p2");
sc_trace(mVcdFile, add_ln280_61_reg_7487, "add_ln280_61_reg_7487");
sc_trace(mVcdFile, add_ln284_61_fu_4643_p2, "add_ln284_61_fu_4643_p2");
sc_trace(mVcdFile, add_ln284_61_reg_7495, "add_ln284_61_reg_7495");
sc_trace(mVcdFile, add_ln274_248_fu_4649_p2, "add_ln274_248_fu_4649_p2");
sc_trace(mVcdFile, add_ln274_248_reg_7503, "add_ln274_248_reg_7503");
sc_trace(mVcdFile, add_ln274_249_fu_4655_p2, "add_ln274_249_fu_4655_p2");
sc_trace(mVcdFile, add_ln274_249_reg_7508, "add_ln274_249_reg_7508");
sc_trace(mVcdFile, add_ln280_62_fu_4669_p2, "add_ln280_62_fu_4669_p2");
sc_trace(mVcdFile, add_ln280_62_reg_7513, "add_ln280_62_reg_7513");
sc_trace(mVcdFile, add_ln284_62_fu_4680_p2, "add_ln284_62_fu_4680_p2");
sc_trace(mVcdFile, add_ln284_62_reg_7520, "add_ln284_62_reg_7520");
sc_trace(mVcdFile, add_ln274_256_fu_4686_p2, "add_ln274_256_fu_4686_p2");
sc_trace(mVcdFile, add_ln274_256_reg_7527, "add_ln274_256_reg_7527");
sc_trace(mVcdFile, add_ln274_257_fu_4691_p2, "add_ln274_257_fu_4691_p2");
sc_trace(mVcdFile, add_ln274_257_reg_7532, "add_ln274_257_reg_7532");
sc_trace(mVcdFile, add_ln288_2_fu_4696_p2, "add_ln288_2_fu_4696_p2");
sc_trace(mVcdFile, add_ln288_2_reg_7537, "add_ln288_2_reg_7537");
sc_trace(mVcdFile, add_ln289_fu_4701_p2, "add_ln289_fu_4701_p2");
sc_trace(mVcdFile, add_ln289_reg_7542, "add_ln289_reg_7542");
sc_trace(mVcdFile, add_ln290_fu_4705_p2, "add_ln290_fu_4705_p2");
sc_trace(mVcdFile, add_ln290_reg_7547, "add_ln290_reg_7547");
sc_trace(mVcdFile, add_ln291_fu_4709_p2, "add_ln291_fu_4709_p2");
sc_trace(mVcdFile, add_ln291_reg_7552, "add_ln291_reg_7552");
sc_trace(mVcdFile, add_ln293_fu_4713_p2, "add_ln293_fu_4713_p2");
sc_trace(mVcdFile, add_ln293_reg_7557, "add_ln293_reg_7557");
sc_trace(mVcdFile, add_ln294_fu_4717_p2, "add_ln294_fu_4717_p2");
sc_trace(mVcdFile, add_ln294_reg_7562, "add_ln294_reg_7562");
sc_trace(mVcdFile, add_ln295_fu_4721_p2, "add_ln295_fu_4721_p2");
sc_trace(mVcdFile, add_ln295_reg_7567, "add_ln295_reg_7567");
sc_trace(mVcdFile, ap_enable_reg_pp0_iter0_reg, "ap_enable_reg_pp0_iter0_reg");
sc_trace(mVcdFile, ap_block_pp0_stage7_subdone, "ap_block_pp0_stage7_subdone");
sc_trace(mVcdFile, ap_block_pp0_stage3_subdone, "ap_block_pp0_stage3_subdone");
sc_trace(mVcdFile, ap_port_reg_ctx_state_3_read, "ap_port_reg_ctx_state_3_read");
sc_trace(mVcdFile, ap_port_reg_ctx_state_7_read, "ap_port_reg_ctx_state_7_read");
sc_trace(mVcdFile, ap_port_reg_rtl_key_r, "ap_port_reg_rtl_key_r");
sc_trace(mVcdFile, grp_MAJ_fu_864_ap_ready, "grp_MAJ_fu_864_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_864_x, "grp_MAJ_fu_864_x");
sc_trace(mVcdFile, grp_MAJ_fu_864_y, "grp_MAJ_fu_864_y");
sc_trace(mVcdFile, grp_MAJ_fu_864_z, "grp_MAJ_fu_864_z");
sc_trace(mVcdFile, grp_MAJ_fu_864_rtl_key_r, "grp_MAJ_fu_864_rtl_key_r");
sc_trace(mVcdFile, grp_MAJ_fu_876_ap_ready, "grp_MAJ_fu_876_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_876_x, "grp_MAJ_fu_876_x");
sc_trace(mVcdFile, grp_MAJ_fu_876_y, "grp_MAJ_fu_876_y");
sc_trace(mVcdFile, grp_MAJ_fu_876_z, "grp_MAJ_fu_876_z");
sc_trace(mVcdFile, grp_MAJ_fu_885_ap_ready, "grp_MAJ_fu_885_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_885_x, "grp_MAJ_fu_885_x");
sc_trace(mVcdFile, grp_MAJ_fu_885_y, "grp_MAJ_fu_885_y");
sc_trace(mVcdFile, grp_MAJ_fu_885_z, "grp_MAJ_fu_885_z");
sc_trace(mVcdFile, grp_MAJ_fu_894_ap_ready, "grp_MAJ_fu_894_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_894_x, "grp_MAJ_fu_894_x");
sc_trace(mVcdFile, grp_MAJ_fu_894_y, "grp_MAJ_fu_894_y");
sc_trace(mVcdFile, grp_MAJ_fu_894_z, "grp_MAJ_fu_894_z");
sc_trace(mVcdFile, grp_MAJ_fu_903_ap_ready, "grp_MAJ_fu_903_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_903_x, "grp_MAJ_fu_903_x");
sc_trace(mVcdFile, grp_MAJ_fu_903_y, "grp_MAJ_fu_903_y");
sc_trace(mVcdFile, grp_MAJ_fu_903_z, "grp_MAJ_fu_903_z");
sc_trace(mVcdFile, grp_MAJ_fu_912_ap_ready, "grp_MAJ_fu_912_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_912_x, "grp_MAJ_fu_912_x");
sc_trace(mVcdFile, grp_MAJ_fu_912_y, "grp_MAJ_fu_912_y");
sc_trace(mVcdFile, grp_MAJ_fu_912_z, "grp_MAJ_fu_912_z");
sc_trace(mVcdFile, grp_MAJ_fu_921_ap_ready, "grp_MAJ_fu_921_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_921_x, "grp_MAJ_fu_921_x");
sc_trace(mVcdFile, grp_MAJ_fu_921_y, "grp_MAJ_fu_921_y");
sc_trace(mVcdFile, grp_MAJ_fu_921_z, "grp_MAJ_fu_921_z");
sc_trace(mVcdFile, grp_MAJ_fu_930_ap_ready, "grp_MAJ_fu_930_ap_ready");
sc_trace(mVcdFile, grp_MAJ_fu_930_x, "grp_MAJ_fu_930_x");
sc_trace(mVcdFile, grp_MAJ_fu_930_y, "grp_MAJ_fu_930_y");
sc_trace(mVcdFile, grp_MAJ_fu_930_z, "grp_MAJ_fu_930_z");
sc_trace(mVcdFile, grp_EP1_fu_939_ap_ready, "grp_EP1_fu_939_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_939_x, "grp_EP1_fu_939_x");
sc_trace(mVcdFile, grp_EP1_fu_939_rtl_key_r, "grp_EP1_fu_939_rtl_key_r");
sc_trace(mVcdFile, grp_EP1_fu_947_ap_ready, "grp_EP1_fu_947_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_947_x, "grp_EP1_fu_947_x");
sc_trace(mVcdFile, grp_EP1_fu_947_ap_return, "grp_EP1_fu_947_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_954_ap_ready, "grp_EP1_fu_954_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_954_x, "grp_EP1_fu_954_x");
sc_trace(mVcdFile, grp_EP1_fu_954_ap_return, "grp_EP1_fu_954_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_961_ap_ready, "grp_EP1_fu_961_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_961_x, "grp_EP1_fu_961_x");
sc_trace(mVcdFile, grp_EP1_fu_961_ap_return, "grp_EP1_fu_961_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_968_ap_ready, "grp_EP1_fu_968_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_968_x, "grp_EP1_fu_968_x");
sc_trace(mVcdFile, grp_EP1_fu_968_ap_return, "grp_EP1_fu_968_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_975_ap_ready, "grp_EP1_fu_975_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_975_x, "grp_EP1_fu_975_x");
sc_trace(mVcdFile, grp_EP1_fu_975_ap_return, "grp_EP1_fu_975_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_982_ap_ready, "grp_EP1_fu_982_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_982_x, "grp_EP1_fu_982_x");
sc_trace(mVcdFile, grp_EP1_fu_982_ap_return, "grp_EP1_fu_982_ap_return");
sc_trace(mVcdFile, grp_EP1_fu_989_ap_ready, "grp_EP1_fu_989_ap_ready");
sc_trace(mVcdFile, grp_EP1_fu_989_x, "grp_EP1_fu_989_x");
sc_trace(mVcdFile, grp_EP1_fu_989_ap_return, "grp_EP1_fu_989_ap_return");
sc_trace(mVcdFile, grp_EP0_fu_996_ap_ready, "grp_EP0_fu_996_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_996_x, "grp_EP0_fu_996_x");
sc_trace(mVcdFile, grp_EP0_fu_996_rtl_key_r, "grp_EP0_fu_996_rtl_key_r");
sc_trace(mVcdFile, grp_EP0_fu_1004_ap_ready, "grp_EP0_fu_1004_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1004_x, "grp_EP0_fu_1004_x");
sc_trace(mVcdFile, grp_EP0_fu_1011_ap_ready, "grp_EP0_fu_1011_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1011_x, "grp_EP0_fu_1011_x");
sc_trace(mVcdFile, grp_EP0_fu_1018_ap_ready, "grp_EP0_fu_1018_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1018_x, "grp_EP0_fu_1018_x");
sc_trace(mVcdFile, grp_EP0_fu_1025_ap_ready, "grp_EP0_fu_1025_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1025_x, "grp_EP0_fu_1025_x");
sc_trace(mVcdFile, grp_EP0_fu_1032_ap_ready, "grp_EP0_fu_1032_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1032_x, "grp_EP0_fu_1032_x");
sc_trace(mVcdFile, grp_EP0_fu_1039_ap_ready, "grp_EP0_fu_1039_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1039_x, "grp_EP0_fu_1039_x");
sc_trace(mVcdFile, grp_EP0_fu_1046_ap_ready, "grp_EP0_fu_1046_ap_ready");
sc_trace(mVcdFile, grp_EP0_fu_1046_x, "grp_EP0_fu_1046_x");
sc_trace(mVcdFile, grp_SIG1_fu_1053_ap_ready, "grp_SIG1_fu_1053_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1053_x, "grp_SIG1_fu_1053_x");
sc_trace(mVcdFile, grp_SIG1_fu_1060_ap_ready, "grp_SIG1_fu_1060_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1060_x, "grp_SIG1_fu_1060_x");
sc_trace(mVcdFile, grp_SIG1_fu_1067_ap_ready, "grp_SIG1_fu_1067_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1067_x, "grp_SIG1_fu_1067_x");
sc_trace(mVcdFile, grp_SIG1_fu_1074_ap_ready, "grp_SIG1_fu_1074_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1074_x, "grp_SIG1_fu_1074_x");
sc_trace(mVcdFile, grp_SIG1_fu_1081_ap_ready, "grp_SIG1_fu_1081_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1081_x, "grp_SIG1_fu_1081_x");
sc_trace(mVcdFile, grp_SIG1_fu_1088_ap_ready, "grp_SIG1_fu_1088_ap_ready");
sc_trace(mVcdFile, grp_SIG1_fu_1088_x, "grp_SIG1_fu_1088_x");
sc_trace(mVcdFile, grp_SIG0_fu_1095_ap_ready, "grp_SIG0_fu_1095_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1095_x, "grp_SIG0_fu_1095_x");
sc_trace(mVcdFile, grp_SIG0_fu_1102_ap_ready, "grp_SIG0_fu_1102_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1102_x, "grp_SIG0_fu_1102_x");
sc_trace(mVcdFile, grp_SIG0_fu_1109_ap_ready, "grp_SIG0_fu_1109_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1109_x, "grp_SIG0_fu_1109_x");
sc_trace(mVcdFile, grp_SIG0_fu_1116_ap_ready, "grp_SIG0_fu_1116_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1116_x, "grp_SIG0_fu_1116_x");
sc_trace(mVcdFile, grp_SIG0_fu_1123_ap_ready, "grp_SIG0_fu_1123_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1123_x, "grp_SIG0_fu_1123_x");
sc_trace(mVcdFile, grp_SIG0_fu_1130_ap_ready, "grp_SIG0_fu_1130_ap_ready");
sc_trace(mVcdFile, grp_SIG0_fu_1130_x, "grp_SIG0_fu_1130_x");
sc_trace(mVcdFile, grp_CH_fu_1137_ap_ready, "grp_CH_fu_1137_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1137_x, "grp_CH_fu_1137_x");
sc_trace(mVcdFile, grp_CH_fu_1137_y, "grp_CH_fu_1137_y");
sc_trace(mVcdFile, grp_CH_fu_1137_z, "grp_CH_fu_1137_z");
sc_trace(mVcdFile, grp_CH_fu_1137_rtl_key_r, "grp_CH_fu_1137_rtl_key_r");
sc_trace(mVcdFile, grp_CH_fu_1149_ap_ready, "grp_CH_fu_1149_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1149_x, "grp_CH_fu_1149_x");
sc_trace(mVcdFile, grp_CH_fu_1149_y, "grp_CH_fu_1149_y");
sc_trace(mVcdFile, grp_CH_fu_1149_z, "grp_CH_fu_1149_z");
sc_trace(mVcdFile, grp_CH_fu_1158_ap_ready, "grp_CH_fu_1158_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1158_x, "grp_CH_fu_1158_x");
sc_trace(mVcdFile, grp_CH_fu_1158_y, "grp_CH_fu_1158_y");
sc_trace(mVcdFile, grp_CH_fu_1158_z, "grp_CH_fu_1158_z");
sc_trace(mVcdFile, grp_CH_fu_1167_ap_ready, "grp_CH_fu_1167_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1167_x, "grp_CH_fu_1167_x");
sc_trace(mVcdFile, grp_CH_fu_1167_y, "grp_CH_fu_1167_y");
sc_trace(mVcdFile, grp_CH_fu_1167_z, "grp_CH_fu_1167_z");
sc_trace(mVcdFile, grp_CH_fu_1176_ap_ready, "grp_CH_fu_1176_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1176_x, "grp_CH_fu_1176_x");
sc_trace(mVcdFile, grp_CH_fu_1176_y, "grp_CH_fu_1176_y");
sc_trace(mVcdFile, grp_CH_fu_1176_z, "grp_CH_fu_1176_z");
sc_trace(mVcdFile, grp_CH_fu_1185_ap_ready, "grp_CH_fu_1185_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1185_x, "grp_CH_fu_1185_x");
sc_trace(mVcdFile, grp_CH_fu_1185_y, "grp_CH_fu_1185_y");
sc_trace(mVcdFile, grp_CH_fu_1185_z, "grp_CH_fu_1185_z");
sc_trace(mVcdFile, grp_CH_fu_1194_ap_ready, "grp_CH_fu_1194_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1194_x, "grp_CH_fu_1194_x");
sc_trace(mVcdFile, grp_CH_fu_1194_y, "grp_CH_fu_1194_y");
sc_trace(mVcdFile, grp_CH_fu_1194_z, "grp_CH_fu_1194_z");
sc_trace(mVcdFile, grp_CH_fu_1203_ap_ready, "grp_CH_fu_1203_ap_ready");
sc_trace(mVcdFile, grp_CH_fu_1203_x, "grp_CH_fu_1203_x");
sc_trace(mVcdFile, grp_CH_fu_1203_y, "grp_CH_fu_1203_y");
sc_trace(mVcdFile, grp_CH_fu_1203_z, "grp_CH_fu_1203_z");
sc_trace(mVcdFile, ap_block_pp0_stage3, "ap_block_pp0_stage3");
sc_trace(mVcdFile, ap_block_pp0_stage5, "ap_block_pp0_stage5");
sc_trace(mVcdFile, ap_block_pp0_stage7, "ap_block_pp0_stage7");
sc_trace(mVcdFile, ap_block_pp0_stage1, "ap_block_pp0_stage1");
sc_trace(mVcdFile, ap_block_pp0_stage4, "ap_block_pp0_stage4");
sc_trace(mVcdFile, ap_block_pp0_stage6, "ap_block_pp0_stage6");
sc_trace(mVcdFile, ap_block_pp0_stage2, "ap_block_pp0_stage2");
sc_trace(mVcdFile, add_ln274_1_fu_1357_p2, "add_ln274_1_fu_1357_p2");
sc_trace(mVcdFile, add_ln274_fu_1394_p2, "add_ln274_fu_1394_p2");
sc_trace(mVcdFile, add_ln274_3_fu_1400_p2, "add_ln274_3_fu_1400_p2");
sc_trace(mVcdFile, add_ln284_63_fu_1411_p2, "add_ln284_63_fu_1411_p2");
sc_trace(mVcdFile, add_ln274_5_fu_1449_p2, "add_ln274_5_fu_1449_p2");
sc_trace(mVcdFile, add_ln274_4_fu_1486_p2, "add_ln274_4_fu_1486_p2");
sc_trace(mVcdFile, add_ln274_7_fu_1491_p2, "add_ln274_7_fu_1491_p2");
sc_trace(mVcdFile, add_ln284_64_fu_1501_p2, "add_ln284_64_fu_1501_p2");
sc_trace(mVcdFile, add_ln274_9_fu_1539_p2, "add_ln274_9_fu_1539_p2");
sc_trace(mVcdFile, add_ln274_8_fu_1575_p2, "add_ln274_8_fu_1575_p2");
sc_trace(mVcdFile, add_ln274_11_fu_1581_p2, "add_ln274_11_fu_1581_p2");
sc_trace(mVcdFile, add_ln284_65_fu_1591_p2, "add_ln284_65_fu_1591_p2");
sc_trace(mVcdFile, add_ln274_13_fu_1629_p2, "add_ln274_13_fu_1629_p2");
sc_trace(mVcdFile, add_ln274_12_fu_1676_p2, "add_ln274_12_fu_1676_p2");
sc_trace(mVcdFile, add_ln274_15_fu_1681_p2, "add_ln274_15_fu_1681_p2");
sc_trace(mVcdFile, add_ln284_66_fu_1691_p2, "add_ln284_66_fu_1691_p2");
sc_trace(mVcdFile, add_ln259_fu_1703_p2, "add_ln259_fu_1703_p2");
sc_trace(mVcdFile, add_ln259_3_fu_1715_p2, "add_ln259_3_fu_1715_p2");
sc_trace(mVcdFile, add_ln274_17_fu_1735_p2, "add_ln274_17_fu_1735_p2");
sc_trace(mVcdFile, add_ln259_6_fu_1746_p2, "add_ln259_6_fu_1746_p2");
sc_trace(mVcdFile, add_ln259_9_fu_1758_p2, "add_ln259_9_fu_1758_p2");
sc_trace(mVcdFile, add_ln274_16_fu_1778_p2, "add_ln274_16_fu_1778_p2");
sc_trace(mVcdFile, add_ln274_19_fu_1782_p2, "add_ln274_19_fu_1782_p2");
sc_trace(mVcdFile, add_ln284_67_fu_1792_p2, "add_ln284_67_fu_1792_p2");
sc_trace(mVcdFile, add_ln259_12_fu_1802_p2, "add_ln259_12_fu_1802_p2");
sc_trace(mVcdFile, add_ln259_15_fu_1814_p2, "add_ln259_15_fu_1814_p2");
sc_trace(mVcdFile, add_ln274_21_fu_1834_p2, "add_ln274_21_fu_1834_p2");
sc_trace(mVcdFile, add_ln259_18_fu_1845_p2, "add_ln259_18_fu_1845_p2");
sc_trace(mVcdFile, add_ln259_21_fu_1857_p2, "add_ln259_21_fu_1857_p2");
sc_trace(mVcdFile, add_ln274_20_fu_1877_p2, "add_ln274_20_fu_1877_p2");
sc_trace(mVcdFile, add_ln274_23_fu_1882_p2, "add_ln274_23_fu_1882_p2");
sc_trace(mVcdFile, add_ln284_68_fu_1892_p2, "add_ln284_68_fu_1892_p2");
sc_trace(mVcdFile, add_ln259_24_fu_1904_p2, "add_ln259_24_fu_1904_p2");
sc_trace(mVcdFile, add_ln259_27_fu_1916_p2, "add_ln259_27_fu_1916_p2");
sc_trace(mVcdFile, add_ln274_25_fu_1936_p2, "add_ln274_25_fu_1936_p2");
sc_trace(mVcdFile, add_ln259_30_fu_1946_p2, "add_ln259_30_fu_1946_p2");
sc_trace(mVcdFile, add_ln259_33_fu_1958_p2, "add_ln259_33_fu_1958_p2");
sc_trace(mVcdFile, add_ln274_24_fu_1978_p2, "add_ln274_24_fu_1978_p2");
sc_trace(mVcdFile, add_ln274_27_fu_1984_p2, "add_ln274_27_fu_1984_p2");
sc_trace(mVcdFile, add_ln284_69_fu_1994_p2, "add_ln284_69_fu_1994_p2");
sc_trace(mVcdFile, add_ln259_36_fu_2006_p2, "add_ln259_36_fu_2006_p2");
sc_trace(mVcdFile, add_ln259_39_fu_2018_p2, "add_ln259_39_fu_2018_p2");
sc_trace(mVcdFile, add_ln274_29_fu_2038_p2, "add_ln274_29_fu_2038_p2");
sc_trace(mVcdFile, add_ln259_42_fu_2048_p2, "add_ln259_42_fu_2048_p2");
sc_trace(mVcdFile, add_ln259_45_fu_2060_p2, "add_ln259_45_fu_2060_p2");
sc_trace(mVcdFile, add_ln274_28_fu_2080_p2, "add_ln274_28_fu_2080_p2");
sc_trace(mVcdFile, add_ln274_31_fu_2086_p2, "add_ln274_31_fu_2086_p2");
sc_trace(mVcdFile, add_ln284_70_fu_2096_p2, "add_ln284_70_fu_2096_p2");
sc_trace(mVcdFile, add_ln259_48_fu_2108_p2, "add_ln259_48_fu_2108_p2");
sc_trace(mVcdFile, add_ln259_51_fu_2120_p2, "add_ln259_51_fu_2120_p2");
sc_trace(mVcdFile, add_ln274_33_fu_2140_p2, "add_ln274_33_fu_2140_p2");
sc_trace(mVcdFile, add_ln259_54_fu_2151_p2, "add_ln259_54_fu_2151_p2");
sc_trace(mVcdFile, add_ln259_57_fu_2163_p2, "add_ln259_57_fu_2163_p2");
sc_trace(mVcdFile, add_ln274_32_fu_2183_p2, "add_ln274_32_fu_2183_p2");
sc_trace(mVcdFile, add_ln274_35_fu_2188_p2, "add_ln274_35_fu_2188_p2");
sc_trace(mVcdFile, add_ln284_71_fu_2198_p2, "add_ln284_71_fu_2198_p2");
sc_trace(mVcdFile, add_ln259_60_fu_2210_p2, "add_ln259_60_fu_2210_p2");
sc_trace(mVcdFile, add_ln259_63_fu_2222_p2, "add_ln259_63_fu_2222_p2");
sc_trace(mVcdFile, add_ln274_37_fu_2242_p2, "add_ln274_37_fu_2242_p2");
sc_trace(mVcdFile, add_ln259_66_fu_2253_p2, "add_ln259_66_fu_2253_p2");
sc_trace(mVcdFile, add_ln259_69_fu_2265_p2, "add_ln259_69_fu_2265_p2");
sc_trace(mVcdFile, add_ln274_36_fu_2285_p2, "add_ln274_36_fu_2285_p2");
sc_trace(mVcdFile, add_ln274_39_fu_2290_p2, "add_ln274_39_fu_2290_p2");
sc_trace(mVcdFile, add_ln284_72_fu_2300_p2, "add_ln284_72_fu_2300_p2");
sc_trace(mVcdFile, add_ln259_72_fu_2312_p2, "add_ln259_72_fu_2312_p2");
sc_trace(mVcdFile, add_ln259_75_fu_2324_p2, "add_ln259_75_fu_2324_p2");
sc_trace(mVcdFile, add_ln274_41_fu_2344_p2, "add_ln274_41_fu_2344_p2");
sc_trace(mVcdFile, add_ln259_78_fu_2355_p2, "add_ln259_78_fu_2355_p2");
sc_trace(mVcdFile, add_ln259_81_fu_2367_p2, "add_ln259_81_fu_2367_p2");
sc_trace(mVcdFile, add_ln274_40_fu_2387_p2, "add_ln274_40_fu_2387_p2");
sc_trace(mVcdFile, add_ln274_43_fu_2392_p2, "add_ln274_43_fu_2392_p2");
sc_trace(mVcdFile, add_ln284_73_fu_2402_p2, "add_ln284_73_fu_2402_p2");
sc_trace(mVcdFile, add_ln259_84_fu_2414_p2, "add_ln259_84_fu_2414_p2");
sc_trace(mVcdFile, add_ln259_87_fu_2426_p2, "add_ln259_87_fu_2426_p2");
sc_trace(mVcdFile, add_ln274_45_fu_2446_p2, "add_ln274_45_fu_2446_p2");
sc_trace(mVcdFile, add_ln259_90_fu_2457_p2, "add_ln259_90_fu_2457_p2");
sc_trace(mVcdFile, add_ln259_93_fu_2469_p2, "add_ln259_93_fu_2469_p2");
sc_trace(mVcdFile, add_ln274_44_fu_2489_p2, "add_ln274_44_fu_2489_p2");
sc_trace(mVcdFile, add_ln274_47_fu_2494_p2, "add_ln274_47_fu_2494_p2");
sc_trace(mVcdFile, add_ln284_74_fu_2504_p2, "add_ln284_74_fu_2504_p2");
sc_trace(mVcdFile, add_ln259_96_fu_2516_p2, "add_ln259_96_fu_2516_p2");
sc_trace(mVcdFile, add_ln259_99_fu_2528_p2, "add_ln259_99_fu_2528_p2");
sc_trace(mVcdFile, add_ln274_49_fu_2547_p2, "add_ln274_49_fu_2547_p2");
sc_trace(mVcdFile, add_ln259_102_fu_2558_p2, "add_ln259_102_fu_2558_p2");
sc_trace(mVcdFile, add_ln259_105_fu_2569_p2, "add_ln259_105_fu_2569_p2");
sc_trace(mVcdFile, add_ln274_48_fu_2588_p2, "add_ln274_48_fu_2588_p2");
sc_trace(mVcdFile, add_ln274_51_fu_2593_p2, "add_ln274_51_fu_2593_p2");
sc_trace(mVcdFile, add_ln284_75_fu_2603_p2, "add_ln284_75_fu_2603_p2");
sc_trace(mVcdFile, add_ln259_108_fu_2615_p2, "add_ln259_108_fu_2615_p2");
sc_trace(mVcdFile, add_ln259_111_fu_2626_p2, "add_ln259_111_fu_2626_p2");
sc_trace(mVcdFile, add_ln274_53_fu_2645_p2, "add_ln274_53_fu_2645_p2");
sc_trace(mVcdFile, add_ln259_114_fu_2655_p2, "add_ln259_114_fu_2655_p2");
sc_trace(mVcdFile, add_ln259_117_fu_2666_p2, "add_ln259_117_fu_2666_p2");
sc_trace(mVcdFile, add_ln274_52_fu_2685_p2, "add_ln274_52_fu_2685_p2");
sc_trace(mVcdFile, add_ln274_55_fu_2691_p2, "add_ln274_55_fu_2691_p2");
sc_trace(mVcdFile, add_ln284_76_fu_2701_p2, "add_ln284_76_fu_2701_p2");
sc_trace(mVcdFile, add_ln259_120_fu_2713_p2, "add_ln259_120_fu_2713_p2");
sc_trace(mVcdFile, add_ln259_123_fu_2724_p2, "add_ln259_123_fu_2724_p2");
sc_trace(mVcdFile, add_ln274_57_fu_2743_p2, "add_ln274_57_fu_2743_p2");
sc_trace(mVcdFile, add_ln259_126_fu_2753_p2, "add_ln259_126_fu_2753_p2");
sc_trace(mVcdFile, add_ln259_129_fu_2764_p2, "add_ln259_129_fu_2764_p2");
sc_trace(mVcdFile, add_ln274_56_fu_2783_p2, "add_ln274_56_fu_2783_p2");
sc_trace(mVcdFile, add_ln274_59_fu_2789_p2, "add_ln274_59_fu_2789_p2");
sc_trace(mVcdFile, add_ln284_77_fu_2799_p2, "add_ln284_77_fu_2799_p2");
sc_trace(mVcdFile, add_ln259_132_fu_2811_p2, "add_ln259_132_fu_2811_p2");
sc_trace(mVcdFile, add_ln259_135_fu_2822_p2, "add_ln259_135_fu_2822_p2");
sc_trace(mVcdFile, add_ln274_61_fu_2833_p2, "add_ln274_61_fu_2833_p2");
sc_trace(mVcdFile, add_ln274_60_fu_2844_p2, "add_ln274_60_fu_2844_p2");
sc_trace(mVcdFile, add_ln274_63_fu_2849_p2, "add_ln274_63_fu_2849_p2");
sc_trace(mVcdFile, add_ln284_78_fu_2859_p2, "add_ln284_78_fu_2859_p2");
sc_trace(mVcdFile, add_ln274_253_fu_2876_p2, "add_ln274_253_fu_2876_p2");
sc_trace(mVcdFile, add_ln274_252_fu_2871_p2, "add_ln274_252_fu_2871_p2");
sc_trace(mVcdFile, add_ln274_65_fu_2886_p2, "add_ln274_65_fu_2886_p2");
sc_trace(mVcdFile, add_ln274_64_fu_2897_p2, "add_ln274_64_fu_2897_p2");
sc_trace(mVcdFile, add_ln274_67_fu_2902_p2, "add_ln274_67_fu_2902_p2");
sc_trace(mVcdFile, add_ln284_79_fu_2912_p2, "add_ln284_79_fu_2912_p2");
sc_trace(mVcdFile, add_ln274_69_fu_2924_p2, "add_ln274_69_fu_2924_p2");
sc_trace(mVcdFile, add_ln274_68_fu_2935_p2, "add_ln274_68_fu_2935_p2");
sc_trace(mVcdFile, add_ln274_71_fu_2940_p2, "add_ln274_71_fu_2940_p2");
sc_trace(mVcdFile, add_ln284_80_fu_2950_p2, "add_ln284_80_fu_2950_p2");
sc_trace(mVcdFile, add_ln274_73_fu_2962_p2, "add_ln274_73_fu_2962_p2");
sc_trace(mVcdFile, add_ln274_72_fu_2973_p2, "add_ln274_72_fu_2973_p2");
sc_trace(mVcdFile, add_ln274_75_fu_2978_p2, "add_ln274_75_fu_2978_p2");
sc_trace(mVcdFile, add_ln284_81_fu_2988_p2, "add_ln284_81_fu_2988_p2");
sc_trace(mVcdFile, add_ln274_77_fu_3000_p2, "add_ln274_77_fu_3000_p2");
sc_trace(mVcdFile, add_ln274_76_fu_3011_p2, "add_ln274_76_fu_3011_p2");
sc_trace(mVcdFile, add_ln274_79_fu_3016_p2, "add_ln274_79_fu_3016_p2");
sc_trace(mVcdFile, add_ln284_82_fu_3026_p2, "add_ln284_82_fu_3026_p2");
sc_trace(mVcdFile, add_ln274_81_fu_3038_p2, "add_ln274_81_fu_3038_p2");
sc_trace(mVcdFile, add_ln274_80_fu_3049_p2, "add_ln274_80_fu_3049_p2");
sc_trace(mVcdFile, add_ln274_83_fu_3054_p2, "add_ln274_83_fu_3054_p2");
sc_trace(mVcdFile, add_ln284_83_fu_3064_p2, "add_ln284_83_fu_3064_p2");
sc_trace(mVcdFile, add_ln274_85_fu_3076_p2, "add_ln274_85_fu_3076_p2");
sc_trace(mVcdFile, add_ln274_84_fu_3087_p2, "add_ln274_84_fu_3087_p2");
sc_trace(mVcdFile, add_ln274_87_fu_3092_p2, "add_ln274_87_fu_3092_p2");
sc_trace(mVcdFile, add_ln284_84_fu_3102_p2, "add_ln284_84_fu_3102_p2");
sc_trace(mVcdFile, add_ln274_89_fu_3114_p2, "add_ln274_89_fu_3114_p2");
sc_trace(mVcdFile, add_ln274_88_fu_3125_p2, "add_ln274_88_fu_3125_p2");
sc_trace(mVcdFile, add_ln274_91_fu_3130_p2, "add_ln274_91_fu_3130_p2");
sc_trace(mVcdFile, add_ln284_85_fu_3140_p2, "add_ln284_85_fu_3140_p2");
sc_trace(mVcdFile, add_ln274_93_fu_3152_p2, "add_ln274_93_fu_3152_p2");
sc_trace(mVcdFile, add_ln274_92_fu_3163_p2, "add_ln274_92_fu_3163_p2");
sc_trace(mVcdFile, add_ln274_95_fu_3168_p2, "add_ln274_95_fu_3168_p2");
sc_trace(mVcdFile, add_ln284_86_fu_3178_p2, "add_ln284_86_fu_3178_p2");
sc_trace(mVcdFile, add_ln274_97_fu_3190_p2, "add_ln274_97_fu_3190_p2");
sc_trace(mVcdFile, add_ln274_96_fu_3200_p2, "add_ln274_96_fu_3200_p2");
sc_trace(mVcdFile, add_ln274_99_fu_3206_p2, "add_ln274_99_fu_3206_p2");
sc_trace(mVcdFile, add_ln284_87_fu_3216_p2, "add_ln284_87_fu_3216_p2");
sc_trace(mVcdFile, add_ln274_101_fu_3228_p2, "add_ln274_101_fu_3228_p2");
sc_trace(mVcdFile, add_ln274_100_fu_3238_p2, "add_ln274_100_fu_3238_p2");
sc_trace(mVcdFile, add_ln274_103_fu_3244_p2, "add_ln274_103_fu_3244_p2");
sc_trace(mVcdFile, add_ln284_88_fu_3254_p2, "add_ln284_88_fu_3254_p2");
sc_trace(mVcdFile, add_ln274_105_fu_3266_p2, "add_ln274_105_fu_3266_p2");
sc_trace(mVcdFile, add_ln274_104_fu_3276_p2, "add_ln274_104_fu_3276_p2");
sc_trace(mVcdFile, add_ln274_107_fu_3282_p2, "add_ln274_107_fu_3282_p2");
sc_trace(mVcdFile, add_ln284_89_fu_3292_p2, "add_ln284_89_fu_3292_p2");
sc_trace(mVcdFile, add_ln274_109_fu_3304_p2, "add_ln274_109_fu_3304_p2");
sc_trace(mVcdFile, add_ln274_108_fu_3314_p2, "add_ln274_108_fu_3314_p2");
sc_trace(mVcdFile, add_ln274_111_fu_3320_p2, "add_ln274_111_fu_3320_p2");
sc_trace(mVcdFile, add_ln284_90_fu_3330_p2, "add_ln284_90_fu_3330_p2");
sc_trace(mVcdFile, add_ln274_113_fu_3342_p2, "add_ln274_113_fu_3342_p2");
sc_trace(mVcdFile, add_ln274_112_fu_3353_p2, "add_ln274_112_fu_3353_p2");
sc_trace(mVcdFile, add_ln274_115_fu_3358_p2, "add_ln274_115_fu_3358_p2");
sc_trace(mVcdFile, add_ln284_91_fu_3368_p2, "add_ln284_91_fu_3368_p2");
sc_trace(mVcdFile, add_ln274_117_fu_3380_p2, "add_ln274_117_fu_3380_p2");
sc_trace(mVcdFile, add_ln274_116_fu_3391_p2, "add_ln274_116_fu_3391_p2");
sc_trace(mVcdFile, add_ln274_119_fu_3396_p2, "add_ln274_119_fu_3396_p2");
sc_trace(mVcdFile, add_ln284_92_fu_3406_p2, "add_ln284_92_fu_3406_p2");
sc_trace(mVcdFile, add_ln274_121_fu_3418_p2, "add_ln274_121_fu_3418_p2");
sc_trace(mVcdFile, add_ln274_120_fu_3429_p2, "add_ln274_120_fu_3429_p2");
sc_trace(mVcdFile, add_ln274_123_fu_3434_p2, "add_ln274_123_fu_3434_p2");
sc_trace(mVcdFile, add_ln284_93_fu_3444_p2, "add_ln284_93_fu_3444_p2");
sc_trace(mVcdFile, add_ln274_125_fu_3456_p2, "add_ln274_125_fu_3456_p2");
sc_trace(mVcdFile, add_ln274_124_fu_3467_p2, "add_ln274_124_fu_3467_p2");
sc_trace(mVcdFile, add_ln274_127_fu_3472_p2, "add_ln274_127_fu_3472_p2");
sc_trace(mVcdFile, add_ln284_94_fu_3482_p2, "add_ln284_94_fu_3482_p2");
sc_trace(mVcdFile, add_ln274_129_fu_3494_p2, "add_ln274_129_fu_3494_p2");
sc_trace(mVcdFile, add_ln274_128_fu_3505_p2, "add_ln274_128_fu_3505_p2");
sc_trace(mVcdFile, add_ln274_131_fu_3510_p2, "add_ln274_131_fu_3510_p2");
sc_trace(mVcdFile, add_ln284_95_fu_3520_p2, "add_ln284_95_fu_3520_p2");
sc_trace(mVcdFile, add_ln274_133_fu_3532_p2, "add_ln274_133_fu_3532_p2");
sc_trace(mVcdFile, add_ln274_132_fu_3543_p2, "add_ln274_132_fu_3543_p2");
sc_trace(mVcdFile, add_ln274_135_fu_3548_p2, "add_ln274_135_fu_3548_p2");
sc_trace(mVcdFile, add_ln284_96_fu_3558_p2, "add_ln284_96_fu_3558_p2");
sc_trace(mVcdFile, add_ln274_137_fu_3570_p2, "add_ln274_137_fu_3570_p2");
sc_trace(mVcdFile, add_ln274_136_fu_3581_p2, "add_ln274_136_fu_3581_p2");
sc_trace(mVcdFile, add_ln274_139_fu_3586_p2, "add_ln274_139_fu_3586_p2");
sc_trace(mVcdFile, add_ln284_97_fu_3596_p2, "add_ln284_97_fu_3596_p2");
sc_trace(mVcdFile, add_ln274_141_fu_3608_p2, "add_ln274_141_fu_3608_p2");
sc_trace(mVcdFile, add_ln274_140_fu_3619_p2, "add_ln274_140_fu_3619_p2");
sc_trace(mVcdFile, add_ln274_143_fu_3624_p2, "add_ln274_143_fu_3624_p2");
sc_trace(mVcdFile, add_ln284_98_fu_3634_p2, "add_ln284_98_fu_3634_p2");
sc_trace(mVcdFile, add_ln274_145_fu_3646_p2, "add_ln274_145_fu_3646_p2");
sc_trace(mVcdFile, add_ln274_144_fu_3657_p2, "add_ln274_144_fu_3657_p2");
sc_trace(mVcdFile, add_ln274_147_fu_3662_p2, "add_ln274_147_fu_3662_p2");
sc_trace(mVcdFile, add_ln284_99_fu_3672_p2, "add_ln284_99_fu_3672_p2");
sc_trace(mVcdFile, add_ln274_149_fu_3684_p2, "add_ln274_149_fu_3684_p2");
sc_trace(mVcdFile, add_ln274_148_fu_3695_p2, "add_ln274_148_fu_3695_p2");
sc_trace(mVcdFile, add_ln274_151_fu_3700_p2, "add_ln274_151_fu_3700_p2");
sc_trace(mVcdFile, add_ln284_100_fu_3710_p2, "add_ln284_100_fu_3710_p2");
sc_trace(mVcdFile, add_ln274_153_fu_3722_p2, "add_ln274_153_fu_3722_p2");
sc_trace(mVcdFile, add_ln274_152_fu_3732_p2, "add_ln274_152_fu_3732_p2");
sc_trace(mVcdFile, add_ln274_155_fu_3738_p2, "add_ln274_155_fu_3738_p2");
sc_trace(mVcdFile, add_ln284_101_fu_3748_p2, "add_ln284_101_fu_3748_p2");
sc_trace(mVcdFile, add_ln274_157_fu_3760_p2, "add_ln274_157_fu_3760_p2");
sc_trace(mVcdFile, add_ln274_156_fu_3770_p2, "add_ln274_156_fu_3770_p2");
sc_trace(mVcdFile, add_ln274_159_fu_3776_p2, "add_ln274_159_fu_3776_p2");
sc_trace(mVcdFile, add_ln284_102_fu_3786_p2, "add_ln284_102_fu_3786_p2");
sc_trace(mVcdFile, add_ln274_161_fu_3798_p2, "add_ln274_161_fu_3798_p2");
sc_trace(mVcdFile, add_ln274_160_fu_3808_p2, "add_ln274_160_fu_3808_p2");
sc_trace(mVcdFile, add_ln274_163_fu_3814_p2, "add_ln274_163_fu_3814_p2");
sc_trace(mVcdFile, add_ln284_103_fu_3824_p2, "add_ln284_103_fu_3824_p2");
sc_trace(mVcdFile, add_ln274_165_fu_3836_p2, "add_ln274_165_fu_3836_p2");
sc_trace(mVcdFile, add_ln274_164_fu_3846_p2, "add_ln274_164_fu_3846_p2");
sc_trace(mVcdFile, add_ln274_167_fu_3852_p2, "add_ln274_167_fu_3852_p2");
sc_trace(mVcdFile, add_ln284_104_fu_3862_p2, "add_ln284_104_fu_3862_p2");
sc_trace(mVcdFile, add_ln274_169_fu_3874_p2, "add_ln274_169_fu_3874_p2");
sc_trace(mVcdFile, add_ln274_168_fu_3885_p2, "add_ln274_168_fu_3885_p2");
sc_trace(mVcdFile, add_ln274_171_fu_3890_p2, "add_ln274_171_fu_3890_p2");
sc_trace(mVcdFile, add_ln284_105_fu_3900_p2, "add_ln284_105_fu_3900_p2");
sc_trace(mVcdFile, add_ln274_173_fu_3912_p2, "add_ln274_173_fu_3912_p2");
sc_trace(mVcdFile, add_ln274_172_fu_3923_p2, "add_ln274_172_fu_3923_p2");
sc_trace(mVcdFile, add_ln274_175_fu_3928_p2, "add_ln274_175_fu_3928_p2");
sc_trace(mVcdFile, add_ln284_106_fu_3938_p2, "add_ln284_106_fu_3938_p2");
sc_trace(mVcdFile, add_ln274_177_fu_3950_p2, "add_ln274_177_fu_3950_p2");
sc_trace(mVcdFile, add_ln274_176_fu_3961_p2, "add_ln274_176_fu_3961_p2");
sc_trace(mVcdFile, add_ln274_179_fu_3966_p2, "add_ln274_179_fu_3966_p2");
sc_trace(mVcdFile, add_ln284_107_fu_3976_p2, "add_ln284_107_fu_3976_p2");
sc_trace(mVcdFile, add_ln274_181_fu_3988_p2, "add_ln274_181_fu_3988_p2");
sc_trace(mVcdFile, add_ln274_180_fu_3999_p2, "add_ln274_180_fu_3999_p2");
sc_trace(mVcdFile, add_ln274_183_fu_4004_p2, "add_ln274_183_fu_4004_p2");
sc_trace(mVcdFile, add_ln284_108_fu_4014_p2, "add_ln284_108_fu_4014_p2");
sc_trace(mVcdFile, add_ln274_185_fu_4026_p2, "add_ln274_185_fu_4026_p2");
sc_trace(mVcdFile, add_ln274_184_fu_4037_p2, "add_ln274_184_fu_4037_p2");
sc_trace(mVcdFile, add_ln274_187_fu_4042_p2, "add_ln274_187_fu_4042_p2");
sc_trace(mVcdFile, add_ln284_109_fu_4052_p2, "add_ln284_109_fu_4052_p2");
sc_trace(mVcdFile, add_ln274_189_fu_4064_p2, "add_ln274_189_fu_4064_p2");
sc_trace(mVcdFile, add_ln274_260_fu_4079_p2, "add_ln274_260_fu_4079_p2");
sc_trace(mVcdFile, add_ln274_259_fu_4075_p2, "add_ln274_259_fu_4075_p2");
sc_trace(mVcdFile, add_ln274_188_fu_4090_p2, "add_ln274_188_fu_4090_p2");
sc_trace(mVcdFile, add_ln274_191_fu_4095_p2, "add_ln274_191_fu_4095_p2");
sc_trace(mVcdFile, add_ln284_110_fu_4105_p2, "add_ln284_110_fu_4105_p2");
sc_trace(mVcdFile, add_ln274_193_fu_4117_p2, "add_ln274_193_fu_4117_p2");
sc_trace(mVcdFile, add_ln274_192_fu_4128_p2, "add_ln274_192_fu_4128_p2");
sc_trace(mVcdFile, add_ln274_195_fu_4133_p2, "add_ln274_195_fu_4133_p2");
sc_trace(mVcdFile, add_ln284_111_fu_4143_p2, "add_ln284_111_fu_4143_p2");
sc_trace(mVcdFile, add_ln274_197_fu_4155_p2, "add_ln274_197_fu_4155_p2");
sc_trace(mVcdFile, add_ln274_196_fu_4166_p2, "add_ln274_196_fu_4166_p2");
sc_trace(mVcdFile, add_ln274_199_fu_4171_p2, "add_ln274_199_fu_4171_p2");
sc_trace(mVcdFile, add_ln284_112_fu_4181_p2, "add_ln284_112_fu_4181_p2");
sc_trace(mVcdFile, add_ln274_201_fu_4193_p2, "add_ln274_201_fu_4193_p2");
sc_trace(mVcdFile, add_ln274_200_fu_4204_p2, "add_ln274_200_fu_4204_p2");
sc_trace(mVcdFile, add_ln274_203_fu_4209_p2, "add_ln274_203_fu_4209_p2");
sc_trace(mVcdFile, add_ln284_113_fu_4219_p2, "add_ln284_113_fu_4219_p2");
sc_trace(mVcdFile, add_ln274_205_fu_4231_p2, "add_ln274_205_fu_4231_p2");
sc_trace(mVcdFile, add_ln274_204_fu_4242_p2, "add_ln274_204_fu_4242_p2");
sc_trace(mVcdFile, add_ln274_207_fu_4247_p2, "add_ln274_207_fu_4247_p2");
sc_trace(mVcdFile, add_ln284_114_fu_4257_p2, "add_ln284_114_fu_4257_p2");
sc_trace(mVcdFile, add_ln274_209_fu_4269_p2, "add_ln274_209_fu_4269_p2");
sc_trace(mVcdFile, add_ln274_208_fu_4280_p2, "add_ln274_208_fu_4280_p2");
sc_trace(mVcdFile, add_ln274_211_fu_4285_p2, "add_ln274_211_fu_4285_p2");
sc_trace(mVcdFile, add_ln284_115_fu_4295_p2, "add_ln284_115_fu_4295_p2");
sc_trace(mVcdFile, add_ln274_213_fu_4307_p2, "add_ln274_213_fu_4307_p2");
sc_trace(mVcdFile, add_ln274_212_fu_4318_p2, "add_ln274_212_fu_4318_p2");
sc_trace(mVcdFile, add_ln274_215_fu_4323_p2, "add_ln274_215_fu_4323_p2");
sc_trace(mVcdFile, add_ln284_116_fu_4333_p2, "add_ln284_116_fu_4333_p2");
sc_trace(mVcdFile, add_ln274_217_fu_4345_p2, "add_ln274_217_fu_4345_p2");
sc_trace(mVcdFile, add_ln274_216_fu_4356_p2, "add_ln274_216_fu_4356_p2");
sc_trace(mVcdFile, add_ln274_219_fu_4361_p2, "add_ln274_219_fu_4361_p2");
sc_trace(mVcdFile, add_ln284_117_fu_4371_p2, "add_ln284_117_fu_4371_p2");
sc_trace(mVcdFile, add_ln274_221_fu_4383_p2, "add_ln274_221_fu_4383_p2");
sc_trace(mVcdFile, add_ln274_220_fu_4394_p2, "add_ln274_220_fu_4394_p2");
sc_trace(mVcdFile, add_ln274_223_fu_4399_p2, "add_ln274_223_fu_4399_p2");
sc_trace(mVcdFile, add_ln284_118_fu_4409_p2, "add_ln284_118_fu_4409_p2");
sc_trace(mVcdFile, add_ln274_225_fu_4421_p2, "add_ln274_225_fu_4421_p2");
sc_trace(mVcdFile, add_ln274_224_fu_4432_p2, "add_ln274_224_fu_4432_p2");
sc_trace(mVcdFile, add_ln274_227_fu_4437_p2, "add_ln274_227_fu_4437_p2");
sc_trace(mVcdFile, add_ln284_119_fu_4447_p2, "add_ln284_119_fu_4447_p2");
sc_trace(mVcdFile, add_ln274_229_fu_4459_p2, "add_ln274_229_fu_4459_p2");
sc_trace(mVcdFile, add_ln274_228_fu_4470_p2, "add_ln274_228_fu_4470_p2");
sc_trace(mVcdFile, add_ln274_231_fu_4475_p2, "add_ln274_231_fu_4475_p2");
sc_trace(mVcdFile, add_ln284_120_fu_4485_p2, "add_ln284_120_fu_4485_p2");
sc_trace(mVcdFile, add_ln274_233_fu_4497_p2, "add_ln274_233_fu_4497_p2");
sc_trace(mVcdFile, add_ln274_232_fu_4507_p2, "add_ln274_232_fu_4507_p2");
sc_trace(mVcdFile, add_ln274_235_fu_4513_p2, "add_ln274_235_fu_4513_p2");
sc_trace(mVcdFile, add_ln284_121_fu_4523_p2, "add_ln284_121_fu_4523_p2");
sc_trace(mVcdFile, add_ln274_237_fu_4535_p2, "add_ln274_237_fu_4535_p2");
sc_trace(mVcdFile, add_ln274_236_fu_4545_p2, "add_ln274_236_fu_4545_p2");
sc_trace(mVcdFile, add_ln274_239_fu_4551_p2, "add_ln274_239_fu_4551_p2");
sc_trace(mVcdFile, add_ln284_122_fu_4561_p2, "add_ln284_122_fu_4561_p2");
sc_trace(mVcdFile, add_ln274_241_fu_4573_p2, "add_ln274_241_fu_4573_p2");
sc_trace(mVcdFile, add_ln274_240_fu_4583_p2, "add_ln274_240_fu_4583_p2");
sc_trace(mVcdFile, add_ln274_243_fu_4589_p2, "add_ln274_243_fu_4589_p2");
sc_trace(mVcdFile, add_ln284_123_fu_4599_p2, "add_ln284_123_fu_4599_p2");
sc_trace(mVcdFile, add_ln274_245_fu_4611_p2, "add_ln274_245_fu_4611_p2");
sc_trace(mVcdFile, add_ln274_244_fu_4621_p2, "add_ln274_244_fu_4621_p2");
sc_trace(mVcdFile, add_ln274_247_fu_4627_p2, "add_ln274_247_fu_4627_p2");
sc_trace(mVcdFile, add_ln284_124_fu_4637_p2, "add_ln284_124_fu_4637_p2");
sc_trace(mVcdFile, add_ln274_250_fu_4660_p2, "add_ln274_250_fu_4660_p2");
sc_trace(mVcdFile, add_ln274_251_fu_4664_p2, "add_ln274_251_fu_4664_p2");
sc_trace(mVcdFile, add_ln284_125_fu_4674_p2, "add_ln284_125_fu_4674_p2");
sc_trace(mVcdFile, add_ln274_258_fu_4725_p2, "add_ln274_258_fu_4725_p2");
sc_trace(mVcdFile, add_ln274_255_fu_4729_p2, "add_ln274_255_fu_4729_p2");
sc_trace(mVcdFile, add_ln288_1_fu_4734_p2, "add_ln288_1_fu_4734_p2");
sc_trace(mVcdFile, add_ln292_1_fu_4745_p2, "add_ln292_1_fu_4745_p2");
sc_trace(mVcdFile, add_ln288_fu_4740_p2, "add_ln288_fu_4740_p2");
sc_trace(mVcdFile, add_ln292_fu_4749_p2, "add_ln292_fu_4749_p2");
sc_trace(mVcdFile, ap_NS_fsm, "ap_NS_fsm");
sc_trace(mVcdFile, ap_block_pp0_stage0_subdone, "ap_block_pp0_stage0_subdone");
sc_trace(mVcdFile, ap_idle_pp0_1to16, "ap_idle_pp0_1to16");
sc_trace(mVcdFile, ap_block_pp0_stage1_subdone, "ap_block_pp0_stage1_subdone");
sc_trace(mVcdFile, ap_block_pp0_stage2_subdone, "ap_block_pp0_stage2_subdone");
sc_trace(mVcdFile, ap_idle_pp0_0to15, "ap_idle_pp0_0to15");
sc_trace(mVcdFile, ap_reset_idle_pp0, "ap_reset_idle_pp0");
sc_trace(mVcdFile, ap_block_pp0_stage4_subdone, "ap_block_pp0_stage4_subdone");
sc_trace(mVcdFile, ap_block_pp0_stage5_subdone, "ap_block_pp0_stage5_subdone");
sc_trace(mVcdFile, ap_block_pp0_stage6_subdone, "ap_block_pp0_stage6_subdone");
sc_trace(mVcdFile, ap_enable_pp0, "ap_enable_pp0");
#endif
}
}
sha256_transform::~sha256_transform() {
if (mVcdFile)
sc_close_vcd_trace_file(mVcdFile);
delete grp_MAJ_fu_864;
delete grp_MAJ_fu_876;
delete grp_MAJ_fu_885;
delete grp_MAJ_fu_894;
delete grp_MAJ_fu_903;
delete grp_MAJ_fu_912;
delete grp_MAJ_fu_921;
delete grp_MAJ_fu_930;
delete grp_EP1_fu_939;
delete grp_EP1_fu_947;
delete grp_EP1_fu_954;
delete grp_EP1_fu_961;
delete grp_EP1_fu_968;
delete grp_EP1_fu_975;
delete grp_EP1_fu_982;
delete grp_EP1_fu_989;
delete grp_EP0_fu_996;
delete grp_EP0_fu_1004;
delete grp_EP0_fu_1011;
delete grp_EP0_fu_1018;
delete grp_EP0_fu_1025;
delete grp_EP0_fu_1032;
delete grp_EP0_fu_1039;
delete grp_EP0_fu_1046;
delete grp_SIG1_fu_1053;
delete grp_SIG1_fu_1060;
delete grp_SIG1_fu_1067;
delete grp_SIG1_fu_1074;
delete grp_SIG1_fu_1081;
delete grp_SIG1_fu_1088;
delete grp_SIG0_fu_1095;
delete grp_SIG0_fu_1102;
delete grp_SIG0_fu_1109;
delete grp_SIG0_fu_1116;
delete grp_SIG0_fu_1123;
delete grp_SIG0_fu_1130;
delete grp_CH_fu_1137;
delete grp_CH_fu_1149;
delete grp_CH_fu_1158;
delete grp_CH_fu_1167;
delete grp_CH_fu_1176;
delete grp_CH_fu_1185;
delete grp_CH_fu_1194;
delete grp_CH_fu_1203;
}
}
| [
"guhey.ambuj@gmail.com"
] | guhey.ambuj@gmail.com |
2289d8992b846c156434a77b53e4849abb92af64 | 9280fea108f5b3912629de7851f6bbbde561c9a4 | /src/drivers/xsens_driver/src/xsens_gps_translator.cpp | 5baa2edc9ec209b3a059862457894fb9131ce8da | [
"MIT",
"Apache-2.0"
] | permissive | bytetok/vde | 93071992618b7c539cd618eaae24d65f1099295b | ff8950abbb72366ed3072de790c405de8875ecc3 | refs/heads/main | 2023-08-23T15:08:14.644017 | 2021-10-09T03:59:09 | 2021-10-09T03:59:09 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 6,074 | cpp | // Copyright 2018 the Autoware Foundation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Co-developed by Tier IV, Inc. and Apex.AI, Inc.
#include <cstring>
#include <cmath>
#include <limits>
#include <numeric>
#include <utility>
#include <vector>
#include <iostream>
#include <iomanip>
#include "sensor_msgs/msg/nav_sat_fix.hpp"
#include "sensor_msgs/msg/nav_sat_status.hpp"
#include "xsens_driver/xsens_common.hpp"
#include "xsens_driver/xsens_gps_translator.hpp"
#include "helper_functions/byte_reader.hpp"
#include "common/types.hpp"
using autoware::common::types::float64_t;
namespace autoware
{
namespace drivers
{
namespace xsens_driver
{
////////////////////////////////////////////////////////////////////////////////
XsensGpsTranslator::XsensGpsTranslator(const Config &)
: XsensBaseTranslator()
{
}
void XsensGpsTranslator::parse_xdigroup_mtdata2(
XDIGroup xdigroup,
sensor_msgs::msg::NavSatFix & message,
int32_t data_id,
const std::vector<uint8_t> & content)
{
switch (xdigroup) {
case XDIGroup::TEMPERATURE:
break;
case XDIGroup::TIMESTAMP:
break;
case XDIGroup::ORIENTATION_DATA:
break;
case XDIGroup::PRESSURE:
break;
case XDIGroup::ACCELERATION:
break;
case XDIGroup::POSITION:
break;
case XDIGroup::GNSS:
parse_gnss(message, data_id, content);
break;
case XDIGroup::ANGULAR_VELOCITY:
break;
case XDIGroup::GPS:
break;
case XDIGroup::SENSOR_COMPONENT_READOUT:
break;
case XDIGroup::ANALOG_IN:
break;
case XDIGroup::MAGNETIC:
break;
case XDIGroup::VELOCITY:
break;
case XDIGroup::STATUS:
break;
default:
throw std::runtime_error("Unknown group");
}
}
void XsensGpsTranslator::parse_gnss(
sensor_msgs::msg::NavSatFix & message,
int32_t data_id,
const std::vector<uint8_t> & content)
{
const GNSS value = GNSS_from_int(static_cast<uint8_t>(data_id & 0x00F0));
switch (value) {
case GNSS::PVT_DATA:
{
autoware::common::helper_functions::ByteReader byte_reader(content);
uint32_t itow = 0;
byte_reader.read(itow);
uint16_t year = 0;
byte_reader.read(year);
uint8_t month = 0;
byte_reader.read(month);
uint8_t day = 0;
byte_reader.read(day);
uint8_t hour = 0;
byte_reader.read(hour);
uint8_t minute = 0;
byte_reader.read(minute);
uint8_t second = 0;
byte_reader.read(second);
uint8_t valid = 0;
byte_reader.read(valid);
uint32_t tAcc = 0;
byte_reader.read(tAcc);
int32_t nano = 0;
byte_reader.read(nano);
uint8_t fixtype = 0;
byte_reader.read(fixtype);
uint8_t flags = 0;
byte_reader.read(flags);
uint8_t numSV = 0;
byte_reader.read(numSV);
// Skip pad byte
byte_reader.skip(1);
int32_t lon = 0;
byte_reader.read(lon);
int32_t lat = 0;
byte_reader.read(lat);
int32_t height = 0;
byte_reader.read(height);
int32_t hMSL = 0;
byte_reader.read(hMSL);
uint32_t hAcc = 0;
byte_reader.read(hAcc);
uint32_t vAcc = 0;
byte_reader.read(vAcc);
int32_t velN = 0;
byte_reader.read(velN);
int32_t velE = 0;
byte_reader.read(velE);
int32_t velD = 0;
byte_reader.read(velD);
int32_t gSpeed = 0;
byte_reader.read(gSpeed);
int32_t headMot = 0;
byte_reader.read(headMot);
uint32_t sAcc = 0;
byte_reader.read(sAcc);
uint32_t headAcc = 0;
byte_reader.read(headAcc);
int32_t headVeh = 0;
byte_reader.read(headVeh);
uint16_t gdop = 0;
byte_reader.read(gdop);
uint16_t pdop = 0;
byte_reader.read(pdop);
uint16_t tdop = 0;
byte_reader.read(tdop);
uint16_t vdop = 0;
byte_reader.read(vdop);
uint16_t hdop = 0;
byte_reader.read(hdop);
uint16_t ndop = 0;
byte_reader.read(ndop);
uint16_t edop = 0;
byte_reader.read(edop);
// scaling correction
float64_t dlon = lon * 1e-7;
float64_t dlat = lat * 1e-7;
float64_t dheadMot = headMot * 1e-5;
float64_t dheadVeh = headVeh * 1e-5;
float64_t dgdop = gdop * 0.01;
float64_t dpdop = pdop * 0.01;
float64_t dtdop = tdop * 0.01;
float64_t dvdop = vdop * 0.01;
float64_t dhdop = hdop * 0.01;
float64_t dndop = ndop * 0.01;
float64_t dedop = edop * 0.01;
// NOTE(esteve): None of this is actually necessary for the ROS NavSatFix message
(void)dheadMot;
(void)dheadVeh;
(void)dgdop;
(void)dpdop;
(void)dtdop;
(void)dvdop;
(void)dhdop;
(void)dndop;
(void)dedop;
if (fixtype == 0x00) {
message.status.status = sensor_msgs::msg::NavSatStatus::STATUS_NO_FIX;
message.status.service = 0;
} else {
message.status.status = sensor_msgs::msg::NavSatStatus::STATUS_FIX;
message.status.service = sensor_msgs::msg::NavSatStatus::SERVICE_GPS;
}
message.latitude = dlat;
message.longitude = dlon;
message.altitude = height / 1e3;
}
break;
case GNSS::SATELLITES_INFO:
break;
}
}
} // namespace xsens_driver
} // namespace drivers
} // namespace autoware
| [
"Will.Heitman@utdallas.edu"
] | Will.Heitman@utdallas.edu |
f3d611724a224fd4e2d0285d99a34f9f6705e15a | 6f3ededa42c35f313a7d34c591d732b2602a9a5e | /ouzel/core/ios/EngineIOS.hpp | 272262692ed618ccb9512a4e357814807883b5c0 | [
"BSD-2-Clause",
"BSD-3-Clause"
] | permissive | WooZoo86/ouzel | ebd0f2a13aa76e447c80ed03eda797bf6e625e83 | 7c950c4dc7c73d5f2e8ccce69fee9c876b9ac5ba | refs/heads/master | 2021-05-14T07:41:52.977341 | 2017-12-23T04:05:48 | 2017-12-23T04:05:48 | null | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 738 | hpp | // Copyright (C) 2017 Elviss Strazdins
// This file is part of the Ouzel engine.
#pragma once
#include <dispatch/dispatch.h>
#include "core/Engine.hpp"
namespace ouzel
{
class EngineIOS: public Engine
{
public:
EngineIOS(int aArgc, char* aArgv[]);
virtual int run() override;
virtual void executeOnMainThread(const std::function<void(void)>& func) override;
virtual bool openURL(const std::string& url) override;
virtual void setScreenSaverEnabled(bool newScreenSaverEnabled) override;
virtual bool setCurrentThreadName(const std::string& name) override;
protected:
dispatch_queue_t mainQueue;
int argc = 0;
char** argv = nullptr;
};
}
| [
"elviss@elviss.lv"
] | elviss@elviss.lv |
c71224b1013f73606b45c1ab533e818abe9c1fab | 6fabf246882ce46d715c75589e6f8ea3d37fb2a6 | /BruinNav/MyMap.h | aabd106e2cf6e608abb8ad044446b813998928d6 | [] | no_license | biankaursul/projects | dee7f41037777ebcd6063f583be539022b63b540 | 6ee008c94060c13e2ee7c9ab9cbf81bbf5bf8aa8 | refs/heads/master | 2020-04-09T03:18:47.992359 | 2018-12-01T20:41:32 | 2018-12-01T20:41:32 | 159,977,528 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 2,846 | h | // MyMap.h
// Skeleton for the MyMap class template. You must implement the first six
// member functions.
#include <unistd.h>
#include <iostream>
using namespace std;
template<typename KeyType, typename ValueType>
class MyMap
{
public:
MyMap()
{
m_root = NULL;
m_size = 0;
}
~MyMap()
{
clear();
}
void clear()
{
freeTree(m_root);
m_root = NULL;
m_size = 0;
}
int size() const
{
return m_size;
}
void associate(const KeyType& key, const ValueType& value)
{
ValueType* ptr = find(key);
if(ptr != nullptr)
*ptr = value;
else
insert(key, value);
}
// for a map that can't be modified, return a pointer to const ValueType
const ValueType* find(const KeyType& key) const
{
Node* cur = m_root;
while( cur != NULL)
{
if (cur->key == key)
return &(cur->value);
else if (cur->key < key)
cur = cur->right;
else
cur = cur->left;
}
return nullptr;
}
// for a modifiable map, return a pointer to modifiable ValueType
ValueType* find(const KeyType& key)
{
return const_cast<ValueType*>(const_cast<const MyMap*>(this)->find(key));
}
// C++11 syntax for preventing copying and assignment
MyMap(const MyMap&) = delete;
MyMap& operator=(const MyMap&) = delete;
private:
struct Node
{
Node(const KeyType& akey, const ValueType& avalue)
:key(akey)
{
//key = akey;
value = avalue;
left = right = NULL;
}
const KeyType key;
ValueType value;
Node* left;
Node* right;
};
Node* m_root;
int m_size;
void freeTree(Node* cur)
{
if (cur == NULL)
return;
freeTree(cur->left);
freeTree(cur->right);
delete cur;
}
void insert(const KeyType& key, const ValueType& value)
{
if(m_root == nullptr)
{
m_root = new Node(key, value);
m_size++;
return;
}
Node* cur = m_root;
for(;;)
{
if(cur->key == key) return;
else if(cur->key < key)
{
if(cur->right == nullptr){
cur->right = new Node(key, value);
m_size++;
return;
}
else cur = cur->right;
}
else if(cur->key > key)
{
if(cur->left == nullptr)
{
cur->left = new Node(key, value);
m_size++;
return;
}
else cur = cur->left;
}
}
}
};
| [
"37175449+biankaursul@users.noreply.github.com"
] | 37175449+biankaursul@users.noreply.github.com |
f15dbaf7d541881cf148b18bf124d8d5f855d0f2 | 48fc028918006422bffac99107af6dd30cc3716e | /src/test/bswap_tests.cpp | 60d890c03b40f987282c6e1cc761ce5a5742ad32 | [
"MIT"
] | permissive | kawriscoin/Kawris | 160c3a8c597fb85a2c092f334c6635b2f37d9b33 | 404ee3940039719cfa4c87f6ebca6641c08685c9 | refs/heads/main | 2023-08-06T15:14:36.477769 | 2021-10-09T13:16:25 | 2021-10-09T13:16:25 | 366,500,796 | 0 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 735 | cpp | // Copyright (c) 2016 The Bitcoin Core developers
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
#include "compat/byteswap.h"
#include "test/test_kawris.h"
#include <boost/test/unit_test.hpp>
BOOST_FIXTURE_TEST_SUITE(bswap_tests, BasicTestingSetup)
BOOST_AUTO_TEST_CASE(bswap_tests)
{
// Sibling in bitcoin/src/qt/test/compattests.cpp
uint16_t u1 = 0x1234;
uint32_t u2 = 0x56789abc;
uint64_t u3 = 0xdef0123456789abc;
uint16_t e1 = 0x3412;
uint32_t e2 = 0xbc9a7856;
uint64_t e3 = 0xbc9a78563412f0de;
BOOST_CHECK(bswap_16(u1) == e1);
BOOST_CHECK(bswap_32(u2) == e2);
BOOST_CHECK(bswap_64(u3) == e3);
}
BOOST_AUTO_TEST_SUITE_END()
| [
"81927663+kawriscoin@users.noreply.github.com"
] | 81927663+kawriscoin@users.noreply.github.com |
072a4fb0b12f6e603de1401bacc2d3eac6c464f3 | 7058dc235f1e2f686e1183e8b81ea7c3587447ed | /dnhobf.cc | aae2896117c212f57a6887276f3eb74e4114476b | [] | no_license | Sparen/DanmakufuObfuscator | 4878eb36a69060600d26f08e180b6e602e8ba07a | 5b0e92345158ad3829593b51ecb881f292f41a98 | refs/heads/master | 2021-01-23T22:05:41.400633 | 2017-02-05T21:31:40 | 2017-02-05T21:31:40 | 37,858,967 | 6 | 0 | null | null | null | null | UTF-8 | C++ | false | false | 1,886 | cc | #include <iostream>
#include <vector>
#include <string>
#include <stdio.h>
#include <stdlib.h>
#include "dnhobf_fxn.h"
using std::string;
using std::cout;
using std::cin;
using std::endl;
using std::vector;
int main(int argc, char** argv){
cout << endl << "DANMAKUFU OBFUSCATOR BY SPAREN" << endl;
cout << "~~~This program is use-at-your-own-risk.~~~" << endl;
cout << "~~~Please make sure you have backed up your code before using this program.~~~" << endl;
if(argc<2){
cout << "Error: No File Specified." << endl;
cout << "Usage: ./dnhobf filename.ext" << endl;
}
for(int i = 1; i < argc; i++){//for every file
FILE* infile = fopen(argv[i], "r");
if(infile){//exists
freopen(argv[i], "r+", infile);
cout << "Preparing " << argv[i] << " for obfuscation." << endl;
fclose(infile);
string filename(argv[i]);
//prompt user for obfuscation level here
cout << "Please select an obfuscation level for " << filename << endl;
string input;
bool satisfied = false;
while(!satisfied){
cout << "1: Only remove comments - good for shrinking filesize" << endl;
cout << "2: Remove comments and whitespace" << endl;
cout << "q: quit" << endl;
cout << "Option 2 may be unstable. Please submit bug reports via Github Issues." << endl;
cin >> input;
if(input == "1"){
ObfuscateA1(filename); satisfied = true;
}else if(input == "2"){
ObfuscateA2(filename); satisfied = true;
}else if(input == "q" || input == "Q"){
cout << "Thank you for using Sparen's Danmakufu Obfuscator" << endl;
exit(EXIT_SUCCESS);
}else{
cout << "Invalid input. Please type '1', '2', or 'q' without quotes." << endl;
}
}
}else{
cout << "Error: " << argv[i] << " does not exist." << endl;
fclose(infile);
}
}
cout << "Thank you for using Sparen's Danmakufu Obfuscator" << endl;
return 0;
}
| [
"andrewsuicune@gmail.com"
] | andrewsuicune@gmail.com |
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