path stringlengths 21 275 | code stringlengths 43 5.18M |
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1801BM1_cpu11/f11/hdl/wbc/rtl/dc_fpp.v | //
// Copyright (c) 2014-2022 by 1801BM1@gmail.com
//
// DC304 MMU Chip Floating Point Register File
//______________________________________________________________________________
//
// Generic implementation of Register File, memory blocks are supposed to be
// inferred. Some verions of synthesys tools (Quartus, etc... |
1801BM1_cpu11/am4/hdl/syn/tbe/de0_tb4.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//
// Testbench for the M4 replica, native QBUS version
//______________________________________________________________________________
//
`include "../../tbe/config.v"
//______________________________________________________________________________
//
module memory
(
... |
1801BM1_cpu11/am4/hdl/org/rtl/am4_plm.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// M4 processor PDP-11 instruction decoding PLM (D123, D136)
//
module plm_dec
(
input [15:0] ins, // PDP-11 instruction opcode
output reg bf, // byte operation flag
... |
1801BM1_cpu11/am4/hdl/syn/rtl/am4.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
module am4
(
input pin_clk, // processor clock
input pin_dclo_n, // processor reset
input pin_aclo_n, // power fail notification
input ... |
1801BM1_cpu11/lsi/hdl/org/rtl/mcp1611.v | //
// Copyright (c) 2014-2020 by 1801BM1@gmail.com
//
// MCP-1611 Data Chip model, for debug and simulating only
//______________________________________________________________________________
//
module mcp1611
(
input pin_c1, // clock phase 1
input pin_c2, // clock phase 2
inp... |
1801BM1_cpu11/lsi/hdl/org/rtl/lsi.v | //
// Copyright (c) 2014-2019 by 1801BM1@gmail.com
//
// LSI-11 asynchronous model, for debug and modelling only
// This file contains the wrapper for MCP-1600 chipset,
// it implements external circuits of the M2/KD-11A processor
// without onboard dynamic memory and its controller.
//_________________________________... |
1801BM1_cpu11/am4/hdl/syn/rtl/am4_seq.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// Microprogram Sequencer - combination of Am2909 and 29811,
// adopted for M4 project, with configurable micro-address width
//
module am4_seq
#(parameter
AM4_ADDR_WIDTH = 10
)
(
inpu... |
1801BM1_cpu11/f11/hdl/wbc/rtl/dc_302.v | //
// Copyright (c) 2014-2021 by 1801BM1@gmail.com
//
// DC302 Data Chip model
//______________________________________________________________________________
//
module dc302
(
input pin_clk, // main clock
input pin_mce_p, // master rising edge
input pin_mce_n, // master fallin... |
1801BM1_cpu11/f11/hdl/org/tbe/tb_rom.v | //
// Copyright (c) 2021 by 1801BM1@gmail.com
//
// Testbench for the KDF-11A control lines decoding ROM
//______________________________________________________________________________
//
`include "../../tbe/config.v"
module tb_test_rom
(
input [4:0] a,
output [7:0] d
);
reg [7:0] rom;
assign d = rom;
always... |
1801BM1_cpu11/am4/hdl/org/rtl/am4_2902.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// Hig-Speed Look-Ahead Carry Generator
//
module am2902
(
input cin, // carry input
input [3:0] g_n, // carry generate input
input [3:0] p_n, //... |
1801BM1_cpu11/f11/hdl/wbc/rtl/dc_303.v | //
// Copyright (c) 2014-2022 by 1801BM1@gmail.com
//
// DC303 Control Chip model
//
// - DC303_CS = 0, 23-001C7-AA, rni = ma[8:0] == 9'x000
// - DC303_CS = 1, 23-002C7-AA, rni = ma[8:0] == 9'x000
// - DC303_CS = 2, 23-203C7-AA, rni = ma[8:4] == 5'x00
//_______________________________________________________________... |
1801BM1_cpu11/f11/hdl/org/tbe/tb_alu.v | //
// Copyright (c) 2021 by 1801BM1@gmail.com
//
// Testbench for the DC302 ALU decoder
//______________________________________________________________________________
//
`include "../../tbe/config.v"
module tb_302();
integer i;
reg clk;
reg [15:0] mi;
tri1 [15:0] ad;
tri1 [15:0] m;
reg ez_n;
tri1 bs;
//_______... |
1801BM1_cpu11/f11/hdl/org/tbe/de0_top.v | //
// Copyright (c) 2014-2019 by 1801BM1@gmail.com
//
// Top module for DE0 board based system
//______________________________________________________________________________
//
// Top project module - instantiates the DE0 board itself
//
module de0
(
input de0_clock_50, // clock input 50 MHz
inp... |
1801BM1_cpu11/am4/hdl/wbc/rtl/am4_mcrom.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//
//______________________________________________________________________________
//
// M4 microcode ROM, for debug and simulating only
//
module mcrom
(
input clk, // input clock
input ena, // clock enable
input [9:0] addr, // instruction ... |
1801BM1_cpu11/am4/hdl/org/tbe/de0_tb4.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//
// Testbench for the M4 replica, native QBUS version
//______________________________________________________________________________
//
`include "../../tbe/config.v"
//______________________________________________________________________________
//
module memory
(
... |
1801BM1_cpu11/lsi/hdl/org/rtl/mcp1621.v | //
// Copyright (c) 2014-2020 by 1801BM1@gmail.com
//
// MCP-1621 Control Chip model, for debug and simulating only
//______________________________________________________________________________
//
module mcp1621
(
input pin_c1, // clock phase 1
input pin_c2, // clock phase 2
... |
1801BM1_cpu11/f11/hdl/syn/tbe/de0_tbl.v | //
// Copyright (c) 2021 by 1801BM1@gmail.com
//
// Testbench for the F-11 replica, external QBUS version
//______________________________________________________________________________
//
`include "../../tbe/config.v"
//______________________________________________________________________________
//
module memory
(... |
1801BM1_cpu11/f11/hdl/wbc/rtl/dc_pla.v | //
// Copyright (c) 2014-2022 by 1801BM1@gmail.com
//
//______________________________________________________________________________
//
// PLA matrix:
// - 23 inputs - 7 lower bits of next address, 16 bits of data
// - selected if upper next address bits na[8:7] are both zeroes
// - 25 outputs - 9 bits of ne... |
1801BM1_cpu11/am4/hdl/org/rtl/am4_29811.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// Microinstruction decoder
//
module am29811
(
input tst, // entry for conditional instructions
input [3:0] i, // microcode instruction
//
o... |
1801BM1_cpu11/am4/hdl/org/rtl/am4_delay.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// Delay line
//
module am4_delay
(
input clk, // DLL input clock
input inp, // DLL input data
output [9:0] phase // DLL outputs
);
reg [9:0] dll; ... |
1801BM1_cpu11/am4/hdl/wbc/rtl/am4_plm.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//______________________________________________________________________________
//
// M4 processor PDP-11 instruction decoding PLM (D123, D136)
//
module plm_dec
(
input [15:0] ins, // PDP-11 instruction opcode
output reg bf, // byte operation flag
... |
1801BM1_cpu11/f11/hdl/org/rtl/dc_rom.v | //
// Copyright (c) 2014-2022 by 1801BM1@gmail.com
//
//______________________________________________________________________________
//
// MicROM module, (128 + 10) lines x 4 pages x 25-bit words
// 25-bit word provides 9-bit next address in the upper bits,
// the rest is 16-bit microcode opcode
//
module dc_rom
#(pa... |
1801BM1_cpu11/f11/hdl/org/tbe/de0_tbl.v | //
// Copyright (c) 2021 by 1801BM1@gmail.com
//
// Testbench for the F-11 replica, external QBUS version
//______________________________________________________________________________
//
`include "../../tbe/config.v"
//______________________________________________________________________________
//
module memory
(... |
1801BM1_cpu11/lsi/hdl/syn/rtl/mcp1631.v | //
// Copyright (c) 2014-2019 by 1801BM1@gmail.com
//
// MCP-1631 MicROM model, for debug and simulating only
//______________________________________________________________________________
//
//
module mcp1631
(
input pin_clk, // main clock
input [10:0] pin_lc, // location counter
out... |
1801BM1_cpu11/am4/hdl/syn/rtl/am4_mcrom.v | //
// Copyright (c) 2020 by 1801BM1@gmail.com
//
//______________________________________________________________________________
//
// M4 microcode ROM, for debug and simulating only
//
`timescale 1ns / 100ps
module mcrom
(
input clk, // input clock
input ena, // clock enable
input [9:0] ... |
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