text stringlengths 41 20k |
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/*
============================================================================
Name : displayYUV.c
Author : mpelcat & kdesnos & jheulot
Modified by : jserot (for use in the HoCL framework)
Version :
Copyright : CECILL-C
Description : Displaying YUV frames one next to another in a row
================... |
/*******************************************************************************
* tpencoder.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a testbench module to emulate a rotary quad encoder with a bu... |
#include <systemc.h>
class sc_mutexx : public sc_prim_channel
{
public:
sc_event _free;
bool _locked;
// blocks until mutex could be locked
void lock()
{
while( _locked ) {
wait( _free );
}
_locked = true;
}
// returns false if mutex could not be lock... |
#include "systemc.h"
#include "../cnm_base.h"
SC_MODULE(cu_driver) {
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM activate command
// sc_out<sc_logic> RSTB; //
sc_out<sc_logic>... |
/**************************************************************************
* *
* Catapult(R) Machine Learning Reference Design Library *
* *
* Software Ver... |
/*******************************************************************************
Vendor: GoodKook, goodkook@gmail.com
Associated Filename: sc_shifter_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_SHIFTER_TB_H_
#defi... |
/*
$Id: ticks.h,v 1.3 2010/11/23 22:42:02 scott Exp $
Description: Macros for timing
Usage: Define the timer call desired (e.g. #define FTIME, TIMEOFDAY, GETTIME)
before including "ticks.h"
Example:
#define TIMEOFDAY 1
#include "ticks.h"
void benchmark(void)
{
tick_t start, finish;
tget(start);
timed_section();
... |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: arp@poshtkohi.info
Website: http://www.poshtkohi.info
*/
#ifndef DEFINE_H
#define DEFINE_H
#include "systemc.h"
//#include <iostream>
#include "stdio.h"
#define SIZE 16
#define NB 4
#def... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
/*
Problem 3 Testbench
*/
#include<systemc.h>
#include<comm.cpp>
SC_MODULE(communicationInterfaceTB) {
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
/*
* Copyright 2019 Google, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* ... |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses... |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// =======================================... |
// -------------------------------------------------
// Contact: contact@lubis-eda.com
// Author: Tobias Ludwig, Michael Schwarz
// -------------------------------------------------
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file ... |
/// \file transmitter.h
/// \brief File containing the entity of the transmitter component.
///
/// See also transmitter.cpp
#ifndef TRANSMITTER_H
#define TRANSMITTER_H
#include <systemc.h>
#include "NOC_package.h"
/*! \class transmitter
\brief SystemC description of the transmitter module.
It is the transmi... |
/*
* breg_if.h
*
* Created on: 14 de mai de 2017
* Author: drcfts
*/
#ifndef BREG_IF_H_
#define BREG_IF_H_
#include "systemc.h"
#include <stdint.h>
struct breg_if : public sc_interface{
virtual int32_t
read(const unsigned address) = 0;
virtual void
write(const unsigned address, int32_t dado) = 0;
... |
/*******************************************************************************
* adc_types.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Defines types of ESP32 ADC being used.
*******************************... |
//
// Created by tobias on 29.11.17.
//
#ifndef PROJECT_EXAMPLE2_H
#define PROJECT_EXAMPLE2_H
#include "systemc.h"
#include "Interfaces.h"
#include "types.h"
struct Example4 : public sc_module {
SC_HAS_PROCESS(Example4);
Example4(sc_module_name name) :
master_in1("master_in1"),
value... |
/**********************************************************************
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#inc... |
/**************************************************************************
* *
* Catapult(R) Machine Learning Reference Design Library *
* *
* Software Ver... |
#include <systemc.h>
SC_MODULE( fir ) {
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void... |
#ifndef COUNTER_H
#define COUNTER_H
#include <systemc.h>
#include "constants.h"
SC_MODULE(CounterModule){
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_int... |
#ifndef __I2C_CONTROLLER_TB_H
#define __I2C_CONTROLLER_TB_H
#include <systemc.h>
#include <i2c_controller.h>
#include <i2c_slave_controller.h>
SC_MODULE(i2c_controller_tb)
{
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> ... |
/*******************************************************************************
Poorman's Standard-Emulator
---------------------------
Vendor: GoodKook, goodkook@gmail.com
Associated Filename: sc_DUT_TB.h
Purpose: Testbench for DUT
Revision History: Jun. 1, 2024
*******************************************************... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], cloc... |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: arp@poshtkohi.info
Website: http://www.poshtkohi.info
*/
#ifndef __s3_h__
#define __s3_h__
#include <systemc.h>
SC_MODULE(s3)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > ... |
#include <systemc.h>
SC_MODULE ( half_adder ) {
sc_in< sc_logic > augend;
sc_in< sc_logic > addend;
sc_out< sc_logic > sum;
sc_out< sc_logic > carry_out;
void func();
SC_CTOR ( half_adder ) {
SC_METHOD ( func );
sensitive << augend << addend;
};
};
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* ... |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* ... |
array = new float*[5]; //TODO: eliminare **?
//Int8
float idCC4CSminint8 = 0;
float idCC4CSmaxint8 = 0;
//Int16
float idCC4CSminint16 = 0;
float idCC4CSmaxint16 = 0;
//Int32
float idCC4CSminint32 = 0;
float idCC4CSmaxint32 = 0;
//Float
float idCC4CSminfloat = 0;
float idCC4CSmaxfl... |
.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
for (xml_node_iterator seqProcess_it=instancesPS.begin(); seqProcess_it!=instancesPS.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_v... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*... |
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_... |
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Mon Nov 16 23:44:47 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Tue Nov 17 14:53:19 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_... |
#ifndef TESTBENCH_
#define TESTBENCH_
#include <systemc.h>
SC_MODULE (tbreg){
//l'horloge
sc_in <bool> clk;
sc_out < sc_uint<11> > din;
sc_in < sc_uint<15> > coded_dout;
sc_out < sc_uint<15> > coded_din;
sc_in < sc_uint<11> > dout;
//hand shake signals
sc_out < bool > din_vld;
sc_in < bool >... |
#ifndef NEURON_H
#define NEURON_H
#include "systemc.h"
SC_MODULE(Neuron) {
sc_in<float> input1, input2;
sc_out<float> output;
float w1, w2, b, y;
float output_temp;
void neuron();
SC_CTOR(Neuron) {
SC_METHOD(neuron);
sensitive << input1 << input2;
}
};
#endif |
#include <systemc.h>
#ifndef ACC_H
#define ACC_H
//#define __SYNTHESIS__
//#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME SA_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#defin... |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: arp@poshtkohi.info
Website: http://www.poshtkohi.info
*/
#ifndef __s6_h__
#define __s6_h__
#include <systemc.h>
SC_MODULE(s6)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > ... |
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FI... |
/*******************************************************************************
* mux_in.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for the PCNT mux in the GPIO matrix.
******************************... |
#include <systemc.h>
SC_MODULE(tb)
{
sc_in<bool> clk;
sc_out<bool> reset;
sc_out< sc_int<16> > input;
sc_out<bool> input_valid;
sc_in<bool> input_ready;
sc_in< sc_int<16> > output;
sc_in<bool> output_valid;
sc_out<bool> output_ready;
void source();
void sink();
SC_CTOR(tb){
SC_C... |
#include "Neuron.h"
#include "systemc.h"
SC_MODULE(Neural_Network) {
sc_in<float> input1, input2;
sc_out<float> output;
sc_signal<float> c1, c2;
Neuron* N1;
Neuron* N2;
Neuron* N3;
SC_CTOR(Neural_Network) {
// vvvvv put your code here vvvvv
N1 = new Neuron("N1");
... |
#include "systemc.h"
SC_MODULE(tb) {
sc_out < sc_uint<4> > OPa,OPb;
sc_out < sc_uint<4> > OP;
sc_in<bool> Clk;
void tbGen() {
OPa.write(0111);
OPb.write(0001);
OP.write(0);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(1);
wait(10,SC_NS);
OPa.write(0111);
OPb... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:45:43 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
#include "dut_Div_64Ux2U_32U_4.h"
/* Declaration of the synthesized module. */
str... |
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*... |
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_... |
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
... |
/******************************************************************************
* (C) Copyright 2014 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apac... |
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/cnn/data_buffer.h"
#include "hwcore/cnn/pe.h"
#include "hwcore/cnn/top_cnn.h"
#include "hwcore/cnn/weight_buffer.h"
#include "hwcore/hw/statusreg.h"
#include "hwcore/pipes/pipes.h"
#inclu... |
//
// Created by tobias on 29.11.17.
//
#ifndef PROJECT_STIMULI2_H
#define PROJECT_STIMULI2_H
#include "systemc.h"
#include "Interfaces.h"
#include "types.h"
struct Stimuli2 : public sc_module {
SC_HAS_PROCESS(Stimuli2);
Stimuli2(sc_module_name name) :
value("value")
{ SC_THREAD(fsm); }
//B... |
// ----------------------------------------------------------------------------
// SystemC SCVerify Flow -- sysc_sim_trans.cpp
//
// HLS version: 10.4b/841621 Production Release
// HLS date: Thu Oct 24 17:20:07 PDT 2019
// Flow Packages: HDL_Tcl 8.0a, SCVerify 10.4
//
// Generated by: billyk@cad.eecs.harvar... |
_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[3].Connections::InBlocking<ac_int<8, true ... |
3181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7... |
/*******************************************************************************
* mux_pcnt.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for the PCNT mux in the GPIO matrix.
******************************... |
#pragma once
#include <systemc.h>
//#include "../CORE/core.h"
#include "../../CORE/core.h"
#include "CACHES/icache.h"
#include "CACHES/dcache.h"
#include "wb_river_mc.h"
SC_MODULE(IP_RIVER)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_ui... |
#ifndef I_CACHE
#define I_CACHE
#include <systemc.h>
#include "../../../UTIL/debug_util.h"
SC_MODULE(icache)
{
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> ... |
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
#include "sc_run.h"
SC_MODULE (scClk) {
// --------------------- Ports ---------------------
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk) {
SC_THREAD(clockThread);
}
void clockThread () {
sc_time... |
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], cloc... |
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
#include "../../UTIL/fifo.h"
#define x12x2_size 130
SC_MODULE(x1_multiplier)
{
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPT... |
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER... |
/**********************************************************************
Filename: E_fir_pe.h
Purpose : FPGA Emulated PE of Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _E_FIR_PE_H_
#define _E_FIR_PE_... |
/*******************************************************************************
Vendor: GoodKook, goodkook@gmail.com
Associated Filename: sc_dffrs_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_DFFRS_TB_H_
#define _... |
//---------------------------------------------------------------------------------------
//
// DISTRIBUTED HEMPS - version 5.0
//
// Research group: GAPH-PUCRS - contact fernando.moraes@pucrs.br
//
// Distribution: September 2013
//
// Source name: queue.h
//
// Brief description: Methods of process co... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:46:16 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
#include "dut_Div_64Ux2U_32U_4.h"
/* Declaration of the synthesized module. */
str... |
/* Copyright 2017 Pedro Cuadra <pjcuadra@gmail.com> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless req... |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: arp@poshtkohi.info
Website: http://www.poshtkohi.info
*/
#ifndef __s8_h__
#define __s8_h__
#include <systemc.h>
SC_MODULE(s8)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> >... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Tue Nov 17 14:07:23 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_... |
#include "systemc.h"
#include "../cnm_base.h"
#include "../half.hpp"
using half_float::half;
SC_MODULE(fpu_driver) {
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_out<sc_logic> add_en; // Signals that an ad... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
/**
* @file sc_clk.h
* @brief This file contains the SystemC module for the clock
* @ingroup systemc_modules
*/
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
//#include "sc_run.h"
SC_MODULE(scClk)
{
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk)
{
SC_THREAD(clockTh... |
//
// Created by ludwig on 30.01.17.
//
#include <Interfaces.h>
#include "systemc.h"
enum trans_t {
SINGLE_READ, SINGLE_WRITE
};
enum ack_t {
OK, RTY, ERR
};
enum addr_t {
SLAVE0, SLAVE1, SLAVE2, SLAVE3
};
struct bus_req_t{
addr_t addr;
trans_t trans_type;
bool data;
};
struct bus_resp_t{
... |
/**********************************************************************
Filename: E_fir_pe.h
Purpose : Emulated PE of Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _E_FIR_PE_H_
#define _E_FIR_PE_H_
#... |
/**
* @file sc_config.h
* @brief This file contains the SystemC configuration
* @ingroup systemc_modules
*/
#ifndef SC_CONFIG_H
#define SC_CONFIG_H
#include <systemc.h>
typedef struct sc_thread_config_s
{
bool rst_act_level;
int rst_act_microsteps;
bool ena_act_level;
bool clk_act_edge;
sc_ti... |
//-----------------------------------------------------
#include <systemc.h>
/**
* @brief Enum that represents the main FPU operations
*
*/
typedef enum {
SC_FPU_ADD = 1,
SC_FPU_SUB = 2,
SC_FPU_MULT = 3,
SC_FPU_DIV = 4
} sc_fpu_op_t;
/**
* @brief Class the represent and FPU using PV model
*
*/
SC_MODU... |
#ifndef ACC_H
#define ACC_H
#include <systemc.h>
// #define __SYNTHESIS__
#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME VM_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#defi... |
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATE
#define SYSTEMC_INTEGRATE
#include <systemc.h>
#include "../ap_sysc/hls_bus_if.h"
// #include "tb_driver.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1... |
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:46:16 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_Div_64Ux2U_32U_4_h
#define CYNTH_PART_dut_dut_Div_64Ux2U_32U_4_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut_... |
//////////////////////////////////////////////////////////////////////
//// ////
//// AES subbytes module header ////
//// ////
//// This file is part of the Syste... |
#ifndef __full_adder_h__
#define __full_adder_h__
#include <systemc.h>
//---------------------------------------
SC_MODULE(full_adder)
{
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a <<... |
#ifndef LOCAL_TEST_UTILS_H
#define LOCAL_TEST_UTILS_H
// Needed for all tests
#include <Gemmini.h>
static Gemmini g("g");
static sc_signal<sc_biguint<7>> funct_write;
static sc_signal<sc_biguint<64>> rs1;
static sc_signal<sc_biguint<64>> rs2;
static sc_signal<sc_biguint<7>> opcode;
#define FUNCT_CONFIG 0
#define... |
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : goodkook@gmail.com
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FI... |
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux3) {
sc_in <bool> sel;
sc_in <sc_uint<3>> in0;
sc_in <sc_uint<3>> in1;
sc_out <sc_uint<3>> out;
/*
** module global variables
*/
SC_CTOR (Mux3){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// ... |
//
// Copyright 2022 Sergey Khabarov, sergeykhbr@gmail.com
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless requ... |
/*******************************************************************************
* btclient.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a model for a net client. It can behave as a web client or serve... |
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef __L2CACHE_H__
#define __L2CACHE_H__
#include <systemc.h>
#include <tlm.h>
// Convenience Sockets:
#include <tlm_utils/p... |
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