code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module aq_mp_rst_top (
ciu_rst_b,
clkgen_rst_b,
core0_rst_b,
forever_cpuclk,
pad_cpu_rst_b,
pad_yy_dft_clk_rst_b,
pad_yy_mbist_mode,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
sync_sys_apb_rst_b,
sys_apb_clk,
sys_apb_rst_b
);
// &Ports; @23
input forever_cpuclk;
input pa... | 6.814271 |
module aq_prio (
clk,
rst_b,
valid,
clr,
sel
);
parameter NUM = 2;
input clk;
input rst_b;
input [NUM-1:0] valid;
input clr;
output [NUM-1:0] sel;
reg [NUM-1:0] prio [NUM-1:0];
reg [NUM-1:0] unused [NUM-1:0];
wire [NUM-1:0] sel;
wire [NUM-1:0] clr_bus;
assign clr_b... | 6.5303 |
module aq_ram19x11 (
input CLKA,
input WEA,
input [10:0] ADDRA,
input [18:0] DINA,
input CLKB,
input [10:0] ADDRB,
output [18:0] DOUTB
);
reg [18:0] array[0:2048];
always @(posedge CLKA) begin
if (WEA) begin
array[ADDRA[10:0]] = DINA[18:0];
end
end
reg [18:0] data;
... | 6.733145 |
module aq_ram25x16 (
input CLKA,
input WEA,
input [15:0] ADDRA,
input [24:0] DINA,
input CLKB,
input [15:0] ADDRB,
output [24:0] DOUTB
);
reg [24:0] array[0:2048];
always @(posedge CLKA) begin
if (WEA) begin
array[ADDRA[10:0]] = DINA[24:0];
end
end
reg [24:0] data;
... | 7.737306 |
module aq_rtu_int (
cp0_rtu_int_vld,
dp_int_ex2_inst_split,
dtu_rtu_int_mask,
int_retire_int_vec,
int_retire_int_vld
);
// &Ports; @25
input [14:0] cp0_rtu_int_vld;
input dp_int_ex2_inst_split;
input dtu_rtu_int_mask;
output [4 : 0] int_retire_int_vec;
output int_retire_int_vld;
// ... | 7.774232 |
module aq_serdes_n_to_1 (
input ioclk,
input gclk,
input reset,
input [9:0] datain,
output iob_data_out
);
wire cascade_di;
wire cascade_ti;
wire cascade_do;
wire cascade_to;
reg toggle;
reg [4:0] datain_d;
reg rst_inst;
always @(posedge gclk or posedge... | 7.158293 |
module aq_sigcap (
// --------------------------------------------------
// AXI4 Lite Interface
// --------------------------------------------------
// Reset, Clock
input S_AXI_ARESETN,
input S_AXI_ACLK,
// Write Address Channel
input [15:0] S_AXI_AWADDR,
input [ 3:0] S_AXI_AWCAC... | 6.886592 |
module aq_spsram_1024x16 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [15:0] D;
input GWEN;
input [15:0] WEN;
output [15:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.605262 |
module aq_spsram_1024x64 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [9 : 0] A;
input CEN;
input CLK;
input [63:0] D;
input GWEN;
input [63:0] WEN;
output [63:0] Q;
// &Regs; @24
// &Wires; @25
wire [9 : 0] A;
wire CEN;
wire CLK;
wire... | 7.605262 |
module aq_spsram_128x8 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [6:0] A;
input CEN;
input CLK;
input [7:0] D;
input GWEN;
input [7:0] WEN;
output [7:0] Q;
// &Regs; @24
// &Wires; @25
wire [6:0] A;
wire CEN;
wire CLK;
wire [7:0] D;
w... | 8.40252 |
module aq_spsram_2048x32 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [10:0] A;
input CEN;
input CLK;
input [31:0] D;
input GWEN;
input [31:0] WEN;
output [31:0] Q;
// &Regs; @24
// &Wires; @25
wire [10:0] A;
wire CEN;
wire CLK;
wire [31... | 8.19862 |
module aq_spsram_256x59 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [7 : 0] A;
input CEN;
input CLK;
input [58:0] D;
input GWEN;
input [58:0] WEN;
output [58:0] Q;
// &Regs; @24
// &Wires; @25
wire [7 : 0] A;
wire CEN;
wire CLK;
wire ... | 7.115472 |
module aq_spsram_64x58 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [57:0] D;
input GWEN;
input [57:0] WEN;
output [57:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [... | 7.947531 |
module aq_spsram_64x88 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [87:0] D;
input GWEN;
input [87:0] WEN;
output [87:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [... | 7.947531 |
module aq_spsram_64x98 (
A,
CEN,
CLK,
D,
GWEN,
Q,
WEN
);
// &Ports; @23
input [5 : 0] A;
input CEN;
input CLK;
input [97:0] D;
input GWEN;
input [97:0] WEN;
output [97:0] Q;
// &Regs; @24
// &Wires; @25
wire [5 : 0] A;
wire CEN;
wire CLK;
wire [... | 7.947531 |
module aq_vdsp_8_bit_ff1 (
out,
rem,
src,
zero
);
// &Ports; @18
input [7:0] src;
output [4:0] out;
output rem;
output zero;
// &Regs; @19
reg rem_1;
reg [4:0] result;
// &Wires; @20
wire [4:0] out;
wire rem;
wire [7:0] src;
wire zero;
// &CombBeg; @2... | 7.782013 |
module aq_vlsu_rot_data (
data_in,
data_out,
rot_sel
);
// &Ports; @24
input [63:0] data_in;
input [7 : 0] rot_sel;
output [63:0] data_out;
// &Regs; @25
reg [ 63:0] data_settle;
// &Wires; @26
wire [ 63:0] data;
wire [ 63:0] data_in;
wire [ 63:0] data_out;
wire [ 63:0] data_rot0;
... | 6.820042 |
module aq_zybo_vga (
input RST_N,
input CLK,
input [31:0] DIN,
input ACTIVE,
input HIN,
input VIN,
output HSYNC,
output VSYNC,
output [4:0] DOUT_R,
output [5:0] DOUT_G,
output [4:0] DOUT_B
);
reg HSYNC;
reg VSYNC;
reg [4:0] DOUT_R;
reg [5:0] DOUT_G;
reg [4:0] DOU... | 6.880747 |
module ar (
din,
clk,
rst,
arload,
arinc,
dout
);
input [15:0] din;
input clk, rst, arload, arinc;
output [15:0] dout;
reg [15:0] dout;
always @(posedge clk or negedge rst)
if (!rst) dout <= 0;
else if (arload) dout <= din;
else if (arinc) dout <= dout + 1;
endmodule
| 6.957779 |
module aram8x16 (
input wr_in,
rd_in,
input [2:0] addr_in,
addr_out,
input [15:0] data_wr,
output [15:0] data_rd
);
reg [ 7:0] out;
reg [15:0] mem [7:0];
always @(*) begin
if (wr_in) mem[addr_in] = data_wr;
if (rd_in) out = (rd_in) ? mem[addr_out] : 16'hzz;
end
assign data_rd... | 8.522772 |
module ArbDynamicPriority (
clk,
rst_n,
req,
priorityLevel,
grant
);
parameter REQ_NUM = 4;
parameter PRI_WIDTH = clog2(REQ_NUM);
parameter PRI_TOTALW = REQ_NUM * PRI_WIDTH;
//
input clk;
input rst_n;
input [REQ_NUM-1:0] req;
input [PRI_TOTALW-1:0] priorityLevel;
output reg [REQ_NU... | 7.747255 |
module arbel (
input X,
input Y,
input C,
output W,
output Z
);
wire W1, W2;
wire Z1, Z2;
mux2x1 M1 (
X,
Y,
C,
W1
);
mux2x1 M2 (
Y,
X,
C,
Z1
);
not N1 (W2, W1);
not N2 (W, W2);
not N7 (Z2, Z1);
not N8 (Z, Z2);
endmodule
| 8.13877 |
module arbit (
input wire sclk,
input wire rst,
input wire rd_req,
input wire wr_req,
input wire rd_end,
input wire wr_end,
output wire rd_cmd_start,
output wire wr_cmd_start
);
parameter IDLE = 4'b0001;
parameter ARBIT = 4'b0010;
parameter WR = 4'b0100;
parameter RD = 4'b1... | 7.672948 |
module arbiter3 (
input wire clk,
input wire rst_n,
input wire [2:0] grant,
output wire [2:0] arbitration
);
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[2] = grant[2] & (~grant[1] | prio2_1) & (~grant[0] | prio2_0);
assign arbitration[1] = grant[1] & (~grant[2] | ~prio2_1... | 8.317171 |
module arbiter4 (
input wire clk,
input wire rst_n,
input wire [3:0] grant,
output wire [3:0] arbitration
);
reg prio3_2;
reg prio3_1;
reg prio3_0;
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[3] = grant[3]& (~grant[2] | prio3_2) &(~grant[1] | prio3_1)& (~grant[0] | prio... | 7.886769 |
module arbiter5 (
input wire clk,
input wire rst_n,
input wire [4:0] grant,
output wire [4:0] arbitration
);
reg prio4_3;
reg prio4_2;
reg prio4_1;
reg prio4_0;
reg prio3_2;
reg prio3_1;
reg prio3_0;
reg prio2_1;
reg prio2_0;
reg prio1_0;
assign arbitration[4] = grant[4]& (~gr... | 7.226772 |
module vc_FixedArbChain #(
parameter p_num_reqs = 2
) (
input logic kin, // kill in
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grants, // (one-hot) 1 indicates req won grant
output logic kout // kil... | 8.484232 |
module vc_VariableArbChain #(
parameter p_num_reqs = 2
) (
input logic kin, // kill in
input logic [p_num_reqs-1:0] priority_, // (one-hot) 1 is req w/ highest pri
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grant... | 7.922999 |
module vc_VariableArb #(
parameter p_num_reqs = 2
) (
input logic [p_num_reqs-1:0] priority_, // (one-hot) 1 is req w/ highest pri
input logic [p_num_reqs-1:0] reqs, // 1 = making a req, 0 = no req
output logic [p_num_reqs-1:0] grants // (one-hot) 1 is req won grant
);
logic dummy_kout;... | 7.922999 |
module arbiter_1m_2s #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
/* Master wishbone */
input [ADDR_WIDTH-1:0] m_addr_i,
input [DATA_WIDTH-1:0] m_data_i,
output [DATA_WIDTH-1:0] m_data_o,
input m_cyc_i,
input [ 3:0] m_sel_i,
input ... | 6.968401 |
module arbiter_tb ();
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
reg [2:0] pe_request_bundle;
reg [2:0] north_request_bundle;
reg [2:0] east_request_bundle;
// Configuration bundles are composed by:
... | 7.933876 |
module prior_arb #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] req,
output [WIDTH-1:0] gnt
);
wire [WIDTH-1:0] var;
assign var = req - 1'b1;
assign gnt = req & ~var;
endmodule
| 7.84627 |
module function:because there are three kinds of accesses to mem ,
/// we need to determine which will be allowed to access mem finally.
module arbiter_for_mem(//input
clk,
rst,
v_mem_download,
v_d_m_are... | 6.680089 |
module function:because there are two kinds of uploadregs to
/// OUT_rep: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_rep.
module arbiter_for_OUT_rep(//input
clk,
rst,
OUT_rep_rdy... | 6.680089 |
module arbiter_LRU4 (
grant_vector,
req_vector,
enable,
CLK,
RST
);
input [3:0] req_vector;
input CLK;
input RST;
input enable;
output [3:0] grant_vector;
reg [1:0] lru[3:0];
reg [3:0] grant_vector;
reg [3:0] grant_vector_1d;
reg [3:0] grant_vector_pre;
reg [1:0] equal_sloc;
r... | 7.01686 |
module tb ();
reg [3:0] req;
wire [3:0] grant;
reg RST;
reg enable;
reg CLK;
integer i;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST = 1;
enable = 0;
req = 4'b0;
//repeat(5) @(posedge CLK)
#4 RST = 0;
//@(posedge CLK)
enable = 1;
req =... | 7.002324 |
module arbiter #(
parameter NUM_PORTS = 6
) (
input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2 * NUM_POR... | 7.470414 |
module implements an arbiter, giving priority to the highest index
module arbiter_priority
#(
parameter NUM_ENTRIES = 8,
parameter NUM_ENTRIES_LOG = $clog2(NUM_ENTRIES)
)
(
// client side
input logic [NUM_ENTRIES-1:0] client_valid,
input logic [NUM_ENTRIES_LOG-1:0] top_client,
output lo... | 6.667836 |
module testbench;
logic a_req, b_req, reset, clock, a_res, b_res;
arbiter arb (
.a_req(a_req),
.b_req(b_req),
.reset(reset),
.clock(clock),
.a_res(a_res),
.b_res(b_res)
);
// Clock
always begin
#5;
clock = ~clock;
end
initial begin
$monitor("Time:%4.0f ... | 7.015571 |
module testbench_rx ();
localparam DURATION = 500; // duration of simulation (time units)
initial begin
#DURATION $finish;
end
wire clk, reset;
generator u1 (
clk,
reset
);
wire [4:0] reqs_in;
wire [4:0] acks_in;
wire [2:0] selected;
wire [7:0] datas_in [4:0];
localparam P ... | 6.984192 |
module arbiter_top (
PCLK,
PRESETn,
PADDR,
PWRITE,
PSEL,
PENABLE,
PWDATA,
PRDATA,
PREADY,
APB_BYPASS,
APB_REQ,
APB_ARB_TYPE,
REQ,
GNT
);
// APB interface
input PCLK;
input PRESETn;
input PWRITE;
input PSEL;
input PENABLE;
input [7:0] PADDR;
input ... | 8.392315 |
module arbiter_URAM #(
parameter NUM_WR = 8,
parameter NUM_MUL = 4,
parameter DATA_WIDTH = 64,
parameter KEY_WIDTH = 32
) (
input [NUM_MUL*NUM_WR*DATA_WIDTH-1:0] rd_BRAM_out,
input [KEY_WIDTH-1:0] key_rd,
input [NUM_MUL-1:0] opt_rd,
output [NUM_MUL-1:0] arbiter_result
);
//key_rd, the ... | 7.974177 |
module arb_counter (
out,
count,
init,
set,
reset,
clk
);
input set, reset, clk;
input [3:0] init;
output [3:0] count;
output out;
reg [3:0] count;
reg out;
always @(negedge clk or negedge set or negedge reset) begin
if (!set) begin
count = init;
out = 0;
end... | 6.64194 |
module arb_counter_tb;
reg set, reset, clk;
reg [3:0] init;
wire [3:0] count;
wire out;
reg [3:0] count_p, count_c;
reg out_p, out_c;
arb_counter SA (
out,
count,
init,
set,
reset,
clk
);
parameter STDIN = 32'h8000_0000;
integer testid;
integer ret;
initial... | 6.554006 |
module is used to pick which component gets to output to the val/rdy SPI wrapper if multiple components can send a valid message.
// The arbitrator puts an address header on the outgoing packet so that downstream components can tell which component sent the response
// The nbits parameter is the length of the message.
... | 9.583561 |
module arbitrator_2_masters (
clk,
rst,
//master ports
m0_we_i,
m0_cyc_i,
m0_stb_i,
m0_sel_i,
m0_ack_o,
m0_dat_i,
m0_dat_o,
m0_adr_i,
m0_int_o,
m1_we_i,
m1_cyc_i,
m1_stb_i,
m1_sel_i,
m1_ack_o,
m1_dat_i,
m1_dat_o,
m1_adr_i,
m1_int_o,
... | 8.041478 |
module arbitrer_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
g1,
g2,
// Inputs
r1,
r2,
d1,
d2,
rstn
);
input r1;
output a1;
input r2;
output a2;
output g1;
input d1;
output g2;
input d2;
input rstn;
wire mutex_r1, mutex_r2;
wire toogle_in1, toggle_in2;... | 6.736451 |
module arbitrer_r1_2ph ( /*AUTOARG*/
// Outputs
a1,
a2,
g1,
g2,
// Inputs
r1,
r2,
d1,
d2,
rstn
);
input r1;
output a1;
input r2;
output a2;
output g1;
input d1;
output g2;
input d2;
input rstn;
wire mutex_r1, mutex_r2;
wire latch_en1, latch_en2;
... | 6.736451 |
module arbitro (
input clk,
input almost_full0,
input almost_full1,
input almost_full2,
input almost_full3,
input [3:0] state,
input empty0_naranja,
input empty1_naranja,
input empty2_naranja,
input empty3_naranja,
input empty0_morado,
input empty1_morado,
input empty... | 6.71338 |
module arbitro2 #(
// Tamaño de cada celda de memoria, [11:10] clase [9:8] destino [7:0] datos
parameter WORD_SIZE = 12
) (
input clk,
input reset,
input [WORD_SIZE-1:0] data_in_arb,
input fifo_empty,
input [3:0] fifos_almost_full,
output reg [WORD_SIZE-1:0] data_out_arb,
output reg po... | 7.13765 |
module arbitro_demux (
input [5:0] mux_arbitro_1,
input reset_L,
destiny,
output reg [5:0] D0_out,
D1_out
);
always @(*) begin
if (~reset_L) begin
D0_out = 0;
D1_out = 0;
end else begin
if (destiny == 0) D0_out = mux_arbitro_1;
else if (destiny == 1) D1_out = mux_a... | 6.72883 |
module logica_pops_synth (
VC0_empty,
VC1_empty,
D0_pause,
D1_pause,
clk,
reset_L,
VC0_pop_synth,
VC1_pop_synth,
pop_delay_VC0,
pop_delay_VC1
);
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
wire _00_;
(* src = "./arbitro_mux_synthes/logica_pops_synth.v:4" *)
... | 6.842325 |
module arbitro_mux (
input reset_L,
clk,
input [5:0] VC0,
input [5:0] VC1,
input pop_delay_VC0,
pop_delay_VC1,
input VC0_empty,
VC1_empty,
output reg [5:0] arbitro_D0_out,
arbitro_D1_out,
output reg D0_push,
D1_push
);
always @(posedge clk) begin
if (~reset_L) begi... | 6.514522 |
module ArbPriorityRR (
clk,
rst_n,
req,
grant
);
parameter REQ_NUM = 4;
parameter COUNTER_W = clog2(REQ_NUM);
//
input clk;
input rst_n;
input [REQ_NUM-1:0] req;
output reg [REQ_NUM-1:0] grant;
//
reg [COUNTER_W-1:0] rrCounter;
wire incCounter;
wire [REQ_NUM-1:0] prioritySel;
wir... | 6.772825 |
module priorityLogic (
Sel,
reqIn,
reqOut
);
parameter REQ_NUM = 2;
//
input Sel;
input [REQ_NUM-1:0] reqIn;
output wire [REQ_NUM-1:0] reqOut;
//
assign reqOut[0] = Sel ? reqIn[0] : 1'b0;
generate
genvar k;
for (k = 1; k < REQ_NUM; k = k + 1) begin : uPLogic
assign reqOut[k] = ... | 6.502438 |
module arb_decoder (
bus_addr,
rd_wr_in,
rd_wr_out,
en,
dma_en,
mem_en,
io_en
);
parameter DMA_FRAME = 20'h00001;
parameter DISK_FRAME = 20'h00003;
parameter BUSADDRW = 32;
input [BUSADDRW-1:0] bus_addr;
input rd_wr_in;
output rd_wr_out;
input en;
output dma_en;
output ... | 7.007837 |
module arb_pattern_type_muxes (
Arb_WhichPort, // I [C_ARB_PORT_ENCODING_WIDTH-1:0]
PI_ArbPatternType_I, // I [C_NUM_PORTS*C_ARB_PATTERN_TYPE_WIDTH-1:0]
PI_ArbPatternType_O // O [C_ARB_PATTERN_TYPE_WIDTH-1:0]
);
parameter C_NUM_PORTS = 8; // Allowed Values: 1-8
parameter C_ARB_PORT_ENCODING_WIDTH =... | 7.374951 |
module forms the qualification engine for a single master as
// part of a larger arbitration engine for a slave. It would typically
// be instantiated from arb_select_master.v to form a complete arbitor solution.
//
module arb_qualify_master
#(
parameter WIDTH=16 // Bit width of destination field.
)
( ... | 8.218298 |
module arb_req_pending_muxes (
Arb_ReqPending, // I [C_NUM_PORTS-1:0]
Arb_PortNum, // I [C_ARB_PORT_ENCODING_WIDTH-1:0]
Arb_PatternEnable // O
);
parameter C_NUM_PORTS = 8; // Allowed Values: 1-8
parameter C_ARB_PORT_ENCODING_WIDTH = 3; // Allowed Values: 1-3
input [C_NUM_PORTS-1:0] Arb_ReqPen... | 6.856042 |
module implements an high speed round robin arbiter
module arb_rr #(parameter NUM_REQS=4) (
input logic clock,
input logic reset,
output logic [NUM_REQS-1:0] grants,
input logic pop,
input logic [NUM_REQS-1:0] reqs
);
logic [NUM_... | 6.667836 |
module arb_test ();
reg clk, reset_n, wreq, fifo_full;
reg [7:0] memadrs, memdata;
wire [7:0] synth_ctrl, synth_data;
reg [7:0] test_state;
reg [7:0] wait_cnt;
synth_arb arb1 (
.clk(clk),
.reset_n(reset_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wreq),
.synth_ctrl... | 6.90103 |
module arb_v (
reset,
clk,
dma_breq,
dma_grant,
tdsp_breq,
tdsp_grant
);
input reset, clk, dma_breq, tdsp_breq;
output reg dma_grant, tdsp_grant;
// include state encodings defined in arb.h
`include "arb.h"
// STATE REGISTERS
reg [2:0] state; // current state
reg [2:0] next_s... | 8.59133 |
module arb_wavegen #(
parameter OUTPUT_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire enable_pulse, // Acts as a clock divider
input wire [11:0] step, // Acts as a clock multiplier
input wire [11:0] range,
input wire [11:0] wr_addr,
input wire [OUTPUT_WIDTH-1:0] wr_data,
... | 7.314566 |
module control_rotator (
input [3:0] joystick, //UDLR
input [3:0] keyboard,
input rotate,
input [1:0] orientation,
output [3:0] out
);
assign out = {m_up, m_down, m_left, m_right};
wire m_up = ~(orientation[0] ^ rotate) ? keyboard[3] | joystick[3] : ((orientation[1] ^ orienta... | 8.033793 |
module input_toggle (
input clk,
input reset,
input btn,
output reg state
);
reg btn_old;
always @(posedge clk) begin
btn_old <= btn;
if (reset) state <= 0;
else if (~btn_old & btn) state <= ~state;
end
endmodule
| 7.20813 |
module arcade_video #(
parameter WIDTH = 320,
DW = 8,
GAMMA = 1
) (
input clk_video,
input ce_pix,
input [DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output CLK_VIDEO,
output CE_PIXEL,
output ... | 6.828318 |
module screen_rotate (
input CLK_VIDEO,
input CE_PIXEL,
input [7:0] VGA_R,
input [7:0] VGA_G,
input [7:0] VGA_B,
input VGA_HS,
input VGA_VS,
input VGA_DE,
input rotate_ccw,
input no_rotate,
input flip,
output video_rotated,
output FB... | 7.258265 |
module arcade_wrapper (
input _2LFT,
input _2S3,
input _2DN,
input _2S2,
input _2UP,
input _2S1,
input _START,
input _2RGT,
input _1LFT,
input _1S3,
input _1DN,
input _1S2,
input _1UP,
input _1S1,
input _START1,
input _1RGT
//input sw[7:0], //select s... | 6.97422 |
module Arch_Map (
input logic en, clock, reset,
input logic [`NUM_SUPER-1:0] retire_en, // retire signal from ROB
`ifndef DEBUG
input ROB_ARCH_MAP_OUT_t ROB_Arch_Map_out
`else
input ROB_ARCH_MAP_OUT_t ... | 6.856361 |
modules
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: MIT
// Copyright (c) 2021 Dmitry Matyunin
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal... | 6.704136 |
module arch_fifo_axis #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter CLOCK_MODE = "ASYNC",
parameter FIFO_PACKET = 0,
parameter FIFO_DEPTH = 1024,
parameter DATA_WIDTH = 8,
parameter PROG_FULL_THRESHOLD = 64
) (
input wire s_aclk,
input wire s_arese... | 6.916777 |
module arch_fifo_async #(
parameter FPGA_VENDOR = "xilinx",
parameter FPGA_FAMILY = "7series",
parameter RD_DATA_WIDTH = 8,
parameter WR_DATA_WIDTH = 8
) (
output wire [RD_DATA_WIDTH-1:0] dout,
output wire empty,
output wire full,
output wire rd_rst_busy,
output wire wr_rst_busy,... | 6.526387 |
module arduino_adc (
adc_ltc2308_conduit_end_CONVST,
adc_ltc2308_conduit_end_SCK,
adc_ltc2308_conduit_end_SDI,
adc_ltc2308_conduit_end_SDO,
clk_clk,
motor_export,
pll_sys_locked_export,
reset_reset_n,
uart_rxd,
uart_txd
);
output adc_ltc2308_conduit_end_CONVST;
output adc_lt... | 6.595463 |
module arduino_adc_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 7.019349 |
module arduino_adc_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear... | 7.019349 |
module arduino_adc_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg ... | 7.019349 |
module arduino_adc_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
in... | 7.019349 |
module arduino_adc_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "arduino_adc_onchip_memory2.hex";
output [31:0] readdata;
input [15:0] addre... | 7.108928 |
module arduino_adc_pll_sys (
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional... | 6.506893 |
module arduino_adc_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input wr... | 7.41614 |
module arduino_adc_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1568128486 : 35;
endmodul... | 7.41614 |
module arduino_shield (
input wire UART,
input wire I2C,
input wire SPI,
inout wire [15:0] SH_IO,
output wire I2C_OE
);
wire [15:0] gpio;
wire uart_rx;
wire uart_tx;
wire i2c_scl;
wire i2c_sda;
wire i2c_scl_int;
wire i2c_sda_int;
wire i2c_oe_int;
... | 6.848058 |
module area_1 (
input pixelclk,
input rst_n,
input en,
input i_binary,
input i_hs,
input i_vs,
input i_de,
//input [23:0] i_rgb_1,
//
//output [23:0] o_rgb_1_6,
output wire hs_r,
output wire vs_r,
output w... | 7.014839 |
module area_BMR #(
parameter N = 8
) (
input [6*N-1:0] p_input, //A, B, C: 2*N
output o
);
wire signed [N-1:0] xA, yA, xB, yB, xC, yC;
assign xA = p_input[6*N-1:5*N];
assign yA = p_input[5*N-1:4*N];
assign xB = p_input[4*N-1:3*N];
assign yB = p_input[3*N-1:2*N];
assign xC = p_input[2*N-1:1*... | 6.953901 |
module area_cnt (
input pixelclk,
input reset_n,
input i_vsync_pos,
input wb,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output [11:0] area
);
reg [11:0] area_r... | 6.697345 |
module areg (
output reg DALtx,
// The QBUS signals as seen by the FPGA
inout [21:0] DAL, // bidirectional to save FPGA pins
input RDOUT,
output reg TDOUT,
input RRPLY,
output reg TRPLY,
input RDIN,
output reg TDIN,
input RSYNC,
output reg TSYNC,
input RIRQ4,
output... | 6.809406 |
module aregc01_3v3 ( OUT, VIN3, GNDO, EN, GNDR, VDDO, VDDR, VDD, ENB );
input VDD;
input VDDO;
input GNDO;
input VDDR;
input GNDR;
input EN;
output OUT;
input ENB;
input VIN3;
wire real VDDR;
reg real OUT;
wire EN;
real NaN;
initial begin
NaN = 0.0 / 0.0;
OUT <= 0.0;
end
al... | 6.547788 |
module aReg (
clk,
alu_dataOut_1,
aReg_out
);
input clk;
input [31:0] alu_dataOut_1;
output reg [31:0] aReg_out;
always @(posedge clk) begin
aReg_out <= alu_dataOut_1;
end
endmodule
| 6.864059 |
module select_vector (
input wire [`SPECTAG_LEN-1:0] spectag,
input wire [ `REG_NUM-1:0] dat0,
input wire [ `REG_NUM-1:0] dat1,
input wire [ `REG_NUM-1:0] dat2,
input wire [ `REG_NUM-1:0] dat3,
input wire [ `REG_NUM-1:0] dat4,
output reg [ `REG_NUM-1:0] out
);
alw... | 6.539981 |
module argmax_cell #(
parameter DATA_WIDTH = 8,
parameter RESULT_WIDTH = 16,
parameter INDEX_WIDTH = 10,
parameter CELL_AMOUNT = 4
) (
input wire clk,
input wire [INDEX_WIDTH-1:0] input_index,
input wire [DATA_WIDTH-1:0] input_value,
input wire input_enable,
output reg [RESULT_WI... | 6.610927 |
module.
//////////////////////////////////////////////////////////////////////////////////
module argmax_simulator();
event error;
always @ (error) begin
$display("ERROR at time %t", $time);
#`CLOCK $stop;
end
task check_output(input [`DATA_WIDTH*2:0] result, input [`DATA_WIDTH*2:0] go... | 6.641851 |
module returns a one hot vector where the high bit corresponds to
the location of the minimum number in the input vector
Note that there is only clk, reset, and enable for control signals.
This module is to be used in parallel with pipeline train.
This module always takes ceil(log2(BLOCKLENGTH)) time steps.
This is r... | 7.878483 |
module am2 #(
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
reg... | 6.990385 |
module am3 #(
parameter BLOCKLENGTH = 3,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
//f... | 6.762173 |
module am4 #(
parameter BLOCKLENGTH = 4,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output [0:BLOCKLENGTH-1] arg
);
wire [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, in, data_in)
//f... | 6.918724 |
module argmin_helper #(
parameter WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter NUM_INP = 2,
parameter NUM_OUTP = 1,
parameter STAGE = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH*NUM_INP-1:0] inp,
input wire [ADDR_WIDTH*NUM_INP-1:0] inp_addr,
output wire [WIDTH*NUM... | 8.658206 |
module argmin_stage #(
parameter WIDTH = 1,
parameter ADDR_WIDTH = 1,
parameter STAGE = 1
) (
input wire clk,
input wire rst,
input wire [WIDTH-1:0] left_val,
// One bit of the address input will go unused
/* verilator lint_off UNUSED */
input wire [ADDR_WIDTH-1:0] left_addr,
/*... | 8.183015 |
module argmin_test (
input clk,
input rst,
input wire [10*32-1:0] inp,
output wire [31:0] outp,
output wire [3:0] outp_addr
);
argmin_10 #(
.WIDTH(32)
) am (
clk,
rst,
inp,
outp,
outp_addr
);
endmodule
| 6.698899 |
module argmax_tb();
reg clk;
reg signed [{{i_bits - 1}}:0] xi;
reg signed [{{q_bits - 1}}:0] xq;
integer arg_max_input;
reg m_axis_tvalid;
wire s_axis_tready;
reg m_axis_tready;
wire [{{ out_max_bi... | 6.614633 |
module fifo_v2_DEPTH8 (
clk_i,
rst_ni,
flush_i,
testmode_i,
full_o,
empty_o,
alm_full_o,
alm_empty_o,
data_i,
push_i,
data_o,
pop_i
);
input [166:0] data_i;
output [166:0] data_o;
input clk_i;
input rst_ni;
input flush_i;
input testmode_i;
input push_i;
i... | 7.120907 |
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