code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module XNOR2xp5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (B__bar, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B__bar);
and (int_fwire_1, A, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (B) (A => Y) = 0;
if (~B) (A => Y) = 0;
if (A) (B => Y) = 0;
if (~A) (B => Y) = 0;
endspecify
endmodule
| 7.501645 |
module XOR2x1_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (A__bar, A);
and (int_fwire_0, A__bar, B);
not (B__bar, B);
and (int_fwire_1, A, B__bar);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (~B) (A => Y) = 0;
if (B) (A => Y) = 0;
if (~A) (B => Y) = 0;
if (A) (B => Y) = 0;
endspecify
endmodule
| 7.745016 |
module XOR2x2_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (A__bar, A);
and (int_fwire_0, A__bar, B);
not (B__bar, B);
and (int_fwire_1, A, B__bar);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (~B) (A => Y) = 0;
if (B) (A => Y) = 0;
if (~A) (B => Y) = 0;
if (A) (B => Y) = 0;
endspecify
endmodule
| 7.871675 |
module XOR2xp5_ASAP7_75t_R (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
not (A__bar, A);
and (int_fwire_0, A__bar, B);
not (B__bar, B);
and (int_fwire_1, A, B__bar);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
if (~B) (A => Y) = 0;
if (B) (A => Y) = 0;
if (~A) (B => Y) = 0;
if (A) (B => Y) = 0;
endspecify
endmodule
| 7.586169 |
module asc16x8 (
input wire clk,
input wire [10:0] bitmap_addr,
output wire [ 7:0] bitmap_byte
);
`ifdef SIM
reg [7:0] bitmap_reg [0 : 2047];
reg bitmap_byte_r;
assign bitmap_byte = bitmap_byte_r;
initial begin
$readmemh("../rtl/asc16x8.mem", bitmap_reg, 0, 2047);
end
always @(posedge clk) begin
bitmap_byte_r <= bitmap_reg[bitmap_addr];
end
`else
asc16X8_xilinx asc16X8_xilinx_inst (
.clka (clk), // input clka
.addra(bitmap_addr), // input [10 : 0] addra
.douta(bitmap_byte) // output [7 : 0] douta
);
`endif
endmodule
| 7.16411 |
module ASCII (
input [7:0] ivData,
input iCE,
input iClk,
input iReset,
output [6:0] ovDisplay
);
reg [6:0] rvDisplay_Q;
reg [6:0] rvDisplay_D;
assign ovDisplay = rvDisplay_Q;
always @(posedge iClk) begin
if (iReset) begin
rvDisplay_Q <= 7'b0111111;
end else begin
if (iCE) begin
rvDisplay_Q <= rvDisplay_D;
end else begin
rvDisplay_Q <= rvDisplay_Q;
end
end
end
always @* begin
case (ivData)
8'd65: rvDisplay_D = 7'b0001000; //a
8'd66: rvDisplay_D = 7'b0000000; //b
8'd67: rvDisplay_D = 7'b1000110; //c
8'd68: rvDisplay_D = 7'b1000000; //d
8'd69: rvDisplay_D = 7'b0000110; //e
8'd70: rvDisplay_D = 7'b0001110; //f
8'd71: rvDisplay_D = 7'b1000010; //g
8'd72: rvDisplay_D = 7'b0001001; //h
8'd73: rvDisplay_D = 7'b1111001; //i
8'd74: rvDisplay_D = 7'b1100001; //j
8'd75: rvDisplay_D = 7'b0001001; //k
8'd76: rvDisplay_D = 7'b1000111; //l
8'd77: rvDisplay_D = 7'b0101011; //m
8'd78: rvDisplay_D = 7'b0101011; //n
8'd79: rvDisplay_D = 7'b0100011; //o
8'd80: rvDisplay_D = 7'b0001100; //p
8'd81: rvDisplay_D = 7'b0011000; //q
8'd82: rvDisplay_D = 7'b0101111; //r
8'd83: rvDisplay_D = 7'b0010010; //s
8'd84: rvDisplay_D = 7'b0111001; //t
8'd85: rvDisplay_D = 7'b1100011; //u
8'd86: rvDisplay_D = 7'b1100011; //v
8'd87: rvDisplay_D = 7'b1100011; //w
8'd88: rvDisplay_D = 7'b0111001; //x
8'd89: rvDisplay_D = 7'b0011001; //y
8'd90: rvDisplay_D = 7'b0100100; //z
default: rvDisplay_D = 7'b0111111;
endcase
end
endmodule
| 7.45935 |
module ascii2dec (
input clk,
input rst,
input [7:0] a_in,
output reg [7:0] out
);
always @(posedge clk or posedge rst) begin
if (rst) out <= 8'h00;
else begin
case (a_in)
8'h30: out <= 8'h00;
8'h31: out <= 8'h01;
8'h32: out <= 8'h02;
8'h33: out <= 8'h03;
8'h34: out <= 8'h04;
8'h35: out <= 8'h05;
8'h36: out <= 8'h06;
8'h37: out <= 8'h07;
8'h38: out <= 8'h08;
8'h39: out <= 8'h09;
8'h61: out <= 8'h0a;
8'h62: out <= 8'h0b;
8'h63: out <= 8'h0c;
8'h64: out <= 8'h0d;
8'h65: out <= 8'h0e;
8'h66: out <= 8'h0f;
default: out <= 8'hZZ;
endcase
end
end
endmodule
| 6.712574 |
module asciiHex2Bin (
output reg [3:0] val,
input [7:0] inVal
);
always @(*) begin
casex (inVal)
8'h61: val = 4'ha;
8'h62: val = 4'hb;
8'h63: val = 4'hc;
8'h64: val = 4'hd;
8'h65: val = 4'he;
8'h66: val = 4'hf;
default: val = inVal[3:0];
endcase // casex (inVal)
end // always @ (*)
endmodule
| 7.574772 |
module ascii_alu (
input clk,
input [7:0] a,
input [7:0] b,
input [10:0] op_code,
input reset,
input go,
//output reg [7:0] out,
output reg [39:0] display,
output [2:0] rgb1,
output [2:0] rgb2,
output wire horizSyncOut,
output wire vertSyncOut,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B
);
wire [39:0] display_EBT, display_GRT, display_SWT, display_RGB;
assign display_RGB = {
5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111
};
assign display_VGA = {
5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111, 5'b11111
};
eight_bit_top EBT (
.a(a),
.b(b),
.op_code(op_code),
.display(display_EBT)
);
greetings_top GRT (
.clk(clk),
.a(a),
.op_code(op_code),
.display(display_GRT)
);
stopwatch_top SWT (
.clk(clk),
.reset(reset),
.go(go),
.op_code(op_code),
.display(display_SWT)
);
RGB_show_top RGBT (
.clk(clk),
.op_code(op_code),
.rgb1(rgb1),
.rgb2(rgb2)
);
vga_show_top VGAT (
.clk(clk),
.op_code(op_code),
.a(a),
.reset(reset),
.horizSyncOut(horizSyncOut),
.vertSyncOut(vertSyncOut),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
always @(posedge clk) begin
case (op_code)
11'b00000000001: display = display_EBT;
11'b00000000010: display = display_EBT;
11'b00000000100: display = display_EBT;
11'b00000001000: display = display_EBT;
11'b00000010000: display = display_RGB;
11'b00000100000: display = display_GRT;
11'b00001000000: display = display_SWT;
11'b00010000000: display = display_VGA;
default:
display = {5'b11111, 5'b11111, 5'b01011, 5'b01010, 5'b01101, 5'b11111, 5'b11111, 5'b11111};
endcase
end
endmodule
| 7.835936 |
module ascii_alu_testbench;
reg clk;
reg [7:0] a;
reg [7:0] b;
reg [10:0] op_code;
reg reset;
reg go;
//output reg [7:0] out,
wire [39:0] display_alu;
wire [2:0] rgb1;
wire [2:0] rgb2;
wire horizSyncOut;
wire vertSyncOut;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
ascii_alu ASA (
.clk(clk),
.a(a),
.b(b),
.go(go),
.reset(reset),
.op_code(op_code),
.display(display_alu),
.rgb1(rgb1),
.rgb2(rgb2),
.horizSyncOut(horizSyncOut),
.vertSyncOut(vertSyncOut),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
initial begin
a = 0;
b = 0;
op_code = 0;
clk = 0;
#10 reset = 1;
#10 reset = 0;
#300 op_code = 11'b00010000000;
#400 a = 2;
end
always #2 clk = ~clk;
endmodule
| 6.591844 |
module ascii_control (
clk,
rst,
pi_data,
pi_sig,
data_dis
);
input clk, rst;
input pi_sig;
input [7:0] pi_data;
output reg [19:0] data_dis;
reg [3:0] cnt_num;
reg [15:0] data_reg;
reg clear_sig;
reg data_en;
reg [3:0] data_trans;
reg [3:0] data_num;
reg [19:0] data_sum;
reg [3:0] state;
reg sum_out_sig;
//clear_sig
always @(posedge clk or posedge rst)
if (rst) clear_sig <= 1'b0;
else if (data_en == 1'b1) clear_sig <= 1'b1;
else clear_sig <= 1'b0;
always @(posedge clk or posedge rst)
if (rst) data_en <= 1'b0;
else if (pi_sig == 1'b1) data_en <= 1'b1;
else data_en <= 1'b0;
//data_reg
always @(posedge clk or posedge rst)
if (rst) data_reg <= 8'd0;
else if (pi_sig == 1'b1) data_reg <= pi_data;
else data_reg <= data_reg;
//data_num
always @(posedge clk or posedge rst)
if (rst) data_num <= 4'd0;
else if (clear_sig == 1'b1 && data_num == 4'd7) data_num <= 4'd0;
else if (pi_sig == 1'b1) data_num <= data_num + 1'b1;
//data_trans
always @(posedge clk or posedge rst)
if (rst) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd0) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd4) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd5) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd6) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd7) data_trans <= 4'd0;
else if (data_en == 1'b1 && data_num == 4'd1) data_trans <= pi_data[3:0];
else if (data_en == 1'b1 && data_num == 4'd2) data_trans <= pi_data[3:0];
else if (data_en == 1'b1 && data_num == 4'd3) data_trans <= pi_data[3:0];
//data_sum
always @(posedge clk or posedge rst)
if (rst) data_sum <= 20'd0;
else if (clear_sig == 1'b1 && data_num == 4'd1) data_sum <= data_trans * 20'd100;
else if (clear_sig == 1'b1 && data_num == 4'd2) data_sum <= data_sum + data_trans * 20'd10;
else if (clear_sig == 1'b1 && data_num == 4'd3) data_sum <= data_sum + data_trans * 20'd1;
else if (clear_sig == 1'b1 && data_num == 4'd5) data_sum <= 20'd0;
//sum_out_sig
always @(posedge clk or posedge rst)
if (rst) sum_out_sig <= 1'b0;
else if (data_num == 4'd4 && data_en == 1'b1) sum_out_sig <= 1'b1;
else sum_out_sig <= 1'b0;
//data_dis
always @(posedge clk or posedge rst)
if (rst) data_dis <= 20'd0;
else if (sum_out_sig == 1'b1) data_dis <= data_sum;
else data_dis <= data_dis;
endmodule
| 6.91175 |
module ascii_conv ( //converts the real data from kb module to ASCII
input [8:0] rd_data,
output reg [7:0] ascii
);
always @* begin
ascii = 0;
case (rd_data)
{1'b0, 8'h45} : ascii = 8'h30; //0
{1'b0, 8'h16} : ascii = 8'h31; //1
{1'b0, 8'h1e} : ascii = 8'h32; //2
{1'b0, 8'h26} : ascii = 8'h33; //3
{1'b0, 8'h25} : ascii = 8'h34; //4
{1'b0, 8'h2e} : ascii = 8'h35; //5
{1'b0, 8'h36} : ascii = 8'h36; //6
{1'b0, 8'h3d} : ascii = 8'h37; //7
{1'b0, 8'h3e} : ascii = 8'h38; //8
{1'b0, 8'h46} : ascii = 8'h39; //9
{1'b1, 8'h1c} : ascii = 8'h41; //A
{1'b1, 8'h32} : ascii = 8'h42; //B
{1'b1, 8'h21} : ascii = 8'h43; //C
{1'b1, 8'h23} : ascii = 8'h44; //D
{1'b1, 8'h24} : ascii = 8'h45; //E
{1'b1, 8'h2b} : ascii = 8'h46; //F
{1'b1, 8'h34} : ascii = 8'h47; //G
{1'b1, 8'h33} : ascii = 8'h48; //H
{1'b1, 8'h43} : ascii = 8'h49; //I
{1'b1, 8'h3b} : ascii = 8'h4a; //J
{1'b1, 8'h42} : ascii = 8'h4b; //K
{1'b1, 8'h4b} : ascii = 8'h4c; //L
{1'b1, 8'h3a} : ascii = 8'h4d; //M
{1'b1, 8'h31} : ascii = 8'h4e; //N
{1'b1, 8'h44} : ascii = 8'h4f; //O
{1'b1, 8'h4d} : ascii = 8'h50; //P
{1'b1, 8'h15} : ascii = 8'h51; //Q
{1'b1, 8'h2d} : ascii = 8'h52; //R
{1'b1, 8'h1b} : ascii = 8'h53; //S
{1'b1, 8'h2c} : ascii = 8'h54; //T
{1'b1, 8'h3c} : ascii = 8'h55; //U
{1'b1, 8'h2a} : ascii = 8'h56; //V
{1'b1, 8'h1d} : ascii = 8'h57; //W
{1'b1, 8'h22} : ascii = 8'h58; //X
{1'b1, 8'h35} : ascii = 8'h59; //Y
{1'b1, 8'h1a} : ascii = 8'h5a; //Z
{1'b0, 8'h1c} : ascii = 8'h61; //a
{1'b0, 8'h32} : ascii = 8'h62; //b
{1'b0, 8'h21} : ascii = 8'h63; //c
{1'b0, 8'h23} : ascii = 8'h64; //d
{1'b0, 8'h24} : ascii = 8'h65; //e
{1'b0, 8'h2b} : ascii = 8'h66; //f
{1'b0, 8'h34} : ascii = 8'h67; //g
{1'b0, 8'h33} : ascii = 8'h68; //h
{1'b0, 8'h43} : ascii = 8'h69; //i
{1'b0, 8'h3b} : ascii = 8'h6a; //j
{1'b0, 8'h42} : ascii = 8'h6b; //k
{1'b0, 8'h4b} : ascii = 8'h6c; //l
{1'b0, 8'h3a} : ascii = 8'h6d; //m
{1'b0, 8'h31} : ascii = 8'h6e; //n
{1'b0, 8'h44} : ascii = 8'h6f; //o
{1'b0, 8'h4d} : ascii = 8'h70; //p
{1'b0, 8'h15} : ascii = 8'h71; //q
{1'b0, 8'h2d} : ascii = 8'h72; //r
{1'b0, 8'h1b} : ascii = 8'h73; //s
{1'b0, 8'h2c} : ascii = 8'h74; //t
{1'b0, 8'h3c} : ascii = 8'h75; //u
{1'b0, 8'h2a} : ascii = 8'h76; //v
{1'b0, 8'h1d} : ascii = 8'h77; //w
{1'b0, 8'h22} : ascii = 8'h78; //x
{1'b0, 8'h35} : ascii = 8'h79; //y
{1'b0, 8'h1a} : ascii = 8'h7a; //z
{1'b0, 8'h0e} : ascii = 8'h60; // `
{1'b0, 8'h4e} : ascii = 8'h2d; // -
{1'b0, 8'h55} : ascii = 8'h3d; // =
{1'b0, 8'h54} : ascii = 8'h5b; // [
{1'b0, 8'h5b} : ascii = 8'h5d; // ]
{1'b0, 8'h5d} : ascii = 8'h5c; // \
{1'b0, 8'h4c} : ascii = 8'h3b; // ;
{1'b0, 8'h52} : ascii = 8'h27; // '
{1'b0, 8'h41} : ascii = 8'h2c; // ,
{1'b0, 8'h49} : ascii = 8'h2e; // .
{1'b0, 8'h4a} : ascii = 8'h2f; // /
{1'b0, 8'h29} : ascii = 8'h20; //space
{1'b0, 8'h5a} : ascii = 8'h0d; //enter
{1'b0, 8'h66} : ascii = 8'h08; //backspace
default: ascii = 8'h2a; //*
endcase
end
endmodule
| 7.434394 |
module ascii_input (
input clk25, // 25MHz clock
input rst, // active high reset
// I/O interface to keyboard
input key_clk, // clock input from keyboard / device
input ioctl_download,
input [ 7:0] textinput_dout,
input [15:0] textinput_addr,
// I/O interface to computer
input cs, // chip select, active high
input address, // =0 RX buffer, =1 RX status
output reg [7:0] dout, // 8-bit output bus.
output data_ready // 8-bit output bus.
);
wire new_clk;
Clock_divider_ascii #(4000) cdiv (
clk25,
new_clk
);
// save loaded data into ram
reg [15:0] ascii_last_byte = 16'b0;
reg [7:0] ascii_data[0:65535]; //65536
reg [15:0] text_byte = 16'b0;
reg in_dl = 1'b0;
assign data_ready = in_dl & !ioctl_download;
reg prev_ps2_clkdb; // previous clock state (in clk25 domain)
// keyboard translation signals
reg [7:0] ascii; // ASCII code of received character
reg ascii_rdy; // new ASCII character received
reg shift; // state of the shift key
reg [2:0] cur_state;
reg [2:0] next_state;
always @(posedge clk25 or posedge rst) begin
if (rst) begin
prev_ps2_clkdb <= 1'b0;
ascii_rdy <= 0;
ascii_last_byte = 16'b0;
end else begin
// and sample the state of the PS/2 data line
//if ((prev_ps2_clkdb == 1'b1) && (key_clk == 1'b0))
if ((prev_ps2_clkdb == 1'b1) && (new_clk == 1'b0)) begin
// check for negative edge of PS/2 clock
if (!ascii_rdy & data_ready & (text_byte <= ascii_last_byte)) begin
case (ascii_data[text_byte])
8'h0A: ascii = 8'h0D;
default: ascii = ascii_data[text_byte];
endcase
ascii_rdy <= 1;
$display("inside a %x text_byte %x ascii_last_byte %x", ascii, text_byte,
ascii_last_byte);
text_byte = text_byte + 16'b00000001;
end
end
// update previous clock state
prev_ps2_clkdb <= new_clk; //ps2_clkdb;
//prev_ps2_clkdb <= key_clk;//ps2_clkdb;
if (ioctl_download) begin
$display("ioctl_download: %x", textinput_addr);
ascii_data[textinput_addr] = textinput_dout;
ascii_last_byte = textinput_addr;
text_byte = 16'b0;
in_dl = 1'b1;
end else begin
// if (in_dl & text_byte>=(ascii_last_byte+1) & !ascii_rdy)
// if (in_dl & text_byte>(ascii_last_byte+1) & !ascii_rdy)
if (in_dl & text_byte > (ascii_last_byte)) begin
in_dl = 1'b0;
$display("indl %x", in_dl);
$display("ascii_rdy %x", ascii_rdy);
end
end
// handle I/O from CPU
if (cs == 1'b1) begin
if (address == 1'b0) begin
// RX buffer address
dout <= {1'b1, ascii[6:0]};
$display("put ascii %x in_dl %x text_byte %x ascii_last_byte %x ascii_rdy %x", ascii,
in_dl, text_byte, ascii_last_byte, ascii_rdy);
ascii_rdy <= 1'b0;
end else begin
// RX status register
dout <= {ascii_rdy, 7'b0};
end
end
end
end
endmodule
| 7.377676 |
module ascii_keyboard #(
parameter ROM_SIZE = 256,
parameter DIGI_NUM = 6
) (
// ps2_keyboard variables
input clk,
input clrn,
input ps2_clk,
input ps2_data,
// digi_encdr variables
output wire [7*DIGI_NUM-1:0] digi_output
);
wire [7:0] data;
wire [2:0] en_n;
wire ready, overflow, next_ctrl;
wire [23:0] result;
reg [ 2:0] hex = 3'b011;
nextdata_ctrl nctrl (
// input
.clk(clk),
.ready(ready),
// output
.next_ctrl(next_ctrl)
);
ps2_keyboard i1 (
// input
.clk(clk),
.clrn(clrn),
.nextdata_n(next_ctrl),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
// output
.ready(ready),
.overflow(overflow),
.data(data)
);
ascii_map amap (
// input
.clk(clk),
.ps2_data(data),
.nextdata_n(next_ctrl),
// output
.ascii_data(result[7:0]),
.last_code(result[15:8]),
.count(result[23:16])
);
digi_control dctrl (
// input
.clk(clk),
.ps2_data(data),
.nextdata_n(next_ctrl),
// output
.en_n(en_n)
);
genvar i;
generate
for (i = 0; i < 3; i = i + 1) begin : digi
digi_encdr dencdr (
// input
.en_n(en_n[i]),
.in_data(result[8*i+7 : 8*i]),
.hex(hex[i]),
// output
.digi(digi_output[14*i+13 : 14*i])
);
end
endgenerate
endmodule
| 7.575271 |
module ascii_map #(
parameter ROM_SIZE = 256,
parameter BREAK_CODE = 'hf0,
parameter CAPS_CODE = 'h58
) (
input clk,
input [7:0] ps2_data,
input nextdata_n,
output reg [7:0] ascii_data,
output reg [7:0] last_code,
output reg [7:0] count
);
// ROM Initialization
reg [7:0] lwr_rom[ROM_SIZE-1:0];
reg [7:0] caps_rom[ROM_SIZE-1:0];
integer i;
initial begin
for (i = 0; i < 256; i = i + 1) begin
lwr_rom[i] = 0;
caps_rom[i] = 0;
end
// $readmemh("D:/intelFPGA_lite/18.0/DESIGN/kbd/lwr_ascii.txt", lwr_rom, 0, ROM_SIZE-1);
// $readmemh("D:/intelFPGA_lite/18.0/DESIGN/kbd/caps_ascii.txt", caps_rom, 0, ROM_SIZE-1);
$readmemh("lwr_ascii.txt", lwr_rom, 0, ROM_SIZE - 1);
$readmemh("caps_ascii.txt", caps_rom, 0, ROM_SIZE - 1);
end
// Convert ps2 into ascii
reg break_mode, caps, caps_pressing;
initial begin
break_mode = 0;
caps = 0;
caps_pressing = 0;
end
always @(posedge clk) begin
if (!ps2_data) ascii_data <= ascii_data;
else if (break_mode) begin
ascii_data <= ascii_data; // nothing to do
if (ps2_data == CAPS_CODE && !nextdata_n) caps_pressing <= 0;
end else begin
if (ps2_data == CAPS_CODE) begin
if (!caps_pressing) begin
caps <= ~caps;
caps_pressing <= 1;
end
end else if (ps2_data != BREAK_CODE) begin
if (caps) ascii_data <= caps_rom[ps2_data];
else ascii_data <= lwr_rom[ps2_data];
end else ascii_data <= ascii_data;
end
if (ps2_data && !nextdata_n) break_mode <= (ps2_data == BREAK_CODE);
else break_mode <= break_mode;
end
// Record last available code
initial last_code = 0;
always @(posedge clk)
if (ps2_data) begin
if (ps2_data != BREAK_CODE) last_code <= ps2_data;
else last_code <= last_code;
end else last_code <= last_code;
// Total hits
reg [ROM_SIZE-1:0] counting_list;
reg count_break;
initial begin
counting_list = 0;
count = 0;
count_break = 0;
end
always @(posedge clk) begin
if (ps2_data) begin
if (counting_list[ps2_data]) begin
if (count_break && !nextdata_n) counting_list[ps2_data] <= 0;
count <= count;
end else if (ps2_data != BREAK_CODE) begin
if (count >= 99) count <= 0;
else count <= count + 1;
counting_list[ps2_data] <= 1;
end else count <= count;
end else count <= count;
if (ps2_data && !nextdata_n) count_break <= (ps2_data == BREAK_CODE);
else count_break <= count_break;
end
endmodule
| 6.680399 |
module ascii_ram (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [7:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.689672 |
module ASCII_to_7Seg ( // Just a test
clk,
rst,
ASCII,
Display
);
input clk, rst;
input [7:0] ASCII;
output [6:0] Display;
reg [6:0] Display;
always @(posedge clk or posedge rst) begin
if (rst) begin
Display <= 7'b1111110;
end else begin
if (ASCII == 8'h1C) Display <= 7'b0001000;
else Display <= 7'b0110000;
end
end
endmodule
| 7.124884 |
module ascii_to_binary (
input [7:0] ascii,
output reg [3:0] binary
);
always @(*) begin
case (ascii)
8'h30: binary <= 0;
8'h31: binary <= 1;
8'h32: binary <= 2;
8'h33: binary <= 3;
8'h34: binary <= 4;
8'h35: binary <= 5;
8'h36: binary <= 6;
8'h37: binary <= 7;
8'h38: binary <= 8;
8'h39: binary <= 9;
endcase
end
endmodule
| 6.529807 |
module ascii_to_bitmap #(
parameter FONT_ROM_FILENAME = "lib/pico8-hexadecimal.hex"
) (
input clk,
input [7:0] digit,
input [2:0] line,
output reg [3:0] bits
);
reg [3:0] font[0:2048];
initial $readmemh(FONT_ROM_FILENAME, font);
always @(posedge clk) bits <= font[{digit, line}];
endmodule
| 7.528499 |
module Ascon_FSM (
start,
clk,
reset,
in,
done,
out
);
input start, reset;
input clk;
input [320-1:0] in;
output reg done;
output [320-1:0] out;
reg state, next_state;
reg start_round, reset_round_cnt;
reg sel1, sel2, sel_cst;
reg [5:0] cycle_cnt, round_cnt;
// STATE DEFINITION
`define IDLE 0
`define COMPUTE 1
encrypt_spa ascon_spa (
clk,
sel1,
sel2,
sel_cst,
done,
in,
out
);
always @(*) begin
next_state = state;
done = 0;
sel1 = 0;
sel2 = 0;
sel_cst = 0;
start_round = 0;
reset_round_cnt = 0;
case (state)
`IDLE: begin
if (start) begin
next_state = `COMPUTE;
reset_round_cnt = 1;
sel1 = 1;
sel2 = 1;
end
end
`COMPUTE: begin
if (cycle_cnt == 0) begin
sel_cst = 1;
end
if (cycle_cnt == 3) begin
start_round = 1;
sel2 = 1;
end
if (cycle_cnt == 3 & round_cnt == 11) begin
done = 1;
next_state = `IDLE;
start_round = 1;
end
end
endcase
end
// STATE EVOLUTION
always @(posedge clk) begin
if (reset) begin
state <= `IDLE;
end else begin
state <= next_state;
end
end
// CYCLE COUNTER EVOLUTION
always @(posedge clk) begin
if (state == `COMPUTE & ~start_round) begin
cycle_cnt <= cycle_cnt + 1;
end else begin
cycle_cnt <= 0;
end
end
// ROUND COUNTER EVOLUTION
always @(posedge clk) begin
if (reset_round_cnt) begin
round_cnt <= 0;
end else if (start_round) begin
round_cnt <= round_cnt + 1;
end
end
always @(done) begin
if (done) begin
#20 $finish();
end
end
endmodule
| 7.631264 |
module Ascon_tb ();
`include "MSKand_HPC2.vh"
parameter d = 2;
parameter W = 64;
parameter L = 16;
parameter B = 80;
// WIRE
wire [320*d-1:0] out;
// REGS
reg clk;
reg start_dut, reset, started;
reg [16*5*and_pini_nrnd-1:0] rnd;
reg [10:0] counter;
reg [320-1:0] in;
wire [319:0] out_umsk;
// Clock generation
localparam Tclk = 10;
localparam Tclkd = (Tclk / 2.0);
always @(*) #(Tclk / 2.0) clk <= ~clk;
// Module instantiation
Ascon_FSM #(d) dut (
start_dut,
clk,
reset,
rnd,
in,
done,
out
);
// Simulation
initial begin
`ifdef VCD_PATH
$dumpfile(`VCD_PATH);
`else
$dumpfile("a.vcd");
`endif
$dumpvars(0, Ascon_tb);
clk = 0;
reset = 1;
#40 reset = 0;
start_dut = 1;
started = 1;
counter = 0;
in = 320'h80400c0600000000000102030405060708090a0b0c0d0e0f000102030405060708090a0b0c0d0e0f;
rnd = {(16 * 5 * and_pini_nrnd) {1'b1}};
#10 start_dut = 0;
in = 640'hX;
end
// Cycle counter for timing purpose
always @(posedge clk) begin
if (started) begin
counter = counter + 1;
end
end
always @(done) begin
if (done) begin
#20 $finish();
end
end
// Debug
genvar j;
generate
for (j = 0; j < 320; j = j + 1) begin
assign out_umsk[j] = ^(out[d*(j+1)-1:d*j]);
end
endgenerate
endmodule
| 7.327461 |
module asc_speed (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [2:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.511819 |
module asc_to_7seg (
bin,
seg
);
input [7:0] bin;
output [6:0] seg;
reg [6:0] seg;
always @(bin) begin
case (bin)
8'h0, "0": seg = 7'b1000000; // output = 0 indicates a lit segment
8'h1, "1": seg = 7'b1111001; // ---0---
8'h2, "2": seg = 7'b0100100; // | |
8'h3, "3": seg = 7'b0110000; // 5 1
8'h4, "4": seg = 7'b0011001; // | |
8'h5, "5": seg = 7'b0010010; // ---6---
8'h6, "6": seg = 7'b0000010; // | |
8'h7, "7": seg = 7'b1111000; // 4 2
8'h8, "8": seg = 7'b0000000; // | |
8'h9, "9": seg = 7'b0011000; // ---3---
8'ha: seg = 7'b0001000;
8'hb: seg = 7'b0000011;
8'hc: seg = 7'b1000110;
8'hd: seg = 7'b0100001;
8'he: seg = 7'b0000110;
8'hf: seg = 7'b0001110;
"a", "A": seg = 7'b0001000;
"b", "B": seg = 7'b0000011;
"c", "C": seg = 7'b1000110;
"d", "D": seg = 7'b0100001;
"e", "E": seg = 7'b0000110;
"f", "F": seg = 7'b0001110;
"g", "G": seg = 7'b0010000;
"h", "H": seg = 7'b0001011;
"i", "I": seg = 7'b1111011;
"j", "J": seg = 7'b1100001;
"k", "K": seg = 7'b0000111;
"l", "L": seg = 7'b1000111;
"m", "M": seg = 7'b0101011;
"n", "N": seg = 7'b0101011;
"o", "O": seg = 7'b0100011;
"p", "P": seg = 7'b0001100;
"q", "Q": seg = 7'b0011000;
"r", "R": seg = 7'b0101111;
"s", "S": seg = 7'b0010010;
"t", "T": seg = 7'b1001110;
"u", "U": seg = 7'b1000001;
"v", "V": seg = 7'b1000000;
"w", "W": seg = 7'b1000000; // a couple of letters
"x", "X": seg = 7'b0001001; // don't map well. Show
"y", "Y": seg = 7'b0011001; // something anyway.
"z", "Z": seg = 7'b0100100;
" ": seg = 7'b1111111;
"-": seg = 7'b0111111;
default: seg = 7'b1111111;
endcase
end
endmodule
| 7.101012 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module asdf;
// Inputs
reg clk;
reg rst;
reg en;
reg load;
reg [3:0] init;
// Outputs
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
timer uut (
.clk(clk),
.rst(rst),
.en(en),
.load(load),
.init(init),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
en = 0;
load = 0;
init = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.287821 |
module alua_Sel (
input [31:0] pc,
input [31:0] data1,
input alua_sel,
output [31:0] alua
);
assign alua = alua_sel ? data1 : pc; // 1 data1, 0 pc
endmodule
| 6.728452 |
module asel_53 (
input asel_signal,
input [15:0] custom_input,
input [15:0] ra_data,
output reg [15:0] out
);
always @* begin
if (asel_signal) begin
out = custom_input;
end else begin
out = ra_data;
end
end
endmodule
| 6.625559 |
module dual_port_RAM #(
parameter DEPTH = 16,
parameter WIDTH = 8
) (
input wclk //写时钟
, input wenc //写使能
, input [$clog2(DEPTH)-1:0] waddr //深度对2取对数，得到地址的位宽。
, input [ WIDTH-1:0] wdata //数据写入
, input rclk //读时钟
, input renc //读使能
, input [$clog2(DEPTH)-1:0] raddr //深度对2取对数，得到地址的位宽。
, output reg [ WIDTH-1:0] rdata //数据输出
);
reg [WIDTH-1:0] RAM_MEM[0:DEPTH-1]; //寄存器数组
//读写分离
always @(posedge wclk) begin
if (wenc) RAM_MEM[waddr] <= wdata;
end
always @(posedge rclk) begin
if (renc) rdata <= RAM_MEM[raddr];
end
endmodule
| 6.886919 |
module asyn_fifo #(
parameter WIDTH = 8,
parameter DEPTH = 16
) (
input wclk,
input rclk,
input wrstn,
input rrstn,
input winc, //写使能
input rinc, //读使能
input [WIDTH-1:0] wdata,
output wire wfull ,
output wire rempty ,
output wire [WIDTH-1:0] rdata
);
//扩展地址
reg [$clog2(DEPTH):0]
rptr_expand,
rptr_expand_g,
rptr_expand_g_d1,
rptr_expand_g_d2, //写时钟域的读地址
wptr_expand,
wptr_expand_g,
wptr_expand_g_d1,
wptr_expand_g_d2; //读时钟域的写地址
wire wenc, renc;
assign wenc = winc & (~wfull); //写使能且未写满
assign renc = rinc & (~rempty); //读使能且未读空
/**************原始指针读写变化逻辑***********************/
always @(posedge wclk, negedge wrstn) begin
if (~wrstn) wptr_expand <= 0;
else if (wenc) wptr_expand <= wptr_expand + 1;
else wptr_expand <= wptr_expand;
end
always @(posedge rclk, negedge rrstn) begin
if (~rrstn) rptr_expand <= 0;
else if (renc) rptr_expand <= rptr_expand + 1;
else rptr_expand <= rptr_expand;
end
/*********指针地址转换为格雷码*******************/
//由于定义时格雷码是reg类型，因此打一拍更加规范,当然也为了过本题的原因
always @(posedge wclk, negedge wrstn) begin
if (~wrstn) wptr_expand_g <= 0;
else wptr_expand_g <= (wptr_expand >> 1) ^ (wptr_expand);
end
always @(posedge rclk, negedge rrstn) begin
if (~rrstn) rptr_expand_g <= 0;
else rptr_expand_g <= (rptr_expand >> 1) ^ (rptr_expand);
end
/******************同步器************************/
always @(posedge wclk, negedge wrstn) begin
if (~wrstn) {rptr_expand_g_d2, rptr_expand_g_d1} <= 2'b0;
else {rptr_expand_g_d2, rptr_expand_g_d1} <= {rptr_expand_g_d1, rptr_expand_g};
end
always @(posedge rclk, negedge rrstn) begin
if (~rrstn) {wptr_expand_g_d2, wptr_expand_g_d1} <= 2'b0;
else {wptr_expand_g_d2, wptr_expand_g_d1} <= {wptr_expand_g_d1, wptr_expand_g};
end
/***************EMPTY&FULL************************/
assign rempty = (rptr_expand_g == wptr_expand_g_d2) ? 1 : 0;
assign wfull = (wptr_expand_g == {~(rptr_expand_g_d2[$clog2(
DEPTH
)-:2]), rptr_expand_g_d2[$clog2(
DEPTH
)-2:0]}) ? 1 : 0;
/********************双口RAM例化****************/
dual_port_RAM #(DEPTH, WIDTH) d1 (
wclk //
, wenc //
, wptr_expand[$clog2(DEPTH)-1:0] //
, wdata //
, rclk //
, renc //
, rptr_expand[$clog2(DEPTH)-1:0] //!!!
, rdata //
);
endmodule
| 8.920376 |
module ASFIFO_tb;
parameter DEPTH = 16;
parameter WIDTH = 8;
/************端口声明****************/
reg wclk, rclk, wrstn, rrstn, winc, rinc;
reg [WIDTH-1:0] wdata;
wire wfull, rempty;
wire [WIDTH-1:0] rdata;
/************模块例化****************/
asyn_fifo a1 (
wclk,
rclk,
wrstn,
rrstn,
winc,
rinc,
wdata,
wfull,
rempty,
rdata
);
/************激励****************/
initial begin
$dumpfile("ASFIFO.vcd");
$dumpvars;
wclk <= 0;
rclk <= 0;
wrstn <= 0;
rrstn <= 0;
winc <= 1;
rinc <= 0;
wdata <= $random;
#35 wrstn <= 1;
rrstn <= 1;
repeat (10) begin
@(negedge wclk) wdata <= $random;
end
#6 rinc <= 1;
repeat (20) begin
@(negedge wclk) wdata <= $random;
end
winc <= 0;
#1000 $finish;
end
/************时钟****************/
always #10 wclk = ~wclk;
always #3 rclk = ~rclk;
endmodule
| 6.975138 |
module ASGEN (
input Clock, // 10 MHz
input Reset_n,
output [13:0] SignalOut // Square Wave of 1.250 MHz
);
// Internal feeding
//parameter VMIN = 15'hFFF;
//parameter VPP = 15'h1FF;
//parameter HALFPERIOD = 4;
// External feeding
parameter VMIN = 15'h3F;
parameter VPP = 15'hFFF; // 144 mV
parameter HALFPERIOD = 2;
reg [14:0] Signal_q, Signal_d;
reg [9:0] CC;
(* syn_encoding = "user, safe" *) reg [1:0] State_q, State_d;
parameter RISING_STATE = 3'b01, FALLING_STATE = 3'b10;
always @(State_q, Signal_q, CC) begin
Signal_d <= Signal_q;
State_d <= State_q;
case (State_q)
RISING_STATE: begin
Signal_d <= VPP + VMIN;
if (CC == 'b0) State_d <= FALLING_STATE;
end
FALLING_STATE: begin
Signal_d <= VMIN;
if (CC == 'b0) State_d <= RISING_STATE;
end
default: begin
State_d <= FALLING_STATE;
end
endcase
end
assign SignalOut = Signal_q[13:0];
always @(posedge Clock or negedge Reset_n) begin
if (Reset_n == 1'b0) begin
State_q <= RISING_STATE;
Signal_q <= VMIN;
CC <= 'b0;
end else begin
State_q <= State_d;
Signal_q <= Signal_d;
CC <= (CC > HALFPERIOD) ? 'b0 : CC + 1;
end
end
endmodule
| 6.730195 |
module ASG_NR_NBFC (
clk,
rst,
result
);
input clk;
input rst;
output reg [3:0] result;
function [3:0] get_address;
input [1:0] state_var;
begin
case (state_var)
2'b00: get_address <= 4'b0000;
default: get_address <= 4'b1111;
endcase
end
endfunction
always @(posedge clk or negedge rst) begin
if (~rst) result = get_address(2'b00);
else result = get_address(2'b11);
end
endmodule
| 6.937886 |
module ASG_NR_SUPN (
in_a,
in_b,
out_a
);
input in_a;
input in_b;
output reg [3:0] out_a;
supply0 s0;
supply1 s1;
supply0 p0;
supply1 p1;
assign s0 = in_a;
assign s1 = in_b;
buf (p0, in_a);
buf (p1, in_b);
always @(s0 or s1 or p0 or p1) out_a = {s0, s1, p0, p1};
endmodule
| 6.610801 |
module ashift16 (
data,
distance,
result
);
input [31:0] data;
input [3:0] distance;
output [31:0] result;
wire [31:0] sub_wire0;
wire sub_wire1 = 1'h1;
wire [31:0] result = sub_wire0[31:0];
lpm_clshift LPM_CLSHIFT_component (
.data(data),
.direction(sub_wire1),
.distance(distance),
.result(sub_wire0)
// synopsys translate_off
, .aclr(),
.clken(),
.clock(),
.overflow(),
.underflow()
// synopsys translate_on
);
defparam LPM_CLSHIFT_component.lpm_shifttype = "ARITHMETIC", LPM_CLSHIFT_component.lpm_type =
"LPM_CLSHIFT", LPM_CLSHIFT_component.lpm_width = 32, LPM_CLSHIFT_component.lpm_widthdist = 4;
endmodule
| 6.699781 |
module asic_and2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a & b;
endmodule
| 8.277154 |
module asic_and3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = a & b & c;
endmodule
| 8.374047 |
module asic_and4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = a & b & c & d;
endmodule
| 9.106081 |
module asic_ao21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = (a0 & a1) | b0;
endmodule
| 8.022812 |
module asic_ao211 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input c0,
output z
);
assign z = (a0 & a1) | b0 | c0;
endmodule
| 7.432624 |
module asic_ao22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = (a0 & a1) | (b0 & b1);
endmodule
| 8.333303 |
module asic_ao221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = (a0 & a1) | (b0 & b1) | (c0);
endmodule
| 7.695692 |
module asic_ao222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = (a0 & a1) | (b0 & b1) | (c0 & c1);
endmodule
| 7.664919 |
module asic_ao31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = (a0 & a1 & a2) | b0;
endmodule
| 7.82953 |
module asic_ao311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = (a0 & a1 & a2) | b0 | c0;
endmodule
| 7.297137 |
module asic_ao32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = (a0 & a1 & a2) | (b0 & b1);
endmodule
| 8.151539 |
module asic_ao33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = (a0 & a1 & a2) | (b0 & b1 & b2);
endmodule
| 7.891379 |
module asic_aoi21 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
output z
);
assign z = ~((a0 & a1) | b0);
endmodule
| 8.508327 |
module asic_aoi211 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input c0,
output z
);
assign z = ~((a0 & a1) | b0 | c0);
endmodule
| 7.635824 |
module asic_aoi22 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
output z
);
assign z = ~((a0 & a1) | (b0 & b1));
endmodule
| 8.570028 |
module asic_aoi221 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
output z
);
assign z = ~((a0 & a1) | (b0 & b1) | c0);
endmodule
| 7.938187 |
module asic_aoi222 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = ~((a0 & a1) | (b0 & b1) | (c0 & c1));
endmodule
| 7.934978 |
module asic_aoi31 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
output z
);
assign z = ~((a0 & a1 & a2) | b0);
endmodule
| 8.270253 |
module asic_aoi311 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input c0,
output z
);
assign z = ~((a0 & a1 & a2) | b0 | c0);
endmodule
| 7.833196 |
module asic_aoi32 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
output z
);
assign z = ~((a0 & a1 & a2) | (b0 & b1));
endmodule
| 8.65695 |
module asic_aoi33 #(
parameter PROP = "DEFAULT"
) (
input a0,
input a1,
input a2,
input b0,
input b1,
input b2,
output z
);
assign z = ~((a0 & a1 & a2) | (b0 & b1 & b2));
endmodule
| 8.329056 |
module asic_buf #(
parameter PROP = "DEFAULT"
) (
input a,
output z
);
assign z = a;
endmodule
| 7.152511 |
module asic_clkand2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a & b;
endmodule
| 8.005463 |
module asic_clkbuf #(
parameter PROP = "DEFAULT"
) (
input a,
output z
);
assign z = a;
endmodule
| 7.283178 |
module asic_clkinv #(
parameter PROP = "DEFAULT"
) (
input a,
output z
);
assign z = ~a;
endmodule
| 8.145487 |
module asic_clkmux2 #(
parameter PROP = "DEFAULT"
) (
input clk0,
input clk1,
input sel,
output z
);
assign z = sel ? clk0 : clk1;
endmodule
| 7.264576 |
module asic_clknand2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a & b);
endmodule
| 8.441109 |
module asic_clknor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a | b);
endmodule
| 7.665582 |
module asic_clkor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a | b;
endmodule
| 7.838454 |
module asic_clkxor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = a ^ b;
endmodule
| 8.354975 |
module asic_csa32 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output sum,
output carry
);
assign sum = a ^ b ^ c;
assign carry = (a & b) | (b & c) | (c & a);
endmodule
| 8.977818 |
module asic_csa42 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
input cin,
output sum,
output carry,
output cout
);
assign cout = (a & b) | (b & c) | (a & c);
assign sumint = a ^ b ^ c;
assign sum = cin ^ d ^ sumint;
assign carry = (cin & d) | (cin & sumint) | (d & sumint);
endmodule
| 8.445865 |
module asic_decap #(
parameter PROP = "DEFAULT"
) (
input vss,
output vdd
);
endmodule
| 6.535078 |
module asic_dffnq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
output reg q
);
always @(negedge clk) q <= d;
endmodule
| 7.499818 |
module asic_dffq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
| 7.020688 |
module asic_dffqn #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
output reg qn
);
always @(posedge clk) qn <= ~d;
endmodule
| 7.984324 |
module asic_dffrq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
input nreset,
output reg q
);
always @(posedge clk or negedge nreset)
if (!nreset) q <= 1'b0;
else q <= d;
endmodule
| 7.292078 |
module asic_dffrqn #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
input nreset,
output reg qn
);
always @(posedge clk or negedge nreset)
if (!nreset) qn <= 1'b1;
else qn <= ~d;
endmodule
| 7.902752 |
module asic_dffsq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
input nset,
output reg q
);
always @(posedge clk or negedge nset)
if (!nset) q <= 1'b1;
else q <= d;
endmodule
| 7.065913 |
module asic_dffsqn #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
input nset,
output reg qn
);
always @(posedge clk or negedge nset)
if (!nset) qn <= 1'b0;
else qn <= ~d;
endmodule
| 8.035124 |
module asic_dmux2 #(
parameter PROP = "DEFAULT"
) (
input sel1,
input sel0,
input in1,
input in0,
output out
);
assign out = sel0 & in0 | sel1 & in1;
endmodule
| 7.506973 |
module asic_dmux3 #(
parameter PROP = "DEFAULT"
) (
input sel2,
input sel1,
input sel0,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 | sel1 & in1 | sel2 & in2;
endmodule
| 7.78096 |
module asic_dmux4 #(
parameter PROP = "DEFAULT"
) (
input sel3,
input sel2,
input sel1,
input sel0,
input in3,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 | sel1 & in1 | sel2 & in2 | sel3 & in3;
endmodule
| 7.841063 |
module asic_dmux5 #(
parameter PROP = "DEFAULT"
) (
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input in4,
input in3,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 | sel1 & in1 | sel2 & in2 | sel3 & in3 | sel4 & in4;
endmodule
| 7.695757 |
module asic_dmux6 #(
parameter PROP = "DEFAULT"
) (
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input in5,
input in4,
input in3,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 | sel1 & in1 | sel2 & in2 | sel3 & in3 | sel4 & in4 | sel5 & in5;
endmodule
| 7.378883 |
module asic_dmux7 #(
parameter PROP = "DEFAULT"
) (
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input in6,
input in5,
input in4,
input in3,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 |
sel1 & in1 |
sel2 & in2 |
sel3 & in3 |
sel4 & in4 |
sel5 & in5 |
sel6 & in6;
endmodule
| 7.131071 |
module asic_dmux8 #(
parameter PROP = "DEFAULT"
) (
input sel7,
input sel6,
input sel5,
input sel4,
input sel3,
input sel2,
input sel1,
input sel0,
input in7,
input in6,
input in5,
input in4,
input in3,
input in2,
input in1,
input in0,
output out
);
assign out = sel0 & in0 |
sel1 & in1 |
sel2 & in2 |
sel3 & in3 |
sel4 & in4 |
sel5 & in5 |
sel6 & in6 |
sel7 & in7;
endmodule
| 7.241782 |
module asic_dsync #(
parameter PROP = "DEFAULT"
) (
input clk, // clock
input nreset, // async active low reset
input in, // input data
output out // synchronized data
);
localparam SYNCPIPE = 2;
reg [SYNCPIPE-1:0] sync_pipe;
always @(posedge clk or negedge nreset)
if (!nreset) sync_pipe[SYNCPIPE-1:0] <= 'b0;
else sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-1:0], in};
assign out = sync_pipe[SYNCPIPE-1];
endmodule
| 8.873007 |
module asic_footer #(
parameter PROP = "DEFAULT"
) (
input nsleep, // 0 = disabled ground
input vssin, // input supply
output vssout // gated output supply
);
// Primitive Device
nmos m0 (vddout, vddin, nsleep); //d,s,g
endmodule
| 7.206173 |
module asic_iddr #(
parameter PROP = "DEFAULT"
) (
input clk, // clock
input in, // data input sampled on both edges of clock
output reg outrise, // rising edge sample
output reg outfall // falling edge sample
);
// Negedge Sample
always @(negedge clk) outfall <= in;
// Posedge Sample
reg inrise;
always @(posedge clk) inrise <= in;
// Posedge Latch (for hold)
always @(clk or inrise) if (~clk) outrise <= inrise;
endmodule
| 7.732139 |
module asic_inv #(
parameter PROP = "DEFAULT"
) (
input a,
output z
);
assign z = ~a;
endmodule
| 7.741121 |
module asic_isohi #(
parameter PROP = "DEFAULT"
) (
input iso, // isolation signal
input in, // input
output out // out = iso | in
);
assign out = iso | in;
endmodule
| 7.416668 |
module asic_isolo #(
parameter PROP = "DEFAULT"
) (
input iso, // isolation signal
input in, // input
output out // out = ~iso & in
);
assign out = ~iso & in;
endmodule
| 7.663716 |
module asic_keeper #(
parameter PROP = "DEFAULT"
) (
inout z
);
endmodule
| 6.674383 |
module asic_latnq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
output reg q
);
always @(clk or d) if (~clk) q <= d;
endmodule
| 7.069341 |
module asic_latq #(
parameter PROP = "DEFAULT"
) (
input d,
input clk,
output reg q
);
always @(clk or d) if (clk) q <= d;
endmodule
| 6.662664 |
module asic_mux2 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input s,
output z
);
assign z = (d0 & ~s) | (d1 & s);
endmodule
| 7.909366 |
module asic_mux3 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input d2,
input s0,
input s1,
output z
);
assign z = (d0 & ~s0 & ~s1) | (d1 & s0 & ~s1) | (d2 & s1);
endmodule
| 7.735542 |
module asic_mux4 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input d2,
input d3,
input s0,
input s1,
output z
);
assign z = (d0 & ~s1 & ~s0) | (d1 & ~s1 & s0) | (d2 & s1 & ~s0) | (d2 & s1 & s0);
endmodule
| 8.691704 |
module asic_muxi2 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input s,
output z
);
assign z = ~((d0 & ~s) | (d1 & s));
endmodule
| 8.259592 |
module asic_muxi3 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input d2,
input s0,
input s1,
output z
);
assign z = ~((d0 & ~s0 & ~s1) | (d1 & s0 & ~s1) | (d2 & s1));
endmodule
| 8.161664 |
module asic_muxi4 #(
parameter PROP = "DEFAULT"
) (
input d0,
input d1,
input d2,
input d3,
input s0,
input s1,
output z
);
assign z = ~((d0 & ~s1 & ~s0) | (d1 & ~s1 & s0) | (d2 & s1 & ~s0) | (d2 & s1 & s0));
endmodule
| 8.940778 |
module asic_nand2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a & b);
endmodule
| 8.952388 |
module asic_nand3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = ~(a & b & c);
endmodule
| 8.822009 |
module asic_nand4 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
input d,
output z
);
assign z = ~(a & b & c & d);
endmodule
| 9.743313 |
module asic_nor2 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
output z
);
assign z = ~(a | b);
endmodule
| 7.48129 |
module asic_nor3 #(
parameter PROP = "DEFAULT"
) (
input a,
input b,
input c,
output z
);
assign z = ~(a | b | c);
endmodule
| 7.648988 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.