code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module axi_fifo_51 #(
parameter DATA_WIDTH = 32,
parameter ALMOST_FULL_THRESH = 16,
parameter TUSER_WIDTH = 8,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tlast,
input [TUSER_WIDTH-1:0] s_axis_tuser,
output s_axis_tready,
output almost_full,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
output m_axis_tlast,
output [TUSER_WIDTH-1:0] m_axis_tuser,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH + TUSER_WIDTH + 1;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
localparam [ADDR_WIDTH:0] high_thresh = ALMOST_FULL_THRESH;
reg [ADDR_WIDTH:0] data_cnt_s = {{ADDR_P1{{1'b0}}}};
reg [ADDR_P1:0] high_compare;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "distributed" *) reg [FIFO_MSB:0] buffer[DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_ptr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = {s_axis_tlast, s_axis_tuser, s_axis_tdata};
assign m_axis_tdata = data_d1[DATA_WIDTH-1:0];
assign m_axis_tuser = data_d1[FIFO_MSB-1:DATA_WIDTH];
assign m_axis_tlast = data_d1[FIFO_MSB];
assign almost_full = high_compare[ADDR_WIDTH];
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
next_wr_addr = wr_addr + 1;
end
end
end
// Data Cnt Logic
always @(posedge clk) begin
data_cnt_s <= next_wr_ptr - next_rd_ptr + occ_reg[0];
high_compare <= high_thresh - data_cnt_s;
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= 0;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 7.573804 |
module axi_fifo_64 #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input clk,
input sync_reset,
input s_axis_tvalid,
input [DATA_WIDTH-1:0] s_axis_tdata,
output s_axis_tready,
input [8:0] delay,
output m_axis_tvalid,
output [DATA_WIDTH-1:0] m_axis_tdata,
input m_axis_tready
);
localparam ADDR_P1 = ADDR_WIDTH + 1;
localparam FIFO_WIDTH = DATA_WIDTH;
localparam FIFO_MSB = FIFO_WIDTH - 1;
localparam ADDR_MSB = ADDR_WIDTH - 1;
localparam DEPTH = 2 ** ADDR_WIDTH;
reg [ADDR_WIDTH:0] wr_ptr = 0, next_wr_ptr;
reg [ADDR_WIDTH:0] wr_addr = 0, next_wr_addr;
reg [ADDR_WIDTH:0] rd_ptr = 0, next_rd_ptr;
(* ram_style = "block" *)reg [FIFO_MSB:0] buffer [DEPTH-1:0];
wire [FIFO_MSB:0] wr_data;
reg [8:0] delay_d1, next_delay_d1;
wire add_delay;
wire [ADDR_WIDTH:0] delay_s;
// full when first MSB different but rest same
wire full;
// empty when pointers match exactly
wire empty;
// control signals
reg wr;
reg rd;
reg [1:0] occ_reg = 2'b00, next_occ_reg;
reg [FIFO_MSB:0] data_d0, data_d1, next_data_d0, next_data_d1;
// control signals
assign full = ((wr_addr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) && (wr_addr[ADDR_MSB:0] == rd_ptr[ADDR_MSB:0]));
assign s_axis_tready = ~full;
assign m_axis_tvalid = occ_reg[1];
assign empty = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0;
assign wr_data = s_axis_tdata;
assign m_axis_tdata = data_d1;
assign add_delay = (delay != delay_d1) ? 1'b1 : 1'b0;
assign delay_s = {1'b0, delay};
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
buffer[i] = 0;
end
end
// Write logic
always @* begin
wr = 1'b0;
next_wr_ptr = wr_ptr;
next_wr_addr = wr_addr;
next_delay_d1 = delay_d1;
if (s_axis_tvalid) begin
// input data valid
if (~full) begin
// not full, perform write
wr = 1'b1;
next_wr_ptr = wr_ptr + 1;
if (add_delay == 1'b1) begin
next_wr_addr = wr_ptr + delay_s + 1;
next_delay_d1 = delay;
end else begin
next_wr_addr = wr_addr + 1;
end
end
end
end
always @(posedge clk) begin
if (sync_reset) begin
wr_ptr <= 0;
wr_addr <= delay_s;
occ_reg <= 0;
data_d0 <= 0;
data_d1 <= 0;
delay_d1 <= 0;
end else begin
wr_ptr <= next_wr_ptr;
wr_addr <= next_wr_addr;
occ_reg <= next_occ_reg;
data_d0 <= next_data_d0;
data_d1 <= next_data_d1;
delay_d1 <= next_delay_d1;
end
if (wr) begin
buffer[wr_addr[ADDR_MSB:0]] <= wr_data;
end
end
// Read logic
always @* begin
rd = 1'b0;
next_rd_ptr = rd_ptr;
next_occ_reg[0] = occ_reg[0];
next_occ_reg[1] = occ_reg[1];
next_data_d0 = data_d0;
next_data_d1 = data_d1;
if (occ_reg != 2'b11 | m_axis_tready == 1'b1) begin
// output data not valid OR currently being transferred
if (~empty) begin
// not empty, perform read
rd = 1'b1;
next_rd_ptr = rd_ptr + 1;
end
end
if (rd) begin
next_occ_reg[0] = 1'b1;
end else if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[0] = 1'b0;
end
if (m_axis_tready == 1'b1 || occ_reg[1] == 1'b0) begin
next_occ_reg[1] = occ_reg[0];
end
if (rd) begin
next_data_d0 = buffer[rd_ptr[ADDR_MSB:0]];
end
if (m_axis_tready | ~occ_reg[1]) begin
next_data_d1 = data_d0;
end
end
always @(posedge clk) begin
if (sync_reset) begin
rd_ptr <= 0;
end else begin
rd_ptr <= next_rd_ptr;
end
end
endmodule
| 8.202893 |
module axi_fifo_bram #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output reg [WIDTH-1:0] o_tdata = 'd0,
output reg o_tvalid = 1'b0,
input o_tready,
output reg [15:0] space,
output reg [15:0] occupied
);
wire [WIDTH-1:0] int_tdata;
wire int_tready;
wire full, empty;
wire write = i_tvalid & i_tready;
// read_int will assert when either a read occurs or the output register is empty (and there is data in the shift register fifo)
wire read_int = ~empty & int_tready;
// read will only assert when an actual 1read request occurs at the interface
wire read = o_tready & o_tvalid;
assign i_tready = ~full;
// Read side states
localparam ST_EMPTY = 0;
localparam PRE_READ = 1;
localparam READING = 2;
reg [SIZE-1:0] wr_addr, rd_addr;
reg [1:0] read_state;
reg empty_reg = 1'b1, full_reg = 1'b0;
always @(posedge clk)
if (reset) wr_addr <= 0;
else if (clear) wr_addr <= 0;
else if (write) wr_addr <= wr_addr + 1;
ram_2port #(
.DWIDTH(WIDTH),
.AWIDTH(SIZE)
) ram (
.clka (clk),
.ena (1'b1),
.wea (write),
.addra(wr_addr),
.dia (i_tdata),
.doa (),
.clkb (clk),
.enb ((read_state == PRE_READ) | read_int),
.web (1'b0),
.addrb(rd_addr),
.dib ({WIDTH{1'b1}}),
.dob (int_tdata)
);
always @(posedge clk)
if (reset) begin
read_state <= ST_EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end else if (clear) begin
read_state <= ST_EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end else
case (read_state)
ST_EMPTY:
if (write) begin
//rd_addr <= wr_addr;
read_state <= PRE_READ;
end
PRE_READ: begin
read_state <= READING;
empty_reg <= 0;
rd_addr <= rd_addr + 1;
end
READING:
if (read_int)
if (rd_addr == wr_addr) begin
empty_reg <= 1;
if (write) read_state <= PRE_READ;
else read_state <= ST_EMPTY;
end else rd_addr <= rd_addr + 1;
endcase // case(read_state)
wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
wire becoming_full = wr_addr == dont_write_past_me;
always @(posedge clk)
if (reset) full_reg <= 0;
else if (clear) full_reg <= 0;
else if (read_int & ~write) full_reg <= 0;
//else if(write & ~read_int & (wr_addr == (rd_addr-3)))
else if (write & ~read_int & becoming_full) full_reg <= 1;
//assign empty = (read_state != READING);
assign empty = empty_reg;
// assign full = ((rd_addr - 1) == wr_addr);
assign full = full_reg;
// Output registered stage
always @(posedge clk) begin
// Valid flag
if (reset | clear) o_tvalid <= 1'b0;
else if (int_tready) o_tvalid <= ~empty;
// Data
if (int_tready) o_tdata <= int_tdata;
end
assign int_tready = o_tready | ~o_tvalid;
//////////////////////////////////////////////
// space and occupied are for diagnostics only
// not guaranteed exact
localparam NUMLINES = (1 << SIZE);
always @(posedge clk)
if (reset) space <= NUMLINES;
else if (clear) space <= NUMLINES;
else if (read & ~write) space <= space + 16'b1;
else if (write & ~read) space <= space - 16'b1;
always @(posedge clk)
if (reset) occupied <= 16'b0;
else if (clear) occupied <= 16'b0;
else if (read & ~write) occupied <= occupied - 16'b1;
else if (write & ~read) occupied <= occupied + 16'b1;
endmodule
| 8.008711 |
module axi_fifo_cascade #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output [15:0] space,
output [15:0] occupied
);
wire [WIDTH-1:0] int1_tdata, int2_tdata;
wire int1_tvalid, int1_tready, int2_tvalid, int2_tready;
axi_fifo_short #(
.WIDTH(WIDTH)
) pre_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(i_tdata),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata(int1_tdata),
.o_tvalid(int1_tvalid),
.o_tready(int1_tready),
.space(),
.occupied()
);
axi_fifo #(
.WIDTH(WIDTH),
.SIZE (SIZE)
) main_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(int1_tdata),
.i_tvalid(int1_tvalid),
.i_tready(int1_tready),
.o_tdata(int2_tdata),
.o_tvalid(int2_tvalid),
.o_tready(int2_tready),
.space(space),
.occupied(occupied)
); // May change unexpectedly, but are always conservative
axi_fifo_short #(
.WIDTH(WIDTH)
) post_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(int2_tdata),
.i_tvalid(int2_tvalid),
.i_tready(int2_tready),
.o_tdata(o_tdata),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endmodule
| 7.133169 |
module axi_fifo_fake #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output [17:0] space,
output [17:0] occupied
);
assign o_tdata = i_tdata;
assign o_tvalid = i_tvalid;
assign i_tready = o_tready;
assign space = 128;
assign occupied = 0;
endmodule
| 6.535135 |
module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data.
// It extracts and indicates the header (first word) of a packet in the FIFO. The header and flag are pipelined
// for timing closure.
//
module axi_fifo_header
#(
parameter WIDTH=64 // Bit width of FIFO word.
)
(
input clk,
input reset,
input clear,
// Monitored FIFO signals
input [WIDTH-1:0] o_tdata,
input o_tvalid,
input o_tready,
input o_tlast,
input pkt_present,
// Header signals
output reg [WIDTH-1:0] header,
output reg header_valid
);
localparam WAIT_SOF = 0;
localparam WAIT_EOF = 1;
reg out_state;
//
// Monitor packets leaving FIFO
//
always @(posedge clk)
if (reset | clear) begin
out_state <= WAIT_SOF;
end else
case(out_state)
//
// After RESET or the EOF of previous packet, the first cycle with
// output valid asserted is the SOF and presents the Header word.
// The cycle following the concurrent presentation of asserted output
// valid and output ready presents the word following the header.
//
WAIT_SOF:
if (o_tvalid && o_tready) begin
out_state <= WAIT_EOF;
end else begin
out_state <= WAIT_SOF;
end
//
// EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
//
WAIT_EOF:
if (o_tlast && o_tvalid && o_tready) begin
out_state <= WAIT_SOF;
end else begin
out_state <= WAIT_EOF;
end
endcase // case(in_state)
//
// Pipeline Header signals
//
always @(posedge clk)
if (reset | clear) begin
header <= 0;
header_valid <= 0;
end else if (o_tvalid && (out_state == WAIT_SOF) && pkt_present) begin
// Header will remian valid until o_tready is asserted as this will cause a state transition.
header <= o_tdata;
header_valid <= 1;
end else begin
header_valid <= 0;
end
endmodule
| 8.147278 |
module axi_fifo_legacy #(
parameter WIDTH = 32,
SIZE = 9
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output reg [15:0] space,
output reg [15:0] occupied
);
generate
if (SIZE <= 5) begin
wire [5:0] space_short, occupied_short;
axi_fifo_short #(
.WIDTH(WIDTH)
) fifo_short (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(i_tdata),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata(o_tdata),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(space_short),
.occupied(occupied_short)
);
always @* space <= {10'b0, space_short};
always @* occupied <= {10'b0, occupied_short};
end else begin
wire write = i_tvalid & i_tready;
wire read = o_tvalid & o_tready;
wire full, empty;
assign i_tready = ~full;
assign o_tvalid = ~empty;
// Read side states
localparam EMPTY = 0;
localparam PRE_READ = 1;
localparam READING = 2;
reg [SIZE-1:0] wr_addr, rd_addr;
reg [1:0] read_state;
reg empty_reg = 1'b1, full_reg = 1'b0;
always @(posedge clk)
if (reset) wr_addr <= 0;
else if (clear) wr_addr <= 0;
else if (write) wr_addr <= wr_addr + 1;
ram_2port #(
.DWIDTH(WIDTH),
.AWIDTH(SIZE)
) ram (
.clka (clk),
.ena (1'b1),
.wea (write),
.addra(wr_addr),
.dia (i_tdata),
.doa (),
.clkb (clk),
.enb ((read_state == PRE_READ) | read),
.web (1'b0),
.addrb(rd_addr),
.dib ({WIDTH{1'b1}}),
.dob (o_tdata)
);
always @(posedge clk)
if (reset) begin
read_state <= EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end else if (clear) begin
read_state <= EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end else
case (read_state)
EMPTY:
if (write) begin
//rd_addr <= wr_addr;
read_state <= PRE_READ;
end
PRE_READ: begin
read_state <= READING;
empty_reg <= 0;
rd_addr <= rd_addr + 1;
end
READING:
if (read)
if (rd_addr == wr_addr) begin
empty_reg <= 1;
if (write) read_state <= PRE_READ;
else read_state <= EMPTY;
end else rd_addr <= rd_addr + 1;
endcase // case(read_state)
wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
wire becoming_full = wr_addr == dont_write_past_me;
always @(posedge clk)
if (reset) full_reg <= 0;
else if (clear) full_reg <= 0;
else if (read & ~write) full_reg <= 0;
//else if(write & ~read & (wr_addr == (rd_addr-3)))
else if (write & ~read & becoming_full) full_reg <= 1;
//assign empty = (read_state != READING);
assign empty = empty_reg;
// assign full = ((rd_addr - 1) == wr_addr);
assign full = full_reg;
//////////////////////////////////////////////
// space and occupied are for diagnostics only
// not guaranteed exact
localparam NUMLINES = (1 << SIZE);
always @(posedge clk)
if (reset) space <= NUMLINES;
else if (clear) space <= NUMLINES;
else if (read & ~write) space <= space + 16'b1;
else if (write & ~read) space <= space - 16'b1;
always @(posedge clk)
if (reset) occupied <= 16'b0;
else if (clear) occupied <= 16'b0;
else if (read & ~write) occupied <= occupied - 16'b1;
else if (write & ~read) occupied <= occupied + 16'b1;
end
endgenerate
endmodule
| 7.812887 |
module uses the SRLC32E primitive explicitly and as such
// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
//
module axi_fifo_short
#(parameter WIDTH=32)
(
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output reg [5:0] space,
output reg [5:0] occupied
);
reg full, empty;
wire write = i_tvalid & i_tready;
wire read = o_tready & o_tvalid;
assign i_tready = ~full;
assign o_tvalid = ~empty;
reg [4:0] a;
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_srlc32e
SRLC32E
srlc32e(.Q(o_tdata[i]), .Q31(),
.A(a), //.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),.A4(a[4]),
.CE(write),.CLK(clk),.D(i_tdata[i]));
end
endgenerate
always @(posedge clk)
if(reset)
begin
a <= 0;
empty <= 1;
full <= 0;
end
else if(clear)
begin
a <= 0;
empty <= 1;
full<= 0;
end
else if(read & ~write)
begin
full <= 0;
if(a==0)
empty <= 1;
else
a <= a - 1;
end
else if(write & ~read)
begin
empty <= 0;
if(~empty)
a <= a + 1;
if(a == 30)
full <= 1;
end
// NOTE will fail if you write into a full fifo or read from an empty one
//////////////////////////////////////////////////////////////
// space and occupied are used for diagnostics, not
// guaranteed correct
//assign space = full ? 0 : empty ? 16 : 15-a;
//assign occupied = empty ? 0 : full ? 16 : a+1;
always @(posedge clk)
if(reset)
space <= 6'd32;
else if(clear)
space <= 6'd32;
else if(read & ~write)
space <= space + 6'd1;
else if(write & ~read)
space <= space - 6'd1;
always @(posedge clk)
if(reset)
occupied <= 6'd0;
else if(clear)
occupied <= 6'd0;
else if(read & ~write)
occupied <= occupied - 6'd1;
else if(write & ~read)
occupied <= occupied + 6'd1;
endmodule
| 7.023134 |
module uses the SRLC32E primitive explicitly and as such
// can only be used with Xilinx technology of the VIRTEX-6/SPARTAN-6/SIERIES-7 or newer.
//
module axi_fifo_short_al
#(parameter WIDTH=32)
(
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tvalid,
output i_tready,
output i_tready_al,
output [WIDTH-1:0] o_tdata,
output o_tvalid,
input o_tready,
output reg [5:0] space,
output reg [5:0] occupied
);
reg full, empty;
reg full_al;
wire write = i_tvalid & i_tready;
wire read = o_tready & o_tvalid;
assign i_tready = ~full;
assign i_tready_al = ~full_al;
assign o_tvalid = ~empty;
reg [4:0] a;
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_srlc32e
SRLC32E
srlc32e(.Q(o_tdata[i]), .Q31(),
.A(a), //.A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),.A4(a[4]),
.CE(write),.CLK(clk),.D(i_tdata[i]));
end
endgenerate
always @(posedge clk)
if(reset)
begin
a <= 0;
empty <= 1;
full <= 0;
full_al <= 0;
end
else if(clear)
begin
a <= 0;
empty <= 1;
full<= 0;
full_al <= 0;
end
else if(read & ~write)
begin
full <= 0;
if(a >= 28)
full_al <= 1'b1;
else
full_al <= 1'b0;
if(a==0)
empty <= 1;
else
a <= a - 1;
end
else if(write & ~read)
begin
empty <= 0;
if(~empty)
a <= a + 1;
if(a == 30)
full <= 1;
if(a >= 28)
full_al <= 1'b1;
end
// NOTE will fail if you write into a full fifo or read from an empty one
//////////////////////////////////////////////////////////////
// space and occupied are used for diagnostics, not
// guaranteed correct
//assign space = full ? 0 : empty ? 16 : 15-a;
//assign occupied = empty ? 0 : full ? 16 : a+1;
always @(posedge clk)
if(reset)
space <= 6'd32;
else if(clear)
space <= 6'd32;
else if(read & ~write)
space <= space + 6'd1;
else if(write & ~read)
space <= space - 6'd1;
always @(posedge clk)
if(reset)
occupied <= 6'd0;
else if(clear)
occupied <= 6'd0;
else if(read & ~write)
occupied <= occupied - 6'd1;
else if(write & ~read)
occupied <= occupied + 6'd1;
endmodule
| 7.023134 |
module axi_fir_filter_dec #(
parameter WIDTH = 24,
parameter COEFF_WIDTH = 18,
parameter NUM_COEFFS = 47,
parameter [NUM_COEFFS*COEFF_WIDTH-1:0] COEFFS_VEC = {
{1'b0, {(COEFF_WIDTH - 1) {1'b1}}}, {(COEFF_WIDTH * (NUM_COEFFS - 1)) {1'b0}}
},
parameter BLANK_OUTPUT = 0
) (
input clk,
input reset,
input [2*WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] tdata_fir0_dec0;
wire tvalid_fir0_dec0;
wire tlast_fir0_dec0;
wire tready_fir0_dec0;
wire [WIDTH-1:0] tdata_fir1_dec1;
wire tvalid_fir1_dec1;
wire tlast_fir1_dec1;
wire tready_fir1_dec1;
wire [WIDTH-1:0] tdata_fir0;
wire [WIDTH-1:0] tdata_fir1;
wire [WIDTH-1:0] tdata_dec0;
wire [WIDTH-1:0] tdata_dec1;
// Split input data into real and imag. part.
assign tdata_fir0 = i_tdata[2*WIDTH-1:WIDTH];
assign tdata_fir1 = i_tdata[WIDTH-1:0];
// FIR filter for real part
axi_fir_filter #(
.IN_WIDTH(WIDTH),
.COEFF_WIDTH(COEFF_WIDTH),
.OUT_WIDTH(WIDTH),
.NUM_COEFFS(NUM_COEFFS),
.COEFFS_VEC(COEFFS_VEC),
.RELOADABLE_COEFFS(0),
.BLANK_OUTPUT(0),
.SYMMETRIC_COEFFS(1),
.SKIP_ZERO_COEFFS(1),
.USE_EMBEDDED_REGS_COEFFS(0)
) hbfir0 (
.clk(clk),
.reset(reset),
.clear(reset),
.s_axis_data_tdata(tdata_fir0),
.s_axis_data_tlast(i_tlast),
.s_axis_data_tvalid(i_tvalid),
.s_axis_data_tready(i_tready),
.m_axis_data_tdata(tdata_fir0_dec0),
.m_axis_data_tlast(tlast_fir0_dec0),
.m_axis_data_tvalid(tvalid_fir0_dec0),
.m_axis_data_tready(tready_fir0_dec0),
.s_axis_reload_tdata(18'd0),
.s_axis_reload_tvalid(1'b0),
.s_axis_reload_tlast(1'b0),
.s_axis_reload_tready()
);
// FIR filter for imag. part
axi_fir_filter #(
.IN_WIDTH(WIDTH),
.COEFF_WIDTH(COEFF_WIDTH),
.OUT_WIDTH(WIDTH),
.NUM_COEFFS(NUM_COEFFS),
.COEFFS_VEC(COEFFS_VEC),
.RELOADABLE_COEFFS(0),
.BLANK_OUTPUT(0),
.SYMMETRIC_COEFFS(1),
.SKIP_ZERO_COEFFS(1),
.USE_EMBEDDED_REGS_COEFFS(0)
) hbfir1 (
.clk(clk),
.reset(reset),
.clear(reset),
.s_axis_data_tdata(tdata_fir1),
.s_axis_data_tlast(i_tlast),
.s_axis_data_tvalid(i_tvalid),
.s_axis_data_tready(),
.m_axis_data_tdata(tdata_fir1_dec1),
.m_axis_data_tlast(tlast_fir1_dec1),
.m_axis_data_tvalid(tvalid_fir1_dec1),
.m_axis_data_tready(tready_fir1_dec1),
.s_axis_reload_tdata(18'd0),
.s_axis_reload_tvalid(1'b0),
.s_axis_reload_tlast(1'b0),
.s_axis_reload_tready()
);
// Decimator for real part
keep_one_in_n #(
.KEEP_FIRST(1),
.WIDTH(WIDTH),
.MAX_N(4)
) dec0 (
.clk(clk),
.reset(reset),
.vector_mode(1'b0),
.n(2),
.i_tdata(tdata_fir0_dec0),
.i_tlast(tlast_fir0_dec0),
.i_tvalid(tvalid_fir0_dec0),
.i_tready(tready_fir0_dec0),
.o_tdata(tdata_dec0),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready)
);
// Decimator for imag. part
keep_one_in_n #(
.KEEP_FIRST(1),
.WIDTH(WIDTH),
.MAX_N(4)
) dec1 (
.clk(clk),
.reset(reset),
.vector_mode(1'b0),
.n(2),
.i_tdata(tdata_fir1_dec1),
.i_tlast(tlast_fir1_dec1),
.i_tvalid(tvalid_fir1_dec1),
.i_tready(tready_fir1_dec1),
.o_tdata(tdata_dec1),
.o_tlast(),
.o_tvalid(),
.o_tready(o_tready)
);
assign o_tdata = {tdata_dec0, tdata_dec1};
endmodule
| 6.533817 |
module
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module axi_generator #(
parameter C_RATE = 125000000,
parameter C_PIXELS = 12
)(
// AXI Interface
input axi_clock,
input axi_reset,
output reg [31:0] axi_data = 32'd0,
output reg axi_write_en = 1'b0
);
localparam MESSAGE_COUNT = 36;
localparam [31:0] MESSAGES [0:MESSAGE_COUNT-1] = {
32'h00FF0000,
32'h0100FF00,
32'h020000FF,
32'h030000FF,
32'h0400FF00,
32'h05FF0000,
32'h0600ff00,
32'h070000ff,
32'h0800ff00,
32'h09ff0000,
32'h0A00ff00,
32'h0B0000ff,
32'h000ff000,
32'h01000ff0,
32'h02f0000f,
32'h030ff000,
32'h04000ff0,
32'h05f0000f,
32'h060ff000,
32'h07000ff0,
32'h08f0000f,
32'h090ff000,
32'h0Affff00,
32'h0B00ffff,
32'h00555555,
32'h01444444,
32'h02500050,
32'h03123456,
32'h04654321,
32'h05987654,
32'h06999911,
32'h07114466,
32'h08345345,
32'h09800080,
32'h0A00ffff,
32'h0Bff00ff
};
reg [31:0] cycle_counter = 32'd0;
reg [31:0] message_index = 32'd0;
always @(posedge axi_clock)begin
if(axi_reset == 1'b1)begin
axi_write_en <= 1'b0;
cycle_counter <= 32'd0;
end
else begin
axi_write_en <= 1'b0;
cycle_counter <= cycle_counter + 1'b1;
// send the next message every C_RATE cycles
if(cycle_counter == C_RATE)begin
axi_data <= MESSAGES[message_index];
axi_write_en <= 1'b1;
cycle_counter <= 32'd0;
message_index <= message_index + 1'b1;
if(message_index == MESSAGE_COUNT-1)begin
message_index <= 32'd0;
end
end
end
end
endmodule
| 8.13663 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_gpreg_clock_mon #(
parameter ID = 0,
parameter BUF_ENABLE = 0) (
// clock
input d_clk,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal registers
reg up_d_preset = 'd0;
reg up_d_resetn = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [31:0] up_d_count_s;
wire d_rst;
wire d_clk_g;
// decode block select
assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_d_preset <= 1'd1;
up_wack <= 'd0;
up_d_resetn <= 'd0;
end else begin
up_d_preset <= ~up_d_resetn;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_d_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'b0000: up_rdata <= {31'd0, up_d_resetn};
4'b0010: up_rdata <= up_d_count_s;
default: up_rdata <= 32'd0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_d_count_s),
.d_rst (d_rst),
.d_clk (d_clk_g));
ad_rst i_d_rst_reg (
.rst_async (up_d_preset),
.clk (d_clk_g),
.rstn (),
.rst (d_rst));
generate
if (BUF_ENABLE == 1) begin
BUFG i_bufg (
.I (d_clk),
.O (d_clk_g));
end else begin
assign d_clk_g = d_clk;
end
endgenerate
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_gpreg_io #(
parameter ID = 0) (
// gpio
output reg [31:0] up_gp_ioenb,
output reg [31:0] up_gp_out,
input [31:0] up_gp_in,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal registers
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_gp_ioenb <= {32{1'b1}};
up_gp_out <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_gp_ioenb <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_gp_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'b0000: up_rdata <= up_gp_ioenb;
4'b0001: up_rdata <= up_gp_out;
4'b0010: up_rdata <= up_gp_in;
default: up_rdata <= 32'd0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_hdmi_rx_tpm (
input hdmi_clk,
input hdmi_sof,
input hdmi_de,
input [15:0] hdmi_data,
output reg hdmi_tpm_oos);
wire [15:0] hdmi_tpm_lr_data_s;
wire hdmi_tpm_lr_mismatch_s;
wire [15:0] hdmi_tpm_fr_data_s;
wire hdmi_tpm_fr_mismatch_s;
reg [15:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_lr_mismatch = 'd0;
reg hdmi_tpm_fr_mismatch = 'd0;
// Limited range
assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[15:8] > 8'heb) ? 8'heb : hdmi_tpm_data[15:8]);
assign hdmi_tpm_lr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h10) ? 8'h10 :
((hdmi_tpm_data[ 7:0] > 8'heb) ? 8'heb : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_lr_mismatch_s = (hdmi_tpm_lr_data_s == hdmi_data) ? 1'b0 : 1'b1;
// Full range
assign hdmi_tpm_fr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[15:8] > 8'hfe) ? 8'hfe : hdmi_tpm_data[15:8]);
assign hdmi_tpm_fr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h01) ? 8'h01 :
((hdmi_tpm_data[ 7:0] > 8'hfe) ? 8'hfe : hdmi_tpm_data[ 7:0]);
assign hdmi_tpm_fr_mismatch_s = (hdmi_tpm_fr_data_s == hdmi_data) ? 1'b0 : 1'b1;
always @(posedge hdmi_clk) begin
if (hdmi_sof == 1'b1) begin
hdmi_tpm_data <= 16'd0;
hdmi_tpm_lr_mismatch <= 1'd0;
hdmi_tpm_fr_mismatch <= 1'd0;
hdmi_tpm_oos <= hdmi_tpm_lr_mismatch & hdmi_tpm_fr_mismatch;
end else if (hdmi_de == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
hdmi_tpm_lr_mismatch <= hdmi_tpm_lr_mismatch | hdmi_tpm_lr_mismatch_s;
hdmi_tpm_fr_mismatch <= hdmi_tpm_fr_mismatch | hdmi_tpm_fr_mismatch_s;
end
end
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
`timescale 1ns/100ps
module axi_hdmi_tx_es #(
parameter DATA_WIDTH = 32) (
// hdmi interface
input hdmi_clk,
input hdmi_hs_de,
input hdmi_vs_de,
input [(DATA_WIDTH-1):0] hdmi_data_de,
output reg [(DATA_WIDTH-1):0] hdmi_data);
localparam BYTE_WIDTH = DATA_WIDTH/8;
// internal registers
reg hdmi_hs_de_d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
reg hdmi_hs_de_2d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
reg hdmi_hs_de_3d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
reg hdmi_hs_de_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_5d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
// internal wires
wire [(DATA_WIDTH-1):0] hdmi_sav_s;
wire [(DATA_WIDTH-1):0] hdmi_eav_s;
// hdmi embedded sync insertion
assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
always @(posedge hdmi_clk) begin
hdmi_hs_de_d <= hdmi_hs_de;
case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
hdmi_hs_de_d, hdmi_hs_de})
5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}};
5'b10000: hdmi_data_d <= hdmi_eav_s;
default: hdmi_data_d <= hdmi_data_de;
endcase
hdmi_hs_de_2d <= hdmi_hs_de_d;
hdmi_data_2d <= hdmi_data_d;
hdmi_hs_de_3d <= hdmi_hs_de_2d;
hdmi_data_3d <= hdmi_data_2d;
hdmi_hs_de_4d <= hdmi_hs_de_3d;
hdmi_data_4d <= hdmi_data_3d;
hdmi_hs_de_5d <= hdmi_hs_de_4d;
hdmi_data_5d <= hdmi_data_4d;
case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d,
hdmi_hs_de_2d, hdmi_hs_de_d})
5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}};
5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}};
5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}};
5'b01111: hdmi_data <= hdmi_sav_s;
default: hdmi_data <= hdmi_data_5d;
endcase
end
endmodule
| 8.180735 |
module axi_hndshk_split (
ready_src,
valid_dst,
aclk,
aresetn,
valid_src,
ready_dst
);
parameter N_OUTPUTS = 2;
input aclk;
input aresetn;
input valid_src;
output logic ready_src;
output logic [N_OUTPUTS-1:0] valid_dst;
input [N_OUTPUTS-1:0] ready_dst;
logic [N_OUTPUTS-1:0] r_done, c_done;
always_comb begin
c_done = r_done;
ready_src = 0;
valid_dst = '0;
if (valid_src) begin
for (int i = 0; i < N_OUTPUTS; i++) begin
if (!c_done[i]) begin
valid_dst[i] = 1;
if (ready_dst[i]) c_done[i] = 1;
end
end
if (&c_done) begin
ready_src = 1;
c_done = 0;
end
end
end
always_ff @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
r_done <= 0;
end else begin
r_done <= c_done;
end
end
endmodule
| 6.624263 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module axi_hp_clk#(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_AXIHP = 6 // To get 150MHz for the reference clock
)(
input rst,
input clk_in,
output clk_axihp,
output locked_axihp
);
wire clkfb_axihp, clk_axihp_pre;
BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD), // 20
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_axihp), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(1'b0), // input
.clkout0(clk_axihp_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_axihp), // output
.locked(locked_axihp) // output
);
endmodule
| 8.081644 |
module axi_interconnect_v1_7_axic_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_interconnect_v1_7_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG)
);
endmodule
| 6.850312 |
module axi_interconnect_v1_7_axic_sample_cycle_ratio #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
) (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO - 1 : C_RATIO - 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *)reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY - 1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_carry #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(DI),
.S (S)
);
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b0),
.S (S)
);
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst (
.O (O),
.DI (CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1 (
.O (O),
.DI (CIN),
.SRI(I)
);
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b1),
.S (S_n)
);
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator_mask #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator_mask_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
assign m_local = M;
end
// Instantiate one carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_comparator_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
axi_interconnect_v1_7_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_mux #(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
) (
input wire [ C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [ C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl" || C_SEL_WIDTH < 3) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH+:C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
axi_interconnect_v1_7_mux #(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH - 1),
.C_DATA_WIDTH(C_DATA_WIDTH)
) mux_c_inst (
.S(S[C_SEL_WIDTH-2:0]),
.A(A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O(C)
);
// Upper half recursively.
axi_interconnect_v1_7_mux #(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH - 1),
.C_DATA_WIDTH(C_DATA_WIDTH)
) mux_d_inst (
.S(S[C_SEL_WIDTH-2:0]),
.A(A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O(D)
);
// Generate instantiated mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH; bit_cnt = bit_cnt + 1) begin : NUM
if (C_SEL_WIDTH == 4) begin : USE_F8
MUXF8 muxf8_inst (
.I0(C[bit_cnt]),
.I1(D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if (C_SEL_WIDTH == 3) begin : USE_F7
MUXF7 muxf7_inst (
.I0(C[bit_cnt]),
.I1(D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_ndeep_srl #(
parameter C_FAMILY = "none", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
) (
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam P_SRLASIZE = 5;
localparam P_NUMSRLS = (C_A_WIDTH > P_SRLASIZE) ? (2 ** (C_A_WIDTH - P_SRLASIZE)) : 1;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
for (i = 0; i < P_NUMSRLS; i = i + 1) begin : gen_srls
SRLC32E srl_inst (
.CLK(CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31(d_i[i+1])
);
end
endgenerate
// Instantiate MUX
generate
if (C_A_WIDTH > P_SRLASIZE) begin : gen_srl_mux
axi_interconnect_v1_7_nto1_mux #(
.C_RATIO (2 ** (C_A_WIDTH - P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH - P_SRLASIZE),
.C_DATAOUT_WIDTH(1),
.C_ONEHOT (0)
) srl_q_mux_inst (
.SEL_ONEHOT({2 ** (C_A_WIDTH - P_SRLASIZE) {1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_nto1_mux #(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
) (
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i = 1; i < C_RATIO; i = i + 1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i = 1; i < C_RATIO; i = i + 1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
| 6.850312 |
module axi_interconnect_v1_7_splitter #(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
) (
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
| 6.850312 |
module axi_interconnect_v1_7_wdata_mux #(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
) (
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [ C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [ C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [ C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [ C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [ C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder(input [C_SELECT_WIDTH-1:0] sel);
integer i;
begin
for (i = 0; i < C_NUM_SLAVE_SLOTS; i = i + 1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [ C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS > 1) begin : gen_wmux
// SI-side write command queue
axi_interconnect_v1_7_axic_reg_srl_fifo #(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
) wmux_aw_fifo (
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID(S_AVALID),
.S_READY(S_AREADY),
.M_MESG (m_select_enc),
.M_VALID(m_avalid),
.M_READY(m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
axi_interconnect_v1_7_mux_enc #(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH(C_WMESG_WIDTH)
) mux_w (
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE(1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
| 6.850312 |
module axi_interconnect_v1_7_wdata_router #(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of all data signals
parameter integer C_NUM_MASTER_SLOTS = 1, // Number of M_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of S_ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
) (
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [ C_WMESG_WIDTH-1:0] S_WMESG,
input wire S_WLAST,
input wire S_WVALID,
output wire S_WREADY,
// Master Data Ports
output wire [ C_WMESG_WIDTH-1:0] M_WMESG, // Broadcast to all MI-slots
output wire M_WLAST, // Broadcast to all MI-slots
output wire [C_NUM_MASTER_SLOTS-1:0] M_WVALID, // Per MI-slot
input wire [C_NUM_MASTER_SLOTS-1:0] M_WREADY, // Per MI-slot
// Address Arbiter Ports
input wire [ C_SELECT_WIDTH-1:0] S_ASELECT, // Target MI-slot index from SI-side AW command
input wire S_AVALID,
output wire S_AREADY
);
// Decode select input to 1-hot
function [C_NUM_MASTER_SLOTS-1:0] f_decoder(input [C_SELECT_WIDTH-1:0] sel);
integer i;
begin
for (i = 0; i < C_NUM_MASTER_SLOTS; i = i + 1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
//---------------------------------------------------------------------------
// Internal signal declarations
//---------------------------------------------------------------------------
wire [C_NUM_MASTER_SLOTS-1:0] m_select_hot;
wire [ C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
//---------------------------------------------------------------------------
// Router
//---------------------------------------------------------------------------
// SI-side write command queue
axi_interconnect_v1_7_axic_reg_srl_fifo #(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_USE_FULL (1)
) wrouter_aw_fifo (
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID(S_AVALID),
.S_READY(S_AREADY),
.M_MESG (m_select_enc),
.M_VALID(m_avalid),
.M_READY(m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// W-channel payload and LAST are broadcast to all MI-slot's W-mux
assign M_WMESG = S_WMESG;
assign M_WLAST = S_WLAST;
// Assert m_aready when last beat acknowledged by slave
assign m_aready = m_avalid & S_WVALID & S_WLAST & (|(M_WREADY & m_select_hot));
// M_WVALID is generated per MI-slot (including error handler at slot C_NUM_MASTER_SLOTS).
// The slot selected by the head of the queue (m_select_enc) is enabled.
assign M_WVALID = {C_NUM_MASTER_SLOTS{S_WVALID & m_avalid}} & m_select_hot;
// S_WREADY is muxed from the MI slot selected by the head of the queue (m_select_enc).
assign S_WREADY = m_avalid & (|(M_WREADY & m_select_hot));
endmodule
| 6.850312 |
module to control
the input and output data flow from axi interface.
NOTICE: if you want to migrate the decompressor to other platform or other interface. Only the decompressor
module is needed.
********************************************/
`timescale 1ns/1ps
module axi_io
#(
parameter C_M_AXI_ADDR_WIDTH=64,
C_M_AXI_DATA_WIDTH=512
)(
input clk,
input rst_n,
//////ports from axi_slave module
input start,
output done,
output idle,
output ready,
input[C_M_AXI_ADDR_WIDTH-1:0] src_addr, //address to read from host memory
input[C_M_AXI_ADDR_WIDTH-1:0] des_addr, ///address to write result to host memory
input[31:0] compression_length,
input[31:0] decompression_length,
/////////ports to read data from host memory
output dma_rd_req,
output[C_M_AXI_ADDR_WIDTH-1:0] dma_rd_addr,
output[7:0] dma_rd_len,
input dma_rd_req_ack,
input[C_M_AXI_DATA_WIDTH-1:0] dma_rd_data,
input dma_rd_data_valid,
output dma_rd_data_taken,
///////// ports to write data to host memory
output dma_wr_req,
output[C_M_AXI_ADDR_WIDTH-1:0] dma_wr_addr,
output[7:0] dma_wr_len,
input dma_wr_req_ack,
output[C_M_AXI_DATA_WIDTH-1:0] dma_wr_data,
output dma_wr_wvalid,
output[63:0] dma_wr_data_strobe,
output dma_wr_data_last,
input dma_wr_ready,
output dma_wr_bready,
input dma_wr_done
);
wire dec_almostfull;
/********************
reorder the input and output data
data for dma is in this order: byte n,byte n-1,...,byte 1,byte 0,
data for decompressor is in a reverse order: byte 0,byte 1,...byte n-1,byte n
********************/
wire[C_M_AXI_DATA_WIDTH-1:0] dec_data_in,dec_data_out;
wire[C_M_AXI_ADDR_WIDTH-1:0] dec_byte_valid;
genvar i;
generate
for(i=0;i<(C_M_AXI_DATA_WIDTH/8);i=i+1)begin
assign dec_data_in[i*8+7:i*8+0] = dma_rd_data[C_M_AXI_DATA_WIDTH-i*8-1:C_M_AXI_DATA_WIDTH-i*8-8];
assign dma_wr_data[C_M_AXI_DATA_WIDTH-i*8-1:C_M_AXI_DATA_WIDTH-i*8-8] = dec_data_out[i*8+7:i*8+0];
assign dma_wr_data_strobe[C_M_AXI_ADDR_WIDTH-1-i]=dec_byte_valid[i];
end
endgenerate
/*******************/
wire done_decompressor;
wire done_control;
decompressor d0(
.clk(clk),
.rst_n(rst_n),
.data(dec_data_in),
.valid_in(dma_rd_data_valid),
.start(start),
.compression_length({3'b0,compression_length}),
.decompression_length(decompression_length),
.wr_ready(dma_wr_ready),
.data_fifo_almostfull(dec_almostfull),
.done(done_decompressor),
.last(dma_wr_data_last),
.data_out(dec_data_out),
.byte_valid_out(dec_byte_valid),
.valid_out(dma_wr_wvalid)
);
io_control io_control0(
.clk(clk),
.rst_n(rst_n),
.src_addr(src_addr),
.rd_req(dma_rd_req),
.rd_req_ack(dma_rd_req_ack),
.rd_len(dma_rd_len),
.done_i(done_decompressor),
.start(start),
.idle(idle),
.ready(ready),
.rd_address(dma_rd_addr),
.done_out(done_control),
.wr_valid(dma_wr_wvalid),
.wr_ready(dma_wr_ready),
.des_addr(des_addr),
.wr_req(dma_wr_req),
.wr_req_ack(dma_wr_req_ack),
.wr_len(dma_wr_len),
.wr_address(dma_wr_addr),
.bready(dma_wr_bready),
.bresp(dma_wr_done),
.decompression_length(decompression_length),
.compression_length({3'b0,compression_length})
);
assign dma_rd_data_taken = ~dec_almostfull;
assign done = done_decompressor && done_control;
endmodule
| 7.851287 |
module axi_istr_bfm (
input wire clock_i, // Clock Input
input wire reset_i, // Reset Input
// ===============================================================================
// AXI 4 Stream Transmit Channel
output reg [3:0] tid_o,
output wire tvalid_o, // Receive Data channel valid
input wire tready_i, // Receive Data channel ready
output wire tlast_o, // Receive Data channel last word
output wire [31:0] tdata_o // Receive Data channel data
);
// ---------------------------------------------------------------------------------------
// Local Parameters
localparam BUF_WI_L2 = 12; // Number of bits to address buffer depth
localparam NO_CH_L2 = 4;
localparam buf_size = (1 << NO_CH_L2) * (1 << BUF_WI_L2); // Number of buffers * Buffer depth
// ---------------------------------------------------------------------------------------
// Wires and Registers
reg [15:0] rdy_del;
initial rdy_del = 0;
reg [31:0] mem[0:buf_size];
reg [31:0] last_cnt, dcnt;
reg [15:0] tvalid_r;
wire [15:0] tvalid_d;
reg en = 0;
initial tid_o = 0;
assign tdata_o = tvalid_o ? mem[{tid_o[3:0], dcnt[BUF_WI_L2-1:0]}] : 32'hBAD1_XXXX;
assign tlast_o = (dcnt == last_cnt);
always @(posedge clock_i) if (tvalid_o && tready_i && tlast_o) en <= #1 1'b0;
always @(posedge clock_i)
if (reset_i) dcnt <= #1 32'h0;
else if (tvalid_o && tready_i) dcnt <= #1 dcnt + 32'h01;
always @(posedge clock_i)
if (reset_i) tvalid_r <= #1 16'h0;
else if (tvalid_o && tready_i) tvalid_r <= #1 16'h0;
else tvalid_r <= #1{tvalid_r[14:0], tready_i & !tvalid_o & en};
assign tvalid_d = {tvalid_r[14:0], 1'b1};
assign tvalid_o = tvalid_d[rdy_del] & en;
task init;
input id;
input mode;
input count;
integer i, count, mode, id;
reg [31:0] tmp;
begin
@(posedge clock_i);
#1;
dcnt = 0;
en = 1;
tvalid_r = 0;
tid_o = id;
last_cnt = count - 1;
if (mode != 99)
for (i = 0; i < count; i = i + 1) begin
tmp = $random;
case (mode)
default: mem[{tid_o[3:0], i[BUF_WI_L2-1:0]}] = i + 1;
1: mem[{tid_o[3:0], i[BUF_WI_L2-1:0]}] = tmp;
2: mem[{tid_o[3:0], i[BUF_WI_L2-1:0]}] = {tid_o[3:0], i[27:0]};
3: mem[{tid_o[3:0], i[BUF_WI_L2-1:0]}] = {tid_o[3:0], tmp[27:0]};
4: mem[{tid_o[3:0], i[BUF_WI_L2-1:0]}] = {16'h00, 4'h0, tid_o[3:0], i[7:0]};
endcase
end
@(posedge clock_i);
while (en) @(posedge clock_i);
@(posedge clock_i);
end
endtask
endmodule
| 7.065561 |
module axi_join #(
parameter INPUTS = 2
) (
input [INPUTS-1:0] i_tlast,
input [INPUTS-1:0] i_tvalid,
output [INPUTS-1:0] i_tready,
output o_tlast,
output o_tvalid,
input o_tready
);
wire all_here = &i_tvalid;
assign o_tvalid = all_here;
assign o_tlast = |i_tlast;
assign i_tready = {INPUTS{o_tready & all_here}};
endmodule
| 7.584888 |
module axi_jtaguart (
input wire clock
, input wire reset
, output wire tx_ready
, input wire tx_valid
, input wire [7:0] tx_data
, input wire rx_ready
, output wire rx_valid
, output wire [7:0] rx_data
);
wire jtaguart_idle_o;
alt_jtag_atlantic jtag_uart_0_alt_jtag_atlantic (
.clk (clock)
, .rst_n(!reset)
, .r_dat(tx_data)
, .r_val(tx_valid)
, .r_ena(tx_ready)
, .t_dat (rx_data)
, .t_dav (rx_ready)
, .t_ena (rx_valid)
, .t_pause(jtaguart_idle_o)
);
defparam jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
endmodule
| 7.190045 |
module axi_lite_wrapper #(
// Users to add parameters here
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_LENGTH_WIDTH = 14,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 64,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
) (
// Users to add ports here
input dataload_ready,
input tile_done,
input op_done,
input AXI4_cmdack,
input AXI4_error,
input [3:0] FSM_comp,
input [3:0] FSM_data,
output rst,
output axi_rst,
output config_load,
output config_done,
output op_go,
output psum_split_condense,
output padding,
output maxpooling,
output relu,
output tile_order_first,
output tile_order_last,
output [5:0] ifmapR,
output [5:0] ifmapC,
output [5:0] ofmapR,
output [5:0] ofmapC,
output [2:0] kernelR,
output [2:0] kernelC,
output [9:0] inchannel,
output [4:0] outchannel,
output [1:0] bias_len,
output wght_load,
output ifmap_load,
output ofmap_offload,
output [C_M_AXI_ADDR_WIDTH-1:0] ctrl_addr,
output [C_LENGTH_WIDTH-1:3] ctrl_mst_length,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
axi_light_slv_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axi_light_slv_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.dataload_ready(dataload_ready),
.tile_done(tile_done),
.op_done(op_done),
.AXI4_cmdack(AXI4_cmdack),
.AXI4_error(AXI4_error),
.FSM_comp(FSM_comp),
.FSM_data(FSM_data),
.rst(rst),
.axi_rst(axi_rst),
.config_load(config_load),
.config_done(config_done),
.op_go(op_go),
.psum_split_condense(psum_split_condense),
.padding(padding),
.maxpooling(maxpooling),
.relu(relu),
.tile_order_first(tile_order_first),
.tile_order_last(tile_order_last),
.ifmapR(ifmapR),
.ifmapC(ifmapC),
.ofmapR(ofmapR),
.ofmapC(ofmapC),
.kernelR(kernelR),
.kernelC(kernelC),
.inchannel(inchannel),
.outchannel(outchannel),
.bias_len(bias_len),
.wght_load(wght_load),
.ifmap_load(ifmap_load),
.ofmap_offload(ofmap_offload),
.ctrl_addr(ctrl_addr),
.ctrl_mst_length(ctrl_mst_length)
);
// Add user logic here
// User logic ends
endmodule
| 6.785077 |
module axi_lite_generic_reg #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
) (
// Users to add ports here
input wire [(1<<(C_S00_AXI_ADDR_WIDTH-2))*C_S00_AXI_DATA_WIDTH-1:0] GPIO_IN,
output wire [(1<<(C_S00_AXI_ADDR_WIDTH-2))-1:0] GPIO_STROBES,
output wire [C_S00_AXI_DATA_WIDTH-1:0] GPIO_OUT,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
axi_lite_generic_reg_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) axi_lite_generic_reg_S00_AXI_inst (
.GPIO_IN(GPIO_IN),
.GPIO_STROBES(GPIO_STROBES),
.GPIO_OUT(GPIO_OUT),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.986845 |
module AXI_LITE_master_IP_v1_0 #(
// Users to add parameters here
parameter REG_DATA_VALUE_0 = 32'h00000000,
parameter REG_DATA_VALUE_1 = 32'h00000000,
parameter REG_DATA_VALUE_2 = 32'h00000000,
parameter REG_DATA_VALUE_3 = 32'h00000000,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_TRANSACTIONS_NUM = 4
) (
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_init_axi_txn,
output wire m00_axi_error,
output wire m00_axi_txn_done,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
AXI_LITE_master_IP_v1_0_M00_AXI #(
.REG_DATA_VALUE_0(REG_DATA_VALUE_0),
.REG_DATA_VALUE_1(REG_DATA_VALUE_1),
.REG_DATA_VALUE_2(REG_DATA_VALUE_2),
.REG_DATA_VALUE_3(REG_DATA_VALUE_3),
.C_M_START_DATA_VALUE(C_M00_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M00_AXI_TRANSACTIONS_NUM)
) AXI_LITE_master_IP_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.ERROR(m00_axi_error),
.TXN_DONE(m00_axi_txn_done),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.642195 |
module axi_lite_master #(
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
) (
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
endmodule
| 6.775936 |
module axi_lite_slave_int #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 4
) (
// Users to add parameters here
output [ C_S_AXI_DATA_WIDTH-1:0] WDATA_O,
input [ C_S_AXI_DATA_WIDTH-1:0] RDATA_I,
output WENA_O,
output RENA_O,
output [ C_S_AXI_ADDR_WIDTH -1:0] RADDR_O,
output [ C_S_AXI_ADDR_WIDTH -1:0] WADDR_O,
// AXI4-Lite Slave Port
input S_AXI_ACLK,
input S_AXI_ARESETN,
input [ C_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
output reg S_AXI_AWREADY,
input [ C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output reg S_AXI_WREADY,
output [ 1:0] S_AXI_BRESP,
output reg S_AXI_BVALID,
input S_AXI_BREADY,
input [ C_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input S_AXI_ARVALID,
output reg S_AXI_ARREADY,
output [ C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output [ 1:0] S_AXI_RRESP,
output reg S_AXI_RVALID,
input S_AXI_RREADY
);
localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH / 32) + 1;
localparam EXTRA_ZEROS = {ADDR_LSB{1'b0}};
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] wdata_r;
integer byte_index;
assign S_AXI_BRESP = 2'b00;
assign S_AXI_RRESP = 2'b00;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
S_AXI_AWREADY <= 1'b0;
end else begin
if ((S_AXI_AWREADY == 1'b0 && S_AXI_AWVALID == 1'b1)) S_AXI_AWREADY <= 1'b1;
else S_AXI_AWREADY <= 1'b0;
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
S_AXI_WREADY <= 1'b0;
end else begin
if ((S_AXI_WREADY == 1'b0 && S_AXI_WVALID == 1'b1)) S_AXI_WREADY <= 1'b1;
else S_AXI_WREADY <= 1'b0;
end
end
assign slv_reg_wren = S_AXI_WREADY & S_AXI_WVALID;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
S_AXI_BVALID <= 1'b0;
end else begin
if ((S_AXI_WREADY == 1'b1 && S_AXI_WVALID == 1'b1 && S_AXI_BVALID == 1'b0))
S_AXI_BVALID <= 1'b1;
else if ((S_AXI_BREADY == 1'b1 && S_AXI_BVALID == 1'b1)) S_AXI_BVALID <= 1'b0;
end
end
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
S_AXI_ARREADY <= 1'b0;
end else begin
if ((S_AXI_ARREADY == 1'b0 && S_AXI_ARVALID == 1'b1)) S_AXI_ARREADY <= 1'b1;
else S_AXI_ARREADY <= 1'b0;
end
end
assign slv_reg_rden = S_AXI_ARREADY & S_AXI_ARVALID;
always @(posedge S_AXI_ACLK) begin
if (S_AXI_ARESETN == 1'b0) begin
S_AXI_RVALID <= 1'b0;
end else begin
if ((S_AXI_ARREADY == 1'b1 && S_AXI_ARVALID == 1'b1 && S_AXI_RVALID == 1'b0))
S_AXI_RVALID <= 1'b1;
else if ((S_AXI_RVALID == 1'b1 && S_AXI_RREADY == 1'b1)) S_AXI_RVALID <= 1'b0;
end
end
assign S_AXI_RDATA = RDATA_I;
assign RADDR_O = {S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1 : ADDR_LSB], EXTRA_ZEROS};
assign WADDR_O = {S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH-1 : ADDR_LSB], EXTRA_ZEROS};
assign WDATA_O = S_AXI_WDATA;
assign RENA_O = slv_reg_rden;
assign WENA_O = slv_reg_wren;
endmodule
| 7.923453 |
module AXI_Lite_test (
ACLK,
ARESETN
);
input ACLK;
input ARESETN;
wire ACLK_1;
wire ARESETN_1;
wire [31:0] axi_lite_master_0_M_AXI_ARADDR;
wire axi_lite_master_0_M_AXI_ARREADY;
wire axi_lite_master_0_M_AXI_ARVALID;
wire [31:0] axi_lite_master_0_M_AXI_AWADDR;
wire axi_lite_master_0_M_AXI_AWREADY;
wire axi_lite_master_0_M_AXI_AWVALID;
wire axi_lite_master_0_M_AXI_BREADY;
wire [1:0] axi_lite_master_0_M_AXI_BRESP;
wire axi_lite_master_0_M_AXI_BVALID;
wire [31:0] axi_lite_master_0_M_AXI_RDATA;
wire axi_lite_master_0_M_AXI_RREADY;
wire [1:0] axi_lite_master_0_M_AXI_RRESP;
wire axi_lite_master_0_M_AXI_RVALID;
wire [31:0] axi_lite_master_0_M_AXI_WDATA;
wire axi_lite_master_0_M_AXI_WREADY;
wire [3:0] axi_lite_master_0_M_AXI_WSTRB;
wire axi_lite_master_0_M_AXI_WVALID;
assign ACLK_1 = ACLK;
assign ARESETN_1 = ARESETN;
AXI_Lite_test_axi_lite_master_0_0 axi_lite_master_0 (
.M_AXI_ACLK(ACLK_1),
.M_AXI_ARADDR(axi_lite_master_0_M_AXI_ARADDR),
.M_AXI_ARESETN(ARESETN_1),
.M_AXI_ARREADY(axi_lite_master_0_M_AXI_ARREADY),
.M_AXI_ARVALID(axi_lite_master_0_M_AXI_ARVALID),
.M_AXI_AWADDR(axi_lite_master_0_M_AXI_AWADDR),
.M_AXI_AWREADY(axi_lite_master_0_M_AXI_AWREADY),
.M_AXI_AWVALID(axi_lite_master_0_M_AXI_AWVALID),
.M_AXI_BREADY(axi_lite_master_0_M_AXI_BREADY),
.M_AXI_BRESP(axi_lite_master_0_M_AXI_BRESP),
.M_AXI_BVALID(axi_lite_master_0_M_AXI_BVALID),
.M_AXI_RDATA(axi_lite_master_0_M_AXI_RDATA),
.M_AXI_RREADY(axi_lite_master_0_M_AXI_RREADY),
.M_AXI_RRESP(axi_lite_master_0_M_AXI_RRESP),
.M_AXI_RVALID(axi_lite_master_0_M_AXI_RVALID),
.M_AXI_WDATA(axi_lite_master_0_M_AXI_WDATA),
.M_AXI_WREADY(axi_lite_master_0_M_AXI_WREADY),
.M_AXI_WSTRB(axi_lite_master_0_M_AXI_WSTRB),
.M_AXI_WVALID(axi_lite_master_0_M_AXI_WVALID)
);
AXI_Lite_test_axi_lite_slave_0_0 axi_lite_slave_0 (
.S_AXI_ACLK(ACLK_1),
.S_AXI_ARADDR(axi_lite_master_0_M_AXI_ARADDR[4:0]),
.S_AXI_ARESETN(ARESETN_1),
.S_AXI_ARREADY(axi_lite_master_0_M_AXI_ARREADY),
.S_AXI_ARVALID(axi_lite_master_0_M_AXI_ARVALID),
.S_AXI_AWADDR(axi_lite_master_0_M_AXI_AWADDR[4:0]),
.S_AXI_AWREADY(axi_lite_master_0_M_AXI_AWREADY),
.S_AXI_AWVALID(axi_lite_master_0_M_AXI_AWVALID),
.S_AXI_BREADY(axi_lite_master_0_M_AXI_BREADY),
.S_AXI_BRESP(axi_lite_master_0_M_AXI_BRESP),
.S_AXI_BVALID(axi_lite_master_0_M_AXI_BVALID),
.S_AXI_RDATA(axi_lite_master_0_M_AXI_RDATA),
.S_AXI_RREADY(axi_lite_master_0_M_AXI_RREADY),
.S_AXI_RRESP(axi_lite_master_0_M_AXI_RRESP),
.S_AXI_RVALID(axi_lite_master_0_M_AXI_RVALID),
.S_AXI_WDATA(axi_lite_master_0_M_AXI_WDATA),
.S_AXI_WREADY(axi_lite_master_0_M_AXI_WREADY),
.S_AXI_WSTRB(axi_lite_master_0_M_AXI_WSTRB),
.S_AXI_WVALID(axi_lite_master_0_M_AXI_WVALID)
);
endmodule
| 6.506887 |
module AXI_Lite_test_axi_lite_master_0_0 (
WCOMPLETE,
RCOMPLETE,
M_AXI_ACLK,
M_AXI_ARESETN,
M_AXI_AWADDR,
M_AXI_AWPROT,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BRESP,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARADDR,
M_AXI_ARPROT,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RVALID,
M_AXI_RREADY
);
output wire WCOMPLETE;
output wire RCOMPLETE;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK" *)
input wire M_AXI_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXI_ARESETN RST" *)
input wire M_AXI_ARESETN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] M_AXI_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] M_AXI_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire M_AXI_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire M_AXI_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] M_AXI_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] M_AXI_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire M_AXI_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire M_AXI_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] M_AXI_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire M_AXI_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire M_AXI_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] M_AXI_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] M_AXI_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire M_AXI_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire M_AXI_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] M_AXI_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] M_AXI_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire M_AXI_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire M_AXI_RREADY;
axi_lite_master #(
.C_TRANSACTIONS_NUM(4)
) inst (
.WCOMPLETE(WCOMPLETE),
.RCOMPLETE(RCOMPLETE),
.M_AXI_ACLK(M_AXI_ACLK),
.M_AXI_ARESETN(M_AXI_ARESETN),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
endmodule
| 6.506887 |
module AXI_Lite_test_axi_lite_slave_0_0 (
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_RREADY
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *)
input wire S_AXI_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *)
input wire S_AXI_ARESETN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [4 : 0] S_AXI_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire S_AXI_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire S_AXI_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] S_AXI_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] S_AXI_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire S_AXI_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire S_AXI_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] S_AXI_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire S_AXI_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire S_AXI_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [4 : 0] S_AXI_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire S_AXI_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire S_AXI_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] S_AXI_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] S_AXI_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire S_AXI_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire S_AXI_RREADY;
axi_lite_slave inst (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
endmodule
| 6.506887 |
module AXI_Lite_test_wrapper (
ACLK,
ARESETN
);
input ACLK;
input ARESETN;
wire ACLK;
wire ARESETN;
AXI_Lite_test AXI_Lite_test_i (
.ACLK(ACLK),
.ARESETN(ARESETN)
);
endmodule
| 6.506887 |
module axi_lite_write ( /*AUTOARG*/
// Outputs
wready,
bvalid,
bresp,
reg_data_addr,
reg_data_write,
reg_data,
// Inputs
clk,
reset,
awvalid,
awready,
wvalid,
wdata,
bready
);
parameter C_ADDR_WIDTH = 10;
parameter C_DATA_WIDTH = 32;
input clk;
input reset;
input awvalid;
input awready;
input wvalid;
output wready;
input [C_DATA_WIDTH-1:0] wdata;
output bvalid;
input bready;
output [1:0] bresp;
output [C_ADDR_WIDTH-1:0] reg_data_addr;
output reg_data_write;
output [C_DATA_WIDTH-1:0] reg_data;
/***************************************************************************/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [C_DATA_WIDTH-1:0] reg_data;
reg [C_ADDR_WIDTH-1:0] reg_data_addr;
reg reg_data_write;
// End of automatics
/***************************************************************************/
// HandShake signals
wire awhandshake;
wire whandshake;
wire bhandshake;
assign awhandshake = awvalid & awready;
assign whandshake = wvalid & wready;
assign bhandshake = bvalid & bready;
// wchannel only accept data after aw handshake
reg wready_i;
assign wready = wready_i;
always @(posedge clk) begin
if (reset) begin
wready_i <= #1 1'b0;
end else begin
wready_i <= #1 (awhandshake | wready_i) & ~whandshake;
end
end // always @ (posedge clk)
// Data is registered but not latched (like awaddr) since is used a cycle later
always @(posedge clk) begin
reg_data <= #1 wdata;
reg_data_write <= #1 whandshake;
end
// bresponse is send after success w handshake
reg bvalid_i;
assign bvalid = bvalid_i;
assign bresp = 2'b0; // Okay
always @(posedge clk) begin
if (reset) begin
bvalid_i <= #1 1'b0;
end else begin
bvalid_i <= #1 (whandshake | bvalid_i) & ~bhandshake;
end
end // always @ (posedge clk)
endmodule
| 6.724579 |
module axi_logpwr (
input clk,
input reset,
input [31:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [15:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
// Signals
reg ready;
reg valid_1;
wire valid_12;
wire last_12;
wire [31:0] rng;
wire [15:0] in_real_0;
wire [15:0] in_imag_0;
wire [15:0] out_logpwr_12;
wire [16:0] fifo_di;
wire [16:0] fifo_do;
wire fifo_wren;
wire fifo_afull;
wire fifo_rden;
wire fifo_empty;
// Input control
assign in_real_0 = i_tdata[31:16];
assign in_imag_0 = i_tdata[15:0];
always @(posedge clk) begin
ready <= ~fifo_afull | o_tready;
valid_1 <= i_tvalid & ready;
end
assign i_tready = ready;
// Delays
delay_bit #(11) dl_valid (
valid_1,
valid_12,
clk
);
delay_bit #(12) dl_last (
i_tlast,
last_12,
clk
);
// RNG Instance
rng rng_I (
.out(rng),
.clk(clk),
.rst(reset)
);
// logpwr Instance
f15_logpwr logpwr_I (
.in_real_0(in_real_0),
.in_imag_0(in_imag_0),
.out_12(out_logpwr_12),
.rng(rng),
.clk(clk),
.rst(reset)
);
// Output FIFO
assign fifo_di = {last_12, out_logpwr_12};
assign fifo_wren = {valid_12};
fifo_srl #(
.WIDTH(17),
.LOG2_DEPTH(6),
.AFULL_LEVEL(49)
) fifo_I (
.di(fifo_di),
.wren(fifo_wren),
.afull(fifo_afull),
.do(fifo_do),
.rden(fifo_rden),
.empty(fifo_empty),
.clk(clk),
.rst(reset)
);
assign o_tdata = fifo_do[15:0];
assign o_tlast = fifo_do[16];
assign o_tvalid = ~fifo_empty;
assign fifo_rden = ~fifo_empty & o_tready;
endmodule
| 6.533255 |
module axi_loopback #(
parameter WIDTH = 64
) (
input clk,
input reset,
// Input AXIS
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
// Output AXIS
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] fifoin_tdata, fifoout_tdata, dmux_tdata;
wire fifoin_tlast, dmux_tlast;
wire fifoin_tvalid, dmux_tvalid;
wire fifoin_tready, dmux_tready;
// Since most real endpoints go via Demux4 place one in here to look for bugs.
axi_demux4 #(
.ACTIVE_CHAN(4'b0001),
.WIDTH(WIDTH)
) demux (
.clk(clk),
.reset(reset),
.clear(1'b0),
.header(),
.dest(2'b00),
.i_tdata(i_tdata),
.i_tlast(i_tlast),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o0_tdata(dmux_tdata),
.o0_tlast(dmux_tlast),
.o0_tvalid(dmux_tvalid),
.o0_tready(dmux_tready),
.o1_tdata(),
.o1_tlast(),
.o1_tvalid(),
.o1_tready(1'b1),
.o2_tdata(),
.o2_tlast(),
.o2_tvalid(),
.o2_tready(1'b1),
.o3_tdata(),
.o3_tlast(),
.o3_tvalid(),
.o3_tready(1'b1)
);
axi_fifo_short #(
.WIDTH(WIDTH + 1)
) axi_fifo_short1 (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata({dmux_tlast, dmux_tdata}),
.i_tvalid(dmux_tvalid),
.i_tready(dmux_tready),
.o_tdata({fifoin_tlast, fifoin_tdata}),
.o_tvalid(fifoin_tvalid),
.o_tready(fifoin_tready),
.space(),
.occupied()
);
reg header;
always @(posedge clk) begin
if (reset) begin
header <= 1'b1;
end else if (header) begin
if (fifoin_tvalid & fifoin_tready & ~fifoin_tlast) header <= 1'b0;
end else begin
if (fifoin_tvalid & fifoin_tready & fifoin_tlast) header <= 1'b1;
end
end
assign fifoout_tdata = header ?
{fifoin_tdata[63:32] ,fifoin_tdata[15:0],fifoin_tdata[31:16]} :
fifoin_tdata;
axi_fifo_short #(
.WIDTH(WIDTH + 1)
) axi_fifo_short2 (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata({fifoin_tlast, fifoout_tdata}),
.i_tvalid(fifoin_tvalid),
.i_tready(fifoin_tready),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endmodule
| 7.836661 |
module axi_master32_stub (
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [31:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [31:0] M2S_AXI_WDATA,
output [3:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 32'b0;
assign M2S_AXI_WSTRB = 4'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule
| 7.901287 |
module axi_master_generic ( /*AUTOARG*/
// Outputs
awid,
awadr,
awlen,
awsize,
awburst,
awlock,
awcache,
awprot,
awvalid,
wid,
wrdata,
wstrb,
wlast,
wvalid,
bid,
bresp,
bvalid,
arid,
araddr,
arlen,
arsize,
arlock,
arcache,
arprot,
arvalid,
rready,
// Inputs
aclk,
aresetn,
awready,
wready,
bready,
arready,
rid,
rdata,
rresp,
rlast,
rvalid
);
//
// Global Signals
//
input wire aclk;
input wire aresetn; //Active LOW
//
// Write Address Channel
//
output reg [3:0] awid; // Address Write ID
output reg [31:0] awadr; // Write Address
output reg [3:0] awlen; // Burst Length
output reg [2:0] awsize; // Burst Size
output reg [1:0] awburst; // Burst Type
output reg [1:0] awlock; // Lock Type
output reg [3:0] awcache; // Cache Type
output reg [2:0] awprot; // Protection Type
output reg awvalid; // Write Address Valid
input wire awready; // Write Address Ready
//
// Write Data Channel
//
output reg [3:0] wid; // Write ID
output reg [31:0] wrdata; // Write Data
output reg [3:0] wstrb; // Write Strobes
output reg wlast; // Write Last
output reg wvalid; // Write Valid
input wire wready; // Write Ready
//
// Write Response CHannel
//
output reg [3:0] bid; // Response ID
output reg [1:0] bresp; // Write Response
output reg bvalid; // Write Response Valid
input wire bready; // Response Ready
//
// Read Address Channel
//
output reg [3:0] arid; // Read Address ID
output reg [31:0] araddr; // Read Address
output reg [3:0] arlen; // Burst Length
output reg [2:0] arsize; // Burst Size
output reg [1:0] arlock; // Lock Type
output reg [3:0] arcache; // Cache Type
output reg [2:0] arprot; // Protection Type
output reg arvalid; // Read Address Valid
input wire arready; // Read Address Ready
input wire [3:0] rid; // Read ID
input wire [31:0] rdata; // Read Data
input wire [1:0] rresp; // Read Response
input wire rlast; // Read Last
input wire rvalid; // Read Valid
output reg rready; // Read Ready
endmodule
| 7.371913 |
module axi_master_ic_dec (
M0_AADDR,
M1_AADDR,
M2_AADDR,
M0_AID,
M1_AID,
M2_AID,
M0_ASLV,
M1_ASLV,
M2_ASLV,
M0_AIDOK,
M1_AIDOK,
M2_AIDOK
);
input [32-1:0] M0_AADDR;
input [32-1:0] M1_AADDR;
input [32-1:0] M2_AADDR;
input [4-1:0] M0_AID;
input [4-1:0] M1_AID;
input [4-1:0] M2_AID;
output [1-1:0] M0_ASLV;
output [1-1:0] M1_ASLV;
output [1-1:0] M2_ASLV;
output M0_AIDOK;
output M1_AIDOK;
output M2_AIDOK;
parameter DEC_MSB = 32 - 1;
parameter DEC_LSB = 32 - 1;
reg [ 1-1:0] M0_ASLV;
reg [ 1-1:0] M1_ASLV;
reg [ 1-1:0] M2_ASLV;
reg M0_AIDOK;
reg M1_AIDOK;
reg M2_AIDOK;
wire [DEC_MSB:DEC_LSB] M0_AADDR_DEC;
wire [DEC_MSB:DEC_LSB] M1_AADDR_DEC;
wire [DEC_MSB:DEC_LSB] M2_AADDR_DEC;
assign M0_AADDR_DEC = M0_AADDR[DEC_MSB:DEC_LSB];
assign M1_AADDR_DEC = M1_AADDR[DEC_MSB:DEC_LSB];
assign M2_AADDR_DEC = M2_AADDR[DEC_MSB:DEC_LSB];
always @(M0_AADDR or M0_AIDOK) begin
case (M0_AIDOK)
1'b1: M0_ASLV = 1'd0;
default: M0_ASLV = 1'd0;
endcase
end
always @(M0_AID) begin
case (M0_AID[4-1:0])
4'b0011: M0_AIDOK = 1'b1;
default: M0_AIDOK = 1'b0;
endcase
end
always @(M1_AADDR or M1_AIDOK) begin
case (M1_AIDOK)
1'b1: M1_ASLV = 1'd0;
default: M1_ASLV = 1'd0;
endcase
end
always @(M1_AID) begin
case (M1_AID[4-1:0])
4'b0010: M1_AIDOK = 1'b1;
default: M1_AIDOK = 1'b0;
endcase
end
always @(M2_AADDR or M2_AIDOK) begin
case (M2_AIDOK)
1'b1: M2_ASLV = 1'd0;
default: M2_ASLV = 1'd0;
endcase
end
always @(M2_AID) begin
case (M2_AID[4-1:0])
4'b1010: M2_AIDOK = 1'b1;
default: M2_AIDOK = 1'b0;
endcase
end
endmodule
| 6.749778 |
module axi_master_read_stub (
output M2S_AXI_ACLK,
//Read M2S_AXI_transation
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read M2S_AXI_transation
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
endmodule
| 8.03225 |
module axi_master_stub (
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
//Read Transaction
assign M2S_AXI_ARVALID = 1'b0;
assign M2S_AXI_ARADDR = 32'b0;
assign M2S_AXI_ARBURST = 2'b0;
assign M2S_AXI_ARLEN = 4'b0;
assign M2S_AXI_ARSIZE = 2'b0;
assign M2S_AXI_RREADY = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 32'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 64'b0;
assign M2S_AXI_WSTRB = 8'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule
| 7.836666 |
module axi_master_write_stub (
output M2S_AXI_ACLK,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 33'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 64'b0;
assign M2S_AXI_WSTRB = 8'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule
| 7.00851 |
module axi_mcb_simple_fifo #(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
) (
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY - 1'b1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = C_FULL - 1'b1;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [ C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
reg full_r;
reg empty_r;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH - 1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if (wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
///////////////////////////////////////
always @(posedge clk) begin
if (rst) begin
full_r <= 1'b0;
end else if (wr_en & ~rd_en) begin
full_r <= a_full;
end else if (~wr_en & rd_en) begin
full_r <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
empty_r <= 1'b1;
end else if (~wr_en & rd_en) begin
empty_r <= a_empty;
end else if (wr_en & ~rd_en) begin
empty_r <= 1'b0;
end
end
assign full = full_r;
assign empty = empty_r;
assign a_full = (cnt_read == C_FULL);
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule
| 7.265372 |
module mig_7series_v4_2_axi_mc_simple_fifo #(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
) (
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY - 1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL - 1 : C_FULL - (C_DEPTH / 8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory[C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH - 1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if (wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule
| 7.091312 |
module axi_mem_wrapper #(
parameter ID_WIDTH = 0,
parameter MEM_SIZE = 0,
parameter mem_clear = 0,
parameter INIT_FILE = ""
) (
input wire clk,
input wire rst_n,
input wire [ID_WIDTH-1:0] i_awid,
input wire [ 31:0] i_awaddr,
input wire [ 7:0] i_awlen,
input wire [ 2:0] i_awsize,
input wire [ 1:0] i_awburst,
input wire i_awvalid,
output wire o_awready,
input wire [ID_WIDTH-1:0] i_arid,
input wire [ 31:0] i_araddr,
input wire [ 7:0] i_arlen,
input wire [ 2:0] i_arsize,
input wire [ 1:0] i_arburst,
input wire i_arvalid,
output wire o_arready,
input wire [63:0] i_wdata,
input wire [ 7:0] i_wstrb,
input wire i_wlast,
input wire i_wvalid,
output wire o_wready,
output wire [ID_WIDTH-1:0] o_bid,
output wire [ 1:0] o_bresp,
output wire o_bvalid,
input wire i_bready,
output wire [ID_WIDTH-1:0] o_rid,
output wire [ 63:0] o_rdata,
output wire [ 1:0] o_rresp,
output wire o_rlast,
output wire o_rvalid,
input wire i_rready
);
localparam AW = $clog2(MEM_SIZE);
wire [AW-1:2] wb_adr;
wire [ 31:0] wb_dat;
wire [ 3:0] wb_sel;
wire wb_we;
wire wb_cyc;
wire wb_stb;
reg wb_ack;
wire [ 31:0] wb_rdt;
axi2wb #(
.AW(AW),
.IW(ID_WIDTH)
) axi2wb (
.i_clk (clk),
.i_rst (~rst_n),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat),
.o_wb_sel(wb_sel),
.o_wb_we (wb_we),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_rdt(wb_rdt),
.i_wb_ack(wb_ack),
.i_wb_err(1'b0),
.i_awaddr (i_awaddr[AW-1:0]),
.i_awid (i_awid),
.i_awvalid(i_awvalid),
.o_awready(o_awready),
.i_araddr (i_araddr[AW-1:0]),
.i_arid (i_arid),
.i_arvalid(i_arvalid),
.o_arready(o_arready),
.i_wdata (i_wdata),
.i_wstrb (i_wstrb),
.i_wvalid(i_wvalid),
.o_wready(o_wready),
.o_bid (o_bid),
.o_bresp (o_bresp),
.o_bvalid(o_bvalid),
.i_bready(i_bready),
.o_rdata (o_rdata),
.o_rid (o_rid),
.o_rresp (o_rresp),
.o_rlast (o_rlast),
.o_rvalid(o_rvalid),
.i_rready(i_rready)
);
wire [31:0] mem_addr;
wire [63:0] mem_wdata;
wire [63:0] mem_rdata;
wire [ 7:0] mem_we;
assign mem_we[3:0] = (wb_cyc & wb_stb & wb_we & !wb_adr[2]) ? wb_sel : 4'd0;
assign mem_we[7:4] = (wb_cyc & wb_stb & wb_we & wb_adr[2]) ? wb_sel : 4'd0;
assign mem_wdata = {wb_dat, wb_dat};
assign wb_rdt = wb_adr[2] ? mem_rdata[63:32] : mem_rdata[31:0];
always @(posedge clk) begin
wb_ack <= wb_cyc & wb_stb & !wb_ack;
if (~rst_n) wb_ack <= 1'b0;
end
dpram64 #(
.SIZE(MEM_SIZE),
.mem_clear(mem_clear),
.memfile(INIT_FILE)
) ram (
.clk (clk),
.we (mem_we),
.din (mem_wdata),
.waddr({wb_adr[AW-1:3], 3'b000}),
.raddr({wb_adr[AW-1:3], 3'b000}),
.dout (mem_rdata)
);
endmodule
| 6.819355 |
module axi_mmu_v2_1_9_addr_decoder #(
parameter C_FAMILY = "rtl",
parameter integer C_NUM_RANGES = 1, // Number of address ranges [1..256]
parameter integer C_NUM_RANGES_LOG = 1, // Width of matching range index (min 1)
parameter integer C_ADDR_WIDTH = 32, // Width of address operand [2:64]
parameter [C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_RANGES*64{1'b1}}, // Aligned to 2**C_RANGE_SIZE
parameter [C_NUM_RANGES*32-1:0] C_RANGE_SIZE = {C_NUM_RANGES*32{1'b0}}, // Binary power of range size [0=null_range, 1..C_ADDR_WIDTH]
parameter [C_NUM_RANGES:0] C_RANGE_QUAL = {C_NUM_RANGES{1'b1}} // Range enabled for this decoder instance
) (
input wire [ C_ADDR_WIDTH-1:0] addr, // Decoder input operand
output wire [C_NUM_RANGES_LOG-1:0] range_enc, // Index of matching address range (encoded)
output wire match // Decode successful
);
// Generate Variables
genvar rng;
// Functions
// Function to detect match of one addressable range (returns Boolean).
function decode_address(input [C_ADDR_WIDTH-1:0] base, input [31:0] size,
input [C_ADDR_WIDTH-1:0] addr);
integer i;
begin
if (size == 32'b0) begin // null range
decode_address = 1'b0;
end else begin
decode_address = 1'b1;
for (i = size; i < C_ADDR_WIDTH; i = i + 1) begin
decode_address = decode_address & ~(addr[i] ^ base[i]);
end
end
end
endfunction
// Translate one-hot to binary encoded
function [C_NUM_RANGES_LOG-1:0] f_hot2enc(input [C_NUM_RANGES-1:0] one_hot);
integer i;
integer j;
begin
for (i = 0; i < C_NUM_RANGES_LOG; i = i + 1) begin
f_hot2enc[i] = 1'b0;
for (j = 0; j < C_NUM_RANGES; j = j + 1) begin
f_hot2enc[i] = f_hot2enc[i] | (j[i] & one_hot[j]);
end
end
end
endfunction
wire [C_NUM_RANGES-1:0] range_hot; // Range matching address (1-hot).
generate
for (rng = 0; rng < C_NUM_RANGES; rng = rng + 1) begin : gen_rng
assign range_hot[rng] = C_RANGE_QUAL[rng] ? decode_address(
C_BASE_ADDR[rng*64+:C_ADDR_WIDTH], C_RANGE_SIZE[rng*32+:32], addr
) : 1'b0;
end
assign match = |range_hot;
assign range_enc = f_hot2enc(range_hot);
endgenerate
endmodule
| 7.25219 |
module axi_mm_systemc ( /*AUTOARG*/
// Outputs
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awprot,
m_axi_awvalid,
m_axi_awlock,
m_axi_awcache,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arprot,
m_axi_arvalid,
m_axi_arlock,
m_axi_arcache,
m_axi_rready,
BRAM_RdData_A,
BRAM_RdData_B,
// Inputs
axi_aclk,
axi_aresetn,
interrupt,
ready,
m_axi_awready,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_En_A,
BRAM_WE_A,
BRAM_Addr_A,
BRAM_WrData_A,
BRAM_Rst_B,
BRAM_Clk_B,
BRAM_En_B,
BRAM_WE_B,
BRAM_Addr_B,
BRAM_WrData_B
);
input axi_aclk;
input axi_aresetn;
input interrupt;
input ready;
output [31:0] m_axi_awaddr;
output [7:0] m_axi_awlen;
output [2:0] m_axi_awsize;
output [1:0] m_axi_awburst;
output [2:0] m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output m_axi_awlock;
output [3:0] m_axi_awcache;
output [31:0] m_axi_wdata;
output [3:0] m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0] m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0] m_axi_araddr;
output [7:0] m_axi_arlen;
output [2:0] m_axi_arsize;
output [1:0] m_axi_arburst;
output [2:0] m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
output m_axi_arlock;
output [3:0] m_axi_arcache;
input [31:0] m_axi_rdata;
input [1:0] m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
input BRAM_Rst_A;
input BRAM_Clk_A;
input BRAM_En_A;
input [3:0] BRAM_WE_A;
input [31:0] BRAM_Addr_A;
input [31:0] BRAM_WrData_A;
output [31:0] BRAM_RdData_A;
input BRAM_Rst_B;
input BRAM_Clk_B;
input BRAM_En_B;
input [3:0] BRAM_WE_B;
input [31:0] BRAM_Addr_B;
input [31:0] BRAM_WrData_B;
output [31:0] BRAM_RdData_B;
endmodule
| 6.956547 |
module axi_modbus_v1_0 #(
// Users to add parameters here
parameter INTR_CLOCK = 5,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S0_AXI
parameter integer C_S0_AXI_DATA_WIDTH = 32,
parameter integer C_S0_AXI_ADDR_WIDTH = 7
) (
// Users to add ports here
input wire modbus_clk,
input wire modbus_rst_n,
input wire rs485_rx,
output wire rs485_tx,
output wire rs485_oe,
output wire intr,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S0_AXI
input wire s0_axi_aclk,
input wire s0_axi_aresetn,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
input wire [2 : 0] s0_axi_awprot,
input wire s0_axi_awvalid,
output wire s0_axi_awready,
input wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input wire [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
input wire s0_axi_wvalid,
output wire s0_axi_wready,
output wire [1 : 0] s0_axi_bresp,
output wire s0_axi_bvalid,
input wire s0_axi_bready,
input wire [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input wire [2 : 0] s0_axi_arprot,
input wire s0_axi_arvalid,
output wire s0_axi_arready,
output wire [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output wire [1 : 0] s0_axi_rresp,
output wire s0_axi_rvalid,
input wire s0_axi_rready
);
// Instantiation of Axi Bus Interface S0_AXI
axi_modbus_v1_0_S0_AXI #(
.C_S_AXI_DATA_WIDTH(C_S0_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S0_AXI_ADDR_WIDTH),
.INTR_CLOCK(INTR_CLOCK)
) axi_modbus_v1_0_S0_AXI_inst (
/******************************************/
.modbus_clk (modbus_clk ),
.modbus_rst_n (modbus_rst_n),
.rs485_rx(rs485_rx),
.rs485_tx(rs485_tx),
.rs485_oe(rs485_oe),
.intr(intr),
/******************************************/
.S_AXI_ACLK(s0_axi_aclk),
.S_AXI_ARESETN(s0_axi_aresetn),
.S_AXI_AWADDR(s0_axi_awaddr),
.S_AXI_AWPROT(s0_axi_awprot),
.S_AXI_AWVALID(s0_axi_awvalid),
.S_AXI_AWREADY(s0_axi_awready),
.S_AXI_WDATA(s0_axi_wdata),
.S_AXI_WSTRB(s0_axi_wstrb),
.S_AXI_WVALID(s0_axi_wvalid),
.S_AXI_WREADY(s0_axi_wready),
.S_AXI_BRESP(s0_axi_bresp),
.S_AXI_BVALID(s0_axi_bvalid),
.S_AXI_BREADY(s0_axi_bready),
.S_AXI_ARADDR(s0_axi_araddr),
.S_AXI_ARPROT(s0_axi_arprot),
.S_AXI_ARVALID(s0_axi_arvalid),
.S_AXI_ARREADY(s0_axi_arready),
.S_AXI_RDATA(s0_axi_rdata),
.S_AXI_RRESP(s0_axi_rresp),
.S_AXI_RVALID(s0_axi_rvalid),
.S_AXI_RREADY(s0_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 7.328772 |
module axi_multiplexer #(
parameter DATA_WIDTH = 64,
parameter N_IN = 16,
parameter SEL_WIDTH = $clog2(N_IN)
) (
IN_DATA,
OUT_DATA,
SEL
);
//parameter DATA_WIDTH = 64;
//parameter N_IN = 16;
//parameter SEL_WIDTH = $clog2(N_IN);
input wire [(N_IN * DATA_WIDTH) - 1:0] IN_DATA;
output wire [DATA_WIDTH - 1:0] OUT_DATA;
input wire [SEL_WIDTH - 1:0] SEL;
assign OUT_DATA = IN_DATA[SEL*DATA_WIDTH+:DATA_WIDTH];
endmodule
| 8.058716 |
module axi_mux #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter PRE_FIFO_SIZE = 0,
parameter POST_FIFO_SIZE = 0,
parameter SIZE = 4
) (
input clk,
input reset,
input clear,
input [(WIDTH*SIZE)-1:0] i_tdata,
input [SIZE-1:0] i_tlast,
input [SIZE-1:0] i_tvalid,
output [SIZE-1:0] i_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH*SIZE-1:0] i_tdata_int;
wire [SIZE-1:0] i_tlast_int, i_tvalid_int, i_tready_int;
wire [WIDTH-1:0] o_tdata_int;
wire o_tlast_int, o_tvalid_int, o_tready_int;
reg [3:0] st_port;
reg st_active;
genvar n;
generate
if (PRE_FIFO_SIZE == 0) begin
assign i_tdata_int = i_tdata;
assign i_tlast_int = i_tlast;
assign i_tvalid_int = i_tvalid;
assign i_tready = i_tready_int;
end else begin
for (n = 0; n < SIZE; n = n + 1) begin
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (PRE_FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({i_tlast[n], i_tdata[WIDTH*(n+1)-1:WIDTH*n]}),
.i_tvalid(i_tvalid[n]),
.i_tready(i_tready[n]),
.o_tdata({i_tlast_int[n], i_tdata_int[WIDTH*(n+1)-1:WIDTH*n]}),
.o_tvalid(i_tvalid_int[n]),
.o_tready(i_tready_int[n]),
.space(),
.occupied()
);
end
end
endgenerate
always @(posedge clk)
if (reset) begin
st_port <= 0;
st_active <= 1'b0;
end else if (st_active) begin
if (o_tlast_int & o_tvalid_int & o_tready_int) begin
st_active <= 1'b0;
if ((PRIO != 0) | (st_port == (SIZE - 1))) st_port <= 0;
else st_port <= st_port + 1;
end
end // if (st_active)
else
if(i_tvalid_int[st_port]) st_active <= 1'b1;
else if (st_port == (SIZE - 1)) st_port <= 0;
else st_port <= st_port + 1;
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1) begin : gen1
assign i_tready_int[i] = st_active & o_tready_int & (st_port == i);
end
endgenerate
assign o_tvalid_int = st_active & i_tvalid_int[st_port];
assign o_tlast_int = i_tlast_int[st_port];
genvar j;
generate
for (j = 0; j < WIDTH; j = j + 1) begin : gen2
assign o_tdata_int[j] = i_tdata_int[st_port*WIDTH+j];
end
endgenerate
generate
if (POST_FIFO_SIZE == 0) begin
assign o_tdata = o_tdata_int;
assign o_tlast = o_tlast_int;
assign o_tvalid = o_tvalid_int;
assign o_tready_int = o_tready;
end else
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (POST_FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o_tlast_int, o_tdata_int}),
.i_tvalid(o_tvalid_int),
.i_tready(o_tready_int),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endgenerate
endmodule
| 6.885529 |
module axi_mux4 #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
output i1_tready,
input [WIDTH-1:0] i2_tdata,
input i2_tlast,
input i2_tvalid,
output i2_tready,
input [WIDTH-1:0] i3_tdata,
input i3_tlast,
input i3_tvalid,
output i3_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] o_tdata_int;
wire o_tlast_int, o_tvalid_int, o_tready_int;
reg [3:0] mx_state;
localparam MX_IDLE = 4'b0000;
localparam MX_0 = 4'b0001;
localparam MX_1 = 4'b0010;
localparam MX_2 = 4'b0100;
localparam MX_3 = 4'b1000;
always @(posedge clk)
if (reset | clear) mx_state <= MX_IDLE;
else
case (mx_state)
MX_IDLE:
if (i0_tvalid) mx_state <= MX_0;
else if (i1_tvalid) mx_state <= MX_1;
else if (i2_tvalid) mx_state <= MX_2;
else if (i3_tvalid) mx_state <= MX_3;
MX_0:
if (o_tready_int & o_tvalid_int & o_tlast_int)
if (PRIO) mx_state <= MX_IDLE;
else if (i1_tvalid) mx_state <= MX_1;
else if (i2_tvalid) mx_state <= MX_2;
else if (i3_tvalid) mx_state <= MX_3;
else mx_state <= MX_IDLE;
MX_1:
if (o_tready_int & o_tvalid_int & o_tlast_int)
if (PRIO) mx_state <= MX_IDLE;
else if (i2_tvalid) mx_state <= MX_2;
else if (i3_tvalid) mx_state <= MX_3;
else mx_state <= MX_IDLE;
MX_2:
if (o_tready_int & o_tvalid_int & o_tlast_int)
if (PRIO) mx_state <= MX_IDLE;
else if (i3_tvalid) mx_state <= MX_3;
else mx_state <= MX_IDLE;
MX_3:
if (o_tready_int & o_tvalid_int & o_tlast_int)
if (PRIO) mx_state <= MX_IDLE;
else mx_state <= MX_IDLE;
default: mx_state <= MX_IDLE;
endcase // case (mx_state)
assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
assign {o_tlast_int, o_tdata_int} = mx_state[3] ? {i3_tlast, i3_tdata} :
mx_state[2] ? {i2_tlast, i2_tdata} :
mx_state[1] ? {i1_tlast, i1_tdata} :
{i0_tlast, i0_tdata};
generate
if (BUFFER == 0) begin
assign o_tdata = o_tdata_int;
assign o_tlast = o_tlast_int;
assign o_tvalid = o_tvalid_int;
assign o_tready_int = o_tready;
end else
axi_fifo_short #(
.WIDTH(WIDTH + 1)
) axi_fifo_short (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o_tlast_int, o_tdata_int}),
.i_tvalid(o_tvalid_int),
.i_tready(o_tready_int),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
endgenerate
endmodule
| 8.171347 |
module axi_mux8 #(
parameter PRIO = 0,
parameter WIDTH = 64,
parameter BUFFER = 0
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
output i1_tready,
input [WIDTH-1:0] i2_tdata,
input i2_tlast,
input i2_tvalid,
output i2_tready,
input [WIDTH-1:0] i3_tdata,
input i3_tlast,
input i3_tvalid,
output i3_tready,
input [WIDTH-1:0] i4_tdata,
input i4_tlast,
input i4_tvalid,
output i4_tready,
input [WIDTH-1:0] i5_tdata,
input i5_tlast,
input i5_tvalid,
output i5_tready,
input [WIDTH-1:0] i6_tdata,
input i6_tlast,
input i6_tvalid,
output i6_tready,
input [WIDTH-1:0] i7_tdata,
input i7_tlast,
input i7_tvalid,
output i7_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH-1:0] o_tdata_int0, o_tdata_int1;
wire o_tlast_int0, o_tlast_int1;
wire o_tvalid_int0, o_tvalid_int1;
wire o_tready_int0, o_tready_int1;
axi_mux4 #(
.PRIO (PRIO),
.WIDTH (WIDTH),
.BUFFER(0)
) mux4_int0 (
.clk(clk),
.reset(reset),
.clear(clear),
.i0_tdata(i0_tdata),
.i0_tlast(i0_tlast),
.i0_tvalid(i0_tvalid),
.i0_tready(i0_tready),
.i1_tdata(i1_tdata),
.i1_tlast(i1_tlast),
.i1_tvalid(i1_tvalid),
.i1_tready(i1_tready),
.i2_tdata(i2_tdata),
.i2_tlast(i2_tlast),
.i2_tvalid(i2_tvalid),
.i2_tready(i2_tready),
.i3_tdata(i3_tdata),
.i3_tlast(i3_tlast),
.i3_tvalid(i3_tvalid),
.i3_tready(i3_tready),
.o_tdata(o_tdata_int0),
.o_tlast(o_tlast_int0),
.o_tvalid(o_tvalid_int0),
.o_tready(o_tready_int0)
);
axi_mux4 #(
.PRIO (PRIO),
.WIDTH (WIDTH),
.BUFFER(0)
) mux4_int1 (
.clk(clk),
.reset(reset),
.clear(clear),
.i0_tdata(i4_tdata),
.i0_tlast(i4_tlast),
.i0_tvalid(i4_tvalid),
.i0_tready(i4_tready),
.i1_tdata(i5_tdata),
.i1_tlast(i5_tlast),
.i1_tvalid(i5_tvalid),
.i1_tready(i5_tready),
.i2_tdata(i6_tdata),
.i2_tlast(i6_tlast),
.i2_tvalid(i6_tvalid),
.i2_tready(i6_tready),
.i3_tdata(i7_tdata),
.i3_tlast(i7_tlast),
.i3_tvalid(i7_tvalid),
.i3_tready(i7_tready),
.o_tdata(o_tdata_int1),
.o_tlast(o_tlast_int1),
.o_tvalid(o_tvalid_int1),
.o_tready(o_tready_int1)
);
axi_mux4 #(
.PRIO (PRIO),
.WIDTH (WIDTH),
.BUFFER(BUFFER)
) mux2 (
.clk(clk),
.reset(reset),
.clear(clear),
.i0_tdata(o_tdata_int0),
.i0_tlast(o_tlast_int0),
.i0_tvalid(o_tvalid_int0),
.i0_tready(o_tready_int0),
.i1_tdata(o_tdata_int1),
.i1_tlast(o_tlast_int1),
.i1_tvalid(o_tvalid_int1),
.i1_tready(o_tready_int1),
.i2_tdata(0),
.i2_tlast(1'b0),
.i2_tvalid(1'b0),
.i2_tready(),
.i3_tdata(0),
.i3_tlast(1'b0),
.i3_tvalid(1'b0),
.i3_tready(),
.o_tdata(o_tdata),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready)
);
endmodule
| 6.922538 |
module axi_mux_select #(
parameter WIDTH = 32,
parameter PRE_FIFO_SIZE = 0,
parameter POST_FIFO_SIZE = 0,
parameter SWITCH_ON_LAST = 0, // Wait until tlast is asserted before updating
parameter SIZE = 4
) (
input clk,
input reset,
input clear,
input [$clog2(SIZE)-1:0] select,
input [SIZE*WIDTH-1:0] i_tdata,
input [SIZE-1:0] i_tlast,
input [SIZE-1:0] i_tvalid,
output [SIZE-1:0] i_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [WIDTH*SIZE-1:0] i_tdata_int;
wire [WIDTH-1:0] i_tdata_arr[0:SIZE-1];
wire [SIZE-1:0] i_tlast_int, i_tvalid_int, i_tready_int;
wire [WIDTH-1:0] o_tdata_int;
wire o_tlast_int, o_tvalid_int, o_tready_int;
genvar n;
generate
if (PRE_FIFO_SIZE == 0) begin
assign i_tdata_int = i_tdata;
assign i_tlast_int = i_tlast;
assign i_tvalid_int = i_tvalid;
assign i_tready = i_tready_int;
end else begin
for (n = 0; n < SIZE; n = n + 1) begin
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (PRE_FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({i_tlast[n], i_tdata[WIDTH*(n+1)-1:WIDTH*n]}),
.i_tvalid(i_tvalid[n]),
.i_tready(i_tready[n]),
.o_tdata({i_tlast_int[n], i_tdata_int[WIDTH*(n+1)-1:WIDTH*n]}),
.o_tvalid(i_tvalid_int[n]),
.o_tready(i_tready_int[n]),
.space(),
.occupied()
);
end
end
endgenerate
// Make arrays for easier muxing
genvar i;
generate
for (i = 0; i < SIZE; i = i + 1) begin
assign i_tdata_arr[i] = i_tdata_int[WIDTH*(i+1)-1:WIDTH*i];
end
endgenerate
// Switch select line either immediately or after the last word in a packet
reg [$clog2(SIZE)-1:0] select_hold;
generate
if (SWITCH_ON_LAST) begin
reg init;
always @(posedge clk) begin
if (reset | clear) begin
init <= 1'b0;
select_hold <= 'd0;
end else begin
if (|i_tvalid) begin
init <= 1'b1;
end
// Set select any time after reset and before the first packet OR
// at the end of a packet
if (~init | (o_tlast_int & o_tvalid_int & o_tready_int)) begin
select_hold <= select;
end
end
end
end else begin
always @(*) begin
select_hold <= select;
end
end
endgenerate
// Mux
assign o_tdata_int = i_tdata_arr[select_hold];
assign o_tlast_int = i_tlast_int[select_hold];
assign o_tvalid_int = i_tvalid_int[select_hold];
assign i_tready_int = (1'b1 << select_hold) & {SIZE{o_tready_int}};
generate
if (POST_FIFO_SIZE == 0) begin
assign o_tdata = o_tdata_int;
assign o_tlast = o_tlast_int;
assign o_tvalid = o_tvalid_int;
assign o_tready_int = o_tready;
end else begin
axi_fifo #(
.WIDTH(WIDTH + 1),
.SIZE (POST_FIFO_SIZE)
) axi_fifo (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata({o_tlast_int, o_tdata_int}),
.i_tvalid(o_tvalid_int),
.i_tready(o_tready_int),
.o_tdata({o_tlast, o_tdata}),
.o_tvalid(o_tvalid),
.o_tready(o_tready),
.space(),
.occupied()
);
end
endgenerate
endmodule
| 7.675637 |
module axi_ostr_bfm (
input wire clock_i, // Clock Input
input wire reset_i, // Reset Input
// ===============================================================================
// AXI 4 Stream Transmit Channel
output reg [3:0] tid_o,
input wire tvalid_i, // Transmit data channel valid
output wire tready_o, // Transmit data channel ready
input wire tlast_i, // Transmit data channel last word
input wire [3:0] tstrb_i, // Transmit data channel byte strobes
input wire [3:0] tkeep_i, // Transmit data channel byte strobes
input wire [31:0] tdata_i // Transmit data channel data
);
// ---------------------------------------------------------------------------------------
// Local Parameters
localparam BUF_WI_L2 = 12; // Number of bits to address buffer depth
localparam NO_CH_L2 = 4;
localparam buf_size = (1 << NO_CH_L2) * (1 << BUF_WI_L2); // Number of buffers * Buffer depth
// ---------------------------------------------------------------------------------------
// Wires and Registers
integer rdy_del;
reg [31:0] mem[0:buf_size];
reg [31:0] cnt, last_cnt;
reg [15:0] tready_r;
wire [15:0] tready_d;
reg [15:0] en_cnt;
wire enable;
initial begin
tid_o = 0;
rdy_del = 0;
end
always @(posedge clock_i)
if (tready_o && tvalid_i)
mem[{tid_o[NO_CH_L2-1:0], cnt[BUF_WI_L2-1:0]}] <= #1 tdata_i;
always @(posedge clock_i)
if (reset_i) cnt <= #1 32'h0;
else if (tready_o && tvalid_i) cnt <= #1 cnt + 32'h1;
always @(posedge clock_i) if (tready_o && tvalid_i && tlast_i) last_cnt <= #1 cnt + 32'h1;
always @(posedge clock_i)
if (reset_i) tready_r <= #1 16'h0;
else if (tvalid_i && tready_o) tready_r <= #1 16'h0;
else if (!enable) tready_r <= #1 16'h0;
else tready_r <= #1{tready_r[14:0], tvalid_i & !tready_o};
assign tready_d = {tready_r[14:0], 1'b1};
assign tready_o = tready_d[rdy_del] & enable;
// ===============================================================================
// Transfer complete tracking
reg rx_busy;
/*
always @(posedge clock_i)
if(reset_i) rx_busy <= #1 1'b0;
else
if(tlast_i && tready_o && tvalid_i) rx_busy <= #1 1'b0;
else
if(tvalid_i) rx_busy <= #1 1'b1;
task wait_rx_done;
begin
while(rx_busy) @(posedge clock_i);
@(posedge clock_i);
end
endtask
*/
task wait_idle;
begin
while (!enable) @(posedge clock_i);
while (enable) @(posedge clock_i);
repeat (3) @(posedge clock_i);
end
endtask
// ===============================================================================
// Delayed Module Enable
always @(posedge clock_i)
if (reset_i) en_cnt <= #1 16'h0;
else if (enable && tready_o && tvalid_i) en_cnt <= #1 en_cnt - 16'h01;
assign enable = en_cnt != 16'h0;
// ===============================================================================
// Tasks
task init;
input id;
input mode;
input count;
integer i, count, mode, id, tmp;
begin
@(posedge clock_i);
#1;
cnt = 0;
tid_o = id;
last_cnt = 32'h0;
tready_r = 0;
en_cnt = count;
for (i = 0; i < count; i = i + 1) begin
tmp = $random;
case (mode)
default: mem[{tid_o[3:0], i[BUF_WI_L2:0]}] = i + 1;
1: mem[{tid_o[3:0], i[BUF_WI_L2:0]}] = tmp;
2: mem[{tid_o[3:0], i[BUF_WI_L2:0]}] = {tid_o[NO_CH_L2-1:0], i[27:0]};
3: mem[{tid_o[3:0], i[BUF_WI_L2:0]}] = {tid_o[NO_CH_L2-1:0], tmp[27:0]};
4: mem[{tid_o[3:0], i[BUF_WI_L2:0]}] = {16'h00, tid_o[NO_CH_L2-1:0], i[11:0]};
endcase
end
end
endtask
endmodule
| 7.458363 |
module axi_packet_mux #(
parameter NUM_INPUTS = 1,
parameter MUX_PRE_FIFO_SIZE = 0, // Use 0 (most efficient) unless there is need to compensate for unbalanced input path latencies
parameter MUX_POST_FIFO_SIZE = 0, // Generally leave at 0, similar effect as FIFO_SIZE
parameter FIFO_SIZE = 5 // Size of FIFO in CHDR framer
) (
input clk,
input reset,
input clear,
input [NUM_INPUTS*64-1:0] i_tdata,
input [NUM_INPUTS-1:0] i_tlast,
input [NUM_INPUTS-1:0] i_tvalid,
output [NUM_INPUTS-1:0] i_tready,
input [NUM_INPUTS*128-1:0] i_tuser,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire [NUM_INPUTS*(64+128)-1:0] i_tdata_flat;
genvar i;
generate
for (i = 0; i < NUM_INPUTS; i = i + 1) begin
assign i_tdata_flat[(128+64)*(i+1)-1:(128+64)*i] = {
i_tuser[128*(i+1)-1:128*i], i_tdata[64*(i+1)-1:64*i]
};
end
endgenerate
wire [ 63:0] int_tdata;
wire [127:0] int_tuser;
wire int_tlast, int_tvalid, int_tready;
axi_mux #(
.PRIO(0),
.WIDTH(128 + 64),
.PRE_FIFO_SIZE(MUX_PRE_FIFO_SIZE),
.POST_FIFO_SIZE(MUX_POST_FIFO_SIZE),
.SIZE(NUM_INPUTS)
) axi_mux (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata(i_tdata_flat),
.i_tlast(i_tlast),
.i_tvalid(i_tvalid),
.i_tready(i_tready),
.o_tdata({int_tuser, int_tdata}),
.o_tlast(int_tlast),
.o_tvalid(int_tvalid),
.o_tready(int_tready)
);
chdr_framer #(
.SIZE (FIFO_SIZE),
.WIDTH(64)
) chdr_framer (
.clk(clk),
.reset(reset),
.clear(1'b0),
.i_tdata(int_tdata),
.i_tuser(int_tuser),
.i_tlast(int_tlast),
.i_tvalid(int_tvalid),
.i_tready(int_tready),
.o_tdata(o_tdata),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready)
);
endmodule
| 6.789618 |
module rp_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2) begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
| 6.765574 |
module rp_pcie_bram_7vx_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [ 8:0] waddr0_i, // write address
input [ 8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [ 15:0] wdip_i, // write parity
input [ 3:0] wen_i, // write enable
input [ 8:0] raddr0_i, // write address
input [ 8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [ 15:0] rdop_o, // read parity
input [ 3:0] ren_i // read enable
);
genvar i;
wire [ 3:0] wen = {wen_i[3], wen_i[2], wen_i[1], wen_i[0]};
wire [ 3:0] ren = {ren_i[3], ren_i[2], ren_i[1], ren_i[0]};
wire [35:0] waddr = {waddr1_i, waddr1_i, waddr0_i, waddr0_i};
wire [35:0] raddr = {raddr1_i, raddr1_i, raddr0_i, raddr0_i};
generate
for (i = 0; i < 4; i = i + 1) begin : RAMB18E1
RAMB18E1 #(
.SIM_DEVICE("7SERIES"),
.DOA_REG(1),
.DOB_REG(1),
.SRVAL_A(36'h00000),
.INIT_FILE("NONE"),
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.INIT_A(36'h00000),
.INIT_B(36'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36),
.SRVAL_B(36'h00000)
) u_fifo (
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.ENARDEN(ren[i]),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.ADDRARDADDR({raddr[(9*i)+8:(9*i)+0], 5'b0}),
.ADDRBWRADDR({waddr[(9*i)+8:(9*i)+0], 5'b0}),
.DIADI(wdata_i[(2*16*i)+15:(2*16*i)+0]),
.DIBDI(wdata_i[(2*16*i)+31:(2*16*i)+16]),
.DIPADIP(wdip_i[(2*2*i)+1:(2*2*i)+0]),
.DIPBDIP(wdip_i[(2*2*i)+3:(2*2*i)+2]),
.DOADO(rdata_o[(2*16*i)+15:(2*16*i)+0]),
.DOBDO(rdata_o[(2*16*i)+31:(2*16*i)+16]),
.DOPADOP(rdop_o[(2*2*i)+1:(2*2*i)+0]),
.DOPBDOP(rdop_o[(2*2*i)+3:(2*2*i)+2]),
.WEA({2'b00}),
.WEBWE({4{wen[i]}})
);
end
endgenerate
endmodule
| 6.590647 |
module rp_pcie_bram_7vx_cpl #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [ 9:0] waddr0_i, // write address
input [ 9:0] waddr1_i, // write address
input [ 9:0] waddr2_i, // write address
input [ 9:0] waddr3_i, // write address
input [127:0] wdata_i, // write data
input [ 15:0] wdip_i, // write parity
input wen0_i, // write enable Bank0
input wen1_i, // write enable Bank1
input wen2_i, // write enable Bank2
input wen3_i, // write enable Bank3
input wen4_i, // write enable Bank4
input wen5_i, // write enable Bank5
input wen6_i, // write enable Bank6
input wen7_i, // write enable Bank7
input [ 9:0] raddr0_i, // write address
input [ 9:0] raddr1_i, // write address
input [ 9:0] raddr2_i, // write address
input [ 9:0] raddr3_i, // write address
output [127:0] rdata_o, // read data
output [ 15:0] rdop_o, // read parity
input ren0_i, // read enable Bank0
input ren1_i, // read enable Bank1
input ren2_i, // read enable Bank2
input ren3_i, // read enable Bank3
input ren4_i, // read enable Bank4
input ren5_i, // read enable Bank5
input ren6_i, // read enable Bank6
input ren7_i // read enable Bank7
);
generate
begin
if (COMPLETION_SPACE == "16KB") begin : CPL_FIFO_16KB
rp_pcie_bram_7vx_16k #(
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
) U0 (
.clk_i (clk_i),
.reset_i(reset_i),
.waddr0_i(waddr0_i[9:0]),
.waddr1_i(waddr1_i[9:0]),
.waddr2_i(waddr2_i[9:0]),
.waddr3_i(waddr3_i[9:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen7_i, wen6_i, wen5_i, wen4_i, wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i(raddr0_i[9:0]),
.raddr1_i(raddr1_i[9:0]),
.raddr2_i(raddr2_i[9:0]),
.raddr3_i(raddr3_i[9:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren7_i, ren6_i, ren5_i, ren4_i, ren3_i, ren2_i, ren1_i, ren0_i})
);
end else begin : CPL_FIFO_8KB
rp_pcie_bram_7vx_8k #(
.IMPL_TARGET(IMPL_TARGET),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
) U0 (
.clk_i (clk_i),
.reset_i(reset_i),
.waddr0_i(waddr0_i[8:0]),
.waddr1_i(waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i(raddr0_i[8:0]),
.raddr1_i(raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
end
end
endgenerate
endmodule
| 6.590647 |
module rp_pcie_bram_7vx_rep_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [ 8:0] addr_i, // address
input [127:0] wdata_i, // write data
input [ 15:0] wdip_i, // write parity
input [ 1:0] wen_i, // write enable
output [127:0] rdata_o, // read data
output [ 15:0] rdop_o // read parity
);
genvar i;
wire [1:0] wen = {wen_i[1], wen_i[0]};
generate
for (i = 0; i < 2; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.DOA_REG (1),
.DOB_REG (1),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.RAM_MODE ("TDP"),
.READ_WIDTH_A (36),
.READ_WIDTH_B (36),
.RSTREG_PRIORITY_A ("REGCE"),
.RSTREG_PRIORITY_B ("REGCE"),
.SIM_COLLISION_CHECK ("ALL"),
.SRVAL_A (36'h000000000),
.SRVAL_B (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.WRITE_MODE_B ("WRITE_FIRST"),
.WRITE_WIDTH_A (36),
.WRITE_WIDTH_B (36)
) u_buffer (
.CASCADEINA (),
.CASCADEINB (),
.CASCADEOUTA (),
.CASCADEOUTB (),
.CLKARDCLK (clk_i),
.CLKBWRCLK (clk_i),
.DBITERR (),
.ENARDEN (1'b1),
.ENBWREN (1'b1),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.REGCEAREGCE (1'b1),
.REGCEB (1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB (1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB (1'b0),
.SBITERR (),
.ADDRARDADDR ({1'b1, addr_i[8:0], 6'b0}),
.ADDRBWRADDR ({1'b1, addr_i[8:0], 1'b1, 5'b0}),
.DIADI (wdata_i[(2*32*i)+31:(2*32*i)+0]),
.DIBDI (wdata_i[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP (wdip_i[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP (wdip_i[(2*4*i)+7:(2*4*i)+4]),
.DOADO (rdata_o[(2*32*i)+31:(2*32*i)+0]),
.DOBDO (rdata_o[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP (rdop_o[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP (rdop_o[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY (),
.RDADDRECC (),
.WEA ({4{wen[i]}}),
.WEBWE ({4'b0, {4{wen[i]}}})
);
end
endgenerate
endmodule
| 6.590647 |
module rp_pcie_bram_7vx_rep #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [ 8:0] addr_i, // write address
input [127:0] wdata_i, // write data
input [ 15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
output [127:0] rdata_o, // read data
output [ 15:0] rdop_o // read parity
);
rp_pcie_bram_7vx_rep_8k #(
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
) U0 (
.clk_i (clk_i),
.reset_i(reset_i),
.addr_i (addr_i[8:0]),
.wdata_i(wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen1_i, wen0_i}),
.rdata_o(rdata_o[127:0]),
.rdop_o (rdop_o[15:0])
);
endmodule
| 6.590647 |
module rp_pcie_bram_7vx_req #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [ 8:0] waddr0_i, // write address
input [ 8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [ 15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
input wen2_i, // write enable
input wen3_i, // write enable
input [ 8:0] raddr0_i, // write address
input [ 8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [ 15:0] rdop_o, // read parity
input ren0_i, // read enable
input ren1_i, // read enable
input ren2_i, // read enable
input ren3_i // read enable
);
rp_pcie_bram_7vx_8k #(
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
) U0 (
.clk_i (clk_i),
.reset_i(reset_i),
.waddr0_i(waddr0_i[8:0]),
.waddr1_i(waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i(raddr0_i[8:0]),
.raddr1_i(raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
endmodule
| 6.590647 |
module axi_pcie_mm_s_v1_04_a_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b0),
.S (S)
);
end
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst (
.O (O),
.DI (CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1 (
.O (O),
.DI (CIN),
.SRI(I)
);
end
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b1),
.S (S_n)
);
end
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
axi_pcie_mm_s_v1_04_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_pcie_mm_s_v1_04_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_pcie_mm_s_v1_04_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 6.771003 |
module axi_pcie_mm_s_v1_04_a_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.CLK(ACLK),
.RST(ARESET),
.WR_CLK(1'b0),
.WR_EN(S_VALID),
.WR_READY(S_READY),
.WR_DATA(S_MESG),
.RD_CLK(1'b0),
.RD_EN(M_READY),
.RD_VALID(M_VALID),
.RD_DATA(M_MESG)
);
endmodule
| 6.771003 |
module axi_pcie_v1_08_a_carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b0),
.S (S)
);
end
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst (
.O (O),
.DI (CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1 (
.O (O),
.DI (CIN),
.SRI(I)
);
end
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b1),
.S (S_n)
);
end
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_comparator #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 3;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
axi_pcie_v1_08_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_comparator_sel #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_pcie_v1_08_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_comparator_sel_static #(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
) (
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = (C_DATA_WIDTH + C_BITS_PER_LUT - 1) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [ C_NUM_LUT-1:0] sel;
wire [ C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if (C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
axi_pcie_v1_08_a_carry_and #(
.C_FAMILY(C_FAMILY)
) compare_inst (
.COUT(carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_fifo #(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
) (
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE)
) inst (
.CLK(ACLK),
.RST(ARESET),
.WR_CLK(1'b0),
.WR_EN(S_VALID),
.WR_READY(S_READY),
.WR_DATA(S_MESG),
.RD_CLK(1'b0),
.RD_EN(M_READY),
.RD_VALID(M_VALID),
.RD_DATA(M_MESG)
);
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_GTX_DRP_CHANALIGN_FIX_3752_V6 #(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
) (
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [ 7:0] daddr,
output reg [ 3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
localparam DRP_IDLE_FTS = 1;
localparam DRP_IDLE_TS1 = 2;
localparam DRP_RESET = 3;
localparam DRP_WRITE_FTS = 6;
localparam DRP_WRITE_DONE_FTS = 7;
localparam DRP_WRITE_TS1 = 8;
localparam DRP_WRITE_DONE_TS1 = 9;
localparam DRP_COM = 10'b0110111100;
localparam DRP_FTS = 10'b0100111100;
localparam DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if (~Reset_n) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate = drpstate;
next_daddr = daddr;
den = 0;
din = 0;
dwe = 0;
case (drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET: begin
next_drpstate = DRP_WRITE_TS1;
next_daddr = 8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS: begin
den = 1;
dwe = 1;
case (daddr)
8'h8: din = 16'hFD3C;
8'h9: din = 16'hC53C;
8'hA: din = 16'hFDBC;
8'hB: din = 16'h853C;
endcase
next_drpstate = DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS: begin
if (drdy) begin
if (daddr == 8'hB) begin
next_drpstate = DRP_IDLE_FTS;
next_daddr = 8'h8;
end else begin
next_drpstate = DRP_WRITE_FTS;
next_daddr = daddr + 1'b1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS: begin
if (write_ts1_gated) begin
next_drpstate = DRP_WRITE_TS1;
next_daddr = 8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1: begin
den = 1;
dwe = 1;
case (daddr)
8'h8: din = 16'hFC4A;
8'h9: din = 16'hDC4A;
8'hA: din = 16'hC04A;
8'hB: din = 16'h85BC;
endcase
next_drpstate = DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1: begin
if (drdy) begin
if (daddr == 8'hB) begin
next_drpstate = DRP_IDLE_TS1;
next_daddr = 8'h8;
end else begin
next_drpstate = DRP_WRITE_TS1;
next_daddr = daddr + 1'b1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1: begin
if (write_fts_gated) begin
next_drpstate = DRP_WRITE_FTS;
next_daddr = 8'h8;
end
end
endcase
end
endmodule
| 7.560006 |
module for Spartan-6 PCIe Block
// The BRAM A port is the write port.
// The BRAM B port is the read port.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_pcie_v1_08_a_pcie_bram_s6 #(
parameter DOB_REG = 0, // 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36
) (
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [11:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [11:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 11 :
(WIDTH == 9) ? 10 :
(WIDTH == 18) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
5
);
localparam WRITE_MODE_INT = "NO_CHANGE";
//synthesis translate_off
initial begin
case (WIDTH)
4,9,18,36:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
wire [31:0] di_wire, do_wire;
wire [3:0] dip_wire, dop_wire;
generate
case (WIDTH)
36: begin : width_36
assign di_wire = wdata_i[31:0];
assign dip_wire = wdata_i[35:32];
assign rdata_o = {dop_wire, do_wire};
end
18: begin : width_18
assign di_wire = {16'd0, wdata_i[15:0]};
assign dip_wire = {2'd0, wdata_i[17:16]};
assign rdata_o = {dop_wire[1:0], do_wire[15:0]};
end
9: begin : width_9
assign di_wire = {24'd0, wdata_i[7:0]};
assign dip_wire = {3'd0, wdata_i[8]};
assign rdata_o = {dop_wire[0], do_wire[7:0]};
end
4: begin : width_4
assign di_wire = {28'd0, wdata_i[3:0]};
assign dip_wire = 4'd0;
assign rdata_o = do_wire[3:0];
end
endcase
endgenerate
RAMB16BWER #(
.SIM_DEVICE ("SPARTAN6"),
.DATA_WIDTH_A (WIDTH),
.DATA_WIDTH_B (WIDTH),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.WRITE_MODE_A (WRITE_MODE_INT),
.WRITE_MODE_B (WRITE_MODE_INT)
) ramb16 (
.CLKA (user_clk_i),
.RSTA (reset_i),
.DOA (),
.DOPA (),
.ADDRA ({waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DIA (di_wire),
.DIPA (dip_wire),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.REGCEA (1'b0),
.CLKB (user_clk_i),
.RSTB (reset_i),
.WEB (4'd0),
.DIB (32'd0),
.DIPB (4'd0),
.ADDRB ({raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b0}}}),
.DOB (do_wire),
.DOPB (dop_wire),
.ENB (ren_i),
.REGCEB (rce_i)
);
endmodule
| 7.510734 |
module for Spartan-6 PCIe Block
//
// Given the selected core configuration, calculate the number of
// BRAMs and pipeline stages and instantiate the BRAMS.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi_pcie_v1_08_a_pcie_bram_top_s6 #(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 20,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
) (
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [11:0] mim_tx_waddr,
input [35:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [11:0] mim_tx_raddr,
output [35:0] mim_tx_rdata,
input mim_rx_wen,
input [11:0] mim_rx_waddr,
input [35:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [11:0] mim_rx_raddr,
output [35:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
512 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 2048) ? 1 :
(BYTES_TX <= 4096) ? 2 :
(BYTES_TX <= 8192) ? 4 :
9
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
9
);
axi_pcie_v1_08_a_pcie_brams_s6 #(
.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
axi_pcie_v1_08_a_pcie_brams_s6 #(
.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule
| 7.510734 |
module axi_pcie_v1_08_a_pcie_reset_delay_v6 #(
parameter PL_FAST_TRAIN = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter TCQ = 1
) (
input wire ref_clk,
input wire sys_reset_n,
output delayed_sys_reset_n
);
localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;
reg [ 7:0] reg_count_7_0;
reg [ 7:0] reg_count_15_8;
reg [ 7:0] reg_count_23_16;
wire [23:0] concat_count;
assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};
always @(posedge ref_clk or negedge sys_reset_n) begin
if (!sys_reset_n) begin
reg_count_7_0 <= #TCQ 8'h0;
reg_count_15_8 <= #TCQ 8'h0;
reg_count_23_16 <= #TCQ 8'h0;
end else begin
if (delayed_sys_reset_n != 1'b1) begin
reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;
reg_count_15_8 <= #TCQ(reg_count_7_0 == 8'hff) ? reg_count_15_8 + 1'b1 : reg_count_15_8;
reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;
end
end
end
assign delayed_sys_reset_n = concat_count[TBIT];
endmodule
| 7.560006 |
module axi_pcie_v1_08_a_pselect_f #(
parameter C_AB = 9,
parameter C_AW = 32,
parameter [0:C_AW - 1] C_BAR = 'bz,
parameter C_FAMILY = "nofamily"
) (
input [0:C_AW-1] A,
input AValid,
output CS
);
// Local Paramater declaration
//--------------------------
localparam [0:C_AB-1] BAR = C_BAR[0:C_AB-1];
//------------------------------------------------------------------------------
// Behavioral decoder
//------------------------------------------------------------------------------
generate
if (C_AB > 0) begin : XST_WA
assign CS = (A[0:C_AB-1] == BAR[0:C_AB-1]) ? AValid : 1'b0;
end
if (C_AB == 0) begin : PASS_ON_GEN
assign CS = AValid;
end
endgenerate
endmodule
| 7.560006 |
module_profile.v
// Version : v5.0
// Description : register module having all the registers of axi performance
// monitor read and write logic. Address decoding is also
// implemented in this module based on which the corresponding
// read and write enables being generated
// Verilog-Standard:verilog-2001
//-----------------------------------------------------------------------------
// Structure:
//
// axi_perf_mon_v5_0_11_top.v
// \-- axi_perf_mon_v5_0_11_dff_async_reset.v
//
//-----------------------------------------------------------------------------
// Description: Used to detect the edge for capture event and reset event
// ~~~~~~~~~~~
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module axi_perf_mon_v5_0_11_dff_async_reset (
data ,
clk ,
reset ,
q
);
input data, clk, reset ;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @ ( posedge clk or posedge reset)
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
endmodule
| 7.065413 |
module axi_perf_mon_v5_0_11_sync_fifo #(
parameter WIDTH = 8, // The width of the FIFO data
parameter DEPTH_LOG2 = 3 // Specify power-of-2 FIFO depth
) (
input rst_n,
input clk,
input wren,
input rden,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout,
output reg full,
output reg empty
);
localparam DEPTH = 1 << DEPTH_LOG2;
/* ========================================================================== */
// Register and Wire Declarations
/* ========================================================================== */
(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:DEPTH-1]; // memory for storing FIFO data
reg [DEPTH_LOG2:0] wptr; // wr ptr, with extra wrap bit
reg [DEPTH_LOG2:0] rptr; // rd ptr, with extra wrap bit
//reg rd_en_del; //Delayed read enable
wire [DEPTH_LOG2:0] wptr_inc; // wr ptr incremented by 1
wire [DEPTH_LOG2:0] rptr_inc; // rd ptr incremented by 1
wire [DEPTH_LOG2:0] wptr_nxt; // next wr ptr, with extra wrap bit
wire [DEPTH_LOG2:0] rptr_nxt; // next rd ptr, with extra wrap bit
wire [DEPTH_LOG2-1:0] mem_wptr; // mem wrptr, extra bit removed
wire [DEPTH_LOG2-1:0] mem_rptr; // mem rdptr, extra bit removed
wire almost_full; // only 1 entry available in FIFO
wire almost_empty; // only 1 space used in FIFO
//================================================================================
// Code the FIFO
//================================================================================
assign wptr_inc = wptr + 1'b1; // automatically wraps
assign rptr_inc = rptr + 1'b1; // automatically wraps
assign wptr_nxt = wren ? wptr_inc : wptr;
assign rptr_nxt = rden ? rptr_inc : rptr;
assign mem_wptr = wptr[DEPTH_LOG2-1:0]; // get rid of extra bit
assign mem_rptr = rptr[DEPTH_LOG2-1:0]; // get rid of extra bit
// Assign dout
always @(posedge clk) begin
//if (~rst_n)
// dout <= 0;
//else if(rden == 1'b1) begin
dout <= mem[mem_rptr]; //read data output
//end
end
// Almost_full if one more write will make the FIFO full
assign almost_full = (wptr_inc[DEPTH_LOG2] != rptr[DEPTH_LOG2]) &&
(wptr_inc[DEPTH_LOG2-1:0] == rptr[DEPTH_LOG2-1:0]);
// Almost_empty if one more read will make the FIFO empty
assign almost_empty = (wptr[DEPTH_LOG2:0] == rptr_inc[DEPTH_LOG2:0]);
// Flags
always @(posedge clk) begin
if (~rst_n) begin
full <= 1'b0;
empty <= 1'b1;
rptr <= {(DEPTH_LOG2 + 1) {1'b0}};
wptr <= {(DEPTH_LOG2 + 1) {1'b0}};
end else begin
full <= (almost_full & wren & ~rden) | (full & ~rden);
empty <= (almost_empty & rden & ~wren) | (empty & ~wren);
rptr <= rptr_nxt;
wptr <= wptr_nxt;
// rd_en_del <= rden;
end
end
// Assign memory
always @(posedge clk) begin
if (wren) mem[mem_wptr] <= din;
end
endmodule
| 6.932985 |
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