code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module BoothMultipilcation (
clk,
X,
Y,
Z
);
input clk;
input signed [31:0] X, Y;
output signed [63:0] Z;
reg signed [63:0] Z;
reg [1:0] temp; // for 01 or 10
integer i;
reg E1;
reg [31:0] Y1;
always @(X, Y) begin
Z = 64'd0;
E1 = 1'd0;
for (i = 0; i < 32; i = i + 1) begin
temp = {X[i], E1};
Y1 = -Y;
case (temp)
2'd2: Z[63 : 32] = Z[63 : 32] + Y1;
2'd1: Z[63 : 32] = Z[63 : 32] + Y;
default: begin
end
endcase
Z = Z >>> 1; //arithmatic shift
E1 = X[i];
end
if (Y == 32'h8000_0000) begin
Z = -Z;
end
end
endmodule
| 6.92481 |
module BoothMultiplication_tb;
// Inputs
reg clk;
reg [31:0] Multiplicand;
reg [31:0] Multiplier;
reg run;
// Outputs
wire isValid;
wire [63:0] result;
// Instantiate the Unit Under Test (UUT)
BoothMultipilcation uut (
.clk(clk),
.Multiplicand(Multiplicand),
.Multiplier(Multiplier),
.run(run),
.isValid(isValid),
.result(result)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
Multiplicand = 4;
Multiplier = -7;
run = 0;
// Wait 100 ns for global reset to finish
#170;
run = 1;
#400;
run = 0;
#40;
run = 1;
end
endmodule
| 7.014879 |
module BoothMultiplier (
input clk,
rst,
input [4:0] cand,
ier,
output [10:0] R,
output valid
);
reg [4:0] AC = 0, QR = 0;
reg [2:0] counter = 6;
reg Qn = 0, sh_en = 0, op_en = 0;
wire [ 1:0] op;
reg [ 1:0] opr;
wire [10:0] all;
ControlUnit(
QR[0], Qn, op_en, op
); Shifter(
{AC, QR, Qn}, all, sh_en
);
always @(posedge clk or posedge rst) begin
if (rst) begin
AC = 0;
QR = ier;
Qn = 0;
counter = 6;
sh_en = 0;
op_en = 0;
end else if (counter != 0) begin
if (counter != 6) begin
sh_en = 1;
sh_en = 0;
{AC, QR, Qn} = all;
end
op_en = 1;
op_en = 0;
opr = op;
if (opr == 2'b01) begin
AC = AC + cand;
end
if (opr == 2'b10) begin
AC = AC - cand;
end
counter = counter - 1;
end
end
assign R = all;
assign valid = (counter == 0);
endmodule
| 7.014879 |
module boothPP #(
parameter WIDTH = 14
) (
input [WIDTH-1:0] in,
output [ WIDTH:0] out_in,
output [ WIDTH:0] out_in_n,
output [ WIDTH:0] out_in_2,
output [ WIDTH:0] out_in_2n,
output [ WIDTH:0] out_zero
);
wire [WIDTH:0] onesComp; // One's Comp
// +1 needs to be compensated in PP reductions
assign onesComp = ~{1'b0, in};
assign out_in = {1'b0, in};
assign out_in_n = onesComp;
assign out_in_2 = {in, 1'b0};
assign out_in_2n = {onesComp[WIDTH-1:0], 1'b1};
assign out_zero = 0;
endmodule
| 7.890708 |
module boothPPCal #(
parameter WIDTH = 14
) (
input [WIDTH:0] pp,
input [WIDTH:0] pp_n,
input [WIDTH:0] pp_2,
input [WIDTH:0] pp_2n,
input [WIDTH:0] pp_zero,
input [ 2:0] booth,
output comp,
output [WIDTH:0] out
);
wire single_pp, double_pp, neg_pp;
boothEnc bEnc (
.in(booth),
.single(single_pp),
.double(double_pp),
.neg(neg_pp)
);
boothSel #(
.WIDTH(WIDTH)
) bSel (
.single(single_pp),
.double(double_pp),
.neg(neg_pp),
.in(pp),
.in_n(pp_n),
.in_2(pp_2),
.in_2n(pp_2n),
.zero(pp_zero),
.out(out)
);
assign comp = neg_pp & (single_pp | double_pp);
endmodule
| 7.433765 |
module boothPPCal_tb;
parameter WIDTH = 14; // For 16 bit WIDTH = 16
// Inputs
reg [WIDTH-1:0] multiplier;
reg [WIDTH-1:0] multiplicand;
reg [2:0] booth;
reg [WIDTH+2:0] temp_multiplier;
// Outputs
wire [WIDTH:0] product; // Partial product
wire comp;
wire [WIDTH:0] pp_in, pp_n, pp_2, pp_2n, pp_zero;
integer i, j;
boothPP #(
.WIDTH(WIDTH)
) bPP (
.in(multiplicand),
.out_in(pp_in),
.out_in_n(pp_n),
.out_in_2(pp_2),
.out_in_2n(pp_2n),
.out_zero(pp_zero)
);
// Get partial produts for each row
boothPPCal #(
.WIDTH(WIDTH)
) pp (
.pp(pp_in),
.pp_n(pp_n),
.pp_2(pp_2),
.pp_2n(pp_2n),
.pp_zero(pp_zero),
.booth(booth),
.comp(comp),
.out(product)
);
initial begin
multiplier = 0;
multiplicand = 0;
temp_multiplier = 0;
booth = 3'b0;
#5;
// Get basic partial products
for (j = 1; j <= 10; j = j + 1) begin
multiplicand = $random;
multiplier = $random;
temp_multiplier = {1'b0, 1'b0, multiplier, 1'b0};
for (i = 1; i <= (WIDTH + 1) / 2; i = i + 1) begin
booth = {temp_multiplier[2*i], temp_multiplier[2*i-1], temp_multiplier[2*i-2]};
#10;
end
end
$finish();
end
endmodule
| 6.816759 |
module BoothPPG_32R4 (
a,
b,
sign,
i,
pp0,
pp1,
pp2,
pp3,
pp4,
pp5,
pp6,
pp7,
pp8,
pp9,
pp10,
pp11,
pp12,
pp13,
pp14,
pp15,
pp16
);
input wire [31:0] a;
input wire [31:0] b;
input wire sign;
output wire [15:0] i;
output wire [33:0] pp0;
output wire [33:0] pp1;
output wire [33:0] pp2;
output wire [33:0] pp3;
output wire [33:0] pp4;
output wire [33:0] pp5;
output wire [33:0] pp6;
output wire [33:0] pp7;
output wire [33:0] pp8;
output wire [33:0] pp9;
output wire [33:0] pp10;
output wire [33:0] pp11;
output wire [33:0] pp12;
output wire [33:0] pp13;
output wire [33:0] pp14;
output wire [33:0] pp15;
output wire [31:0] pp16;
assign i[15:0] = {
b[31],
b[29],
b[27],
b[25],
b[23],
b[21],
b[19],
b[17],
b[15],
b[13],
b[11],
b[9],
b[7],
b[5],
b[3],
b[1]
};
BoothPPG_32R4_NORM ppg0 (
.mulcand(a),
.r4input({b[1:0], 1'b0}),
.sign(sign),
.pp(pp0)
);
BoothPPG_32R4_NORM ppg1 (
.mulcand(a),
.r4input(b[3:1]),
.sign(sign),
.pp(pp1)
);
BoothPPG_32R4_NORM ppg2 (
.mulcand(a),
.r4input(b[5:3]),
.sign(sign),
.pp(pp2)
);
BoothPPG_32R4_NORM ppg3 (
.mulcand(a),
.r4input(b[7:5]),
.sign(sign),
.pp(pp3)
);
BoothPPG_32R4_NORM ppg4 (
.mulcand(a),
.r4input(b[9:7]),
.sign(sign),
.pp(pp4)
);
BoothPPG_32R4_NORM ppg5 (
.mulcand(a),
.r4input(b[11:9]),
.sign(sign),
.pp(pp5)
);
BoothPPG_32R4_NORM ppg6 (
.mulcand(a),
.r4input(b[13:11]),
.sign(sign),
.pp(pp6)
);
BoothPPG_32R4_NORM ppg7 (
.mulcand(a),
.r4input(b[15:13]),
.sign(sign),
.pp(pp7)
);
BoothPPG_32R4_NORM ppg8 (
.mulcand(a),
.r4input(b[17:15]),
.sign(sign),
.pp(pp8)
);
BoothPPG_32R4_NORM ppg9 (
.mulcand(a),
.r4input(b[19:17]),
.sign(sign),
.pp(pp9)
);
BoothPPG_32R4_NORM ppg10 (
.mulcand(a),
.r4input(b[21:19]),
.sign(sign),
.pp(pp10)
);
BoothPPG_32R4_NORM ppg11 (
.mulcand(a),
.r4input(b[23:21]),
.sign(sign),
.pp(pp11)
);
BoothPPG_32R4_NORM ppg12 (
.mulcand(a),
.r4input(b[25:23]),
.sign(sign),
.pp(pp12)
);
BoothPPG_32R4_NORM ppg13 (
.mulcand(a),
.r4input(b[27:25]),
.sign(sign),
.pp(pp13)
);
BoothPPG_32R4_NORM ppg14 (
.mulcand(a),
.r4input(b[29:27]),
.sign(sign),
.pp(pp14)
);
BoothPPG_32R4_NORM ppg15 (
.mulcand(a),
.r4input(b[31:29]),
.sign(sign),
.pp(pp15)
);
BoothPPG_32R4_MSB ppg16 (
.mulcand(a),
.msb(b[31]),
.sign(sign),
.pp(pp16)
);
endmodule
| 7.209531 |
module BoothPPG_32R4_MSB (
mulcand,
msb,
sign,
pp
);
input wire [31:0] mulcand;
input wire msb;
input wire sign;
output wire [31:0] pp;
assign pp = ((sign == 0) && (msb == 1)) ? mulcand : 32'b0;
endmodule
| 7.209531 |
module BoothPPG_32R4_NORM (
mulcand,
r4input,
sign,
pp
);
input wire [31:0] mulcand;
input wire [2:0] r4input;
input wire sign;
output wire [33:0] pp;
wire [32:0] raw;
assign raw[32:0] = (r4input[1]^r4input[0] === 0)?
((r4input[2]^r4input[0] === 0)?0:{mulcand[31:0], 1'b0}):
((sign === 0)?{1'b0, mulcand[31:0]}:{mulcand[31], mulcand[31:0]});
genvar i;
generate
for (i = 0; i <= 32; i = i + 1) begin
assign pp[i] = raw[i] ^ r4input[2];
end
endgenerate
assign pp[33] = (sign === 0) ? r4input[2] : pp[32];
endmodule
| 7.209531 |
module boothSel #(
parameter WIDTH = 14
) (
input single, // The single input to the Selector
input double, // The double input to the Selector
input neg, // The neg input to the Selector
input [WIDTH:0] in, // The input to the Selector
input [WIDTH:0] in_n, // The input to the Selector
input [WIDTH:0] in_2, // The input to the Selector
input [WIDTH:0] in_2n, // The input to the Selector
input [WIDTH:0] zero, // The input to the Selector
output reg [WIDTH:0] out // The output to the Selector
);
always @(*) begin
// This genrates the outputs to the Selector
case ({
single, double, neg
})
3'b000: out = zero;
3'b100: out = in;
3'b010: out = in_2;
3'b011: out = in_2n;
3'b101: out = in_n;
3'b001: out = zero;
default: out = zero;
endcase
end
endmodule
| 7.630619 |
module Adder (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire cout;
wire [7:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[2],
q[2]
);
fa fa4 (
a[3],
b[3],
q[2],
sum[3],
q[3]
);
fa fa5 (
a[4],
b[4],
q[3],
sum[4],
q[4]
);
fa fa6 (
a[5],
b[5],
q[4],
sum[5],
q[5]
);
fa fa7 (
a[6],
b[6],
q[5],
sum[6],
q[6]
);
fa fa8 (
a[7],
b[7],
q[6],
sum[7],
cout
);
endmodule
| 6.808429 |
module booth_substep (
input wire signed [7:0] a,
Q,
input wire signed q0,
input wire signed [7:0] m,
output reg signed [7:0] f8,
output reg signed [7:0] l8,
output reg cq0
);
wire [7:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
m,
subam
);
always @(*) begin
if (Q[0] == q0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = a[0];
f8 = a >> 1;
if (a[7] == 1) f8[7] = 1;
end else if (Q[0] == 1 && q0 == 0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = subam[0];
f8 = subam >> 1;
if (subam[7] == 1) f8[7] = 1;
end else begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = addam[0];
f8 = addam >> 1;
if (addam[7] == 1) f8[7] = 1;
end
end
endmodule
| 6.761271 |
modules instantiated within the controller and datapath units,
// and the top module that instantiates the controller and datapath and wires together the necessary
// ports together.
//////////////////////////////////////////////////////////////////////////////////
// Accumulator register for the datapath circuit
// this is a 32-bit register that shift arithmetically to the right.
// The register has a single input that is 32-bits and is the output
// of a 2's complement adder/subtractor.
// There are two outputs, one sends the least significant bit '[0]' of the register
// to the B register everytime the Shift signal is high.
// The other output is the 32-bit value of the register itself which serves as the
// input to the 2's complement adder/subtractor.
module Acc_Reg#( parameter W = 32 )
( in,
clk,
reset,
load,
shift,
Acc_out_B,
Acc_out_AS
);
input [W-1:0] in;
input clk;
input reset;
input load;
input shift;
output Acc_out_B;
output [W-1:0] Acc_out_AS;
reg [W-1:0] Acc_Reg;
initial
begin
Acc_Reg = 32'b0;
end
always @( posedge clk or posedge reset )
begin
if ( reset )
Acc_Reg <= 32'b0;
else
begin
case ({ shift, load })
2'b00: Acc_Reg <= Acc_Reg;
2'b01: Acc_Reg <= in;
// concatenates the MSB of the reg and the removes the LSB.
2'b10: Acc_Reg <= { Acc_Reg[W-1], Acc_Reg[W-1:1] };
default: Acc_Reg <= Acc_Reg;
endcase
end
end
// LSB of the register is sent as the input of the B register.
assign Acc_out_B = Acc_Reg[0];
assign Acc_out_AS = Acc_Reg;
endmodule
| 8.393884 |
modules,
// the LSB of the B register is sent into the bi Register, this serves
// as the previous bit of the B register, while at the same time
// the LSB is also sent into the input of an XOR gate and the cin of
// 2's complement adder/subtractor.
// The LSB serves three functions. The previous bit of the B reg (bi-1),
// the current bit of the B reg (bi, gets sent to XOR gate), and the
// input that controls the adder/subtractor.
// This is ESSENTIAL to create the functionality of BOOTH'S ALGORITHM.
module B_Reg#( parameter W = 32 )
( in,
shiftIn,
clk,
load,
shift,
B_out_biReg,
B_out_XOR,
B_Result
);
input shiftIn;
input [W-1:0] in;
input clk;
input load;
input shift;
output B_out_XOR;
output B_out_biReg;
output [W-1:0] B_Result;
reg [W-1:0] B_Reg;
initial
begin
B_Reg = 32'b0;
end
always @( posedge clk )
begin
case ({ shift, load })
2'b00: B_Reg <= B_Reg;
2'b01: B_Reg <= in;
//concatenates the single-bit input from the acc Reg
//and the upper 31 bits of the B Reg/
2'b10: B_Reg <= {shiftIn, B_Reg[W-1:1]};
default: B_Reg <= B_Reg;
endcase
end
assign B_out_biReg = B_Reg[0];
assign B_out_XOR = B_Reg[0];
assign B_Result = B_Reg;
endmodule
| 9.092212 |
module xor_gate (
in0,
in1,
out
);
input in0;
input in1;
output out;
assign out = in1 ^ in0;
endmodule
| 8.121905 |
module mux_2in #(
parameter W = 32
) (
in0,
in1,
sel,
out
);
input [W-1:0] in0; // value is instantiated in datapath unit.
input [W-1:0] in1;
input sel;
output [W-1:0] out;
assign out = sel ? in1 : in0;
endmodule
| 8.648457 |
module A_Reg #(
parameter W = 32
) (
in,
clk,
load,
out
);
input [W-1:0] in;
input clk;
input load;
output [W-1:0] out;
reg [W-1:0] A_Reg;
initial begin
A_Reg = 32'b0;
end
always @(posedge clk) begin
if (load) A_Reg <= in;
end
assign out = A_Reg;
endmodule
| 8.82846 |
module AS_2comp #(
parameter W = 32
) (
a,
b,
cin,
out
);
input [W-1:0] a;
input [W-1:0] b;
input cin;
output [W-1:0] out;
assign out = cin ? (b + ~a + cin) : (b + a);
endmodule
| 8.280241 |
modules are part os the control circuit.
// The DFF is used as part of the state, next-state controller logic.
// The DFF is a clocked register that can be used to allow for
// a single clock cycle to occur before the states are sent to the controller
// after the next state inputs are sent into this DFF.
module DFF
( d,
clk,
q
);
input d;
input clk;
output q;
reg q;
initial
begin
q = 1'b0;
end
always @( posedge clk )
begin
q <= d;
end
endmodule
| 7.368768 |
module Countdown_Counter (
SubCount,
CountRst,
clk,
Done,
CountReg
);
input SubCount;
input CountRst;
input clk;
output Done;
output [5:0] CountReg;
reg [5:0] CountReg;
initial begin
CountReg = 6'd32;
end
// only posedge clk in sensitivity list and not
// also posedge reset, because if it is included
// the combinational logic of the Done flag
// never has time to occur ( be set high ) before the register
// is reset again to 6'd32 so it never "sees" the zero.
always @(posedge clk) begin
if (CountRst) CountReg <= 6'd32;
else if (SubCount) CountReg <= CountReg - 1;
else CountReg <= CountReg;
end
assign Done = (CountReg == 0);
endmodule
| 7.614592 |
module Controller_Logic (
Start,
Done,
state0,
state1,
nstate0,
nstate1,
SubCount,
CountRst,
accRst,
accLd,
Bld,
Ald,
biRst,
Ready,
Shift
);
input Start;
input Done;
input state0;
input state1;
output nstate0;
output nstate1;
//reg nstate0;
//reg nstate1;
output accRst;
output accLd;
output Bld;
output Ald;
output biRst;
output Ready;
output Shift;
output CountRst;
output SubCount;
// calculating the next state
/*
always @(*)
begin
nstate1 = 1'b0;
nstate0 = 1'b0;
case ({ state1, state0 })
2'b00: begin
if ( Start )
begin
nstate1 = 1'b0;
nstate0 = 1'b1;
end
end
2'b01: begin
if ( !Done )
begin
nstate1 = 1'b1;
nstate0 = 1'b0;
end
else
begin
nstate1 = 1'b0;
nstate0 = 1'b0;
end
end
2'b10: begin
if ( !Done )
begin
nstate1 = 1'b0;
nstate0 = 1'b1;
end
else
begin
nstate1 = 1'b0;
nstate0 = 1'b0;
end
end
default: begin
nstate1 = state1;
nstate0 = state0;
end
endcase
end
*/
assign nstate1 = (state0 & ~Done);
assign nstate0 = ((state1 & ~Done) | (~state1 & ~state0 & Start));
// output
assign accRst = (~state1 & ~state0 & Start);
assign accLd = (state0 & ~Done);
assign Bld = (~state1 & ~state0 & Start);
assign Ald = (~state1 & ~state0 & Start);
assign biRst = (~state1 & ~state0 & Start);
assign Ready = ((state1 & Done) | (state0 & Done) | (~state1 & ~state0 & ~Start));
assign Shift = (state1 & ~Done);
assign CountRst = (Done);
assign SubCount = (state1 & ~Done);
endmodule
| 7.304573 |
module
// for initial debugging and to view the signal occurences of
// each operand and other key outputs within the circuit.
module Booths_Signed_Mult32#( parameter W = 32 )
( A,
B,
Start,
clk,
Result,
accRst,
accLd,
Bld,
Ald,
bi_1_Rst,
Ready,
Shift,
CountRst,
SubCount,
state0,
state1,
nstate0,
nstate1,
Done,
B_Result,
Acc_out_AS_in,
CountReg
);
input [W-1:0] A;
input [W-1:0] B;
input Start;
input clk;
output [63:0] Result;
output accRst;
output accLd;
output Bld;
output Ald;
output bi_1_Rst;
output Ready;
output Shift;
output CountRst;
output SubCount;
output state0;
output state1;
output nstate0;
output nstate1;
output Done;
output [W-1:0] B_Result;
output [W-1:0] Acc_out_AS_in;
output [5:0] CountReg;
wire accRst;
wire accLd;
wire Bld;
wire Ald;
wire bi_1_Rst;
wire Shift;
Datapath_unit#(W) datapath ( .A ( A ),
.B ( B ),
.clk ( clk ),
.Result ( Result ),
.accLd ( accLd ),
.Bld ( Bld ),
.Ald ( Ald ),
.accRst ( accRst ),
.bi_1_Rst ( bi_1_Rst ),
.Shift ( Shift ),
.B_Result ( B_Result ),
.Acc_out_AS_in ( Acc_out_AS_in )
);
Control_unit controller ( .clk ( clk ),
.Start ( Start ),
.accRst ( accRst ),
.accLd ( accLd ),
.Bld ( Bld ),
.Ald ( Ald ),
.bi_1_Rst ( bi_1_Rst ),
.Ready ( Ready ),
.Shift ( Shift ),
.CountRst ( CountRst ),
.SubCount ( SubCount),
.state0 ( state0 ),
.state1 ( state1 ),
.nstate0 ( nstate0 ),
.nstate1 ( nstate1 ),
.Done ( Done ),
.CountReg ( CountReg )
);
endmodule
| 7.454266 |
module carry_save_adder #(
parameter DATA_WIDTH = 32
) (
input [DATA_WIDTH - 1:0] a,
input [DATA_WIDTH - 1:0] b,
input [DATA_WIDTH - 1:0] c,
output [DATA_WIDTH - 1:0] sum,
output [DATA_WIDTH - 1:0] cout
);
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : three
assign {cout[i], sum[i]} = a[i] + b[i] + c[i];
end
endgenerate
endmodule
| 7.192563 |
module booth_2bit #(
parameter DATA_WIDTH = 34,
parameter EXTEND_WIDTH = 33,
parameter BIAS = 0
) (
input [2:0] y,
input [DATA_WIDTH - 1:0] num_double,
input [DATA_WIDTH - 1:0] num_double_minus,
input [DATA_WIDTH - 1:0] num_data_width,
input [DATA_WIDTH - 1:0] num_minus,
output [EXTEND_WIDTH + DATA_WIDTH - 1:0] num_booth_extend
);
wire y0;
wire y1;
wire y2;
reg [DATA_WIDTH - 1:0] num_booth;
assign num_booth_extend = {{EXTEND_WIDTH{num_booth[DATA_WIDTH-1]}}, num_booth} << BIAS;
assign {y2, y1, y0} = y;
always @(*) begin
case ({
y2, y1, y0
})
3'b000: begin
num_booth <= 'd0;
end
//+1
3'b001: begin
num_booth <= num_data_width;
end
//+1
3'b010: begin
num_booth <= num_data_width;
end
//+2
3'b011: begin
num_booth <= num_double;
end
//-2
3'b100: begin
num_booth <= num_double_minus;
end
//-1
3'b101: begin
num_booth <= num_minus;
end
//-1
3'b110: begin
num_booth <= num_minus;
end
3'b111: begin
num_booth <= 'd0;
end
default: begin
num_booth <= 'd0;
end
endcase
end
endmodule
| 6.656786 |
module booth_32x32_mult (
product,
Q,
M
);
parameter REG_SIZE = 32;
parameter REG_HALF_SIZE = REG_SIZE / 2;
input [REG_SIZE-1:0] Q, M;
output [REG_SIZE + REG_SIZE - 1:0] product;
reg [REG_SIZE + REG_SIZE -1:0] prod;
reg [2:0] two_bit_recoding[REG_SIZE-1:0];
reg [REG_SIZE + REG_SIZE-1:0] partial_products[REG_HALF_SIZE-1:0];
wire [REG_SIZE:0] inverted_M;
integer i, j;
assign inverted_M = {~M[REG_SIZE-1], ~M} + 1;
always @(*) begin
two_bit_recoding[0] = {Q[1], Q[0], 1'b0}; // set recoding bits for first bit
j = 1;
for (i = 2; i < REG_SIZE; i = i + 2) begin // set rest of recoding bits
two_bit_recoding[j] = {Q[i+1], Q[i], Q[i-1]};
j = j + 1;
end
for (i = 0; i < REG_HALF_SIZE; i = i + 1) begin
case (two_bit_recoding[i])
3'b001, 3'b010: partial_products[i] = $signed({M[REG_SIZE-1], M});
3'b011: partial_products[i] = $signed({M, 1'b0});
3'b100: partial_products[i] = $signed({inverted_M[REG_SIZE-1:0], 1'b0});
3'b101, 3'b110: partial_products[i] = $signed(inverted_M);
default: partial_products[i] = 0;
endcase
end
prod = partial_products[0];
// bit shift all the partial products
for (i = 1; i < REG_HALF_SIZE; i = i + 1) partial_products[i] = partial_products[i] << (i + i);
// add all partial products
for (i = 1; i < REG_HALF_SIZE; i = i + 1) prod = prod + partial_products[i];
end
assign product = prod;
endmodule
| 6.621393 |
module booth_4bit;
input [3:0] m;
input [4:0] q;
output [7:0] z;
wire [3:0] a_out1;
wire [4:0] q_out1;
wire [3:0] a_out2;
wire [4:0] q_out2;
wire [3:0] a_out3;
wire [4:0] q_out3;
wire [3:0] a_out4;
wire [4:0] q_out4;
booth_base booth1 (
.a_in(4'b0000),
.m(m),
.q_in({q, 1'b0}),
.a_out(a_out1),
.q_out(q_out1)
);
booth_base booth2 (
.a_in(a_out1),
.m(m),
.q_in(q_out1),
.a_out(a_out2),
.q_out(q_out2)
);
booth_base booth3 (
.a_in(a_out2),
.m(m),
.q_in(q_out2),
.a_out(a_out3),
.q_out(q_out3)
);
booth_base booth4 (
.a_in(a_out3),
.m(m),
.q_in(q_out3),
.a_out(a_out4),
.q_out(q_out4)
);
endmodule
| 7.103872 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module controls what operation is perforemed based on the booth algorithm. If adding or subtracting or just shifting.
//cass modules are full adders for each row of the array multiplier that work based on the control signals generated.
//Python script was used to generate the verilog code without errors.
//Refer to the refernce book for exact architecture.
module tb_booth_array_16bit();
reg signed [15:0] a,b;
wire signed [31:0] prod;
booth_array_16bit uut(.prod(prod),.a(a),.b(b));
initial
begin
#20 a = 16'd30; b = 16'd500;
#20 a = -16'd333; b = 16'd333;
#20 a = -16'd3131; b = -16'd720;
#20 a = 16'd623; b = -16'd774;
#20 a = 16'd32767; b = -16'd32767;
#20 a = 16'd1; b = 16'd32767;
#20 $stop;
end
initial
begin
$monitor("time=%3d, a=%5d, b=%5d, prod=%10d",$time,a,b,prod);
end
initial
begin
$dumpfile("booth_array_16bit.vcd");
$dumpvars;
end
endmodule
| 7.033768 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_16bit (
pout,
a,
pin,
cin
);
output [15:0] pout;
input [15:0] a;
input [14:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(x),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
endmodule
| 6.689494 |
module cass_17bit (
pout,
a,
pin,
cin
);
output [16:0] pout;
input [15:0] a;
input [15:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(x),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
endmodule
| 7.022218 |
module cass_18bit (
pout,
a,
pin,
cin
);
output [17:0] pout;
input [15:0] a;
input [16:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(x),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
endmodule
| 6.757213 |
module cass_19bit (
pout,
a,
pin,
cin
);
output [18:0] pout;
input [15:0] a;
input [17:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(x),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
endmodule
| 6.666081 |
module cass_20bit (
pout,
a,
pin,
cin
);
output [19:0] pout;
input [15:0] a;
input [18:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(x),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
endmodule
| 6.560783 |
module cass_21bit (
pout,
a,
pin,
cin
);
output [20:0] pout;
input [15:0] a;
input [19:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(x),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
endmodule
| 6.786658 |
module cass_22bit (
pout,
a,
pin,
cin
);
output [21:0] pout;
input [15:0] a;
input [20:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(x),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
endmodule
| 6.857238 |
module cass_23bit (
pout,
a,
pin,
cin
);
output [22:0] pout;
input [15:0] a;
input [21:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(c22),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
cass ca23 (
.pout(pout[22]),
.cout(x),
.a(a[15]),
.pin(pin[21]),
.cin(c22)
);
endmodule
| 6.786241 |
module cass_25bit (
pout,
a,
pin,
cin
);
output [24:0] pout;
input [15:0] a;
input [23:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(c22),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
cass ca23 (
.pout(pout[22]),
.cout(c23),
.a(a[15]),
.pin(pin[21]),
.cin(c22)
);
cass ca24 (
.pout(pout[23]),
.cout(c24),
.a(a[15]),
.pin(pin[22]),
.cin(c23)
);
cass ca25 (
.pout(pout[24]),
.cout(x),
.a(a[15]),
.pin(pin[23]),
.cin(c24)
);
endmodule
| 6.507961 |
module cass_27bit (
pout,
a,
pin,
cin
);
output [26:0] pout;
input [15:0] a;
input [25:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(c22),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
cass ca23 (
.pout(pout[22]),
.cout(c23),
.a(a[15]),
.pin(pin[21]),
.cin(c22)
);
cass ca24 (
.pout(pout[23]),
.cout(c24),
.a(a[15]),
.pin(pin[22]),
.cin(c23)
);
cass ca25 (
.pout(pout[24]),
.cout(c25),
.a(a[15]),
.pin(pin[23]),
.cin(c24)
);
cass ca26 (
.pout(pout[25]),
.cout(c26),
.a(a[15]),
.pin(pin[24]),
.cin(c25)
);
cass ca27 (
.pout(pout[26]),
.cout(x),
.a(a[15]),
.pin(pin[25]),
.cin(c26)
);
endmodule
| 6.595239 |
module cass_30bit (
pout,
a,
pin,
cin
);
output [29:0] pout;
input [15:0] a;
input [28:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(c22),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
cass ca23 (
.pout(pout[22]),
.cout(c23),
.a(a[15]),
.pin(pin[21]),
.cin(c22)
);
cass ca24 (
.pout(pout[23]),
.cout(c24),
.a(a[15]),
.pin(pin[22]),
.cin(c23)
);
cass ca25 (
.pout(pout[24]),
.cout(c25),
.a(a[15]),
.pin(pin[23]),
.cin(c24)
);
cass ca26 (
.pout(pout[25]),
.cout(c26),
.a(a[15]),
.pin(pin[24]),
.cin(c25)
);
cass ca27 (
.pout(pout[26]),
.cout(c27),
.a(a[15]),
.pin(pin[25]),
.cin(c26)
);
cass ca28 (
.pout(pout[27]),
.cout(c28),
.a(a[15]),
.pin(pin[26]),
.cin(c27)
);
cass ca29 (
.pout(pout[28]),
.cout(c29),
.a(a[15]),
.pin(pin[27]),
.cin(c28)
);
cass ca30 (
.pout(pout[29]),
.cout(x),
.a(a[15]),
.pin(pin[28]),
.cin(c29)
);
endmodule
| 6.567409 |
module cass_31bit (
pout,
a,
pin,
cin
);
output [30:0] pout;
input [15:0] a;
input [29:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass ca8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass ca9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass ca10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass ca11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass ca12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass ca13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass ca14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass ca15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass ca16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass ca17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
cass ca18 (
.pout(pout[17]),
.cout(c18),
.a(a[15]),
.pin(pin[16]),
.cin(c17)
);
cass ca19 (
.pout(pout[18]),
.cout(c19),
.a(a[15]),
.pin(pin[17]),
.cin(c18)
);
cass ca20 (
.pout(pout[19]),
.cout(c20),
.a(a[15]),
.pin(pin[18]),
.cin(c19)
);
cass ca21 (
.pout(pout[20]),
.cout(c21),
.a(a[15]),
.pin(pin[19]),
.cin(c20)
);
cass ca22 (
.pout(pout[21]),
.cout(c22),
.a(a[15]),
.pin(pin[20]),
.cin(c21)
);
cass ca23 (
.pout(pout[22]),
.cout(c23),
.a(a[15]),
.pin(pin[21]),
.cin(c22)
);
cass ca24 (
.pout(pout[23]),
.cout(c24),
.a(a[15]),
.pin(pin[22]),
.cin(c23)
);
cass ca25 (
.pout(pout[24]),
.cout(c25),
.a(a[15]),
.pin(pin[23]),
.cin(c24)
);
cass ca26 (
.pout(pout[25]),
.cout(c26),
.a(a[15]),
.pin(pin[24]),
.cin(c25)
);
cass ca27 (
.pout(pout[26]),
.cout(c27),
.a(a[15]),
.pin(pin[25]),
.cin(c26)
);
cass ca28 (
.pout(pout[27]),
.cout(c28),
.a(a[15]),
.pin(pin[26]),
.cin(c27)
);
cass ca29 (
.pout(pout[28]),
.cout(c29),
.a(a[15]),
.pin(pin[27]),
.cin(c28)
);
cass ca30 (
.pout(pout[29]),
.cout(c30),
.a(a[15]),
.pin(pin[28]),
.cin(c29)
);
cass ca31 (
.pout(pout[30]),
.cout(x),
.a(a[15]),
.pin(pin[29]),
.cin(c30)
);
endmodule
| 7.017559 |
module booth_array_4bit (
prod,
a,
b
);
output [7:0] prod;
input [3:0] a, b;
wire cr1, cr2, cr3, cr4;
wire [3:0] mdr1, mdr2, mdr3, mdr4;
wire [3:0] poutr1;
wire [4:0] poutr2;
wire [5:0] poutr3;
wire [6:0] poutr4;
ctrl c1 (
.md (mdr1),
.cin(cr1),
.a (a),
.xi ({b[3], b[2]})
);
cass_4bit c4b1 (
.pout(poutr1),
.a(mdr1),
.pin(3'd0),
.cin(cr1)
);
ctrl c2 (
.md (mdr2),
.cin(cr2),
.a (a),
.xi ({b[2], b[1]})
);
cass_5bit c5b1 (
.pout(poutr2),
.a(mdr2),
.pin(poutr1),
.cin(cr2)
);
ctrl c3 (
.md (mdr3),
.cin(cr3),
.a (a),
.xi ({b[1], b[0]})
);
cass_6bit c6b1 (
.pout(poutr3),
.a(mdr3),
.pin(poutr2),
.cin(cr3)
);
ctrl c4 (
.md (mdr4),
.cin(cr4),
.a (a),
.xi ({b[0], 1'b0})
);
cass_7bit c7b1 (
.pout(poutr4),
.a(mdr4),
.pin(poutr3),
.cin(cr4)
);
assign prod = {poutr4[6], poutr4};
endmodule
| 7.16085 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_4bit (
pout,
a,
pin,
cin
);
output [3:0] pout;
input [3:0] a;
input [2:0] pin;
input cin;
wire c1, c2, c3;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(x),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
//cass ca5(.pout(pout[4]),.cout(x),.a(a[3]),.pin(pin[3]),.cin(c4));
//cass ca6(.pout(pout[5]),.cout(x),.a(a[3]),.pin(pin[4]),.cin(c5));
//cass ca7(.pout(pout[6]),.cout(x),.a(a[3]),.pin(pin[5]),.cin(c6));
endmodule
| 7.509654 |
module cass_5bit (
pout,
a,
pin,
cin
);
output [4:0] pout;
input [3:0] a;
input [3:0] pin;
input cin;
wire c1, c2, c3, c4;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(x),
.a(a[3]),
.pin(pin[3]),
.cin(c4)
);
//cass ca6(.pout(pout[5]),.cout(x),.a(a[3]),.pin(pin[4]),.cin(c5));
//cass ca7(.pout(pout[6]),.cout(x),.a(a[3]),.pin(pin[5]),.cin(c6));
endmodule
| 7.407323 |
module cass_6bit (
pout,
a,
pin,
cin
);
output [5:0] pout;
input [3:0] a;
input [4:0] pin;
input cin;
wire c1, c2, c3, c4, c5;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[3]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(x),
.a(a[3]),
.pin(pin[4]),
.cin(c5)
);
//cass ca7(.pout(pout[6]),.cout(x),.a(a[3]),.pin(pin[5]),.cin(c6));
endmodule
| 7.247962 |
module cass_7bit (
pout,
a,
pin,
cin
);
output [6:0] pout;
input [3:0] a;
input [5:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass ca3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass ca4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass ca5 (
.pout(pout[4]),
.cout(c5),
.a(a[3]),
.pin(pin[3]),
.cin(c4)
);
cass ca6 (
.pout(pout[5]),
.cout(c6),
.a(a[3]),
.pin(pin[4]),
.cin(c5)
);
cass ca7 (
.pout(pout[6]),
.cout(x),
.a(a[3]),
.pin(pin[5]),
.cin(c6)
);
endmodule
| 7.596903 |
module cass_16bit (
pout,
a,
pin,
cin
);
output [15:0] pout;
input [15:0] a, pin;
input cin;
cass c1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass c2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c1)
);
cass c3 (
.pout(pout[2]),
.cout(c3),
.a(a[2]),
.pin(pin[1]),
.cin(c2)
);
cass c4 (
.pout(pout[3]),
.cout(c4),
.a(a[3]),
.pin(pin[2]),
.cin(c3)
);
cass c5 (
.pout(pout[4]),
.cout(c5),
.a(a[4]),
.pin(pin[3]),
.cin(c4)
);
cass c6 (
.pout(pout[5]),
.cout(c6),
.a(a[5]),
.pin(pin[4]),
.cin(c5)
);
cass c7 (
.pout(pout[6]),
.cout(c7),
.a(a[6]),
.pin(pin[5]),
.cin(c6)
);
cass c8 (
.pout(pout[7]),
.cout(c8),
.a(a[7]),
.pin(pin[6]),
.cin(c7)
);
cass c9 (
.pout(pout[8]),
.cout(c9),
.a(a[8]),
.pin(pin[7]),
.cin(c8)
);
cass c10 (
.pout(pout[9]),
.cout(c10),
.a(a[9]),
.pin(pin[8]),
.cin(c9)
);
cass c11 (
.pout(pout[10]),
.cout(c11),
.a(a[10]),
.pin(pin[9]),
.cin(c10)
);
cass c12 (
.pout(pout[11]),
.cout(c12),
.a(a[11]),
.pin(pin[10]),
.cin(c11)
);
cass c13 (
.pout(pout[12]),
.cout(c13),
.a(a[12]),
.pin(pin[11]),
.cin(c12)
);
cass c14 (
.pout(pout[13]),
.cout(c14),
.a(a[13]),
.pin(pin[12]),
.cin(c13)
);
cass c15 (
.pout(pout[14]),
.cout(c15),
.a(a[14]),
.pin(pin[13]),
.cin(c14)
);
cass c16 (
.pout(pout[15]),
.cout(c16),
.a(a[15]),
.pin(pin[14]),
.cin(c15)
);
cass c17 (
.pout(pout[16]),
.cout(c17),
.a(a[15]),
.pin(pin[15]),
.cin(c16)
);
endmodule
| 6.689494 |
module booth_code_25_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [24:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [24:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 24:0] product;
reg sn;
// &Wires; @24
wire [ 24:0] A;
wire [2 : 0] code;
parameter SRC_WIDTH = 25;
// &CombBeg; @28
always @(code[2:0] or A[24:0]) begin
case (code[2:0])
3'b000: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
3'b001: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b010: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b011: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-2:0], 1'b0};
3'b100: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0], 1'b0};
3'b101: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end
// &CombBeg; @42
always @(A[24] or code[2:0]) begin
case (code[2:0])
3'b000: sn = 1'b1;
3'b001: sn = ~A[SRC_WIDTH-1];
3'b010: sn = ~A[SRC_WIDTH-1];
3'b011: sn = ~A[SRC_WIDTH-1];
3'b100: sn = A[SRC_WIDTH-1];
3'b101: sn = A[SRC_WIDTH-1];
3'b110: sn = A[SRC_WIDTH-1];
3'b111: sn = 1'b1;
default: sn = 1'bx;
endcase
// &CombEnd; @54
end
// &CombBeg; @56
always @(code[2:0]) begin
case (code[2:0])
3'b000: h[1:0] = 2'b00;
3'b001: h[1:0] = 2'b00;
3'b010: h[1:0] = 2'b00;
3'b011: h[1:0] = 2'b00;
3'b100: h[1:0] = 2'b10;
3'b101: h[1:0] = 2'b01;
3'b110: h[1:0] = 2'b01;
3'b111: h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end
// &ModuleEnd; @70
endmodule
| 6.7345 |
module booth_code_33_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [32:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [32:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 32:0] product;
reg sn;
// &Wires; @24
wire [ 32:0] A;
wire [2 : 0] code;
parameter SRC_WIDTH = 33;
// &CombBeg; @28
always @(A[32:0] or code[2:0]) begin
case (code[2:0])
3'b000: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
3'b001: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b010: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b011: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-2:0], 1'b0};
3'b100: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0], 1'b0};
3'b101: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end
// &CombBeg; @42
always @(A[32] or code[2:0]) begin
case (code[2:0])
3'b000: sn = 1'b1;
3'b001: sn = ~A[SRC_WIDTH-1];
3'b010: sn = ~A[SRC_WIDTH-1];
3'b011: sn = ~A[SRC_WIDTH-1];
3'b100: sn = A[SRC_WIDTH-1];
3'b101: sn = A[SRC_WIDTH-1];
3'b110: sn = A[SRC_WIDTH-1];
3'b111: sn = 1'b1;
default: sn = 1'bx;
endcase
// &CombEnd; @54
end
// &CombBeg; @56
always @(code[2:0]) begin
case (code[2:0])
3'b000: h[1:0] = 2'b00;
3'b001: h[1:0] = 2'b00;
3'b010: h[1:0] = 2'b00;
3'b011: h[1:0] = 2'b00;
3'b100: h[1:0] = 2'b10;
3'b101: h[1:0] = 2'b01;
3'b110: h[1:0] = 2'b01;
3'b111: h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end
// &ModuleEnd; @70
endmodule
| 7.463438 |
module booth_code_54_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [53:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [53:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 53:0] product;
reg sn;
// &Wires; @24
wire [ 53:0] A;
wire [2 : 0] code;
parameter SRC_WIDTH = 54;
// &CombBeg; @28
always @(code[2:0] or A[53:0]) begin
case (code[2:0])
3'b000: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
3'b001: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b010: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-1:0]};
3'b011: product[SRC_WIDTH-1:0] = {A[SRC_WIDTH-2:0], 1'b0};
3'b100: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-2:0], 1'b0};
3'b101: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b110: product[SRC_WIDTH-1:0] = {~A[SRC_WIDTH-1:0]};
3'b111: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'b0}};
default: product[SRC_WIDTH-1:0] = {SRC_WIDTH{1'bx}};
endcase
// &CombEnd; @40
end
// &CombBeg; @42
always @(code[2:0] or A[53]) begin
case (code[2:0])
3'b000: sn = 1'b1;
3'b001: sn = ~A[SRC_WIDTH-1];
3'b010: sn = ~A[SRC_WIDTH-1];
3'b011: sn = ~A[SRC_WIDTH-1];
3'b100: sn = A[SRC_WIDTH-1];
3'b101: sn = A[SRC_WIDTH-1];
3'b110: sn = A[SRC_WIDTH-1];
3'b111: sn = 1'b1;
default: sn = 1'bx;
endcase
// &CombEnd; @54
end
// &CombBeg; @56
always @(code[2:0]) begin
case (code[2:0])
3'b000: h[1:0] = 2'b00;
3'b001: h[1:0] = 2'b00;
3'b010: h[1:0] = 2'b00;
3'b011: h[1:0] = 2'b00;
3'b100: h[1:0] = 2'b10;
3'b101: h[1:0] = 2'b01;
3'b110: h[1:0] = 2'b01;
3'b111: h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
// &CombEnd; @68
end
// &ModuleEnd; @70
endmodule
| 7.580571 |
module Booth_ControlUnit (
input q0,
input q1,
output reg [1:0] BoothOp
);
always @(*) begin
$display("q1 = %b , q0=%b", q1, q0);
case ({
q1, q0
})
2'b01: begin
BoothOp = 2'b01;
$display("%b", BoothOp);
end
2'b10: begin
BoothOp = 2'b10;
$display("%b", BoothOp);
end
default: BoothOp = 2'b00;
endcase
end
endmodule
| 6.555426 |
module Booth_ControlUnit_tb;
// Inputs
reg q0;
reg q1;
wire [1:0] q1q0;
// Instantiate the Unit Under Test (UUT)
Booth_ControlUnit uut (
.q0 (q0),
.q1 (q1),
.q1q0(q1q0)
);
initial begin
// Initialize Inputs
q0 = 0;
q1 = 0;
#100;
q0 = 1;
q1 = 0;
#100;
q0 = 0;
q1 = 1;
#100;
q0 = 1;
q1 = 1;
#100;
// Add stimulus here
end
endmodule
| 6.555426 |
module: Booth_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Booth_ControlUnit_test;
// Inputs
reg q0;
reg q1;
// Outputs
wire [1:0] q1q0;
// Instantiate the Unit Under Test (UUT)
Booth_ControlUnit uut (
.q0(q0),
.q1(q1),
.BoothOp(q1q0)
);
initial begin
// Initialize Inputs
q0 = 0;
q1 = 0;
#100;
q0 = 1;
q1 = 0;
#100;
q0 = 0;
q1 = 1;
#100;
q0 = 1;
q1 = 1;
// Add stimulus here
end
endmodule
| 6.667857 |
module booth_cu (
input L,
input lsb,
output reg [1:0] booth_op
);
always @(*) begin
case ({
lsb, L
})
2'b01: begin
booth_op <= 2'b01;
end
2'b10: begin
booth_op <= 2'b10;
end
default: booth_op <= 2'b00;
endcase
end
endmodule
| 7.050264 |
module BOOTH_datapath (
output wire q0,
qm1,
eqz,
output wire [9:0] data_out,
input wire [4:0] data_in,
input wire LdA,
LdQ,
LdM,
clrA,
clrQ,
clrff,
sftA,
sftQ,
sftDff,
add_sub,
EnableALU,
clk,
LdCount,
decr
);
wire [4:0] A, M, Q, Z;
wire [3:0] LdCountValue;
wire [3:0] count;
assign eqz = ~|count;
assign data_out = {A, Q};
assign q0 = Q[0];
SHIFTREG1 REG_A (
A,
Z,
A[4],
clk,
LdA,
clrA,
sftA
);
//A[15] -sign of the register A to be carry forwarded for
//the next iterations after the shift right operation is
//performed.
SHIFTREG2 REG_Q (
Q,
LdCountValue,
data_in,
A[0],
clk,
LdQ,
clrQ,
sftQ
);
//A[0]- LSB of the register A which is to be shifted to
//the next register Q which stores the multiplier.
DFF QM1 (
qm1,
Q[0],
sftDff,
clk,
clrff
);
//the dff input is Q[0] which is the LSB of register Q
//the multiplier.
PIPO REG_M (
M,
data_in,
clk,
LdM
);
ALU AL (
Z,
A,
M,
add_sub,
EnableALU
);
COUNTER CN (
count,
LdCountValue,
decr,
LdCount,
clk
);
endmodule
| 6.79379 |
module booth_encoder (
Booth_b_DI,
Sel_1x_SO,
Sel_2x_SO,
Sel_sign_SO
);
input wire [2:0] Booth_b_DI;
output wire Sel_1x_SO;
output wire Sel_2x_SO;
output wire Sel_sign_SO;
wire Sel_xnor_S;
assign Sel_1x_SO = ^Booth_b_DI[1:0];
assign Sel_xnor_S = ~(^Booth_b_DI[2:1]);
assign Sel_2x_SO = ~(Sel_1x_SO | Sel_xnor_S);
assign Sel_sign_SO = Booth_b_DI[2];
endmodule
| 7.829276 |
module booth_encoder (
x,
single,
double,
neg
);
input [2:0] x;
output single, double, neg;
wire notx0, notx1, notx2, w0, w1;
not #(387.77, 363.86) not0 (notx0, x[0]);
not #(387.77, 363.86) not1 (notx1, x[1]);
not #(387.77, 363.86) not2 (notx2, x[2]);
xor #(350.51, 306.96) xor0 (single, x[0], x[1]);
assign neg = x[2];
assign #(452.43, 400.56) w0 = x[0] & x[1] & notx2;
assign #(452.43, 400.56) w1 = notx0 & notx1 & x[2];
or #(458.88, 449.74) or0 (double, w0, w1);
endmodule
| 7.829276 |
module booth_selector (
double,
shifted,
single,
y,
neg,
p
);
input double, shifted, single, y, neg;
output p;
assign #(1125.88, 1235.74) p = (neg ^ ((y & single) | (shifted & double)));
endmodule
| 7.153136 |
module ripple_carry_adder #(
parameter width = 4
) (
a,
b,
cin,
sum,
cout
);
input [width - 1:0] a, b;
input cin;
wire [width -1:0] c;
output [width - 1:0] sum;
output cout;
genvar i;
generate
for (i = 0; i < width; i = i + 1) begin : for_rca
case (i)
1'b0: full_adder fa (.a(a[i]), .b(b[i]), .cin(cin), .sum(sum[i]), .cout(c[i]));
default:
full_adder fa (.a(a[i]), .b(b[i]), .cin(c[i-1]), .sum(sum[i]), .cout(c[i]));
endcase
end
endgenerate
assign cout = c[width-1];
endmodule
| 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor #(350.51, 306.96) xor_1 (sum, a, b);
and #(452.43, 400.56) and_1 (cout, a, b);
endmodule
| 6.966406 |
module invert (
output ib,
input b
);
assign ib = ~b;
endmodule
| 7.953624 |
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921 |
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431 |
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532 |
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689 |
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479 |
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861 |
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291 |
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047 |
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557 |
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906 |
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259 |
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322 |
module fa (
input wire i0,
i1,
cin,
output wire sum,
cout
);
wire t0, t1, t2;
xor3 _i0 (
i0,
i1,
cin,
sum
);
and2 _i1 (
i0,
i1,
t0
);
and2 _i2 (
i1,
cin,
t1
);
and2 _i3 (
cin,
i0,
t2
);
or3 _i4 (
t0,
t1,
t2,
cout
);
endmodule
| 7.001699 |
module Adder (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire cout;
wire [7:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[2],
q[2]
);
fa fa4 (
a[3],
b[3],
q[2],
sum[3],
q[3]
);
fa fa5 (
a[4],
b[4],
q[3],
sum[4],
q[4]
);
fa fa6 (
a[5],
b[5],
q[4],
sum[5],
q[5]
);
fa fa7 (
a[6],
b[6],
q[5],
sum[6],
q[6]
);
fa fa8 (
a[7],
b[7],
q[6],
sum[7],
cout
);
endmodule
| 6.808429 |
module booth_substep (
input wire signed [7:0] a,
Q,
input wire signed q0,
input wire signed [7:0] m,
output reg signed [7:0] f8,
output reg signed [7:0] l8,
output reg cq0
);
wire [7:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
m,
subam
);
always @(*) begin
if (Q[0] == q0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = a[0];
f8 = a >> 1;
if (a[7] == 1) f8[7] = 1;
end else if (Q[0] == 1 && q0 == 0) begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = subam[0];
f8 = subam >> 1;
if (subam[7] == 1) f8[7] = 1;
end else begin
cq0 = Q[0];
l8 = Q >> 1;
l8[7] = addam[0];
f8 = addam >> 1;
if (addam[7] == 1) f8[7] = 1;
end
end
endmodule
| 6.761271 |
module booth_multiplier32 (
input wire clk,
input wire sync_rst,
input wire valid,
input wire [31:0] A,
input wire [31:0] B,
output wire [63:0] R,
output wire ready
);
// load and store A
reg [31:0] A_reg;
always @(posedge clk)
if (sync_rst) A_reg <= 32'b0;
else if (valid & ready) A_reg <= A;
else A_reg <= A_reg;
// load and store PART-SUM,B
reg [65:0] M;
wire [34:0] PARTSUM_load;
always @(posedge clk)
if (sync_rst) M <= 66'b0;
else if (valid & ready) M <= {33'b0, B, 1'b0};
else if ((~valid) & ready) M <= M;
else M <= {PARTSUM_load, M[32:2]};
// calculate PART-SUM, analyse M[2:0]
wire [34:0] A_ext;
assign A_ext = {A_reg[31], A_reg[31], A_reg[31], A_reg};
wire [34:0] M_ext;
assign M_ext = {M[65], M[65], M[65:33]};
wire [34:0] A_op;
assign A_op={35{(M[2:0]==3'b001)|(M[2:0]==3'b010)}} & A_ext |
{35{(M[2:0]==3'b011)}} & {A_ext[33:0],1'b0} |
{35{(M[2:0]==3'b100)}} & {~A_ext[33:0]+1'b1,1'b0} |
{35{(M[2:0]==3'b101)|(M[2:0]==3'b110)}} & (~A_ext+1'b1) ;
assign PARTSUM_load = M_ext + A_op;
// get RESULT
assign R = M[64:1];
reg start;
always @(posedge clk)
if (sync_rst) start <= 0;
else start <= valid & ready;
reg [3:0] count;
always @(posedge clk)
if (sync_rst) count <= 4'd0;
else if (start) count <= 4'd1;
else if (count == 5'd15) count <= 4'd0;
else if (count == 4'd0) count <= count;
else count <= count + 4'd1;
assign ready = (~(|count)) & (~start);
endmodule
| 6.943306 |
module booth_multiplier32_tb;
// Inputs
reg clk;
reg sync_rst;
reg valid;
reg signed [31:0] A;
reg signed [31:0] B;
reg [30:0] A_data;
reg [30:0] B_data;
// Outputs
wire [63:0] R;
wire ready;
// Instantiate the Unit Under Test (UUT)
booth_multiplier32 uut (
.clk(clk),
.sync_rst(sync_rst),
.valid(valid),
.A(A),
.B(B),
.R(R),
.ready(ready)
);
// Initial signals
initial
fork
clk = 0;
sync_rst = 0;
valid = 0;
A = 0;
B = 0;
#2 sync_rst = 1;
#8 sync_rst = 0;
#14 A_data = {$random} % (2 ** 31);
#14 A = {1'b0, A_data};
#14 B_data = {$random} % (2 ** 31);
#14 B = {1'b0, B_data};
#14 valid = 1;
#19 valid = 0;
#204 A_data = {$random} % (2 ** 31);
#204 A = {1'b0, A_data};
#204 B_data = {$random} % (2 ** 31);
#204 B = {1'b1, B_data};
#204 valid = 1;
#209 valid = 0;
#404 A_data = {$random} % (2 ** 31);
#404 A = {1'b1, A_data};
#404 B_data = {$random} % (2 ** 31);
#404 B = {1'b0, B_data};
#404 valid = 1;
#409 valid = 0;
#604 A_data = {$random} % (2 ** 31);
#604 A = {1'b1, A_data};
#604 B_data = {$random} % (2 ** 31);
#604 B = {1'b1, B_data};
#604 valid = 1;
#609 valid = 0;
#810 $stop;
join
// Clock signal
always #5 clk = ~clk;
// Auto check
wire signed [63:0] Mul;
assign Mul = A * B;
integer cycle;
initial cycle = 1;
always #200 cycle <= cycle + 1;
reg result;
initial begin
result = 1;
#805;
if (result) $display("SIMULATION SUCCEEDED!");
else $display("SIMULATION FAILED!");
end
always #200
if (Mul == R) $display("%ds: passed!", 200 * cycle);
else
fork
$display("%ds: Something wrong!", 200 * cycle);
result = 0;
join
endmodule
| 6.943306 |
module booth_multiplier_8bit (
A,
B,
P
);
input [7:0] A, B;
output [8:0] P;
full_adder_booth_encoded_8bit ROW_0 ();
full_adder_booth_encoded_8bit ROW_1 ();
full_adder_booth_encoded_8bit ROW_2 ();
full_adder_booth_encoded_8bit ROW_3 ();
full_adder_booth_encoded_8bit ROW_4 ();
full_adder_booth_encoded_8bit ROW_5 ();
full_adder_booth_encoded_8bit ROW_6 ();
full_adder_booth_encoded_8bit ROW_7 ();
endmodule
| 6.943306 |
module booth_multiplier_module (
input clk,
input rst_n,
input start_sig,
input [7:0] A,
input [7:0] B,
output done_sig,
output [15:0] product,
output [ 7:0] SQ_a,
output [ 7:0] SQ_s,
output [16:0] SQ_p
);
/*******************/
reg [3:0]i;
reg [7:0]a; //result of A
reg [7:0]s; //reverse result of A
reg [16:0]p; //operation register P=2*8+1=17
reg [3:0]n; //用来指示n(8)次循环
reg isDone;
/*******************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 4'd0;
a <= 8'd0;
s <= 8'd0;
p <= 17'd0; //p初始化为0
n <= 4'd0;
isDone <= 1'b0;
end else if (start_sig)
case (i)
0: begin
a <= A;
s <= (~A + 1'b1);
p <= {8'd0, B, 1'b0}; //填充P空间
i <= i + 1'b1;
end
1: //P空间操作
if (n == 8) begin
n <= 4'd0;
i <= 4'd3; //8次循环完成 跳到步骤3
end else if (p[1:0] == 2'b01) begin //+A
p <= {p[16:9] + a, p[8:0]};
i <= i + 1'b1;
end else if (p[1:0] == 2'b10) begin //-A
p <= {p[16:9] + s, p[8:0]};
i <= i + 1'b1;
end else i <= i + 1'b1;
2: //P空间移位
begin
p <= {p[16], p[16:1]}; //右移一位
n <= n + 1'b1; //记录一次操作
i <= 4'd1; //退回步骤1 继续循环
end
3: //求得计算结果
begin
isDone <= 1'b1;
i <= i + 1'b1;
end
4: begin
isDone <= 1'b0;
i <= 4'd0;
end
endcase
end
assign done_sig = isDone;
assign product = p[16:1];
assign SQ_a = a;
assign SQ_s = s;
assign SQ_p = p;
endmodule
| 6.943306 |
module booth_multiplier_module_improve (
input clk,
input rst_n,
input start_sig,
input [7:0] A,
input [7:0] B,
output done_sig,
output [15:0] product,
output [ 7:0] SQ_a,
output [ 7:0] SQ_s,
output [16:0] SQ_p
);
/*******************/
reg [3:0]i;
reg [7:0]a; //result of A
reg [7:0]s; //reverse result of A
reg [16:0]p; //operation register P=2*8+1=17
reg [3:0]n; //用来指示n(8)次循环
reg isDone;
reg [7:0]diff1; //临时储存P空间的±A操作结果
reg [7:0]diff2;
/*******************/
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 4'd0;
a <= 8'd0;
s <= 8'd0;
p <= 17'd0; //p初始化为0
n <= 4'd0;
isDone <= 1'b0;
end else if (start_sig)
case (i)
0: begin
a <= A;
s <= (~A + 1'b1);
p <= {8'd0, B, 1'b0}; //填充P空间
i <= i + 1'b1;
end
1,2,3,4,5,6,7,8: //P空间操作 + P空间移位
begin
diff1 = p[16:9] + a; //取得当前的即时计算结果
diff2 = p[16:9] + s; //because综合成"无延时的瞬态"组合逻辑电路
if (p[1:0] == 2'b01) p <= {diff1[7], diff1, p[8:1]}; //+A操作+右移一位
else if (p[1:0] == 2'b10) p <= {diff2[7], diff2, p[8:1]}; //-A操作+右移一位
else p <= {p[16], p[16:1]}; //无操作+右移一位
i <= i + 1'b1;
end
9:
begin //取得计算结果 -- 相当于在一个时钟(上步骤的每个态)完成了两个计算: 1.瞬态完成p±a 2.时钟沿作用下完成p>>1
isDone <= 1'b1;
i <= i + 1'b1;
end
10: begin
isDone <= 1'b0;
i <= 4'd0;
end
endcase
end
assign done_sig = isDone;
assign product = p[16:1];
assign SQ_a = a;
assign SQ_s = s;
assign SQ_p = p;
endmodule
| 6.943306 |
module booth_multiplier_module_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [7:0] A;
reg [7:0] B;
wire done_sig;
wire [15:0] product;
wire [7:0] SQ_a;
wire [7:0] SQ_s;
wire [16:0] SQ_p;
/*******************/
/*
booth_multiplier_module u1(
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.A(A),
.B(B),
.done_sig(done_sig),
.product(product),
.SQ_a(SQ_a),
.SQ_s(SQ_s),
.SQ_p(SQ_p)
);
*/
booth_multiplier_module_improve u2 (
.clk(clk),
.rst_n(rst_n),
.start_sig(start_sig),
.A(A),
.B(B),
.done_sig(done_sig),
.product(product),
.SQ_a(SQ_a),
.SQ_s(SQ_s),
.SQ_p(SQ_p)
);
/*******************/
initial begin
clk = 0;
rst_n = 0;
#500;
rst_n = 1;
forever #25 clk = ~clk;
end
/*******************/
reg [3:0] i;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
i <= 4'd0;
A <= 8'd0;
B <= 8'd0;
start_sig <= 1'b0;
end else
case (i)
0: // 2 * 4
if (done_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
A = 8'd2;
B = 8'd4;
end
1: // -4 * 5
if (done_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
A = 8'b1111_1100;
B = 8'd5;
end
2: // 36 * -8
if (done_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
A = 8'd36;
B = 8'b1111_1000;
end
3: // -127 * -127
if (done_sig) begin
start_sig <= 1'b0;
i <= i + 1'b1;
end else begin
start_sig <= 1'b1;
A = 8'b1000_0001;
B = 8'b1000_0001;
end
4: i <= 4'd4;
endcase
end
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
endmodule
| 6.943306 |
module Booth_multiplier_pipeline #(
parameter DATAWIDTH = 8
) (
input CLK,
input RSTn,
input [DATAWIDTH - 1 : 0] A,
input [DATAWIDTH - 1 : 0] B,
output [DATAWIDTH * 2 - 1 : 0] RESULT
);
wire [ DATAWIDTH * 2 : 0 ] P = { 8'b0, B, 1'b0 };
wire [ DATAWIDTH * 2 - 1 : 0] M = { ~A+1'b1, A};
wire [ DATAWIDTH * 2 : 0 ] P1;
wire [ DATAWIDTH * 2 - 1 : 0] M1;
wire [ DATAWIDTH * 2 : 0 ] P2;
wire [ DATAWIDTH * 2 - 1 : 0] M2;
wire [ DATAWIDTH * 2 : 0 ] P3;
wire [ DATAWIDTH * 2 - 1 : 0] M3;
wire [ DATAWIDTH * 2 : 0 ] P4;
wire [ DATAWIDTH * 2 - 1 : 0] M4;
wire [ DATAWIDTH * 2 : 0 ] P5;
wire [ DATAWIDTH * 2 - 1 : 0] M5;
wire [ DATAWIDTH * 2 : 0 ] P6;
wire [ DATAWIDTH * 2 - 1 : 0] M6;
wire [ DATAWIDTH * 2 : 0 ] P7;
wire [ DATAWIDTH * 2 - 1 : 0] M7;
wire [ DATAWIDTH * 2 : 0 ] P8;
wire [ DATAWIDTH * 2 - 1 : 0] M8;
operate I1 (
.CLK(CLK),
.RSTn(RSTn),
.P(P),
.M(M),
.P_out(P1),
.M_out(M1)
);
operate I2 (
.CLK(CLK),
.RSTn(RSTn),
.P(P1),
.M(M1),
.P_out(P2),
.M_out(M2)
);
operate I3 (
.CLK(CLK),
.RSTn(RSTn),
.P(P2),
.M(M2),
.P_out(P3),
.M_out(M3)
);
operate I4 (
.CLK(CLK),
.RSTn(RSTn),
.P(P3),
.M(M3),
.P_out(P4),
.M_out(M4)
);
operate I5 (
.CLK(CLK),
.RSTn(RSTn),
.P(P4),
.M(M4),
.P_out(P5),
.M_out(M5)
);
operate I6 (
.CLK(CLK),
.RSTn(RSTn),
.P(P5),
.M(M5),
.P_out(P6),
.M_out(M6)
);
operate I7 (
.CLK(CLK),
.RSTn(RSTn),
.P(P6),
.M(M6),
.P_out(P7),
.M_out(M7)
);
operate I8 (
.CLK(CLK),
.RSTn(RSTn),
.P(P7),
.M(M7),
.P_out(P8),
.M_out(M8)
);
assign RESULT = P8[16:1];
endmodule
| 7.922206 |
module booth_multiplier_tb;
// Declare inputs and outputs
reg clk, load, reset;
reg signed [7:0] a, b;
wire signed [15:0] product;
// Instantiate the Unit Under Test (UUT)
booth_multiplier multiplier (
.clk(clk),
.reset(reset),
.load(load),
.Mc(a),
.Mp(b),
.product(product)
);
initial begin
// Start the test and reset the multiplier to start condition
clk = 0;
reset = 1;
#10 reset = 0;
#10
// Example 1: multiplication of positive with positive number
$display(
"\nExample 1: Mc = 35 and Mp = 67"
);
a = 35;
b = 67;
load = 1;
#20 load = 0;
#90 $display("Product = %0d\n", product);
// Example 2: multiplication of positive with negative number
$display("\nExample 2: Mc = -79 and Mp = 43");
a = -79;
b = 43;
load = 1;
#20 load = 0;
#90 $display("Product = %0d\n", product);
// Example 3: multiplication of negative with positive number
$display("\nExample 3: Mc = 52 and Mp = -121");
a = 52;
b = -121;
load = 1;
#20 load = 0;
#90 $display("Product = %0d\n", product);
// Example 4: multiplication of negative with negative number
$display("\nExample 4: Mc = -19 and Mp = -98");
a = -19;
b = -98;
load = 1;
#20 load = 0;
#90 $display("Product = %0d\n", product);
$finish;
end
// Switch clock signal every 5 clock cycles
always #5 clk = !clk;
endmodule
| 6.943306 |
module test;
// Registers
reg clk;
reg en;
reg [7:0] A, B;
wire [15:0] Output; // The read data
wire ready;
// Initialize varibles
initial begin
#1 en = 0;
clk = 0;
A = 8'd129;
B = 8'd1;
#2 en = 1;
#15 en = 0;
#12 $finish;
end
// Monitoring the output
always @(clk) begin
if ($time % 2 != 0) begin
$display("\ntime=%8d\ten=%d\tclk=%d", $time, en, clk);
end
end
// Some module
booth_multiplier BOOTH1 (
.en(en),
.clk(clk),
.A(A),
.B(B),
.Output(Output),
.ready(ready)
);
//For the clock
always begin
#1 clk = !clk;
end
endmodule
| 6.888292 |
module
//===================================================================
module booth_multi_top (
clk,
rstn,
multiplier, //16bits
multiplicand, //32bits
Sum_result, //output [31:0] low [15:0] * [15:0] bits
Carry_result //output [31:0] high [15:0] * [31:16] bits
);
input clk;
input rstn;
input [15:0] multiplier;
input [31:0] multiplicand;
output [31:0] Sum_result, Carry_result;
//cnt_booth_multi delay
wire [31:0] Sum1,Sum2;
reg [31:0] sum1_delay,sum2_delay;
reg [15:0] sum2_delay2;
//instance
booth_32_16_wrapper #(.WIDTH (32) ) u_booth_32_16_wrapper (
.clk (clk ),
.rstn (rstn ),
.multiplier (multiplier ), //16bits
.multiplicand (multiplicand ), //32bits
.Sum_1 (Sum1 ), //output [31:0] low 16 * 16 bits
.Sum_2 (Sum2 ) //output [31:0] high 16 * 16 bits
);
//CSA_result
always @(posedge clk or negedge rstn) begin
if(!rstn)begin
sum1_delay <= 0;
sum2_delay <= 0;
sum2_delay2 <= 0;
end
else begin
sum1_delay <= Sum1;
sum2_delay <= Sum2;
sum2_delay2 <= sum2_delay[31:16];
end
end
//data aligment
assign Sum_result = sum1_delay;
assign Carry_result = {sum2_delay[15:0],sum2_delay2};
endmodule
| 7.574158 |
module Booth_Norm (
input [31:0] mulcand,
input [2:0] r4input,
input sign,
output [33:0] pp
);
wire [32:0] raw;
assign raw[32:0] = (r4input[1]^r4input[0] === 0)?
((r4input[2]^r4input[0] === 0)?0:{mulcand[31:0], 1'b0}):
((sign === 0)?{1'b0, mulcand[31:0]}:{mulcand[31], mulcand[31:0]});
genvar i;
generate
for (i = 0; i <= 32; i = i + 1) begin
assign pp[i] = raw[i] ^ r4input[2];
end
endgenerate
assign pp[33] = (sign === 0) ? r4input[2] : pp[32];
endmodule
| 6.762597 |
module booth_recode (
out,
mcand,
code
);
output reg [25:0] out;
input [24:0] mcand;
input [2:0] code;
always @(mcand, code)
case (code)
3'b000: out = 26'b0;
3'b001: out = {mcand[24], mcand};
3'b010: out = {mcand[24], mcand};
3'b011: out = {mcand, 1'b0};
3'b100: out = -{mcand, 1'b0};
3'b101: out = -{mcand[24], mcand};
3'b110: out = -{mcand[24], mcand};
3'b111: out = 26'b0;
endcase
endmodule
| 6.587652 |
module booth_recoded_multiplier (
clk,
reset,
multiplicand,
multiplier,
prod
);
//Input
input clk; // Clock
input reset; // Reset
input [11:0] multiplicand, multiplier;
//Output
output [23:0] prod;
//Wire
wire [11:0] A, B, A_2comp, B_2comp;
wire [17:0] enc_op;
wire [ 5:0] cor_bit;
wire [84:0] pp;
wire [23:0] out_x, out_y, sum, sumBuf;
wire cout;
//DFF
reg_N #(12) reg12_00 (
reset,
clk,
multiplicand,
A
);
reg_N #(12) reg12_01 (
reset,
clk,
multiplier,
B
);
reg_N #(24) reg24_00 (
reset,
clk,
{A[11] ^ B[11], sum[22:0]},
prod
);
//Binary to 2's complement conversion
bin2comp #(12) bin00 (
A,
A_2comp
);
bin2comp #(12) bin01 (
B,
B_2comp
);
bin2comp #(24) bin02 (
{A[11] ^ B[11], sumBuf[22:0]},
sum
);
//Booth Encoder for Multiplier
boothEnNBits #(12) booth_enc00 (
B_2comp,
enc_op
);
//Partial Product Generator
ppGenNBits #(12) pp_gen00 (
enc_op,
A_2comp,
pp,
cor_bit
);
//Summation of Partial Product
ppCompressor_12 pp_comp (
pp,
cor_bit,
out_x,
out_y
);
//Carry Look-ahead Adder
cla_24bit cla00 (
out_x,
out_y,
1'b0,
sumBuf,
cout
);
endmodule
| 6.624849 |
module
//===================================================================
`timescale 1ns / 1ps
`include "booth_recoded_multiplier.v"
module booth_recoded_multiplier_tb();
// Inputs
reg clk;
reg reset;
reg [11:0] multiplicand;
reg [11:0] multiplier;
// Outputs
wire [23:0] prod;
// Instantiate the Unit Under Test (UUT)
booth_recoded_multiplier uut (
.clk(clk),
.reset(reset),
.multiplicand(multiplicand),
.multiplier(multiplier),
.prod(prod)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
multiplicand = 0;
multiplier = 0;
#5 reset = 0;
end
initial begin
//Case 1: multiplicand = 25; multiplier = 15;
#8 multiplicand = 25; multiplier = 15;
//Case 2: multiplicand = -30; multiplier = -40;
#8 multiplicand = -30; multiplier = -40;
//Case 3: multiplicand = -25; multiplier = 30;
#8 multiplicand = -25; multiplier = 30;
//Case 4: multiplicand = 30; multiplier = -15;
#8 multiplicand = 30; multiplier = -15;
//Case 5: multiplicand = 100; multiplier = 3;
#8 multiplicand = 100; multiplier = 3;
//Case 6: multiplicand = 80; multiplier = -56;
#8 multiplicand = 80; multiplier = -56;
//finish
#8 $finish;
end
always @(*) begin
#4 clk = ~clk;
end
initial begin
$monitor("time %3d: %12b %12b %24b",$time,multiplicand,multiplier,prod);
end
endmodule
| 7.574158 |
module booth_selector (
Booth_a_DI,
Sel_1x_SI,
Sel_2x_SI,
Sel_sign_SI,
Booth_pp_DO
);
input wire [1:0] Booth_a_DI;
input wire Sel_1x_SI;
input wire Sel_2x_SI;
input wire Sel_sign_SI;
output wire Booth_pp_DO;
assign Booth_pp_DO = ~(~((Sel_1x_SI && Booth_a_DI[1]) | (Sel_2x_SI && Booth_a_DI[0])) ^ Sel_sign_SI);
endmodule
| 7.153136 |
module booth_signed_multiplier_16 (
product,
A,
B
);
input signed [15:0] A, B;
output signed [31:0] product;
reg [31:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] B1;
always @(*) begin
product = 32'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 16; i = i + 1) begin
temp = {A[i], E1};
case (temp)
2'd2: product[31:16] = product[31:16] + B1;
2'd1: product[31:16] = product[31:16] + B;
default: begin
end
endcase
product = product >> 1; // Logical Shift Right
product[31] = product[30]; // Preserve the sign bit
E1 = A[i];
end
if (B == 16'd32) begin
product = -product;
end
end
endmodule
| 7.22283 |
module booth_signed_multiplier_4 (
product,
A,
B
);
input signed [3:0] A, B;
output signed [7:0] product;
reg [7:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [3:0] B1;
always @(*) begin
product = 8'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 4; i = i + 1) begin
temp = {A[i], E1};
case (temp)
2'd2: product[7:4] = product[7:4] + B1;
2'd1: product[7:4] = product[7:4] + B;
default: begin
end
endcase
product = product >> 1; // Logical Shift Right
product[7] = product[6]; // Preserve the sign bit
E1 = A[i];
end
if (B == 4'd8) begin
product = -product;
end
end
endmodule
| 7.22283 |
module booth_signed_multiplier_8 (
product,
A,
B
);
input signed [7:0] A, B;
output signed [15:0] product;
reg [15:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [7:0] B1;
always @(*) begin
product = 16'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 8; i = i + 1) begin
temp = {A[i], E1};
case (temp)
2'd2: product[15:8] = product[15:8] + B1;
2'd1: product[15:8] = product[15:8] + B;
default: begin
end
endcase
product = product >> 1; // Logical Shift Right
product[15] = product[14]; // Preserve the sign bit
E1 = A[i];
end
if (B == 8'd16) begin
product = -product;
end
end
endmodule
| 7.22283 |
module: booth
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module booth_tb;
// Inputs
reg [24:0] x;
reg [24:0] y;
// Outputs
wire [49:0] p;
// Instantiate the Unit Under Test (UUT)
booth uut (
.p(p),
.x(x),
.y(y)
);
initial begin
// Initialize Inputs
x = 0;
y = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x = 25'd5;
y = 25'd6;
#20;
x = 25'h777777;
y = 25'b0101010111101;
#20;
x = 25'd19;
y = 25'hff;
#20;
x = 25'd49;
y = 25'hff00ff;
#20;
x = 24'b111101100000000000000000;
y = 24'b111101100000000000000000;
#20;
$display("%b * %b = %b", x, y, p, $time);
#20;
x = 24'hffffff;
y = 24'hffffff;
#20;
$display("%b * %b = %b", x, y, p, $time);
#20;
x = 24'd18;
y = 24'd982;
#20;
$display("%b * %b = %b", x, y, p, $time);
#20;
x = 24'd194;
y = 24'd0911;
#20;
$display("%b * %b = %b", x, y, p, $time);
#20;
x = -25'b1;
y = -25'b1;
#20;
$display("%b * %b = %b", x, y, p, $time);
#20;
x = -25'b1;
y = 25'b1;
#20;
$display("%b * %b = %b", x, y, p, $time);
end
endmodule
| 6.559363 |
module eight_bit_adder_subractor (
input wire cin,
input wire [7:0] i0,
i1,
output wire [7:0] sum
);
wire cout;
wire [7:0] temp;
wire [7:0] int_ip; //intermediate input - processed from the inputs and fed into fa module
//if cin == 1, int_ip = 1's complement
//else int_ip = i1
xor2 x0 (
i1[0],
cin,
int_ip[0]
);
xor2 x1 (
i1[1],
cin,
int_ip[1]
);
xor2 x2 (
i1[2],
cin,
int_ip[2]
);
xor2 x3 (
i1[3],
cin,
int_ip[3]
);
xor2 x4 (
i1[4],
cin,
int_ip[4]
);
xor2 x5 (
i1[5],
cin,
int_ip[5]
);
xor2 x6 (
i1[6],
cin,
int_ip[6]
);
xor2 x7 (
i1[7],
cin,
int_ip[7]
);
//if cin == 1, cin added to make two's complement
//else addition takes place
fa fa1 (
i0[0],
int_ip[0],
cin,
sum[0],
temp[0]
);
fa fa2 (
i0[1],
int_ip[1],
temp[0],
sum[1],
temp[1]
);
fa fa3 (
i0[2],
int_ip[2],
temp[1],
sum[2],
temp[2]
);
fa fa4 (
i0[3],
int_ip[3],
temp[2],
sum[3],
temp[3]
);
fa fa5 (
i0[4],
int_ip[4],
temp[3],
sum[4],
temp[4]
);
fa fa6 (
i0[5],
int_ip[5],
temp[4],
sum[5],
temp[5]
);
fa fa7 (
i0[6],
int_ip[6],
temp[5],
sum[6],
temp[6]
);
fa fa8 (
i0[7],
int_ip[7],
temp[6],
sum[7],
cout
);
endmodule
| 7.124161 |
module booth_substep (
input wire signed [7:0] acc, //Current value of accumulator
input wire signed [7:0] Q, //Current value of Q (initially the multiplier)
input wire signed q0, //Current value of q-1 th bit
input wire signed [7:0] multiplicand, //the multipliand
output reg signed [7:0] next_acc, //next accumulator value || value of 8 MSB's of 16 bit output [17:8]
output reg signed [7:0] next_Q, //Next value of Q || value of 8 LSB's of 16 bit output [7:0]
output reg q0_next
);
wire [7:0] addsub_temp; //next value of q_-1 th bit
eight_bit_adder_subractor myadd (
Q[0],
acc,
multiplicand,
addsub_temp
);
always @(*) begin
if (Q[0] == q0) begin
q0_next = Q[0];
next_Q = Q >> 1;
next_Q[7] = acc[0];
//right shift
next_acc = acc >> 1;
//with sign extension
if (acc[7] == 1) next_acc[7] = 1;
end else begin //if Q[0] != q0 (that is, q_-1 bit)
q0_next = Q[0];
next_Q = Q >> 1;
next_Q[7] = addsub_temp[0];
//right shift
next_acc = addsub_temp >> 1;
//with sign extension
if (addsub_temp[7] == 1) next_acc[7] = 1;
end
end
endmodule
| 6.761271 |
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