code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module OAI33D2HVT (
A1,
A2,
A3,
B1,
B2,
B3,
ZN
);
input A1, A2, A3, B1, B2, B3;
output ZN;
or (A, A1, A2, A3);
or (B, B1, B2, B3);
nand (ZN, A, B);
specify
(A1 => ZN) = (0, 0);
(A2 => ZN) = (0, 0);
(A3 => ZN) = (0, 0);
(B1 => ZN) = (0, 0);
(B2 => ZN) = (0, 0)... | 6.579591 |
module OAI33D4HVT (
A1,
A2,
A3,
B1,
B2,
B3,
ZN
);
input A1, A2, A3, B1, B2, B3;
output ZN;
or (A, A1, A2, A3);
or (B, B1, B2, B3);
nand (ZN, A, B);
specify
(A1 => ZN) = (0, 0);
(A2 => ZN) = (0, 0);
(A3 => ZN) = (0, 0);
(B1 => ZN) = (0, 0);
(B2 => ZN) = (0, 0)... | 6.723295 |
module OR2D0HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.818015 |
module OR2D1HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.093008 |
module OR2D2HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.375407 |
module OR2D4HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.088539 |
module OR2D8HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.019447 |
module OR2XD1HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.419713 |
module OR3D1HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 6.774595 |
module OR3D2HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 7.168888 |
module OR3D4HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 7.225882 |
module OR3XD1HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 6.725959 |
module OR4D0HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.791091 |
module OR4D1HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.98472 |
module OR4D2HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 7.161565 |
module OR4D4HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 7.116772 |
module OR4D8HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.686429 |
module OR4XD1HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.88515 |
module cr_tcipif_dummy_bus (
bmu_tcipif_ibus_acc_deny,
bmu_tcipif_ibus_addr,
bmu_tcipif_ibus_req,
bmu_tcipif_ibus_write,
cpurst_b,
forever_cpuclk,
pad_yy_gate_clk_en_b,
tcipif_bmu_ibus_acc_err,
tcipif_bmu_ibus_data,
tcipif_bmu_ibus_data_vld,
tcipif_bmu_ibus_grnt,
tcipif_b... | 7.807747 |
module tcm_controller (
input wire clk,
input wire rstn,
input wire [$clog2(`TCM_SIZE)-1:0] addr,
input wire w_rb,
input wire [ `BUS_ACC_WIDTH-1:0] acc,
output reg [ `BUS_WIDTH-1:0] rdata,
input wire [ `BUS_WIDTH-1:0] wdata,
input wire ... | 6.865106 |
module tcm_mem_pmem_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//---------------------------------------------------------------... | 6.878785 |
module tcm_mem_ram (
// Inputs
input clk_i
, input rst_i
, input [13:0] addr0_i
, input [31:0] data0_i
, input [ 3:0] wr0_i
, input [13:0] addr1_i
// Outputs
, output [31:0] data0_o
, output [31:0] data1_o
);
//-------------------------------------------------... | 7.439146 |
module tcm_mem_ram (
// Inputs
input clk0_i
, input rst0_i
, input [13:0] addr0_i
, input [31:0] data0_i
, input [ 3:0] wr0_i
, input clk1_i
, input rst1_i
, input [13:0] addr1_i
, input [31:0] data1_i
, input [ 3:0] wr1_i
// Outputs
, o... | 7.439146 |
module tcm_wrapper (
input wire clk,
input wire rstn,
// data bus interface
input wire [ `XLEN-1:0] d_addr, // byte addr
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
output wire [ `BUS_WIDTH-1:0] d_rdata,
input... | 6.955985 |
module tcon (
input wire CLK120, // 120 MHz clock
output reg CKV_, // Clock
output reg STV_, // STV[D|U]
output reg OEV_, // OE Vertical
output reg STH_, // STH[L|R]
output reg OEH_, // OE Horizontal
output wire CPH1_, // CPH
output wire CLK10_, // 10MHz clock
output reg [... | 7.756165 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/tcon_comb/tcon_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
s_pad,
t_pad,
u_pad,
v_pad,
w_pad,
x_pad,
y_pad,
z_pad,
a0_pad,
... | 6.939825 |
module Tcounter_tb ();
reg clk;
reg restn;
reg enable;
wire [3:0] Q;
Tcounter #(5) counter (
enable,
restn,
clk,
Q
);
always begin
clk = 0;
#10 clk = 1;
forever #50 clk = ~clk;
end
initial begin
restn = 0;
enable = 0;
#10 restn = 1;
enable = 1;
... | 7.163737 |
module tcPreset (
tcPresetEn,
presetIn,
tcAddr,
presetOut
);
input tcPresetEn;
input [`tcPresetLen-1:0] presetIn;
input [`tcAddrLen-1:0] tcAddr;
output [(`tcPresetLen*`tcNumbers)-1:0] presetOut;
reg [`tcPresetLen-1:0] presets[`tcNumbers-1:0];
always @(posedge tcPresetEn) begin
if (t... | 7.423486 |
module tcp_check #(
parameter SRC_PORT = 16'h0400,
parameter DES_PORT = 16'h00aa
) (
input clk,
input reset,
input [31:0] tcp_data_in,
input tcp_data_valid,
output reg tcp_error_out
);
localparam IDLE_s = 2'b00;
localparam HEADER_s = 2'b01;
localparam DATA_s = 2'b11;
localparam END_... | 6.637453 |
module Tcp_test;
// Inputs
reg CLOCK = 0;
reg paused = 1;
wire available;
wire [7:0] pktcount;
wire streamvalid;
wire [7:0] stream;
wire pcapfinished;
wire newpkt;
wire [7:0] tcpdata1, tcpdata2;
wire tcpdataValidA;
wire tcpdataValidB;
// Instantiate the Unit Under Test (UUT)
PcapParser #(... | 6.796265 |
module tcrc_cell2 (
input wire enable,
input wire preload,
input wire clock,
input wire reset,
input wire load,
input wire Input,
output wire q
);
//tmrg default triplicate
//tmrg tmr_error false
reg q_i;
//triplication signals
wire q_iVoted = q_i;
assign q = q_iVoted;
... | 7.498852 |
module tcrc2 (
input wire clock,
input wire bitin,
input wire activ,
input wire reset,
input wire [14:0] crc_pre_load_ext,
input wire [14:0] crc_pre_load_rem,
input wire extended,
input wire load,
input wire load_activ,
in... | 7.645063 |
module tcReset (
tcResetEn,
resetIn,
tcAddr,
resetOut
);
input tcResetEn, resetIn;
input [`tcAddrLen-1:0] tcAddr;
output [`tcNumbers-1:0] resetOut;
reg [`tcNumbers-1:0] resets;
always @(posedge tcResetEn) begin
if (tcResetEn) begin
resets[tcAddr] = resetIn;
end
end
assi... | 7.414333 |
module tcsm_smtc (
in,
out
);
parameter nob = 4;
input [nob:0] in;
output [nob:0] out;
wire [nob:0] in_c, tc;
assign in_c = ~in;
assign tc = in_c + 1;
assign out = in[4] ? tc : in;
endmodule
| 7.205662 |
module tcu (
input clk,
n_Rst,
input byte_send, //data is sent
input start_trans, //signal from the debugger to start transmitting
input start_send,
output reg enable_count, //counts the number of bits that is sent out
output reg enable_start,
output reg tx_enable,
output reg star... | 7.620568 |
module Tcustom1Rcustom_look_ahead_routing #(
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4
) (
reset,
clk,
current_r_addr,
dest_e_addr,
src_e_addr,
destport
);
input [RAw-1 : 0] current_r_addr;
input [EAw-1 : 0] dest_e_addr;
input [EAw-1 : 0] src_e_addr;
outp... | 7.316693 |
module Tcustom1Rcustom_look_ahead_routing_genvar #(
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4,
parameter CURRENT_R_ADDR = 0
) (
dest_e_addr,
src_e_addr,
destport,
reset,
clk
);
input [EAw-1 : 0] dest_e_addr;
input [EAw-1 : 0] src_e_addr;
output [DSTPw-1 : 0] de... | 7.316693 |
module tcu_ctrl_reset (
input wire clk_i,
input wire reset_n_i,
output wire reset_sync_n_o,
input wire tcu_reset_i
);
reg r_tcu_reset, rin_tcu_reset;
reg [3:0] r_tcu_reset_count, rin_tcu_reset_count;
always @(posedge clk_i or negedge reset_n_i) begin
if (reset_n_i == 1'b0) begin
r... | 6.59883 |
module tcu_priv_timer #(
parameter TIMER_SIZE = 32,
parameter CLKFREQ_MHZ = 100
) (
input wire clk_i,
input wire reset_n_i,
input wire timer_value_valid_i,
input wire [TIMER_SIZE-1:0] timer_value_i,
input wire timer_int_stall_i,
output reg timer_int_valid_o //trig... | 8.038579 |
module tc_clock_generator_fmax (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h00;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inve... | 7.250333 |
module tc_clock_generator_fmin (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h7f;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inve... | 7.250333 |
module tc_clock_generator_h01 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h01;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h02 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h02;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h04 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h04;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h08 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h08;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h10 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h10;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h20 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h20;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h30 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h30;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h38 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h38;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h3b (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h3b;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h3c (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h3c;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_clock_generator_h40 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h40;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inver... | 7.250333 |
module tc_counter (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin
... | 7.607854 |
module tc_ds1wm (
ADDR,
ADS_N,
CLK,
EN_N,
RD_N,
WR_N,
MR,
INTR,
DATA,
IO,
STPZ
);
output [2:0] ADDR;
output ADS_N;
output CLK;
output EN_N;
output RD_N;
output WR_N;
output MR;
input INTR;
inout [7:0] DATA;
inout IO;
input STPZ;
reg MR;
`ifd... | 6.591918 |
module tc_heartbeat (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begi... | 7.636051 |
module tc_prescaler (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begi... | 7.768142 |
module tc_shiftreg (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin... | 7.859092 |
module part_TD25 (
INPUT,
O_5ns,
O_10ns,
O_15ns,
O_20ns,
O_25ns
);
input INPUT;
output O_5ns, O_10ns, O_15ns, O_20ns, O_25ns;
reg O_5ns, O_10ns, O_15ns, O_20ns, O_25ns;
initial begin
O_5ns <= 0;
O_10ns <= 0;
O_15ns <= 0;
O_20ns <= 0;
O_25ns <= 0;
end
always @(p... | 6.781923 |
module: TD4_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`default_nettype none
module TD4_test;
// Inputs
reg clock;
reg reset;
reg [3:0] sw;
// Outputs
wi... | 7.147029 |
module TD4_top (
clock,
reset,
sw,
LED
);
input clock, reset;
input [3:0] sw;
output [3:0] LED;
wire [3:0] ip; //instruction pointer
wire [7:0] ramdata; //ramo
TD4_core TD4_core0 (
.clock(clock),
.reset(reset),
.sw(sw),
.LED(LED),
.ip(ip),
.ramdata(ra... | 6.998169 |
module ram16 (
addr,
data
);
input [3:0] addr;
output [7:0] data;
//ram
wire [7:0] ram[15:0];
assign data = ram[addr];
assign ram[0] = 8'b10110111;
assign ram[1] = 8'b00000001;
assign ram[2] = 8'b11100001;
assign ram[3] = 8'b00000001;
assign ram[4] = 8'b11100011;
assign ram[5] = 8'b1011... | 7.26066 |
module tdata_m3_for_arty_a7_axis_broadcaster_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 8,
parameter C_M_AXIS_TDATA_WIDTH = 8
) (
input wire [C_S_AXIS_TDATA_WIDTH-1:0] tdata,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[7:0], tdata[7:0]};
endmodule
| 8.718377 |
module tdata_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 8.718377 |
module tdata_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 8.718377 |
module tdata_mov_obj_det_axis_subset_converter_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_W... | 6.972496 |
module tdata_mov_obj_det_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_W... | 6.972496 |
module tdata_system_axis_subset_converter_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)... | 7.827217 |
module TDC (
input clk,
input start,
input stop,
input reset,
output reg [39:0] data,
output reg valid
);
wire [9:0] fine1_out;
wire [9:0] fine2_out;
wire [15:0] course_out;
wire coarse_done;
reg set;
wire or_reset;
wire fine1_stop;
wire fine2_stop;
or (or_reset, set, reset)... | 7.096077 |
module TdcFifo_1024x8 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull
);
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output rdfull;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] ... | 6.58075 |
module TdcFifo_1024x8 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull
);
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output rdfull;
endmodule
| 6.58075 |
module TdcTestBench;
parameter master_ck_period = 25;
parameter master_ck_half_period = master_ck_period / 2;
parameter master_ck_hold = 1; // data hold time
parameter fast_ck_period = 4;
parameter fast_ck_half_period = fast_ck_period / 2;
parameter fast_ck_hold = 0.5; // data hold time
reg Master_cl... | 6.673967 |
module TDC_DeltaT_1Chan #(
parameter WORDSIZE = 16,
parameter CNTSIZE = 38
) (
input CH1,
input [CNTSIZE-1:0] cnt,
input clk,
input rst,
output [WORDSIZE-1:0] outData,
output wrEn
);
reg [CNTSIZE-1:0] last1_d, last1_q; //last time point registers
reg wrEn_d, wrEn_q; //write enabl... | 7.313546 |
module: Two_Digit_Counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TDC_test;
// Inputs
reg clk;
reg rst;
// Outputs
wire [6:0] seg_1;
wire [6:0] seg_10;
// Instantia... | 6.826338 |
module TDC_TOP (
input iCLK,
input iRST,
input iHIT,
//DEBUG OUTPUTS
//output [`NUM_STAGES-1:0] oTHERMOMETERSTART,
//output [`NUM_STAGES-1:0] oTHERMOMETERSTOP,
//END OF DEBUG OUTPUTS
output oVALUEREADY,
//output [`COARSE_BITS-1:0] oCOARSEARBITERVALUE,
output [`NUM_OUTPUT_BITS-1:0... | 7.854513 |
module tDecoder;
reg [15:0] instruction;
reg clk, reset, IR;
//start signals
wire ALUstr, MOVstr, LDSRstr;
wire [3:0] opCode;
//decoder control signals
wire IRiEn, IRjEn;
reg BRjEn, IF;
// Register signals
wire [ 3:0] index;
wire [15:0] bus;
decoder D (
IR,
instruction,
AL... | 6.910868 |
module tdest_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDEST_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 6.91769 |
module tdest_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDEST_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 6.91769 |
module RX (
input wire HCLK,
input wire HRESETn,
input wire SCK,
input wire SDI,
output wire [31:0] DATA,
output wire BRCK,
output wire BWCK
);
localparam ST_S0 = 4'b0001,
ST_S1 = 4'b0010,
ST_S2 = 4'b... | 7.66798 |
module tdl (
input en,
input clk,
input trigI,
output [3:0] counter_value
);
tdl_on_slice seg0 (
.en(en),
.clk(clk),
.and_gate0_I0(trigI),
.counter_value(counter_value[3:0])
);
endmodule
| 7.859092 |
module tdl_on_slice (
input en,
input clk,
input and_gate0_I0,
output cascade_out,
output [3:0] counter_value
);
wire [3:0] and_to_fd;
(* s = "true" *) AND2 and_gate0 (
.O (and_to_fd[0]),
.I0(and_gate0_I0),
.I1(en)
);
(* s = "true" *) AND2 and_gate1 (
.O (and_to_fd[... | 6.621552 |
module tdm (
num,
an,
num1,
num2,
num3,
num4,
clk
);
output reg [3:0] num;
output reg [3:0] an;
// hex inputs
input [3:0] num1;
input [3:0] num2;
input [3:0] num3;
input [3:0] num4;
input clk;
reg [1:0] counter;
reg cout;
initial begin
counter = 3'b000;
end
a... | 6.815959 |
module tdm_gen (
input bclk,
input wclk,
output tdm_out
);
reg [1:0] wc_ff;
reg [5:0] bclk_cnt;
parameter FIX_DATA = 32'hABCD0000;
assign tdm_out = FIX_DATA[bclk_cnt[4:0]];
always @(posedge bclk) begin
wc_ff <= {wc_ff[0], wclk};
end
always @(negedge bclk) begin
if (wc_ff == 2'b01)... | 7.082334 |
module tdm_input (
input mclk,
input [7:0] cnt256_n,
input tdm_in,
output reg [15:0] ch1_out,
output reg [15:0] ch2_out
);
reg [63:0] data_reg;
always @(posedge mclk) begin
if (cnt256_n == 8'd0) begin
//VtgWX^̃f[^Oɏo
ch1_out <= data_reg[63:48];
ch2_out <= data_reg[31:16];
... | 6.532695 |
module Tdot (
input wire clk,
input wire reset,
input wire [7:0] a0,
input wire [7:0] a1,
input wire [7:0] a2,
input wire [7:0] b0,
input wire [7:0] b1,
input wire [7:0] b2,
input wire [7:0] c,
output wire [7:0] y
);
top t (
.clk(clk),
.reset(reset),
.a0(a0),... | 8.210756 |
module tdo_mux (
input TDO_0C,
input TDO_17,
input [32:0] FSEL,
output reg TDO
);
always @(TDO_0C or TDO_17 or FSEL)
case (FSEL)
33'h000001000: TDO <= TDO_0C;
33'h000800000: TDO <= TDO_17;
default: TDO <= 1'b0;
endcase
endmodule
| 7.233606 |
module true_dual_port_ram_readfirst_reg1 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
... | 9.063194 |
module true_dual_port_ram_readfirst_reg2 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
... | 9.063194 |
module true_dual_port_ram_writefirst_reg1 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
... | 9.063194 |
module true_dual_port_ram_writefirst_reg2 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
... | 9.063194 |
module tdt_dmi_pulse_sync #(
parameter SYNC_NUM = 2
) (
input src_clk,
input dst_clk,
input src_rst_b,
input dst_rst_b,
input src_pulse,
output dst_pulse
);
reg src_pulse_2_lvl;
wire dst_lvl;
reg dst_lvl_d;
wire dst_lvl_src;
reg dst_lvl_src_d;
wire dst_pulse_2_src;
alw... | 6.996321 |
module tdt_dmi_rst_top (
sys_apb_clk,
sys_apb_rst_b,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
sync_sys_apb_rst_b
);
input sys_apb_clk;
input sys_apb_rst_b;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
output sync_sys_apb_rst_b;
wire sync_sys_apb_rst_b;
wire async_apb_rst_b;
reg sy... | 6.717745 |
module tdt_dmi_sync_dff #(
parameter SYNC_NUM = 2
) (
input dst_clk,
input dst_rst_b,
input src_in,
output dst_out
);
reg [SYNC_NUM-1:0] sync_ff;
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) sync_ff[SYNC_NUM-1:0] <= {SYNC_NUM{1'b0}};
else sync_ff[SYNC_NUM-1:0... | 6.782225 |
module tdt_dm_pulse_sync #(
parameter SYNC_NUM = 2
) (
input src_clk,
input dst_clk,
input src_rst_b,
input dst_rst_b,
input src_pulse,
output dst_pulse
);
reg src_pulse_2_lvl;
wire dst_lvl;
reg dst_lvl_d;
wire dst_lvl_src;
reg dst_lvl_src_d;
wire dst_pulse_2_src;
alwa... | 7.389619 |
module tdt_dm_sync_dff #(
parameter SYNC_NUM = 2
) (
input dst_clk,
input dst_rst_b,
input src_in,
output dst_out
);
reg [SYNC_NUM-1:0] sync_ff;
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) sync_ff[SYNC_NUM-1:0] <= {SYNC_NUM{1'b0}};
else sync_ff[SYNC_NUM-1:0]... | 7.288187 |
module tdt_dtm_io (
input pad_dtm_jtag2_sel,
input pad_dtm_tap_en,
input pad_dtm_tdi,
input pad_dtm_tms_i,
output dtm_pad_tdo,
output dtm_pad_tdo_en,
output dtm_pad_tms_o,
output dtm_pad_tms_oe,
input chain_io_tdo,
input ctrl_io_tdo_en,
input ctrl_io_tms_oe,
output... | 6.511749 |
module TD_Detect (
oTD_Stable,
oNTSC,
oPAL,
iTD_VS,
iTD_HS,
iRST_N
);
input iTD_VS;
input iTD_HS;
input iRST_N;
output oTD_Stable;
output oNTSC;
output oPAL;
reg NTSC;
reg PAL;
reg Pre_VS;
reg [7:0] Stable_Cont;
assign oTD_Stable = NTSC || PAL;
assign oNTSC = NTSC;
ass... | 6.977162 |
module td_fused_top_ap_hadd_0_full_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
`ifdef complex_dsp
adde... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
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