code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((re... | 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_a... | 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_ar... | 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) be... | 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start... | 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ... | 6.847206 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-... | 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comp... | 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_D... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina ... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out... | 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EX... | 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[... | 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((re... | 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_a... | 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_ar... | 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) be... | 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start... | 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ... | 6.847206 |
module brake_sm (
input wire clk,
input wire brake,
input wire [2:0] left_signal,
input wire [2:0] right_signal,
output reg [2:0] left_lights,
output reg [1:0] center_lights,
output reg [2:0] right_lights
);
// State parameters
parameter idle_state = 2'd0;
parameter brake_state = 2'd1... | 8.827864 |
module sram #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 8,
DEPTH = 256,
MEMFILE = ""
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
reg [DATA_WIDTH-1:0] memory_array[0:DEPTH-1];
... | 7.388143 |
module bram0 #(
parameter ADDR_WIDTH = 13 //width of addresses buses
//parameter ramN = "filedir passed as a parameter" //Number of ram
) (
input CLK,
input [(ADDR_WIDTH-1):0] W_ADDR,
input [(ADDR_WIDTH-1):0] R_ADDR,
input WRITE_EN,
input READ_EN,
input [7:0] DIN,
output reg [7:0] ... | 6.865968 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;... | 7.357455 |
module bram16 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input sys_clk,
input sys_rst,
input [15:0] do,
output reg [15:0] di,
input we,
input [15:0] a
);
//-----------------------------------------------------------------
// Storage depth in 16 bit words
//-----------------------------... | 8.517978 |
module af2048x8_2048x8 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 8;
parameter RD_DATA_WIDTH = 8;
parameter UPA... | 6.662899 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk0;
reg clk1;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
... | 7.277485 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial be... | 7.277485 |
module dpram_18x1024_x2 (
clk_a_0,
WEN_a_0,
REN_a_0,
WR_ADDR_a_0,
RD_ADDR_a_0,
WDATA_a_0,
RDATA_a_0,
clk_b_0,
WEN_b_0,
REN_b_0,
WR_ADDR_b_0,
RD_ADDR_b_0,
WDATA_b_0,
RDATA_b_0,
clk_a_1,
WEN_a_1,
REN_a_1,
WR_ADDR_a_1,
RD_ADDR_a_1,
WDATA_a_1... | 6.662554 |
module dpram_18x1024_9x2048 (
clk_a_0,
WEN_a_0,
REN_a_0,
WR_ADDR_a_0,
RD_ADDR_a_0,
WDATA_a_0,
RDATA_a_0,
clk_b_0,
WEN_b_0,
REN_b_0,
WR_ADDR_b_0,
RD_ADDR_b_0,
WDATA_b_0,
RDATA_b_0,
clk_a_1,
WEN_a_1,
REN_a_1,
WR_ADDR_a_1,
RD_ADDR_a_1,
WDATA... | 6.662554 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CH... | 6.650974 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CH... | 6.650974 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CH... | 6.650974 |
module BRAM1Load(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter ... | 7.231042 |
module bram1w4r #(
parameter DATA_WIDTH = 32,
RAM_SIZE = 1024
) (
clk,
we,
waddr,
data_i,
raddr1,
data_o1,
raddr2,
data_o2,
raddr3,
data_o3,
raddr4,
data_o4
);
input clk, we;
input [31:0] waddr, raddr1, raddr2, raddr3, raddr4;
input [DATA_WIDTH-1 : 0] data_... | 6.705907 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;... | 7.357455 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;... | 7.357455 |
module bram1_tb #(
parameter ABITS = 8,
DBITS = 8,
TRANSP = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS... | 7.32327 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ... | 6.804739 |
module BRAM2K (
input [11:0] addra,
input clka,
input [7:0] dina,
input ena,
input wea,
input clkb,
input enb,
input [11:0] addrb,
output reg [7:0] doutb
);
reg [7:0] BRAM8[2047:0];
initial #5 doutb <= 0;
always @(posedge clka) begin
if (ena & wea) BRAM8[addra] <= dina;
... | 7.551636 |
module BRAM2Load(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter ... | 6.538112 |
module show you how to infer a two-port 1024x32 BRAM in
// your circuit using the standard Verilog code.
//
module bram2p
#(parameter DATA_WIDTH = 32, RAM_SIZE = 1024)
(clka, wea, ena, addra, data_ia, data_oa, // BRAM port A
clkb, web, enb, addrb, data_ib, data_ob); // BRAM port B
input clka, wea, ena;
input... | 6.896868 |
module bram2rgb (
//input wire [19:0] addr,
//input wire [7:0] cdata,
//input wire pclk,
input wire clk,
xrst,
en,
input wire [23:0] in_from_ram,
output reg [19:0] ram_addr = 0,
output reg vd_2s,
hd_2s,
output reg [23:0] rgb24bit = 0,
output reg den_2s = 0
);
reg [1:0]... | 7.345716 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ... | 6.804739 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ... | 6.804739 |
module bram3 #(
parameter ADDR_WIDTH = 13 //width of addresses buses
) (
input CLK,
input [(ADDR_WIDTH-1):0] W_ADDR,
input [(ADDR_WIDTH-1):0] R_ADDR,
input WRITE_EN,
input READ_EN,
input [7:0] DIN,
output reg [7:0] DOUT
);
reg [7:0] mem[2**(ADDR_WIDTH-3):0];
integer idx;
initial... | 6.753298 |
module bram32 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input sys_clk,
input sys_rst,
input [31:0] do,
output reg [31:0] di,
input we,
input [15:0] a
);
//-----------------------------------------------------------------
// Storage depth in 32 bit words
//-----------------------------... | 7.815549 |
module BRAM32K_16 (
doa,
dia,
addra,
cea,
clka,
wea,
dob,
dib,
addrb,
ceb,
clkb,
web
);
output [15:0] doa;
output [15:0] dob;
input [15:0] dia;
input [15:0] dib;
input [11:0] addra;
input [11:0] addrb;
input [1:0] wea;
input [1:0] web;
input cea;
in... | 6.590082 |
module af2048x18_2048x18 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter... | 6.743763 |
module af4096x9_4096x9 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 9;
parameter UPA... | 6.606759 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk0;
reg clk1;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
... | 7.277485 |
module spram_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 36;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 4;
input wire WEN_i;
input wire REN_... | 6.683816 |
module spram_32x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 32;
parameter RD_DATA_WIDTH = 32;
parameter BE_WIDTH = 4;
input wire WEN_i;
input wire REN_... | 6.91401 |
module spram_18x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_... | 6.524103 |
module spram_16x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 16;
parameter RD_DATA_WIDTH = 16;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_... | 6.696585 |
module spram_9x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 9;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wire REN_i;
... | 6.700121 |
module spram_8x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 8;
parameter RD_DATA_WIDTH = 8;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wire REN_i;
... | 6.803316 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`ADDR_WIDTH-1:0] ra;
wire [`DATA_WIDTH-1:0] rq;
reg wce;
reg [`ADDR_WIDTH-1:0] wa;
reg [`DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
ini... | 7.277485 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial be... | 7.277485 |
module dpram_36x1024 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 36;
parameter BE1_WIDTH = 4;
parameter BE2_... | 6.801704 |
module dpram_18x2048 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_... | 6.602544 |
module dpram_9x4096 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 12;
parameter DATA_WIDTH = 9;
parameter BE1_WIDTH = 1;
parameter BE2_WI... | 7.1368 |
module BRAM4k8bit (
CLK,
ADDR,
WE,
EN,
DIN,
DOUT
);
input CLK;
input WE;
input EN;
input [11:0] ADDR;
input [7:0] DIN;
output reg [7:0] DOUT;
reg [7:0] mem[4095:0];
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
mem[ADDR] <= DIN;
end
DOUT ... | 6.616116 |
module bram64x256 (
input clk,
input wr,
input [7:0] adr,
input [63:0] din,
output [63:0] dout
);
reg [63:0] ram[255:0];
reg [63:0] rDout;
assign dout = rDout;
always @(posedge clk) begin
if (wr) ram[adr] <= din;
rDout <= ram[adr];
end
endmodule
| 7.235974 |
module BRAM6k9bit (
CLK,
ADDR,
WE,
EN,
DIN,
DINP,
DOUT,
DOUTP
);
input CLK;
input WE;
input EN;
input [12:0] ADDR;
input [7:0] DIN;
input DINP;
output [7:0] DOUT;
output DOUTP;
wire [7:0] ram0_DOUT, ram1_DOUT, ram2_DOUT;
wire ram0_DOUTP, ram1_DOUTP, ram2_DOUTP;
re... | 6.598609 |
module BRam8x512x512 (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0:0] wea;
input [17:0] addra;
input [7:0] dina;
input clkb;
input [17:0] addrb;
output reg [7:0] doutb;
reg [7 : 0] mem[0 : 2 ** 18 - 1];
always @(posedge clka) begin
if (wea) mem[a... | 6.795288 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
... | 7.774683 |
module RAM256X8 (
B1ADDR,
B1DATA,
CLK3,
A1ADDR,
A1DATA,
A1EN,
CLK2
);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter TRANSP3 = 1;
input CLK2;
input CLK3;
input [7:0] A1ADDR;
input [7:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
output [7:0] B1DATA;
wire c2 = ... | 6.860788 |
module ramtb ();
reg clk;
reg rst;
reg tx;
// output port
wire wr_en_1; // enable BRAM1
wire [31:0] wr_add_1; // address of BRAM1
wire [31:0] wr_data_1; // write data
wire wr_en_2; // enable BRAM2
wire [31:0] wr_add_2; // write address BRAM2
wire [31:0] wr_data_2; // write data on BRAM2
c... | 6.767128 |
module AFIFO_18K_BLK (
DIN,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Async_Flush,
Overrun_Error,
Full_Watermark,
Almost_Full,
Full,
Underrun_Error,
Empty_Watermark,
Almost_Empty,
Empty,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter ... | 6.825329 |
module RAM_18K_BLK (
WEN_i,
REN_i,
WR_CLK_i,
RD_CLK_i,
WR_BE_i,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
... | 6.833245 |
module DPRAM_18K_BLK (
CLK1_i,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
CLK2_i,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_... | 6.841924 |
module RAM_18K_BLK (
WEN_i,
REN_i,
WR_CLK_i,
RD_CLK_i,
WR_BE_i,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
... | 6.833245 |
module DPRAM_18K_BLK (
CLK1_i,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
CLK2_i,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_... | 6.841924 |
module AFIFO_18K_BLK (
DIN,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Async_Flush,
Overrun_Error,
Full_Watermark,
Almost_Full,
Full,
Underrun_Error,
Empty_Watermark,
Almost_Empty,
Empty,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter ... | 6.825329 |
module BRAM_12 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH =... | 6.745427 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.