code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output ... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wir... | 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 37,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_tdf1_adjustments (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outp... | 6.827284 |
module td_fused_top_tdf1_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [D... | 6.827284 |
module td_fused_top_tdf1_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [D... | 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wir... | 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module td_fused_top_tdf1_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd432;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output ... | 6.827284 |
module td_fused_top_tdf1_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 432;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWID... | 6.827284 |
module td_fused_top_tdf1_filters_0 (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd108;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.827284 |
module td_fused_top_tdf1_filters_0_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 108;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.827284 |
module td_fused_top_tdf1_filters_0_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 108;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWI... | 6.827284 |
module td_fused_top_tdf1_filters_1 (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd108;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
td_fused_to... | 6.827284 |
module td_fused_top_tdf1_filters_1_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 108;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("... | 6.827284 |
module td_fused_top_tdf1_filters_1_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 108;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("... | 6.827284 |
module td_fused_top_tdf1_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 432;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWID... | 6.827284 |
module td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #(
parameter ID = 47,
NUM_STAGE = 2,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire ce... | 6.827284 |
module td_fused_top_ap_hcmp_0_no_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
input wire s_axis_operation_tvalid,
input wire [ 7:0] s_axis_operation_tdata,
output wire m_... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output ... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module td_fused_top_start_for_tdf2_readFilters24_U0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
... | 6.827284 |
module td_fused_top_start_for_tdf2_readFilters24_U0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [D... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] ... | 6.827284 |
module td_fused_top_fifo_w1_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w1_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w12_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w12_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr... | 6.827284 |
module td_fused_top_fifo_w6_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w6_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w5_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w5_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_fifo_w5_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
inpu... | 6.827284 |
module td_fused_top_fifo_w5_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0... | 6.827284 |
module td_fused_top_Block_entry_proc_proc392 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [Address... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input c... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_weight_vecs_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0]... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd144;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38022_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 8;
parameter MEM_SIZE = 144;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input... | 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 25,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hadd_3_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wi... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output ... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module td_fused_top_hcmp_16ns_16ns_1_2_no_dsp_1 #(
parameter ID = 47,
NUM_STAGE = 2,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire ce... | 6.827284 |
module td_fused_top_ap_hcmp_0_no_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
input wire s_axis_operation_tvalid,
input wire [ 7:0] s_axis_operation_tdata,
output wire m_... | 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_4_max_dsp_1 #(
parameter ID = 20,
NUM_STAGE = 4,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hmul_2_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wir... | 6.827284 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module td_fused_top_hsub_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 37,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 25,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hadd_3_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wi... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B; // Input B, a 32-bit floating point number
input [9:0] ShiftDet;
// Output ports
output ... | 6.969233 |
module FPAddSub_PrealignModule (
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B; // Input B, a 32-bit floating point number
input operation;
// ... | 7.069212 |
module td_fused_top_hadd_16ns_16ns_16_5_full_dsp_1 #(
parameter ID = 25,
NUM_STAGE = 5,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hadd_3_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wi... | 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.