code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ADDSUB_16 (
X,
Y,
Sub,
S,
Cout
);
input [15:0] X, Y;
input Sub;
output [15:0] S;
output Cout;
CLA_16 adder0 (
X,
Y ^ {16{Sub}},
Sub,
S,
Cout
);
endmodule
| 7.168592 |
module ADDSUB_32 (
X,
Y,
Sub,
S,
Cout
);
input [31:0] X;
input [31:0] Y;
input Sub;
output [31:0] S;
output Cout;
CLA_32 adder0 (
X,
Y ^ {32{Sub}},
Sub,
S,
Cout
);
endmodule
| 7.639771 |
module CLA_4 (
X,
Y,
Cin,
S,
Cout
);
input [3:0] X;
input [3:0] Y;
input Cin;
output [3:0] S;
output Cout;
and get_0_0_0 (tmp_0_0_0, X[0], Y[0]);
or get_0_0_1 (tmp_0_0_1, X[0], Y[0]);
and get_0_1_0 (tmp_0_1_0, X[1], Y[1]);
or get_0_1_1 (tmp_0_1_1, X[1], Y[1]);
and get_0_2_0 (tmp_0_2_0, X[2], Y[2]);
or get_0_2_1 (tmp_0_2_1, X[2], Y[2]);
and get_0_3_0 (tmp_0_3_0, X[3], Y[3]);
or get_0_3_1 (tmp_0_3_1, X[3], Y[3]);
and get_1_0_0 (tmp_1_0_0, ~tmp_0_0_0, tmp_0_0_1);
xor getS0 (S0, tmp_1_0_0, Cin);
and get_1_1_0 (tmp_1_1_0, ~tmp_0_1_0, tmp_0_1_1);
not get_1_1_1 (tmp_1_1_1, tmp_0_0_0);
nand get_1_1_2 (tmp_1_1_2, Cin, tmp_0_0_1);
nand get_2_0_0 (tmp_2_0_0, tmp_1_1_1, tmp_1_1_2);
xor getS1 (S1, tmp_1_1_0, tmp_2_0_0);
and get_1_2_0 (tmp_1_2_0, ~tmp_0_2_0, tmp_0_2_1);
not get_1_2_1 (tmp_1_2_1, tmp_0_1_0);
nand get_1_2_2 (tmp_1_2_2, tmp_0_1_1, tmp_0_0_0);
nand get_1_2_3 (tmp_1_2_3, tmp_0_1_1, tmp_0_0_1, Cin);
nand get_2_1_0 (tmp_2_1_0, tmp_1_2_1, tmp_1_2_2, tmp_1_2_3);
xor getS2 (S2, tmp_1_2_0, tmp_2_1_0);
and get_1_3_0 (tmp_1_3_0, ~tmp_0_3_0, tmp_0_3_1);
not get_1_3_1 (tmp_1_3_1, tmp_0_2_0);
nand get_1_3_2 (tmp_1_3_2, tmp_0_2_1, tmp_0_1_0);
nand get_1_3_3 (tmp_1_3_3, tmp_0_2_1, tmp_0_1_1, tmp_0_0_0);
nand get_1_3_4 (tmp_1_3_4, tmp_0_2_1, tmp_0_1_1, tmp_0_0_1, Cin);
nand get_2_2_0 (tmp_2_2_0, tmp_1_3_1, tmp_1_3_2, tmp_1_3_3, tmp_1_3_4);
xor getS3 (S3, tmp_1_3_0, tmp_2_2_0);
not get_1_4_0 (tmp_1_4_0, tmp_0_3_0);
nand get_1_4_1 (tmp_1_4_1, tmp_0_3_1, tmp_0_2_0);
nand get_1_4_2 (tmp_1_4_2, tmp_0_3_1, tmp_0_2_1, tmp_0_1_0);
nand get_1_4_3 (tmp_1_4_3, tmp_0_3_1, tmp_0_2_1, tmp_0_1_1, tmp_0_0_0);
nand get_1_4_4 (tmp_1_4_4, tmp_0_3_1, tmp_0_2_1, tmp_0_1_1, tmp_0_0_1, Cin);
nand getCout (Cout, tmp_1_4_0, tmp_1_4_1, tmp_1_4_2, tmp_1_4_3, tmp_1_4_4);
assign S = {S3, S2, S1, S0};
endmodule
| 6.769755 |
module addsub_tb;
parameter tck = 10;
reg op, oc; // 0: add, 1: sub
wire [`WIDTH-1:0] y;
reg [`WIDTH-1:0] a, b;
reg c_in;
wire c_out, h_out;
reg clk;
addsub dut (
op,
oc,
y,
a,
b,
c_in,
c_out,
h_out
);
initial begin
$dumpvars(-1, dut);
$dumpfile("addsub_tb.vcd");
end
always #(tck / 2) clk = ~clk;
integer i, j;
initial begin
clk = 0;
op = 0;
oc = 0;
c_in = 0;
for (i = 0; i < (1 << `WIDTH); i = i + 50)
for (j = 0; j < (1 << `WIDTH); j = j + 50) begin
a = i;
b = j;
@(negedge clk);
$display("%h %h : %h %h", c_out, y, a, b);
end
$finish;
end
endmodule
| 6.553753 |
module addsum (
input [31:0] pc,
imm,
output [31:0] pc_branch
);
assign pc_branch = pc + imm;
endmodule
| 6.871015 |
module addTest (
input clk,
input req_in,
output fin,
input [31:0] a_in,
input [31:0] b_in,
output wire [31:0] s1,
output wire cout1,
output wire [31:0] s2,
output wire cout2
);
reg req = 1'b0;
reg [31:0] a = 0, b = 0;
always @(posedge clk) begin
if (req_in) begin
req <= 1'b1;
a <= a_in;
b <= b_in;
end
end
assign {cout1, s1} = a + b;
add #(32) add (
req,
fin,
a,
b,
s2,
cout2
);
endmodule
| 6.798843 |
module addX (
a,
b,
cin,
out,
cout
);
parameter WIRE = 8;
input [WIRE-1:0] a, b;
input cin;
output [WIRE-1:0] out;
output cout;
wire ret;
if (WIRE > 1) begin
add add0 (
a[0],
b[0],
cin,
out[0],
ret
);
addX #(
.WIRE(WIRE - 1)
) recall (
a[WIRE-1:1],
b[WIRE-1:1],
ret,
out[WIRE-1:1],
cout
);
end else
add add0 (
a[0],
b[0],
cin,
out[0],
cout
);
endmodule
| 6.58028 |
module addy (
add_sub,
dataa,
datab,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output [6:0] result;
wire [6:0] sub_wire0;
wire [6:0] result = sub_wire0[6:0];
lpm_add_sub lpm_add_sub_component (
.dataa(dataa),
.add_sub(add_sub),
.datab(datab),
.result(sub_wire0)
// synopsys translate_off
, .aclr(),
.cin(),
.clken(),
.clock(),
.cout(),
.overflow()
// synopsys translate_on
);
defparam lpm_add_sub_component.lpm_direction = "UNUSED", lpm_add_sub_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", lpm_add_sub_component.lpm_representation = "UNSIGNED",
lpm_add_sub_component.lpm_type = "LPM_ADD_SUB", lpm_add_sub_component.lpm_width = 7;
endmodule
| 7.019129 |
module addzero (
input [15:0] ramout,
input useAllBits,
output [15:0] z
);
//assign zero = 0;
//assign z[15:0] = useAllBits ? ramout : {zero,zero,zero,zero,ramout[11:0]};
assign z[15] = useAllBits & ramout[15];
assign z[14] = useAllBits & ramout[14];
assign z[13] = useAllBits & ramout[13];
assign z[12] = useAllBits & ramout[12];
assign z[11:0] = ramout[11:0];
endmodule
| 8.587073 |
module ADD_ #(
parameter N = 8,
M = N
) ( // N >= M
input [N-1:0] A,
input [M-1:0] B,
output [ N:0] O
);
assign O = A + B;
endmodule
| 8.457458 |
module adder_1 (
A,
B,
Carry_in,
clk,
Sum,
Carry_out
);
input A;
input B;
input Carry_in;
input clk;
output Sum;
output Carry_out;
wire [8:0] ds;
wire [1:0] w_A_0;
wire [1:0] w_B_0;
jdff dff_0_0 (
.din (Carry_in),
.dout(ds[0]),
.clk (clk)
);
jxor xor_0_0 (
.dina(w_A_0[1]),
.dinb(w_B_0[1]),
.dout(ds[1]),
.clk (clk)
);
jand and_0_0 (
.dina(w_A_0[0]),
.dinb(w_B_0[0]),
.dout(ds[2]),
.clk (clk)
);
jspl spl_0_0 (
.din (ds[0]),
.douta(ds[3]),
.doutb(ds[4])
);
jspl spl_0_1 (
.din (ds[1]),
.douta(ds[5]),
.doutb(ds[6])
);
jxor xor_1_0 (
.dina(ds[3]),
.dinb(ds[5]),
.dout(Sum),
.clk (clk)
);
jand and_1_0 (
.dina(ds[4]),
.dinb(ds[6]),
.dout(ds[7]),
.clk (clk)
);
jdff dff_1_0 (
.din (ds[2]),
.dout(ds[8]),
.clk (clk)
);
jcb cb_1_0 (
.dina(ds[7]),
.dinb(ds[8]),
.dout(Carry_out)
);
jspl jspl_w_A_0 (
.douta(w_A_0[0]),
.doutb(w_A_0[1]),
.din (A)
);
jspl jspl_w_B_0 (
.douta(w_B_0[0]),
.doutb(w_B_0[1]),
.din (B)
);
endmodule
| 6.607745 |
module add_12 (
clk_i,
rst_n_i,
data_1_i,
data_2_i,
data_sum_o
);
//----------------------------------------------------------------------------------------------------------------------
// Global constant and function headers
//----------------------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------------------
// parameter definitions
//----------------------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------------------
// localparam definitions
//----------------------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------------------
// I/O signals
//----------------------------------------------------------------------------------------------------------------------
// System Clock Signals
input clk_i;
input rst_n_i;
input [11:0] data_1_i;
input [11:0] data_2_i;
output reg [11:0] data_sum_o;
//----------------------------------------------------------------------------------------------------------------------
// Internal wires and registers
//----------------------------------------------------------------------------------------------------------------------
reg [11:0] r_add_1;
reg [11:0] r_add_2;
reg [11:0] r_add_3;
reg [11:0] r_add_4;
reg r_skip;
//----------------------------------------------------------------------------------------------------------------------
// Implmentation
//----------------------------------------------------------------------------------------------------------------------
always @(posedge clk_i) begin
if (~rst_n_i) begin
r_add_1 <= 0;
end else begin
r_add_1[11:4] <= data_1_i[11:4] + data_2_i[11:4];
r_add_1[3:0] <= 0;
end
end
//
always @(posedge clk_i) begin : ADD_1
if (~rst_n_i) begin
r_add_2 <= 0;
r_add_3 <= 0;
r_add_4 <= 0;
end else begin
r_add_2 <= r_add_1;
r_add_3 <= r_add_2;
r_add_4 <= r_add_3;
end
end
//
always @(posedge clk_i) begin : SUM
if (~rst_n_i) begin
data_sum_o <= 0;
end else begin
data_sum_o <= r_add_4;
end
end
//----------------------------------------------------------------------------------------------------------------------
// Sub module instantiation
//----------------------------------------------------------------------------------------------------------------------
endmodule
| 6.716336 |
module add_128 (
a1,
a2,
s
);
input [7:0] a1, a2;
output wire [8:0] s;
assign s = a1 + a2;
endmodule
| 7.113309 |
module add_16 (
a1,
a2,
s
);
input [4:0] a1, a2;
output wire [5:0] s;
assign s = a1 + a2;
endmodule
| 6.977906 |
module add_16_bit (
Sum,
A,
B
);
input [15:0] A, B;
output [15:0] Sum;
wire [15:0] CO;
full_adder_1bit FA0 (
.A (A[0]),
.B (B[0]),
.CI(1'b0),
.S (Sum[0]),
.CO(CO[0])
);
full_adder_1bit FA1 (
.A (A[1]),
.B (B[1]),
.CI(CO[0]),
.S (Sum[1]),
.CO(CO[1])
);
full_adder_1bit FA2 (
.A (A[2]),
.B (B[2]),
.CI(CO[1]),
.S (Sum[2]),
.CO(CO[2])
);
full_adder_1bit FA3 (
.A (A[3]),
.B (B[3]),
.CI(CO[2]),
.S (Sum[3]),
.CO(CO[3])
);
full_adder_1bit FA4 (
.A (A[4]),
.B (B[4]),
.CI(CO[3]),
.S (Sum[4]),
.CO(CO[4])
);
full_adder_1bit FA5 (
.A (A[5]),
.B (B[5]),
.CI(CO[4]),
.S (Sum[5]),
.CO(CO[5])
);
full_adder_1bit FA6 (
.A (A[6]),
.B (B[6]),
.CI(CO[5]),
.S (Sum[6]),
.CO(CO[6])
);
full_adder_1bit FA7 (
.A (A[7]),
.B (B[7]),
.CI(CO[6]),
.S (Sum[7]),
.CO(CO[7])
);
full_adder_1bit FA8 (
.A (A[8]),
.B (B[8]),
.CI(CO[7]),
.S (Sum[8]),
.CO(CO[8])
);
full_adder_1bit FA9 (
.A (A[9]),
.B (B[9]),
.CI(CO[8]),
.S (Sum[9]),
.CO(CO[9])
);
full_adder_1bit FA10 (
.A (A[10]),
.B (B[10]),
.CI(CO[9]),
.S (Sum[10]),
.CO(CO[10])
);
full_adder_1bit FA11 (
.A (A[11]),
.B (B[11]),
.CI(CO[10]),
.S (Sum[11]),
.CO(CO[11])
);
full_adder_1bit FA12 (
.A (A[12]),
.B (B[12]),
.CI(CO[11]),
.S (Sum[12]),
.CO(CO[12])
);
full_adder_1bit FA13 (
.A (A[13]),
.B (B[13]),
.CI(CO[12]),
.S (Sum[13]),
.CO(CO[13])
);
full_adder_1bit FA14 (
.A (A[14]),
.B (B[14]),
.CI(CO[13]),
.S (Sum[14]),
.CO(CO[14])
);
full_adder_1bit FA15 (
.A (A[15]),
.B (B[15]),
.CI(CO[14]),
.S (Sum[15]),
.CO(CO[15])
);
endmodule
| 6.770312 |
module add_16_pipe (
c_out,
sum,
a,
b,
c_in,
clock
);
parameter size = 16;
parameter half = size / 2;
parameter double = 2 * size;
parameter triple = 3 * half;
parameter size1 = half - 1; // 7
parameter size2 = size - 1; // 15
parameter size3 = half + 1; // 9
parameter R1 = 1; // 1
parameter L1 = half;
parameter R2 = size3;
parameter L2 = size;
parameter R3 = size + 1;
parameter L3 = size + half;
parameter R4 = double - half + 1;
parameter L4 = double;
input [size2:0] a, b;
input c_in, clock;
output [size2:0] sum;
output c_out;
reg [double:0] IR;
reg [triple:0] PR;
reg [ size:0] OR;
assign {c_out, sum} = OR;
always @(posedge clock) begin
// Load input register
IR[0] <= c_in;
IR[L1:R1] <= a[size1:0];
IR[L2:R2] <= b[size1:0];
IR[L3:R3] <= a[size2:half];
IR[L4:R4] <= b[size2:half];
// Load pipeline register
PR[L3:R3] <= IR[L4:R4];
PR[L2:R2] <= IR[L3:R3];
PR[half:0] <= IR[L2:R2] + IR[L1:R1] + IR[0];
OR <= {{1'b0, PR[L3:R3]} + {1'b0, PR[L2:R2]} + PR[half], PR[size1:0]};
end
endmodule
| 6.825404 |
module add_1p #(
parameter WIDTH = 15, // Total bit width
WIDTH1 = 7, // Bit width of LSBs
WIDTH2 = 8
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
input clk, // Clock
output LSBs_Carry
); // Test port
reg [WIDTH1-1:0] l1, l2, s1; // LSBs of inputs
reg [WIDTH1:0] r1; // LSBs of inputs
reg [WIDTH2-1:0] l3, l4, r2, s2; // MSBs of input
always @(posedge clk) begin
// Split in MSBs and LSBs and store in registers
// Split LSBs from input x,y
l1[WIDTH1-1:0] <= x[WIDTH1-1:0];
l2[WIDTH1-1:0] <= y[WIDTH1-1:0];
// Split MSBs from input x,y
l3[WIDTH2-1:0] <= x[WIDTH2-1+WIDTH1:WIDTH1];
l4[WIDTH2-1:0] <= y[WIDTH2-1+WIDTH1:WIDTH1];
/************* First stage of the adder *****************/
r1 <= {1'b0, l1} + {1'b0, l2};
r2 <= l3 + l4;
/************** Second stage of the adder ****************/
s1 <= r1[WIDTH1-1:0];
// Add MSBs (x+y) and carry from LSBs
s2 <= r1[WIDTH1] + r2;
end
assign LSBs_Carry = r1[WIDTH1]; // Add a test signal
// Build a single registered output word
// of WIDTH = WIDTH1 + WIDTH2
assign sum = {s2, s1};
endmodule
| 6.651794 |
module ADD_1_bit (
c_out,
sum,
a,
b,
c_in
);
output c_out, sum;
input a, b, c_in;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
not not1 (w1, a);
not not2 (w2, b);
not not3 (w3, c_in);
and and1 (w4, a, w2, w3); //
and and2 (w5, w1, b, w3); // for sum
and and3 (w6, w1, w2, c_in); //
and and4 (w7, a, b, c_in); //
and and5 (w8, a, b); //
and and6 (w9, a, c_in); // for c_out
and and7 (w10, b, c_in); //
or or_sum (sum, w4, w5, w6, w7); // sum
or or_cout (c_out, w8, w9, w10); // c_out
endmodule
| 6.849935 |
module ADD_1_test;
reg a, b, cin;
wire sum, carry;
ADD_1 a1 (
sum,
carry,
a,
b,
cin
);
integer i;
initial begin
$dumpfile("ADD_1_test.vcd");
$dumpvars(0, ADD_1_test);
for (i = 0; i < 8; i = i + 1) begin
{a, b, cin} = i;
#5;
$display("%d + %d + %d = %d %d", a, b, cin, carry, sum);
end
$finish;
$display("Test Completed");
end
endmodule
| 6.708502 |
module add_2p #(
parameter WIDTH = 22, // Total bit width
WIDTH1 = 7, // Bit width of LSBs
WIDTH2 = 7, // Bit width of middle
WIDTH12 = 14, // Sum WIDTH1+WIDTH2
WIDTH3 = 8
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
output LSBs_Carry,
MSBs_Carry, // Single bits
input clk
); // Clock
reg [WIDTH1-1:0] l1, l2, v1, s1; // LSBs of inputs
reg [WIDTH1:0] q1; // LSBs of inputs
reg [WIDTH2-1:0] l3, l4, s2; // Middle bits
reg [WIDTH2:0] q2, v2; // Middle bits
reg [WIDTH3-1:0] l5, l6, q3, v3, s3; // MSBs of input
// Split in MSBs and LSBs and store in registers
always @(posedge clk) begin
// Split LSBs from input x,y
l1[WIDTH1-1:0] <= x[WIDTH1-1:0];
l2[WIDTH1-1:0] <= y[WIDTH1-1:0];
// Split middle bits from input x,y
l3[WIDTH2-1:0] <= x[WIDTH2-1+WIDTH1:WIDTH1];
l4[WIDTH2-1:0] <= y[WIDTH2-1+WIDTH1:WIDTH1];
// Split MSBs from input x,y
l5[WIDTH3-1:0] <= x[WIDTH3-1+WIDTH12:WIDTH12];
l6[WIDTH3-1:0] <= y[WIDTH3-1+WIDTH12:WIDTH12];
//************** First stage of the adder ****************
q1 <= {1'b0, l1} + {1'b0, l2}; // Add LSBs of x and y
q2 <= {1'b0, l3} + {1'b0, l4}; // Add LSBs of x and y
q3 <= l5 + l6; // Add MSBs of x and y
//************* Second stage of the adder *****************
v1 <= q1[WIDTH1-1:0]; // Save q1
// Add result from middle bits (x+y) and carry from LSBs
v2 <= q1[WIDTH1] + {1'b0, q2[WIDTH2-1:0]};
// Add result from MSBs bits (x+y) and carry from middle
v3 <= q2[WIDTH2] + q3;
//************* Third stage of the adder ******************
s1 <= v1; // Save v1
s2 <= v2[WIDTH2-1:0]; // Save v2
// Add result from MSBs bits (x+y) and 2. carry from middle
s3 <= v2[WIDTH2] + v3;
end
assign LSBs_Carry = q1[WIDTH1]; // Provide test signals
assign MSBs_Carry = v2[WIDTH2];
// Build a single output word of WIDTH=WIDTH1+WIDTH2+WIDTH3
assign sum = {s3, s2, s1}; // Connect sum to output pins
endmodule
| 6.519861 |
module add_3 (
input [31:0] yiwei,
input [31:0] pc,
output [31:0] yp
);
assign yp = yiwei + pc;
endmodule
| 7.418891 |
module add_32 (
a1,
a2,
s
);
input [5:0] a1, a2;
output wire [6:0] s;
assign s = a1 + a2;
endmodule
| 6.904223 |
module add_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa + datab;
assign overflow = computation[32];
assign result = computation[31:0];
endmodule
| 7.951311 |
module add_32b_testbench ();
reg [31:0] A;
reg [31:0] B;
reg C_in;
wire [31:0] O;
wire C_out;
add_32b add32tb (
O,
C_out,
A,
B,
C_in
);
initial begin
C_in = 1'b0;
A = 32'b00000000000000000000000000000011;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000000000000001000100;
B = 32'b00000000000000000000001000000001;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000100000000000000001;
B = 32'b00000000100000000000000000000001;
#`DELAY;
A = 32'b10000000000000000000000000000000;
B = 32'b10000000000000000000000000000000;
#`DELAY;
A = 32'b10000010000000000000000000000000;
B = 32'b10000000000000000000100000000001;
#`DELAY;
A = 32'b00000000000100000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b10000000010000000000000000000001;
B = 32'b00000000000000000000000000000001;
#`DELAY;
C_in = 1'b1;
A = 32'b00000000000000000000000000000011;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000000000000001000100;
B = 32'b00000000000000000000001000000001;
#`DELAY;
A = 32'b00000000000000000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b00000000000000100000000000000001;
B = 32'b00000000100000000000000000000001;
#`DELAY;
A = 32'b10000000000000000000000000000000;
B = 32'b10000000000000000000000000000000;
#`DELAY;
A = 32'b10000010000000000000000000000000;
B = 32'b10000000000000000000100000000001;
#`DELAY;
A = 32'b00000000000100000000000000000001;
B = 32'b00000000000000000000000000000000;
#`DELAY;
A = 32'b10000000010000000000000000000001;
B = 32'b00000000000000000000000000000001;
#`DELAY;
end
initial begin
$monitor("time = %2d, A = %10d, B = %10d, R = %10d, C_out = %1b ", $time, A, B, O, C_out);
end
endmodule
| 6.92566 |
module add_32x16b (
input i_clk,
input i_rst_n,
input i_calc_en,
input [511:0] i_npe_dat_out,
//input i_ram_dat_vld,
input [511:0] i_ram_dat,
output [511:0] o_bias_dat_o
);
wire signed [15:0] npe_dat [31:0];
wire signed [15:0] ram_dat [31:0];
wire signed [15:0] bias_dat[31:0];
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
assign npe_dat[i] = i_npe_dat_out[((i+1)*16-1) : (i*16)];
assign ram_dat[i] = i_ram_dat[((i+1)*16-1):(i*16)];
assign o_bias_dat_o[((i+1)*16-1):(i*16)] = bias_dat[i];
end
endgenerate
generate
for (i = 0; i < 32; i = i + 1) begin
add #(
.DATIN_WIDTH (16),
.DATOUT_WIDTH(16)
) add_inst (
.clk(i_clk),
.rst_n(i_rst_n),
.en(i_calc_en),
.clr(1'b0),
.i_op_a(npe_dat[i]),
.i_op_b(ram_dat[i]),
.o_result(bias_dat[i])
);
end
endgenerate
endmodule
| 7.345913 |
module add_32_bit (
input [31:0] Ra,
input [31:0] Rb,
input wire cin,
output wire [31:0] sum,
output wire cout
);
wire cout1;
CLA16 CLA1 (
.Ra (Ra[15:0]),
.Rb (Rb[15:0]),
.cin (cin),
.sum (sum[15:0]),
.cout(cout1)
);
CLA16 CLA2 (
.Ra (Ra[31:16]),
.Rb (Rb[31:16]),
.cin (cout1),
.sum (sum[31:16]),
.cout(cout)
);
endmodule
| 7.271914 |
module CLA16 (
input wire [15:0] Ra,
input wire [15:0] Rb,
input wire cin,
output wire [15:0] sum,
output wire cout
);
wire cout1, cout2, cout3;
CLA4 CLA1 (
.Ra (Ra[3:0]),
.Rb (Rb[3:0]),
.cin (cin),
.sum (sum[3:0]),
.cout(cout1)
);
CLA4 CLA2 (
.Ra (Ra[7:4]),
.Rb (Rb[7:4]),
.cin (cout1),
.sum (sum[7:4]),
.cout(cout2)
);
CLA4 CLA3 (
.Ra (Ra[11:8]),
.Rb (Rb[11:8]),
.cin (cout2),
.sum (sum[11:8]),
.cout(cout3)
);
CLA4 CLA4 (
.Ra (Ra[15:12]),
.Rb (Rb[15:12]),
.cin (cout3),
.sum (sum[15:12]),
.cout(cout)
);
endmodule
| 8.139623 |
module CLA4 (
input wire [3:0] Ra,
input wire [3:0] Rb,
input wire cin,
output wire [3:0] sum,
output wire cout
);
// Creating wires for Propoate and Generate
wire [3:0] P, G, c;
assign P = Ra ^ Rb;
assign G = Ra & Rb;
assign c[0] = cin;
assign c[1] = G[0] | (P[0] & c[0]);
assign c[2] = G[1] | (P[1] & G[0]) | P[1] & P[0] & c[0];
assign c[3] = G[2] | (P[2] & G[1]) | P[2] & P[1] & G[0] | P[2] & P[1] & P[0] & c[0];
assign cout = G[3] | (P[3]&G[2]) | P[3]&P[2]&G[1] | P[3]&P[2]&P[1]&G[0] | P[3]&P[2]&P[1]&P[0]&c[0];
assign sum[3:0] = P ^ c;
endmodule
| 7.783567 |
module CLA_4 (
input wire c_in,
input wire [3:0] a,
input wire [3:0] b,
output wire [3:0] s,
output wire c_out,
output wire c3
);
//gate syntax: gate name(arg1,arg2,out)
//Pi = Ai XOR Bi
//Gi = Ai * Bi
//Si = Pi XOR Ci
//Ci+1 = Gi + Pi*Ci
//ADDER 0
wire p0, g0, c1;
//P0 = A0 XOR B0
xor_gate prop0 (
a[0],
b[0],
p0
);
//G0 = A0*B0
and_gate gen0 (
a[0],
b[0],
g0
);
//S0 = P0 XOR C0
xor_gate sum0 (
p0,
c_in,
s[0]
);
//C1 = G0 + P0*C0
wire p0c0;
and_gate c1and0 (
p0,
c_in,
p0c0
);
or_gate c1or0 (
g0,
p0c0,
c1
);
//ADDER 1
wire p1, g1, c2;
//P1 = A1 XOR B1
xor_gate prop1 (
a[1],
b[1],
p1
);
//G1 = A1*B1
and_gate gen1 (
a[1],
b[1],
g1
);
//S1 = P1 XOR C1
xor_gate sum1 (
p1,
c1,
s[1]
);
//C2 = G1 + C1*S1
//C2 = G1 + P1*(G0 + P0*C0)
// = G1 + P1*G0 + P1*P0*C0
wire p1g0, p1p0c0;
and_gate and_p1g0 (
p1,
g0,
p1g0
);
and_3 and_p1p0c0 (
p1,
p0,
c_in,
p1p0c0
);
or_3 c2_or (
g1,
p1g0,
p1p0c0,
c2
);
//ADDER 2
wire p2, g2;
//P2 = A2 XOR B2
xor_gate prop2 (
a[2],
b[2],
p2
);
//G2 = A2*B2
and_gate gen2 (
a[2],
b[2],
g2
);
//S2 = P2 XOR C2
xor_gate sum2 (
p2,
c2,
s[2]
);
//C3 = G2 + P2 * (G1 + P1*(G0 + P0*C0))
// = G2 + P2*G1 + P2*P1(G0 + P0*C0)
// = G2 + P2*G1 + P2*P1*G0 + P2*P1*P0*C0
wire p2g1, p2p1g0, p2p1p0c0;
and_gate and_p2g1 (
p2,
g1,
p2g1
);
and_3 and_p2p1g0 (
p2,
p1,
g0,
p2p1g0
);
and_4 and_p2p1p0c0 (
p2,
p1,
p0,
c_in,
p2p1p0c0
);
or_4 c3_or (
g2,
p2g1,
p2p1g0,
p2p1p0c0,
c3
);
//ADDER 3
wire p3, g3;
//P3 = A3 XOR B3
xor_gate prop3 (
a[3],
b[3],
p3
);
//G3 = A3 * B2
and_gate gen3 (
a[3],
b[3],
g3
);
//S3 = P3 XOR C3
xor_gate sum3 (
p3,
c3,
s[3]
);
//C_out = G3 + P3 * (G2 + P2*(G1 + P1*(G0 + P0*C0)))
// = G3 + P3*G2 + P3*P2*(G1 + P1*(G0 + P0*C0))
// = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*(G0 + P0*C0)
// = G3 + P3*G2 + P3*P2*G1 + P3*P2*P1*G0 + P3*P2*P1*P0*C0
wire p3g2, p3p2g1, p3p2p1g0, p3p2p1p0c0;
and_gate and_p3g2 (
p3,
g2,
p3g2
);
and_3 and_p3p2g1 (
p3,
p2,
g1,
p3p2g1
);
and_4 and_p3p2p1g0 (
p3,
p2,
p1,
g0,
p3p2p1g0
);
and_5 and_p3p2p1p0c0 (
p3,
p2,
p1,
p0,
c_in,
p3p2p1p0c0
);
or_5 c_out_or (
g3,
p3g2,
p3p2g1,
p3p2p1g0,
p3p2p1p0c0,
c_out
);
endmodule
| 6.766102 |
module add_3p #(
parameter WIDTH = 29, // Total bit width
WIDTH0 = 7, // Bit width of LSBs
WIDTH1 = 7, // Bit width of 2. LSBs
WIDTH01 = 14, // Sum WIDTH0+WIDTH1
WIDTH2 = 7, // Bit width of 2. MSBs
WIDTH012 = 21, // Sum WIDTH0+WIDTH1+WIDTH2
WIDTH3 = 8
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
output LSBs_Carry,
Middle_Carry,
MSBs_Carry, // Test pins
input clk
); // Clock
reg [WIDTH0-1:0] l0, l1, r0, v0, s0; // LSBs of inputs
reg [WIDTH0:0] q0; // LSBs of inputs
reg [WIDTH1-1:0] l2, l3, r1, s1; // 2. LSBs of input
reg [WIDTH1:0] v1, q1; // 2. LSBs of input
reg [WIDTH2-1:0] l4, l5, s2, h7; // 2. MSBs bits
reg [WIDTH2:0] q2, v2, r2; // 2. MSBs bits
reg [WIDTH3-1:0] l6, l7, q3, v3, r3, s3, h8;
// MSBs of input
always @(posedge clk) begin
// Split in MSBs and LSBs and store in registers
// Split LSBs from input x,y
l0[WIDTH0-1:0] <= x[WIDTH0-1:0];
l1[WIDTH0-1:0] <= y[WIDTH0-1:0];
// Split 2. LSBs from input x,y
l2[WIDTH1-1:0] <= x[WIDTH1-1+WIDTH0:WIDTH0];
l3[WIDTH1-1:0] <= y[WIDTH1-1+WIDTH0:WIDTH0];
// Split 2. MSBs from input x,y
l4[WIDTH2-1:0] <= x[WIDTH2-1+WIDTH01:WIDTH01];
l5[WIDTH2-1:0] <= y[WIDTH2-1+WIDTH01:WIDTH01];
// Split MSBs from input x,y
l6[WIDTH3-1:0] <= x[WIDTH3-1+WIDTH012:WIDTH012];
l7[WIDTH3-1:0] <= y[WIDTH3-1+WIDTH012:WIDTH012];
//************* First stage of the adder *****************
q0 <= {1'b0, l0} + {1'b0, l1}; // Add LSBs of x and y
q1 <= {1'b0, l2} + {1'b0, l3}; // Add 2. LSBs of x / y
q2 <= {1'b0, l4} + {1'b0, l5}; // Add 2. MSBs of x/y
q3 <= l6 + l7; // Add MSBs of x and y
//************* Second stage of the adder *****************
v0 <= q0[WIDTH0-1:0]; // Save q0
// Add result from 2. LSBs (x+y) and carry from LSBs
v1 <= q0[WIDTH0] + {1'b0, q1[WIDTH1-1:0]};
// Add result from 2. MSBs (x+y) and carry from 2. LSBs
v2 <= q1[WIDTH1] + {1'b0, q2[WIDTH2-1:0]};
// Add result from MSBs (x+y) and carry from 2. MSBs
v3 <= q2[WIDTH2] + q3;
//************** Third stage of the adder *****************
r0 <= v0; // Delay for LSBs
r1 <= v1[WIDTH1-1:0]; // Delay for 2. LSBs
// Add result from 2. MSBs (x+y) and carry from 2. LSBs
r2 <= v1[WIDTH1] + {1'b0, v2[WIDTH2-1:0]};
// Add result from MSBs (x+y) and carry from 2. MSBs
r3 <= v2[WIDTH2] + v3;
//************ Fourth stage of the adder ******************
s0 <= r0; // Delay for LSBs
s1 <= r1; // Delay for 2. LSBs
s2 <= r2[WIDTH2-1:0]; // Delay for 2. MSBs
// Add result from MSBs (x+y) and carry from 2. MSBs
s3 <= r2[WIDTH2] + r3;
end
assign LSBs_Carry = q0[WIDTH1]; // Provide test signals
assign Middle_Carry = v1[WIDTH1];
assign MSBs_Carry = r2[WIDTH2];
// Build a single output word of
// WIDTH = WIDTH0 + WIDTH1 + WIDTH2 + WIDTH3
assign sum = {s3, s2, s1, s0}; // Connect sum to output
endmodule
| 6.961492 |
module add_4 (
a1,
a2,
s
);
input [2:0] a1, a2;
output wire [3:0] s;
assign s = a1 + a2;
endmodule
| 6.864207 |
module add_42 (
input [7:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out,
output reg z,
output reg v,
output reg n
);
reg [15:0] holder;
always @* begin
if (io_dip[0+0-:1] == 1'h0) begin
holder = a + b;
end else begin
holder = a - b;
end
out = holder[0+15-:16];
if (holder == 1'h0) begin
z = 1'h1;
end else begin
z = 1'h0;
end
v = ((io_dip[7+0-:1] ^ a[15+0-:1]) & (io_dip[7+0-:1] ^ b[15+0-:1]) & ~holder[15+0-:1]) | (~(io_dip[7+0-:1] ^ a[15+0-:1]) & ~(io_dip[7+0-:1] ^ b[15+0-:1]) & holder[15+0-:1]);
n = holder[15+0-:1];
end
endmodule
| 7.613639 |
module add_4_new (
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout
);
wire [4:0] sum;
assign sum = a + b + cin;
assign cout = sum[4];
assign s = sum[3:0];
endmodule
| 6.618152 |
module add_5 (
clk,
rst_n,
din_vld,
// dout_vld,
//ź,dout
dout
);
//
parameter DATA_W = 8;
//źŶ
input clk;
input rst_n;
input din_vld;
//źŶ
// output dout_vld;
output [DATA_W-1:0] dout;
//źreg
reg [DATA_W-1:0] dout;
// reg dout_vld;
reg [DATA_W-1:0] cnt;
wire add_cnt, end_cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
end else if (add_cnt) begin
if (end_cnt) cnt <= 0;
else cnt <= cnt + 2;
end
end
assign add_cnt = din_vld;
assign end_cnt = add_cnt && cnt == 200 - 1;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
dout <= 0;
end else begin
dout <= cnt;
end
end
endmodule
| 6.519817 |
module add_512 (
input wire clk,
input wire rst,
input wire [511 : 0] add_in0,
input wire [511 : 0] add_in1,
output reg [511 : 0] add_out
);
always @(posedge clk)
if (rst) begin
add_out <= 512'b0;
end else begin
add_out <= add_in0 + add_in1;
end
endmodule
| 7.574962 |
module add_516 (
input wire clk,
input wire rst,
input wire [515 : 0] add_in0,
input wire [515 : 0] add_in1,
output reg [515 : 0] add_out
);
always @(posedge clk)
if (rst) begin
add_out <= 516'b0;
end else begin
add_out <= add_in0 + add_in1;
end
endmodule
| 7.919171 |
module add_64 (
a1,
a2,
s
);
input [6:0] a1, a2;
output wire [7:0] s;
assign s = a1 + a2;
endmodule
| 7.070133 |
module ADD_64_test;
parameter n = 64;
reg signed [n-1:0] a, b;
wire signed [n-1:0] sum, carry;
ADD_64 a1 (
sum,
carry,
a,
b
);
initial begin
$dumpfile("ADD_64_test.vcd");
$dumpvars(0, ADD_64_test);
a = 999999999;
b = 12345;
#100;
$display("%d + %d = %d %d", a, b, carry[n-1], sum);
$display("Test Completed");
a = 10;
b = 3;
#100;
$display("%d + %d = %d %d", a, b, carry[n-1], sum);
$display("Test Completed");
end
endmodule
| 6.879811 |
module add_8 (
a1,
a2,
s
);
input [3:0] a1, a2;
output wire [4:0] s;
assign s = a1 + a2;
endmodule
| 6.655259 |
module add_8bit (
a,
b,
c_in,
s,
c_out
);
input [7:0] a;
input [7:0] b;
input c_in;
output [7:0] s;
output c_out;
wire [6:0] c;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(s[0]),
.c_out(c[0])
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.c_in(c[0]),
.s(s[1]),
.c_out(c[1])
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.c_in(c[1]),
.s(s[2]),
.c_out(c[2])
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.c_in(c[2]),
.s(s[3]),
.c_out(c[3])
);
full_adder fa4 (
.a(a[4]),
.b(b[4]),
.c_in(c[3]),
.s(s[4]),
.c_out(c[4])
);
full_adder fa5 (
.a(a[5]),
.b(b[5]),
.c_in(c[4]),
.s(s[5]),
.c_out(c[5])
);
full_adder fa6 (
.a(a[6]),
.b(b[6]),
.c_in(c[5]),
.s(s[6]),
.c_out(c[6])
);
full_adder fa7 (
.a(a[7]),
.b(b[7]),
.c_in(c[6]),
.s(s[7]),
.c_out(c_out)
);
endmodule
| 6.573601 |
module add_8bit_tb;
reg [7:0] a;
reg [7:0] b;
reg c_in;
wire [7:0] s;
wire c_out;
add_8bit uut (
.a(a),
.b(b),
.c_in(c_in),
.s(s),
.c_out(c_out)
);
initial begin
$dumpfile("add_8bit_tb.vcd");
$dumpvars(0, add_8bit_tb);
a = 8'b00000001;
b = 8'b00000001;
c_in = 1'b0;
#10 a = 8'b00000011;
b = 8'b00000101;
c_in = 1'b1;
#10 a = 8'b00000001;
b = 8'b00000001;
c_in = 1'b1;
#10 a = 8'b00000010;
b = 8'b00000011;
c_in = 1'b0;
#10 a = 8'b10000001;
b = 8'b10000001;
c_in = 1'b0;
#10 a = 8'b00011001;
b = 8'b00110001;
c_in = 1'b0;
#10 a = 8'b00110001;
b = 8'b00011001;
c_in = 1'b0;
#10 a = 8'b00000011;
b = 8'b00000011;
c_in = 1'b1;
#10 a = 8'b11111111;
b = 8'b00000001;
c_in = 1'b0;
#10 a = 8'b11111111;
b = 8'b00000000;
c_in = 1'b1;
#10 a = 8'b11111111;
b = 8'b11111111;
c_in = 1'b0;
end
endmodule
| 6.707433 |
module ADD_8_tb;
// Parameters
localparam ELEMENT_BIT_DEPTH = 14;
// Ports
reg [ELEMENT_BIT_DEPTH*8-1:0] addend_array;
wire [ ELEMENT_BIT_DEPTH-1:0] add;
ADD_8 #(
.ELEMENT_BIT_DEPTH(ELEMENT_BIT_DEPTH)
) ADD_8_dut (
.addend_array(addend_array),
.add (add)
);
initial begin
begin
$dumpfile("ADD_8.vcd");
$dumpvars(0, ADD_8_tb);
addend_array = {
14'h0769, 14'h0182, 14'h07b9, 14'h0575, 14'h0668, 14'h034d, 14'h0286, 14'h02d8
};
#5 $finish;
end
end
endmodule
| 7.60826 |
module AddSL (
input [31:0] Add,
input [31:0] Shiftleft,
output [31:0] Result
);
assign Result = Add + Shiftleft;
endmodule
| 6.585724 |
module add_and_square_v6 (
clk,
A,
B,
C,
OUT
);
parameter DEMUX = 16;
parameter NBITS = 3;
localparam NCBITS = DEMUX * NBITS;
// We have 6 output bits: the bottom bit is always 0.
parameter OUTBITS = 6;
input [NCBITS-1:0] A;
input [NCBITS-1:0] B;
input [NCBITS-1:0] C;
output [OUTBITS*DEMUX-1:0] OUT;
input clk;
//% Vectorized A input (now 16x3)
wire [NBITS-1:0] inA[DEMUX-1:0];
//% Vectorized B input (now 16x3)
wire [NBITS-1:0] inB[DEMUX-1:0];
//% Vectorized C input (now 16x3)
wire [NBITS-1:0] inC[DEMUX-1:0];
//% A+B+C (x16)
wire [4:0] sum_of_inputs[DEMUX-1:0];
//% (A+B+C)^2 (x16)
wire [5:0] res_square[DEMUX-1:0];
generate
genvar in_i;
for (in_i = 0; in_i < DEMUX; in_i = in_i + 1) begin : INIT
assign inA[in_i] = A[in_i*NBITS+:NBITS];
assign inB[in_i] = B[in_i*NBITS+:NBITS];
assign inC[in_i] = C[in_i*NBITS+:NBITS];
assign OUT[in_i*OUTBITS+:OUTBITS] = res_square[in_i];
end
endgenerate
generate
genvar ii;
for (ii = 0; ii < DEMUX; ii = ii + 1) begin : EXTEND_LOOP
ternary_add_logic u_ternary_add (
.A (inA[ii]),
.B (inB[ii]),
.C (inC[ii]),
.D (sum_of_inputs[ii]),
.CLK(clk)
);
slice_square_logic u_slicesquare (
.I (sum_of_inputs[ii]),
.SQR(res_square[ii]),
.CLK(clk)
);
end
endgenerate
endmodule
| 6.70474 |
module add_array #(
parameter WL = 16
) (
input clk,
input [WL-1:0] add_array_in0,
input [WL-1:0] add_array_in1,
input [WL-1:0] add_array_in2,
input [WL-1:0] add_array_in3,
input [WL-1:0] add_array_in4,
input [WL-1:0] add_array_in5,
input [WL-1:0] add_array_in6,
input [WL-1:0] add_array_in7,
input [WL-1:0] add_array_in8,
input [WL-1:0] add_array_in9,
input [WL-1:0] add_array_in10,
input [WL-1:0] add_array_in11,
input [WL-1:0] add_array_in12,
input [WL-1:0] add_array_in13,
input [WL-1:0] add_array_in14,
input [WL-1:0] add_array_in15,
output [WL-1:0] add_array_out
);
wire [WL-1:0] s0_out0;
wire [WL-1:0] s0_out1;
wire [WL-1:0] s0_out2;
wire [WL-1:0] s0_out3;
wire [WL-1:0] s0_out4;
wire [WL-1:0] s0_out5;
wire [WL-1:0] s0_out6;
wire [WL-1:0] s0_out7;
wire [WL-1:0] s1_out0;
wire [WL-1:0] s1_out1;
wire [WL-1:0] s1_out2;
wire [WL-1:0] s1_out3;
wire [WL-1:0] s2_out0;
wire [WL-1:0] s2_out1;
add add1 (
.A (add_array_in0),
.B (add_array_in1),
.S (s0_out0),
.CLK(clk)
);
add add2 (
.A (add_array_in2),
.B (add_array_in3),
.S (s0_out1),
.CLK(clk)
);
add add3 (
.A (add_array_in4),
.B (add_array_in5),
.S (s0_out2),
.CLK(clk)
);
add add4 (
.A (add_array_in6),
.B (add_array_in7),
.S (s0_out3),
.CLK(clk)
);
add add5 (
.A (add_array_in8),
.B (add_array_in9),
.S (s0_out4),
.CLK(clk)
);
add add6 (
.A (add_array_in10),
.B (add_array_in11),
.S (s0_out5),
.CLK(clk)
);
add add7 (
.A (add_array_in12),
.B (add_array_in13),
.S (s0_out6),
.CLK(clk)
);
add add8 (
.A (add_array_in14),
.B (add_array_in15),
.S (s0_out7),
.CLK(clk)
);
add add9 (
.A (s0_out0),
.B (s0_out1),
.S (s1_out0),
.CLK(clk)
);
add add10 (
.A (s0_out2),
.B (s0_out3),
.S (s1_out1),
.CLK(clk)
);
add add11 (
.A (s0_out4),
.B (s0_out5),
.S (s1_out2),
.CLK(clk)
);
add add12 (
.A (s0_out6),
.B (s0_out7),
.S (s1_out3),
.CLK(clk)
);
add add13 (
.A (s1_out0),
.B (s1_out1),
.S (s2_out0),
.CLK(clk)
);
add add14 (
.A (s1_out2),
.B (s1_out3),
.S (s2_out1),
.CLK(clk)
);
add add15 (
.A (s2_out0),
.B (s2_out1),
.S (add_array_out),
.CLK(clk)
);
endmodule
| 6.56336 |
module Add_B (
entrada_AddPC,
entrada_Imediato,
saida_addB
);
input [31:0] entrada_AddPC, entrada_Imediato;
output wire [31:0] saida_addB;
assign saida_addB = entrada_AddPC + entrada_Imediato;
endmodule
| 7.998531 |
modules/adder/add32.v"
`endif
module add_bpc(EX_npc, EX_imm, EX_bpc);
input wire [31:0] EX_npc, EX_imm;
output wire [31:0] EX_bpc;
wire cout;
wire cin = 0;
add32 add32(
.a(EX_npc),
.b(EX_imm),
.cin(cin),
.s(EX_bpc),
.cout(cout)
);
endmodule
| 7.633156 |
module ADD_Branch (
i_op1,
i_op2,
o_out
);
input [`WIDTH_BRANCH-1:0] i_op1;
input [`WIDTH_BRANCH-1:0] i_op2;
output [`WIDTH_BRANCH-1:0] o_out;
assign o_out = i_op1 + i_op2;
endmodule
| 7.19109 |
module add_char
(
input wire clk ,
input wire rst_n ,
input wire [20:0] A,
input wire [17:0] B,
output wire [21:0] C
);
//寄存
reg [20:0] reg_A;
reg [17:0] reg_B;
always@(posedge clk or negedge rst_n)
if()
endmodule
| 7.167624 |
module add_circuit (
input wire x,
input wire y,
input wire cin,
output wire z,
output wire cout
);
wire [1:0] temp;
assign temp = {1'b0, x} + {1'b0, y} + {1'b0, cin};
assign z = temp[0];
assign cout = temp[1];
endmodule
| 6.50232 |
module add_circuit2 (
input wire [7:0] x,
input wire [7:0] y,
output wire [7:0] z,
output wire cout
);
localparam N = 8, N1 = N - 1;
wire [N:0] temp;
assign temp = {1'b0, x} + {1'b0, y};
assign z = temp[N1:0];
assign cout = temp[N];
endmodule
| 6.596746 |
module add_circuit3 #(
parameter N = 3
) (
input wire [ N:0] x,
input wire [ N:0] y,
output wire [N+1:0] z
// output wire cout
);
localparam N1 = N - 1;
wire [N:0] temp;
assign temp = {1'b0, x} + {1'b0, y};
assign z = temp;
//assign z = temp[N1:0];
//assign cout = temp[N];
endmodule
| 7.796889 |
module ADD_CLA_24 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [23:0] iA, iB;
input iC;
output [23:0] oS;
output oG, oP, oC;
wire [2:0] G, P, C;
ADD_CLA_8 adder0 (
.iA(iA[7:0]),
.iB(iB[7:0]),
.iC(C[0]),
.oS(oS[7:0]),
.oG(G[0]),
.oP(P[0]),
.oC()
);
ADD_CLA_8 adder1 (
.iA(iA[15:8]),
.iB(iB[15:8]),
.iC(C[1]),
.oS(oS[15:8]),
.oG(G[1]),
.oP(P[1]),
.oC()
);
ADD_CLA_8 adder2 (
.iA(iA[23:16]),
.iB(iB[23:16]),
.iC(C[2]),
.oS(oS[23:16]),
.oG(G[2]),
.oP(P[2]),
.oC()
);
CLA_3 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 6.994189 |
module ADD_CLA_4 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [3:0] iA, iB;
input iC;
output [3:0] oS;
output oG, oP, oC;
wire [3:0] G, P, C;
assign G = iA & iB;
assign P = iA | iB;
CLA_4 ADD_CLA_4_ (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
assign oS = iA ^ iB ^ C;
endmodule
| 7.109737 |
module ADD_CLA_8 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [7:0] iA, iB;
input iC;
output [7:0] oS;
output oG, oP, oC;
wire [1:0] G, P, C;
ADD_CLA_4 adder0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0]),
.oC()
);
ADD_CLA_4 adder1 (
.iA(iA[7:4]),
.iB(iB[7:4]),
.iC(C[1]),
.oS(oS[7:4]),
.oG(G[1]),
.oP(P[1]),
.oC()
);
CLA_2 cla (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
.oC({oC, C})
);
endmodule
| 7.544648 |
module ADD_CLA_8_tb ();
reg [7:0] iA, iB;
reg iC;
wire [7:0] oS;
wire oG, oP, oC;
ADD_CLA_8 ADD_CLA_8_ (
.iA(iA),
.iB(iB),
.iC(iC),
.oS(oS),
.oG(oG),
.oP(oP),
.oC(oC)
);
initial begin
#0;
iA = 8'd125;
iB = 8'd11;
iC = 1'b0;
#10;
iA = 8'd127;
iB = 8'd105;
iC = 1'b1;
#10;
iA = 8'b11111111;
iB = 8'b11111111;
iC = 1'b1;
end
endmodule
| 6.731247 |
module ADD_CLA_FINAL (
a,
b,
symbol,
out
);
parameter DATA_WIDTH = 32;
input [DATA_WIDTH - 1:0] a, b;
input symbol;
output [DATA_WIDTH - 1:0] out;
wire [24:0] fraction_25;
wire [7:0] diff_exp, exp_max, exp_max_tmp;
wire sign_diff_exp, cout_exp_tmp;
wire [31:0] out_normal, out_special;
wire check_special;
smallALU_CLA SMALL_ALU_CLA (
.in_0(a[30:23]),
.in_1(b[30:23]),
.out(diff_exp),
.sign_out(sign_diff_exp)
);
control_CLA CONTROL_CLA (
.diff_exp(diff_exp),
.sign_exp(sign_diff_exp),
.fraction_a({1'b1, a[22:0]}),
.fraction_b({1'b1, b[22:0]}),
.sign_a(a[31]),
.sign_b(b[31]),
.symbol(symbol),
.sign_out(out_normal[31]),
.out(fraction_25)
);
exponent_max_cla EXP_MAX_CLA (
.exp_0 (a[30:23]),
.exp_1 (b[30:23]),
.exp_max(exp_max_tmp)
);
SUB_CLA_8 FS_EXP_MAX_CLA (
.iA(exp_max_tmp),
.iB(8'b01111111),
.iC(1'b0),
.oS(exp_max),
.oC(cout_exp_tmp),
.oP(),
.oG()
);
Norm_CLA NORM_FRAC_CLA (
.exp_max(exp_max),
.fraction_25(fraction_25),
.exp_out(out_normal[30:23]),
.fraction_out(out_normal[22:0])
);
Special_Add SP_ADD (
.a(a),
.b(b),
.symbol(symbol),
.out(out_special),
.check_special(check_special)
);
assign out = (check_special == 1'b0) ? ((a == b) ? 32'd0 : ({32{!check_special}} & (out_normal)) | ({32{check_special}} & (out_special))) : out_special;
endmodule
| 7.751084 |
module add_const (
out,
in
);
parameter const_val = 1;
output [31:0] out;
input [31:0] in;
assign out = in + const_val;
endmodule
| 7.470997 |
module add_const_design (
clk,
a,
b,
z
);
input clk;
input [3:0] a;
input [3:0] b;
output reg [3:0] z;
always @(posedge clk) z <= a + b + (1'b1 - 1'b1);
endmodule
| 6.944334 |
module add_ex (
input clk,
input [31:0] pc_in,
input [31:0] shift_in,
output [31:0] add
);
reg [31:0] addition;
always @(posedge clk) begin
addition <= pc_in + shift_in;
end
assign add = addition;
endmodule
| 7.224738 |
module add_exec1 (
rs_index,
rs1_data,
rs2_data,
func,
rob_ind,
clk1,
clk2,
rd,
ex_b
);
input [7:0] rs1_data;
input [7:0] rs2_data;
input [3:0] func, rd;
input [2:0] rob_ind, rs_index;
input clk1, clk2, ex_b;
integer count_as;
integer temp, temp1;
reg [15:0] out1;
// add = 2cyles (40units)
// sub = 2cyles (40units)
// mul = 3cyles (60units)
// add = 4cyles (80units)
always @(posedge clk1) begin
if (ex_b == 1) begin
count_as = 0;
case (func)
4'b0000: begin
out1 <= #40 rs1_data + rs2_data;
count_as <= #41 1;
tomasulo.ROB[rob_ind][2] <= #40 rs1_data + rs2_data;
tomasulo.regbank[rd][1] <= #40 16'b1000;
tomasulo.regbank[rd][0] <= #40 rs1_data + rs2_data;
tomasulo.add_array[rs_index][6] <= #40 0;
tomasulo.pr3_exec_b[0] <= #40 0; //Making it free
tomasulo.pr3_addcount <= #40 tomasulo.pr3_addcount - 1;
tomasulo.add_count <= #40 tomasulo.add_count - 1; //This is for RS
#42;
end
4'b0001: begin
out1 <= #40 rs1_data - rs2_data;
count_as <= #40 1;
// tomasulo.pr3_addexec = 0;
tomasulo.ROB[rob_ind][2] <= #40 rs1_data - rs2_data;
tomasulo.regbank[rd][1] <= #40 16'b1000;
tomasulo.regbank[rd][0] <= #40 rs1_data - rs2_data;
tomasulo.add_array[rs_index][6] <= #40 0;
tomasulo.pr3_exec_b[0] <= #40 0; //Making it free
tomasulo.pr3_addcount <= #40 tomasulo.pr3_addcount - 1; //This is for exec
tomasulo.add_count <= #40 tomasulo.add_count - 1; //This is for RS
#42;
end
endcase
for (temp = 0; temp < 3 && (count_as == 1); temp++) begin
if (tomasulo.add_array[temp][4] == 0) begin
if (tomasulo.add_array[temp][1] == rd) tomasulo.add_array[temp][4] = 1;
end
if (tomasulo.add_array[temp][5] == 0) begin
if (tomasulo.add_array[temp][2] == rd) tomasulo.add_array[temp][5] = 1;
end
end
for (temp = 0; temp < 3 && (count_as == 1); temp++) begin
if (tomasulo.mul_array[temp][4] == 0) begin
if (tomasulo.mul_array[temp][1] == rd) tomasulo.mul_array[temp][4] = 1;
end
if (tomasulo.mul_array[temp][5] == 0) begin
if (tomasulo.mul_array[temp][2] == rd) tomasulo.mul_array[temp][5] = 1;
end
end
if (count_as == 1) begin
$display("\nExec unit 1 :");
$display("rs1_data = %b, rs2_data = %b, funct = %b, rob_ind = %b,out = %b\n", rs1_data,
rs2_data, func, rob_ind, out1);
end
end
end
endmodule
| 9.024716 |
module add_exec2 (
rs_index,
rs1_data,
rs2_data,
func,
rob_ind,
clk1,
clk2,
rd,
ex_b
);
input [7:0] rs1_data;
input [7:0] rs2_data;
input [3:0] func, rd;
input [2:0] rob_ind, rs_index;
input clk1, clk2, ex_b;
integer count_as;
integer temp, temp1;
reg [15:0] out1;
always @(posedge clk1) begin
if (ex_b == 1) begin
count_as = 0;
case (func)
4'b0000: begin
out1 <= #40 rs1_data + rs2_data;
count_as <= #41 1;
// tomasulo.pr3_addexec = 0;
tomasulo.ROB[rob_ind][2] <= #40 rs1_data + rs2_data;
tomasulo.regbank[rd][1] <= #40 16'b1000;
tomasulo.regbank[rd][0] <= #40 rs1_data + rs2_data;
tomasulo.add_array[rs_index][6] <= #40 0;
tomasulo.pr3_exec_b[1] <= #40 0; //Making it free
tomasulo.pr3_addcount <= #40 tomasulo.pr3_addcount - 1; //This is foe exec
tomasulo.add_count <= #40 tomasulo.add_count - 1; //This is for RS
#42;
end
4'b0001: begin
out1 <= #40 rs1_data - rs2_data;
count_as <= #41 1;
// tomasulo.pr3_addexec = 0;
tomasulo.ROB[rob_ind][2] <= #40 rs1_data - rs2_data;
tomasulo.regbank[rd][1] <= #40 16'b1000;
tomasulo.regbank[rd][0] <= #40 rs1_data - rs2_data;
tomasulo.add_array[rs_index][6] <= #40 0;
tomasulo.pr3_exec_b[1] <= #40 0; //Making it free
tomasulo.pr3_addcount <= #40 tomasulo.pr3_addcount - 1;
tomasulo.add_count <= #40 tomasulo.add_count - 1; //This is for RS
#42;
end
endcase
for (temp = 0; temp < 3 && (count_as == 1); temp++) begin
if (tomasulo.add_array[temp][4] == 0) begin
if (tomasulo.add_array[temp][1] == rd) tomasulo.add_array[temp][4] = 1;
end
if (tomasulo.add_array[temp][5] == 0) begin
if (tomasulo.add_array[temp][2] == rd) tomasulo.add_array[temp][5] = 1;
end
end
for (temp = 0; temp < 3 && (count_as == 1); temp++) begin
if (tomasulo.mul_array[temp][4] == 0) begin
if (tomasulo.mul_array[temp][1] == rd) tomasulo.mul_array[temp][4] = 1;
end
if (tomasulo.mul_array[temp][5] == 0) begin
if (tomasulo.mul_array[temp][2] == rd) tomasulo.mul_array[temp][5] = 1;
end
end
if (count_as == 1) begin
$display("\nExec unit 2 : ");
$display("rs1_data = %b, rs2_data = %b, funct = %b, rob_ind = %b,out = %b\n", rs1_data,
rs2_data, func, rob_ind, out1);
end
end
end
endmodule
| 9.320063 |
module full (
input a,
input b,
input c,
output s,
output v
);
assign s = a ^ b ^ c;
assign v = a & (b | c) | b & c;
endmodule
| 7.892995 |
module add5 (
input [4:0] a,
b,
output [5:0] c
);
wire [3:0] v;
full a0 (
a[0],
b[0],
1'b0,
c[0],
v[0]
);
full a1 (
a[1],
b[1],
v[0],
c[1],
v[1]
);
full a2 (
a[2],
b[2],
v[1],
c[2],
v[2]
);
full a3 (
a[3],
b[3],
v[2],
c[3],
v[3]
);
full a4 (
a[4],
b[4],
v[3],
c[4],
c[5]
);
endmodule
| 6.662767 |
module add_fan_out (
input [1:0] in0,
input [1:0] in1,
output [1:0] out0,
output [1:0] out1,
input clk
);
reg [1:0] res0;
reg [1:0] res1;
always @(posedge clk) begin
res0 <= in0 + in1;
res1 <= in0 - in1;
end
assign out0 = res0;
assign out1 = res1;
endmodule
| 6.897195 |
module add_ff_design (
clk,
reset_,
a,
b,
z
);
input clk;
input reset_;
input [3:0] a;
input [3:0] b;
output reg [3:0] z;
always @(posedge clk, negedge reset_)
if (!reset_) begin
z <= 0;
end else begin
z <= a + b;
end
endmodule
| 7.173034 |
module add_fp_clk (
clk,
rst_n
, ena_add_fp_clk
, data_in_1
, data_in_2
, data_out
);
parameter DATA_WIDTH = 32;
input clk;
input rst_n;
input ena_add_fp_clk;
input [DATA_WIDTH-1:0] data_in_1;
input [DATA_WIDTH-1:0] data_in_2;
output [DATA_WIDTH-1:0] data_out;
reg [DATA_WIDTH-1:0] dff_data_in_1;
reg [DATA_WIDTH-1:0] dff_data_in_2;
reg [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] data_out_wire;
//////////////////////////////////
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dff_data_in_1 <= 0;
end else if (ena_add_fp_clk) begin
dff_data_in_1 <= data_in_1;
end else begin
dff_data_in_1 <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dff_data_in_2 <= 0;
end else if (ena_add_fp_clk) begin
dff_data_in_2 <= data_in_2;
end else begin
dff_data_in_2 <= 0;
end
end
floating_point_adder floating_point_adder_01 (
.clk(clk)
, .rst_n(rst_n)
, .input_factor_01(dff_data_in_1)
, .input_factor_02(dff_data_in_2)
, .output_adder(data_out_wire)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else if (ena_add_fp_clk) begin
data_out <= data_out_wire;
end else begin
data_out <= data_out;
end
end
endmodule
| 7.585168 |
module add_full (
input a,
input b,
input cin,
output cout,
output s
);
assign cout = a & b | a & cin | b & cin;
assign s = ~a & ~b & cin | ~a & b & ~cin | a & ~b & ~cin | a & b & cin;
endmodule
| 7.057721 |
module add_func (
X,
Y,
sum,
overflow
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] sum;
output wire overflow;
wire ci = 0;
add_rca_32_bit adder (
.X (X),
.Y (Y),
.ci (ci),
.sum(sum),
.co (overflow)
);
endmodule
| 8.216946 |
module add_g (
input clk,
input rst,
input [10:0] data_0,
input [10:0] data_1,
output reg signed [11:0] result
);
always @(posedge clk) begin
if (rst) result <= 0;
else result <= data_1 - data_0;
end
endmodule
| 7.113429 |
module add_half (
input a,
b,
output reg c_out,
output sum
);
my_xor XOR1 (
a,
b,
sum
);
always @(*) begin
// sum = a ^ b;
c_out <= a & b;
end
endmodule
| 7.260022 |
module add_judge_r (
input [9215:0] vout,
input [14*27-1:0] index_judge_in,
output reg flag
);
integer j;
always @(*) begin
flag = 0;
for (j = 0; j < 27; j = j + 1) flag = flag + vout[index_judge_in[j*14+:14]];
end
endmodule
| 6.779657 |
module add_key (
addKeyOut,
roundText,
roundKey
);
output [63:0] addKeyOut;
input [63:0] roundText;
input [79:0] roundKey;
assign addKeyOut = roundText ^ roundKey[63:0];
endmodule
| 7.292369 |
module add_mega (
add_sub,
dataa,
datab,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire sub_wire0;
wire [31:0] sub_wire1;
wire overflow = sub_wire0;
wire [31:0] result = sub_wire1[31:0];
lpm_add_sub LPM_ADD_SUB_component (
.add_sub(add_sub),
.datab(datab),
.dataa(dataa),
.overflow(sub_wire0),
.result(sub_wire1)
// synopsys translate_off
, .aclr(),
.cin(),
.clken(),
.clock(),
.cout()
// synopsys translate_on
);
defparam LPM_ADD_SUB_component.lpm_direction = "UNUSED", LPM_ADD_SUB_component.lpm_hint =
"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_ADD_SUB_component.lpm_width = 32;
endmodule
| 7.100227 |
module add_mega (
add_sub,
dataa,
datab,
overflow,
result
);
input add_sub;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
endmodule
| 7.100227 |
module add_mlt(input clk,
input[15:0]dataa,datab,
input ld_a,ld_b,ld_p,cr_p,dc_b,
output [15:0]ax,py,bd,
output zero,[15:0]out
);
Reg1 A(.load(ld_a),.data(dataa),.clk(clk),.X(ax));
Reg2 P(.load_P(ld_p),.clear_p(cr_p),.data_P(out),.clk(clk),.Y(py));
Reg3 B(.loadb(ld_b),.clk(clk),.dcb(dc_b),.datb(datab),.datout(bd));
comp CMP(.clk(clk),.in(bd),.zer(zero));
multiply ADD(.clk(clk),.eqzero(zero),.a(ax),.p(py),.Z(out));
endmodule
| 6.637452 |
module add_mod (
input wire clk,
input wire [23:0] a,
input wire [23:0] b,
output wire [23:0] out
);
reg [24:0] sum;
always @(posedge clk) sum <= a + b;
assign out = sum - (sum >= 24'd12587009 ? 24'd12587009 : 23'd0);
endmodule
| 7.093165 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module add_module(Clk, data_in, reset, enable, textOut, next, done);
input Clk;
input [7:0] data_in;
input reset;
input enable;
input next;
output reg [8*32:0] textOut;
output reg done;
reg [8:0] data_out;
reg [7:0] input_A, input_B;
reg [4:0] state;
localparam
START = 5'b00001,
LOAD_A = 5'b00010,
LOAD_B = 5'b00100,
CALCULATE = 5'b01000,
DONE = 5'b10000;
always @(posedge Clk, posedge reset)
begin
//if (!enable)
//begin
//end
//else
//begin
if (reset)
begin
state <= START;
end
else
begin
case (state)
START:
begin
textOut = "Addition Adds 2 Numbers ";
input_A <= 0;
input_B <= 0;
done <= 0;
data_out <= 0;
if (next && enable)
state <= LOAD_A;
end
LOAD_A:
begin
textOut = "Input 1st # Then Press Btnc ";
if (next)
begin
input_A <= data_in;
state <= LOAD_B;
end
end
LOAD_B:
begin
textOut = "Input 2nd # Then Press Btnc ";
if (next)
begin
input_B <= data_in;
state <= CALCULATE;
end
end
CALCULATE:
begin
data_out <= input_A + input_B;
textOut = "Calculating... ";
if (next)
state <= DONE;
end
DONE:
begin
textOut = {"The Sum is: ", bin2x({0,0,0,data_out[8]}), bin2x(data_out[7:4]), bin2x(data_out[3:0]), " "};
done <= 1;
end
endcase
end
//end
end
function [7:0] bin2x;
input [3:0] data;
begin
case (data)
4'h0: bin2x = "0";4'h1: bin2x = "1";4'h2: bin2x = "2";4'h3: bin2x = "3";
4'h4: bin2x = "4";4'h5: bin2x = "5";4'h6: bin2x = "6";4'h7: bin2x = "7";
4'h8: bin2x = "8";4'h9: bin2x = "9";4'hA: bin2x = "A";4'hB: bin2x = "B";
4'hC: bin2x = "C";4'hD: bin2x = "D";4'hE: bin2x = "E";4'hF: bin2x = "F";
default:bin2x = "0";
endcase
end
endfunction
endmodule
| 7.088073 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_16_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 7.018182 |
module adder (
a,
b,
y
);
input a, b;
output y;
reg y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_1_bit (
a,
b,
operation,
Result
);
input a, b;
input operation;
output Result;
reg Result;
wire Result_add;
wire Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
//always@(a or b or operation)
// begin
// case (operation)
// 1'b0: Result = Result_add; // Addition
// 1'b1: Result = Result_mul; // multiply
//endcase
// end
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 6.690052 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_2_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 6.768282 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_32_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 7.393024 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_4_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 7.496552 |
module adder (
a,
b,
y
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_64_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 64;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 7.073299 |
module adder (
a,
b,
y
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
//output [0:WIDTH-1] y;
output reg [0:(WIDTH*2)-1] y;
wire [0:WIDTH-1] g;
assign g = 0;
always @(a or b) begin
y = {g, (a + b)};
end
endmodule
| 7.4694 |
module add_mul_8_bit (
a,
b,
operation,
Result
);
parameter WIDTH = 8;
input [0:WIDTH-1] a, b;
input operation;
output reg [0:(WIDTH*2)-1] Result;
wire [0:(WIDTH*2)-1] Result_add;
wire [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
always @(*) begin
Result = operation ? Result_mul : Result_add;
end
endmodule
| 6.776442 |
module adder (
a,
b,
y
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_16_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 16;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_2_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 2;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_32_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 32;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
module adder (
a,
b,
y
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] y;
always @(a or b) begin
y = a + b;
end
endmodule
| 7.4694 |
module add_mul_combine_4_bit (
a,
b,
Result_mul,
Result_add
);
parameter WIDTH = 4;
input [0:WIDTH-1] a, b;
output reg [0:WIDTH-1] Result_add;
output reg [0:(WIDTH*2)-1] Result_mul;
adder adder_1 (
.a(a),
.b(b),
.y(Result_add)
);
multiplier multiplier_1 (
.a(a),
.b(b),
.y(Result_mul)
);
endmodule
| 6.911403 |
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