code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module for alu
module alu(x,y,z,c_in,c_out,lt,eq,gt,overflow,ALUOp);
// Declare variables to be connected to inputs and outputs
input [15:0] x;
input [15:0] y;
output reg [15:0] z;
input c_in;
output reg c_out=0;
output reg lt,eq,gt;
output reg overflow;
input [2:0] ALUOp;
always @(x,y,ALUOp)
begin
case(ALUOp)
3'... | 8.189305 |
module ALU (
input [3:0] inA,
input [3:0] inB,
input [1:0] op,
output [3:0] ans
);
//Ŀ
assign ans = (op == 2'b00) ? inA & inB :
(op == 2'b01) ? inA | inB :
(op == 2'b10) ? inA ^ inB :
(op == 2'b11) ? inA + inB
: 4'b000 ; //error
endmodule
| 7.960621 |
module ALU (
input [3:0] inA,
input [3:0] inB,
input [1:0] inC,
input [1:0] op,
output [3:0] ans
);
assign ans = (op == 2'b00) ? $signed(
$signed(inA) >>> inC
) : (op == 2'b01) ? inA >> inC : (op == 2'b10) ? inA - inB : (op == 2'b11) ? inA + inB : 4'b0000;
endmodule
| 7.960621 |
module add (
input [31:0] a,
b,
input funct,
output reg [31:0] addres,
output reg cout
);
reg x;
always @(*) begin
case (funct)
2'b0: begin
{cout, addres} = a + b;
end
2'b1: begin
{x, addres} = a - b;
cout = 0;
end
endcase
end
endmodule
| 6.686118 |
module calc (
input [31:0] a,
b,
input funct,
output reg [31:0] calres,
output reg ovf
);
reg [31:0] cal;
always @(*) begin
case (funct)
1'b0: begin
{cal, calres} = a * b;
if (cal == 32'd0) ovf = 0;
else ovf = 1;
end
1'b1: begin
calres = a / ... | 6.573936 |
module ALU (
input clock,
input reset,
input [ 3:0] io_operation,
input [31:0] io_inputx,
input [31:0] io_inputy,
output [31:0] io_result
);
wire [31:0] _T_1 = io_inputx & io_inputy;
wire [31:0] _T_3 = io_inputx | io_inputy;
wire [31:0] _T_6 = io_inputx + io_inputy;
wi... | 7.960621 |
module ALU( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_in1, // @[:@6.4]
input [31:0] io_in2, // @[:@6.4]
input [12:0] io_alu_opcode, // @[:@6.4]
output [31:0] io_out // @[:@6.4]
);
wire [31:0] _T_21 = io_in1 + io_in2; // @[ALUTester.scala 38:32:@13.4]
... | 6.800631 |
module ALU (
result,
zero,
A,
B,
control
);
`include "Parameters.vh"
input [XLEN - 1 : 0] A; // Operand A
input [XLEN - 1 : 0] B; // Operand B
input [2 : 0] control;
output zero;
output reg [XLEN - 1 : 0] result;
// ALU Operations
always @(*) begin
case (control)
ADD_OP... | 8.31389 |
module alu1 (
out,
carryout,
A,
B,
carryin,
control
);
output out, carryout;
input A, B, carryin;
input [2:0] control;
wire xor_input, sum, logicout;
xor x1 (xor_input, B, control[0]);
full_adder f1 (
sum,
carryout,
A,
xor_input,
carryin
);
logicuni... | 7.4996 |
module alu16 (
input wire [15:0] alu16_arg1,
input wire [15:0] alu16_arg2,
output reg [15:0] alu16_out,
input wire [ 2:0] alu16_op,
input wire [ 7:0] alu16_flags_in,
output reg [ 7:0] alu16_flags_out
);
`include "ucode_consts.vh"
parameter FLAG_S = 7; // sign flag
parameter FLAG_Z... | 7.135467 |
module ALU16B (
input logic [15:0] in1,
in2,
input logic [3:0] opCode,
output logic [15:0] out,
output negative,
zero
);
logic [15:0] in1Selector, in2Selector, outSelector;
assign in1Selector = opCode[3] ? ~in1 : in1;
assign in2Selector = opCode[2] ? ~in2 : in2;
assign outSelector = (o... | 7.260804 |
module mux_16bit (
a,
b,
c,
d,
sel,
out
);
input [15:0] a, b, c, d;
input [1:0] sel;
output [15:0] out;
assign out = sel[1] ? (sel[0] ? a : b) : (sel[0] ? c : d);
endmodule
| 7.354098 |
module mux_1bit (
a,
b,
c,
d,
sel,
out
);
input a, b, c, d;
input [1:0] sel;
output out;
assign out = sel[1] ? (sel[0] ? a : b) : (sel[0] ? c : d);
endmodule
| 8.087151 |
module fa1 (
a,
b,
cin,
cout,
s
);
input a, b, cin;
output cout, s;
wire w1, w2, w3;
xor a1 (w1, a, b);
and a2 (w2, a, b);
and a3 (w3, cin, w1);
xor a4 (s, w1, cin);
or a5 (cout, w3, w2);
endmodule
| 7.927977 |
module fa4 (
a,
b,
cin,
cout,
s
);
input [3:0] a, b;
input cin;
output cout;
output [3:0] s;
wire c1, c2, c3;
fa1 a1 (
a[0],
b[0],
cin,
c1,
s[0]
);
fa1 a2 (
a[1],
b[1],
c1,
c2,
s[1]
);
fa1 a3 (
a[2],
b[2],... | 7.255881 |
module fa16 (
a,
b,
cin,
cout,
s
);
input [15:0] a, b;
input cin;
output cout;
output [15:0] s;
//cout = overflow
wire c1, c2, c3;
fa4 a41 (
a[3:0],
b[3:0],
cin,
c1,
s[3:0]
);
fa4 a42 (
a[7:4],
b[7:4],
c1,
c2,
s[7:4]
);... | 6.682792 |
module sub4 (
a,
b,
cin,
sel,
cout,
ov,
s
);
input [3:0] a, b;
input cin, sel;
output cout, ov;
output [3:0] s;
wire c1, c2, c3;
fa1 sa1 (
a[0],
b[0] ^ sel,
cin,
c1,
s[0]
);
fa1 sa2 (
a[1],
b[1] ^ sel,
c1,
c2,
s[1]... | 7.03439 |
module sub16 (
a,
b,
ov,
s
);
input [15:0] a, b;
output ov;
output [15:0] s;
wire c1, c2, c3;
sub4 s1 (
a[3:0],
b[3:0],
1'b1,
1'b1,
c1
,,
s[3:0]
);
sub4 s2 (
a[7:4],
b[7:4],
c1,
1'b1,
c2
,,
s[7:4]
);
... | 7.317719 |
module divider (
a,
b,
out,
ov
);
input [15:0] a, b;
output [15:0] out;
output ov;
reg [31:0] temp;
reg [15:0] q;
reg [15:0] dividor;
always @(a, b) begin
q = a;
dividor = b;
temp = {16'b0, q};
//pdf에 제시된 방식이용 , 16bit -> 16번반복
repeat (16) begin
if (temp[31:16]... | 7.389371 |
module ALU16bit (
a,
b,
sel,
ov,
out
);
input [15:0] a, b;
input [1:0] sel;
output ov;
output [15:0] out;
wire [15:0] add, sub, mul, div;
wire ov1, ov2, ov3, ov4;
fa16 alu_add (
a,
b,
1'b0,
ov1,
add
);
sub16 alu_sub (
a,
b,
ov2,
... | 6.964646 |
module alu16_unit_24 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
wire [16-1:0] M_compare_out;
reg [ 1-1:0] M_compare_z;
reg [ 1-1:0] M_compare_v;
reg [ 1-1:0] M_compare_n;
reg [ 6-1:0] M_compare_alufn;
compare_unit_27 compare (
.z(M_compare_z),
... | 6.598123 |
module fulladder (
input wire a,
b,
c,
output wire sum,
c_out
);
wire x1, a1, a2;
xor xor1 (x1, a, b); // xor(out, in, in);
xor xor2 (sum, x1, c);
and and1 (a1, a, b); // and(out, in, in);
and and2 (a2, x1, c);
or or1 (c_out, a1, a2); // or(out, in, in);
endmodule
| 7.454465 |
module ALU_1bits (
input wire a_i,
input wire b_i,
input wire c_i,
input wire [1:0] op,
output wire r_o,
output wire c_o
);
wire and_o, or_o, add_o, zero;
assign and_o = a_i & b_i;
assign or_o = a_i | b_i;
assign zero = 1'b0;
fulladder adder (
a_i,
b_i,
c_i,
... | 7.548747 |
module alu2 (
Out,
A,
B
);
input signed [15:0] A, B;
output signed [15:0] Out;
assign Out = A + B;
endmodule
| 8.232598 |
module meiaSoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.280431 |
module meiaSoma
//-----------------
//-- Soma Completa
//-----------------
module somaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaSoma MS1 (s2, s3, a, b);
meiaSoma MS2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.661006 |
module somaCompleta
// ----------------------
// -- Somador de 4 bits
// ----------------------
module somador4bits(s0, s1, s2, s3, carry, comparador, a0, a1, a2, a3, b0 ,b1, b2, b3);
output s0, s1, s2, s3, carry, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
somaCompleta SM1(s0, w1, b0, a1, 0... | 7.41852 |
module somador
//------------------
//-- Meia Diferena
//------------------
module meiaDiferenca(s0, s1, a ,b);
output s0, s1;
input a, b;
wire s2;
xor XOR1 (s0, a, b);
not NOT1 (s2, a);
and AND1 (s1, b, s2);
endmodule
| 7.81062 |
module Meia Diferena
//----------------------
//-- Diferena Completa
//----------------------
module diferencaCompleta(s0, s1, a, b, c);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
meiaDiferenca MD1 (s2, s3, a, b);
meiaDiferenca MD2 (s0, s4, s2, c);
or OR1 (s1, s3, s4);
endmodule
| 7.055737 |
module Diferenca Completa
// ----------------------
// -- Subtrator de 4 bits
// ----------------------
module subtrator4bits(s0, s1, s2, s3, comparador, a0, a1, a2, a3, b0, b1, b2, b3);
output s0, s1, s2, s3, comparador;
input a0, a1, a2, a3, b0 ,b1, b2, b3;
wire w1, w2, w3;
diferencaCompleta DC1 (s0, w1, a0 ,b0, ... | 6.693215 |
module comparadorLogico
// ------------------------
// -- Incremento de 1 em a
// ------------------------
module incremento_de_1_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
somador4bits S4B1(s0, s1, s2, s3, s4, s5, a0, a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.063838 |
module
// ------------------------
// -- Incremento de 1 em b
// ------------------------
module incremento_de_1_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
somador4bits S4B2(s0, s1, s2, s3, s4, s5, b0, b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ------------------------
// -- Decremento de 1 em a
// ------------------------
module decremento_de_1_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
subtrator4bits Su4B1(s0, s1, s2, s3, s4, a0, a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// ------------------------
// -- Decremento de 1 em b
// ------------------------
module decremento_de_1_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
subtrator4bits Su4B2(s0, s1, s2, s3, s4, b0, b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
endmodule
| 7.103827 |
module
// -------------------------
// -- Complemento de 2 em a
// -------------------------
module complemento_de_2_em_a(s0, s1, s2, s3, s4, a0, a1, a2, a3);
output s0, s1, s2, s3, s4;
input a0 ,a1, a2, a3;
complementode1 C1_2(s00, s01, s02, s03, s10, s11, s12, s13, a0 ,a1, a2, a3, 1'b1, 0'b0, 0'b0, 0'b0);
somador... | 7.103827 |
module
// ------------------------
// --Complemento de 2 em b
// ------------------------
module complemento_de_2_em_b(s0, s1, s2, s3, s4, b0, b1, b2, b3);
output s0, s1, s2, s3, s4;
input b0 ,b1, b2, b3;
complementode1 C1_2(s00, s01, s02, s03, s10, s11, s12, s13, b0 ,b1, b2, b3, 1'b1, 0'b0, 0'b0, 0'b0);
somador4bi... | 7.103827 |
module
// ----------------------
// -- Produto com 2 bits
// ----------------------
module produto_com_2_bits(s0, s1, s2, s3, a0, a1, b0, b1);
output s0, s1, s2, s3;
input a0, a1, b0, b1;
wire s4, s5, s6, s7, s8;
and AND1 (s4, a1, b1);
and AND2 (s5, a0, b0);
and AND3 (s6, a1, b0);
and AND4 (s7, a0, b1);
and AND5 (... | 7.103827 |
module ALU3 (
LEDR,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
KEY
);
input [9:0] SW;
input [2:0] KEY;
output [7:0] LEDR;
output [9:0] HEX0;
output [9:0] HEX1;
output [9:0] HEX2;
output [9:0] HEX3;
output [9:0] HEX4;
output [9:0] HEX5;
wire [7:0] ALUout;
wire [7:0... | 6.981781 |
module mux7to1 (
SW,
KEY,
ALUout,
AaddOne,
AaddB,
AverilogB,
AXORB,
HighorLow,
LeftShift,
RightShift,
Multiplication
);
input [7:0] SW;
input [2:0] KEY;
output reg [7:0] ALUout;
input [7:0] AaddOne;
input [7:0] AaddB;
input [7:0] AverilogB;
input [7:0] AXORB;
... | 9.111626 |
module verilogCircuit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [7:0] S;
output cout;
wire c1;
wire c2;
wire c3;
verilogAdder v0 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(c1)
);
verilogAdder v1 (
.A(A[1... | 6.973848 |
module verilogAdder (
A,
B,
cin,
S,
cout
);
input A, B, cin;
output S, cout;
assign {cout, S} = A + B + cin;
endmodule
| 7.201902 |
module adderCircuit (
A,
B,
cin,
S,
cout
);
input [3:0] A;
input [3:0] B;
input cin;
output [7:0] S;
output cout;
wire c1;
wire c2;
wire c3;
fullAdder a0 (
.A(A[0]),
.B(B[0]),
.cin(cin),
.S(S[0]),
.cout(c1)
);
fullAdder a1 (
.A(A[1]),
... | 6.586857 |
module alu32 (
a,
b,
ALUControl,
result
);
input wire [31:0] a, b;
input wire [3:0] ALUControl;
output reg [31:0] result;
wire signed [31:0] a_signed, b_signed;
assign a_signed = a;
assign b_signed = b;
always @(*) begin
case (ALUControl)
4'b0000: result <= a + b;
4'b000... | 8.104213 |
module.
////////////////////////////////////////////////////////////////////////////////
module ALU32Bit_tb();
reg [3:0] ALUControl; // control bits for ALU operation
reg [31:0] A, B; // inputs
wire [31:0] ALUResult; // answer
wire Zero; // Zero=1 if ALUResult == 0... | 6.641851 |
module Alu32b_extended (
aluOp,
leftOperand,
rightOperand, // or shamt
aluResult
);
input wire [3:0] aluOp;
input wire [31:0] leftOperand;
input wire [31:0] rightOperand;
output reg [31:0] aluResult;
wire [31:0] aluSimpleResult;
wire [31:0] shiftRightLogically;
assign shiftRightLogical... | 6.86071 |
module ALU4 (
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//=======================================================
s_ALU4 ALU1 (
SW[9],
SW[3:0],
... | 6.658307 |
module ALU4B (
input logic [3:0] in1,
in2,
opCode,
output logic [3:0] out,
output negative,
zero
);
logic [3:0] in1Selector, in2Selector, outSelector;
assign in1Selector = opCode[3] ? ~in1 : in1;
assign in2Selector = opCode[2] ? ~in2 : in2;
assign outSelector = (opCode[1]) ? ~(in1Selec... | 7.024057 |
module ALU_4bits (
input wire [3:0] a_i,
input wire [3:0] b_i,
input wire c_i,
input wire [1:0] op,
output wire [3:0] r_o,
output wire c_o
);
wire ALU_c[3:0];
wire ALU_r[3:0];
ALU_1bits ALU1 (
a_i[0],
b_i[0],
c_i,
op,
ALU_r[0],
ALU_c[0]
);
ALU_1bit... | 8.318136 |
module ALU (
input CLK100MHZ,
input [3:0] Num1,
Num2,
input [1:0] Op,
output [3:0] LED1,
LED2,
output [1:0] LED_Op,
output reg [7:0] AN,
output reg [6:0] display
);
reg [ 7:0] result;
reg [ 3:0] digito;
reg [18:0] refresh;
wire [ 2:0] active_display;
assign LED1 = Num... | 7.960621 |
module ALUunit (
alufun,
a,
b,
carryin,
result,
carryout
);
input a, b, alufun, carryin;
output reg result, carryout;
always @(*) begin
if(alufun == 1)//减法
begin
if (a == 1 && b == 0) begin
result = carryin;
carryout = 1;
end else if (a == 0 && b == 1) ... | 6.726604 |
module CMP (
sign,
zero,
overflow,
negative,
alufun,
result
);
input zero, overflow, negative, sign;
input [2:0] alufun;
output reg [31:0] result;
wire n_negative;
parameter EQ = 3'b001;
parameter NEQ = 3'b000;
parameter LT = 3'b010;
parameter LEZ = 3'b110;
parameter LTZ = 3'b... | 8.344089 |
module Shift (
A,
B,
alufun,
result
);
input [31:0] A, B;
input [1:0] alufun;
output reg [31:0] result;
parameter SLL = 2'b00;
parameter SRL = 2'b01;
parameter SRA = 2'b11;
always @(*) begin
if (A[4] == 1) begin
case (alufun)
SLL: result = B << 16;
SRL: result... | 6.947224 |
module ALU4_2 (
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR
);
//=======================================================
// REG/WIRE declarations
//=============================================... | 7.712894 |
module ALU4_LA (
a,
b,
c_in,
c_out,
less,
sel,
out,
P,
G
);
input less;
input [3:0] a, b;
input [2:0] sel;
input c_in;
output [3:0] out;
output P, G;
output c_out;
wire [2:0] c;
wire [3:0] p, g;
alu_slice_LA a1 (
a[0],
b[0],
c_in,
less,... | 6.96335 |
module alu64 (
input [63:0] A,
input [63:0] B,
input [ 5:0] shamt,
// input [5:0] high, // used to set upper bound of string
// input [5:0] low, // used to set lower bound of string
input [ 3:0] aluctrl,
input CLK,
output reg [63:0] Z
... | 6.82162 |
module for ALU64bit
module ALU64bit(key,left,right,select);
output reg [63:0] key;
input [63:0] left, right;
input select;
always @(left,right,select)
begin
if(select) // Key 1 : add
key = left + right;
else // Key 2 : subtract... | 7.736513 |
module cla74182 (
input wire [3:0] g,
input wire [3:0] p,
input wire cin,
output wire pout,
output wire gout,
output wire coutx,
output wire couty,
output wire coutz
);
assign coutx = p[0] & (cin | g[0]);
assign couty = p[1] & (p[0] | g[1]) & (cin | g[0] | g[1]);
assign coutz = p[... | 7.244733 |
module alu8b (
output [7:0] bus,
output reg carry,
output reg zero,
input [7:0] a,
input [7:0] b,
input sub,
input out,
input clr,
input clk,
input fi
);
wire [7:0] int_reg;
wire int_carry, int_zero;
assign {int_carry, int_reg} = a + (b ^ {8{sub}}) + sub;
assign int_zero ... | 7.372182 |
module ALU8bit (
input [3:0] Opcode,
input [7:0] Operand1,
input [7:0] Operand2,
output reg [15:0] Result,
output reg flagC,
output reg flagZ
);
parameter [3:0] ADD = 4'b0000;
parameter [3:0] SUB = 4'b0001;
parameter [3:0] MUL = 4'b0010;
parameter [3:0] DIV = 4'b0011;
parameter [3:0] A... | 7.016761 |
module to test how to port VHDL code to verilog
// in a little smaller units.
// This module is purely combinatorial logic.
module alu9900(
input [16:0] arg1, // 17-bit input to support DIV steps
input [15:0] arg2,
input [3:0] ope,
input compare, // for compare, set this to 1 and ope to sub.
output [15:0] alu_r... | 7.771489 |
module ALUAdd (
input [31:0] a,
input [31:0] b,
output reg [31:0] result
);
always @(*) begin
result <= a + b;
end
endmodule
| 7.227614 |
module aluAdder (
result,
pcFour,
relaAddress
);
input [31:0] pcFour, relaAddress;
output [31:0] result;
assign result = pcFour + relaAddress;
// for branch, if branch, new pc = result.
endmodule
| 7.10724 |
module contains 1 control signal, ALUALtSrc, if it is deasserted, it will
* take data from register file as the operand; if it is asserted, it will
* take data from immediate number as the operand.
*/
module alualtsrcmux( input wire [31:0] regsrc,
input wire [31:0] immsrc,
input wir... | 6.799318 |
module ALU (
in1,
in2,
shamt,
aluop,
out,
zeroflag
);
input signed [31:0] in1, in2; //edited to signed
reg unsigned [31:0] in1u, in2u;
input [3:0] aluop;
input [4:0] shamt;
output reg [31:0] out;
output reg zeroflag;
always @(in1, in2, aluop) begin
if (in1 == in2) zeroflag =... | 7.37871 |
module ALUAMuxTest ();
reg [31:0] PC, A, MDR;
reg [ 1:0] ALUSrcA;
wire [31:0] out;
ALUAMux dut (
.ALUSrcA(ALUSrcA),
.PC(PC),
.A(A),
.MDR(MDR),
.Data_out(out)
);
initial begin
$dumpfile("memAddrMuxTest.vcd");
$dumpvars;
end
initial begin
ALUSrcA = 0;
PC ... | 7.213011 |
module ALUB (
input [7:0] A,
B, // ALU 8-bit Inputs
input [3:0] ALU_Sel, // ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0, A}... | 8.227322 |
module ALUbasic (
output [7:0] Out, // Output 8 bit
output [3:0] flagArray, // not holding only driving EDI
input Cin, // Carry input bit
input [7:0] A_IN_0,
input [7:0] B_IN_0, // 8-bit data input
input [7:0] OR2,
input [3:0] S_AF, // Most significant 4 b... | 7.565516 |
module alu (
RESULT,
DATA1,
DATA2,
SELECT
);
output reg [7:0] RESULT;
input [7:0] DATA1, DATA2;
input [2:0] SELECT;
always @(*) begin
case (SELECT)
3'b000: begin
RESULT = DATA1; //FORWARD
end
3'b001: begin
RESULT = DATA1 + DATA2; //ADD
end
3'b... | 6.796395 |
module alub_mux (
input wire alub_sel,
input wire [31:0] rdata2,
input wire [31:0] imm,
output wire [31:0] alub
);
assign alub = (alub_sel == 1) ? rdata2 : imm;
endmodule
| 6.888262 |
module ALUcard_top (
input [2:0] opcode,
input [3:0] data,
input GO,
input clk,
input reset,
output [3:0] result,
output cout,
output borrow,
output led_idle,
output led_wait,
output led_rdy,
output led_done
);
wire [3:0] A_w;
wire [3:0] ... | 7.246696 |
module ALU_State (
input clk,
input GO,
input reset,
output reg led_idle,
output reg led_wait,
output reg led_rdy,
output reg led_done
);
reg [3:0] state;
initial begin
led_idle = 0;
led_wait = 0;
led_rdy = 0;
led_done = 0;
state = 0;
end
parameter ... | 7.374085 |
module Shift_in (
input [3:0] data,
input load,
output reg [3:0] A,
output reg [3:0] B
);
initial begin
A = 0;
B = 0;
end
always @(posedge load) begin
A = data;
end
always @(negedge load) begin
B = data;
end
endmodule
| 7.292331 |
module ALU (
input [2:0] opcode,
input [3:0] A,
input [3:0] B,
output reg [3:0] result,
output reg cout,
output reg borrow
);
initial begin
result = 0;
cout = 0;
borrow = 0;
end
parameter ADD = 0;
parameter SUBTRACT = 1;
parameter NOTa = 2;
parameter NOTb = 3;
paramet... | 7.960621 |
module alucell (
ai,
gi,
bi,
pih,
piv,
pi,
ti,
ao,
go,
poh,
pov,
po
);
input [8:1] ai, gi, bi;
input [1:8] ti;
input pi;
input [1:7] pih, piv;
output [8:1] ao, go;
output po;
output [1:7] poh, pov;
wire [1:7] po1, po2, po3, po4, po5, po6, po7;
firs... | 6.686049 |
module ALUControl (
input [1:0] ALUOp,
input [5:0] Function,
output reg [2:0] ALU_Control
);
wire [7:0] ALUControlIn;
assign ALUControlIn = {ALUOp, Function};
always @(ALUControlIn) begin
casex (ALUControlIn)
8'b01xxxxxx: ALU_Control <= 3'b010; //lw, sw
8'b10xxxxxx: ALU_Control <= 3'b... | 8.639118 |
module JR_Control (
input [1:0] alu_op,
input [5:0] funct,
output pcsrc3
);
assign pcsrc3 = ({alu_op, funct} == 8'b00000001) ? 1'b0 : 1'b1;
endmodule
| 6.633219 |
module ALU (
input [15:0] A,
input [15:0] B,
input Cin,
input [3:0] OP,
output [15:0] C,
output Cout
);
wire [15:0] Arithmetic;
wire Overflow;
// activate Cout on arithmetic opertion +/-
// implemented using the fact that OP_add is 0000 and OP_sub is 0001
assign {Overflow,Arithmetic}... | 7.960621 |
module alucont (
aluop1,
aluop0,
f5,
f4,
f3,
f2,
f1,
f0,
gout,
brnout
); //Figure 4.12
input aluop1, aluop0, f5, f4, f3, f2, f1, f0;
output [2:0] gout;
output brnout;
reg [2:0] gout;
reg brnout;
always @(aluop1 or aluop0 or f5 or f4 or f3 or f2 or f1 or f0) begin
... | 6.74583 |
module ALUControl (
input clock,
input reset,
input io_aluop,
input io_itype,
input [6:0] io_funct7,
input [2:0] io_funct3,
output [3:0] io_operation
);
wire [2:0] _GEN_0 = io_itype | io_funct7 == 7'h0 ? 3'h7 : 3'h4; // @[]
wire [1:0] _GEN_1 = io_funct7 == ... | 8.639118 |
module ALUControl (
OpCode,
Funct,
ALUCtrl,
Sign
);
input [5:0] OpCode;
input [5:0] Funct;
output reg [4:0] ALUCtrl;
output Sign;
// Your code below
parameter aluADD = 5'b00000;
parameter aluOR = 5'b00001;
parameter aluAND = 5'b00010;
parameter aluSUB = 5'b00110;
parameter aluSLT =... | 8.639118 |
module ALUControl_MyTest_v;
task passTest;
input [5:0] actualOut, expectedOut;
input [`STRLEN*8:0] testType;
inout [7:0] passed;
if (actualOut == expectedOut) begin
$display("%s passed", testType);
passed = passed + 1;
end else $display("%s failed: %d should be %d", testType, actualO... | 7.301268 |
module: ALU_Control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControlTest;
// Inputs
reg [1:0] ALUOp;
reg [5:0] function_field;
// Outputs
wire [3:0] ALUCtrl;
// In... | 7.194599 |
module: ALUControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControlUnit_TEST;
// Inputs
reg [2:0] ALUOp;
reg [5:0] funct;
// Outputs
wire [3:0] ALUCnt;
// Inst... | 8.370485 |
module ALUControl_Block (
ALUControl,
ALUOp,
Function
);
output [1:0] ALUControl;
reg [1:0] ALUControl;
input [1:0] ALUOp;
input [5:0] Function;
wire [7:0] ALUControlIn;
assign ALUControlIn = {ALUOp, Function};
always @(ALUControlIn)
casex (ALUControlIn)
8'b11xxxxxx: ALUControl = 2'b... | 7.200402 |
module ALUControl_tb;
// Inputs
reg [5:0] funct;
reg [2:0] ALUOp;
// Outputs
wire [3:0] ALUCnt;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.funct (funct),
.ALUOp (ALUOp),
.ALUCnt(ALUCnt)
);
initial begin
// Initialize Inputs
funct = 0;
ALUOp = 0;
... | 6.689514 |
module ALUControl_tb2;
// Inputs
reg [5:0] funct;
reg [2:0] ALUOp;
// Outputs
wire [3:0] ALUCnt;
// Instantiate the Unit Under Test (UUT)
ALUControl uut (
.funct (funct),
.ALUOp (ALUOp),
.ALUCnt(ALUCnt)
);
initial begin
// Initialize Inputs
funct = 0;
ALUOp = 0;
... | 6.689514 |
module alucontrol_stimulus;
reg [1:0] aluop;
reg [5:0] fun;
wire [3:0] aluctrl;
reg [1:0] aluop_in[0:7];
reg [5:0] fun_in[0:7];
reg [3:0] aluctrl_in[0:7];
reg [3:0] aluctrl_cmp;
alucontrol_v2 myAlucontrol (
.aluop(aluop),
.fun(fun),
.aluctrl(aluctrl)
);
integer i;
initial b... | 7.947841 |
module: ALUControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ALUControl_tf;
// Inputs
reg [1:0] ALUOp;
reg [5:0] FuncCode;
// Outputs
wire [3:0] ALUCtl;
// Instantiate... | 7.099352 |
module alucontrol_v2 (
aluOp0,
aluOp1,
fun,
aluctrl
);
input wire aluOp0, aluOp1;
input wire [5:0] fun;
output reg [3:0] aluctrl;
//Evaluate when any input changes.
always @(aluOp0 or aluOp1 or fun) begin
casex ({
aluOp1, aluOp0, fun
}) //For casex a ? represents a don't care... | 7.287868 |
module alucont (
aluop1,
aluop0,
f5,
f4,
f3,
f2,
f1,
f0,
gout
); //Figure 4.12
input aluop1, aluop0, f5, f4, f3, f2, f1, f0;
output [2:0] gout;
reg [2:0] gout;
always @(aluop1 or aluop0 or f5 or f4 or f3 or f2 or f1 or f0) begin
if (~(aluop1 | aluop0)) gout = 3'b010; /... | 6.74583 |
module ALUCt (
input rst,
input [5:0] funct,
input [1:0] alu_ct_op,
output reg [3:0] alu_ct
);
always @(*) begin
if (!rst) alu_ct = 0;
else
case (alu_ct_op)
2'b00: alu_ct = 4'b0010; //加法
2'b01: alu_ct = 4'b0110; //减法
2'b11: alu_ct = 4'b0000; //作比较<
... | 6.617956 |
module ALUctrl (
Clk,
op,
func,
ALUctr
);
input Clk;
input [5:0] op;
input [5:0] func;
output reg [3:0] ALUctr;
parameter R = 6'b000000;
always @(posedge Clk) begin
case (op)
R: begin
//P168
ALUctr[3]=(!func[4]&!func[3]&func[2]&func[1])+(!func[5]&!func[4]&!func[... | 6.533673 |
module aluctrl_testbench;
reg [3:0] func;
reg [1:0] op;
wire [3:0] ctrl_out;
ALUCtrl uut (
.func(func),
.alu_op(op),
.alu_ctrl(ctrl_out)
);
task check_alu_ctrl;
input [3:0] test_num;
input [3:0] expected_ctrl;
input [3:0] got_ctrl;
begin
if (expected_ctrl !== got... | 6.666479 |
module aluCU (
oper,
aluOp,
funcfield
);
input [1:0] aluOp;
input [3:0] funcfield;
output [2:0] oper;
assign oper[0] = (funcfield[0] | funcfield[3]) & aluOp[1];
assign oper[1] = ((~aluOp[1]) | (~funcfield[2]));
assign oper[2] = (aluOp[0] | (aluOp[1] & funcfield[1]));
endmodule
| 7.119252 |
module ALUDecoder (
ALUControl,
ALUOpcode,
funct3,
funct7,
opcode5
);
`include "Parameters.vh"
input [1 : 0] ALUOpcode;
input [2 : 0] funct3;
// The ALU decoder use funct7 and opcode[5] to determine ALU control
input funct7;
input opcode5;
output reg [2 : 0] ALUControl;
reg [1 : 0] ... | 6.68279 |
module aluDemo (
LEDR,
HEX5,
HEX3,
HEX2,
HEX1,
HEX0,
SW,
KEY,
CLOCK_50
);
//DE1-SoC wire interface for driving hardware
output [9:0] LEDR;
output [6:0] HEX5, HEX3, HEX2, HEX1, HEX0;
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
wire clk; // choosing from 32 differe... | 9.663607 |
module clock_divider (
clk_out,
clk_in,
slowDown
);
output clk_out;
reg [31:0] divided_clocks;
input clk_in, slowDown;
//Choose clock frequency for signal tap display or LED display
assign clk_out = slowDown ? divided_clocks[23] : clk_in;
initial divided_clocks = 0;
always @(posedge clk_in)... | 6.818038 |
module ALU (
in1,
in2,
c,
aluout
);
input [2:0] in1, in2;
input [1:0] c;
output reg [2:0] aluout;
always @(in1, in2, c) begin
if (c == 2'b11) //Add
aluout = in1 + in2;
else if (c == 2'b10) //Subtract
aluout = in1 - in2;
else if (c == 2'b01) //And
aluout = in1 & i... | 7.37871 |
module aluFile_testbench ();
reg [63:0] a, b;
reg Cin;
reg [4:0] sel;
wire [63:0] out;
wire cOut;
wire [3:0] status;
aluFile dut (
a,
b,
Cin,
sel,
out,
cOut,
status
);
initial begin
$monitor("sel=%d a=%d b=%d out=%d Cin=%d cOut=%d status=%d", sel, a, b... | 6.802639 |
module aluforwardingmux (
aluforward,
regdata,
aluresult,
dmresult,
out
);
parameter DWIDTH = 32;
input wire [1:0] aluforward;
input wire [DWIDTH-1:0] regdata;
input wire [DWIDTH-1:0] aluresult;
input wire [DWIDTH-1:0] dmresult;
output reg [DWIDTH-1:0] out;
always @(aluforward, regda... | 8.576114 |
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