corpus_id stringlengths 7 12 | paper_id stringlengths 9 16 | title stringlengths 1 261 | abstract stringlengths 70 4.02k | source stringclasses 1
value | bibtex stringlengths 208 20.9k | citation_key stringlengths 6 100 |
|---|---|---|---|---|---|---|
arxiv-1501 | 0710.4656 | A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck | <|reference_start|>A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck: The memory subsystem has always been a bottleneck in performance as well as significant power contributor in memory intensive applications. Many researchers have presented multi-layer... | arxiv | @article{dasygenis2007a,
title={A Memory Hierarchical Layer Assigning and Prefetching Technique to
Overcome the Memory Performance/Energy Bottleneck},
author={Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor,
Dimitrios Soudris, Antonios Thanailakis},
journal={Dans Design, Automation and ... | dasygenis2007a |
arxiv-1502 | 0710.4657 | New Schemes for Self-Testing RAM | <|reference_start|>New Schemes for Self-Testing RAM: This paper gives an overview of a new technique, named pseudo-ring testing (PRT). PRT can be applied for testing wide type of random access memories (RAM): bit- or word-oriented and single- or dual-port RAM's. An essential particularity of the proposed methodology is... | arxiv | @article{bodean2007new,
title={New Schemes for Self-Testing RAM},
author={Gh. Bodean, D. Bodean, A. Labunetz},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4657},
primaryClass={cs.AR}
} | bodean2007new |
arxiv-1503 | 0710.4658 | Compositional Memory Systems for Multimedia Communicating Tasks | <|reference_start|>Compositional Memory Systems for Multimedia Communicating Tasks: Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is ... | arxiv | @article{molnos2007compositional,
title={Compositional Memory Systems for Multimedia Communicating Tasks},
author={A. M. Molnos, M. J. M. Heijligers, S. D. Cotofana, J. T. J. Van
Eijndhoven},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
... | molnos2007compositional |
arxiv-1504 | 0710.4659 | Synchronization Processor Synthesis for Latency Insensitive Systems | <|reference_start|>Synchronization Processor Synthesis for Latency Insensitive Systems: In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulatio... | arxiv | @article{bomel2007synchronization,
title={Synchronization Processor Synthesis for Latency Insensitive Systems},
author={Pierre Bomel (LESTER), Eric Martin (LESTER), Emmanuel Boutillon
(LESTER)},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
... | bomel2007synchronization |
arxiv-1505 | 0710.4660 | Thermal-Aware Task Allocation and Scheduling for Embedded Systems | <|reference_start|>Thermal-Aware Task Allocation and Scheduling for Embedded Systems: Temperature affects not only the reliability but also the performance, power, and cost of the embedded system. This paper proposes a thermal-aware task allocation and scheduling algorithm for embedded systems. The algorithm is used as... | arxiv | @article{hung2007thermal-aware,
title={Thermal-Aware Task Allocation and Scheduling for Embedded Systems},
author={W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix=... | hung2007thermal-aware |
arxiv-1506 | 0710.4661 | Bright-Field AAPSM Conflict Detection and Correction | <|reference_start|>Bright-Field AAPSM Conflict Detection and Correction: As feature sizes shrink, it will be necessary to use AAPSM (Alternating-Aperture Phase Shift Masking) to image critical features, especially on the polysilicon layer. This imposes additional constraints on the layouts beyond traditional design rul... | arxiv | @article{chiang2007bright-field,
title={Bright-Field AAPSM Conflict Detection and Correction},
author={C. Chiang, A. Kahng, S. Sinha, X. Xu, A. Zelikovsky},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={07... | chiang2007bright-field |
arxiv-1507 | 0710.4663 | Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies | <|reference_start|>Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies: Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology reg... | arxiv | @article{datta2007statistical,
title={Statistical Modeling of Pipeline Delay and Design of Pipeline under
Process Variation to Enhance Yield in sub-100nm Technologies},
author={Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee,
Kaushik Roy},
journal={Dans Design, Automation and Test i... | datta2007statistical |
arxiv-1508 | 0710.4665 | New Perspectives and Opportunities From the Wild West of Microelectronic Biochips | <|reference_start|>New Perspectives and Opportunities From the Wild West of Microelectronic Biochips: Application of Microelectronic to bioanalysis is an emerging field which holds great promise. From the standpoint of electronic and system design, biochips imply a radical change of perspective, since new, completely d... | arxiv | @article{manaresi2007new,
title={New Perspectives and Opportunities From the Wild West of Microelectronic
Biochips},
author={Nicolo Manaresi, Gianni Medoro, Melanie Abonnenc, Vincent Auger, Paul
Vulto, Aldo Romani, Luigi Altomare, Marco Tartagni, Roberto Guerrieri},
journal={Dans Design, Automation and ... | manaresi2007new |
arxiv-1509 | 0710.4666 | Verification of Embedded Memory Systems using Efficient Memory Modeling | <|reference_start|>Verification of Embedded Memory Systems using Efficient Memory Modeling: We describe verification techniques for embedded memory systems using efficient memory modeling (EMM), without explicitly modeling each memory bit. We extend our previously proposed approach of EMM in Bounded Model Checking (BMC... | arxiv | @article{ganai2007verification,
title={Verification of Embedded Memory Systems using Efficient Memory Modeling},
author={Malay K. Ganai, Aarti Gupta, Pranav Ashar},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
ep... | ganai2007verification |
arxiv-1510 | 0710.4667 | Integration, Verification and Layout of a Complex Multimedia SOC | <|reference_start|>Integration, Verification and Layout of a Complex Multimedia SOC: We present our experience of designing a single-chip controller for advanced digital still camera from specification all the way to mass production. The process involves collaboration with camera system designer, IP vendors, EDA vendor... | arxiv | @article{chen2007integration,,
title={Integration, Verification and Layout of a Complex Multimedia SOC},
author={Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
epri... | chen2007integration, |
arxiv-1511 | 0710.4669 | SOC Testing Methodology and Practice | <|reference_start|>SOC Testing Methodology and Practice: On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. ... | arxiv | @article{wu2007soc,
title={SOC Testing Methodology and Practice},
author={Cheng-Wen Wu},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4669},
primaryClass={cs.AR}
} | wu2007soc |
arxiv-1512 | 0710.4670 | Evolutionary Optimization in Code-Based Test Compression | <|reference_start|>Evolutionary Optimization in Code-Based Test Compression: We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In contrast to existing code-based methods, we allow unspecified valu... | arxiv | @article{polian2007evolutionary,
title={Evolutionary Optimization in Code-Based Test Compression},
author={Ilia Polian, Alejandro Czutro, Bernd Becker},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4... | polian2007evolutionary |
arxiv-1513 | 0710.4671 | An Application-Specific Design Methodology for STbus Crossbar Generation | <|reference_start|>An Application-Specific Design Methodology for STbus Crossbar Generation: As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. Th... | arxiv | @article{murali2007an,
title={An Application-Specific Design Methodology for STbus Crossbar Generation},
author={Srinivasan Murali, Giovanni De Micheli},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.... | murali2007an |
arxiv-1514 | 0710.4672 | Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration | <|reference_start|>Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration: As microfluidics-based biochips become more complex, manufacturing yield will have significant influence on production volume and product cost. We propose an interstitial redundancy approach to... | arxiv | @article{su2007yield,
title={Yield Enhancement of Digital Microfluidics-Based Biochips Using Space
Redundancy and Local Reconfiguration},
author={Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},... | su2007yield |
arxiv-1515 | 0710.4673 | Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips | <|reference_start|>Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips: Microfluidics-based biochips are soon expected to revolutionize clinical diagnosis, DNA sequencing, and other laboratory procedures involving molecular biology. Most microfluidic biochips are based on the principle of cont... | arxiv | @article{su2007design,
title={Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic
Biochips},
author={Fei Su, Krishnendu Chakrabarty},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4... | su2007design |
arxiv-1516 | 0710.4678 | CMOS-Based Biosensor Arrays | <|reference_start|>CMOS-Based Biosensor Arrays: CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.<|reference_end... | arxiv | @article{thewes2007cmos-based,
title={CMOS-Based Biosensor Arrays},
author={R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow,
M. Augustyniak, M. Jenkner, B. Eversmann, P. Schindler-Bauer, M. Atzesberger,
B. Holzapfl, G. Beer, T. Haneder, H.-C. Hanke},
journal={Dans Design, Automation... | thewes2007cmos-based |
arxiv-1517 | 0710.4679 | DVS for On-Chip Bus Designs Based on Timing Error Correction | <|reference_start|>DVS for On-Chip Bus Designs Based on Timing Error Correction: On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more ... | arxiv | @article{kaul2007dvs,
title={DVS for On-Chip Bus Designs Based on Timing Error Correction},
author={Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor Mudge, Todd
Austin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={ar... | kaul2007dvs |
arxiv-1518 | 0710.4680 | Energy Bounds for Fault-Tolerant Nanoscale Designs | <|reference_start|>Energy Bounds for Fault-Tolerant Nanoscale Designs: The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical framework that is able to assess the trade-offs existing in nanoscale desi... | arxiv | @article{marculescu2007energy,
title={Energy Bounds for Fault-Tolerant Nanoscale Designs},
author={Diana Marculescu},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4680},
primaryClass={cs.CC cs.IT... | marculescu2007energy |
arxiv-1519 | 0710.4681 | A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips | <|reference_start|>A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips: As Moore's Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interc... | arxiv | @article{weber2007a,
title={A Quality-of-Service Mechanism for Interconnection Networks in
System-on-Chips},
author={Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix=... | weber2007a |
arxiv-1520 | 0710.4682 | Applying UML and MDA to Real Systems Design | <|reference_start|>Applying UML and MDA to Real Systems Design: Traditionally system design has been made from a black box/functionality only perspective which forces the developer to concentrate on how the functionality can be decomposed and recomposed into so called components. While this technique is well establishe... | arxiv | @article{oliver2007applying,
title={Applying UML and MDA to Real Systems Design},
author={Ian Oliver},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4682},
primaryClass={cs.SE}
} | oliver2007applying |
arxiv-1521 | 0710.4683 | The Challenges of Hardware Synthesis from C-Like Languages | <|reference_start|>The Challenges of Hardware Synthesis from C-Like Languages: MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: con... | arxiv | @article{edwards2007the,
title={The Challenges of Hardware Synthesis from C-Like Languages},
author={Stephen A. Edwards},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4683},
primaryClass={cs.PL}
... | edwards2007the |
arxiv-1522 | 0710.4684 | Reliability-Centric High-Level Synthesis | <|reference_start|>Reliability-Centric High-Level Synthesis: Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and c... | arxiv | @article{tosun2007reliability-centric,
title={Reliability-Centric High-Level Synthesis},
author={S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.... | tosun2007reliability-centric |
arxiv-1523 | 0710.4685 | Reliable System Specification for Self-Checking Data-Paths | <|reference_start|>Reliable System Specification for Self-Checking Data-Paths: The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments.... | arxiv | @article{bolchini2007reliable,
title={Reliable System Specification for Self-Checking Data-Paths},
author={C. Bolchini, F. Salice, D. Sciuto, L. Pomante},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710... | bolchini2007reliable |
arxiv-1524 | 0710.4686 | Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores | <|reference_start|>Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores: Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital c... | arxiv | @article{sehgal2007test,
title={Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores},
author={Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
epr... | sehgal2007test |
arxiv-1525 | 0710.4687 | On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips | <|reference_start|>On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips: Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index... | arxiv | @article{goel2007on-chip,
title={On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of
System Chips},
author={Sandeep Kumar Goel, Erik Jan Marinissen},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
... | goel2007on-chip |
arxiv-1526 | 0710.4688 | On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs | <|reference_start|>On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs: Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is ... | arxiv | @article{kastensmidt2007on,
title={On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based
FPGAs},
author={F. Lima Kastensmidt, L. Sterpone, L. Carro, M. Sonza Reorda},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archive... | kastensmidt2007on |
arxiv-1527 | 0710.4689 | Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code | <|reference_start|>Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code: Development of energy and performance-efficient embedded software is increasingly relying on application of complex transformations on the critical parts of the source code. Designers applyin... | arxiv | @article{shashidhar2007functional,
title={Functional Equivalence Checking for Verification of Algebraic
Transformations on Array-Intensive Source Code},
author={K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
... | shashidhar2007functional |
arxiv-1528 | 0710.4690 | RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power | <|reference_start|>RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power: This paper presents a novel repeater insertion algorithm for interconnect power minimization. The novelty of our approach is in the judicious integration of an analytical solver and a dynamic programming based method. Specifically, the... | arxiv | @article{liu2007rip:,
title={RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power},
author={Xun Liu, Yuantao Peng, Marios C. Papaefthymiou},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4... | liu2007rip: |
arxiv-1529 | 0710.4691 | An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types | <|reference_start|>An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types: Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has time complexity O(n^2), where n is the number of buffer positions. Lillis, Cheng and Lin ext... | arxiv | @article{li2007an,
title={An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer
Types},
author={Zhuo Li, Weiping Shi},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4691},
primary... | li2007an |
arxiv-1530 | 0710.4692 | Cantilever-Based Biosensors in CMOS Technology | <|reference_start|>Cantilever-Based Biosensors in CMOS Technology: Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical pro... | arxiv | @article{kirstein2007cantilever-based,
title={Cantilever-Based Biosensors in CMOS Technology},
author={K.-U. Kirstein, Y. Li, M. Zimmermann, C. Vancura, T. Volden, W. H.
Song, J. Lichtenberg, A. Hierlemannn},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
... | kirstein2007cantilever-based |
arxiv-1531 | 0710.4693 | Memory Testing Under Different Stress Conditions: An Industrial Evaluation | <|reference_start|>Memory Testing Under Different Stress Conditions: An Industrial Evaluation: This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulatio... | arxiv | @article{majhi2007memory,
title={Memory Testing Under Different Stress Conditions: An Industrial
Evaluation},
author={Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg,
Stefan Eichenberger, Fred Bowen},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne... | majhi2007memory |
arxiv-1532 | 0710.4694 | Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory | <|reference_start|>Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory: We propose an approach to optimally synthesize quantum circuits from non-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e. Controlled-V). Our approach reduces th... | arxiv | @article{yang2007exact,
title={Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum
Gates Using Multiple-Valued Logic and Group Theory},
author={Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek Perkowski},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne... | yang2007exact |
arxiv-1533 | 0710.4695 | SAT-Based Complete Don't-Care Computation for Network Optimization | <|reference_start|>SAT-Based Complete Don't-Care Computation for Network Optimization: This paper describes an improved approach to Boolean network optimization using internal don't-cares. The improvements concern the type of don't-cares computed, their scope, and the computation method. Instead of the traditionally us... | arxiv | @article{mishchenko2007sat-based,
title={SAT-Based Complete Don't-Care Computation for Network Optimization},
author={Alan Mishchenko, Robert K. Brayton},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710... | mishchenko2007sat-based |
arxiv-1534 | 0710.4697 | Statistical Timing Based Optimization using Gate Sizing | <|reference_start|>Statistical Timing Based Optimization using Gate Sizing: The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimization. In this paper, we propose a new sensitivity based, statist... | arxiv | @article{agarwal2007statistical,
title={Statistical Timing Based Optimization using Gate Sizing},
author={Aseem Agarwal, Kaviraj Chopra, David Blaauw},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.46... | agarwal2007statistical |
arxiv-1535 | 0710.4698 | Automated Synthesis of Assertion Monitors using Visual Specifications | <|reference_start|>Automated Synthesis of Assertion Monitors using Visual Specifications: Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked ... | arxiv | @article{gadkari2007automated,
title={Automated Synthesis of Assertion Monitors using Visual Specifications},
author={Ambar A. Gadkari, S. Ramesh},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4698},... | gadkari2007automated |
arxiv-1536 | 0710.4700 | A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms | <|reference_start|>A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms: In this paper, we present a software compilation approach for microprocessor/FPGA platforms that partitions a software binary onto custom hardware implemented in the FPGA. Our approach imposes less restrictions on so... | arxiv | @article{stitt2007a,
title={A Decompilation Approach to Partitioning Software for
Microprocessor/FPGA Platforms},
author={Greg Stitt, Frank Vahid},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4700... | stitt2007a |
arxiv-1537 | 0710.4701 | A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation | <|reference_start|>A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation: This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-s... | arxiv | @article{lee2007a,
title={A Prediction Packetizing Scheme for Reducing Channel Traffic in
Transaction-Level Hardware/Software Co-Emulation},
author={Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min
Kyung},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Alle... | lee2007a |
arxiv-1538 | 0710.4702 | A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures | <|reference_start|>A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures: The aggressive application of scalar replacement to array references substantially reduces the number of memory operations at the expense of a possibly very large number of registers. In t... | arxiv | @article{baradaran2007a,
title={A Register Allocation Algorithm in the Presence of Scalar Replacement
for Fine-Grain Configurable Architectures},
author={Nastaran Baradaran, Pedro C. Diniz},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
a... | baradaran2007a |
arxiv-1539 | 0710.4703 | A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors | <|reference_start|>A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors: This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of Most Recently Used (M... | arxiv | @article{ishihara2007a,
title={A Way Memoization Technique for Reducing Power Consumption of Caches in
Application Specific Integrated Processors},
author={Tohru Ishihara, Farzan Fallah},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
arch... | ishihara2007a |
arxiv-1540 | 0710.4704 | Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization | <|reference_start|>Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization: Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resources withou... | arxiv | @article{kim2007resource,
title={Resource Sharing and Pipelining in Coarse-Grained Reconfigurable
Architecture for Domain-Specific Optimization},
author={Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne ... | kim2007resource |
arxiv-1541 | 0710.4705 | A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning | <|reference_start|>A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning: Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs... | arxiv | @article{lysecky2007a,
title={A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores
using Dynamic Hardware/Software Partitioning},
author={Roman Lysecky, Frank Vahid},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archi... | lysecky2007a |
arxiv-1542 | 0710.4706 | An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs | <|reference_start|>An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs: This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify... | arxiv | @article{rodrigues2007an,
title={An Infrastructure to Functionally Test Designs Generated by Compilers
Targeting FPGAs},
author={Rui Rodrigues, Joao M. P. Cardoso},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
... | rodrigues2007an |
arxiv-1543 | 0710.4707 | Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach | <|reference_start|>Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach: In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an important problem, part... | arxiv | @article{ogras2007energy-,
title={Energy- and Performance-Driven NoC Communication Architecture Synthesis
Using a Decomposition Approach},
author={Umit Y. Ogras, Radu Marculescu},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefi... | ogras2007energy- |
arxiv-1544 | 0710.4709 | Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? | <|reference_start|>Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?: This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leaka... | arxiv | @article{gielen2007analog,
title={Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?},
author={Georges Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr,
Edmond Janssens, Karen Maex, Ted Vucurevich},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne ... | gielen2007analog |
arxiv-1545 | 0710.4710 | HEBS: Histogram Equalization for Backlight Scaling | <|reference_start|>HEBS: Histogram Equalization for Backlight Scaling: In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformatio... | arxiv | @article{iranli2007hebs:,
title={HEBS: Histogram Equalization for Backlight Scaling},
author={Ali Iranli, Hanif Fatemi, Massoud Pedram},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4710},
primar... | iranli2007hebs: |
arxiv-1546 | 0710.4711 | FPGA Architecture for Multi-Style Asynchronous Logic | <|reference_start|>FPGA Architecture for Multi-Style Asynchronous Logic: This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative as... | arxiv | @article{huot2007fpga,
title={FPGA Architecture for Multi-Style Asynchronous Logic},
author={N. Huot (TIMA), H. Dubreuil (TIMA), L. Fesquet (TIMA), M. Renaudin
(TIMA)},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
... | huot2007fpga |
arxiv-1547 | 0710.4712 | An Accurate SER Estimation Method Based on Propagation Probability | <|reference_start|>An Accurate SER Estimation Method Based on Propagation Probability: In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Experiments results and comparison of the results with the ... | arxiv | @article{asadi2007an,
title={An Accurate SER Estimation Method Based on Propagation Probability},
author={Ghazanfar Asadi, Mehdi B. Tahoori},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4712},
p... | asadi2007an |
arxiv-1548 | 0710.4713 | Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques | <|reference_start|>Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques: A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objec... | arxiv | @article{neiroukh2007improving,
title={Improving the Process-Variation Tolerance of Digital Circuits Using Gate
Sizing and Statistical Techniques},
author={Osama Neiroukh, Xiaoyu Song},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archiv... | neiroukh2007improving |
arxiv-1549 | 0710.4714 | Assertion-Based Design Exploration of DVS in Network Processor Architectures | <|reference_start|>Assertion-Based Design Exploration of DVS in Network Processor Architectures: With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use a... | arxiv | @article{yu2007assertion-based,
title={Assertion-Based Design Exploration of DVS in Network Processor
Architectures},
author={Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
a... | yu2007assertion-based |
arxiv-1550 | 0710.4715 | Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown | <|reference_start|>Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown: As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must ... | arxiv | @article{carter2007circuit-level,
title={Circuit-Level Modeling for Concurrent Testing of Operational Defects due
to Gate Oxide Breakdown},
author={Jonathan R. Carter, Sule Ozev, Daniel J. Sorin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},... | carter2007circuit-level |
arxiv-1551 | 0710.4716 | Optimized Generation of Data-Path from C Codes for FPGAs | <|reference_start|>Optimized Generation of Data-Path from C Codes for FPGAs: FPGAs, as computing devices, offer significant speedup over microprocessors. Furthermore, their configurability offers an advantage over traditional ASICs. However, they do not yet enjoy high-level language programmability, as microprocessors ... | arxiv | @article{guo2007optimized,
title={Optimized Generation of Data-Path from C Codes for FPGAs},
author={Zhi Guo, Betul Buyukkurt, Walid Najjar, Kees Vissers},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={071... | guo2007optimized |
arxiv-1552 | 0710.4717 | Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis | <|reference_start|>Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis: This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generated only once for a specific circu... | arxiv | @article{badaoui2007multi-placement,
title={Multi-Placement Structures for Fast and Optimized Placement in Analog
Circuit Synthesis},
author={Raoul F. Badaoui, Ranga Vemuri},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={ar... | badaoui2007multi-placement |
arxiv-1553 | 0710.4718 | Noise Figure Evaluation Using Low Cost BIST | <|reference_start|>Noise Figure Evaluation Using Low Cost BIST: A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of noise figure in several test points of the analog circuit. The method is also... | arxiv | @article{negreiros2007noise,
title={Noise Figure Evaluation Using Low Cost BIST},
author={Marcelo Negreiros, Luigi Carro, Altamiro A. Susin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4718},
p... | negreiros2007noise |
arxiv-1554 | 0710.4719 | Specification Test Compaction for Analog Circuits and MEMS | <|reference_start|>Specification Test Compaction for Analog Circuits and MEMS: Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing e-SVM based statistic... | arxiv | @article{biswas2007specification,
title={Specification Test Compaction for Analog Circuits and MEMS},
author={Sounil Biswas, Peng Li, R. D. (shawn) Blanton, Larry T. Pileggi},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arX... | biswas2007specification |
arxiv-1555 | 0710.4720 | Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits | <|reference_start|>Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits: Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. I... | arxiv | @article{dhillon2007soft-error,
title={Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits},
author={Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePre... | dhillon2007soft-error |
arxiv-1556 | 0710.4721 | IEEE 11494 Compatible ABMs for Basic RF Measurements | <|reference_start|>IEEE 11494 Compatible ABMs for Basic RF Measurements: An analogue testing standard IEEE 1149.4 is mainly targeted for low-frequency testing. The problem studied in this paper is extending the standard also for radio frequency testing. IEEE 1149.4 compatible measurement structures (ABMs) developed in ... | arxiv | @article{syri2007ieee,
title={IEEE 1149.4 Compatible ABMs for Basic RF Measurements},
author={Pekka Syri, Juha Hakkinen, Markku Moilanen},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4721},
prim... | syri2007ieee |
arxiv-1557 | 0710.4722 | Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters | <|reference_start|>Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters: This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize ... | arxiv | @article{chien2007designer-driven,
title={Designer-Driven Topology Optimization for Pipelined Analog to Digital
Converters},
author={Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar,
Tamal Mukherjee},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne ... | chien2007designer-driven |
arxiv-1558 | 0710.4723 | Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance | <|reference_start|>Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance: This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resist... | arxiv | @article{soens2007simulation,
title={Simulation Methodology for Analysis of Substrate Noise Impact on Analog
/ RF Circuits Including Interconnect Resistance},
author={C. Soens, G. Van Der Plas, P. Wambacq, S. Donnay},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (200... | soens2007simulation |
arxiv-1559 | 0710.4724 | Systematic Figure of Merit Computation for the Design of Pipeline ADC | <|reference_start|>Systematic Figure of Merit Computation for the Design of Pipeline ADC: The emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a gi... | arxiv | @article{barrandon2007systematic,
title={Systematic Figure of Merit Computation for the Design of Pipeline ADC},
author={L. Barrandon (IETR), S. Crand (IETR), D. Houzet (IETR)},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={a... | barrandon2007systematic |
arxiv-1560 | 0710.4725 | Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits | <|reference_start|>Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits: This issue discusses the fault-trajectory approach suitability for fault diagnosis on analog networks. Recent works have shown promising results concerning a method based on this concept for ATPG for diagnosing faults on analog network... | arxiv | @article{savioli2007fault-trajectory,
title={Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits},
author={Carlos Eduardo Savioli, Claudio C. Czendrodi, Jose Vicente Calvano,
Antonio Carneiro De Mesquita Filho},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemag... | savioli2007fault-trajectory |
arxiv-1561 | 0710.4727 | Top-Down Design of a Low-Power Multi-Channel 25-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit | <|reference_start|>Top-Down Design of a Low-Power Multi-Channel 25-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit: We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify ... | arxiv | @article{muller2007top-down,
title={Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated
Oscillator Clock-Recovery Circuit},
author={Paul Muller, Armin Tajalli, Mojtaba Atarodi, Yusuf Leblebici},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
... | muller2007top-down |
arxiv-1562 | 0710.4728 | Energy-Aware Routing for E-Textile Applications | <|reference_start|>Energy-Aware Routing for E-Textile Applications: As the scale of electronic devices shrinks, "electronic textiles" (e-textiles) will make possible a wide variety of novel applications which are currently unfeasible. Due to the wearability concerns, low-power techniques are critical for e-textile appl... | arxiv | @article{kao2007energy-aware,
title={Energy-Aware Routing for E-Textile Applications},
author={Jung-Chun Kao, Radu Marculescu},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4728},
primaryClass={c... | kao2007energy-aware |
arxiv-1563 | 0710.4729 | Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits | <|reference_start|>Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits: In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power i... | arxiv | @article{mukhopadhyay2007modeling,
title={Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled
Bulk-CMOS Logic Circuits},
author={Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
... | mukhopadhyay2007modeling |
arxiv-1564 | 0710.4731 | Leakage-Aware Interconnect for On-Chip Network | <|reference_start|>Leakage-Aware Interconnect for On-Chip Network: On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this pa... | arxiv | @article{tsai2007leakage-aware,
title={Leakage-Aware Interconnect for On-Chip Network},
author={Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
ep... | tsai2007leakage-aware |
arxiv-1565 | 0710.4732 | Energy Efficiency of the IEEE 802154 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives | <|reference_start|>Energy Efficiency of the IEEE 802154 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives: Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging in industrial applications. An important milestone in this tran... | arxiv | @article{bougard2007energy,
title={Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless
Microsensor Networks: Modeling and Improvement Perspectives},
author={Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan,
Wim Dehaene},
journal={Dans Design, Automation and Test in Euro... | bougard2007energy |
arxiv-1566 | 0710.4733 | Smart Temperature Sensor for Thermal Testing of Cell-Based ICs | <|reference_start|>Smart Temperature Sensor for Thermal Testing of Cell-Based ICs: In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of in... | arxiv | @article{bota2007smart,
title={Smart Temperature Sensor for Thermal Testing of Cell-Based ICs},
author={S. A. Bota, M. Rosales, J. L. Rossello, J. Segura},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={071... | bota2007smart |
arxiv-1567 | 0710.4734 | Computational Intelligence Characterization Method of Semiconductor Device | <|reference_start|>Computational Intelligence Characterization Method of Semiconductor Device: Characterization of semiconductor devices is used to gather as much data about the device as possible to determine weaknesses in design or trends in the manufacturing process. In this paper, we propose a novel multiple trip p... | arxiv | @article{liau2007computational,
title={Computational Intelligence Characterization Method of Semiconductor
Device},
author={Eric Liau, Doris Schmitt-Landsiedel},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
epr... | liau2007computational |
arxiv-1568 | 0710.4735 | Worst-Case and Average-Case Analysis of n-Detection Test Sets | <|reference_start|>Worst-Case and Average-Case Analysis of n-Detection Test Sets: Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform both a worst-case analysis and an average-case analysis to ... | arxiv | @article{pomeranz2007worst-case,
title={Worst-Case and Average-Case Analysis of n-Detection Test Sets},
author={Irith Pomeranz, Sudhakar M. Reddy},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4735},... | pomeranz2007worst-case |
arxiv-1569 | 0710.4736 | A New Embedded Measurement Structure for eDRAM Capacitor | <|reference_start|>A New Embedded Measurement Structure for eDRAM Capacitor: The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The integration of the DRAM capacitor process into a logic process is challenging to get satisfactory yields. The specific process of DRAM capacitor and the low capacitan... | arxiv | @article{lopez2007a,
title={A New Embedded Measurement Structure for eDRAM Capacitor},
author={L. Lopez (L2MP), J. M. Portal (L2MP), D. Nee (ST-Rousset)},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710... | lopez2007a |
arxiv-1570 | 0710.4737 | Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling | <|reference_start|>Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling: This paper presents new fast exact feasibility tests for uniprocessor real-time systems using preemptive EDF scheduling. Task sets which are accepted by previously described sufficient tests will be evaluated in nearly the same... | arxiv | @article{albers2007efficient,
title={Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling},
author={Karsten Albers, Frank Slomka},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.473... | albers2007efficient |
arxiv-1571 | 0710.4738 | Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique | <|reference_start|>Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique: Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such a... | arxiv | @article{marcon2007exploring,
title={Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique},
author={Cesar Marcon, Ney Calazans, Fernando Moraes, Altamiro Susin, Igor
Reis, Fabiano Hessel},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
ye... | marcon2007exploring |
arxiv-1572 | 0710.4739 | Q-DPM: An Efficient Model-Free Dynamic Power Management Technique | <|reference_start|>Q-DPM: An Efficient Model-Free Dynamic Power Management Technique: When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the technique on low end processor and tight-budget memory. ... | arxiv | @article{li2007q-dpm:,
title={Q-DPM: An Efficient Model-Free Dynamic Power Management Technique},
author={Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4... | li2007q-dpm: |
arxiv-1573 | 0710.4740 | A New Approach to Component Testing | <|reference_start|>A New Approach to Component Testing: Carefully tested electric/electronic components are a requirement for effective hardware-in-the-loop tests and vehicle tests in automotive industry. A new method for definition and execution of component tests is described. The most important advantage of this met... | arxiv | @article{brinkmeyer2007a,
title={A New Approach to Component Testing},
author={Horst Brinkmeyer},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4740},
primaryClass={cs.OH}
} | brinkmeyer2007a |
arxiv-1574 | 0710.4742 | Hardware Accelerated Power Estimation | <|reference_start|>Hardware Accelerated Power Estimation: In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation... | arxiv | @article{coburn2007hardware,
title={Hardware Accelerated Power Estimation},
author={Joel Coburn, Srivaths Ravi, Anand Raghunathan},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4742},
primaryClas... | coburn2007hardware |
arxiv-1575 | 0710.4743 | Efficient Solution of Language Equations Using Partitioned Representations | <|reference_start|>Efficient Solution of Language Equations Using Partitioned Representations: A class of discrete event synthesis problems can be reduced to solving language equations f . X ⊆ S, where F is the fixed component and S the specification. Sequential synthesis deals with FSMs when the automata for F an... | arxiv | @article{mishchenko2007efficient,
title={Efficient Solution of Language Equations Using Partitioned
Representations},
author={Alan Mishchenko, Robert Brayton, Roland Jiang, Tiziano Villa, Nina
Yevtushenko},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
... | mishchenko2007efficient |
arxiv-1576 | 0710.4745 | Embedded Automotive System Development Process | <|reference_start|>Embedded Automotive System Development Process: Model based design enables the automatic generation of final-build software from models for high-volume automotive embedded systems. This paper presents a framework of processes, methods and tools for the design of automotive embedded systems. A steer-b... | arxiv | @article{langenwalter2007embedded,
title={Embedded Automotive System Development Process},
author={Joachim Langenwalter},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4745},
primaryClass={cs.OH}
... | langenwalter2007embedded |
arxiv-1577 | 0710.4746 | RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC | <|reference_start|>RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC: This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLDL) like SystemC. We describe these constructs ... | arxiv | @article{hassan2007rtk-spec,
title={RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in
SystemC},
author={M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu
Imai},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007... | hassan2007rtk-spec |
arxiv-1578 | 0710.4747 | An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories | <|reference_start|>An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories: Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has heavy impact on the reliability of SOCs. Transparent test is one of useful te... | arxiv | @article{li2007an,
title={An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories},
author={Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.474... | li2007an |
arxiv-1579 | 0710.4748 | Systematic Transaction Level Modeling of Embedded Systems with SystemC | <|reference_start|>Systematic Transaction Level Modeling of Embedded Systems with SystemC: This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both application-specific HW and SW components of an em... | arxiv | @article{klingauf2007systematic,
title={Systematic Transaction Level Modeling of Embedded Systems with SystemC},
author={Wolfgang Klingauf},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4748},
pr... | klingauf2007systematic |
arxiv-1580 | 0710.4750 | On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories | <|reference_start|>On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories: Single Event Upsets (SEU) as well as permanent faults can significantly affect the correct on-line operation of digital systems, such as memories and microprocessors; a memory can be made ... | arxiv | @article{schiano2007on,
title={On the Analysis of Reed Solomon Coding for Resilience to
Transient/Permanent Faults in Highly Reliable Memories},
author={L. Schiano, M. Ottavi, F. Lombardi, S. Pontarelli, A. Salsano},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005... | schiano2007on |
arxiv-1581 | 0710.4751 | Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software | <|reference_start|>Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software: Safety-critical embedded systems having to meet real-time constraints are expected to be highly predictable in order to guarantee at design time that certain timing deadlines will always be met. This requirement... | arxiv | @article{wehmeyer2007influence,
title={Influence of Memory Hierarchies on Predictability for Time Constrained
Embedded Software},
author={Lars Wehmeyer, Peter Marwedel},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},... | wehmeyer2007influence |
arxiv-1582 | 0710.4752 | An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms | <|reference_start|>An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms: In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main processing element. An application is ... | arxiv | @article{khan2007an,
title={An Iterative Algorithm for Battery-Aware Task Scheduling on Portable
Computing Platforms},
author={Jawad Khan, Ranga Vemuri},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={071... | khan2007an |
arxiv-1583 | 0710.4753 | Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation | <|reference_start|>Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation: Static program analysis by abstract interpretation is an efficient method to determine properties of embedded software. One example is value analysis, which determines the values stored in th... | arxiv | @article{heckmann2007verifying,
title={Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded
Software by Abstract Interpretation},
author={Reinhold Heckmann, Christian Ferdinand},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007... | heckmann2007verifying |
arxiv-1584 | 0710.4754 | Design of a Virtual Component Neutral Network-on-Chip Transaction Layer | <|reference_start|>Design of a Virtual Component Neutral Network-on-Chip Transaction Layer: Research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus-based architectures but have not focused on compatibility communication standards. This paper describes a number of ... | arxiv | @article{martin2007design,
title={Design of a Virtual Component Neutral Network-on-Chip Transaction Layer},
author={Philippe Martin},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4754},
primaryCl... | martin2007design |
arxiv-1585 | 0710.4755 | Model Reuse through Hardware Design Patterns | <|reference_start|>Model Reuse through Hardware Design Patterns: Increasing reuse opportunities is a well-known problem for software designers as well as for hardware designers. Nonetheless, current software and hardware engineering practices have embraced different approaches to this problem. Software designs are usua... | arxiv | @article{rincon2007model,
title={Model Reuse through Hardware Design Patterns},
author={Fernando Rincon, Francisco Moya, Jesus Barba, Juan Carlos Lopez},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.... | rincon2007model |
arxiv-1586 | 0710.4756 | Design Method for Constant Power Consumption of Differential Logic Circuits | <|reference_start|>Design Method for Constant Power Consumption of Differential Logic Circuits: Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the encryption algorithm implemented within the sec... | arxiv | @article{tiri2007design,
title={Design Method for Constant Power Consumption of Differential Logic
Circuits},
author={Kris Tiri, Ingrid Verbauwhede},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.47... | tiri2007design |
arxiv-1587 | 0710.4757 | Techniques for Fast Transient Fault Grading Based on Autonomous Emulation | <|reference_start|>Techniques for Fast Transient Fault Grading Based on Autonomous Emulation: Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently r... | arxiv | @article{lopez-ongil2007techniques,
title={Techniques for Fast Transient Fault Grading Based on Autonomous
Emulation},
author={Celia Lopez-Ongil, Mario Garcia-Valderas, Marta Portela-Garcia, Luis
Entrena-Arrontes},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005... | lopez-ongil2007techniques |
arxiv-1588 | 0710.4758 | Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling | <|reference_start|>Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling: A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construct a fully-preemptive schedule that leads t... | arxiv | @article{leung2007exploiting,
title={Exploiting Dynamic Workload Variation in Low Energy Preemptive Task
Scheduling},
author={Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={ar... | leung2007exploiting |
arxiv-1589 | 0710.4759 | A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs | <|reference_start|>A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs: As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performa... | arxiv | @article{rossello2007a,
title={A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs},
author={J. L. Rossello, V. Canals, S. A. Bota, A. Keshavarzi, J. Segura},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
... | rossello2007a |
arxiv-1590 | 0710.4760 | Low Power Oriented CMOS Circuit Optimization Protocol | <|reference_start|>Low Power Oriented CMOS Circuit Optimization Protocol: Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed fo... | arxiv | @article{verle2007low,
title={Low Power Oriented CMOS Circuit Optimization Protocol},
author={A. Verle (LIRMM), X. Michel (LIRMM), N. Azemard (LIRMM), P. Maurine
(LIRMM), D. Auvergne (LIRMM)},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
... | verle2007low |
arxiv-1591 | 0710.4761 | Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL | <|reference_start|>Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL: This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves perf... | arxiv | @article{keezer2007low-cost,
title={Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL},
author={D. C. Keezer, C. Gray, A. Majid, N. Taher},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.... | keezer2007low-cost |
arxiv-1592 | 0710.4762 | Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction | <|reference_start|>Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction: This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We pro... | arxiv | @article{kitahara2007area-efficient,
title={Area-Efficient Selective Multi-Threshold CMOS Design Methodology for
Standby Leakage Power Reduction},
author={Takeshi Kitahara, Naoyuki Kawabe, Fimihiro Minami, Katsuhiro Seta,
Toshiyuki Furusawa},
journal={Dans Design, Automation and Test in Europe - DATE'05... | kitahara2007area-efficient |
arxiv-1593 | 0710.4763 | Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality | <|reference_start|>Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality: This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is descri... | arxiv | @article{beck2007logic,
title={Logic Design for On-Chip Test Clock Generation - Implementation Details
and Impact on Delay Test Quality},
author={Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang
Lin, Ron Press},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :... | beck2007logic |
arxiv-1594 | 0710.4764 | Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip | <|reference_start|>Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip: Many existing thermal management techniques focus on reducing the overall power consumption of the chip, and do not address location-specific temperature problems referred to as hotspots. We propose the use of dynamic runtime reco... | arxiv | @article{link2007hotspot,
title={Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip},
author={G. M. Link, N. Vijaykrishnan},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4764},
... | link2007hotspot |
arxiv-1595 | 0710.4780 | Querying XML Documents in Logic Programming | <|reference_start|>Querying XML Documents in Logic Programming: Extensible Markup Language (XML) is a simple, very flexible text format derived from SGML. Originally designed to meet the challenges of large-scale electronic publishing, XML is also playing an increasingly important role in the exchange of a wide variety... | arxiv | @article{almendros-jiménez2007querying,
title={Querying XML Documents in Logic Programming},
author={J. M. Almendros-Jim'enez and A. Becerra-Ter'on and F. J.
Enciso-Ba~nos},
journal={arXiv preprint arXiv:0710.4780},
year={2007},
archivePrefix={arXiv},
eprint={0710.4780},
primaryClass={cs.P... | almendros-jiménez2007querying |
arxiv-1596 | 0710.4793 | Unified Modeling of Complex Real-Time Control Systems | <|reference_start|>Unified Modeling of Complex Real-Time Control Systems: Complex real-time control system is a software dense and algorithms dense system, which needs modern software engineering techniques to design. UML is an object-oriented industrial standard modeling language, used more and more in real-time domai... | arxiv | @article{hai2007unified,
title={Unified Modeling of Complex Real-Time Control Systems},
author={He Hai, Zhong Yi-Fang, Cai Chi-Lan},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.4793},
primaryCla... | hai2007unified |
arxiv-1597 | 0710.4794 | Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage | <|reference_start|>Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage: In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and the... | arxiv | @article{bai2007power-performance,
title={Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches
Considering Total Leakage},
author={Robert Bai, Nam-Sung Kim, Tae Ho Kgil, Dennis Sylvester, Trevor Mudge},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005... | bai2007power-performance |
arxiv-1598 | 0710.4795 | Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture | <|reference_start|>Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture: The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing t... | arxiv | @article{amory2007test,
title={Test Time Reduction Reusing Multiple Processors in a Network-on-Chip
Based Architecture},
author={Alexandre M. Amory, Marcelo Lubaszewski, Fernando G. Moraes, Edson I.
Moreno},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
... | amory2007test |
arxiv-1599 | 0710.4796 | A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware | <|reference_start|>A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware: Due to the emergence of highly dynamic multimedia applications there is a need for flexible platforms and run-time scheduling support for embedded systems. Dynamic Recon... | arxiv | @article{resano2007a,
title={A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the
Reconfiguration Overhead of Dynamically Reconfigurable Hardware},
author={Javier Resano, Daniel Mozos, Francky Catthoor},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (200... | resano2007a |
arxiv-1600 | 0710.4797 | Rapid Generation of Thermal-Safe Test Schedules | <|reference_start|>Rapid Generation of Thermal-Safe Test Schedules: Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in thi... | arxiv | @article{rosinger2007rapid,
title={Rapid Generation of Thermal-Safe Test Schedules},
author={Paul Rosinger, Bashir Al-Hashimi, Krishnendu Chakrabarty},
journal={Dans Design, Automation and Test in Europe - DATE'05, Munich :
Allemagne (2005)},
year={2007},
archivePrefix={arXiv},
eprint={0710.47... | rosinger2007rapid |
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