| # How can I go from timing reports to Verilog? | |
| Tool: OpenSTA | |
| Subcategory: Tracing timing paths | |
| ## Conversation | |
| ### oharboe | |
| I have a timing path in the OpenROAD GUI that I want to understand. | |
| How can I go from the timing report in the GUI to the Verilog? | |
| ### maliberty | |
| https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 should help with naming once merged. | |
| There is no direct link today so you'll have to work back from the names. @QuantamHD has some work to store line numbers that is hopefully going to land but has been tied up in OSS licensing issues. | |
| ### oharboe | |
| @maliberty Here is an example of how it is hard to get from the static timing report to the Verilog: | |
| Build the design with ` make DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk`, then look at the Element `make DESIGN_CONFIG=designs/asap7/mock-array-big/Element/config.mk gui_final`. | |
| How, in general, do I find my way to the Verilog code? | |
|  | |
| ### maliberty | |
| If you use the rename PR I mentioned then the register should have a name matching the Element.v to some degree. Does that work here? | |
| ### oharboe | |
| What I've heard is that tracking from timing reports back to RTL is an "unsolved problem in EDA tools", so https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/pull/1129 is probably as good as it gets for now. | |
| To go beyond this, I suppose Yosys has to grow some sophistication w.r.t. tracking back to the original Verilog. | |
| One of the goals of https://circt.llvm.org/ is to provide an improved infrastructure for RTL as it goes through a number of tools in a flow. Perhaps, one day, yosys will support https://circt.llvm.org/. Ideally this would give Yosys more input languages and better "debug information" through synthesis and technology mapping... | |