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How do I find and view the nets that are causing hold and setup violations?

Tool: OpenSTA

Subcategory: Timing analysis

Conversation

oharboe

It want to find and view nets that cause hold violations.

Today I have to wait and hope for a global routing failure to be able to view the nets that cause hold violations in DRC viewer there.

Repair setup and hold violations...
TNS end percent 5
[INFO RSZ-0041] Resized 2 instances.
[WARNING RSZ-0062] Unable to repair all setup violations.
[INFO RSZ-0046] Found 2957 endpoints with hold violations.
[INFO RSZ-0032] Inserted 40106 hold buffers.
Placement Analysis

vvbandeira

find_timing_paths -path_delay min -slack_max 0

@oharboe, Would this work for you? Note that RSZ just said it had found 2957 hold violations; after inserting the 40106 buffers, there's no warning. So it is likely that all have been fixed -- see the warning in the line above for a contrast about setup violations.

For setup you would do:

find_timing_paths -path_delay max -slack_max 0

oharboe

Found an approach... Here is what I did:

  1. create some hold failures by reducing the clock period from 2000 to 1000ps in mock-array, using diff below.
  2. There are no timing violations in placement, the timing violations happen after CTS.
  3. Modify cts.tcl to write out an ODB file before hold cells are inserted and the design is repair. Post repair in CTS there are no violations.

Now I can run commands to examine minimum hold time violations, which will lead to hold cells being inserted.

report_checks -path_delay min
Startpoint: io_insRight_0[61] (input port clocked by clock)
Endpoint: ces_0_0 (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
   0.00    0.00   clock network delay (propagated)
 200.00  200.00 ^ input external delay
   0.00  200.00 ^ io_insRight_0[61] (in)
  10.45  210.45 ^ input1082/Y (BUFx2_ASAP7_75t_R)
   0.04  210.48 ^ ces_0_0/io_ins_right[61] (Element)
         210.48   data arrival time

   0.00    0.00   clock clock (rise edge)
 337.72  337.72   clock network delay (propagated)
   0.00  337.72   clock reconvergence pessimism
         337.72 ^ ces_0_0/clock (Element)
 102.40  440.11   library hold time
         440.11   data required time
---------------------------------------------------------
         440.11   data required time
        -210.48   data arrival time
---------------------------------------------------------
        -229.63   slack (VIOLATED)
foreach path [find_timing_paths -slack_max 0 -group_count 10 -path_delay min] {puts "[get_property $path slack] [get_property [get_property $path endpoint] full_name]"}
-229.630280 ces_0_0/io_ins_right[61]
-229.599152 ces_0_0/io_ins_right[3]
-229.596451 ces_0_0/io_ins_right[56]
-229.570663 ces_0_0/io_ins_right[51]
-229.570786 ces_0_0/io_ins_right[53]
-229.568649 ces_0_0/io_ins_right[1]
-229.561371 ces_0_0/io_ins_right[14]
-229.517380 ces_0_0/io_ins_right[30]
-229.512604 ces_0_0/io_ins_right[5]
-229.509186 ces_7_0/io_ins_right[61]
diff --git a/flow/designs/asap7/mock-array/Element/constraints.sdc b/flow/designs/asap7/mock-array/Element/constraints.sdc
index be545b8f..0a66e62e 100644
--- a/flow/designs/asap7/mock-array/Element/constraints.sdc
+++ b/flow/designs/asap7/mock-array/Element/constraints.sdc
@@ -4,7 +4,7 @@ set cols [expr {[info exists ::env(MOCK_ARRAY_COLS)] ? $::env(MOCK_ARRAY_COLS) :
 
 set clk_name clock
 set clk_port_name clock
-set clk_period 2000
+set clk_period 1000
 
 set clk_port [get_ports $clk_port_name]
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
diff --git a/flow/designs/asap7/mock-array/constraints.sdc b/flow/designs/asap7/mock-array/constraints.sdc
index 5d33c792..46b20e5b 100644
--- a/flow/designs/asap7/mock-array/constraints.sdc
+++ b/flow/designs/asap7/mock-array/constraints.sdc
@@ -1,6 +1,6 @@
 set sdc_version 2.0
 
-set clk_period 2000
+set clk_period 1000
 create_clock [get_ports clock] -period $clk_period -waveform [list 0 [expr $clk_period/2]]
 
 set clk_name  clock
diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
index 0b7c56b8..2c0c6fef 100644
--- a/flow/scripts/cts.tcl
+++ b/flow/scripts/cts.tcl
@@ -45,6 +45,8 @@ estimate_parasitics -placement
 report_metrics "cts pre-repair"
 utl::pop_metrics_stage
 
+write_db $::env(RESULTS_DIR)/4_1_cts_pre_repair.odb
+
 repair_clock_nets
 
 utl::push_metrics_stage "cts__{}__post_repair"

oharboe

make gui_cts ctrl-f and searching for instance *hold* is helpful. :-)

From there I can go to the buffer tree, then find the endpoints.

image

maliberty

Various useful patterns at https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/2734e98ee7c0f6888a686c2ef2445c0bb837ed0f/flow/scripts/save_images.tcl#L59