Why invertors in front of the flip-flops in a mock-array clock tree?
Tool: Clock Tree Synthesis
Subcategory: Design explanation
Conversation
oharboe
For mock-array, I ran make cts && make gui_cts and pasted the clock tree below.
I'm curious: why is there an inverter in front of every flip-flop and no invertor in front of the macros?
I checked by hovering over a number of the pink dots at the leaf of the clock tree that the flip-flops are the leaf points with an invertor in front.
The clock period is 1000ps and the skew is 50ps, by gleaning at the clockd tree.
oharboe
I have tried to find some documentation on the report_checks output format, but lacking that I'm making some guesses....
The below is a report from mock-array/Element, where I notice the clock clock' (fall edge), but mock-array is positive edge triggered, so why falling edge?
Could it be that my design is positive edge triggered, but that the flip-flop is in fact negative edge triggered?
That would explain the inverter in front of every flip-flop in the clock-tree above too...
I beleve the first path below is the data required path from macro input pin to the flip flop input pin and that the second path is the clock input pin on the macro to the flip flop input pin.
What does (propagated) mean?
I find data required time a bit confusing for the clock propagation path, but my guess that's just the chosen terminology and that the data required time for the clock is in fact the clock required time in my mind of thinking.
>>> report_checks -path_delay min -from io_ins_right[0]
Startpoint: io_ins_right[0] (input port clocked by clock)
Endpoint: _557_ (falling edge-triggered flip-flop clocked by clock')
Path Group: clock
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clock (rise edge)
0.00 0.00 clock network delay (propagated)
50.00 50.00 ^ input external delay
2.24 52.24 ^ io_ins_right[0] (in)
11.98 64.22 ^ hold1749/Y (BUFx2_ASAP7_75t_R)
11.38 75.59 ^ hold745/Y (BUFx2_ASAP7_75t_R)
11.43 87.02 ^ hold1750/Y (BUFx2_ASAP7_75t_R)
11.95 98.97 ^ input129/Y (BUFx2_ASAP7_75t_R)
12.69 111.66 ^ hold1751/Y (BUFx2_ASAP7_75t_R)
12.88 124.54 ^ hold746/Y (BUFx2_ASAP7_75t_R)
12.83 137.37 ^ hold1752/Y (BUFx2_ASAP7_75t_R)
0.18 137.55 ^ _557_/D (DFFLQNx2_ASAP7_75t_R)
137.55 data arrival time
0.00 0.00 clock clock' (fall edge)
99.73 99.73 clock network delay (propagated)
20.00 119.73 clock uncertainty
0.00 119.73 clock reconvergence pessimism
119.73 v _557_/CLK (DFFLQNx2_ASAP7_75t_R)
10.65 130.38 library hold time
130.38 data required time
---------------------------------------------------------
130.38 data required time
-137.55 data arrival time
---------------------------------------------------------
7.16 slack (MET)
maliberty
Is this at the top or in the element?
maliberty
propagated means you are post-cts and "set_propagated_clock [all_clocks]" has been used. The delay is calculated from the actual clock network. The opposite is ideal clocks from before CTS.
maliberty
If you look at DFFLQNx2_ASAP7_75t_R you'll see
ff (IQN,IQNN) {
clocked_on : "!CLK";
next_state : "!D";
power_down_function : "(!VDD) + (VSS)";
}
so it is on the negative edge. The ff choice is made during synthesis