Creating a mock 8192x64 SRAM for megaboom
Tool: Global Placement
Subcategory: Performance issue
Conversation
oharboe
I'm trying to create a mock SRAM for the L2 in https://github.com/The-OpenROAD-Project/megaboom
Here is the behavioral model:
module cc_banks_8192x64(
input [12:0] RW0_addr,
input RW0_en,
RW0_clk,
RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
reg [63:0] Memory[0:8191];
reg [12:0] _RW0_raddr_d0;
reg _RW0_ren_d0;
reg _RW0_rmode_d0;
always @(posedge RW0_clk) begin
_RW0_raddr_d0 <= RW0_addr;
_RW0_ren_d0 <= RW0_en;
_RW0_rmode_d0 <= RW0_wmode;
if (RW0_en & RW0_wmode)
Memory[RW0_addr] <= RW0_wdata;
end // always @(posedge)
assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx;
endmodule
8192 rows x 64 bits = 5*10^5 bits. This yields 2.7*10^6 instances. At CORE_UTILIZATION=40%, this yields the following floorplan 640um * 1400um.
The build times for this module become prohibitive. Synthesis is ca. 6000s, 30000s for global placement, and at least as long for CTS. So I really don't want to run through more than the floorplan and at that point create an abstract.
I have some work in progress where I can mock a smaller area: https://github.com/The-OpenROAD-Project/megaboom/pull/9
I don't have a way to mock a realistic clock period for the .lib file that comes out of the floorplan, nor do I know exactly what is realistic for such an SRAM on ASAP7.
90ps minimum clock period for a 8192x64 SRAM seems pretty good...
>>> report_clock_min_period
RW0_clk period min = 89.24 fmax 11206.30
I can't reconcile the min period of 90ps with what is observed in Timing Report:
I wonder if the .lib file that comes out of the floorplan can be useful in architectural exploration.
This raises a rather open ended question...
Q: How does the .lib file that comes out of the floorplan compare to a realistic .lib file?
Is it a "simple matter of scaling" the .lib file, like I can scale area to get something that is something that is in the range of what I want in my architectural exploration?
maliberty
I believe the min clock period is based on internal reg-to-reg paths and not reg-IO paths as shown above.
Using a memory generator is a better idea as this will only get worse the bigger you make the rams.
maliberty
Expecting to build to build 2.5M instance blocks quickly will be very difficult in any tool.
oharboe
Trying a different approach... Since all I care about is to mock area and timing(creating realistic SRAMs is a separate concern that I'm not tackling now), it doens't matter what the Verilog actually does. Below I have reduced the size of the Memory while I'm using all the address bits.
module cc_banks_8192x64(
input [12:0] RW0_addr,
input RW0_en,
RW0_clk,
RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
reg [63:0] Memory[0:127]; // Smaller memory array
reg [12:0] _RW0_raddr_d0;
reg _RW0_ren_d0;
reg _RW0_rmode_d0;
// XOR high and low bits of the address to use all bits
wire [6:0] effective_addr = RW0_addr[6:0] ^ RW0_addr[12:7];
always @(posedge RW0_clk) begin
_RW0_raddr_d0 <= effective_addr;
_RW0_ren_d0 <= RW0_en;
_RW0_rmode_d0 <= RW0_wmode;
if (RW0_en & RW0_wmode)
Memory[effective_addr] <= RW0_wdata;
end // always @(posedge)
assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx;
endmodule
After a few minutes, I have some area and timing for a mock SRAM that should allow me to see what else is going on in this design...
If I want more aggressive timing, I can adjust the Verilog to be even simpler. Area can be scaled up and down, using the mock_area feature.
After CTS:
oharboe
So with the above approach, I can easily mock large SRAMs and I also have a way to mock the area.
This allows me to set aside the SRAM concerns to investigate what else is going on in the design and learn something interesting.
Setting aside the SRAM concern, I can see a lot of logic and high fanout in the timing path for the FpPipeline in the megaboom design.
What timing closure does this have in commercial tools at a small node? It seems like a lot to ask that PDK and improved post synthesis stages are going to get this to GHz frequencies. Could it be a synthesis problem? Perhaps this version of MegaBoom is missing a pipeline stage or two here? Could there be some structure that has to be specialized in floating point units just like SRAM must be?
From make DESIGN_NAME=FpPipeline gui_place:
>>> report_checks -rise_from io_flush_pipeline -rise_through input504/A -rise_through input504/Y -rise_through wire12207/A -rise_through wire12207/Y -rise_through max_length12204/A -rise_through max_length12204/Y -rise_through fp_issue_unit/_46407_/B -fall_through fp_issue_unit/_46407_/Y -fall_through fp_issue_unit/_46408_/B -rise_through fp_issue_unit/_46408_/Y -rise_through max_length4078/A -rise_through max_length4078/Y -rise_through fp_issue_unit/_46439_/C -rise_through fp_issue_unit/_46439_/Y -rise_through fp_issue_unit/_46571_/A -fall_through fp_issue_unit/_46571_/Y -fall_through fp_issue_unit/_47883_/A -rise_through fp_issue_unit/_47883_/Y -rise_through fp_issue_unit/_47884_/B -rise_through fp_issue_unit/_47884_/Y -rise_through fp_issue_unit/_47885_/C -rise_through fp_issue_unit/_47885_/Y -rise_through fp_issue_unit/_47886_/D -rise_through fp_issue_unit/_47886_/Y -rise_through fp_issue_unit/_47887_/C -rise_through fp_issue_unit/_47887_/Y -rise_through fp_issue_unit/_47888_/C ...
Startpoint: io_flush_pipeline (input port clocked by clock_vir)
Endpoint: fp_issue_unit/_89827_
(rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clock_vir (rise edge)
400.00 400.00 clock network delay (ideal)
300.00 700.00 ^ input external delay
1 0.79 0.00 0.00 700.00 ^ io_flush_pipeline (in)
io_flush_pipeline (net)
0.06 0.02 700.02 ^ input504/A (BUFx2_ASAP7_75t_R)
1 4.55 17.58 15.46 715.48 ^ input504/Y (BUFx2_ASAP7_75t_R)
net504 (net)
17.89 1.29 716.77 ^ wire12207/A (BUFx16f_ASAP7_75t_R)
24 53.86 28.61 18.16 734.93 ^ wire12207/Y (BUFx16f_ASAP7_75t_R)
net12207 (net)
83.92 25.50 760.43 ^ max_length12204/A (BUFx16f_ASAP7_75t_R)
32 49.26 12.98 29.13 789.57 ^ max_length12204/Y (BUFx16f_ASAP7_75t_R)
net12204 (net)
220.31 69.86 859.42 ^ fp_issue_unit/_46407_/B (AOI211x1_ASAP7_75t_R)
3 3.74 59.98 45.43 904.85 v fp_issue_unit/_46407_/Y (AOI211x1_ASAP7_75t_R)
fp_issue_unit/_44478_ (net)
59.98 0.21 905.07 v fp_issue_unit/_46408_/B (NAND2x2_ASAP7_75t_R)
26 33.42 134.87 68.93 973.99 ^ fp_issue_unit/_46408_/Y (NAND2x2_ASAP7_75t_R)
fp_issue_unit/_44479_ (net)
134.89 1.12 975.12 ^ max_length4078/A (BUFx16f_ASAP7_75t_R)
22 31.72 20.83 33.87 1008.99 ^ max_length4078/Y (BUFx16f_ASAP7_75t_R)
net4078 (net)
22.31 2.51 1011.50 ^ fp_issue_unit/_46439_/C (AND4x2_ASAP7_75t_R)
5 7.55 36.45 46.10 1057.60 ^ fp_issue_unit/_46439_/Y (AND4x2_ASAP7_75t_R)
fp_issue_unit/_44510_ (net)
36.56 1.15 1058.76 ^ fp_issue_unit/_46571_/A (NAND2x2_ASAP7_75t_R)
4 3.26 16.65 13.84 1072.59 v fp_issue_unit/_46571_/Y (NAND2x2_ASAP7_75t_R)
fp_issue_unit/_44641_ (net)
16.66 0.11 1072.70 v fp_issue_unit/_47883_/A (INVx1_ASAP7_75t_R)
2 1.33 12.37 10.21 1082.91 ^ fp_issue_unit/_47883_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_45951_ (net)
12.37 0.02 1082.93 ^ fp_issue_unit/_47884_/B (AND4x2_ASAP7_75t_R)
3 5.96 30.73 40.69 1123.62 ^ fp_issue_unit/_47884_/Y (AND4x2_ASAP7_75t_R)
fp_issue_unit/_45952_ (net)
30.87 1.14 1124.77 ^ fp_issue_unit/_47885_/C (AND3x4_ASAP7_75t_R)
3 5.79 18.52 31.17 1155.94 ^ fp_issue_unit/_47885_/Y (AND3x4_ASAP7_75t_R)
fp_issue_unit/_45953_ (net)
19.20 1.89 1157.83 ^ fp_issue_unit/_47886_/D (AND4x2_ASAP7_75t_R)
3 5.98 31.11 42.40 1200.23 ^ fp_issue_unit/_47886_/Y (AND4x2_ASAP7_75t_R)
fp_issue_unit/_45954_ (net)
31.45 1.82 1202.06 ^ fp_issue_unit/_47887_/C (AND3x4_ASAP7_75t_R)
3 5.71 17.88 31.40 1233.46 ^ fp_issue_unit/_47887_/Y (AND3x4_ASAP7_75t_R)
fp_issue_unit/_45955_ (net)
18.17 1.22 1234.68 ^ fp_issue_unit/_47888_/C (AND3x4_ASAP7_75t_R)
2 5.25 17.00 29.05 1263.73 ^ fp_issue_unit/_47888_/Y (AND3x4_ASAP7_75t_R)
fp_issue_unit/_45956_ (net)
17.11 0.76 1264.49 ^ fp_issue_unit/_47889_/B (NAND2x2_ASAP7_75t_R)
3 3.85 15.69 11.87 1276.36 v fp_issue_unit/_47889_/Y (NAND2x2_ASAP7_75t_R)
fp_issue_unit/_45957_ (net)
15.84 0.84 1277.19 v fp_issue_unit/_47890_/B (OR2x2_ASAP7_75t_R)
2 3.01 13.61 25.21 1302.41 v fp_issue_unit/_47890_/Y (OR2x2_ASAP7_75t_R)
fp_issue_unit/_45958_ (net)
13.61 0.09 1302.50 v fp_issue_unit/_47907_/C (OR3x4_ASAP7_75t_R)
105 99.41 170.82 89.41 1391.91 v fp_issue_unit/_47907_/Y (OR3x4_ASAP7_75t_R)
fp_issue_unit/_45975_ (net)
172.27 9.22 1401.13 v fp_issue_unit/_47909_/C (NAND3x2_ASAP7_75t_R)
4 5.43 62.45 62.61 1463.73 ^ fp_issue_unit/_47909_/Y (NAND3x2_ASAP7_75t_R)
fp_issue_unit/_45977_ (net)
62.45 0.14 1463.88 ^ fp_issue_unit/_47962_/A (NAND3x2_ASAP7_75t_R)
2 3.47 24.56 17.68 1481.56 v fp_issue_unit/_47962_/Y (NAND3x2_ASAP7_75t_R)
fp_issue_unit/_46030_ (net)
24.59 0.45 1482.00 v fp_issue_unit/_47966_/B (OR3x2_ASAP7_75t_R)
3 3.30 17.68 37.03 1519.04 v fp_issue_unit/_47966_/Y (OR3x2_ASAP7_75t_R)
fp_issue_unit/_46034_ (net)
17.73 0.51 1519.55 v fp_issue_unit/_47971_/C (OR4x2_ASAP7_75t_R)
7 20.75 71.34 71.67 1591.22 v fp_issue_unit/_47971_/Y (OR4x2_ASAP7_75t_R)
fp_issue_unit/_46039_ (net)
71.41 1.35 1592.57 v fp_issue_unit/_47972_/A (CKINVDCx16_ASAP7_75t_R)
32 25.55 28.08 16.95 1609.51 ^ fp_issue_unit/_47972_/Y (CKINVDCx16_ASAP7_75t_R)
fp_issue_unit/_46040_ (net)
28.08 0.03 1609.55 ^ fp_issue_unit/_47975_/B (OR3x4_ASAP7_75t_R)
4 5.14 14.79 26.50 1636.05 ^ fp_issue_unit/_47975_/Y (OR3x4_ASAP7_75t_R)
fp_issue_unit/_46043_ (net)
15.26 1.43 1637.47 ^ fp_issue_unit/_47976_/B (OR2x2_ASAP7_75t_R)
2 2.90 13.93 21.14 1658.61 ^ fp_issue_unit/_47976_/Y (OR2x2_ASAP7_75t_R)
fp_issue_unit/_46044_ (net)
13.93 0.13 1658.74 ^ fp_issue_unit/_47980_/B (OR3x2_ASAP7_75t_R)
2 3.24 14.84 19.30 1678.04 ^ fp_issue_unit/_47980_/Y (OR3x2_ASAP7_75t_R)
fp_issue_unit/_46048_ (net)
14.93 0.63 1678.68 ^ fp_issue_unit/_47985_/C (OR4x2_ASAP7_75t_R)
21 25.71 98.46 51.90 1730.57 ^ fp_issue_unit/_47985_/Y (OR4x2_ASAP7_75t_R)
fp_issue_unit/_46053_ (net)
98.46 0.42 1730.99 ^ load_slew1306/A (BUFx16f_ASAP7_75t_R)
28 30.02 16.08 30.35 1761.34 ^ load_slew1306/Y (BUFx16f_ASAP7_75t_R)
net1306 (net)
17.27 1.57 1762.91 ^ fp_issue_unit/_48140_/B (NAND2x1_ASAP7_75t_R)
2 1.81 14.47 11.73 1774.64 v fp_issue_unit/_48140_/Y (NAND2x1_ASAP7_75t_R)
fp_issue_unit/_06668_ (net)
14.47 0.03 1774.67 v fp_issue_unit/_48141_/B (OR3x2_ASAP7_75t_R)
3 3.52 18.24 35.07 1809.73 v fp_issue_unit/_48141_/Y (OR3x2_ASAP7_75t_R)
fp_issue_unit/_06669_ (net)
18.24 0.11 1809.84 v fp_issue_unit/_48142_/D (OR4x2_ASAP7_75t_R)
13 37.62 133.19 75.35 1885.19 v fp_issue_unit/_48142_/Y (OR4x2_ASAP7_75t_R)
fp_issue_unit/_06670_ (net)
133.22 1.49 1886.68 v load_slew1217/A (BUFx16f_ASAP7_75t_R)
25 39.76 25.02 40.53 1927.21 v load_slew1217/Y (BUFx16f_ASAP7_75t_R)
net1217 (net)
25.03 0.48 1927.69 v fp_issue_unit/_48144_/B (AND2x2_ASAP7_75t_R)
3 3.40 13.73 25.88 1953.57 v fp_issue_unit/_48144_/Y (AND2x2_ASAP7_75t_R)
fp_issue_unit/_06672_ (net)
13.73 0.05 1953.63 v fp_issue_unit/_48145_/B (NOR2x2_ASAP7_75t_R)
3 2.92 20.73 12.02 1965.65 ^ fp_issue_unit/_48145_/Y (NOR2x2_ASAP7_75t_R)
fp_issue_unit/_06673_ (net)
20.73 0.02 1965.66 ^ fp_issue_unit/_48146_/A2 (AOI21x1_ASAP7_75t_R)
6 10.17 53.11 27.64 1993.30 v fp_issue_unit/_48146_/Y (AOI21x1_ASAP7_75t_R)
fp_issue_unit/_06674_ (net)
53.17 1.07 1994.37 v fp_issue_unit/_65458_/A (NAND2x2_ASAP7_75t_R)
7 16.17 72.15 46.53 2040.90 ^ fp_issue_unit/_65458_/Y (NAND2x2_ASAP7_75t_R)
fp_issue_unit/_22642_ (net)
72.97 4.40 2045.30 ^ wire1108/A (BUFx16f_ASAP7_75t_R)
30 37.30 21.35 27.72 2073.02 ^ wire1108/Y (BUFx16f_ASAP7_75t_R)
net1108 (net)
75.70 23.26 2096.27 ^ fp_issue_unit/_65465_/A (NAND2x2_ASAP7_75t_R)
13 21.19 71.00 42.21 2138.48 v fp_issue_unit/_65465_/Y (NAND2x2_ASAP7_75t_R)
fp_issue_unit/_22649_ (net)
71.33 2.88 2141.36 v load_slew1091/A (BUFx16f_ASAP7_75t_R)
25 35.92 17.57 30.98 2172.34 v load_slew1091/Y (BUFx16f_ASAP7_75t_R)
net1091 (net)
78.63 24.44 2196.78 v fp_issue_unit/_67437_/B (AO21x2_ASAP7_75t_R)
1 4.12 17.15 34.88 2231.66 v fp_issue_unit/_67437_/Y (AO21x2_ASAP7_75t_R)
fp_issue_unit/_46219_ (net)
17.44 1.21 2232.86 v fp_issue_unit/_89797_/A (FAx1_ASAP7_75t_R)
1 6.02 144.25 107.03 2339.89 v fp_issue_unit/_89797_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_46223_ (net)
144.48 3.10 2343.00 v fp_issue_unit/_89798_/A (FAx1_ASAP7_75t_R)
1 2.72 73.82 58.15 2401.14 ^ fp_issue_unit/_89798_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_46254_ (net)
1 1.06 45.86 22.62 2423.76 v fp_issue_unit/_89798_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_00644_ (net)
45.86 0.06 2423.83 v fp_issue_unit/_67461_/A (INVx1_ASAP7_75t_R)
1 2.41 25.51 20.41 2444.24 ^ fp_issue_unit/_67461_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46226_ (net)
25.51 0.10 2444.34 ^ fp_issue_unit/_89799_/B (FAx1_ASAP7_75t_R)
1 1.65 36.10 24.28 2468.62 v fp_issue_unit/_89799_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_46261_ (net)
1 0.86 37.25 19.10 2487.72 ^ fp_issue_unit/_89799_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_46232_ (net)
37.25 0.03 2487.75 ^ fp_issue_unit/_67462_/A (INVx1_ASAP7_75t_R)
1 2.56 21.51 16.75 2504.50 v fp_issue_unit/_67462_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46229_ (net)
21.51 0.24 2504.74 v fp_issue_unit/_89800_/A (FAx1_ASAP7_75t_R)
1 1.68 39.83 26.98 2531.72 ^ fp_issue_unit/_89800_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_46264_ (net)
1 0.90 25.69 17.11 2548.83 v fp_issue_unit/_89800_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_46244_ (net)
25.69 0.03 2548.86 v fp_issue_unit/_89787_/A (INVx1_ASAP7_75t_R)
1 2.56 21.35 16.40 2565.26 ^ fp_issue_unit/_89787_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46231_ (net)
21.36 0.17 2565.43 ^ fp_issue_unit/_89803_/B (FAx1_ASAP7_75t_R)
1 2.30 44.45 26.10 2591.54 v fp_issue_unit/_89803_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_46267_ (net)
1 0.78 39.67 20.18 2611.72 ^ fp_issue_unit/_89803_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_46249_ (net)
39.67 0.01 2611.73 ^ fp_issue_unit/_89786_/A (INVx1_ASAP7_75t_R)
1 1.74 17.87 14.14 2625.88 v fp_issue_unit/_89786_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46243_ (net)
17.87 0.04 2625.92 v fp_issue_unit/_89804_/CI (FAx1_ASAP7_75t_R)
1 0.76 33.65 19.73 2645.65 ^ fp_issue_unit/_89804_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_00646_ (net)
1 0.74 28.73 15.02 2660.67 v fp_issue_unit/_89804_/SN (FAx1_ASAP7_75t_R)
fp_issue_unit/_00645_ (net)
28.73 0.01 2660.68 v fp_issue_unit/_67482_/A (INVx1_ASAP7_75t_R)
1 1.02 13.34 11.32 2672.00 ^ fp_issue_unit/_67482_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46248_ (net)
13.34 0.02 2672.02 ^ fp_issue_unit/_89817_/B (HAxp5_ASAP7_75t_R)
1 0.78 21.67 12.77 2684.79 v fp_issue_unit/_89817_/CON (HAxp5_ASAP7_75t_R)
fp_issue_unit/_00647_ (net)
21.67 0.01 2684.80 v fp_issue_unit/_89769_/A (INVx1_ASAP7_75t_R)
1 2.06 17.70 13.87 2698.68 ^ fp_issue_unit/_89769_/Y (INVx1_ASAP7_75t_R)
fp_issue_unit/_46269_ (net)
17.70 0.03 2698.70 ^ fp_issue_unit/_89811_/A (FAx1_ASAP7_75t_R)
2 2.91 47.02 26.02 2724.72 v fp_issue_unit/_89811_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_46274_ (net)
47.02 0.08 2724.80 v fp_issue_unit/_89814_/A (FAx1_ASAP7_75t_R)
1 1.69 43.76 33.26 2758.06 ^ fp_issue_unit/_89814_/CON (FAx1_ASAP7_75t_R)
fp_issue_unit/_04309_ (net)
43.76 0.01 2758.07 ^ fp_issue_unit/_48635_/B (XOR2x1_ASAP7_75t_R)
1 1.16 22.73 24.82 2782.89 ^ fp_issue_unit/_48635_/Y (XOR2x1_ASAP7_75t_R)
fp_issue_unit/_07145_ (net)
22.73 0.02 2782.92 ^ fp_issue_unit/_48636_/B (NAND2x1_ASAP7_75t_R)
2 1.32 14.09 11.34 2794.26 v fp_issue_unit/_48636_/Y (NAND2x1_ASAP7_75t_R)
fp_issue_unit/_07146_ (net)
14.09 0.02 2794.27 v fp_issue_unit/_48637_/B (OR2x2_ASAP7_75t_R)
3 2.18 11.43 23.11 2817.38 v fp_issue_unit/_48637_/Y (OR2x2_ASAP7_75t_R)
fp_issue_unit/_07147_ (net)
11.43 0.05 2817.43 v fp_issue_unit/_48639_/C (OR3x1_ASAP7_75t_R)
1 0.71 10.68 24.49 2841.92 v fp_issue_unit/_48639_/Y (OR3x1_ASAP7_75t_R)
fp_issue_unit/_00000_ (net)
10.68 0.01 2841.93 v fp_issue_unit/_89827_/D (DFFHQNx2_ASAP7_75t_R)
2841.93 data arrival time
0.00 1500.00 1500.00 clock clock (rise edge)
0.00 1500.00 clock network delay (ideal)
-10.00 1490.00 clock uncertainty
0.00 1490.00 clock reconvergence pessimism
1490.00 ^ fp_issue_unit/_89827_/CLK (DFFHQNx2_ASAP7_75t_R)
-7.35 1482.65 library setup time
1482.65 data required time
-----------------------------------------------------------------------------
1482.65 data required time
-2841.93 data arrival time
-----------------------------------------------------------------------------
-1359.27 slack (VIOLATED)