| # Any thoughts on what to do to solve the global routing problems in MegaBoom? | |
| Tool: Global Routing | |
| Subcategory: Global routing congestion | |
| ## Conversation | |
| ### oharboe | |
| I would like to get https://github.com/The-OpenROAD-Project/megaboom to the point where it goes through a full build and then incrementally improve. | |
| The idea with such big projects is to get the build under CI, separate concerns and continously improve... | |
| Currently it stops in global routing: | |
|  | |
| Current options for DigitalTop: | |
| https://github.com/The-OpenROAD-Project/megaboom/blob/391bbbd8d59b93b15b1cdb850294696a60d2dd4f/BUILD.bazel#L1636 | |
| - the yellow are hold cells. Given the 2000+ps skew in the clock tree, I don't find it shocking that there's ca. 100000 hold cells. I have set clock_latency to 3300, which I could try to change to 1000 to be closer to what is actually going on, but that still leaves 1000ps of clock skew on either side of that... There is the familiar hold cell log jam at the pins... | |
| - there is a lot of congestion on top of the macro. What does that mean and how can it be fixed? | |
| - reduce placement density? | |
| - Increase number of global routing iterations from 30 to 100? | |
|  | |
| If you want to have a look... | |
| 1. Build OpenROAD https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/docs/user/BuildLocally.md | |
| 2. download. 1.3gByte. https://drive.google.com/file/d/1HcAU-pOsPvhcMGKdSWvy_mV17By0qH65/view?usp=sharing | |
| 3. untar | |
| 4. run: | |
| ``` | |
| $ . ~/OpenROAD-flow-scripts/env.sh | |
| OPENROAD: /home/oyvind/OpenROAD-flow-scripts/tools/OpenROAD | |
| $ ./run-me-DigitalTop-asap7-base.sh | |
| ``` | |
| ### rovinski | |
| Some miscellaneous thoughts: | |
| * The keep-out region around the macros seems higher than necessary. Can it be shrunk? | |
| * Is there a way to push the macros all the way to the edges? If there are no pins on one side, then it should be fine to push it all the way to the edge. Right now, the gap between the macro and the edge is just wasted space. | |
| >  | |
| * I'm assuming the highlighted yellow are the hold cells? If so, it looks like they are feeding towards the I/Os. You should double check that your I/O constraints are in reference to the clock tree latency so that they are reasonable. For example, if the input constraint is 50ps, but the capture register has a 2000ps clock latency, then the tools need to insert 1950ps of hold buffers. If the output constraint is 50ps and the launch register clock latency is 2000ps, the best it could do is -1950ps slack. | |
| * Do your large macros have the clock tree latency annotated in them when extracted? I believe that CTS support for this was added to help balancing, but I am not sure if the GUI or the skew report reflect this. If a macro and a register have 1000ps of skew, it could be totally fine if the macro has an internal clock tree of 1000ps. | |
| * Even with that consideration, the clock tree looks very unbalanced. There might be something breaking down with the algorithm. | |
| ### maliberty | |
| I think resolve the clock skew will go a long way to resolving the other problems so let's start there. Even without insertion delay the tree is quite skewed. | |
| MACRO_PLACE_HALO="20 20" seems rather large. How did you pick those? | |
| ### oharboe | |
| Still cooking, but 100 global routing iterations + some fixes from the list above and only 6 violations. Lets see if it can push through... | |
| Many more things to test and tweak in the design, this is just intended to be a baseline. | |
|  | |
| ### maliberty | |
| In looking at auto_prci_ctrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock it goes into a user buffer prci_ctrl_domain/_1019_. I'm not clear why we would have a user buffer in the clock tree. Did you skip remove_buffers in floorplanning? | |
| ### maliberty | |
| How did you run cts? I see 75 instances named 'cklbuf*'. The clkbuf seem only related to a small area (showing only 'Clock tree' instances): | |
|  | |
| I see 7535 instances named 'load_slew*'. It seems most of the tree is not actually clock buffers: | |
|  | |
| ### oharboe | |
| @maliberty So it seems to me that outputting the clock from a module, so that you have the clock coming in with 0 insertion latency and the clock output with the clock tree leaf insertion latency would be useful to deal with a very large clock tree latency as follows: | |
| Create FIFOs on the outside that take the input clock for the module with large clock tree insertion latency as well as the output clock. Now you have two clock domains, use this FIFO to cross the two clock domain. The input/output pins of the module with large clock tree insertion latency can now have a clock latency constraints that is approximately equal to the clock tree insertion latency, which relaxes the constraints within the module. | |
| It is a bit annoying to set up that .sdc file, because you can't know the clock tree insertion latency until after you have run CTS, so a few iterations are probably needed... | |
| ### oharboe | |
| Another datapoint, running times for this design (macros not included): | |
| ``` | |
| Log Elapsed seconds | |
| 1_1_yosys 2614 | |
| 1_1_yosys_hier_report 2518 | |
| 2_1_floorplan 186 | |
| 2_2_floorplan_io 6 | |
| 2_4_floorplan_macro 312 | |
| 2_5_floorplan_tapcell 108 | |
| 2_6_floorplan_pdn 234 | |
| 3_1_place_gp_skip_io 322 | |
| 3_2_place_iop 12 | |
| 3_3_place_gp 2904 | |
| 3_4_place_resized 590 | |
| 3_5_place_dp 683 | |
| 4_1_cts 5259 | |
| ``` | |
| ### maliberty | |
| The cts runtime is likely mostly comprised of rsz runtime buffering that huge clock net. | |
| I haven't looked at the floorplan test case but I think I know what's going on. remove_buffers will not remove a buffer that is between a primary input and output (that would leave a pure feedthru which is a generally a bad thing). So it likely removes all the buffers but one as you have both in and out clock ports tied together. | |
| CTS sees the buffer and assumes you have a manually constructed tree and skips as shown above. | |
| This is not a methodology that OR supports. It seems a difficult one to do in general as you have no real idea what the skew requirement on the output pin should be. I don't understand chipyard or this design so I'm not sure what to suggest here. | |
| re "However, Yosys can't compile ChipTop, nor flatten the entire design(it would run forever), so I only build DigitalTop and hence we get clocks going out at the top level." Can you flatten just DigitalTop into ChipTop and not the whole design? | |
| ### oharboe | |
| @rovinski | |
| > Bad logical designs can absolutely hamper physical design, and this is one example. It is taking away options from the algorithms and defecting to the user to make the proper decision, which is the opposite of what is wanted for automated design and design space exploration. | |
| > | |
| > I have done a decent amount of clock tree structuring for taped out chips, and this is simply a bad methodology except in very specific hand-tuned circumstances. It only works if you ensure the tree is manually balanced and the only reason to do it is to save clock power by reducing the branching factor and/or to reduce clock tree jitter for specific endpoints. | |
| Don't take my word for what MegaBoom is doing and not doing and why. I just have a default assumption that the authors knew what they were doing and did what they did the way they did for a reason... | |
| Since I know they are making a CPU, it makes sense to me(a default assumption until I learn more) that the memory master interface of that CPU is running on a different clock domain and that it is providing the clock which slave devices must use is an output. | |
| Or.... perhaps I'm not generating the Verilog in the right way...? The AXI output clock for the memory master interface might be there for the simulation test harness rather than synthesis? | |
| This Hammer file is for SonicBOOM (a smaller design than MegaBoom), it doesn't offer any clues as to what the AXI output clock means... | |
| https://github.com/ucb-bar/chipyard/blob/main/vlsi/example-designs/sky130-openroad.yml | |
| ### oharboe | |
| This is a screenshot from after global route of ChipTop.sv: | |
| - Standalone reproduction case for CTS in this case which includes the global routing result & congestion report: https://drive.google.com/file/d/1sAFbG_MpjmaN4inulYWUqbeuPsYLqx73/view?usp=sharing | |
| - I was wrong that ChipTop.sv didn't go through synthesis with Yosys. I can't recall what problems I was having, though there are some simulation only .sv files that won't go through Yosys that are not used by ChipTop, perhaps I was confused by those? | |
| - Only two global route failures indicated (white crosses) | |
| - How can I tell if I have a clock tree? | |
| - There are significant caveats still in that the macro abstracts are mocked: they only went through floorplan. I'll do a full build later. Still it is possible to learn something at this stage. | |
| - clock_uncore_clock is fed through to axi4_mem_0_clock and the text says that it is clocked by clock_uncore_clock_vir, which makes sense. clock_uncore_clock_vir is clock_uncore_clock + source latency. | |
| ``` | |
| Startpoint: clock_uncore_clock (clock source 'clock_uncore_clock') | |
| Endpoint: axi4_mem_0_clock (output port clocked by clock_uncore_clock_vir) | |
| ``` | |
|  | |
| There is a second clock into the design, but my guess is that this has something to do with a peripheral or other, not the CPU: | |
|  | |
| ``` | |
| OpenROAD v2.0-11704-gfb0df7fb7 | |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. | |
| Components of this program may be licensed under more restrictive licenses which must be honored. | |
| [WARNING STA-0357] virtual clock clock_uncore_clock_vir can not be propagated. | |
| Estimating parasitics | |
| [WARNING GUI-0076] QXcbConnection: XCB error: 3 (BadWindow), sequence: 3175, resource id: 16788675, major code: 40 (TranslateCoords), minor code: 0 | |
| >>> report_checks -path_delay max -fields {fanout skew} | |
| Startpoint: reset_io (input port clocked by clock_uncore_clock_vir) | |
| Endpoint: system/prci_ctrl_domain/_0952_ | |
| (recovery check against rising-edge clock clock_uncore_clock) | |
| Path Group: asynchronous | |
| Path Type: max | |
| Fanout Delay Time Description | |
| --------------------------------------------------------------- | |
| 0.00 0.00 clock clock_uncore_clock_vir (rise edge) | |
| 1000.00 1000.00 clock network delay (ideal) | |
| 1700.00 2700.00 v input external delay | |
| 1 0.00 2700.00 v reset_io (in) | |
| 1 12.54 2712.54 v input87/Y (BUFx12f_ASAP7_75t_R) | |
| 1 70.17 2782.71 v wire49778/Y (BUFx16f_ASAP7_75t_R) | |
| 4 59.30 2842.00 ^ system/prci_ctrl_domain/_0722_/Y (INVx2_ASAP7_75t_R) | |
| 0.53 2842.54 ^ system/prci_ctrl_domain/_0952_/SETN (DFFASRHQNx1_ASAP7_75t_R) | |
| 2842.54 data arrival time | |
| 8500.00 8500.00 clock clock_uncore_clock (rise edge) | |
| 871.54 9371.54 clock network delay (propagated) | |
| -10.00 9361.54 clock uncertainty | |
| 0.00 9361.54 clock reconvergence pessimism | |
| 9361.54 ^ system/prci_ctrl_domain/_0952_/CLK (DFFASRHQNx1_ASAP7_75t_R) | |
| 15.79 9377.33 library recovery time | |
| 9377.33 data required time | |
| --------------------------------------------------------------- | |
| 9377.33 data required time | |
| -2842.54 data arrival time | |
| --------------------------------------------------------------- | |
| 6534.79 slack (MET) | |
| Startpoint: _32_ (negative level-sensitive latch clocked by clock_uncore_clock) | |
| Endpoint: _10_ | |
| (rising clock gating-check end-point clocked by clock_uncore_clock) | |
| Path Group: gated clock | |
| Path Type: max | |
| Fanout Delay Time Description | |
| --------------------------------------------------------------- | |
| 4250.00 4250.00 clock clock_uncore_clock (fall edge) | |
| 532.14 4782.14 clock network delay (propagated) | |
| 0.00 4782.14 v _32_/CLK (DLLx1_ASAP7_75t_R) | |
| 1 45.86 4828.00 v _32_/Q (DLLx1_ASAP7_75t_R) | |
| 0.02 4828.02 v _10_/B (AND2x4_ASAP7_75t_R) | |
| 4828.02 data arrival time | |
| 8500.00 8500.00 clock clock_uncore_clock (rise edge) | |
| 492.25 8992.25 clock network delay (propagated) | |
| -10.00 8982.25 clock uncertainty | |
| 0.00 8982.25 clock reconvergence pessimism | |
| 8982.25 ^ _10_/A (AND2x4_ASAP7_75t_R) | |
| 0.00 8982.25 clock gating setup time | |
| 8982.25 data required time | |
| --------------------------------------------------------------- | |
| 8982.25 data required time | |
| -4828.02 data arrival time | |
| --------------------------------------------------------------- | |
| 4154.23 slack (MET) | |
| Startpoint: system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_ | |
| (rising edge-triggered flip-flop clocked by clock_uncore_clock) | |
| Endpoint: system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_ | |
| (rising edge-triggered flip-flop clocked by clock_uncore_clock) | |
| Path Group: clock_uncore_clock | |
| Path Type: max | |
| Fanout Delay Time Description | |
| --------------------------------------------------------------- | |
| 0.00 0.00 clock clock_uncore_clock (rise edge) | |
| 1899.28 1899.28 clock network delay (propagated) | |
| 0.00 1899.28 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_/CLK (DFFHQNx2_ASAP7_75t_R) | |
| 6 75.38 1974.65 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095120_/QN (DFFHQNx2_ASAP7_75t_R) | |
| 1 22.16 1996.82 ^ hold78251/Y (BUFx2_ASAP7_75t_R) | |
| 3 20.28 2017.09 ^ hold24171/Y (BUFx2_ASAP7_75t_R) | |
| 1 18.71 2035.80 ^ hold78252/Y (BUFx2_ASAP7_75t_R) | |
| 6 44.43 2080.23 ^ hold14462/Y (BUFx2_ASAP7_75t_R) | |
| 14 32.26 2112.50 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052537_/Y (CKINVDCx20_ASAP7_75t_R) | |
| 10 114.99 2227.49 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095077_/CON (HAxp5_ASAP7_75t_R) | |
| 4 27.96 2255.44 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052831_/Y (INVx4_ASAP7_75t_R) | |
| 2 30.15 2285.59 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_064284_/Y (AND2x2_ASAP7_75t_R) | |
| 6 64.65 2350.24 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_095079_/CON (HAxp5_ASAP7_75t_R) | |
| 6 43.78 2394.03 ^ wire30543/Y (BUFx12_ASAP7_75t_R) | |
| 2 20.98 2415.01 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052672_/Y (INVx11_ASAP7_75t_R) | |
| 3 15.28 2430.28 v max_length29072/Y (BUFx12f_ASAP7_75t_R) | |
| 3 32.78 2463.06 v max_length29071/Y (BUFx10_ASAP7_75t_R) | |
| 13 69.31 2532.38 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052686_/Y (OR4x2_ASAP7_75t_R) | |
| 2 63.47 2595.85 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052855_/Y (OR3x4_ASAP7_75t_R) | |
| 2 43.49 2639.34 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052856_/Y (AND3x4_ASAP7_75t_R) | |
| 16 17.48 2656.82 v wire25227/Y (BUFx16f_ASAP7_75t_R) | |
| 4 89.89 2746.71 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/rob/_052858_/Y (AND4x2_ASAP7_75t_R) | |
| 1 21.42 2768.12 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09468_/Y (NAND2x2_ASAP7_75t_R) | |
| 3 27.61 2795.74 ^ wire22599/Y (BUFx12f_ASAP7_75t_R) | |
| 2 63.18 2858.92 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09478_/Y (OA21x2_ASAP7_75t_R) | |
| 1 21.19 2880.10 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09481_/Y (OR3x4_ASAP7_75t_R) | |
| 1 15.57 2895.67 ^ hold11148/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.93 2911.60 ^ hold8869/Y (BUFx2_ASAP7_75t_R) | |
| 3 22.93 2934.53 ^ hold11149/Y (BUFx2_ASAP7_75t_R) | |
| 5 33.02 2967.55 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_10524_/Y (NOR3x2_ASAP7_75t_R) | |
| 2 32.14 2999.70 v wire20615/Y (BUFx16f_ASAP7_75t_R) | |
| 19 76.62 3076.32 v wire20614/Y (BUFx16f_ASAP7_75t_R) | |
| 30 123.33 3199.65 v wire20613/Y (BUFx16f_ASAP7_75t_R) | |
| 16 26.25 3225.90 v wire20612/Y (BUFx16f_ASAP7_75t_R) | |
| 1 60.57 3286.46 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140035_/Y (AND3x1_ASAP7_75t_R) | |
| 9 19.01 3305.47 v wire19271/Y (BUFx16f_ASAP7_75t_R) | |
| 1 89.99 3395.47 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140050_/Y (AND2x2_ASAP7_75t_R) | |
| 7 36.72 3432.19 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140051_/Y (AO21x2_ASAP7_75t_R) | |
| 6 51.35 3483.53 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140087_/Y (INVx13_ASAP7_75t_R) | |
| 5 35.71 3519.24 ^ wire16755/Y (BUFx16f_ASAP7_75t_R) | |
| 7 104.20 3623.44 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267695_/CON (HAxp5_ASAP7_75t_R) | |
| 5 26.52 3649.96 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140053_/Y (INVx3_ASAP7_75t_R) | |
| 2 31.74 3681.71 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140060_/Y (AND3x1_ASAP7_75t_R) | |
| 2 23.56 3705.27 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267682_/CON (HAxp5_ASAP7_75t_R) | |
| 2 24.40 3729.67 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267682_/SN (HAxp5_ASAP7_75t_R) | |
| 1 28.23 3757.89 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149590_/Y (XNOR2x1_ASAP7_75t_R) | |
| 1 43.36 3801.25 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149594_/Y (AND5x2_ASAP7_75t_R) | |
| 1 24.45 3825.70 ^ wire13571/Y (BUFx12f_ASAP7_75t_R) | |
| 1 64.03 3889.73 ^ wire13570/Y (BUFx16f_ASAP7_75t_R) | |
| 1 79.93 3969.66 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09472_/Y (AO221x2_ASAP7_75t_R) | |
| 1 68.57 4038.23 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09473_/Y (OR5x2_ASAP7_75t_R) | |
| 1 13.72 4051.94 ^ hold11977/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.26 4064.20 ^ hold7674/Y (BUFx2_ASAP7_75t_R) | |
| 2 14.63 4078.84 ^ hold11978/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.72 4094.55 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09475_/Y (OA21x2_ASAP7_75t_R) | |
| 2 20.63 4115.18 ^ hold7675/Y (BUFx2_ASAP7_75t_R) | |
| 5 24.11 4139.29 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_10522_/Y (NOR3x2_ASAP7_75t_R) | |
| 1 22.06 4161.35 v hold18417/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.68 4174.03 v hold10243/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.21 4186.24 v hold18418/Y (BUFx2_ASAP7_75t_R) | |
| 2 20.53 4206.77 v hold7676/Y (BUFx2_ASAP7_75t_R) | |
| 1 18.19 4224.96 v hold18419/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.59 4237.55 v hold10244/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.38 4252.93 v hold18420/Y (BUFx2_ASAP7_75t_R) | |
| 2 13.31 4266.24 v load_slew12502/Y (BUFx12f_ASAP7_75t_R) | |
| 1 15.05 4281.29 v hold18421/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.37 4296.67 v hold10245/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.35 4312.02 v hold18422/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.30 4327.32 v hold7677/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.27 4342.59 v hold18423/Y (BUFx2_ASAP7_75t_R) | |
| 3 30.80 4373.39 v hold10246/Y (BUFx2_ASAP7_75t_R) | |
| 3 35.71 4409.10 v max_length12501/Y (BUFx16f_ASAP7_75t_R) | |
| 17 68.42 4477.52 v wire12498/Y (BUFx16f_ASAP7_75t_R) | |
| 29 122.51 4600.04 v max_length12497/Y (BUFx16f_ASAP7_75t_R) | |
| 18 24.10 4624.14 v max_length12496/Y (BUFx16f_ASAP7_75t_R) | |
| 3 67.14 4691.28 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140063_/Y (AND3x4_ASAP7_75t_R) | |
| 10 59.39 4750.67 v max_length12300/Y (BUFx16f_ASAP7_75t_R) | |
| 3 72.57 4823.25 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140076_/Y (XNOR2x2_ASAP7_75t_R) | |
| 9 20.37 4843.61 ^ load_slew11681/Y (BUFx16f_ASAP7_75t_R) | |
| 5 23.34 4866.96 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_201351_/Y (CKINVDCx16_ASAP7_75t_R) | |
| 3 45.17 4912.12 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267727_/CON (HAxp5_ASAP7_75t_R) | |
| 3 20.27 4932.39 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140092_/Y (INVx2_ASAP7_75t_R) | |
| 1 21.44 4953.83 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267721_/CON (HAxp5_ASAP7_75t_R) | |
| 2 16.81 4970.65 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267668_/Y (INVx1_ASAP7_75t_R) | |
| 2 57.58 5028.23 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267723_/SN (HAxp5_ASAP7_75t_R) | |
| 1 30.13 5058.35 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149595_/Y (XNOR2x1_ASAP7_75t_R) | |
| 1 35.26 5093.62 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149601_/Y (AND5x2_ASAP7_75t_R) | |
| 1 34.85 5128.46 v wire8234/Y (BUFx16f_ASAP7_75t_R) | |
| 1 69.42 5197.89 v wire8233/Y (BUFx16f_ASAP7_75t_R) | |
| 1 86.50 5284.38 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09501_/Y (AO221x2_ASAP7_75t_R) | |
| 1 64.90 5349.29 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09502_/Y (OR4x2_ASAP7_75t_R) | |
| 1 15.04 5364.33 v hold11691/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.71 5377.04 v hold8103/Y (BUFx2_ASAP7_75t_R) | |
| 2 15.24 5392.28 v hold11692/Y (BUFx2_ASAP7_75t_R) | |
| 1 8.30 5400.59 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09503_/Y (NOR2x1_ASAP7_75t_R) | |
| 1 16.07 5416.66 ^ hold11693/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.98 5428.63 ^ hold8104/Y (BUFx2_ASAP7_75t_R) | |
| 2 14.25 5442.89 ^ hold11694/Y (BUFx2_ASAP7_75t_R) | |
| 6 33.66 5476.55 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_13871_/Y (AND3x4_ASAP7_75t_R) | |
| 1 19.94 5496.49 ^ hold17405/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.17 5508.66 ^ hold11980/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.81 5520.46 ^ hold17406/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.68 5532.14 ^ hold11695/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.84 5543.97 ^ hold11981/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.84 5555.81 ^ hold8105/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.69 5567.50 ^ hold11982/Y (BUFx2_ASAP7_75t_R) | |
| 1 11.65 5579.15 ^ hold11696/Y (BUFx2_ASAP7_75t_R) | |
| 1 14.92 5594.07 ^ hold11983/Y (BUFx2_ASAP7_75t_R) | |
| 2 13.10 5607.17 ^ max_length7476/Y (BUFx12f_ASAP7_75t_R) | |
| 1 16.07 5623.24 ^ hold11984/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.88 5639.12 ^ hold11697/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.95 5655.07 ^ hold11985/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.87 5670.94 ^ hold8106/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.89 5686.83 ^ hold11986/Y (BUFx2_ASAP7_75t_R) | |
| 2 26.49 5713.32 ^ hold11698/Y (BUFx2_ASAP7_75t_R) | |
| 2 26.12 5739.44 ^ hold11987/Y (BUFx2_ASAP7_75t_R) | |
| 3 20.02 5759.46 ^ wire7475/Y (BUFx16f_ASAP7_75t_R) | |
| 6 50.30 5809.76 ^ max_length7474/Y (BUFx12f_ASAP7_75t_R) | |
| 2 66.91 5876.68 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140099_/Y (AND2x2_ASAP7_75t_R) | |
| 1 17.15 5893.83 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_140100_/Y (NAND2x2_ASAP7_75t_R) | |
| 8 30.84 5924.67 v wire6776/Y (BUFx16f_ASAP7_75t_R) | |
| 13 114.72 6039.39 v load_slew6775/Y (BUFx16f_ASAP7_75t_R) | |
| 1 54.63 6094.02 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_146049_/Y (OR2x2_ASAP7_75t_R) | |
| 7 41.21 6135.24 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_146050_/Y (OA21x2_ASAP7_75t_R) | |
| 9 39.67 6174.90 v wire5396/Y (BUFx16f_ASAP7_75t_R) | |
| 5 51.31 6226.22 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267763_/CON (HAxp5_ASAP7_75t_R) | |
| 5 17.32 6243.54 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149526_/Y (INVx5_ASAP7_75t_R) | |
| 1 56.08 6299.62 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267765_/CON (HAxp5_ASAP7_75t_R) | |
| 2 29.02 6328.63 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267663_/Y (INVx1_ASAP7_75t_R) | |
| 2 126.39 6455.02 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_267767_/SN (HAxp5_ASAP7_75t_R) | |
| 1 54.46 6509.49 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149603_/Y (XNOR2x1_ASAP7_75t_R) | |
| 1 37.55 6547.04 v system/tile_prci_domain/tile_reset_domain/boom_tile/lsu/_149608_/Y (AND5x2_ASAP7_75t_R) | |
| 1 37.85 6584.88 v wire4143/Y (BUFx16f_ASAP7_75t_R) | |
| 1 69.84 6654.72 v wire4142/Y (BUFx16f_ASAP7_75t_R) | |
| 1 84.81 6739.53 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09493_/Y (AO221x2_ASAP7_75t_R) | |
| 1 57.90 6797.43 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09494_/Y (OR4x2_ASAP7_75t_R) | |
| 1 14.94 6812.38 v hold30872/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.79 6825.17 v hold13130/Y (BUFx2_ASAP7_75t_R) | |
| 2 14.65 6839.82 v hold30873/Y (BUFx2_ASAP7_75t_R) | |
| 2 20.21 6860.03 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09495_/Y (OR2x2_ASAP7_75t_R) | |
| 1 14.23 6874.25 v hold30874/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.10 6886.36 v hold13131/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.38 6898.74 v hold30875/Y (BUFx2_ASAP7_75t_R) | |
| 1 13.47 6912.20 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09505_/Y (AO21x1_ASAP7_75t_R) | |
| 1 12.83 6925.03 v hold30876/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.37 6937.40 v hold13132/Y (BUFx2_ASAP7_75t_R) | |
| 1 15.35 6952.75 v hold30877/Y (BUFx2_ASAP7_75t_R) | |
| 17 31.60 6984.35 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_09506_/Y (NOR3x2_ASAP7_75t_R) | |
| 1 22.33 7006.68 ^ hold32043/Y (BUFx2_ASAP7_75t_R) | |
| 1 12.37 7019.06 ^ hold30878/Y (BUFx2_ASAP7_75t_R) | |
| 4 22.96 7042.02 ^ hold13133/Y (BUFx2_ASAP7_75t_R) | |
| 35 24.88 7066.90 ^ load_slew4133/Y (BUFx16f_ASAP7_75t_R) | |
| 2 26.42 7093.32 ^ hold13134/Y (BUFx2_ASAP7_75t_R) | |
| 5 31.12 7124.44 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/_13971_/Y (AND2x6_ASAP7_75t_R) | |
| 2 27.47 7151.91 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/_3835_/Y (INVx2_ASAP7_75t_R) | |
| 1 14.40 7166.30 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/_5294_/Y (NOR2x2_ASAP7_75t_R) | |
| 5 17.30 7183.60 ^ wire3988/Y (BUFx16f_ASAP7_75t_R) | |
| 1 84.04 7267.64 ^ wire3987/Y (BUFx16f_ASAP7_75t_R) | |
| 8 66.05 7333.69 ^ wire3986/Y (BUFx16f_ASAP7_75t_R) | |
| 9 136.20 7469.90 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_52698_/Y (AND4x2_ASAP7_75t_R) | |
| 6 60.97 7530.87 ^ wire3601/Y (BUFx16f_ASAP7_75t_R) | |
| 10 86.11 7616.98 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54157_/Y (AND2x6_ASAP7_75t_R) | |
| 14 23.34 7640.32 ^ wire2977/Y (BUFx16f_ASAP7_75t_R) | |
| 8 50.78 7691.10 ^ max_length2976/Y (BUFx12f_ASAP7_75t_R) | |
| 16 39.60 7730.70 ^ max_length2975/Y (BUFx16f_ASAP7_75t_R) | |
| 14 17.45 7748.16 ^ wire2974/Y (BUFx16f_ASAP7_75t_R) | |
| 16 29.41 7777.57 ^ wire2973/Y (BUFx16f_ASAP7_75t_R) | |
| 3 77.98 7855.55 ^ wire2972/Y (BUFx16f_ASAP7_75t_R) | |
| 2 82.43 7937.98 v system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54165_/Y (NOR2x2_ASAP7_75t_R) | |
| 10 30.56 7968.54 v max_length1585/Y (BUFx16f_ASAP7_75t_R) | |
| 12 70.74 8039.28 v load_slew1584/Y (BUFx12f_ASAP7_75t_R) | |
| 8 18.25 8057.53 v max_length1583/Y (BUFx12f_ASAP7_75t_R) | |
| 11 46.63 8104.16 v load_slew1582/Y (BUFx16f_ASAP7_75t_R) | |
| 12 55.12 8159.28 v wire1580/Y (BUFx16f_ASAP7_75t_R) | |
| 12 57.79 8217.07 v max_length1579/Y (BUFx16f_ASAP7_75t_R) | |
| 1 39.31 8256.38 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_54636_/Y (AOI221x1_ASAP7_75t_R) | |
| 0.01 8256.39 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_/D (DFFHQNx2_ASAP7_75t_R) | |
| 8256.39 data arrival time | |
| 8500.00 8500.00 clock clock_uncore_clock (rise edge) | |
| 380.41 8880.41 clock network delay (propagated) | |
| -10.00 8870.41 clock uncertainty | |
| 0.00 8870.41 clock reconvergence pessimism | |
| 8870.41 ^ system/tile_prci_domain/tile_reset_domain/boom_tile/core/fp_rename_stage/maptable/_80484_/CLK (DFFHQNx2_ASAP7_75t_R) | |
| -5.21 8865.20 library setup time | |
| 8865.20 data required time | |
| --------------------------------------------------------------- | |
| 8865.20 data required time | |
| -8256.39 data arrival time | |
| --------------------------------------------------------------- | |
| 608.81 slack (MET) | |
| Startpoint: clock_uncore_clock (clock source 'clock_uncore_clock') | |
| Endpoint: axi4_mem_0_clock (output port clocked by clock_uncore_clock_vir) | |
| Path Group: clock_uncore_clock_vir | |
| Path Type: max | |
| Fanout Delay Time Description | |
| --------------------------------------------------------------- | |
| 4250.00 4250.00 clock clock_uncore_clock (fall edge) | |
| 1775.06 6025.06 clock network delay | |
| 6025.06 v axi4_mem_0_clock (out) | |
| 6025.06 data arrival time | |
| 8500.00 8500.00 clock clock_uncore_clock_vir (rise edge) | |
| 1000.00 9500.00 clock network delay (ideal) | |
| -10.00 9490.00 clock uncertainty | |
| 0.00 9490.00 clock reconvergence pessimism | |
| -1700.00 7790.00 output external delay | |
| 7790.00 data required time | |
| --------------------------------------------------------------- | |
| 7790.00 data required time | |
| -6025.06 data arrival time | |
| --------------------------------------------------------------- | |
| 1764.93 slack (MET) | |
| Startpoint: serial_tl_bits_out_ready | |
| (input port clocked by clock_uncore_clock_vir) | |
| Endpoint: system/subsystem_fbus/out_async/_1122_ | |
| (rising edge-triggered flip-flop clocked by serial_tl_clock) | |
| Path Group: serial_tl_clock | |
| Path Type: max | |
| Fanout Delay Time Description | |
| --------------------------------------------------------------- | |
| 0.00 0.00 clock clock_uncore_clock_vir (rise edge) | |
| 1000.00 1000.00 clock network delay (ideal) | |
| 1700.00 2700.00 v input external delay | |
| 1 0.00 2700.00 v serial_tl_bits_out_ready (in) | |
| 1 11.42 2711.42 v input121/Y (BUFx2_ASAP7_75t_R) | |
| 1 21.57 2733.00 v system/subsystem_fbus/out_async/_0655_/Y (AND2x6_ASAP7_75t_R) | |
| 1 27.18 2760.18 ^ system/subsystem_fbus/out_async/_1119_/CON (HAxp5_ASAP7_75t_R) | |
| 1 9.72 2769.90 v system/subsystem_fbus/out_async/_1118_/Y (INVx1_ASAP7_75t_R) | |
| 1 13.58 2783.48 ^ system/subsystem_fbus/out_async/_1120_/CON (HAxp5_ASAP7_75t_R) | |
| 1 8.76 2792.23 v system/subsystem_fbus/out_async/_1117_/Y (INVx1_ASAP7_75t_R) | |
| 12 204.22 2996.46 v system/subsystem_fbus/out_async/_1121_/SN (HAxp5_ASAP7_75t_R) | |
| 12 53.79 3050.25 v load_slew27103/Y (BUFx6f_ASAP7_75t_R) | |
| 2 24.58 3074.83 v system/subsystem_fbus/out_async/_0587_/Y (XNOR2x1_ASAP7_75t_R) | |
| 1 26.20 3101.02 v system/subsystem_fbus/out_async/_0588_/Y (OR3x1_ASAP7_75t_R) | |
| 33 54.44 3155.46 v system/subsystem_fbus/out_async/_0593_/Y (AO22x2_ASAP7_75t_R) | |
| 33 113.80 3269.27 ^ system/subsystem_fbus/out_async/_0594_/Y (NAND2x2_ASAP7_75t_R) | |
| 1 46.55 3315.82 ^ system/subsystem_fbus/out_async/_0679_/Y (OA21x2_ASAP7_75t_R) | |
| 0.02 3315.84 ^ system/subsystem_fbus/out_async/_1122_/D (DFFHQNx2_ASAP7_75t_R) | |
| 3315.84 data arrival time | |
| 8500.00 8500.00 clock serial_tl_clock (rise edge) | |
| 191.14 8691.14 clock network delay (propagated) | |
| -10.00 8681.14 clock uncertainty | |
| 0.00 8681.14 clock reconvergence pessimism | |
| 8681.14 ^ system/subsystem_fbus/out_async/_1122_/CLK (DFFHQNx2_ASAP7_75t_R) | |
| -5.07 8676.07 library setup time | |
| 8676.07 data required time | |
| --------------------------------------------------------------- | |
| 8676.07 data required time | |
| -3315.84 data arrival time | |
| --------------------------------------------------------------- | |
| 5360.23 slack (MET) | |
| ``` | |
| ### oharboe | |
| I've posted a question to Chipyard: https://groups.google.com/g/chipyard/c/BXsafsGlhJ0 | |