markdown/gh_discussions/Runtime/4529.md

# MegaBoom flattened

Tool: Global Routing

Subcategory: Long run times

## Conversation

### oharboe
Based on https://github.com/The-OpenROAD-Project/megaboom/commit/a8e07eab7d4848057ac8e7993d5fee93b3d8653d

After understanding the design better and a best effort to [generating Verilog](https://groups.google.com/g/chipyard/c/XPmGRK_CtZA) for the core with an asynchronous FIFO from the core to the surrounding memory system and buses such that the depth of the clock tree in the core isn't such an enormous issue + I have a report from yosys to list all RAMs and ROMs in the design such that I can be sure that I mock all ROM/RAMs larger than 1024 bits, it was time to try [MegaBoom flattened](https://github.com/The-OpenROAD-Project/megaboom/blob/1cce55c772d823ebca0bf8368f1d363a2e546044/BUILD.bazel#L1153)...

The core here is MegaBoom up to and including L1 data/instruction cache. L2 & peripherals are excluded.

Synthesis times are tolerable and not that far off non-flattened where I break out some macros for the larger parts of the core: ICache, DCache, branch predictor and floating point pipeline.

```
Log                       Elapsed seconds
1_1_yosys                       4057
1_1_yosys_hier_report           4063
Total                           8120
```

From `make gui_synth`, I can see that the core is ca. 98% of the design measured in instances. The rest are buses and asynchronous bridges.

`make memory` reports the table of roms and rams in the design. This report uses yosys and takes ca. 5 minutes to run, very acceptable. It would be *great* if synthesis could be run without optimizations quicky and then to view the results in the hierarchy view...

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/05c5ded4-19e6-417f-ba74-31c5c64aa6ea)

The area of the instances is 250000um^2. I have been having trouble with 30% placement density, so I'm going to try 20% placement density. What is the relationship with CORE_UTILIZATION and placement density here...?

Make that CORE_UTILIZATION=15

sqrt(2500000/0.15) => 1300um * 1300um

Macro placement and estimated routing congestion for 2000um x 2000um. The macros seem to be pushed out to the corners, let's see how that works out in placement and routing...

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/03f9e101-6a6b-4362-a4f9-f93e142c11dc)

Routing congestion in `make gui_place`. Why is the empty area yellow? Is power considered part of routing congestion?

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/cdef90ba-9366-4046-b86d-7cac7a1d476f)

Estimated routing congestion RUDY. I guess RUDY excludes power?

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/203b5a86-3cd4-4c04-bf80-a0b204e98692)

Clock tree looks good:

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/2363f35c-d12e-44b4-bbbb-5773d25b3426)


Global routing has taken 40000s so far, but it seems to have succeeded:

```
[INFO GRT-0101] Running extra iterations to remove overflow.
[INFO GRT-0197] Via related to pin nodes: 10765900
[INFO GRT-0198] Via related Steiner nodes: 1028317
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 14831285
[INFO GRT-0112] Final usage 3D: 118911097

[INFO GRT-0096] Final congestion report:
Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
M1                   0             0            0.00%             0 /  0 /  0
M2            65189536       19765924           30.32%             0 /  0 /  0
M3            88394705       29035790           32.85%             0 /  0 /  0
M4            65419606       14163760           21.65%             0 /  0 /  0
M5            58863583       8001905           13.59%             0 /  0 /  0
M6            42524107       2674369            6.29%             0 /  0 /  0
M7            52346733        775494            1.48%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total        372738270       74417242           19.97%             0 /  0 /  0

[INFO GRT-0018] Total wirelength: 44969527 um
[INFO GRT-0014] Routed nets: 2043518
Warning: There are 10 input ports missing set_input_delay.
Warning: There are 7 output ports missing set_output_delay.
Warning: There are 323 unclocked register/latch pins.
Warning: There are 4128 unconstrained endpoints.

==========================================================================
global route pre repair design report_design_area
--------------------------------------------------------------------------
Design area 523197 u^2 13% utilization.
Perform buffer insertion...
[INFO RSZ-0058] Using max wire length 162um.
```


Global route heat map:

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/504a1b08-d095-41f1-a8be-6392437eeaf5)


Detailed routing without power:

![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/97c26702-6d81-472a-a79d-e15eb6cf1a9e)


Regarding the long global routing times, I set SKIP_INCREMENTAL_REPAIR=1 in detailed routing, whereas it is a global routing argument. I believe that will take care of the pathologically slow global routing...

```
-                'route': ['SKIP_INCREMENTAL_REPAIR=1'],
+                'grt': ['SKIP_INCREMENTAL_REPAIR=1']
```


```
>>> report_checks -path_delay max
Startpoint: system/prci_ctrl_domain/_853_
            (rising edge-triggered flip-flop clocked by clock_uncore)
Endpoint: system/_185_ (recovery check against rising-edge clock clock_uncore)
Path Group: asynchronous
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock_uncore (rise edge)
1973.50 1973.50   clock network delay (propagated)
   0.00 1973.50 ^ system/prci_ctrl_domain/_853_/CLK (DFFASRHQNx1_ASAP7_75t_R)
  87.72 2061.22 v system/prci_ctrl_domain/_853_/QN (DFFASRHQNx1_ASAP7_75t_R)
  41.86 2103.08 v load_slew185637/Y (BUFx16f_ASAP7_75t_R)
  37.04 2140.12 v max_cap185634/Y (BUFx16f_ASAP7_75t_R)
  36.83 2176.95 v wire185631/Y (BUFx16f_ASAP7_75t_R)
  41.48 2218.44 v wire185630/Y (BUFx16f_ASAP7_75t_R)
  47.39 2265.83 v max_length185629/Y (BUFx16f_ASAP7_75t_R)
  39.69 2305.52 v wire185628/Y (BUFx16f_ASAP7_75t_R)
  81.35 2386.87 v max_length185627/Y (BUFx16f_ASAP7_75t_R)
  29.27 2416.13 v load_slew185625/Y (BUFx16f_ASAP7_75t_R)
  52.11 2468.25 v load_slew185624/Y (BUFx12f_ASAP7_75t_R)
  43.24 2511.49 v load_slew185618/Y (BUFx16f_ASAP7_75t_R)
  50.84 2562.32 v load_slew185615/Y (BUFx16f_ASAP7_75t_R)
  34.35 2596.68 v load_slew185559/Y (BUFx16f_ASAP7_75t_R)
  34.56 2631.24 v load_slew185558/Y (BUFx16f_ASAP7_75t_R)
  26.61 2657.85 v load_slew185557/Y (BUFx16f_ASAP7_75t_R)
  46.26 2704.11 v load_slew185556/Y (BUFx16f_ASAP7_75t_R)
  51.34 2755.46 v max_length185555/Y (BUFx12f_ASAP7_75t_R)
  41.44 2796.90 v wire185553/Y (BUFx16f_ASAP7_75t_R)
  51.64 2848.53 v load_slew185552/Y (BUFx16f_ASAP7_75t_R)
  34.46 2882.99 v wire185550/Y (BUFx16f_ASAP7_75t_R)
  51.12 2934.11 v wire185547/Y (BUFx16f_ASAP7_75t_R)
  64.89 2999.00 v load_slew185546/Y (BUFx16f_ASAP7_75t_R)
  37.84 3036.83 v wire185534/Y (BUFx16f_ASAP7_75t_R)
  88.57 3125.41 v wire185533/Y (BUFx3_ASAP7_75t_R)
  17.20 3142.60 v wire23908/Y (BUFx16f_ASAP7_75t_R)
 103.84 3246.44 v wire185532/Y (BUFx16f_ASAP7_75t_R)
  53.90 3300.35 v load_slew185531/Y (BUFx16f_ASAP7_75t_R)
  35.37 3335.71 v load_slew185522/Y (BUFx16f_ASAP7_75t_R)
  31.13 3366.84 v load_slew185507/Y (BUFx16f_ASAP7_75t_R)
  32.21 3399.06 v wire185505/Y (BUFx16f_ASAP7_75t_R)
  37.17 3436.23 v load_slew185504/Y (BUFx16f_ASAP7_75t_R)
  25.45 3461.69 v load_slew185494/Y (BUFx16f_ASAP7_75t_R)
  25.36 3487.04 v wire185486/Y (BUFx16f_ASAP7_75t_R)
  47.14 3534.18 v wire185485/Y (BUFx16f_ASAP7_75t_R)
  24.87 3559.05 v max_cap185484/Y (BUFx16f_ASAP7_75t_R)
  27.89 3586.94 v wire185483/Y (BUFx3_ASAP7_75t_R)
  16.61 3603.56 v wire19831/Y (BUFx16f_ASAP7_75t_R)
 105.13 3708.69 v wire185481/Y (BUFx3_ASAP7_75t_R)
  18.09 3726.78 v wire19408/Y (BUFx16f_ASAP7_75t_R)
 112.70 3839.48 ^ system/_107_/Y (INVx1_ASAP7_75t_R)
   0.03 3839.51 ^ system/_185_/SETN (DFFASRHQNx1_ASAP7_75t_R)
        3839.51   data arrival time

8500.00 8500.00   clock clock_uncore (rise edge)
1969.03 10469.03   clock network delay (propagated)
 -10.00 10459.03   clock uncertainty
   0.00 10459.03   clock reconvergence pessimism
        10459.03 ^ system/_185_/CLK (DFFASRHQNx1_ASAP7_75t_R)
   0.82 10459.85   library recovery time
        10459.85   data required time
---------------------------------------------------------
        10459.85   data required time
        -3839.51   data arrival time
---------------------------------------------------------
        6620.34   slack (MET)


Startpoint: _32_ (negative level-sensitive latch clocked by clock_uncore)
Endpoint: _10_ (rising clock gating-check end-point clocked by clock_uncore)
Path Group: gated clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
4250.00 4250.00   clock clock_uncore (fall edge)
2156.12 6406.12   clock network delay (propagated)
   0.00 6406.12 v _32_/CLK (DLLx1_ASAP7_75t_R)
  32.10 6438.22 v _32_/Q (DLLx1_ASAP7_75t_R)
   0.01 6438.23 v _10_/B (AND2x4_ASAP7_75t_R)
        6438.23   data arrival time

8500.00 8500.00   clock clock_uncore (rise edge)
1955.45 10455.45   clock network delay (propagated)
 -10.00 10445.45   clock uncertainty
   0.00 10445.45   clock reconvergence pessimism
        10445.45 ^ _10_/A (AND2x4_ASAP7_75t_R)
   0.00 10445.45   clock gating setup time
        10445.45   data required time
---------------------------------------------------------
        10445.45   data required time
        -6438.23   data arrival time
---------------------------------------------------------
        4007.22   slack (MET)


Startpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_
            (rising edge-triggered flip-flop clocked by clock_uncore)
Endpoint: system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_
          (rising edge-triggered flip-flop clocked by clock_uncore)
Path Group: clock_uncore
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock_uncore (rise edge)
1977.51 1977.51   clock network delay (propagated)
   0.00 1977.51 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_/CLK (DFFHQNx2_ASAP7_75t_R)
  97.74 2075.25 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100862_/QN (DFFHQNx2_ASAP7_75t_R)
  26.79 2102.04 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055781_/Y (CKINVDCx20_ASAP7_75t_R)
 123.43 2225.47 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_100818_/CON (HAxp5_ASAP7_75t_R)
  36.21 2261.68 ^ wire155277/Y (BUFx12f_ASAP7_75t_R)
  45.28 2306.96 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055932_/Y (NOR2x2_ASAP7_75t_R)
  28.25 2335.21 v max_length142580/Y (BUFx16f_ASAP7_75t_R)
 104.72 2439.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055933_/Y (NAND2x2_ASAP7_75t_R)
  59.96 2499.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055934_/Y (OA22x2_ASAP7_75t_R)
  36.00 2535.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055951_/Y (AND4x2_ASAP7_75t_R)
  12.14 2548.03 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055963_/Y (NAND3x2_ASAP7_75t_R)
  70.12 2618.15 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_055964_/Y (AOI211x1_ASAP7_75t_R)
  55.95 2674.10 ^ load_slew117489/Y (BUFx12f_ASAP7_75t_R)
  53.80 2727.90 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056077_/Y (AND3x4_ASAP7_75t_R)
  25.58 2753.48 ^ max_length114043/Y (BUFx16f_ASAP7_75t_R)
  32.81 2786.29 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056130_/Y (AND2x6_ASAP7_75t_R)
  14.23 2800.52 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056131_/Y (NAND2x1_ASAP7_75t_R)
  15.55 2816.06 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/rob/_056132_/Y (INVx1_ASAP7_75t_R)
  16.14 2832.21 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09390_/Y (NAND2x2_ASAP7_75t_R)
  28.51 2860.72 v wire99845/Y (BUFx16f_ASAP7_75t_R)
  70.62 2931.33 v wire99844/Y (BUFx16f_ASAP7_75t_R)
  56.99 2988.32 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09404_/Y (OAI21x1_ASAP7_75t_R)
  11.35 2999.67 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09407_/Y (NAND2x1_ASAP7_75t_R)
  44.90 3044.57 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09408_/Y (OR4x2_ASAP7_75t_R)
  57.29 3101.86 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09409_/Y (OR5x2_ASAP7_75t_R)
  39.18 3141.05 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11025_/Y (NOR2x2_ASAP7_75t_R)
  25.42 3166.47 ^ wire85735/Y (BUFx3_ASAP7_75t_R)
  16.09 3182.56 ^ wire22108/Y (BUFx16f_ASAP7_75t_R)
  96.00 3278.56 ^ max_length85734/Y (BUFx12f_ASAP7_75t_R)
  59.41 3337.98 ^ wire85733/Y (BUFx3_ASAP7_75t_R)
  15.95 3353.92 ^ wire21265/Y (BUFx16f_ASAP7_75t_R)
  93.06 3446.99 ^ max_length85732/Y (BUFx16f_ASAP7_75t_R)
  52.88 3499.86 ^ wire85731/Y (BUFx12f_ASAP7_75t_R)
  61.48 3561.34 ^ wire85730/Y (BUFx12f_ASAP7_75t_R)
  94.55 3655.89 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374889_/Y (AND3x4_ASAP7_75t_R)
  93.17 3749.07 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374891_/Y (XNOR2x2_ASAP7_75t_R)
  33.79 3782.85 v max_length80723/Y (BUFx16f_ASAP7_75t_R)
  73.46 3856.31 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715616_/CON (HAxp5_ASAP7_75t_R)
  16.66 3872.97 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374906_/Y (INVx4_ASAP7_75t_R)
  24.46 3897.43 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715614_/CON (HAxp5_ASAP7_75t_R)
  13.62 3911.05 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715583_/Y (INVx1_ASAP7_75t_R)
 101.30 4012.35 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715612_/SN (HAxp5_ASAP7_75t_R)
  45.01 4057.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384513_/Y (XNOR2x1_ASAP7_75t_R)
  28.70 4086.05 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384518_/Y (AND5x2_ASAP7_75t_R)
  31.22 4117.28 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09414_/Y (AO22x2_ASAP7_75t_R)
  32.81 4150.08 v wire55436/Y (BUFx12f_ASAP7_75t_R)
  66.68 4216.77 v wire55435/Y (BUFx12f_ASAP7_75t_R)
  67.25 4284.01 v wire55434/Y (BUFx12f_ASAP7_75t_R)
  66.32 4350.34 v wire55433/Y (BUFx12f_ASAP7_75t_R)
  67.31 4417.65 v wire55432/Y (BUFx12f_ASAP7_75t_R)
  71.71 4489.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09415_/Y (OR4x1_ASAP7_75t_R)
  50.77 4540.13 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09416_/Y (OR5x2_ASAP7_75t_R)
  50.72 4590.86 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09417_/Y (OR5x2_ASAP7_75t_R)
  33.49 4624.35 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11022_/Y (AOI22x1_ASAP7_75t_R)
  26.99 4651.33 ^ load_slew51767/Y (BUFx16f_ASAP7_75t_R)
  59.33 4710.67 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_11023_/Y (AND2x6_ASAP7_75t_R)
  32.05 4742.72 ^ wire50793/Y (BUFx16f_ASAP7_75t_R)
  70.46 4813.18 ^ wire50792/Y (BUFx16f_ASAP7_75t_R)
  57.14 4870.32 ^ max_length50791/Y (BUFx12f_ASAP7_75t_R)
  57.90 4928.22 ^ wire50790/Y (BUFx16f_ASAP7_75t_R)
  89.00 5017.21 ^ wire50789/Y (BUFx16f_ASAP7_75t_R)
  65.37 5082.59 ^ wire50788/Y (BUFx12f_ASAP7_75t_R)
  62.25 5144.84 ^ wire50787/Y (BUFx12f_ASAP7_75t_R)
  73.66 5218.50 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374879_/Y (AND2x2_ASAP7_75t_R)
  30.04 5248.54 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374909_/Y (NAND2x2_ASAP7_75t_R)
  75.54 5324.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374941_/Y (XNOR2x2_ASAP7_75t_R)
  47.25 5371.33 v wire46725/Y (BUFx3_ASAP7_75t_R)
  16.83 5388.16 v wire7813/Y (BUFx16f_ASAP7_75t_R)
  77.75 5465.91 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715634_/CON (HAxp5_ASAP7_75t_R)
  20.02 5485.92 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_374961_/Y (INVx4_ASAP7_75t_R)
  27.92 5513.84 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715636_/CON (HAxp5_ASAP7_75t_R)
  14.52 5528.36 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715578_/Y (INVx1_ASAP7_75t_R)
 110.73 5639.08 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715638_/SN (HAxp5_ASAP7_75t_R)
  46.55 5685.64 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384519_/Y (XNOR2x1_ASAP7_75t_R)
  41.02 5726.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384524_/Y (AND5x2_ASAP7_75t_R)
  63.15 5789.80 v wire30208/Y (BUFx12f_ASAP7_75t_R)
  83.85 5873.65 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09398_/Y (AO221x2_ASAP7_75t_R)
  31.18 5904.83 v wire29780/Y (BUFx12f_ASAP7_75t_R)
  67.42 5972.25 v wire29779/Y (BUFx12f_ASAP7_75t_R)
  66.73 6038.98 v wire29778/Y (BUFx12f_ASAP7_75t_R)
  66.08 6105.06 v wire29777/Y (BUFx12f_ASAP7_75t_R)
  99.39 6204.45 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09399_/Y (OR4x2_ASAP7_75t_R)
  52.91 6257.36 v wire29446/Y (BUFx12f_ASAP7_75t_R)
  74.94 6332.30 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09400_/Y (OR3x2_ASAP7_75t_R)
  11.77 6344.06 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13817_/Y (NOR2x1_ASAP7_75t_R)
  36.79 6380.86 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13818_/Y (AND3x4_ASAP7_75t_R)
  22.16 6403.01 ^ wire29198/Y (BUFx3_ASAP7_75t_R)
  16.12 6419.13 ^ wire4813/Y (BUFx16f_ASAP7_75t_R)
  79.70 6498.83 ^ wire29197/Y (BUFx3_ASAP7_75t_R)
  17.06 6515.89 ^ wire4798/Y (BUFx16f_ASAP7_75t_R)
 110.37 6626.27 ^ wire29196/Y (BUFx3_ASAP7_75t_R)
  17.81 6644.08 ^ wire4769/Y (BUFx16f_ASAP7_75t_R)
  71.73 6715.81 ^ wire29195/Y (BUFx12f_ASAP7_75t_R)
  63.73 6779.54 ^ wire29194/Y (BUFx16f_ASAP7_75t_R)
  82.80 6862.34 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380843_/Y (AND3x4_ASAP7_75t_R)
  80.15 6942.49 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380845_/Y (XNOR2x2_ASAP7_75t_R)
  40.14 6982.63 v wire24381/Y (BUFx3_ASAP7_75t_R)
  16.96 6999.59 v wire4637/Y (BUFx16f_ASAP7_75t_R)
 169.90 7169.49 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715676_/CON (HAxp5_ASAP7_75t_R)
  22.93 7192.41 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_380978_/Y (INVx5_ASAP7_75t_R)
  39.12 7231.53 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715678_/CON (HAxp5_ASAP7_75t_R)
  17.36 7248.89 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715581_/Y (INVx1_ASAP7_75t_R)
 139.72 7388.61 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_715680_/SN (HAxp5_ASAP7_75t_R)
  46.63 7435.24 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384526_/Y (XNOR2x1_ASAP7_75t_R)
  43.35 7478.59 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_384530_/Y (AND5x2_ASAP7_75t_R)
  21.89 7500.48 ^ wire14553/Y (BUFx16f_ASAP7_75t_R)
  60.38 7560.86 ^ wire14552/Y (BUFx12f_ASAP7_75t_R)
  78.29 7639.15 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09424_/Y (AO221x2_ASAP7_75t_R)
  46.92 7686.07 ^ wire14505/Y (BUFx12f_ASAP7_75t_R)
  61.68 7747.74 ^ wire14504/Y (BUFx12f_ASAP7_75t_R)
  63.66 7811.41 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09425_/Y (OR4x2_ASAP7_75t_R)
  18.88 7830.29 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/core/_09426_/Y (OA21x2_ASAP7_75t_R)
   9.19 7839.48 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13964_/Y (NOR2x1_ASAP7_75t_R)
  32.41 7871.89 v system/tile_prci_domain/tile_reset_domain_boom_tile/core/_13965_/Y (AND3x4_ASAP7_75t_R)
  21.83 7893.72 v wire14423/Y (BUFx3_ASAP7_75t_R)
  16.60 7910.32 v wire2687/Y (BUFx16f_ASAP7_75t_R)
  76.26 7986.58 v wire14422/Y (BUFx3_ASAP7_75t_R)
  17.63 8004.21 v wire2673/Y (BUFx16f_ASAP7_75t_R)
  92.08 8096.29 v max_length14421/Y (BUFx16f_ASAP7_75t_R)
  48.26 8144.55 v wire14420/Y (BUFx12f_ASAP7_75t_R)
  65.64 8210.20 v wire14419/Y (BUFx12f_ASAP7_75t_R)
  78.20 8288.39 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_462481_/Y (AND2x2_ASAP7_75t_R)
  32.72 8321.11 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_462482_/Y (NAND2x2_ASAP7_75t_R)
  51.65 8372.77 ^ wire13868/Y (BUFx16f_ASAP7_75t_R)
  93.74 8466.51 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_463033_/Y (OR2x6_ASAP7_75t_R)
  66.52 8533.02 ^ wire13185/Y (BUFx16f_ASAP7_75t_R)
 125.00 8658.02 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_469024_/Y (NOR2x2_ASAP7_75t_R)
  73.88 8731.90 v wire7777/Y (BUFx16f_ASAP7_75t_R)
 117.54 8849.44 v system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_477305_/Y (OR3x4_ASAP7_75t_R)
  46.53 8895.97 v wire2121/Y (BUFx3_ASAP7_75t_R)
  16.26 8912.24 v wire1767/Y (BUFx16f_ASAP7_75t_R)
 100.49 9012.73 v max_length2120/Y (BUFx16f_ASAP7_75t_R)
  62.86 9075.59 v max_length2119/Y (BUFx16f_ASAP7_75t_R)
  21.06 9096.65 v wire2118/Y (BUFx16f_ASAP7_75t_R)
  76.88 9173.53 v max_length2117/Y (BUFx16f_ASAP7_75t_R)
  36.80 9210.33 v wire2116/Y (BUFx16f_ASAP7_75t_R)
  83.84 9294.17 v wire2115/Y (BUFx16f_ASAP7_75t_R)
 105.13 9399.30 v wire2101/Y (BUFx16f_ASAP7_75t_R)
  95.85 9495.16 v wire2100/Y (BUFx16f_ASAP7_75t_R)
  52.35 9547.50 v max_length2099/Y (BUFx16f_ASAP7_75t_R)
  38.11 9585.61 v wire2098/Y (BUFx3_ASAP7_75t_R)
  16.02 9601.62 v wire113/Y (BUFx16f_ASAP7_75t_R)
 127.64 9729.27 v max_length2096/Y (BUFx16f_ASAP7_75t_R)
  47.57 9776.84 v wire2094/Y (BUFx3_ASAP7_75t_R)
  16.12 9792.96 v wire70/Y (BUFx16f_ASAP7_75t_R)
 103.02 9895.98 v max_length2093/Y (BUFx16f_ASAP7_75t_R)
  51.33 9947.30 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_521833_/Y (NOR2x1_ASAP7_75t_R)
  14.62 9961.93 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_521834_/Y (AO21x1_ASAP7_75t_R)
   0.01 9961.94 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_/D (DFFHQNx2_ASAP7_75t_R)
        9961.94   data arrival time

8500.00 8500.00   clock clock_uncore (rise edge)
1952.03 10452.03   clock network delay (propagated)
 -10.00 10442.03   clock uncertainty
   0.00 10442.03   clock reconvergence pessimism
        10442.03 ^ system/tile_prci_domain/tile_reset_domain_boom_tile/lsu/_719555_/CLK (DFFHQNx2_ASAP7_75t_R)
  -6.09 10435.94   library setup time
        10435.94   data required time
---------------------------------------------------------
        10435.94   data required time
        -9961.94   data arrival time
---------------------------------------------------------
         474.00   slack (MET)


Startpoint: system/serial_tl_domain/_1267_
            (rising edge-triggered flip-flop clocked by serial_tl_0_clock)
Endpoint: system/serial_tl_domain/_1188_
          (rising edge-triggered flip-flop clocked by serial_tl_0_clock)
Path Group: serial_tl_0_clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock serial_tl_0_clock (rise edge)
  48.42   48.42   clock network delay (propagated)
   0.00   48.42 ^ system/serial_tl_domain/_1267_/CLK (DFFASRHQNx1_ASAP7_75t_R)
 130.15  178.57 ^ system/serial_tl_domain/_1267_/QN (DFFASRHQNx1_ASAP7_75t_R)
  69.41  247.98 v system/serial_tl_domain/_0676_/Y (NOR2x2_ASAP7_75t_R)
  39.09  287.06 v system/serial_tl_domain/_0823_/Y (AND2x4_ASAP7_75t_R)
  22.08  309.14 ^ system/serial_tl_domain/_1128_/CON (HAxp5_ASAP7_75t_R)
   9.17  318.32 v system/serial_tl_domain/_1125_/Y (INVx1_ASAP7_75t_R)
  13.54  331.85 ^ system/serial_tl_domain/_1129_/CON (HAxp5_ASAP7_75t_R)
   8.88  340.73 v system/serial_tl_domain/_1123_/Y (INVx1_ASAP7_75t_R)
  83.77  424.51 v system/serial_tl_domain/_1130_/SN (HAxp5_ASAP7_75t_R)
  41.84  466.35 v load_slew119094/Y (BUFx10_ASAP7_75t_R)
  24.78  491.13 v system/serial_tl_domain/_0863_/Y (AND2x2_ASAP7_75t_R)
  19.53  510.67 v system/serial_tl_domain/_0864_/Y (AND2x2_ASAP7_75t_R)
  23.33  534.00 v system/serial_tl_domain/_0866_/Y (AO32x1_ASAP7_75t_R)
  49.05  583.05 v system/serial_tl_domain/_0870_/Y (OR5x2_ASAP7_75t_R)
  22.11  605.16 v system/serial_tl_domain/_0872_/Y (OA22x2_ASAP7_75t_R)
   0.01  605.17 v system/serial_tl_domain/_1188_/D (DFFHQNx2_ASAP7_75t_R)
         605.17   data arrival time

8500.00 8500.00   clock serial_tl_0_clock (rise edge)
  47.57 8547.57   clock network delay (propagated)
 -10.00 8537.57   clock uncertainty
   0.00 8537.57   clock reconvergence pessimism
        8537.57 ^ system/serial_tl_domain/_1188_/CLK (DFFHQNx2_ASAP7_75t_R)
  -4.26 8533.31   library setup time
        8533.31   data required time
---------------------------------------------------------
        8533.31   data required time
        -605.17   data arrival time
---------------------------------------------------------
        7928.14   slack (MET)

```

```
>>> report_clock_min_period
clock_uncore period_min = 8026.00 fmax = 124.60
serial_tl_0_clock period_min = 571.86 fmax = 1748.67
```

```
$ ./orfs make FLOW_VARIANT=flat elapsed
Log                       Elapsed seconds
1_1_yosys                       4057
1_1_yosys_hier_report           4063
2_1_floorplan                    393
2_2_floorplan_io                  12
No elapsed time found in bazel-bin/logs/asap7/ChipTop/flat/2_3_floorplan_tdms.log
2_4_floorplan_macro             1817
2_5_floorplan_tapcell            678
2_6_floorplan_pdn                580
3_1_place_gp_skip_io             877
3_2_place_iop                     38
3_3_place_gp                    7678
3_4_place_resized               1341
3_5_place_dp                    1934
4_1_cts                        12699
5_1_grt                        68906
5_2_fillcell                     143
5_3_route                      20911
6_1_merge                        556
6_report                        7928
generate_abstract               1166
Total                         135777
```


### oharboe
@gudeh Any idea why the colors are so different for estimated and actual routing congestion? The estimate appears to give a very similar looking image, but why is the actual estimated congestion different?

### rovinski
@oharboe Just a thought, have you properly constrained the async FIFO in SDC? I found this line https://github.com/The-OpenROAD-Project/megaboom/blob/1cce55c772d823ebca0bf8368f1d363a2e546044/constraints-chiptop.sdc#L13. I'm not sure if this covers the async FIFO or not. This would be okay for design space exploration, but for a real implementation it isn't sufficient. See [this very good guide](https://gist.github.com/brabect1/7695ead3d79be47576890bbcd61fe426).

### oharboe
Regarding the very long global routing times. The global routing is actually fast, it is incremental repair and [reporting times](https://github.com/The-OpenROAD-Project/OpenROAD/issues/4533) that are slow.