flipflop + inverter + rebuffer + output buffer
Tool: Clock Tree Synthesis
Subcategory: Unexpected optimization
Conversation
oharboe
Is the "rebuffer" buffer superfluous here?
The "rebuffer" buffer does not exist in placement, only after CTS.
make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_final:
make DESIGN_CONFIG=designs/asap7/mock-array/Element/config.mk gui_place:
maliberty
It is there for timing optimization as the path has negative slack which is addressed post-CTS. Is there a reason to think it superfluous?
oharboe
No extra buffers after removing set_load -pin_load 10 [all_outputs]:
Untar cts-nobuffer.tar.gz
$ ./run-me-mock-array_Element-asap7-base.sh
OpenROAD v2.0-12488-g85f541bb6
openroad> report_checks -to io_lsbOuts_7
Startpoint: _755_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_lsbOuts_7 (output port clocked by clock_vir)
Path Group: clock_vir
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clock (rise edge)
74.98 74.98 clock network delay (propagated)
0.00 74.98 ^ _755_/CLK (DFFHQNx2_ASAP7_75t_R)
45.97 120.95 v _755_/QN (DFFHQNx2_ASAP7_75t_R)
13.06 134.01 ^ _435_/Y (INVx4_ASAP7_75t_R)
18.04 152.05 ^ output265/Y (BUFx2_ASAP7_75t_R)
0.01 152.06 ^ io_lsbOuts_7 (out)
152.06 data arrival time
300.00 300.00 clock clock_vir (rise edge)
70.00 370.00 clock network delay (ideal)
-20.00 350.00 clock uncertainty
0.00 350.00 clock reconvergence pessimism
-240.00 110.00 output external delay
110.00 data required time
---------------------------------------------------------
110.00 data required time
-152.06 data arrival time
---------------------------------------------------------
-42.06 slack (VIOLATED)
maliberty
How do I stop "don't touch" from removing the output buffer so I get the comparison I'm after?
Set don't touch after the output buffer is created.
If I delete set_load -pin_load 10 [all_outputs], the extra buffer goes away.
Probably the timing improves and the net no longer needs repair. Similarly with the set_driving_cell changing the timing.