Router violation with proprietary PDK
Tool: Detailed Routing
Subcategory: Routing violations
Conversation
sebinho
Hi Guys,
I am posting here regarding an issue I am struggling with regarding the detailed routing of OR. I am using a proprietary PDK, so it is difficult for me to share a complete example of the issue.
I am constantly running into metal spacing violations on M1 with my 45nm PDK. I systematically get the same error, typically on the same net(s). Because of that, the router always goes up to the max number of iterations (64) and never finds a solution. Here is a snapshot of the issue at hand.
You can see on the bottom orange rectangle (this is a VIA between M1 and M2), that the metal spacing is 0.06um. This violates the metal spacing rule of 0.07. M1 is in dark blue. You can see M2 in cyan in the picture below.
What I noticed is that the routing tool is able to select between 2 types of vias (on its own). Sometimes he selects a horizontal via (like the one that is problematic) and sometimes he takes a vertical via (like the one show in the upper part of the image where the 0.07um rule is respected). The solution to the problem is quite straightforward when done manually. Simply replace the problematic via with its vertical version. But somehow the tool cannot see that.
Is there something that can be done for such an issue @maliberty ? I understand that it is not easy to debug as I cannot share my PDK . Apologies for that. Thanks for your help.
maliberty
You said to goes to 64 iterations. Does drt report these violation itself or are they only seen by another drc tool?
Precision Innovations does provide paid support under NDA if that makes sense for you.
@osamahammad21 any thoughts?
maliberty
Does the drc straddle the boundary of two different cells? (ie the pins are in different instances)
sebinho
I reran the tool with different settings and 1 get 1 violation for metal spacing. It is a different location in my design but once again it seems to be at the boundary between 2 different cells. See below red line for separation.
Any clue how this could be solved? Thanks a lot
sebinho
@maliberty do you have any recommendations on where to look first in order to speed up the routing for a proprietary PDK? Now that I added an extra layer of complexity (custom DEF file to specify core/die size and pins locations, custom power grid), it often crash due to not being able to access pins. Or it takes forever to eventually not solve all violations. Should I incrementally try to simplify the technology (.LEF) file? Any other things I should look into? My test design (very small module) goes through Sky130/freepdk45 in a matter of minutes even with a very similar DEF file and power grid… Thanks for your help
maliberty
Should I have the assumption that it is possible to port any rules deck with OpenROAD?
That's probably too strong a statement (eg we don't support all rules below 12nm) but for older nodes it should be possible. More rules certainly will slow down the router if they make it more difficult to find legal solutions.
@osamahammad21 am I correct in thinkin we support ADJACENTCUTS / WITHIN?