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--- |
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title: bench_verilog(2) |
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date: 24/09/08 |
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--- |
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# NAME |
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bench_verilog - bench verilog |
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# SYNOPSIS |
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bench_verilog |
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[filename] |
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# DESCRIPTION |
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`bench_verilog` is used after the `bench_wires` command. This command |
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generates a Verilog netlist of the generated pattern layout by the `bench_wires` |
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command. |
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This command is optional when running the Extraction Rules generation |
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flow. This step is required if the favorite extraction tool (i.e., reference |
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extractor) requires a Verilog netlist to extract parasitics of the pattern layout. |
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# OPTIONS |
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`filename`: Name for the Verilog output file (e.g., `output.v`). |
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# ARGUMENTS |
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This command has no arguments. |
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# EXAMPLES |
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# SEE ALSO |
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