repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_Color_Space_Converter.v | 8,845 | module MODULE1 (
clk,
reset,
VAR12,
VAR20,
VAR13,
VAR8,
VAR15,
VAR5,
VAR35,
VAR23,
VAR29,
VAR3,
VAR21,
VAR32
);
parameter VAR14 = 23;
parameter VAR34 = 23;
parameter VAR18 = 1;
parameter VAR24 = 1;
input clk;
input reset;
input [VAR14: 0] VAR12;
input VAR20;
input VAR13;
input [VAR18:0] VAR8;
input VAR15;
input VAR5;
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.behavioral.v | 1,643 | module MODULE1 (
VAR12 ,
VAR13,
VAR2,
VAR8,
VAR1,
VAR9
);
output VAR12 ;
input VAR13;
input VAR2;
input VAR8;
input VAR1;
input VAR9;
supply1 VAR6;
supply0 VAR16;
supply1 VAR14 ;
supply0 VAR7 ;
wire VAR10 ;
wire VAR17 ;
wire VAR11;
nor VAR15 (VAR10 , VAR8, VAR13, VAR2 );
nor VAR3 (VAR17 , VAR1, VAR9 );
or VAR4 (VAR11, ... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_dmmu_tlb.v | 10,550 | module MODULE1(
clk, rst,
VAR27, VAR3, VAR38, VAR17, VAR37, VAR18, VAR32, VAR21, VAR26,
VAR22, VAR42, VAR49,
VAR10, VAR25, VAR13, VAR7, VAR29
);
parameter VAR50 = VAR54;
parameter VAR33 = VAR54;
input clk;
input rst;
input VAR27;
input [VAR33-1:0] VAR3;
output VAR38;
output [31:VAR6] VAR17;
output VAR37;
output VAR18;
... | gpl-2.0 |
kevintownsend/R3 | coregen/fifo_fwft_64x1024.v | 37,604 | module MODULE1 (
clk, VAR101, rst, VAR43, VAR164, VAR161, VAR77, dout, din
);
input clk;
input VAR101;
input rst;
output VAR43;
input VAR164;
output VAR161;
output VAR77;
output [63 : 0] dout;
input [63 : 0] din;
wire VAR94;
wire VAR53;
wire \VAR61/VAR136/VAR80.VAR54/VAR130.VAR76/VAR152/VAR28 ;
wire \VAR61/VAR136/VAR80... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.functional.pp.v | 1,069 | module MODULE1( VAR1, VAR3, VAR9, VAR12, VAR8, VAR10 );
input VAR12, VAR3, VAR9;
inout VAR8, VAR10;
output VAR1;
wire VAR5;
and VAR7( VAR5, VAR12, VAR3 );
wire VAR11;
not VAR14( VAR11, VAR9 );
wire VAR6;
and VAR2( VAR6, VAR11, VAR12 );
wire VAR13;
and VAR15( VAR13, VAR3, VAR9 );
or VAR4( VAR1, VAR5, VAR6, VAR13 );
endm... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_rx/MAC_rx_FF.v | 25,298 | module MODULE1 (
VAR27 ,
VAR80 ,
VAR30 ,
VAR26 ,
VAR21 ,
VAR91 ,
VAR62 ,
VAR16 ,
VAR87,
VAR94,
VAR45,
VAR74 ,
VAR35 ,
VAR13 ,
VAR41 ,
VAR82 ,
VAR59,
VAR86
);
input VAR27 ;
input VAR80 ;
input VAR30 ;
input [7:0] VAR26 ;
input VAR21 ;
output VAR91 ;
input VAR62 ;
input VAR16 ;
input VAR45 ;
input [4:0] VAR87 ;
input [4:... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v | 35,319 | module MODULE1 (
output wire VAR40, input wire VAR128, output wire VAR180, output wire [31:0] VAR15, output wire VAR247, input wire [0:0] VAR187, input wire [31:0] VAR129, input wire [10:0] VAR152, input wire VAR111, input wire VAR239, input wire [3:0] VAR149, input wire VAR242, output wire VAR202, output wire VAR51, i... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_sort_stable.v | 2,120 | module MODULE1 #(parameter VAR1(VAR6),
VAR3 = "VAR5"
, VAR7 = VAR6-1
, VAR2 = 0
)
(input [VAR6-1:0] VAR8 [VAR3-1:0]
, output [VAR6-1:0] VAR4 [VAR3-1:0]
); | bsd-3-clause |
omicronns/studies-sys-rek | de1-soc/src/delayLine/delayLine.v | 1,302 | module MODULE1 #(
parameter VAR8 = 0,
parameter VAR1 = 8
)(
input VAR6,
input rst,
input clk,
input [VAR1 - 1:0] in,
output [VAR1 - 1:0] out
);
wire [VAR1 - 1:0] VAR5 [VAR8:0];
assign VAR5[0] = in;
assign out = VAR5[VAR8];
genvar VAR3;
generate
for(VAR3 = 0; VAR3 < VAR8; VAR3 = VAR3 + 1)
begin : VAR7
VAR4 #(
.VAR1(VAR1... | mit |
maijohnson/comp3601_blue_15s2 | AudioController/sin_lut.v | 2,182 | module MODULE1 (input [5:0] VAR2, output [7:0] VAR1);
assign VAR1 = (VAR2 == 6'd0) ? 128 :
(VAR2 == 6'd1) ? 140 :
(VAR2 == 6'd2) ? 152 :
(VAR2 == 6'd3) ? 165 :
(VAR2 == 6'd4) ? 176 :
(VAR2 == 6'd5) ? 188 :
(VAR2 == 6'd6) ? 198 :
(VAR2 == 6'd7) ? 208 :
(VAR2 == 6'd8) ? 218 :
(VAR2 == 6'd9) ? 226 :
(VAR2 == 6'd10) ? 234 ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/medfifo.v | 2,116 | module MODULE1
parameter VAR14=1)
(input clk, input rst,
input [VAR2-1:0] VAR4,
output [VAR2-1:0] VAR12,
input read,
input write,
input VAR6,
output VAR15,
output VAR10,
output [7:0] VAR9,
output [7:0] VAR5);
localparam VAR16 = (1<<VAR14);
wire [VAR2-1:0] dout [0:VAR16-1];
wire [0:VAR16-1] VAR13;
wire [0:VAR16-1] VAR11... | gpl-2.0 |
martinmiranda14/Digitales | Lab_6/Lab_6_prev1.srcs/sources_1/new/clock_divider.v | 1,122 | module MODULE1(
input clk,
input rst,
output reg VAR2
);
localparam VAR1 = 100000;
reg [63:0] VAR3;
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'b1)
VAR3 <= 32'd0;
end
else if (VAR3 == (VAR1 - 32'd1))
VAR3 <= 32'd0;
else
VAR3 <= VAR3 + 32'b1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst == 1'... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_2.behavioral.pp.v | 2,375 | module MODULE1( VAR8, VAR6, VAR4, VAR3, VAR7, VAR5, VAR9 );
input VAR7, VAR3, VAR6, VAR8;
inout VAR5, VAR9;
output VAR4;
VAR2 VAR10(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9));
VAR2 VAR1(.VAR8(VAR8),.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR9(VAR9)); | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_controller_phy.v | 15,072 | module MODULE1 (
VAR96,
VAR130,
VAR171,
VAR33,
VAR1,
VAR94,
VAR24,
VAR38,
VAR30,
VAR163,
VAR59,
VAR83,
VAR144,
VAR70,
VAR168,
VAR61,
VAR79,
VAR40,
VAR39,
VAR62,
VAR100,
VAR166,
VAR146,
VAR118,
VAR99,
VAR120,
VAR64,
VAR78,
VAR3,
VAR50,
VAR42,
VAR88,
VAR27,
VAR119,
VAR95,
VAR149,
VAR150,
VAR52,
VAR129,
VAR173,
VAR123,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_hs__udp_dff_nr_pp_pkg_s.symbol.v | 1,498 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR3 ,
input VAR4 ,
input VAR5,
input VAR2 ,
input VAR8 ,
input VAR6
);
endmodule | apache-2.0 |
davidjabon/Verilog | Binary_to_BCD/binary_to_BCD_eight_bit.v | 1,186 | module MODULE1(
input [7:0] in,
output [3:0] VAR4,
output [3:0] VAR22,
output [1:0] VAR10
);
wire [3:0] VAR13,VAR2,VAR18,VAR21,VAR19,VAR11,VAR12;
wire [3:0] VAR23,VAR16,VAR14,VAR3,VAR7,VAR5,VAR20;
assign VAR23 = {1'b0,in[7:5]};
assign VAR16 = {VAR13[2:0],in[4]};
assign VAR14 = {VAR2[2:0],in[3]};
assign VAR3 = {1'b0,VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.pp.blackbox.v | 1,289 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR2,
VAR1,
VAR7,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR7;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR9 ,
input VAR7 ,
input VAR6 ,
input VAR4 ,
output VAR1 ,
input VAR2 ,
input VAR3,
input VAR5,
input VAR8
);
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_rank_timer.v | 112,499 | module MODULE1 #
( parameter
VAR128 = 2,
VAR107 = 4,
VAR213 = "VAR125",
VAR40 = 1,
VAR126 = 1,
VAR203 = 4,
VAR189 = 2,
VAR169 = 0,
VAR9 = 0,
VAR174 = 5,
VAR14 = 0,
VAR192 = 0,
VAR159 = 0,
VAR10 = 0,
VAR101 = 0,
VAR206 = 0,
VAR96 = 0,
VAR187 = 0,
VAR133 = 0,
VAR6 = 0,
VAR4 = 0,
VAR53 = 0
)
(
VAR20,
VAR61,
VAR179,
VAR87,... | gpl-3.0 |
jotego/jt12 | hdl/jt12_div.v | 4,421 | module MODULE1(
input rst,
input clk,
input VAR15 ,
input [1:0] VAR11,
output reg VAR25, output reg VAR2, output reg VAR17,
output reg VAR20, output reg VAR27, output reg VAR24 );
parameter VAR22=0;
reg [3:0] VAR23, VAR14=4'd0;
reg [2:0] VAR26, VAR28=3'd0;
reg [4:0] VAR13 = 5'd0;
reg [2:0] VAR9 = 3'd0, VAR10=3'd0;
reg ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.behavioral.v | 1,098 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR4 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
plindstroem/oh | elink/dv/dv_elink.v | 37,978 | module MODULE1(
VAR325, VAR160, VAR184, VAR288, VAR103,
VAR128,
clk, reset, VAR280, VAR19, VAR146, VAR121
);
parameter VAR287 = 32;
parameter VAR307 = 32;
parameter VAR141 = 2; parameter VAR243 = 12;
parameter VAR72 = 6;
parameter VAR183 = 12;
parameter VAR327 = 104;
input clk; input reset; output VAR325; output VAR160... | gpl-3.0 |
secworks/ChaCha20-Poly1305 | src/behave/poly13015.v | 5,487 | module MODULE1();
reg [127 : 0] VAR12;
reg [127 : 0] VAR6;
reg [129 : 0] VAR11;
reg [127 : 0] VAR3;
localparam VAR2 = 128'h0ffffffc0ffffffc0ffffffc0fffffff;
localparam VAR15 = 130'h3fffffffffffffffffffffffffffffffb;
task VAR10(input [255 : 0] VAR14);
begin : VAR10
VAR12 = VAR14[255 : 128] & VAR2;
VAR6 = VAR14[127 : 0];... | bsd-2-clause |
duttondj/DigitalDesignI-P4 | keypressed.v | 3,489 | module MODULE1(VAR2, reset, VAR1, VAR5);
input VAR2; input reset; input VAR1; output VAR5;
reg [1:0] VAR7, VAR3;
reg VAR5;
parameter [1:0] VAR6 = 2'b00, VAR4 = 2'b01, VAR9 = 2'b10;
always @(posedge VAR2 or negedge reset) begin
if (reset == 1'b0)
VAR7 <= VAR6;
end
else
VAR7 <= VAR3;
end
always @(VAR7, VAR1) begin
VAR3 =... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9671/axi_ad9671_if.v | 9,247 | module MODULE1 (
VAR57,
VAR24,
VAR45,
VAR44,
VAR8,
VAR34,
VAR43,
VAR40,
VAR46,
VAR2,
VAR36,
VAR53,
VAR15,
VAR23,
VAR21,
VAR4,
VAR47,
VAR26,
VAR3,
VAR31,
VAR59,
VAR37,
VAR20,
VAR48,
VAR35,
VAR58,
VAR5,
VAR27,
VAR28,
VAR19);
parameter VAR51 = 1;
parameter VAR13 = 0;
input VAR57;
input VAR24;
input [(64*VAR51)+63:0] VAR45... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.blackbox.v | 1,322 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR6;
supply1 VAR9;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_1.behavioral.pp.v | 3,847 | module MODULE1( VAR27, VAR17, VAR16, VAR1, VAR14, VAR28 );
input VAR27, VAR17, VAR16;
inout VAR14, VAR28;
output VAR1;
reg VAR12;
VAR24 VAR2(.VAR27(VAR27),.VAR17(VAR17),.VAR16(VAR16),.VAR1(VAR1),.VAR14(VAR14),.VAR28(VAR28),.VAR12(VAR12));
VAR24 VAR29(.VAR27(VAR27),.VAR17(VAR17),.VAR16(VAR16),.VAR1(VAR1),.VAR14(VAR14),.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi_1.v | 2,439 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR11 ,
VAR7 ,
VAR8,
VAR6,
VAR12 ,
VAR4
);
output VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR11 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR12 ;
input VAR4 ;
VAR3 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VA... | apache-2.0 |
spesialstyrker/boula | gen/PCIe/example_design/PIO_EP.v | 8,387 | module MODULE1 #(
parameter VAR25 = 64,
parameter VAR2 = VAR25 / 8 ) (
input clk,
input VAR5,
input VAR67,
output [VAR25-1:0] VAR71,
output [VAR2-1:0] VAR62,
output VAR57,
output VAR47,
output VAR24,
input [VAR25-1:0] VAR20,
input [VAR2-1:0] VAR7,
input VAR78,
input VAR85,
output VAR35,
input [21:0] VAR45,
output VAR82... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.functional.pp.v | 1,994 | module MODULE1 (
VAR15 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR1,
VAR9,
VAR5 ,
VAR14
);
output VAR15 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR9;
input VAR5 ;
input VAR14 ;
wire VAR6 ;
wire VAR13 ;
wire VAR16;
and VAR10 (VAR6 , VAR4, VAR3 );
or VAR2 (VAR13 , VAR6, VAR7 );
VAR8 VAR12 (VAR16, VAR13, VAR1, VAR9);
bu... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_rcv_dc.v | 1,489 | module MODULE1 (
VAR3,
VAR1, ref, VAR2
);
output VAR3;
input VAR1;
input ref;
input VAR2;
assign VAR3 = VAR1 ;
endmodule | gpl-2.0 |
alexforencich/verilog-ethernet | example/VCU108/fpga_1g/rtl/fpga.v | 9,788 | module MODULE1 (
input wire VAR60,
input wire VAR117,
input wire reset,
input wire VAR64,
input wire VAR75,
input wire VAR115,
input wire VAR15,
input wire VAR126,
input wire [3:0] VAR90,
output wire [7:0] VAR36,
input wire VAR110,
input wire VAR106,
output wire VAR40,
output wire VAR85,
input wire VAR94,
input wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_pwrgood_pp_pg/sky130_fd_sc_hs__udp_pwrgood_pp_pg.symbol.v | 1,332 | module MODULE1 (
input VAR3 ,
output VAR4,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/acquire/fifo_control.v | 7,900 | module MODULE1
parameter VAR25 = VAR20-2,
parameter VAR24 = VAR20-1,
parameter VAR14 = 3)
(
input VAR33,
input VAR9,
input VAR13,
input VAR19,
output [8:0] VAR7,
output [8:0] VAR15,
input [23:0] VAR27,
input VAR1,
input VAR18,
output reg VAR21 = 1'b0,
output reg VAR10 = 1'b0,
output reg [VAR25:0] VAR11 = {VAR24{1'b0}},... | lgpl-3.0 |
fredmorcos/attic | projects/vo-tools/archive/machine2graph-3/machines/sbn-dia/sbn.v | 3,296 | module MODULE1 (clk, state, VAR4, VAR24, VAR7);
parameter VAR26 = 8; parameter VAR2 = 32;
input clk;
output [2:0] state;
output [VAR26-1:0] VAR4;
output [VAR2-1:0] VAR24, VAR7;
parameter VAR6 = 4 * VAR26;
reg [VAR6-1:0] VAR13[0:((1<<VAR26)-1)];
reg [VAR2-1:0] VAR15[0:((1<<VAR26)-1)];
reg [VAR2-1:0] VAR8, VAR5;
reg [VAR... | isc |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/ps2/verilog/ps2.v | 13,492 | module MODULE1(
input wire VAR36, input wire VAR8,
output wire [7:0] VAR38, input wire [7:0] VAR25, input wire VAR44, input wire VAR29, output wire VAR3, output wire VAR19,
output wire VAR45, output wire VAR26, output wire VAR6, inout wire VAR47,
output wire VAR4,
inout wire VAR49, inout wire VAR40 );
parameter [2:0]
V... | gpl-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_rfram_generic.v | 8,110 | module MODULE1(
clk, rst,
VAR17, VAR10, VAR12,
VAR9, VAR7, VAR13,
VAR11, VAR1, VAR3, VAR8
);
parameter VAR16 = VAR5;
parameter VAR14 = VAR6;
input clk;
input rst;
input VAR17;
input [VAR14-1:0] VAR10;
output [VAR16-1:0] VAR12;
input VAR9;
input [VAR14-1:0] VAR7;
output [VAR16-1:0] VAR13;
input VAR11;
input VAR1;
input ... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6434ae5eac7e244d/zqynq_lab_1_design_xbar_1_stub.v | 3,660 | module MODULE1(VAR4, VAR19, VAR2, VAR39,
VAR20, VAR26, VAR34, VAR10, VAR9, VAR37,
VAR35, VAR13, VAR23, VAR5, VAR1, VAR27,
VAR29, VAR24, VAR3, VAR33, VAR25, VAR36,
VAR38, VAR11, VAR18, VAR17, VAR15, VAR28,
VAR21, VAR8, VAR32, VAR40, VAR12, VAR30,
VAR16, VAR7, VAR6, VAR22, VAR14, VAR31)
;
input VAR4;
input VAR19;
input [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp_1.v | 2,170 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR9,
VAR4,
VAR2,
VAR5 ,
VAR6
);
output VAR3 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8 ,
VAR9
);
output VAR3 ;... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/md_top.v | 5,783 | module MODULE1(
clk,
VAR15,
enable,
VAR51,
VAR19,
VAR41,
VAR49,
VAR61,
VAR44,
VAR30
);
parameter VAR43=21;
parameter VAR25=0;
input clk;
input VAR15;
input enable;
input [31:0] VAR51;
output VAR30;
output VAR19;
output [3:0] VAR41;
output [5:0] VAR49;
output [5:0] VAR61;
output [5:0] VAR44;
wire VAR30;
wire [3:0] VAR41... | gpl-3.0 |
infiniteNOP/nopCPU | control_unit.v | 8,008 | module MODULE1 (input clk, reset, interrupt,
input [7:0] VAR29, VAR27, VAR23,
input [7:0] VAR1, VAR22, VAR3,
output reg [3:0] VAR15,
output reg [7:0] VAR8,VAR2,
output reg [1:0] VAR21, VAR26, VAR31,
output reg [7:0] VAR7, VAR11,
output reg VAR17, VAR25, VAR12, VAR30);
parameter VAR4 = 3'h0;
parameter VAR32 = 3'h1;
para... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.blackbox.v | 1,233 | module MODULE1 (
VAR2,
VAR1,
VAR3
);
output VAR2;
input VAR1;
input VAR3;
supply1 VAR7;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
kielfriedt/ece472 | lab5/mux3.v | 1,029 | module MODULE1( sel, VAR3, VAR2, VAR1, VAR4 );
input [1:0] sel;
input [31:0] VAR3, VAR2, VAR1;
output VAR4;
reg [31:0] VAR4;
always @(VAR3 or VAR2 or VAR1 or sel)
begin
case (sel)
2'b00:VAR4 = VAR3;
2'b10:VAR4 = VAR2;
2'b01:VAR4 = VAR1;
endcase
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.pp.symbol.v | 1,297 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR4 ,
input VAR3 ,
output VAR1 ,
input VAR5 ,
input VAR8,
input VAR6,
input VAR9
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/etx.v | 16,506 | module MODULE1(
VAR58, VAR101, VAR41, VAR61,
VAR5, VAR68, VAR51, VAR78, VAR43,
VAR83, VAR103, VAR107,
reset, VAR110, VAR44, VAR111, VAR50, VAR92,
VAR12, VAR102, VAR96,
VAR37, VAR19, VAR112, VAR115,
VAR82, VAR69, VAR1, VAR22, VAR114,
VAR73, VAR39, VAR36, VAR93, VAR116,
VAR79, VAR16, VAR15, VAR24,
VAR34, VAR109, VAR8, VA... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/J1_soc-master/hdl/dpram.v | 1,472 | module MODULE1 #(
parameter VAR15 = 13,
parameter VAR2 = 16,
parameter VAR12 = "none"
) (
input VAR7,
input VAR9,
input VAR11,
input [VAR15-1:0] VAR6,
input [VAR2-1:0] VAR3,
input VAR1,
input [VAR15-1:0] VAR14,
output reg [VAR2-1:0] VAR8,
output reg [VAR2-1:0] VAR5,
input VAR13
);
parameter VAR4 = (1 << VAR15);
reg [VA... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/Key_Synchronizer_Bank.v | 1,418 | module MODULE1
parameter VAR5 = 1,
parameter VAR8 = 50000000, parameter VAR1 = 800000000 )
(
input [VAR5-1:0] VAR6,
output [VAR5-1:0] VAR9,
input VAR7
);
genvar VAR10;
generate
begin
for (VAR10 = 0; VAR10 < VAR5; VAR10=VAR10+1)
begin : VAR2
VAR3
.VAR8( VAR8 ),
.VAR1( VAR1 )
)
VAR4
(
.VAR6( VAR6[VAR10] ),
.VAR9( VAR9[VA... | mit |
defano/digital-design | lsuc/rtl/disp_ctrl.v | 5,608 | module MODULE1 (
clk,
reset,
VAR38,
VAR4,
addr,
VAR19,
req,
VAR24,
VAR21,
VAR20,
VAR36);
input clk;
input reset;
output [6:0] VAR38; output [3:0] VAR4;
input [7:0] addr;
input VAR19;
input req;
inout VAR24;
input [7:0] VAR21;
output [7:0] VAR20;
output VAR36;
reg [3:0] VAR16;
reg [6:0] VAR6;
reg [6:0] VAR3;
reg [6:0] V... | mit |
Kumikomi/openreroc_motion_sensor | hardware/src/sonic_sensor.v | 3,143 | module MODULE1(
input clk,
input rst,
input req,
output VAR15,
inout VAR2,
output [31:0] VAR7
output [3:0] VAR11;
);
parameter VAR14 = 0,
VAR20 = 1,
VAR16 = 2,
VAR3 = 3,
VAR5 = 4,
VAR12 = 5,
VAR1 = 6,
VAR4 = 7,
VAR19 = 8;
reg [3:0] state;
reg [31:0] VAR17;
reg [32:0] counter;
reg [31:0] VAR9;
wire VAR13;
wire VAR6;
wir... | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/ecc/mig_7series_v2_3_ecc_merge_enc.v | 5,947 | module MODULE1
parameter VAR19 = 100,
parameter VAR16 = 64,
parameter VAR3 = 72,
parameter VAR5 = 4,
parameter VAR7 = 1,
parameter VAR12 = 64,
parameter VAR9 = 72,
parameter VAR22 = 8,
parameter VAR28 = 4
)
(
VAR4, VAR23,
clk, rst, VAR29, VAR21, VAR25, VAR1, VAR10
);
input clk;
input rst;
input [2*VAR28*VAR16-1:0] VAR2... | mit |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/num_7.v | 1,111 | module MODULE1(
input [2:0] VAR7,
output reg [4:0] VAR4
);
parameter [4:0] VAR3 = 5'b11111; parameter [4:0] VAR6 = 5'b10000; parameter [4:0] VAR5 = 5'b01000; parameter [4:0] VAR8 = 5'b00100; parameter [4:0] VAR1 = 5'b00010; parameter [4:0] VAR2 = 5'b00001;
always @ *
begin
case (VAR7)
3'b000:
VAR4 = VAR3;
3'b001:
VAR4 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3_4.v | 2,175 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR7,
VAR10,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR7;
input VAR10;
input VAR1 ;
input VAR4 ;
VAR6 VAR8 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.pp.symbol.v | 1,315 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4 ,
input VAR1 ,
input VAR5,
input VAR6,
input VAR7
);
endmodule | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | Single/DataMem.v | 3,887 | module MODULE1 (
input clk, rst,
input VAR23, VAR6,
input VAR10,
input [31:0] addr, VAR9,
input [7:0] VAR30,
output VAR1,
output reg [31:0] VAR15,
output reg [7:0] VAR14,
output reg [11:0] VAR25,
output irq
);
parameter VAR5 = 256;
parameter VAR18 = 8; reg [31:0] VAR19[VAR5-1:0];
reg [31:0] VAR3, VAR29;
reg [2:0] VAR12... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/I2C_Controller.v | 3,871 | module MODULE1 (
VAR3,
VAR8, VAR2, VAR16, VAR7, VAR4, VAR9, VAR5, VAR6,
VAR13,
VAR15
);
input VAR3;
input [23:0]VAR16;
input VAR7;
input VAR6;
input VAR9;
inout VAR2;
output VAR8;
output VAR4;
output VAR5;
output [5:0] VAR13;
output VAR15;
reg VAR15;
reg VAR14;
reg VAR4;
reg [23:0]VAR1;
reg [5:0]VAR13;
wire VAR8=VAR14 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.behavioral.pp.v | 2,906 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR20 ,
VAR25 ,
VAR16 ,
VAR23,
VAR21 ,
VAR11 ,
VAR1 ,
VAR6
);
output VAR10 ;
input VAR15 ;
input VAR20 ;
input VAR25 ;
input VAR16 ;
input VAR23;
input VAR21 ;
input VAR11 ;
input VAR1 ;
input VAR6 ;
wire VAR17 ;
wire VAR3 ;
wire VAR13 ;
reg VAR22 ;
wire VAR8 ;
wire VAR14 ;
wire VAR18 ;... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_qpll_wrapper.v | 29,706 | module MODULE1 #
(
parameter VAR70 = "VAR130", parameter VAR69 = "VAR58", parameter VAR149 = "3.0", parameter VAR150 = "VAR143", parameter VAR139 = 0
)
(
input VAR148,
input VAR91,
input VAR65,
output VAR106,
output VAR17,
output VAR63,
input VAR73,
input VAR129,
input VAR26,
input [ 7:0] VAR60,
input VAR9,
input [15:0... | mit |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/ovl_frame.v | 2,109 | module MODULE1 (VAR2, reset, enable, VAR25, VAR21, VAR11);
parameter VAR5 = VAR12;
parameter VAR7 = 0;
parameter VAR17 = 0;
parameter VAR23 = VAR6;
parameter VAR9 = VAR24;
parameter VAR18 = VAR14;
parameter VAR13 = VAR8;
parameter VAR3 = VAR19;
parameter VAR10 = VAR4;
parameter VAR1 = VAR16;
input VAR2, reset, enable;
... | mit |
atti92/heterogenhomework | project1/solution1/syn/verilog/fir_hw_coeff_hw_V.v | 1,168 | module MODULE1 (
VAR6, VAR1, VAR7, clk);
parameter VAR5 = 15;
parameter VAR4 = 7;
parameter VAR3 = 128;
input[VAR4-1:0] VAR6;
input VAR1;
output reg[VAR5-1:0] VAR7;
input clk;
reg [VAR5-1:0] VAR2[VAR3-1:0];
begin
begin | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Booth_Multipliers-master/Src/Booth_Multiplier_2x.v | 11,370 | module MODULE1 #(
parameter VAR15 = 16 )(
input VAR16, input VAR8,
input VAR14, input [(VAR15 - 1):0] VAR1, input [(VAR15 - 1):0] VAR6, output reg VAR3, output reg [((2*VAR15) - 1):0] VAR7 );
localparam VAR9 = ((VAR15 + 1)/2);
reg [4:0] VAR2; reg [2:0] VAR4; reg VAR5;
reg [(VAR15 + 1):0] VAR12; reg [(VAR15 + 1):0] VAR1... | gpl-3.0 |
iamllama/EE2020 | ee2020.cache/ip/3d845bac08f84459/dds_compiler_0_stub.v | 1,539 | module MODULE1(VAR4, VAR3,
VAR1, VAR5, VAR2)
;
input VAR4;
input VAR3;
input [23:0]VAR1;
output VAR5;
output [15:0]VAR2;
endmodule | gpl-3.0 |
CeesWolfs/ceespu | src/gpu/primitives/async_fifo.v | 2,718 | module MODULE1 (
input VAR6,
input VAR9,
input [29:0] din,
input VAR16,
output reg VAR18,
input VAR37,
input VAR12,
output reg [29:0] dout,
input VAR33,
output reg VAR26
);
localparam VAR7 = 5'h1e;
localparam VAR24 = 5'h10;
localparam VAR34 = 3'h4;
reg [3:0] VAR3, VAR35 = 1'h0;
reg [7:0] VAR36, VAR29 = 1'h0;
reg [3:0] ... | mit |
TheMadSocrates/vercpu-project | rtl/fpga/memory_decoder.v | 2,224 | module MODULE1(
input wire [ 7 : 0] address,
input wire [ 7 : 0] VAR18,
input wire [ 7 : 0] VAR12,
input wire clk,
input wire VAR16,
input wire VAR4,
output wire [ 7 : 0] VAR1,
output wire [ 7 : 0] VAR13
);
wire [ 7 : 0] VAR11;
wire [ 7 : 0] VAR2;
wire VAR6, VAR9;
assign VAR6 = VAR4 & (~&address);
VAR17 VAR3 (
.address... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_kc705.v | 5,480 | module MODULE1 (
input wire VAR23, input wire VAR22, input wire VAR5, input wire VAR29, input wire VAR6,
input wire VAR15, input wire VAR26, input wire VAR27, output wire [3:0] VAR14, output wire [3:0] VAR31,
input wire [3:0] VAR40,
input wire [3:0] VAR24,
input wire [ 7:0] VAR3, output wire [ 7:0] VAR30, output wire [... | lgpl-3.0 |
MarkBlanco/FPGA_Sandbox | FPGA1/DE1_SOC_golden_top.v | 7,630 | module MODULE1(
output VAR102,
output VAR33,
input VAR9,
output VAR96,
input VAR101,
inout VAR50,
inout VAR83,
output VAR100,
inout VAR106,
output VAR37,
input VAR2,
input VAR47,
input VAR90,
input VAR91,
output [12:0] VAR52,
output [1:0] VAR62,
output VAR56,
output VAR36,
output VAR30,
output VAR27,
inout [15:0] VAR61... | mit |
combinatorylogic/soc | backends/c2/hw/ice/3rdparty.v | 6,596 | module MODULE3(
input wire clk,
output wire VAR12);
localparam VAR21 = (VAR40 / VAR26) - 1;
localparam VAR16 = VAR10(VAR21);
wire [VAR16-1:0] VAR19 = VAR21;
reg [VAR16-1:0] counter;
assign VAR12 = (counter == VAR19);
always @(posedge clk)
counter <= VAR12 ? 0 : (counter + 1);
endmodule
module MODULE1(
input wire clk,
i... | mit |
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v | 19,870 | module MODULE1 (
VAR92,
VAR43,
VAR104,
VAR47,
VAR67,
VAR109,
VAR35,
VAR84,
VAR101,
VAR52,
VAR9,
VAR80,
VAR33,
VAR7,
VAR99,
VAR85,
VAR68,
VAR13,
VAR14,
VAR73);
input [0:0] VAR92;
input [0:0] VAR43;
input [0:0] VAR104;
input [0:0] VAR47;
input [3:0] VAR67;
input [3:0] VAR109;
input [3:0] VAR35;
input [3:0] VAR84;
input [... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/rw_manager_di_buffer.v | 9,896 | module MODULE1 (
VAR49,
VAR59,
VAR24,
VAR13,
VAR27,
VAR56);
input VAR49;
input [35:0] VAR59;
input [1:0] VAR24;
input [1:0] VAR13;
input VAR27;
output [35:0] VAR56;
tri1 VAR49;
tri0 VAR27;
wire [35:0] VAR18;
wire [35:0] VAR56 = VAR18[35:0];
VAR28 VAR1 (
.VAR2 (VAR13),
.VAR55 (VAR49),
.VAR16 (VAR59),
.VAR10 (VAR27),
.VA... | lgpl-3.0 |
ultraembedded/riscv | core/riscv/riscv_pipe_ctrl.v | 15,768 | module MODULE1
parameter VAR29 = 1
,parameter VAR65 = 1
)
(
input VAR18
,input VAR72
,input VAR10
,input VAR22
,input VAR32
,input VAR50
,input VAR56
,input VAR1
,input VAR111
,input VAR33
,input VAR103
,input [4:0] VAR8
,input [5:0] VAR109
,input VAR15
,input VAR116
,input [31:0] VAR119
,input [31:0] VAR27
,input [31:... | bsd-3-clause |
GSejas/Aproximate-Arithmetic-Operators | src_lib/addlib/GeAr_N20_R5_P5_with_recovery.v | 2,323 | module MODULE1(
input clk,
input [19:0] VAR6,
input [19:0] VAR19,
output reg [20:0] VAR1,
output VAR36,
output reg VAR13,
output reg VAR8,
output reg VAR52
);
reg VAR22, VAR37;
wire VAR28,VAR35,VAR30,VAR16,VAR10;
wire VAR15,VAR12,VAR7,VAR31,VAR51,VAR33,VAR44,VAR14;
wire VAR49,VAR39,VAR50,VAR4,VAR41,VAR29,VAR17,VAR2;
re... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_l2_buf2.v | 5,326 | module MODULE1(
VAR17, VAR18,
VAR4, VAR21,
VAR26, VAR22,
VAR20, VAR28,
VAR16, VAR32, VAR31,
VAR37, VAR33,
VAR34, VAR19,
VAR6, VAR14,
VAR29, VAR25,
VAR24, VAR12, VAR2,
VAR27, VAR15,
VAR11, VAR38, VAR9,
VAR5, VAR36, VAR23,
VAR35, VAR1, VAR8,
VAR3, VAR10,
VAR13, VAR30,
VAR7
);
input [127:0] VAR24;
input [27:0] VAR12;
outp... | gpl-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/firdecim_m5_n25.v | 10,844 | module MODULE1
(
VAR26, VAR4,
VAR31, VAR22, VAR33, VAR30
);
parameter VAR38 = 16;
parameter VAR5 = 32;
parameter VAR14 = 32;
output reg signed [(VAR5-1):0] VAR26;
output reg VAR4;
input VAR31; input VAR22;
input VAR33;
input signed [(VAR38-1):0] VAR30;
reg [4:0] VAR29;
reg [2:0] VAR27; reg signed [(VAR38-1):0] VAR1;
re... | gpl-2.0 |
alexforencich/verilog-ethernet | example/AU50/fpga_10g/rtl/fpga.v | 12,042 | module MODULE1 (
output wire VAR25,
output wire VAR148,
output wire VAR60,
output wire VAR125,
output wire VAR53,
output wire VAR31,
input wire VAR40,
input wire VAR86,
output wire VAR17,
output wire VAR116,
input wire VAR188,
input wire VAR191,
output wire VAR207,
output wire VAR38,
input wire VAR185,
input wire VAR14... | mit |
arthurafarias/UFCG-EE-LASD-2014.1-Experiments | experimento-1.stable/RegisterFile.v | 1,092 | module MODULE1( output reg [15:0] VAR3, VAR5, input [15:0] VAR1, input [2:0] VAR10, VAR4, VAR9, input VAR7, VAR2 );
reg [15:0] VAR8[7:0];
always@(posedge VAR2)
if(VAR7)
case(VAR9)
3'VAR6 000 : VAR8[0] = VAR1;
3'VAR6 001 : VAR8[1] = VAR1;
3'VAR6 010 : VAR8[2] = VAR1;
3'VAR6 011 : VAR8[3] = VAR1;
3'VAR6 100 : VAR8[4] = V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc_2.v | 2,258 | module MODULE1 (
VAR3 ,
VAR2,
VAR7 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR9
);
output VAR3 ;
input VAR2;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR9 ;
VAR8 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3 ,
VAR2,
VAR7
);
output VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.functional.pp.v | 1,998 | module MODULE1 (
VAR17 ,
VAR12 ,
VAR8 ,
VAR7 ,
VAR3 ,
VAR15,
VAR6,
VAR16 ,
VAR13
);
output VAR17 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR15;
input VAR6;
input VAR16 ;
input VAR13 ;
wire VAR14 ;
wire VAR11 ;
wire VAR10;
not VAR1 (VAR14 , VAR12 );
nand VAR2 (VAR11 , VAR3, VAR7, VAR8, VAR14 );
VAR5... | apache-2.0 |
freecores/sha3 | high_throughput_core/rtl/round2in1.v | 8,634 | module MODULE1(in, VAR1, VAR34, out);
input [1599:0] in;
input [63:0] VAR1, VAR34;
output [1599:0] out;
wire [63:0] VAR33[4:0][4:0];
wire [63:0] VAR28[4:0];
wire [63:0] VAR10[4:0][4:0], VAR31[4:0][4:0], VAR7[4:0][4:0], VAR39[4:0][4:0], VAR38[4:0][4:0];
wire [63:0] VAR42[4:0];
wire [63:0] VAR43[4:0][4:0], VAR40[4:0][4:0... | apache-2.0 |
gajjanag/6111_Project | src/BCD.v | 5,969 | module MODULE1(
input wire [7:0] VAR4,
output reg [3:0] VAR2,
output reg [3:0] VAR1,
output reg [3:0] VAR3);
always @ (VAR4) begin
case(VAR4)
0: begin VAR3 <= 0; VAR1 <= 0; end
1: begin VAR3 <= 1; VAR1 <= 0; end
2: begin VAR3 <= 2; VAR1 <= 0; end
3: begin VAR3 <= 3; VAR1 <= 0; end
4: begin VAR3 <= 4; VAR1 <= 0; end
5: ... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/rf.v | 1,375 | module MODULE1 (VAR4, clk, VAR1, VAR9, VAR3, VAR5, VAR6, VAR7, VAR8, VAR2, rst);
input [31:0] VAR4;
input [4:0] VAR9, VAR3, VAR5;
input clk;
input [1:0] VAR1;
output [31:0] VAR6, VAR7;
input rst;
input [4 :0] VAR8;
output [31:0] VAR2;
reg [31:0] register[0:31]; | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/pcie_hcmd_slot_mgt.v | 7,150 | module MODULE1
(
input VAR22,
input VAR6,
output VAR25,
output [6:0] VAR17,
input VAR21,
input VAR5,
input [6:0] VAR19
);
localparam VAR30 = 5'b00001;
localparam VAR16 = 5'b00010;
localparam VAR18 = 5'b00100;
localparam VAR4 = 5'b01000;
localparam VAR1 = 5'b10000;
reg [4:0] VAR9;
reg [4:0] VAR24;
reg [127:0] VAR2;
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi_2.v | 2,473 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR1 ,
VAR11 ,
VAR2 ,
VAR6 ,
VAR8,
VAR3,
VAR9 ,
VAR10
);
output VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR8;
input VAR3;
input VAR9 ;
input VAR10 ;
VAR4 VAR5 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.behavioral.v | 1,180 | module MODULE1( VAR5, VAR6, VAR1 );
input VAR5, VAR1;
output VAR6;
VAR3 VAR4(.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1));
VAR3 VAR2(.VAR5(VAR5),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 56,935 | module MODULE1 (
input wire VAR112, input wire VAR29, input wire VAR102, input wire [31:0] VAR121, output wire VAR17, input wire [4:0] VAR83, input wire [31:0] VAR141, input wire VAR251, output wire [255:0] VAR130, output wire VAR233, input wire VAR287, input wire [255:0] VAR252, output wire [26:0] VAR274, output wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.functional.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp.behavioral.v | 2,446 | module MODULE1 (
VAR9 ,
VAR15 ,
VAR23,
VAR14 ,
VAR22
);
output VAR9 ;
output VAR15 ;
input VAR23;
input VAR14 ;
input VAR22 ;
supply1 VAR13;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR19 ;
wire VAR3 ;
reg VAR12 ;
wire VAR1 ;
wire VAR4 ;
wire VAR6 ;
wire VAR24;
wire VAR21 ;
wire VAR20 ;
wire VAR16 ;
wire VAR17 ;
not VAR5 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.symbol.v | 1,393 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR7
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
piranna/wasmachine | src/SuperStack.v | 4,551 | module MODULE1
parameter VAR9 = 8, parameter VAR19 = 3, parameter VAR22 = 0
)
(
input clk,
input reset,
input [ 2:0] VAR10, input [VAR9-1:0] VAR14, input [VAR19 :0] VAR13, input [VAR19 :0] VAR21, input [VAR19 :0] VAR30, input [VAR19 :0] VAR23, input VAR3,
output reg [VAR19 :0] VAR25 = 0, output [VAR9-1:0] out, output [... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/pcie_blk_cf.v | 18,731 | module MODULE1
(
input wire clk,
input wire VAR96,
output VAR25,
input wire VAR135,
input wire [3:0] VAR73,
input wire [7:0] VAR155,
input wire VAR151,
input wire VAR27,
input wire VAR150,
input wire VAR50,
input wire VAR137,
input wire VAR124,
input wire [12:0] VAR8,
input wire [2:0] VAR87,
input wire [2:0] VAR118,
ou... | lgpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/xilinx_s6_pcie_wrapper.v | 15,118 | module MODULE1
(
VAR51, VAR2, VAR32, VAR14,
VAR46, VAR20, VAR77, VAR13,
VAR87, VAR95, VAR60, VAR44, VAR10,
VAR85, VAR98, VAR38, VAR96, VAR11,
VAR83, VAR31, VAR1, VAR71, VAR9,
VAR16, VAR48, VAR6,
VAR35, VAR80,
VAR75, VAR101,
VAR59, VAR27, VAR18,
VAR33, VAR25, VAR69, VAR65,
VAR26, VAR62, VAR90,
VAR30, VAR47, VAR67,
VAR79... | lgpl-3.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_mii_fifo.v | 10,122 | module MODULE1 #
(
parameter VAR112 = "VAR109",
parameter VAR21 = "VAR47",
parameter VAR75 = 8,
parameter VAR104 = (VAR75>8),
parameter VAR90 = (VAR75/8),
parameter VAR95 = 1,
parameter VAR92 = 64,
parameter VAR117 = 4096,
parameter VAR76 = 1,
parameter VAR70 = 1,
parameter VAR10 = VAR70,
parameter VAR7 = VAR10,
parame... | mit |
mrehkopf/sd2snes | verilog/sd2snes_cx4/address.v | 2,839 | module MODULE1(
input VAR1,
input [15:0] VAR25,
input [2:0] VAR5, input [23:0] VAR24, input [7:0] VAR15, input VAR6, output [23:0] VAR7, output VAR10, output VAR19, output VAR3, output VAR18, input [23:0] VAR29,
input [23:0] VAR30,
output VAR9,
output VAR4,
output VAR14,
output VAR12,
output VAR28,
output VAR20,
output... | gpl-2.0 |
marcv81/proxmark3 | fpga/lo_read.v | 3,656 | module MODULE1(
VAR14, VAR8, VAR1,
VAR11, VAR23, VAR6, VAR16, VAR18, VAR13,
VAR20, VAR12,
VAR21, VAR5, VAR2, VAR15,
VAR4, VAR10,
VAR3,
VAR9, VAR19
);
input VAR14, VAR8, VAR1;
output VAR11, VAR23, VAR6, VAR16, VAR18, VAR13;
input [7:0] VAR20;
output VAR12;
input VAR2;
output VAR21, VAR5, VAR15;
input VAR4, VAR10;
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b.functional.pp.v | 1,934 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR4 ,
VAR3,
VAR11,
VAR15 ,
VAR13
);
output VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR3;
input VAR11;
input VAR15 ;
input VAR13 ;
wire VAR1 ;
wire VAR2 ;
wire VAR6;
not VAR7 (VAR1 , VAR8 );
and VAR5 (VAR2 , VAR1, VAR4 );
VAR9 VAR12 (VAR6, VAR2, VAR3, VAR11);
buf VAR14 (VAR10 , VAR6 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.pp.symbol.v | 1,344 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR3 ,
input VAR7,
input VAR8,
input VAR2 ,
input VAR4 ,
input VAR6 ,
input VAR9
);
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/MemoryOnBoard/data_ram_display.v | 5,465 | module MODULE1(
input clk,
input VAR28,
input [3:0] VAR44,
input [1:0] VAR38,
output [3:0] VAR41,
output VAR25, output VAR35, output VAR43,
output VAR30,
output VAR14,
output VAR22,
output VAR31,
output VAR16,
inout[15:0] VAR37,
output VAR19,
inout VAR15,
inout VAR23,
output VAR6,
output VAR11
);
assign VAR41 = VAR44;
... | mit |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/pat_gen/axi_mux.v | 3,664 | module MODULE1 (
input VAR7,
input [7:0] VAR10,
input VAR2,
input VAR12,
output reg VAR5,
input [7:0] VAR9,
input VAR6,
input VAR1,
output reg VAR11,
output reg [7:0] VAR13,
output reg VAR4,
output reg VAR8,
input VAR3
);
always @(VAR7 or VAR10 or VAR2 or VAR12 or VAR9 or
VAR6 or VAR1)
begin
if (VAR7) begin
VAR13 = VAR... | lgpl-3.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkOutputArbiter.v | 8,271 | module MODULE1(VAR38,
VAR4,
VAR51,
select,
VAR28);
input VAR38;
input VAR4;
input [4 : 0] VAR51;
output [4 : 0] select;
input VAR28;
wire [4 : 0] select;
reg [4 : 0] VAR11;
wire [4 : 0] VAR32;
wire VAR31;
wire [1 : 0] VAR30,
VAR13,
VAR16,
VAR12,
VAR34,
VAR42,
VAR26,
VAR18,
VAR17,
VAR15;
wire VAR35,
VAR3,
VAR1,
VAR10,
V... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pcie_brams_7x.v | 9,221 | module MODULE1
parameter [3:0] VAR10 = 4'h1, parameter [5:0] VAR9 = 6'h08, parameter VAR8 = "VAR13",
parameter VAR14 = 0,
parameter VAR17 = 1,
parameter VAR16 = 1,
parameter VAR4 = 1,
parameter VAR25 = 1 )
(
input VAR15,
input VAR20,
input VAR19,
input [12:0] VAR22,
input [71:0] VAR12,
input VAR6,
input VAR5,
input [12... | gpl-3.0 |
mateuszokulanis/OM_FIREWALL | src/firewall_top.v | 2,458 | module MODULE1(
input VAR10,
input VAR11,
input VAR12,
input VAR23,
input VAR1,
output reg [7:0] VAR31,
output reg VAR53,
output reg VAR14,
input [7:0] VAR17,
input VAR54,
input VAR2,
output reg [7:0] VAR39,
output reg VAR59,
output reg VAR22
);
wire VAR4;
wire [7:0] VAR15;
wire VAR63;
wire VAR42;
wire VAR52;
wire VAR6... | mit |
mrehkopf/sd2snes | verilog/sd2snes_gsu/gsu.v | 93,290 | module MODULE1(
input VAR422,
input VAR248,
input [23:0] VAR257,
input [23:0] VAR2,
input VAR414,
input VAR198,
input VAR37,
input VAR199,
input [9:0] VAR270,
input [7:0] VAR436,
output VAR366,
output [7:0] VAR339,
input VAR156,
output VAR143,
output VAR261,
output [23:0] VAR363,
input [15:0] VAR48,
input VAR443,
outpu... | gpl-2.0 |
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