sample_id int64 1 50 | topology stringclasses 5
values | spec_cutoff_frequency_hz float64 1k 100k | spec_min_impedance_ohm float64 1k 20k | spec_target_gain float64 1 5 | optimized_parameters stringlengths 40 70 | electrical_rule_violations int64 0 0 | spice_netlist stringlengths 45 109 | verilog_hdl stringlengths 372 508 |
|---|---|---|---|---|---|---|---|---|
1 | rc_lowpass | 100,000 | 5,000 | 2 | {"R1": 10000.0, "C1": 1.6000000000000002e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 10000.0
C1 out 0 1.6000000000000002e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #... |
2 | sallen_key_lowpass | 5,000 | 1,000 | 5 | {"R1": 9100.0, "R2": 9100.0, "C1": 2e-08, "C2": 1e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 2e-08
C2 pos 0 1e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
3 | voltage_divider | 10,000 | 5,000 | 2 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
4 | opamp_non_inverting | 5,000 | 20,000 | 5 | {"Rf": 39000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 39000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(39000.0)) Rf (.p1(pin_out), .p2(n... |
5 | opamp_inverting | 1,000 | 5,000 | 5 | {"Rin": 10000.0, "Rf": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 10000.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) Rin (.p1(pin_in), .p2(neg))... |
6 | rc_lowpass | 50,000 | 5,000 | 1 | {"R1": 9100.0, "C1": 3.3e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 3.3e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
7 | sallen_key_lowpass | 1,000 | 5,000 | 1 | {"R1": 9100.0, "R2": 9100.0, "C1": 1.8e-07, "C2": 3.3e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1.8e-07
C2 pos 0 3.3e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
8 | voltage_divider | 25,000 | 20,000 | 1 | {"R1": 100.0, "R2": 62000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 62000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
9 | opamp_non_inverting | 10,000 | 5,000 | 3 | {"Rf": 20000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 20000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(20000.0)) Rf (.p1(pin_out), .p2(n... |
10 | opamp_inverting | 15,915 | 20,000 | 1 | {"Rin": 9100.0, "Rf": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
11 | rc_lowpass | 1,000 | 1,000 | 5 | {"R1": 9100.0, "C1": 1.6e-08, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 1.6e-08 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
12 | sallen_key_lowpass | 10,000 | 1,000 | 2 | {"R1": 9100.0, "R2": 9100.0, "C1": 1e-12, "C2": 1e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1e-12
C2 pos 0 1e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
13 | voltage_divider | 1,000 | 1,000 | 1 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
14 | opamp_non_inverting | 1,000 | 1,000 | 2 | {"Rf": 10000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 10000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) Rf (.p1(pin_out), .p2(n... |
15 | opamp_inverting | 50,000 | 20,000 | 5 | {"Rin": 10000.0, "Rf": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 10000.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) Rin (.p1(pin_in), .p2(neg))... |
16 | rc_lowpass | 10,000 | 5,000 | 2 | {"R1": 9100.0, "C1": 1.6000000000000003e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 1.6000000000000003e-09 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
17 | sallen_key_lowpass | 1,000 | 10,000 | 1 | {"R1": 9100.0, "R2": 9100.0, "C1": 1.8e-07, "C2": 3.3e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1.8e-07
C2 pos 0 3.3e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
18 | voltage_divider | 10,000 | 1,000 | 2 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
19 | opamp_non_inverting | 15,915 | 5,000 | 5 | {"Rf": 39000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 39000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(39000.0)) Rf (.p1(pin_out), .p2(n... |
20 | opamp_inverting | 25,000 | 5,000 | 1 | {"Rin": 9100.0, "Rf": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
21 | rc_lowpass | 50,000 | 1,000 | 5 | {"R1": 9100.0, "C1": 3.3e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 3.3e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
22 | sallen_key_lowpass | 10,000 | 1,000 | 5 | {"R1": 9100.0, "R2": 9100.0, "C1": 1e-12, "C2": 1e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1e-12
C2 pos 0 1e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
23 | voltage_divider | 1,000 | 20,000 | 5 | {"R1": 100.0, "R2": 62000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 62000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
24 | opamp_non_inverting | 100,000 | 20,000 | 5 | {"Rf": 39000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 39000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(39000.0)) Rf (.p1(pin_out), .p2(n... |
25 | opamp_inverting | 15,915 | 20,000 | 2 | {"Rin": 9100.0, "Rf": 20000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 20000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
26 | rc_lowpass | 15,915 | 10,000 | 1 | {"R1": 9100.0, "C1": 9.1e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 9.1e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
27 | sallen_key_lowpass | 100,000 | 5,000 | 3 | {"R1": 9100.0, "R2": 9100.0, "C1": 5.6e-08, "C2": 1e-12, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 5.6e-08
C2 pos 0 1e-12
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
28 | voltage_divider | 1,000 | 10,000 | 3 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
29 | opamp_non_inverting | 1,000 | 5,000 | 1 | {"Rf": 100.0, "Rg": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 100.0
Rg neg 0 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) Rf (.p1(pin_out), .p2(neg... |
30 | opamp_inverting | 25,000 | 10,000 | 2 | {"Rin": 9100.0, "Rf": 20000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 20000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
31 | rc_lowpass | 50,000 | 10,000 | 3 | {"R1": 9100.0, "C1": 3.3e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 3.3e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
32 | sallen_key_lowpass | 15,915 | 1,000 | 1 | {"R1": 9100.0, "R2": 9100.0, "C1": 1e-12, "C2": 1e-12, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1e-12
C2 pos 0 1e-12
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
33 | voltage_divider | 15,915 | 10,000 | 1 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
34 | opamp_non_inverting | 10,000 | 10,000 | 2 | {"Rf": 10000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 10000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) Rf (.p1(pin_out), .p2(n... |
35 | opamp_inverting | 15,915 | 10,000 | 1 | {"Rin": 9100.0, "Rf": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
36 | rc_lowpass | 100,000 | 1,000 | 3 | {"R1": 10000.0, "C1": 1.6000000000000002e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 10000.0
C1 out 0 1.6000000000000002e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #... |
37 | sallen_key_lowpass | 15,915 | 5,000 | 1 | {"R1": 9100.0, "R2": 9100.0, "C1": 1e-12, "C2": 1e-12, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1e-12
C2 pos 0 1e-12
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
38 | voltage_divider | 50,000 | 20,000 | 3 | {"R1": 100.0, "R2": 62000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 62000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
39 | opamp_non_inverting | 100,000 | 1,000 | 1 | {"Rf": 100.0, "Rg": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 100.0
Rg neg 0 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) Rf (.p1(pin_out), .p2(neg... |
40 | opamp_inverting | 15,915 | 20,000 | 5 | {"Rin": 10000.0, "Rf": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 10000.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) Rin (.p1(pin_in), .p2(neg))... |
41 | rc_lowpass | 15,915 | 10,000 | 3 | {"R1": 9100.0, "C1": 9.1e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 9100.0
C1 out 0 9.1e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #(... |
42 | sallen_key_lowpass | 50,000 | 10,000 | 3 | {"R1": 9100.0, "R2": 9100.0, "C1": 2.2e-07, "C2": 1e-12, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 2.2e-07
C2 pos 0 1e-12
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
43 | voltage_divider | 15,915 | 1,000 | 1 | {"R1": 100.0, "R2": 51000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 51000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
44 | opamp_non_inverting | 10,000 | 10,000 | 3 | {"Rf": 20000.0, "Rg": 9100.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 20000.0
Rg neg 0 9100.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(20000.0)) Rf (.p1(pin_out), .p2(n... |
45 | opamp_inverting | 100,000 | 5,000 | 1 | {"Rin": 9100.0, "Rf": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
46 | rc_lowpass | 100,000 | 1,000 | 2 | {"R1": 10000.0, "C1": 1.6000000000000002e-10, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 10000.0
C1 out 0 1.6000000000000002e-10 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: rc_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(10000.0)) R1 (.p1(pin_in), .p2(pin_out));
capacitor #... |
47 | sallen_key_lowpass | 10,000 | 10,000 | 2 | {"R1": 9100.0, "R2": 9100.0, "C1": 1e-12, "C2": 1e-09, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in n1 9100.0
R2 n1 pos 9100.0
C1 n1 out 1e-12
C2 pos 0 1e-09
EOP_1 out 0 pos out 100000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: sallen_key_lowpass
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal n1;
wreal pos;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) R1 (.p1(pin... |
48 | voltage_divider | 5,000 | 20,000 | 5 | {"R1": 100.0, "R2": 62000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
R1 in out 100.0
R2 out 0 62000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: voltage_divider
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) R1 (.p1(pin_in), .p2(pin_out));
resistor... |
49 | opamp_non_inverting | 25,000 | 1,000 | 1 | {"Rf": 100.0, "Rg": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
EOP_1 out 0 in neg 100000.0
Rf out neg 100.0
Rg neg 0 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_non_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(100.0)) Rf (.p1(pin_out), .p2(neg... |
50 | opamp_inverting | 15,915 | 20,000 | 1 | {"Rin": 9100.0, "Rf": 10000.0, "Vin": 1.0} | 0 | Vin in 0 1.0
Rin in neg 9100.0
EOP_1 out 0 0 neg 100000.0
Rf out neg 10000.0 | // VoltNet Generated Structural SystemVerilog for synthesized_design
// Topology: opamp_inverting
module synthesized_design (
input wreal pin_in, output wreal pin_out
);
wreal neg;
wreal gnd = 0.0;
vsource #(.v(1.0)) Vin (.p1(pin_in), .p2(gnd));
resistor #(.r(9100.0)) Rin (.p1(pin_in), .p2(neg));... |
VoltNet Physics-Grounded Circuit Synthesis Dataset
This dataset contains physics-verified analog & digital circuit designs generated by the VoltNet framework. Each record includes:
- Circuit topology specifications (RC filter, Sallen-Key 2nd order filter, Op-Amp gain stages, Voltage dividers).
- E24 standard commercial component values.
- SPICE MNA netlists.
- Synthesizable SystemVerilog structural code.
- Zero Electrical Rule Violation (ERV) verification status.
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