agent/hardware.md

Hardware model — query it, never assume it

Always read the device at run time. Hardcoding an SM count, a tile derived from one, or a datasheet peak makes a kernel slower on every machine it was not tuned on.

p = torch.cuda.get_device_properties(0)
p.name, p.major, p.minor
p.multi_processor_count            # size persistent grids from THIS
p.shared_memory_per_block_optin    # the number that matters for big tiles
p.regs_per_multiprocessor, p.max_threads_per_multi_processor, p.total_memory

cudaDeviceProp pr; cudaGetDeviceProperties(&pr, 0);   // multiProcessorCount, sharedMemPerBlockOptin

Measure achieved HBM bandwidth with a large stream-copy. Datasheet peak is not attainable and the gap varies by access pattern.

Capability ladder

Verified by compiling each instruction for each target with CUDA 12.8 (full matrix in ref/ptx.md). "yes" means the instruction assembles — a lower bound on availability, not a claim about speed.

feature	sm_80 Ampere	sm_89 Ada/Lovelace	sm_90 Hopper	sm_100 Blackwell DC	sm_120 Blackwell RTX
async global→shared	cp.async	cp.async	cp.async + TMA	cp.async + TMA	cp.async + TMA
tensor-core MMA	mma.sync	mma.sync	wgmma (warpgroup)	tcgen05 + tensor memory	mma.sync only
fp8 (e4m3/e5m2)	no	yes	yes	yes	yes
fp6 / fp4 / MX scales	no	no	no	yes	yes
clusters / DSMEM	no	no	yes	yes	yes
transaction barriers (expect_tx)	no	no	yes	yes	yes
stmatrix	no	no	yes	yes	yes
setmaxnreg (warp-spec regs)	no	no	yes	yes	yes
PDL (griddepcontrol)	no	no	yes	yes	yes
smem per block (opt-in)	163 KB	99 KB	227 KB	query it	query it

Shared-memory figures are the per thread block opt-in limits from the Programming Guide §16 tables; each is 1 KB below the per-SM partition, which is reserved for system use. Cross-checked on this H200: shared_memory_per_block_optin = 232,448 B against shared_memory_per_multiprocessor = 233,472 B — exactly that 1 KB. Blackwell's value is left as "query it" rather than guessed.

What this means per architecture

sm_89 (Ada / L40S, RTX 40-series) — an Ampere-class programming model with fp8 arithmetic. It has the fp8 mma.sync, but none of the Hopper structure: no TMA, no clusters, no stmatrix, no setmaxnreg, no transaction barriers, no elect.sync. Every Hopper technique — TMA choreography, warp specialisation with register reallocation, cluster barriers — is simply unavailable. Wins come from cp.async multi-stage pipelining, ldmatrix + mma.sync, vectorised access, and fp8. Note the much smaller shared memory: 99 KB opt-in per block against Hopper's 227 KB, so a tile sized for Hopper will not launch at all.

sm_90 (Hopper / H100, H200) — TMA loads + wgmma + producer/consumer warp specialisation over a multi-stage shared-memory pipeline. Not using TMA usually leaves bandwidth on the table.

sm_100 (Blackwell datacenter / B100, B200) — wgmma does not exist here. A warpgroup GEMM written for Hopper will not compile. Blackwell replaces it with tcgen05, whose accumulator lives in a separate tensor memory space rather than in registers, so the register-pressure calculus that drives Hopper tile sizing changes entirely. It also gains native fp4/fp6 and MX block scales, so microscaled formats feed the MMA directly instead of being dequantised by hand as on sm_90.

sm_120 (Blackwell RTX / RTX 50-series, RTX PRO) — Blackwell's consumer line, and tcgen05 is absent. It has TMA, clusters, fp4/fp6 conversions and mma.sync, but not the 5th-gen tensor core instructions. Do not assume "Blackwell" implies tcgen05; check the target.

Portability

mma.sync is the only tensor-core path that assembles from Ada through Blackwell. If one binary must span architectures, either dispatch on __CUDA_ARCH__ between mma.sync / wgmma / tcgen05, or target mma.sync and accept the ceiling. tools/check_toolchain.py <arch> regenerates the matrix for whatever you are building for.

Numbers that decide tile sizes

• A warp is 32 threads; wgmma operates on a warpgroup (128 threads).
• Shared memory is banked 32-wide × 4 B; a conflict-free access needs distinct banks per thread, which padding breaks for 2-byte types — swizzle instead.
• Global loads coalesce into 32 B sectors; aim for 128 B per warp per access.
• Occupancy is limited by whichever of registers / smem / block size binds first — compute all three.