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@@ -65,3 +65,8 @@ collect/openhwgroup/openhwgroup__cva6_s01_01_prs.jsonl filter=lfs diff=lfs merge
 collect/openhwgroup/openhwgroup__cva6_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
 s2/lowRISC__ibex/lowRISC__ibex_s2_01_materials.jsonl filter=lfs diff=lfs merge=lfs -text
 s2/openhwgroup__cva6/openhwgroup__cva6_s2_01_materials.jsonl filter=lfs diff=lfs merge=lfs -text
+s1/chipsalliance/chipsalliance__caliptra-rtl_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
+s1/lowRISC/lowRISC__ibex_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -text
+s1/lowRISC/lowRISC__ibex_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
+s1/openhwgroup/openhwgroup__cva6_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -text
+s1/openhwgroup/openhwgroup__cva6_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text

s1/chipsalliance/chipsalliance__caliptra-rtl_s01_05_patches.jsonl

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dc545987dfaf6f3721ac30caa0d84126bd1e5b60660efc0008ae3c2c336fc4ec
+size 176268751

s1/chipsalliance/chipsalliance__caliptra-rtl_s01_06_single_rtl_candidates.jsonl

@@ -0,0 +1,4 @@
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "lang": "sv", "rtl_files": ["src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "commit_id": "55f5f95fb2b352be2f9c6482142fcc63763e0d31", "timestamp": "2024-03-29T19:25:01+00:00", "pr_title": "[UVM] Implement mailbox sanitize feature in val fw to suppress regression failure", "pr_body": "Implement a firmware feature (for the validation code used in UVM tests) to sanitize the mailbox after detecting double-bit ECC error, to mirror the workaround required in 1.1 Firmware as per https://github.com/chipsalliance/caliptra-rtl/issues/399.\r\n\r\nThis is a temporary solution that should be removed for 2.0, as the mailbox should be modified to avoid spurious data prefetches.", "merge_commit_sha": "234a09993120d436e441827ad2f500154ec4f36a", "issue_title": "Caliptra uC is reading one extra entry from Mailbox SRAM causing unexpected ECC errors", "issue_body": "Hi, We are bringing up Mailbox testcases and observed the following scenario where an unexpected ECC error is getting fired. Below is our sequence.\r\n\r\n1. SOC acquires the MBOX lock by reading MBOX_LOCK register. It returns 0 indicating that the lock has been acquired by SOC.\r\n2. SOC writes MBOX command register.\r\n3. SOC writes MBOX_DLEN register to 8 indicating that it has 8 bytes of data to write.\r\n4. SOC writes MBOX_DATAIN register twice. This causes two writes to SRAM mailbox at addresses 0x0 and 0x1.\r\n5. SOC writes MBOX_EXECUTE to 1 in order for uC to process the mailbox command.\r\n6. When the mailbox state machine is in MBOX_EXECUTE_UC state, we are observing that Caliptra is reading SRAM mailbox at addresses 0x0, 0x1 and 0x2. The first two are expected as DLEN is 8. However the data at address 0x2 are all X and hence ECC error signal (soc_ifc_top1.i_mbox.sram_double_ecc_error) is going X.\r\n\r\nWe want to understand why the mailbox state machine is reading one extra entry from SRAM (DLEN + 4 bytes instead of DLEN bytes). Since the Mailbox SRAM is not initialized on reset, reading from addresses where there have been no previous writes will cause unexpected ECC errors.\r\n\r\nDo Caliptra ROM initializes Mailbox SRAM during bring up?\r\n\r\nMailbox Command from SOC\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/0e81da11-df93-41e0-a60c-872d2a749bdc)\r\n\r\nECC error while Mailbox state machine is reading from address 0x2\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/b3a0e590-1662-4780-8afc-e0275c8537b4)\r\n", "commit_message": "Typo fix in comment", "fix_patch": "diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\nindex 2a1bcd3b3..a117b2a0c 100644\n--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n@@ -40,6 +40,8 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n \n   `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )\n \n+  extern virtual task mbox_teardown();\n+\n   // Constrain command to undefined opcode\n   constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }\n \n@@ -105,3 +107,13 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n   endtask\n \n endclass\n+\n+//==========================================\n+// Task:        mbox_teardown\n+// Description: At end-of-sequence, inject some stalls to allow\n+//              uC to acquire lock and sanitize the mailbox\n+//==========================================\n+task soc_ifc_env_mbox_sram_double_bit_flip_sequence::mbox_teardown();\n+    do_rand_delay(1, DLY_MEDIUM);\n+    super.mbox_teardown();\n+endtask\n", "test_patch": "diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\nindex 9939a2515..417f10e6d 100644\n--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n@@ -322,6 +322,7 @@ void caliptra_rt() {\n         if (cptra_intr_rcv.soc_ifc_notif   ) {\n             uint8_t fsm_chk;\n             uint8_t fail = 0;\n+            uint32_t dlen_received;\n             VPRINTF(LOW, \"Intr received: soc_ifc_notif\\n\");\n             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {\n                 CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)\n@@ -379,6 +380,7 @@ void caliptra_rt() {\n                 }\n                 //read the mbox command\n                 op = soc_ifc_read_mbox_cmd();\n+                dlen_received = op.dlen;\n                 if (op.cmd & MBOX_CMD_FIELD_FW_MASK) {\n                     VPRINTF(MEDIUM, \"Received mailbox firmware command from SOC! Got 0x%x\\n\", op.cmd);\n                     if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {\n@@ -517,6 +519,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else if (fail) {\n                         VPRINTF(LOW, \"Cmd failed\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n@@ -564,6 +574,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else {\n                         soc_ifc_set_mbox_status_field(CMD_COMPLETE);\n                     }\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\nindex c7270fb2d..299846807 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n@@ -108,6 +108,15 @@ void soc_ifc_clr_flow_status_field(uint32_t field) {\n     lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS,reg);\n }\n \n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count) {\n+    for(uint32_t ii=0; ii<attempt_count; ii++) {\n+        if((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {\n+            return 0;\n+        }\n+    }\n+    return 1;\n+}\n+\n mbox_op_s soc_ifc_read_mbox_cmd() {\n     mbox_op_s op;\n \n@@ -226,6 +235,22 @@ void soc_ifc_fw_update(mbox_op_s op) {\n         }\n }\n \n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count) {\n+    if (byte_count > MBOX_DIR_SPAN) {\n+        VPRINTF(FATAL, \"SOC_IFC: Illegal byte_count 0x%x\\n\", byte_count);\n+        SEND_STDOUT_CTRL(0x1);\n+    }\n+    if (soc_ifc_mbox_acquire_lock(attempt_count) != 0) {\n+        VPRINTF(ERROR, \"ERROR: Failed to acquire lock for mbox sanitize operation\\n\");\n+        return 1;\n+    }\n+    for (uint32_t ii=0; ii < byte_count; ii+=4) {\n+        lsu_write_32(MBOX_DIR_BASE_ADDR+ii, 0x0);\n+    }\n+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);\n+    return 0;\n+}\n+\n void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {\n     uint32_t reg;\n     VPRINTF(MEDIUM,\"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\\n\", wait_cycles, wait_cycles > 5 ? \"will override\" : wait_cycles > 0 ? \"will use default 5\" : \"won't override\");\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\nindex 22e415442..84f6ad365 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n@@ -112,9 +112,11 @@ inline void soc_ifc_set_iccm_lock() {\n     lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);\n }\n // Mailbox command flows\n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count);\n mbox_op_s soc_ifc_read_mbox_cmd();\n void soc_ifc_mbox_fw_flow(mbox_op_s op);\n void soc_ifc_fw_update(mbox_op_s op);\n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count);\n \n // SHA Accelerator Functions\n void soc_ifc_sha_accel_acquire_lock();\n", "modified_files": ["src/integration/test_suites/caliptra_rt/caliptra_rt.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.h", "src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "lines_added": 57, "lines_removed": 0}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "lang": "sv", "rtl_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "commit_id": "76d7c90fc8eab682519676e12d3e1599040df43b", "timestamp": "2023-09-08T16:04:47+00:00", "pr_title": "Fixing LEC reported in caliptra_prim_assert_sec_cm.svh", "pr_body": "This error was flagged in https://github.com/chipsalliance/caliptra-rtl/issues/186.  Removing the assertions altogether since they are not used in the current design.", "merge_commit_sha": "7bfc833749685a58e79b8c141ee2daa69764e805", "issue_title": "Formality LEC Failure Verilog 527:   (error) Syntax error found in the definition of argument macro ", "issue_body": "LEC Formality_Error_Code  reported in caliptra_prim_assert_sec_cm.svh\r\n\r\nError: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 49)  (Formality_Error_Code)\r\n1361:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 52)  (Formality_Error_Code)\r\n1362:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 55)  (Formality_Error_Code)\r\n1363:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 58)  (Formality_Error_Code)\r\n1364:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 61)  (Formality_Error_Code)\r\n\r\n[caliptra_fm_errors.tar.gz](https://github.com/chipsalliance/caliptra-rtl/files/12352228/caliptra_fm_errors.tar.gz)\r\n\r\n", "commit_message": "Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_cm.svh\n\nhttps://github.com/chipsalliance/caliptra-rtl/issues/186", "fix_patch": "diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\nindex 11ba287e0..096b7b61f 100644\n--- a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n@@ -45,21 +45,4 @@\n   `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \\\n     REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)\n \n-// macros for security countermeasures that will trigger other errors\n-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \\\n-    REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)\n-\n `endif // PRIM_ASSERT_SEC_CM_SVH\n", "test_patch": "", "modified_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "lines_added": 0, "lines_removed": 17}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "lang": "sv", "rtl_files": ["src/integration/rtl/caliptra_top.sv"], "commit_id": "02f97acf731c1dae6275883b4ccd200cee01e998", "timestamp": "2023-05-29T15:13:01+00:00", "pr_title": "Connection of the SB (debug) bus in Caliptra", "pr_body": "This PR connects `SB` and `LSU` AHB buses together using a 2:1 mux so that access to peripherals is possible via the JTAG port.\r\n\r\n**! This PR is required for the CI in https://github.com/chipsalliance/caliptra-rtl/pull/72 to pass !**", "merge_commit_sha": "b86ce1854884d2064cf6e82f46f406f15c9e7237", "issue_title": "Enable using OpenOCD for interactive debugging of simulated Caliptra core", "issue_body": "This PR adds support for OpenOCD's `remote_bitbang` virtual adapter driver that allows to tap into the running verilated simulation of Caliptra RTL.\r\n\r\nTo achive this several components are added:\r\n- `tcp_server`\r\n  Acts as a communication bridge between OpenOCD and the simulation\r\n- `jtagdpi`\r\n  Parses OpenOCD commands, formats replies and interacts with the simulation via DPI calls\r\n- OpenOCD scripts (`tools/scripts/openocd`)\r\n  These define the interface and target for OpenOCD\r\n\r\nTo connect to a running simulation first build and run the special `infinite_loop` test:\r\n```\r\nmake -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=infinite_loop verilator\r\n```\r\nThen connect to it via OpenOCD (assuming that OpenOCD is installed):\r\n```\r\ncd tools/scripts/openocd\r\nopenocd -f board/caliptra-verilator.cfg\r\n```\r\nFinally start a debugging session with GDB by connecting to OpenOCD. Upon running GDB issue the following command:\r\n```\r\ntarget remote :3333\r\n```\r\nIf everything worked correctly you should be able to eg. dump the RISC-V core registers in GDB:\r\n```\r\ninfo registers\r\n```\r\n\r\nThe PR also includes a new workflow `Interactive debugging` which runs the flow described above in CI and performs various debugging actions. The tests in the new flow include:\r\n\r\n- Core register access via GDB + OpenOCD\r\n- Memory access (ICCM, DCCM and ROM)\r\n- Peripheral access\r\n- Peripheral access while the core is forcibly held in reset", "commit_message": "Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to peripherals\n\nSigned-off-by: Maciej Kurc <mkurc@antmicro.com>", "fix_patch": "diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv\nindex 1dcd23645..f59d9c221 100755\n--- a/src/integration/rtl/caliptra_top.sv\n+++ b/src/integration/rtl/caliptra_top.sv\n@@ -276,6 +276,17 @@ end\n     //========================================================================\r\n     // AHB Master ports\r\n     //========================================================================\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    sb_ahb();\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    lsu_ahb();\r\n+\r\n     CALIPTRA_AHB_LITE_BUS_INF #(\r\n         .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n         .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n@@ -403,34 +414,34 @@ el2_veer_wrapper rvtop (\n     //---------------------------------------------------------------\r\n     // Debug AHB Master\r\n     //---------------------------------------------------------------\r\n-    .sb_haddr               (),\r\n-    .sb_hburst              (),\r\n-    .sb_hmastlock           (),\r\n-    .sb_hprot               (),\r\n-    .sb_hsize               (),\r\n-    .sb_htrans              (),\r\n-    .sb_hwrite              (),\r\n-    .sb_hwdata              (),\r\n-\r\n-    .sb_hrdata              ('0),\r\n-    .sb_hready              ('0),\r\n-    .sb_hresp               ('0),\r\n+    .sb_haddr               ( sb_ahb.haddr   ),\r\n+    .sb_hburst              (                ),\r\n+    .sb_hmastlock           (                ),\r\n+    .sb_hprot               (                ),\r\n+    .sb_hsize               ( sb_ahb.hsize   ),\r\n+    .sb_htrans              ( sb_ahb.htrans  ),\r\n+    .sb_hwrite              ( sb_ahb.hwrite  ),\r\n+    .sb_hwdata              ( sb_ahb.hwdata  ),\r\n+\r\n+    .sb_hrdata              ( sb_ahb.hrdata  ),\r\n+    .sb_hready              ( sb_ahb.hready  ),\r\n+    .sb_hresp               ( sb_ahb.hresp   ),\r\n \r\n     //---------------------------------------------------------------\r\n     // LSU AHB Master\r\n     //---------------------------------------------------------------\r\n-    .lsu_haddr              ( initiator_inst.haddr       ),\r\n-    .lsu_hburst             (                       ),\r\n-    .lsu_hmastlock          (                       ),\r\n-    .lsu_hprot              (                       ),\r\n-    .lsu_hsize              ( initiator_inst.hsize       ),\r\n-    .lsu_htrans             ( initiator_inst.htrans      ),\r\n-    .lsu_hwrite             ( initiator_inst.hwrite      ),\r\n-    .lsu_hwdata             ( initiator_inst.hwdata      ),\r\n-\r\n-    .lsu_hrdata             ( initiator_inst.hrdata[63:0]),\r\n-    .lsu_hready             ( initiator_inst.hready      ),\r\n-    .lsu_hresp              ( initiator_inst.hresp       ),\r\n+    .lsu_haddr              ( lsu_ahb.haddr  ),\r\n+    .lsu_hburst             (                ),\r\n+    .lsu_hmastlock          (                ),\r\n+    .lsu_hprot              (                ),\r\n+    .lsu_hsize              ( lsu_ahb.hsize  ),\r\n+    .lsu_htrans             ( lsu_ahb.htrans ),\r\n+    .lsu_hwrite             ( lsu_ahb.hwrite ),\r\n+    .lsu_hwdata             ( lsu_ahb.hwdata ),\r\n+\r\n+    .lsu_hrdata             ( lsu_ahb.hrdata ),\r\n+    .lsu_hready             ( lsu_ahb.hready ),\r\n+    .lsu_hresp              ( lsu_ahb.hresp  ),\r\n \r\n     //---------------------------------------------------------------\r\n     // DMA Slave\r\n@@ -513,6 +524,51 @@ el2_veer_wrapper rvtop (\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hresp     = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hresp;\r\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hreadyout = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout;\r\n \r\n+    // SB and LSU AHB master mux\r\n+    ahb_lite_2to1_mux #(\r\n+        .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH (`CALIPTRA_AHB_HDATA_SIZE)\r\n+    ) u_sb_lsu_ahb_mux (\r\n+        .hclk                (clk_cg),\r\n+        .hreset_n            (cptra_noncore_rst_b),\r\n+\r\n+        // Initiator 0\r\n+        .hsel_i_0            (1'b1          ),\r\n+        .haddr_i_0           (lsu_ahb.haddr ),\r\n+        .hwdata_i_0          (lsu_ahb.hwdata),\r\n+        .hwrite_i_0          (lsu_ahb.hwrite),\r\n+        .htrans_i_0          (lsu_ahb.htrans),\r\n+        .hsize_i_0           (lsu_ahb.hsize ),\r\n+        .hready_i_0          (1'b1          ),\r\n+        .hresp_o_0           (lsu_ahb.hresp ),\r\n+        .hready_o_0          (lsu_ahb.hready),\r\n+        .hrdata_o_0          (lsu_ahb.hrdata),\r\n+\r\n+        // Initiator 1\r\n+        .hsel_i_1            (1'b1          ),\r\n+        .haddr_i_1           (sb_ahb.haddr  ),\r\n+        .hwdata_i_1          (sb_ahb.hwdata ),\r\n+        .hwrite_i_1          (sb_ahb.hwrite ),\r\n+        .htrans_i_1          (sb_ahb.htrans ),\r\n+        .hsize_i_1           (sb_ahb.hsize  ),\r\n+        .hready_i_1          (1'b1          ),\r\n+        .hresp_o_1           (sb_ahb.hresp  ),\r\n+        .hready_o_1          (sb_ahb.hready ),\r\n+        .hrdata_o_1          (sb_ahb.hrdata ),\r\n+\r\n+        // Responder\r\n+        .hsel_o              (initiator_inst.hsel  ),\r\n+        .haddr_o             (initiator_inst.haddr ),\r\n+        .hwdata_o            (initiator_inst.hwdata),\r\n+        .hwrite_o            (initiator_inst.hwrite),\r\n+        .htrans_o            (initiator_inst.htrans),\r\n+        .hsize_o             (initiator_inst.hsize ),\r\n+        .hready_o            (initiator_inst.hready),\r\n+        .hresp_i             (initiator_inst.hresp ),\r\n+        .hreadyout_i         (initiator_inst.hready),\r\n+        .hrdata_i            (initiator_inst.hrdata)\r\n+    );\r\n+\r\n     // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)\r\n     always_ff @(posedge clk or negedge cptra_rst_b) begin\r\n         if (~cptra_rst_b) begin\r\n", "test_patch": "", "modified_files": ["src/integration/rtl/caliptra_top.sv"], "lines_added": 80, "lines_removed": 24}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "lang": "sv", "rtl_files": ["src/soc_ifc/rtl/soc_ifc_top.sv"], "commit_id": "721cf1171b765533602bbadb9cc94b5f1da480ab", "timestamp": "2023-05-04T16:45:36+00:00", "pr_title": "Moving tool installation to step prior to matrix generation", "pr_body": "Moving tool installation to step prior to matrix generation.  \r\n\r\nIf the tools haven't been cached in a new branch, each test will clobber the cache, causing the tests to install the tools every time.  This re-arranges the order so that we ensure tools are installed prior to creating the test matrix.\r\n\r\nThis also modified the watchdog timer from always_comb to generate as discussed in https://github.com/chipsalliance/caliptra-rtl/issues/71", "merge_commit_sha": "bd79b88789f945225f19884ceb8d5913092fea59", "issue_title": "verilator smoke test (sha512/sha256/iccm_lock/sha_accel) failures", "issue_body": "I ran into the following issue while running some [smoke tests](https://github.com/chipsalliance/caliptra-rtl/actions/runs/4801296942/jobs/8544916590).  I did a few git bisect to see where things broke.\r\n\r\n```\r\n----------------------------------------\r\nRunning SHA512 Smoke Test             !!\r\n----------------------------------------\r\nHit max cycle count (20000000) .. stopping\r\n- /home/runner/work/caliptra-rtl/caliptra-rtl/src/integration/tb/caliptra_top_tb_services.sv:495: Verilog $finish\r\n```\r\n\r\ntestname | commit\r\n--|--\r\nsmoke_test_sha512, smoke_test_sha256, iccm_lock, smoke_test_sha_accel | 51bf68d3c2e3a1499f53d31b1b45f144726041aa \r\n\r\nWondering if these have been fixed internally?", "commit_message": "Changing $display to $error for error messages", "fix_patch": "diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv\nindex a302f0263..e6c5d156f 100644\n--- a/src/soc_ifc/rtl/soc_ifc_top.sv\n+++ b/src/soc_ifc/rtl/soc_ifc_top.sv\n@@ -691,11 +691,9 @@ assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en;\n assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart;\n assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart;\n \n-always_comb begin\n-    for (int i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n-        timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n-        timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n-    end\n+for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n+  assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n+  assign timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n end\n \n //Set WDT status reg\n", "test_patch": "diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml\nindex 0b41a2ebb..5f76eb0d1 100644\n--- a/.github/workflows/build-test-verilator.yml\n+++ b/.github/workflows/build-test-verilator.yml\n@@ -10,31 +10,9 @@ on:\n   workflow_dispatch:\n \n jobs:\n-  build_matrix:\n-    name: Build Smoke Test matrix\n-    runs-on: ubuntu-22.04\n-    outputs:\n-      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n-    steps:\n-      - uses: actions/checkout@v3\n-      - name: Install deps\n-        run: |\n-          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n-            python3-minimal python3-yaml\n-      - name: Build matrix\n-        id: output-matrix\n-        run: |\n-          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n-\n-  build_and_test:\n-    name: Verilator Smoke Test\n+  build_tools:\n+    name: Build Tools\n     runs-on: ubuntu-22.04\n-    needs: build_matrix\n-\n-    strategy:\n-      fail-fast: false\n-      matrix:\n-        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n \n     env:\n       CARGO_INCREMENTAL: 0\n@@ -135,14 +113,93 @@ jobs:\n           path: /opt/riscv\n           key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n \n+      - name: Setup riscv path\n+        run: |\n+          echo /opt/riscv/bin >> $GITHUB_PATH\n+\n+  build_matrix:\n+    name: Build Smoke Test matrix\n+    runs-on: ubuntu-22.04\n+    needs: build_tools\n+    outputs:\n+      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n+    steps:\n+      - uses: actions/checkout@v3\n+      - name: Install deps\n+        run: |\n+          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n+            python3-minimal python3-yaml\n+      - name: Build matrix\n+        id: output-matrix\n+        run: |\n+          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n+\n+  build_and_test:\n+    name: Verilator Smoke Test\n+    runs-on: ubuntu-22.04\n+    needs: build_matrix\n+\n+    strategy:\n+      fail-fast: false\n+      matrix:\n+        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n+\n+    env:\n+      # TODO: is there a way to grab these from build_tools?\n+      CARGO_INCREMENTAL: 0\n+      SCCACHE_VERSION: 0.3.3\n+      RISCV_VERSION: v12.1.0\n+      # TODO: To update to 5.006, clean up lint errors\n+      VERILATOR_VERSION: v5.002\n+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig\n+      SCCACHE_GHA_CACHE_TO: sccache-verilator-10000\n+      SCCACHE_GHA_CACHE_FROM: sccache-verilator-\n+      # Change this to a new random value if you suspect the cache is corrupted\n+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d\n+\n+    steps:\n+      - uses: actions/checkout@v3\n+        with:\n+          submodules: 'true'\n+\n+      - name: Restore Cargo index\n+        uses: actions/cache/restore@v3\n+        id: cargo_index_restore\n+        with:\n+          path: ~/.cargo/registry/index\n+          key: cargo-index-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}-${{ hashFiles('Cargo.lock') }}\n+\n+      - name: Restore sccache binary\n+        uses: actions/cache/restore@v3\n+        id: sccache_bin_restore\n+        with:\n+          path: ~/.cargo/bin/sccache\n+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore verilator dir\n+        uses: actions/cache/restore@v3\n+        id: verilator_restore\n+        with:\n+          path: /opt/verilator\n+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore Risc V Toolchain\n+        uses: actions/cache/restore@v3\n+        id: riscv_restore\n+        with:\n+          path: /opt/riscv\n+          key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n       - name: Setup verilator path\n+        run: |\n+          echo /opt/verilator/bin >> $GITHUB_PATH\n+\n+      - name: Setup riscv path\n         run: |\n           echo /opt/riscv/bin >> $GITHUB_PATH\n \n       - name: Run Caliptra Verilator Smoke Test\n         run: |\n-          # TODO: Add the run_verilator_l0_regression.py script.\n-          # Running a simple test to make sure that there aren't any elaboration issues\n           CALIPTRA_ROOT=$(pwd)\n           cd tools/scripts\n           make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name  }}\ndiff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv\nindex 6ec85caf9..964c67c01 100644\n--- a/src/integration/tb/caliptra_top_tb_services.sv\n+++ b/src/integration/tb/caliptra_top_tb_services.sv\n@@ -488,7 +488,7 @@ module caliptra_top_tb_services\n         cycleCnt <= cycleCnt+1;\n         // Test timeout monitor\n         if(cycleCnt == MAX_CYCLES && !UVM_TB) begin\n-            $display (\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n+            $error(\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n             dump_memory_contents(MEMTYPE_LMEM, 32'h8000_0110, 32'h8000_0180);\n             dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n             dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n@@ -528,12 +528,12 @@ module caliptra_top_tb_services\n             if (UVM_TB) $info(\"INFO: Detected FW write to manually end the test with FAIL; ignoring since the UVM environment will handle this.\");\n             else begin\n                 cycleCntKillReq <= cycleCnt;\n-                $display(\"* TESTCASE FAILED\");\n+                $error(\"* TESTCASE FAILED\");\n                 $display(\" -- Extending simulation for 100 clock cycles to capture ending waveform\");\n             end\n         end\n         if (|cycleCntKillReq && (cycleCnt == (cycleCntKillReq + 100))) begin\n-                $display(\"Dumping memory contents at simulation end due to FAILURE\");\n+                $error(\"Dumping memory contents at simulation end due to FAILURE\");\n                 dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF);\n                 dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n                 dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n", "modified_files": [".github/workflows/build-test-verilator.yml", "src/integration/tb/caliptra_top_tb_services.sv", "src/soc_ifc/rtl/soc_ifc_top.sv"], "lines_added": 89, "lines_removed": 34}

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-{"repo": "openhwgroup/cva6", "pr_id": 2978, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents describe the MMU design and privileged ISA details directly relevant to the page table walker operation."}
-{"repo": "openhwgroup/cva6", "pr_id": 2945, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst"], "reason": "The MMU.rst design document provides behavioral descriptions of the MMU, including TLB structures and replacement policies, which are directly relevant to the shared TLB module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2944, "selected_doc_paths": ["docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents directly describe the issue stage and execute stage, which are critical for understanding the instruction issue, operand fetching, and forwarding logic implemented in the issue_read_operands module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2916, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents cover MMU design, CSR for page table configuration, PMP for physical memory protection, and exception details, all essential for understanding and specifying the MMU behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 2886, "selected_doc_paths": ["docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/04_cv32a65x/riscv/priv.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents collectively cover the CSR definitions, trap handling, PMP, cache control, performance counters, and privileged RISC-V ISA, which are essential for a behavioral specification of the parameterized CSR register file module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2858, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents describe the CSR register layout, exception handling, MMU-related CSRs, PMP, performance counters, and custom cache control registers that are directly implemented in the csr_regfile module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2833, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md"], "reason": "This document describes the design of the instruction decode stage, which is exactly the module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 2830, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Custom_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/03_cva6_design/id_stage.md"], "reason": "These documents cover instruction decoding, CSR operations, exception/interrupt handling, custom and coprocessor instructions, and the decode stage design, which are directly relevant to the decoder module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 2809, "selected_doc_paths": [], "reason": "No available documents cover the L1.5 cache adapter or OpenPiton interface, which is the focus of the RTL module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2802, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU_list.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/PMA.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents cover the MMU design, CSR definitions, PMP/PMA access control, and the privileged RISC-V ISA specification that define the behavior of the memory management unit."}
-{"repo": "openhwgroup/cva6", "pr_id": 2751, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/01_cva6_user/Interfaces.rst"], "reason": "These documents describe the pipeline stages and interfaces that provide the signals probed by the RVFI module, essential for understanding the module's behavioral spec."}
-{"repo": "openhwgroup/cva6", "pr_id": 2728, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/RISCV_Instructions_RV32I.rst", "docs/01_cva6_user/RISCV_Instructions_RV32M.rst", "docs/01_cva6_user/RISCV_Instructions_RV32A.rst", "docs/01_cva6_user/RISCV_Instructions_RV32C.rst", "docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZba.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbc.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbs.rst", "docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst", "docs/01_cva6_user/RISCV_Instructions_RVZicond.rst", "docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst", "docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/03_cva6_design/id_stage.md"], "reason": "These documents cover the instruction decoding, CSR operations, and exception/interrupt handling that are core to the decoder module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 2697, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "The wt_axi_adapter module connects L1 caches to an AXI bus, making the AXI Interface document essential for understanding the bus protocol, while the Cache Control document covers invalidation logic and cache management relevant to the module's operation."}
-{"repo": "openhwgroup/cva6", "pr_id": 2639, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst"], "reason": "This document describes the AXI interface, which is directly relevant to the wt_axi_adapter module that bridges L1 caches to the AXI bus."}
-{"repo": "openhwgroup/cva6", "pr_id": 2599, "selected_doc_paths": ["docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/03_cva6_design/MMU.rst"], "reason": "These documents describe the majority of CSRs implemented in the module (machine, supervisor, hypervisor, debug, floating-point, performance counters, PMP, cache control) and the trap/interrupt/exception handling logic, which are essential for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 2594, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/03_cva6_design/MMU.rst", "docs/04_cv32a65x/riscv/priv.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents describe the CSR register layout, privilege levels, interrupt handling, MMU translation, and PMP configuration that directly correspond to the functionality implemented in the csr_regfile module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2589, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents provide the programmers' view of CSR registers, including machine, supervisor, virtual supervisor, and custom CSRs, as well as exception and interrupt handling, which are essential for writing a behavioral specification of the CSR register file module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2587, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md"], "reason": "These documents directly describe the CSR registers, their behavior, and related features (PMP, interrupts, performance counters) that are implemented in the csr_regfile module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2549, "selected_doc_paths": ["docs/03_cva6_design/if_stage.md"], "reason": "The instruction fetch stage document describes the branch prediction mechanism including the BHT."}
-{"repo": "openhwgroup/cva6", "pr_id": 2469, "selected_doc_paths": ["docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md"], "reason": "These documents provide detailed CSR register descriptions, exception and interrupt handling, PMP configuration, and programmer-level view, which are essential for writing a behavioral spec of the CSR register file."}
-{"repo": "openhwgroup/cva6", "pr_id": 2468, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/04_cv32a65x/riscv/priv.rst"], "reason": "These documents describe the CSR register file behavior, privilege levels, exception handling, and programmer's view, which are essential for understanding the CSR regfile module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 2429, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/AXI_Interface.rst"], "reason": "These documents cover the configuration parameters, PMA/PMP regions, and AXI interface that are defined in config_pkg.sv, which are essential for writing a behavioral spec."}
-{"repo": "openhwgroup/cva6", "pr_id": 2374, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents provide detailed descriptions of the CSR register file module and the CSR sets for various configurations, which are essential for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 2302, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/04_cv32a65x/design/source/parameters_cv32a65x.rst"], "reason": "These documents describe the configuration parameters, PMP settings, CSR registers, and design-specific parameters that directly correspond to the fields and constraints in the uvme_cva6_cfg_c class."}
-{"repo": "openhwgroup/cva6", "pr_id": 2283, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV32A60X_list.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst"], "reason": "These documents directly describe the CSR register file implementation, its registers, trap handling, and related subsystems, providing essential information for writing a behavioral spec."}
-{"repo": "openhwgroup/cva6", "pr_id": 2282, "selected_doc_paths": ["docs/04_cv32a65x/design/source/port_decoder.rst", "docs/04_cv32a65x/design/source/cva6_id_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents provide direct information about the decoder module's ports, integration in the ID stage, and exception handling, which are essential for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 2273, "selected_doc_paths": ["docs/04_cv32a65x/design/source/port_load_store_unit.rst", "docs/03_cva6_design/MMU.rst", "docs/04_cv32a65x/design/source/port_load_unit.rst", "docs/04_cv32a65x/design/source/port_store_unit.rst", "docs/04_cv32a65x/design/source/port_lsu_bypass.rst", "docs/04_cv32a65x/design/source/traps.rst"], "reason": "These documents directly describe the LSU ports, MMU interface, load/store units, bypass logic, and exception handling, which are essential for writing a behavioral specification of the load_store_unit module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2259, "selected_doc_paths": [], "reason": "No official document is relevant to the tc_sram module as it is a generic SRAM macro, not directly related to the CVA6 core documentation."}
-{"repo": "openhwgroup/cva6", "pr_id": 2248, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CVA6_user_guide.rst"], "reason": "These documents describe the configuration parameters and overall system integration for the CVA6 core, which directly correspond to the parameters defined in the RTL config package."}
-{"repo": "openhwgroup/cva6", "pr_id": 2233, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst"], "reason": "These documents directly describe the CSR register file module, the list of CSRs, and the programmer's view of CSRs, including PMP, which are implemented by the RTL module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2227, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents provide a behavioral description of the CSR register file module and the programmer-visible CSR registers implemented by this module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2170, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_caches.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents describe the cache architecture, cacheability regions, and cache control registers, which are essential for understanding the cache controller's behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 2120, "selected_doc_paths": ["docs/04_cv32a65x_design/source/mmu.rst"], "reason": "The MMU document provides a behavioral specification of the memory management unit, which includes the TLB and its operation."}
-{"repo": "openhwgroup/cva6", "pr_id": 2097, "selected_doc_paths": ["docs/04_cv32a65x_design/source/parameters_cv32a65x.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents directly describe the configuration parameters of the CV32A65X core, which are set in the RTL config package and are essential for writing a behavioral spec."}
-{"repo": "openhwgroup/cva6", "pr_id": 2035, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/CSRs.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md"], "reason": "These documents describe the CSR register file implementation, its register definitions, and behavior, which are directly relevant for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 2032, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe the instruction decode stage, decoder port, and exception handling, which are directly relevant to the decoder module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 2019, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst"], "reason": "These documents provide direct behavioral specs and CSR definitions for the CSR register file module."}
-{"repo": "openhwgroup/cva6", "pr_id": 2015, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/04_cv32a65x_design/source/port_csr_regfile.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents cover the CSR register file specification, including machine/supervisor/hypervisor CSRs, trap handling, PMP, performance counters, and cache control, which are all implemented in the csr_regfile module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1956, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV32A60X_list.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60AX_list.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/CSRs.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/04_cv32a65x_design/source/traps.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md"], "reason": "These documents provide detailed descriptions of the CSR register file, CSR lists, traps, interrupts, PMP, cache control, performance counters, and the design of the csr_regfile module itself, which are directly relevant to understanding and specifying the behavior of the RTL module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1955, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe instruction decode, decoder ports, and exception handling which are core to the decoder module's behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 1954, "selected_doc_paths": ["docs/05_cva6_apu/cva6_apu.rst", "docs/05_cva6_apu/cva6_testharness.md", "docs/04_cv32a65x_design/source/subsystem.rst"], "reason": "These documents describe the top-level APU system and subsystem integration, including FPGA-specific configurations and test harness, which are directly relevant to the ariane_xilinx module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1869, "selected_doc_paths": ["docs/04_cv32a65x_design/source/port_decoder.rst", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents directly describe the decoder module's ports, the instruction decode stage, RISC-V instruction set details, exception handling, and CSR registers, which are essential for writing a behavioral spec for the decoder."}
-{"repo": "openhwgroup/cva6", "pr_id": 1860, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst"], "reason": "These documents directly describe the CSR register file module, its programmable registers, and related exception/trap handling, which are essential for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1856, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions_RV32I.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Introduction.rst", "docs/04_cv32a65x_design/source/instructions.rst"], "reason": "The RTL module defines legal opcodes for RV32I instructions and imports various verification components, so the instruction set documents and architectural introduction are most relevant for writing a behavioral spec of this verification environment."}
-{"repo": "openhwgroup/cva6", "pr_id": 1821, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/04_cv32a65x_design/source/subsystem.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents cover the AXI interface, cache subsystem architecture, and configuration parameters, which are essential for understanding the miss handler's external interfaces and behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 1781, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/03_cva6_design/commit_stage.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents cover CSR definitions, trap/interrupt handling, PMP, performance counters, and commit stage, which are directly implemented in the csr_regfile module and necessary for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1771, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/issue_stage.md"], "reason": "The commit and issue stage documents describe the pipeline signals (commit_instr, commit_ack, issue_pointer, etc.) used by the RVFI module, which are essential for writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1750, "selected_doc_paths": ["docs/01_cva6_user/CVA6_user_guide.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/index.rst", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/pcgen_stage.md", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst"], "reason": "These documents cover the overall architecture, configuration parameters, and design of the core stages, which are essential for writing a behavioral spec of the ariane_pkg package that defines core constants and types."}
-{"repo": "openhwgroup/cva6", "pr_id": 1743, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md", "docs/04_cv32a6_design/source/CSRs.rst", "docs/04_cv32a6_design/source/csr.rst", "docs/04_cv32a6_design/source/csr_list.rst"], "reason": "These documents provide detailed descriptions of the CSR registers, their addresses, fields, and side effects, which are essential for understanding and specing the CSR register file behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 1719, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/pcgen_stage.md"], "reason": "These design documents describe the execute stage and PC generation, which directly relate to branch unit functionality including target calculation and mispredict handling."}
-{"repo": "openhwgroup/cva6", "pr_id": 1626, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md", "docs/01_cva6_user/ip-xact/cva6_csr.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/03_cva6_design/intro.rst"], "reason": "These documents provide detailed descriptions of the CSR registers, including configuration, cache control, performance counters, PMP, traps/interrupts, and the programmer's view, which are directly relevant to the csr_regfile module's functionality and would aid in writing a behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1610, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Custom_Instructions.rst"], "reason": "These documents describe the supported and custom instruction sets, which are directly relevant to generating unsupported instructions for verification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1589, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Custom_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover instruction decoding, RISC-V ISA, exception/interrupt handling, CSR operations, custom instructions, and coprocessor interface, which are all essential for the decoder's behavioral specification."}
-{"repo": "openhwgroup/cva6", "pr_id": 1546, "selected_doc_paths": ["docs/01_cva6_user/CSR_Performance_Counters.rst"], "reason": "The document directly describes the performance counters and their CSR interface, which matches the RTL module's purpose."}
-{"repo": "openhwgroup/cva6", "pr_id": 1498, "selected_doc_paths": ["docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents describe the PMP checks and configuration parameters directly used in the MMU module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1467, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md"], "reason": "The ex_stage.md document describes the execute stage, which includes the branch unit's functionality for branch target calculation, branch prediction resolution, and mispredict handling."}
-{"repo": "openhwgroup/cva6", "pr_id": 1368, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md", "docs/01_cva6_user/ip-xact/cva6_csr.rst"], "reason": "These documents directly describe CSR registers, PMP, cache control, performance counters, traps/interrupts, and the IP-XACT CSR specification, all of which are implemented in the csr_regfile module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1355, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md"], "reason": "These documents cover instruction decoding, CSR operations, exception/interrupt handling, and the decode stage, which are directly relevant to the decoder module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 1349, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/intro.rst"], "reason": "These documents describe the commit stage and execute stage, which directly involve store buffer behavior, and the introduction provides context for the design."}
-{"repo": "openhwgroup/cva6", "pr_id": 1335, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/ip-xact/cva6_csr.rst"], "reason": "These documents cover the CSR register file, PMP, performance counters, cache control, traps/interrupts, and the IP-XACT register description, which are all directly implemented in the csr_regfile module and essential for writing a behavioral spec."}
-{"repo": "openhwgroup/cva6", "pr_id": 1329, "selected_doc_paths": ["docs/01_cva6_user/CVA6_user_guide.rst", "docs/01_cva6_user/Introduction.rst", "docs/01_cva6_user/Interfaces.rst", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/index.rst", "docs/03_cva6_design/intro.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/pcgen_stage.md"], "reason": "These documents cover the top-level module architecture, interfaces, pipeline stages, and configuration, which are essential for writing a behavioral specification of the CVA6 core."}
-{"repo": "openhwgroup/cva6", "pr_id": 1302, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/PMA.rst", "docs/03_cva6_design/intro.rst"], "reason": "These documents cover cache parameters, control registers, memory attributes, and overall design that are essential for specifying the cache subsystem behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 1280, "selected_doc_paths": ["docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Custom_Instructions.rst"], "reason": "These documents describe the CVX interface and custom instruction support, which are directly related to the coprocessor module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1236, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover instruction decoding, exception/interrupt handling, the RISC-V instruction set, and the CVXIF interface, which are all directly relevant to the decoder module's functionality."}
-{"repo": "openhwgroup/cva6", "pr_id": 1123, "selected_doc_paths": [], "reason": "The module is a simulation trace utility class, not a core functional block, so no official design document directly describes it."}
-{"repo": "openhwgroup/cva6", "pr_id": 1117, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents detail the CSR register map, trap and interrupt handling, PMP configuration, performance counters, and cache control CSRs, which are the primary components of the CSR register file module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1105, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst"], "reason": "These documents cover the global configuration parameters, memory region rules (PMA/PMP), and pipeline stage definitions that are directly referenced in the ariane_pkg.sv module."}
-{"repo": "openhwgroup/cva6", "pr_id": 1103, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Core_Integration.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover the AXI interface, core integration, parameter configuration, and coprocessor interface, which are essential for writing a behavioral spec of the ariane top-level module."}
-{"repo": "openhwgroup/cva6", "pr_id": 957, "selected_doc_paths": ["docs/id_stage.md", "docs/design_spec/source/cva6_frontend.rst"], "reason": "These documents cover instruction decode and frontend logic, which directly involve the compressed decoder module."}
-{"repo": "openhwgroup/cva6", "pr_id": 937, "selected_doc_paths": ["docs/ex_stage.md"], "reason": "The multiplier module is part of the execute stage, and the ex_stage.md document describes the execute stage which includes multiplication."}
-{"repo": "openhwgroup/cva6", "pr_id": 933, "selected_doc_paths": ["docs/id_stage.md", "docs/issue_stage.md"], "reason": "The decoder module handles instruction decoding and operand fetch, which are described in the instruction decode and issue stage documents."}
-{"repo": "openhwgroup/cva6", "pr_id": 923, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module performs instruction decoding, immediate generation, and exception handling, which are described in the instruction decode stage documentation."}
-{"repo": "openhwgroup/cva6", "pr_id": 922, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module implements instruction decoding, which is the primary subject of the instruction decode stage documentation."}
-{"repo": "openhwgroup/cva6", "pr_id": 921, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The id_stage.md document directly describes the instruction decode stage, which is the primary functionality of the decoder module."}
-{"repo": "openhwgroup/cva6", "pr_id": 908, "selected_doc_paths": ["docs/specifications/cva6_requirement_specification.rst"], "reason": "This document contains the requirements for the CVA6 core, which would include specifications for the MMU module."}
-{"repo": "openhwgroup/cva6", "pr_id": 823, "selected_doc_paths": [], "reason": "None of the provided documents specifically describe the CSR register file or its behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 796, "selected_doc_paths": ["docs/ex_stage.md", "docs/issue_stage.md"], "reason": "The serdiv module is a serial divider used in the execute stage; these documents describe the execution pipeline and issue stage which are most relevant to its operation."}
-{"repo": "openhwgroup/cva6", "pr_id": 792, "selected_doc_paths": [], "reason": "None of the available documents specifically describe CSR registers or the csr_regfile module behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 765, "selected_doc_paths": ["docs/commit_stage.rst"], "reason": "The commit stage document describes how exceptions are committed and how CSR registers are updated, which is directly related to the CSR register file module."}
-{"repo": "openhwgroup/cva6", "pr_id": 756, "selected_doc_paths": ["docs/if_stage.md", "docs/pcgen_stage.md"], "reason": "The frontend module handles instruction fetch and PC generation, which are described in the if_stage and pcgen_stage documents."}
-{"repo": "openhwgroup/cva6", "pr_id": 734, "selected_doc_paths": [], "reason": "No available document covers the CSR register file module directly."}
-{"repo": "openhwgroup/cva6", "pr_id": 724, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module is the core of the instruction decode stage, and the id_stage.md document provides the behavioral specification for this stage."}
-{"repo": "openhwgroup/cva6", "pr_id": 695, "selected_doc_paths": ["docs/issue_stage.md"], "reason": "The re_name module performs register renaming, which is part of the issue stage, as described in the issue stage documentation."}
-{"repo": "openhwgroup/cva6", "pr_id": 644, "selected_doc_paths": [], "reason": "No document in the provided list is specifically relevant to the page table walker module."}
-{"repo": "openhwgroup/cva6", "pr_id": 507, "selected_doc_paths": [], "reason": "None of the provided documents cover physical memory protection (PMP) functionality; they focus on pipeline stages."}
-{"repo": "openhwgroup/cva6", "pr_id": 475, "selected_doc_paths": ["docs/_docs/arch/if_stage.md"], "reason": "The frontend module implements the instruction fetch stage, which is described in the IF stage document."}
-{"repo": "openhwgroup/cva6", "pr_id": 395, "selected_doc_paths": [], "reason": "No document covers compressed instruction decoding or the compressed decoder module."}
-{"repo": "openhwgroup/cva6", "pr_id": 180, "selected_doc_paths": [], "reason": "No available documents cover the debug module memory (dm_mem) or related debug architecture."}
-{"repo": "openhwgroup/cva6", "pr_id": 156, "selected_doc_paths": ["docs/_docs/arch/id_stage.md"], "reason": "The id_stage.md document likely covers instruction decoding, which is the core function of the compressed decoder module."}
-{"repo": "openhwgroup/cva6", "pr_id": 80, "selected_doc_paths": [], "reason": "None of the available documents specifically describe the load unit, memory subsystem, or cache/MMU interfaces needed for a behavioral spec of this RTL module."}
-{"repo": "openhwgroup/cva6", "pr_id": 74, "selected_doc_paths": [], "reason": "No available official document directly describes the cache controller module or its behavior."}
-{"repo": "openhwgroup/cva6", "pr_id": 27, "selected_doc_paths": [], "reason": "None of the available documents cover the multiplier or divider implementation details needed for a behavioral spec of this RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3204, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/03_cva6_design/id_stage.md"], "reason": "These documents cover instruction decoding, exception handling, and CSR interactions, which are essential for understanding and specifying the decoder module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 3189, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst"], "reason": "The MMU design document provides the architectural description of the Memory Management Unit, which includes the TLB, and is essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 3137, "selected_doc_paths": ["docs/01_cva6_user/PMP.rst"], "reason": "The PMP.rst document describes the Physical Memory Protection mechanism, which is the core functionality implemented in the pmp_data_if module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3292, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst"], "reason": "The execute stage document describes FPU integration and the RISC-V instructions document covers the floating-point operations implemented by the FPU wrapper."}
+{"repo": "openhwgroup/cva6", "pr_id": 3191, "selected_doc_paths": ["docs/03_cva6_design/issue_stage.md", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "The issue_stage document directly describes the instruction issue and operand fetching logic, while the CVX interface document details the custom coprocessor interface used by this module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3168, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents directly describe the decode and issue stages, and the CVX interface coprocessor, which are integral to the id_stage module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 3042, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/PMA.rst"], "reason": "These documents describe the configuration parameters, AXI interface settings, and PMA rules directly relevant to the RTL configuration package."}
+{"repo": "openhwgroup/cva6", "pr_id": 3091, "selected_doc_paths": ["docs/03_cva6_design/issue_stage.md", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents directly describe the issue stage, CVXIF interface, configuration parameters, and the interfaces to commit and execute stages, which are essential for understanding the module's behavior and writing a spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 3131, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Interfaces.rst"], "reason": "These documents describe the commit stage, issue stage, decode stage, CSR registers, and interfaces, which are directly relevant to the signals and functionality captured by the RVFI module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3107, "selected_doc_paths": [], "reason": "No official documents explicitly cover the Instruction Trace Interface (ITI) module, which is the subject of the RTL file."}
+{"repo": "openhwgroup/cva6", "pr_id": 3171, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents provide the instruction set architecture, exception/interrupt handling, and CSR behavior that the decoder module implements."}
+{"repo": "openhwgroup/cva6", "pr_id": 3082, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst"], "reason": "The module is an AXI arbiter for the cache subsystem, so the AXI interface document is most relevant for understanding the AXI protocol used."}
+{"repo": "openhwgroup/cva6", "pr_id": 2978, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/06_cv64a6_mmu/riscv/priv.rst", "docs/01_cva6_user/PMP.rst"], "reason": "These documents cover the MMU design, privileged RISC-V ISA for page tables, and PMP integration, all directly relevant to the page table walker module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2945, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst"], "reason": "The MMU design document directly describes the Memory Management Unit including TLB behavior, which is essential for writing a behavioral spec for the shared TLB module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3037, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/user_cfg_doc.rst"], "reason": "These documents describe the configuration parameters, PMP, PMA, cache control, and user configuration, which are directly relevant to the RTL configuration package."}
+{"repo": "openhwgroup/cva6", "pr_id": 2833, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "The id_stage module handles instruction decode and issue; the design document id_stage.md directly describes it, issue_stage.md covers the following pipeline stage, RISCV_Instructions.rst provides instruction encodings used by the decoder, and CVX_Interface_Coprocessor.rst documents the CVXIF interface used for compressed instructions."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2830, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents describe instruction decode, RISC-V instruction sets, exception/interrupt handling, CSR operations, and the coprocessor interface, which are all critical for understanding and specifying the decoder module."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2802, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "The MMU design document provides architecture details, the CSR document describes MMU-related registers, and the privileged specification defines the RISC-V MMU behavior."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2549, "selected_doc_paths": ["docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/pcgen_stage.md"], "reason": "These documents describe the instruction fetch stage and PC generation, which include branch prediction details relevant to the BHT module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2751, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents describe the pipeline stages and CSR behavior that are probed by the RVFI module, providing essential context for writing its behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 2594, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md"], "reason": "These documents comprehensively describe the CSR registers, PMP configuration, performance counters, cache control, and trap/interrupt handling that are directly implemented in the CSR register file module, providing essential reference for writing a behavioral specification."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2599, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/04_cv32a65x/riscv/priv.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst"], "reason": "These documents provide detailed descriptions of the CSR registers, privileged architecture, and exception handling, which are essential for writing a behavioral specification of the CSR register file."}
+{"repo": "openhwgroup/cva6", "pr_id": 2429, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/user_cfg_doc.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CVA6_user_guide.rst"], "reason": "These documents describe the configuration parameters, PMA/PMP settings, and overall CVA6 user configuration, directly matching the parameters defined in config_pkg.sv."}
+{"repo": "openhwgroup/cva6", "pr_id": 2589, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst"], "reason": "These documents describe the CSR register map, privilege levels, PMP, performance counters, cache control, and trap handling, which are essential for writing a behavioral specification of the CSR register file module."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2374, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x/design/source/port_csr_regfile.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents provide the behavioral specification of the CSR register file, its ports, CSR listings, PMP, performance counters, and trap/interrupt handling, which are directly relevant to the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2587, "selected_doc_paths": ["docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe the CSR registers and their behavior implemented in the RTL module, including machine, supervisor, hypervisor, debug, FPU, PMP, cache control, performance counters, and trap handling."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2283, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x/design/source/port_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/04_cv32a65x/riscv/priv.rst"], "reason": "These documents provide direct specification of the CSR regfile module, its port interfaces, the CSR register descriptions, and the RISC-V privileged architecture, which are essential for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2282, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x/design/source/cva6_id_stage.rst", "docs/04_cv32a65x/design/source/port_decoder.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/RISCV_Instructions.rst"], "reason": "These documents directly describe the instruction decode stage, decoder ports, RISC-V instruction set, and exception handling, which are core functions of the decoder module."}
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+{"repo": "openhwgroup/cva6", "pr_id": 1954, "selected_doc_paths": ["docs/04_cv32a65x_design/source/subsystem.rst", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents provide essential information on the system integration, AXI bus interface, and configuration parameters needed to understand the top-level FPGA wrapper module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1955, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents cover the instruction decode stage, decoder ports, supported instructions, and exception handling, which are essential for specifying the decoder module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1869, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents directly describe the decoder module's functionality, ports, instruction decoding, and exception handling, which are essential for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2019, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst"], "reason": "These documents provide a behavioral description of the CSR register file module and its register map, directly aiding in writing a spec."}
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+{"repo": "openhwgroup/cva6", "pr_id": 1781, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents directly describe the CSR registers, trap handling, PMP, performance counters, and cache control CSRs implemented by the csr_regfile module, providing essential behavioral specification details."}
+{"repo": "openhwgroup/cva6", "pr_id": 1719, "selected_doc_paths": ["docs/03_cva6_design/pcgen_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents describe the PC generation and execute stages, which directly cover branch target calculation, misprediction handling, and the interaction with the branch predictor, essential for a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 1750, "selected_doc_paths": ["docs/03_cva6_design/index.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "The design index provides an overview of the pipeline stages and components that use the types defined in ariane_pkg.sv, while the parameters configuration document explains the configuration constants that are central to the package."}
+{"repo": "openhwgroup/cva6", "pr_id": 1856, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/CVA6_user_guide.rst", "docs/02_cva6_requirements/cva6_requirements_specification.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "The verification environment package includes agents for AXI, CVXIF, clock/reset, and CSR register models; these documents provide interface specifications and overall requirements needed for behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1771, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents describe the commit, issue, and execute stages which provide the signals (commit_instr, issue_pointer, lsu_ctrl) mapped in the RVFI wrapper."}
+{"repo": "openhwgroup/cva6", "pr_id": 1589, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst"], "reason": "These documents directly cover instruction decoding and the supported RISC-V instruction set, which are essential for specifying the decoder module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1546, "selected_doc_paths": ["docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents directly describe the performance counter CSRs, their event selection, and configuration parameters relevant to the perf_counters module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1610, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents define the supported RISC-V instructions and configuration parameters, which are essential for understanding which instructions are considered unsupported in the verification module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1626, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md"], "reason": "These documents provide the programmers view and detailed specifications of the CSR registers, including address mappings, behavior, and side effects, which are essential for writing a behavioral spec of the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1743, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst"], "reason": "These documents directly describe the CSRs implemented in the module, including their addresses, fields, and behavior for PMP, cache control, performance counters, and trap handling, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1467, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md"], "reason": "The ex_stage.md document describes the execute stage, which includes the branch unit's branch resolution, target calculation, and misprediction handling."}
+{"repo": "openhwgroup/cva6", "pr_id": 1355, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents cover instruction decoding, RISC-V instruction set, exception/interrupt handling, and CSR interactions, which are core to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 1368, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md"], "reason": "These documents describe the CSR registers, their fields, trap/interrupt behavior, PMP configuration, cache control, and performance counters, which are all implemented in the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1335, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents directly describe the CSRs, PMP behavior, and exception/interrupt handling implemented in the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1498, "selected_doc_paths": ["docs/01_cva6_user/PMP.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents describe PMP checks and the TLB behavior for instruction and data paths, which are core components of the MMU module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1349, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents cover the commit stage and execute stage, which include the store buffer logic and memory interface."}
+{"repo": "openhwgroup/cva6", "pr_id": 1329, "selected_doc_paths": ["docs/01_cva6_user/CVA6_user_guide.rst", "docs/01_cva6_user/Interfaces.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/index.rst", "docs/03_cva6_design/intro.rst", "docs/01_cva6_user/Core_Integration.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover the top-level module integration, interfaces, parameters, and design overview, which are essential for writing a behavioral spec for the cva6.sv top-level module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1302, "selected_doc_paths": ["docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents describe cache control and configuration parameters, which are directly relevant to the cache subsystem definitions in std_cache_pkg."}
+{"repo": "openhwgroup/cva6", "pr_id": 957, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The ID stage document covers instruction decode, including compressed instruction decoding, which is directly relevant to the compressed decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 937, "selected_doc_paths": ["docs/ex_stage.md"], "reason": "The multiplier module is part of the execution stage, and the execute stage document provides behavioral specification for it."}
+{"repo": "openhwgroup/cva6", "pr_id": 1236, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents cover instruction decoding, supported instructions, exception handling, coprocessor offloading, and configuration parameters, which are all central to the decoder module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1280, "selected_doc_paths": ["docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Custom_Instructions.rst", "docs/01_cva6_user/Interfaces.rst"], "reason": "These documents describe the CVX interface, custom instructions, and overall interfaces that are directly used by the example coprocessor module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1105, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents describe the configuration parameters, PMA/PMP rules, and cache configuration that are directly used in the ariane_pkg.sv package."}
+{"repo": "openhwgroup/cva6", "pr_id": 923, "selected_doc_paths": ["docs/id_stage.md", "docs/issue_stage.md", "docs/specifications/cva6_requirement_specification.rst"], "reason": "The instruction decode stage document directly describes the decoder module, the issue stage document covers scoreboard interaction, and the requirement specification provides behavioral specifications."}
+{"repo": "openhwgroup/cva6", "pr_id": 1103, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Core_Integration.rst", "docs/01_cva6_user/Interfaces.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Introduction.rst"], "reason": "These documents describe the external interfaces (AXI, CVX), integration guidance, configuration parameters, and overall module context needed to write a behavioral spec for the top-level ariane module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1123, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe RISC-V instruction formats, CSR definitions, privilege levels, and programmer's view, which are directly referenced by the instr_trace_item class for formatting and tracing instruction execution."}
+{"repo": "openhwgroup/cva6", "pr_id": 922, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The id_stage.md document describes the instruction decode stage, which directly corresponds to the functionality of the decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 921, "selected_doc_paths": ["docs/id_stage.md", "docs/specifications/cva6_requirement_specification.rst"], "reason": "The id_stage.md directly documents the instruction decode stage, and the requirement specification provides functional requirements relevant to the decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1117, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe the behavior and programming model of the CSRs implemented in the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 908, "selected_doc_paths": ["docs/specifications/cva6_requirement_specification.rst"], "reason": "The requirement specification likely includes high-level behavior and requirements for the MMU, which is essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 933, "selected_doc_paths": ["docs/id_stage.md", "docs/issue_stage.md"], "reason": "The decoder module performs instruction decoding and issues instructions to the scoreboard, which are the main topics of the id_stage and issue_stage documents."}
+{"repo": "openhwgroup/cva6", "pr_id": 823, "selected_doc_paths": [], "reason": "None of the available documents cover the CSR register file specifically; they focus on pipeline stages and SoC, which are not directly relevant to the CSR module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 765, "selected_doc_paths": [], "reason": "None of the available documents provide a behavioral spec for the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 756, "selected_doc_paths": ["docs/if_stage.md", "docs/pcgen_stage.md", "docs/id_stage.md"], "reason": "These documents cover instruction fetch, PC generation, and instruction decode, which are the main functionalities of the frontend module."}
+{"repo": "openhwgroup/cva6", "pr_id": 724, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module is the core of the instruction decode stage, and the id_stage.md document directly describes the decode stage logic and its interaction with other stages."}
+{"repo": "openhwgroup/cva6", "pr_id": 796, "selected_doc_paths": ["docs/ex_stage.md"], "reason": "The serdiv module is a serial divider used in the execute stage; the ex_stage document describes the execute stage where this divider resides."}
+{"repo": "openhwgroup/cva6", "pr_id": 507, "selected_doc_paths": [], "reason": "No document in the list covers PMP or memory protection, so none are relevant to the RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 695, "selected_doc_paths": ["docs/issue_stage.md"], "reason": "The re_name module produces renamed instructions that are passed to the issue stage, which is documented in issue_stage.md."}
+{"repo": "openhwgroup/cva6", "pr_id": 792, "selected_doc_paths": ["docs/commit_stage.rst", "docs/ex_stage.md"], "reason": "The commit stage handles exception and commit acknowledgment updates to CSRs like instret, and the execute stage covers CSR operations (CSR_WRITE, CSR_SET, etc.) and exception handling, both critical for a behavioral spec of the CSR register file."}
+{"repo": "openhwgroup/cva6", "pr_id": 644, "selected_doc_paths": [], "reason": "None of the available documents describe the page table walker or memory management unit, which is the subject of the RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 156, "selected_doc_paths": [], "reason": "No document in the list covers the compressed decoder or RISC-V compressed instruction decoding."}
+{"repo": "openhwgroup/cva6", "pr_id": 395, "selected_doc_paths": ["docs/_docs/arch/id_stage.md"], "reason": "The ID stage document likely describes instruction decoding including compressed instruction support, which is directly relevant to the compressed decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 74, "selected_doc_paths": [], "reason": "No document addresses cache controller behavior or design."}
+{"repo": "openhwgroup/cva6", "pr_id": 475, "selected_doc_paths": ["docs/_docs/arch/if_stage.md", "docs/_docs/arch/pcgen_stage.md"], "reason": "The frontend module handles instruction fetch and PC generation; these documents directly describe the IF stage and PCgen stage which are core components of this RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 180, "selected_doc_paths": [], "reason": "None of the available documents cover the debug subsystem or the memory module for execution-based debug clients."}
+{"repo": "openhwgroup/cva6", "pr_id": 80, "selected_doc_paths": ["docs/_docs/arch/ex_stage.md"], "reason": "The ex_stage document covers the execute stage of the pipeline, which includes the load unit, making it the most relevant source for understanding load behavior and interface."}
+{"repo": "openhwgroup/cva6", "pr_id": 734, "selected_doc_paths": [], "reason": "No official document directly describes the CSR register file behavior; all available documents cover pipeline stages or system-level topics."}
+{"repo": "openhwgroup/cva6", "pr_id": 27, "selected_doc_paths": ["docs/_docs/arch/ex_stage.md"], "reason": "The execute stage document likely describes the integration of the multiplier and divider units within the pipeline, which is essential for a behavioral spec of this module."}

s2/openhwgroup__cva6/openhwgroup__cva6_s2_04_review_results.jsonl

@@ -0,0 +1,106 @@
+{"repo": "openhwgroup/cva6", "pr_id": 3137, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses 'shall' to describe that an incoming page fault must not be overwritten, includes no patch-specific signal names or line numbers, and directly addresses the functional area modified by the patch (instruction fetch exception priority)."}
+{"repo": "openhwgroup/cva6", "pr_id": 3042, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the required behavior using normative language, does not contain any patch-specific implementation details, and includes behavioral assertions covering the modified AXI interface and executable region rules."}
+{"repo": "openhwgroup/cva6", "pr_id": 3189, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language, does not contain any signal names or expressions from the patch, and includes behavioral assertions about G-stage flush operations which directly relate to the functional area modified by the patch (the vaddr_vpn_match assignment for hypervisor extension)."}
+{"repo": "openhwgroup/cva6", "pr_id": 3168, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct behavior, avoids patch-specific details, and includes a behavioral assertion that CV-X-IF operation requires RVC to be enabled."}
+{"repo": "openhwgroup/cva6", "pr_id": 3091, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification accurately describes the expected issue and forwarding behavior using normative language, contains no patch-specific details, and includes behavioral assertions about ALU-ALU bypass that directly relate to the removed condition."}
+{"repo": "openhwgroup/cva6", "pr_id": 3292, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language (must/shall/should), contains no patch-specific signal names or expressions, and includes behavioral descriptions that cover the modification area (exception output initialization, implying all fields are driven)."}
+{"repo": "openhwgroup/cva6", "pr_id": 3131, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the expected AMO write data logging behavior without leaking implementation details."}
+{"repo": "openhwgroup/cva6", "pr_id": 3082, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, avoids patch-specific identifiers, and includes a behavioral assertion about uncacheable read alignment."}
+{"repo": "openhwgroup/cva6", "pr_id": 3204, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification does not explicitly require the rd field to be zero for HFENCE.VVMA/HFENCE.GVMA instructions, which is the core behavioral assertion added by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2945, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses 'shall' and 'must' to describe correct behavior, contains no signal names or line numbers from the patch, and includes a behavioral description of the ASID matching condition which is the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 3191, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not explicitly assert that results from exception instructions are invalid for forwarding, which is the core behavioral change of the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 3107, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses must/shall/should statements, contains no patch-specific details, and includes behavioral assertions about valid_o signal assignment, which is the functional area of the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 2978, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses prescriptive language like shall/must, avoids patch-specific signals, and includes assertions on store faults in G-translation and instruction execution permission."}
+{"repo": "openhwgroup/cva6", "pr_id": 2809, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must/should, contains no patch details, and includes invalidation handling behavioral assertions directly related to the patch area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2697, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, avoids patch-specific signal names or expressions, and includes a behavioral assertion about address casting related to the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2833, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses must/shall/should to describe correct behavior, contains no signal names or expressions from the patch, and includes behavioral assertions about the RVC-disabled case, which is the functional area of the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2916, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses prescriptive language and does not reference the bug; it omits patch-specific signal names; and it includes assertions about ASID matching relevant to the fixed connection."}
+{"repo": "openhwgroup/cva6", "pr_id": 3171, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses 'shall' to mandate that unsupported opcode fields (including the missing bit [24:22] check for CPOPW/CLZW/CTZW) result in an illegal instruction, which directly captures the behavioral fix without leaking patch details."}
+{"repo": "openhwgroup/cva6", "pr_id": 3037, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses prescriptive language, contains no patch details, and includes behavioral assertions directly related to the configuration parameters modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 3108, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification describes correct interrupt handling behavior but lacks a behavioral assertion about the interrupt cause encoding format, which is the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2830, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall/should, contains no patch-specific identifiers, and includes behavioral assertions about tinst default value addressing the combinational loop fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 2549, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall to describe correct behavior, contains no patch details, and includes a behavioral assertion about combinational prediction for all instruction slots, directly covering the fix area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2728, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification does not explicitly state the encoding constraint (bit 25 must be zero for RV32) for BCLRI, BINVI, BSETI, BEXTI, and RORI, which is the functional area modified by the patch; thus it is not sufficient for diagnosing a bug in that area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2944, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, contains no patch-specific signal names or expressions, and includes behavioral assertions about CVXIF handling that relate to the patch's functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2858, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification lacks a behavioral assertion directly covering the instruction retired counter increment logic modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2429, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the behavior using shall/should, contains no patch details, and includes assertions about the modified execute region function."}
+{"repo": "openhwgroup/cva6", "pr_id": 2886, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct behavior, does not contain patch-specific identifiers, and includes behavioral assertions about address translation enable, which is the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2639, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification describes correct behavior without bug language, contains no patch-specific signals, and covers burst length calculation related to the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 2248, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' and 'must' correctly, contains no patch details, and includes a direct description of NrPMPEntries which is the parameter changed in the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2802, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes MMU behavior with must/should, avoids patch detail leakage, and includes assertions about misaligned exception handling."}
+{"repo": "openhwgroup/cva6", "pr_id": 2751, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "Spec lacks explicit behavioral assertion about rs1/rs2 width being XLEN, which is the functional area fixed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2259, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes SRAM initialization behavior without leaking patch details and provides sufficient information for diagnosis."}
+{"repo": "openhwgroup/cva6", "pr_id": 2273, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses mandatory language, contains no patch-specific details, and includes a direct behavioral assertion about page-fault generation for overflow."}
+{"repo": "openhwgroup/cva6", "pr_id": 2469, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not include a behavioral assertion about the pmpaddr read value being dependent on the address mode (e.g., setting LSB to 1 for NA4/NAPOT), which is essential to diagnose the bug fixed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2599, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (must, shall) without patch-specific terms, contains no signal names or line numbers from the patch, and includes behavioral assertions on trap handling that directly cover the modified functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2589, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses prescriptive language to describe correct CSR behavior, does not contain any patch-specific identifiers, and includes behavioral descriptions of PMP address lock rules that relate to the modified functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2120, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe behavior, avoids patch-specific signal names, and includes assertions about update only on miss."}
+{"repo": "openhwgroup/cva6", "pr_id": 2302, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification retains the removed field 'mode_h_supported' from the class, which constitutes patch leakage."}
+{"repo": "openhwgroup/cva6", "pr_id": 2282, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses must/shall to describe behavior, contains no patch-specific details, and includes assertions about bitmanipulation instruction decoding that cover the fixed area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2170, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (shall) and omits any bug references; no patch-specific identifiers are present; it includes behavioral assertions on cache hit data handling related to the offset calculation modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2374, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses normative language, contains no patch artifacts, and includes a behavioral assertion about virtual instruction exception that covers the modified privilege check condition."}
+{"repo": "openhwgroup/cva6", "pr_id": 2587, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses proper normative language, avoids patch-specific details, and includes a behavioral assertion about trap delegation under virtualization, directly covering the fixed area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2097, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "Specification uses shall/must for configuration values, no patch-specific symbols, and includes behavioral assertion for HPDCACHE."}
+{"repo": "openhwgroup/cva6", "pr_id": 2594, "passed": false, "checks": {"describes_correct_behavior": false, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification lacks required modal verbs (must/shall/should) for normative description, though it correctly describes behavior without patch leakage and covers the trap-to-supervisor logic modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1955, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "Specification uses 'shall'/'should' to describe correct behavior, contains no patch details, and includes behavioral assertions covering illegal instruction detection for hypervisor extensions."}
+{"repo": "openhwgroup/cva6", "pr_id": 2233, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall for correct behavior, contains no patch-specific identifiers, and includes a general assertion that writes to read-only fields are ignored, which covers the TW field fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 2283, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, avoids patch details, and contains a clear statement about the reserved MPP value when RVH is disabled, which is the area fixed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 2227, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct CSR access behavior, avoids patch-specific signal names, and includes a behavioral assertion that unimplemented CSRs cause an exception, directly covering mcounteren's conditional existence."}
+{"repo": "openhwgroup/cva6", "pr_id": 2032, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses 'shall' to describe correct behavior, avoids Verilog-specific signals from the patch, and includes a behavioral assertion about ZEXT.H decoding that directly covers the patch's functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 1719, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification describes correct alignment requirements using shall/should, avoids patch-specific identifiers, and includes the exact behavioral rule for misaligned exceptions when RVC is disabled."}
+{"repo": "openhwgroup/cva6", "pr_id": 2468, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses descriptive language and covers the mcountinhibit CSR behavior in reset and inhibition context, without leaking patch details."}
+{"repo": "openhwgroup/cva6", "pr_id": 2035, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification lacks an explicit behavioral assertion about clamping MPP to a legal value when RVH is not enabled, which is the functional area addressed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1954, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification does not contain an explicit behavioral assertion regarding the dependency between NBSlave and AXI ID width, which is the functional area addressed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1860, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the CSR behavior using normative language, contains no patch-specific signal names or line numbers, and includes behavioral assertions about the mcountinhibit register and counter inhibition directly related to the modified functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 1869, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall to describe correct behavior, contains no patch-specific identifiers, and includes a behavioral assertion about SFENCE.VMA privilege checking."}
+{"repo": "openhwgroup/cva6", "pr_id": 2019, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct PMP WARL behavior, contains no patch-specific details, and includes a behavioral assertion about the collective WARL for access type fields."}
+{"repo": "openhwgroup/cva6", "pr_id": 1781, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "Generated specification uses normative language, avoids patch-specific details, and includes behavioral assertions about MPP handling during MRET and hardwiring when U-mode absent."}
+{"repo": "openhwgroup/cva6", "pr_id": 1956, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, avoids patch-specific symbols, and includes assertions about ASID width directly related to the patch's functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 2015, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the PMP lock behavior using 'shall' and includes a behavioral assertion about locked TOR entries without leaking patch details."}
+{"repo": "openhwgroup/cva6", "pr_id": 1821, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification lacks a behavioral assertion about the AXI ID assignment for AMO requests, which is the core fix in the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1467, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the behavior using shall/must, contains no patch signal names, and includes the key assertion about misaligned exception only for taken branches/unconditional jumps."}
+{"repo": "openhwgroup/cva6", "pr_id": 1546, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the counter increment behavior using mandatory language, avoids patch-level details, and includes a behavioral assertion for the counter increment conditions."}
+{"repo": "openhwgroup/cva6", "pr_id": 1750, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification does not contain a behavioral assertion directly addressing the self-referencing parameter derivation issue fixed by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1743, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct cycle counter inhibition behavior, contains no patch-specific details, and includes a behavioral assertion that directly relates to the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 1589, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not explicitly assert that ZEXTH is only legal for RV32, which is the exact functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1856, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to define correct behavior, does not contain any patch-specific details, and includes a behavioral requirement that the memory model shall support ELF initialization via DPI functions, which is the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1610, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language, avoids explicit patch details, and includes a behavioral assertion about the corrected constraint on instr_bin[6:5] for the c_op==2'b01 case."}
+{"repo": "openhwgroup/cva6", "pr_id": 1349, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes ready signal behavior using shall statements, contains no patch leakage, and includes a behavioral assertion on the ready condition modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1368, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, avoids patch-specific identifiers, and includes a direct statement about hardwiring reserved PMPCFG bits to 0."}
+{"repo": "openhwgroup/cva6", "pr_id": 1355, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification describes correct decoder behavior, avoids patch-specific details, and includes assertions about atomic operation width legality tied to XLEN."}
+{"repo": "openhwgroup/cva6", "pr_id": 1335, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the PMP write blocking behavior without reusing patch-specific identifiers, and includes a behavioral assertion directly covering the fixed logic."}
+{"repo": "openhwgroup/cva6", "pr_id": 1302, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses normative-like language, avoids patch details, and includes behavioral description of one_hot_to_bin function relevant to the loop variable type fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 1771, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses must/shall/should to describe correct behavior without mentioning bugs; no signal names from the patch appear in the spec; the spec includes behavioral assertions about configuration parameters, which is the functional area of the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1498, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses must/shall/should, avoids patch details, and includes behavioral assertions about access fault reporting for PMP violations."}
+{"repo": "openhwgroup/cva6", "pr_id": 1280, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must to describe expected behavior, contains no patch-specific details, and includes assertions about the combinational logic that addresses the reordered assignment."}
+{"repo": "openhwgroup/cva6", "pr_id": 1626, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification lacks an explicit behavioral assertion that mstatus.UBE is forced to zero, which is the exact modification in the patch, making it insufficient for diagnosing the issue."}
+{"repo": "openhwgroup/cva6", "pr_id": 1105, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses proper modal verbs to describe correct behavior, does not leak patch details, and includes a behavioral assertion about AXI_USER_WIDTH directly related to the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1329, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall to describe behavior, contains no patch-specific details, and includes a behavioral assertion about performance counters being implemented and inhibit-able, which directly relates to the modified area."}
+{"repo": "openhwgroup/cva6", "pr_id": 1103, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' and 'must' to describe behavior, avoids patch-specific identifiers beyond standard signal names, and includes behavioral assertions about the configurable AXI interface directly related to the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 1236, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification contains signal names (illegal_instr_non_bm, illegal_instr_bm) from the patch, violating no_patch_leakage."}
+{"repo": "openhwgroup/cva6", "pr_id": 957, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly uses prescriptive language (e.g., shall), does not contain code-level details from the patch, and includes behavioral assertions for the XLEN-dependent decompression that the patch addresses."}
+{"repo": "openhwgroup/cva6", "pr_id": 922, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must for correct behavior, contains no patch details, and includes a behavioral assertion about DRET legality in debug mode."}
+{"repo": "openhwgroup/cva6", "pr_id": 937, "passed": false, "checks": {"describes_correct_behavior": false, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification does not use must/shall/should to describe correct behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1117, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language and correctly describes minstreth write behavior without leaking patch details, and includes a direct assertion about the modified functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 1123, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the behavioral requirements for instruction trace formatting, including proper handling of FP store instructions, without referencing the patch or bug."}
+{"repo": "openhwgroup/cva6", "pr_id": 923, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch-specific details, and includes behavioral description of fence/fence.i decoding without illegal field checks."}
+{"repo": "openhwgroup/cva6", "pr_id": 933, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall to describe correct behavior, avoids patch details (signal names, line numbers), and includes at least one behavioral assertion about SFENCE.VMA privilege level enforcement related to the patch's functional area."}
+{"repo": "openhwgroup/cva6", "pr_id": 921, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the decoder behavior using must/shall/should, does not contain explicit patch details, and includes behavioral assertions about SFENCE.VMA privilege checking directly related to the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 765, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the WFI behavior as waking only on enabled interrupts, uses normative language, avoids patch-specific signal names, and provides a behavioral assertion directly related to the modified WFI logic."}
+{"repo": "openhwgroup/cva6", "pr_id": 507, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language, avoids patch details, and includes behavioral assertions related to the TOR mode fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 796, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must to describe correct RISC-V division behavior and contains no patch-specific signals; it includes behavioral assertions about signed division, which is the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 823, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch-specific details, and includes a behavioral assertion that illegal access type combinations (R=0,W=1) are ignored, directly covering the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 644, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must to describe correct behavior, does not include any patch-specific signal names or implementation details, and includes a behavioral description of flush handling directly related to the patch's functional change."}
+{"repo": "openhwgroup/cva6", "pr_id": 756, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses mandatory language like 'shall', avoids patch-specific signal names, and includes a behavioral assertion about preserving branch predictions for unaligned fetches, directly covering the patch's function."}
+{"repo": "openhwgroup/cva6", "pr_id": 908, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'must' and 'shall' to describe correct behavior without mentioning bugs or fixes; it does not contain any signal names, variable names, or line numbers from the patch; and it includes a behavioral assertion that a PMP violation during PTW causes an access-fault exception, which directly addresses the functional area modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 395, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly states that C.FLDSP is always legal, matching the patch that removed the illegal instruction check for ft0 destination."}
+{"repo": "openhwgroup/cva6", "pr_id": 792, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch details, and correctly describes vectored mode selection based on target privilege level as required by the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 156, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses shall/should correctly, contains no patch-specific details, and includes behavioral assertions covering the instructions modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 74, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses prescriptive language to describe correct behavior, contains no patch-specific details, and includes assertions directly related to the MSHR handling fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 180, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language for correct behavior, contains no patch code details, and includes a behavioral assertion about the special handling for A0 register access."}
+{"repo": "openhwgroup/cva6", "pr_id": 695, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses appropriate modal verbs and no negative language, contains no names or expressions from the patch header, and provides behavioral assertions about the rename module which is the functional area of the patched file."}
+{"repo": "openhwgroup/cva6", "pr_id": 27, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall/should, contains no patch details, and includes a flush behavior section directly addressing the patch's functional change."}
+{"repo": "openhwgroup/cva6", "pr_id": 724, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language without referencing bugs or patch signals, and includes behavioral assertions covering the FENCE.I immediate check and system instruction default case."}
+{"repo": "openhwgroup/cva6", "pr_id": 80, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses normative language, does not leak patch details, and includes behavioral description of sign extension pipelining related to the fix."}
+{"repo": "openhwgroup/cva6", "pr_id": 475, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not explicitly state that a return instruction should not generate a branch prediction when the RAS prediction is invalid, which is the exact behavior modified by the patch."}
+{"repo": "openhwgroup/cva6", "pr_id": 734, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not explicitly assert the XLEN-dependent availability of PMPCFG1 and PMPCFG3 CSRs for read, which is the functional area modified by the patch."}