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@@ -63,3 +63,5 @@ collect/lowRISC/lowRISC__ibex_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -te
 collect/lowRISC/lowRISC__ibex_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
 collect/openhwgroup/openhwgroup__cva6_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -text
 collect/openhwgroup/openhwgroup__cva6_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
+s2/lowRISC__ibex/lowRISC__ibex_s2_01_materials.jsonl filter=lfs diff=lfs merge=lfs -text
+s2/openhwgroup__cva6/openhwgroup__cva6_s2_01_materials.jsonl filter=lfs diff=lfs merge=lfs -text

collect/chipsalliance/chipsalliance__caliptra-rtl_s01_06_single_rtl_candidates.jsonl

@@ -1,4 +1,4 @@
-{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "lang": "sv", "rtl_files": ["src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "commit_id": "55f5f95fb2b352be2f9c6482142fcc63763e0d31", "timestamp": "2024-03-29T19:25:01+00:00", "pr_title": "[UVM] Implement mailbox sanitize feature in val fw to suppress regression failure", "pr_body": "Implement a firmware feature (for the validation code used in UVM tests) to sanitize the mailbox after detecting double-bit ECC error, to mirror the workaround required in 1.1 Firmware as per https://github.com/chipsalliance/caliptra-rtl/issues/399.\r\n\r\nThis is a temporary solution that should be removed for 2.0, as the mailbox should be modified to avoid spurious data prefetches.", "issue_title": "Caliptra uC is reading one extra entry from Mailbox SRAM causing unexpected ECC errors", "issue_body": "Hi, We are bringing up Mailbox testcases and observed the following scenario where an unexpected ECC error is getting fired. Below is our sequence.\r\n\r\n1. SOC acquires the MBOX lock by reading MBOX_LOCK register. It returns 0 indicating that the lock has been acquired by SOC.\r\n2. SOC writes MBOX command register.\r\n3. SOC writes MBOX_DLEN register to 8 indicating that it has 8 bytes of data to write.\r\n4. SOC writes MBOX_DATAIN register twice. This causes two writes to SRAM mailbox at addresses 0x0 and 0x1.\r\n5. SOC writes MBOX_EXECUTE to 1 in order for uC to process the mailbox command.\r\n6. When the mailbox state machine is in MBOX_EXECUTE_UC state, we are observing that Caliptra is reading SRAM mailbox at addresses 0x0, 0x1 and 0x2. The first two are expected as DLEN is 8. However the data at address 0x2 are all X and hence ECC error signal (soc_ifc_top1.i_mbox.sram_double_ecc_error) is going X.\r\n\r\nWe want to understand why the mailbox state machine is reading one extra entry from SRAM (DLEN + 4 bytes instead of DLEN bytes). Since the Mailbox SRAM is not initialized on reset, reading from addresses where there have been no previous writes will cause unexpected ECC errors.\r\n\r\nDo Caliptra ROM initializes Mailbox SRAM during bring up?\r\n\r\nMailbox Command from SOC\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/0e81da11-df93-41e0-a60c-872d2a749bdc)\r\n\r\nECC error while Mailbox state machine is reading from address 0x2\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/b3a0e590-1662-4780-8afc-e0275c8537b4)\r\n", "commit_message": "Typo fix in comment", "fix_patch": "diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\nindex 2a1bcd3b3..a117b2a0c 100644\n--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n@@ -40,6 +40,8 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n \n   `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )\n \n+  extern virtual task mbox_teardown();\n+\n   // Constrain command to undefined opcode\n   constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }\n \n@@ -105,3 +107,13 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n   endtask\n \n endclass\n+\n+//==========================================\n+// Task:        mbox_teardown\n+// Description: At end-of-sequence, inject some stalls to allow\n+//              uC to acquire lock and sanitize the mailbox\n+//==========================================\n+task soc_ifc_env_mbox_sram_double_bit_flip_sequence::mbox_teardown();\n+    do_rand_delay(1, DLY_MEDIUM);\n+    super.mbox_teardown();\n+endtask\n", "test_patch": "diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\nindex 9939a2515..417f10e6d 100644\n--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n@@ -322,6 +322,7 @@ void caliptra_rt() {\n         if (cptra_intr_rcv.soc_ifc_notif   ) {\n             uint8_t fsm_chk;\n             uint8_t fail = 0;\n+            uint32_t dlen_received;\n             VPRINTF(LOW, \"Intr received: soc_ifc_notif\\n\");\n             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {\n                 CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)\n@@ -379,6 +380,7 @@ void caliptra_rt() {\n                 }\n                 //read the mbox command\n                 op = soc_ifc_read_mbox_cmd();\n+                dlen_received = op.dlen;\n                 if (op.cmd & MBOX_CMD_FIELD_FW_MASK) {\n                     VPRINTF(MEDIUM, \"Received mailbox firmware command from SOC! Got 0x%x\\n\", op.cmd);\n                     if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {\n@@ -517,6 +519,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else if (fail) {\n                         VPRINTF(LOW, \"Cmd failed\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n@@ -564,6 +574,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else {\n                         soc_ifc_set_mbox_status_field(CMD_COMPLETE);\n                     }\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\nindex c7270fb2d..299846807 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n@@ -108,6 +108,15 @@ void soc_ifc_clr_flow_status_field(uint32_t field) {\n     lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS,reg);\n }\n \n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count) {\n+    for(uint32_t ii=0; ii<attempt_count; ii++) {\n+        if((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {\n+            return 0;\n+        }\n+    }\n+    return 1;\n+}\n+\n mbox_op_s soc_ifc_read_mbox_cmd() {\n     mbox_op_s op;\n \n@@ -226,6 +235,22 @@ void soc_ifc_fw_update(mbox_op_s op) {\n         }\n }\n \n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count) {\n+    if (byte_count > MBOX_DIR_SPAN) {\n+        VPRINTF(FATAL, \"SOC_IFC: Illegal byte_count 0x%x\\n\", byte_count);\n+        SEND_STDOUT_CTRL(0x1);\n+    }\n+    if (soc_ifc_mbox_acquire_lock(attempt_count) != 0) {\n+        VPRINTF(ERROR, \"ERROR: Failed to acquire lock for mbox sanitize operation\\n\");\n+        return 1;\n+    }\n+    for (uint32_t ii=0; ii < byte_count; ii+=4) {\n+        lsu_write_32(MBOX_DIR_BASE_ADDR+ii, 0x0);\n+    }\n+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);\n+    return 0;\n+}\n+\n void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {\n     uint32_t reg;\n     VPRINTF(MEDIUM,\"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\\n\", wait_cycles, wait_cycles > 5 ? \"will override\" : wait_cycles > 0 ? \"will use default 5\" : \"won't override\");\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\nindex 22e415442..84f6ad365 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n@@ -112,9 +112,11 @@ inline void soc_ifc_set_iccm_lock() {\n     lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);\n }\n // Mailbox command flows\n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count);\n mbox_op_s soc_ifc_read_mbox_cmd();\n void soc_ifc_mbox_fw_flow(mbox_op_s op);\n void soc_ifc_fw_update(mbox_op_s op);\n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count);\n \n // SHA Accelerator Functions\n void soc_ifc_sha_accel_acquire_lock();\n", "modified_files": ["src/integration/test_suites/caliptra_rt/caliptra_rt.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.h", "src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "lines_added": 57, "lines_removed": 0}
-{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "lang": "sv", "rtl_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "commit_id": "76d7c90fc8eab682519676e12d3e1599040df43b", "timestamp": "2023-09-08T16:04:47+00:00", "pr_title": "Fixing LEC reported in caliptra_prim_assert_sec_cm.svh", "pr_body": "This error was flagged in https://github.com/chipsalliance/caliptra-rtl/issues/186.  Removing the assertions altogether since they are not used in the current design.", "issue_title": "Formality LEC Failure Verilog 527:   (error) Syntax error found in the definition of argument macro ", "issue_body": "LEC Formality_Error_Code  reported in caliptra_prim_assert_sec_cm.svh\r\n\r\nError: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 49)  (Formality_Error_Code)\r\n1361:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 52)  (Formality_Error_Code)\r\n1362:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 55)  (Formality_Error_Code)\r\n1363:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 58)  (Formality_Error_Code)\r\n1364:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 61)  (Formality_Error_Code)\r\n\r\n[caliptra_fm_errors.tar.gz](https://github.com/chipsalliance/caliptra-rtl/files/12352228/caliptra_fm_errors.tar.gz)\r\n\r\n", "commit_message": "Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_cm.svh\n\nhttps://github.com/chipsalliance/caliptra-rtl/issues/186", "fix_patch": "diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\nindex 11ba287e0..096b7b61f 100644\n--- a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n@@ -45,21 +45,4 @@\n   `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \\\n     REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)\n \n-// macros for security countermeasures that will trigger other errors\n-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \\\n-    REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)\n-\n `endif // PRIM_ASSERT_SEC_CM_SVH\n", "test_patch": "", "modified_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "lines_added": 0, "lines_removed": 17}
-{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "lang": "sv", "rtl_files": ["src/integration/rtl/caliptra_top.sv"], "commit_id": "02f97acf731c1dae6275883b4ccd200cee01e998", "timestamp": "2023-05-29T15:13:01+00:00", "pr_title": "Connection of the SB (debug) bus in Caliptra", "pr_body": "This PR connects `SB` and `LSU` AHB buses together using a 2:1 mux so that access to peripherals is possible via the JTAG port.\r\n\r\n**! This PR is required for the CI in https://github.com/chipsalliance/caliptra-rtl/pull/72 to pass !**", "issue_title": "Enable using OpenOCD for interactive debugging of simulated Caliptra core", "issue_body": "This PR adds support for OpenOCD's `remote_bitbang` virtual adapter driver that allows to tap into the running verilated simulation of Caliptra RTL.\r\n\r\nTo achive this several components are added:\r\n- `tcp_server`\r\n  Acts as a communication bridge between OpenOCD and the simulation\r\n- `jtagdpi`\r\n  Parses OpenOCD commands, formats replies and interacts with the simulation via DPI calls\r\n- OpenOCD scripts (`tools/scripts/openocd`)\r\n  These define the interface and target for OpenOCD\r\n\r\nTo connect to a running simulation first build and run the special `infinite_loop` test:\r\n```\r\nmake -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=infinite_loop verilator\r\n```\r\nThen connect to it via OpenOCD (assuming that OpenOCD is installed):\r\n```\r\ncd tools/scripts/openocd\r\nopenocd -f board/caliptra-verilator.cfg\r\n```\r\nFinally start a debugging session with GDB by connecting to OpenOCD. Upon running GDB issue the following command:\r\n```\r\ntarget remote :3333\r\n```\r\nIf everything worked correctly you should be able to eg. dump the RISC-V core registers in GDB:\r\n```\r\ninfo registers\r\n```\r\n\r\nThe PR also includes a new workflow `Interactive debugging` which runs the flow described above in CI and performs various debugging actions. The tests in the new flow include:\r\n\r\n- Core register access via GDB + OpenOCD\r\n- Memory access (ICCM, DCCM and ROM)\r\n- Peripheral access\r\n- Peripheral access while the core is forcibly held in reset", "commit_message": "Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to peripherals\n\nSigned-off-by: Maciej Kurc <mkurc@antmicro.com>", "fix_patch": "diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv\nindex 1dcd23645..f59d9c221 100755\n--- a/src/integration/rtl/caliptra_top.sv\n+++ b/src/integration/rtl/caliptra_top.sv\n@@ -276,6 +276,17 @@ end\n     //========================================================================\r\n     // AHB Master ports\r\n     //========================================================================\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    sb_ahb();\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    lsu_ahb();\r\n+\r\n     CALIPTRA_AHB_LITE_BUS_INF #(\r\n         .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n         .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n@@ -403,34 +414,34 @@ el2_veer_wrapper rvtop (\n     //---------------------------------------------------------------\r\n     // Debug AHB Master\r\n     //---------------------------------------------------------------\r\n-    .sb_haddr               (),\r\n-    .sb_hburst              (),\r\n-    .sb_hmastlock           (),\r\n-    .sb_hprot               (),\r\n-    .sb_hsize               (),\r\n-    .sb_htrans              (),\r\n-    .sb_hwrite              (),\r\n-    .sb_hwdata              (),\r\n-\r\n-    .sb_hrdata              ('0),\r\n-    .sb_hready              ('0),\r\n-    .sb_hresp               ('0),\r\n+    .sb_haddr               ( sb_ahb.haddr   ),\r\n+    .sb_hburst              (                ),\r\n+    .sb_hmastlock           (                ),\r\n+    .sb_hprot               (                ),\r\n+    .sb_hsize               ( sb_ahb.hsize   ),\r\n+    .sb_htrans              ( sb_ahb.htrans  ),\r\n+    .sb_hwrite              ( sb_ahb.hwrite  ),\r\n+    .sb_hwdata              ( sb_ahb.hwdata  ),\r\n+\r\n+    .sb_hrdata              ( sb_ahb.hrdata  ),\r\n+    .sb_hready              ( sb_ahb.hready  ),\r\n+    .sb_hresp               ( sb_ahb.hresp   ),\r\n \r\n     //---------------------------------------------------------------\r\n     // LSU AHB Master\r\n     //---------------------------------------------------------------\r\n-    .lsu_haddr              ( initiator_inst.haddr       ),\r\n-    .lsu_hburst             (                       ),\r\n-    .lsu_hmastlock          (                       ),\r\n-    .lsu_hprot              (                       ),\r\n-    .lsu_hsize              ( initiator_inst.hsize       ),\r\n-    .lsu_htrans             ( initiator_inst.htrans      ),\r\n-    .lsu_hwrite             ( initiator_inst.hwrite      ),\r\n-    .lsu_hwdata             ( initiator_inst.hwdata      ),\r\n-\r\n-    .lsu_hrdata             ( initiator_inst.hrdata[63:0]),\r\n-    .lsu_hready             ( initiator_inst.hready      ),\r\n-    .lsu_hresp              ( initiator_inst.hresp       ),\r\n+    .lsu_haddr              ( lsu_ahb.haddr  ),\r\n+    .lsu_hburst             (                ),\r\n+    .lsu_hmastlock          (                ),\r\n+    .lsu_hprot              (                ),\r\n+    .lsu_hsize              ( lsu_ahb.hsize  ),\r\n+    .lsu_htrans             ( lsu_ahb.htrans ),\r\n+    .lsu_hwrite             ( lsu_ahb.hwrite ),\r\n+    .lsu_hwdata             ( lsu_ahb.hwdata ),\r\n+\r\n+    .lsu_hrdata             ( lsu_ahb.hrdata ),\r\n+    .lsu_hready             ( lsu_ahb.hready ),\r\n+    .lsu_hresp              ( lsu_ahb.hresp  ),\r\n \r\n     //---------------------------------------------------------------\r\n     // DMA Slave\r\n@@ -513,6 +524,51 @@ el2_veer_wrapper rvtop (\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hresp     = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hresp;\r\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hreadyout = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout;\r\n \r\n+    // SB and LSU AHB master mux\r\n+    ahb_lite_2to1_mux #(\r\n+        .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH (`CALIPTRA_AHB_HDATA_SIZE)\r\n+    ) u_sb_lsu_ahb_mux (\r\n+        .hclk                (clk_cg),\r\n+        .hreset_n            (cptra_noncore_rst_b),\r\n+\r\n+        // Initiator 0\r\n+        .hsel_i_0            (1'b1          ),\r\n+        .haddr_i_0           (lsu_ahb.haddr ),\r\n+        .hwdata_i_0          (lsu_ahb.hwdata),\r\n+        .hwrite_i_0          (lsu_ahb.hwrite),\r\n+        .htrans_i_0          (lsu_ahb.htrans),\r\n+        .hsize_i_0           (lsu_ahb.hsize ),\r\n+        .hready_i_0          (1'b1          ),\r\n+        .hresp_o_0           (lsu_ahb.hresp ),\r\n+        .hready_o_0          (lsu_ahb.hready),\r\n+        .hrdata_o_0          (lsu_ahb.hrdata),\r\n+\r\n+        // Initiator 1\r\n+        .hsel_i_1            (1'b1          ),\r\n+        .haddr_i_1           (sb_ahb.haddr  ),\r\n+        .hwdata_i_1          (sb_ahb.hwdata ),\r\n+        .hwrite_i_1          (sb_ahb.hwrite ),\r\n+        .htrans_i_1          (sb_ahb.htrans ),\r\n+        .hsize_i_1           (sb_ahb.hsize  ),\r\n+        .hready_i_1          (1'b1          ),\r\n+        .hresp_o_1           (sb_ahb.hresp  ),\r\n+        .hready_o_1          (sb_ahb.hready ),\r\n+        .hrdata_o_1          (sb_ahb.hrdata ),\r\n+\r\n+        // Responder\r\n+        .hsel_o              (initiator_inst.hsel  ),\r\n+        .haddr_o             (initiator_inst.haddr ),\r\n+        .hwdata_o            (initiator_inst.hwdata),\r\n+        .hwrite_o            (initiator_inst.hwrite),\r\n+        .htrans_o            (initiator_inst.htrans),\r\n+        .hsize_o             (initiator_inst.hsize ),\r\n+        .hready_o            (initiator_inst.hready),\r\n+        .hresp_i             (initiator_inst.hresp ),\r\n+        .hreadyout_i         (initiator_inst.hready),\r\n+        .hrdata_i            (initiator_inst.hrdata)\r\n+    );\r\n+\r\n     // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)\r\n     always_ff @(posedge clk or negedge cptra_rst_b) begin\r\n         if (~cptra_rst_b) begin\r\n", "test_patch": "", "modified_files": ["src/integration/rtl/caliptra_top.sv"], "lines_added": 80, "lines_removed": 24}
-{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "lang": "sv", "rtl_files": ["src/soc_ifc/rtl/soc_ifc_top.sv"], "commit_id": "721cf1171b765533602bbadb9cc94b5f1da480ab", "timestamp": "2023-05-04T16:45:36+00:00", "pr_title": "Moving tool installation to step prior to matrix generation", "pr_body": "Moving tool installation to step prior to matrix generation.  \r\n\r\nIf the tools haven't been cached in a new branch, each test will clobber the cache, causing the tests to install the tools every time.  This re-arranges the order so that we ensure tools are installed prior to creating the test matrix.\r\n\r\nThis also modified the watchdog timer from always_comb to generate as discussed in https://github.com/chipsalliance/caliptra-rtl/issues/71", "issue_title": "verilator smoke test (sha512/sha256/iccm_lock/sha_accel) failures", "issue_body": "I ran into the following issue while running some [smoke tests](https://github.com/chipsalliance/caliptra-rtl/actions/runs/4801296942/jobs/8544916590).  I did a few git bisect to see where things broke.\r\n\r\n```\r\n----------------------------------------\r\nRunning SHA512 Smoke Test             !!\r\n----------------------------------------\r\nHit max cycle count (20000000) .. stopping\r\n- /home/runner/work/caliptra-rtl/caliptra-rtl/src/integration/tb/caliptra_top_tb_services.sv:495: Verilog $finish\r\n```\r\n\r\ntestname | commit\r\n--|--\r\nsmoke_test_sha512, smoke_test_sha256, iccm_lock, smoke_test_sha_accel | 51bf68d3c2e3a1499f53d31b1b45f144726041aa \r\n\r\nWondering if these have been fixed internally?", "commit_message": "Changing $display to $error for error messages", "fix_patch": "diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv\nindex a302f0263..e6c5d156f 100644\n--- a/src/soc_ifc/rtl/soc_ifc_top.sv\n+++ b/src/soc_ifc/rtl/soc_ifc_top.sv\n@@ -691,11 +691,9 @@ assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en;\n assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart;\n assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart;\n \n-always_comb begin\n-    for (int i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n-        timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n-        timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n-    end\n+for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n+  assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n+  assign timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n end\n \n //Set WDT status reg\n", "test_patch": "diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml\nindex 0b41a2ebb..5f76eb0d1 100644\n--- a/.github/workflows/build-test-verilator.yml\n+++ b/.github/workflows/build-test-verilator.yml\n@@ -10,31 +10,9 @@ on:\n   workflow_dispatch:\n \n jobs:\n-  build_matrix:\n-    name: Build Smoke Test matrix\n-    runs-on: ubuntu-22.04\n-    outputs:\n-      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n-    steps:\n-      - uses: actions/checkout@v3\n-      - name: Install deps\n-        run: |\n-          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n-            python3-minimal python3-yaml\n-      - name: Build matrix\n-        id: output-matrix\n-        run: |\n-          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n-\n-  build_and_test:\n-    name: Verilator Smoke Test\n+  build_tools:\n+    name: Build Tools\n     runs-on: ubuntu-22.04\n-    needs: build_matrix\n-\n-    strategy:\n-      fail-fast: false\n-      matrix:\n-        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n \n     env:\n       CARGO_INCREMENTAL: 0\n@@ -135,14 +113,93 @@ jobs:\n           path: /opt/riscv\n           key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n \n+      - name: Setup riscv path\n+        run: |\n+          echo /opt/riscv/bin >> $GITHUB_PATH\n+\n+  build_matrix:\n+    name: Build Smoke Test matrix\n+    runs-on: ubuntu-22.04\n+    needs: build_tools\n+    outputs:\n+      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n+    steps:\n+      - uses: actions/checkout@v3\n+      - name: Install deps\n+        run: |\n+          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n+            python3-minimal python3-yaml\n+      - name: Build matrix\n+        id: output-matrix\n+        run: |\n+          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n+\n+  build_and_test:\n+    name: Verilator Smoke Test\n+    runs-on: ubuntu-22.04\n+    needs: build_matrix\n+\n+    strategy:\n+      fail-fast: false\n+      matrix:\n+        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n+\n+    env:\n+      # TODO: is there a way to grab these from build_tools?\n+      CARGO_INCREMENTAL: 0\n+      SCCACHE_VERSION: 0.3.3\n+      RISCV_VERSION: v12.1.0\n+      # TODO: To update to 5.006, clean up lint errors\n+      VERILATOR_VERSION: v5.002\n+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig\n+      SCCACHE_GHA_CACHE_TO: sccache-verilator-10000\n+      SCCACHE_GHA_CACHE_FROM: sccache-verilator-\n+      # Change this to a new random value if you suspect the cache is corrupted\n+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d\n+\n+    steps:\n+      - uses: actions/checkout@v3\n+        with:\n+          submodules: 'true'\n+\n+      - name: Restore Cargo index\n+        uses: actions/cache/restore@v3\n+        id: cargo_index_restore\n+        with:\n+          path: ~/.cargo/registry/index\n+          key: cargo-index-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}-${{ hashFiles('Cargo.lock') }}\n+\n+      - name: Restore sccache binary\n+        uses: actions/cache/restore@v3\n+        id: sccache_bin_restore\n+        with:\n+          path: ~/.cargo/bin/sccache\n+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore verilator dir\n+        uses: actions/cache/restore@v3\n+        id: verilator_restore\n+        with:\n+          path: /opt/verilator\n+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore Risc V Toolchain\n+        uses: actions/cache/restore@v3\n+        id: riscv_restore\n+        with:\n+          path: /opt/riscv\n+          key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n       - name: Setup verilator path\n+        run: |\n+          echo /opt/verilator/bin >> $GITHUB_PATH\n+\n+      - name: Setup riscv path\n         run: |\n           echo /opt/riscv/bin >> $GITHUB_PATH\n \n       - name: Run Caliptra Verilator Smoke Test\n         run: |\n-          # TODO: Add the run_verilator_l0_regression.py script.\n-          # Running a simple test to make sure that there aren't any elaboration issues\n           CALIPTRA_ROOT=$(pwd)\n           cd tools/scripts\n           make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name  }}\ndiff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv\nindex 6ec85caf9..964c67c01 100644\n--- a/src/integration/tb/caliptra_top_tb_services.sv\n+++ b/src/integration/tb/caliptra_top_tb_services.sv\n@@ -488,7 +488,7 @@ module caliptra_top_tb_services\n         cycleCnt <= cycleCnt+1;\n         // Test timeout monitor\n         if(cycleCnt == MAX_CYCLES && !UVM_TB) begin\n-            $display (\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n+            $error(\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n             dump_memory_contents(MEMTYPE_LMEM, 32'h8000_0110, 32'h8000_0180);\n             dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n             dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n@@ -528,12 +528,12 @@ module caliptra_top_tb_services\n             if (UVM_TB) $info(\"INFO: Detected FW write to manually end the test with FAIL; ignoring since the UVM environment will handle this.\");\n             else begin\n                 cycleCntKillReq <= cycleCnt;\n-                $display(\"* TESTCASE FAILED\");\n+                $error(\"* TESTCASE FAILED\");\n                 $display(\" -- Extending simulation for 100 clock cycles to capture ending waveform\");\n             end\n         end\n         if (|cycleCntKillReq && (cycleCnt == (cycleCntKillReq + 100))) begin\n-                $display(\"Dumping memory contents at simulation end due to FAILURE\");\n+                $error(\"Dumping memory contents at simulation end due to FAILURE\");\n                 dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF);\n                 dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n                 dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n", "modified_files": [".github/workflows/build-test-verilator.yml", "src/integration/tb/caliptra_top_tb_services.sv", "src/soc_ifc/rtl/soc_ifc_top.sv"], "lines_added": 89, "lines_removed": 34}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "lang": "sv", "rtl_files": ["src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "commit_id": "55f5f95fb2b352be2f9c6482142fcc63763e0d31", "timestamp": "2024-03-29T19:25:01+00:00", "pr_title": "[UVM] Implement mailbox sanitize feature in val fw to suppress regression failure", "pr_body": "Implement a firmware feature (for the validation code used in UVM tests) to sanitize the mailbox after detecting double-bit ECC error, to mirror the workaround required in 1.1 Firmware as per https://github.com/chipsalliance/caliptra-rtl/issues/399.\r\n\r\nThis is a temporary solution that should be removed for 2.0, as the mailbox should be modified to avoid spurious data prefetches.", "merge_commit_sha": "234a09993120d436e441827ad2f500154ec4f36a", "issue_title": "Caliptra uC is reading one extra entry from Mailbox SRAM causing unexpected ECC errors", "issue_body": "Hi, We are bringing up Mailbox testcases and observed the following scenario where an unexpected ECC error is getting fired. Below is our sequence.\r\n\r\n1. SOC acquires the MBOX lock by reading MBOX_LOCK register. It returns 0 indicating that the lock has been acquired by SOC.\r\n2. SOC writes MBOX command register.\r\n3. SOC writes MBOX_DLEN register to 8 indicating that it has 8 bytes of data to write.\r\n4. SOC writes MBOX_DATAIN register twice. This causes two writes to SRAM mailbox at addresses 0x0 and 0x1.\r\n5. SOC writes MBOX_EXECUTE to 1 in order for uC to process the mailbox command.\r\n6. When the mailbox state machine is in MBOX_EXECUTE_UC state, we are observing that Caliptra is reading SRAM mailbox at addresses 0x0, 0x1 and 0x2. The first two are expected as DLEN is 8. However the data at address 0x2 are all X and hence ECC error signal (soc_ifc_top1.i_mbox.sram_double_ecc_error) is going X.\r\n\r\nWe want to understand why the mailbox state machine is reading one extra entry from SRAM (DLEN + 4 bytes instead of DLEN bytes). Since the Mailbox SRAM is not initialized on reset, reading from addresses where there have been no previous writes will cause unexpected ECC errors.\r\n\r\nDo Caliptra ROM initializes Mailbox SRAM during bring up?\r\n\r\nMailbox Command from SOC\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/0e81da11-df93-41e0-a60c-872d2a749bdc)\r\n\r\nECC error while Mailbox state machine is reading from address 0x2\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/b3a0e590-1662-4780-8afc-e0275c8537b4)\r\n", "commit_message": "Typo fix in comment", "fix_patch": "diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\nindex 2a1bcd3b3..a117b2a0c 100644\n--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n@@ -40,6 +40,8 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n \n   `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )\n \n+  extern virtual task mbox_teardown();\n+\n   // Constrain command to undefined opcode\n   constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }\n \n@@ -105,3 +107,13 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n   endtask\n \n endclass\n+\n+//==========================================\n+// Task:        mbox_teardown\n+// Description: At end-of-sequence, inject some stalls to allow\n+//              uC to acquire lock and sanitize the mailbox\n+//==========================================\n+task soc_ifc_env_mbox_sram_double_bit_flip_sequence::mbox_teardown();\n+    do_rand_delay(1, DLY_MEDIUM);\n+    super.mbox_teardown();\n+endtask\n", "test_patch": "diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\nindex 9939a2515..417f10e6d 100644\n--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n@@ -322,6 +322,7 @@ void caliptra_rt() {\n         if (cptra_intr_rcv.soc_ifc_notif   ) {\n             uint8_t fsm_chk;\n             uint8_t fail = 0;\n+            uint32_t dlen_received;\n             VPRINTF(LOW, \"Intr received: soc_ifc_notif\\n\");\n             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {\n                 CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)\n@@ -379,6 +380,7 @@ void caliptra_rt() {\n                 }\n                 //read the mbox command\n                 op = soc_ifc_read_mbox_cmd();\n+                dlen_received = op.dlen;\n                 if (op.cmd & MBOX_CMD_FIELD_FW_MASK) {\n                     VPRINTF(MEDIUM, \"Received mailbox firmware command from SOC! Got 0x%x\\n\", op.cmd);\n                     if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {\n@@ -517,6 +519,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else if (fail) {\n                         VPRINTF(LOW, \"Cmd failed\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n@@ -564,6 +574,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else {\n                         soc_ifc_set_mbox_status_field(CMD_COMPLETE);\n                     }\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\nindex c7270fb2d..299846807 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n@@ -108,6 +108,15 @@ void soc_ifc_clr_flow_status_field(uint32_t field) {\n     lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS,reg);\n }\n \n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count) {\n+    for(uint32_t ii=0; ii<attempt_count; ii++) {\n+        if((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {\n+            return 0;\n+        }\n+    }\n+    return 1;\n+}\n+\n mbox_op_s soc_ifc_read_mbox_cmd() {\n     mbox_op_s op;\n \n@@ -226,6 +235,22 @@ void soc_ifc_fw_update(mbox_op_s op) {\n         }\n }\n \n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count) {\n+    if (byte_count > MBOX_DIR_SPAN) {\n+        VPRINTF(FATAL, \"SOC_IFC: Illegal byte_count 0x%x\\n\", byte_count);\n+        SEND_STDOUT_CTRL(0x1);\n+    }\n+    if (soc_ifc_mbox_acquire_lock(attempt_count) != 0) {\n+        VPRINTF(ERROR, \"ERROR: Failed to acquire lock for mbox sanitize operation\\n\");\n+        return 1;\n+    }\n+    for (uint32_t ii=0; ii < byte_count; ii+=4) {\n+        lsu_write_32(MBOX_DIR_BASE_ADDR+ii, 0x0);\n+    }\n+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);\n+    return 0;\n+}\n+\n void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {\n     uint32_t reg;\n     VPRINTF(MEDIUM,\"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\\n\", wait_cycles, wait_cycles > 5 ? \"will override\" : wait_cycles > 0 ? \"will use default 5\" : \"won't override\");\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\nindex 22e415442..84f6ad365 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n@@ -112,9 +112,11 @@ inline void soc_ifc_set_iccm_lock() {\n     lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);\n }\n // Mailbox command flows\n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count);\n mbox_op_s soc_ifc_read_mbox_cmd();\n void soc_ifc_mbox_fw_flow(mbox_op_s op);\n void soc_ifc_fw_update(mbox_op_s op);\n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count);\n \n // SHA Accelerator Functions\n void soc_ifc_sha_accel_acquire_lock();\n", "modified_files": ["src/integration/test_suites/caliptra_rt/caliptra_rt.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.h", "src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "lines_added": 57, "lines_removed": 0}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "lang": "sv", "rtl_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "commit_id": "76d7c90fc8eab682519676e12d3e1599040df43b", "timestamp": "2023-09-08T16:04:47+00:00", "pr_title": "Fixing LEC reported in caliptra_prim_assert_sec_cm.svh", "pr_body": "This error was flagged in https://github.com/chipsalliance/caliptra-rtl/issues/186.  Removing the assertions altogether since they are not used in the current design.", "merge_commit_sha": "7bfc833749685a58e79b8c141ee2daa69764e805", "issue_title": "Formality LEC Failure Verilog 527:   (error) Syntax error found in the definition of argument macro ", "issue_body": "LEC Formality_Error_Code  reported in caliptra_prim_assert_sec_cm.svh\r\n\r\nError: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 49)  (Formality_Error_Code)\r\n1361:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 52)  (Formality_Error_Code)\r\n1362:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 55)  (Formality_Error_Code)\r\n1363:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 58)  (Formality_Error_Code)\r\n1364:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 61)  (Formality_Error_Code)\r\n\r\n[caliptra_fm_errors.tar.gz](https://github.com/chipsalliance/caliptra-rtl/files/12352228/caliptra_fm_errors.tar.gz)\r\n\r\n", "commit_message": "Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_cm.svh\n\nhttps://github.com/chipsalliance/caliptra-rtl/issues/186", "fix_patch": "diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\nindex 11ba287e0..096b7b61f 100644\n--- a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n@@ -45,21 +45,4 @@\n   `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \\\n     REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)\n \n-// macros for security countermeasures that will trigger other errors\n-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \\\n-    REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)\n-\n `endif // PRIM_ASSERT_SEC_CM_SVH\n", "test_patch": "", "modified_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "lines_added": 0, "lines_removed": 17}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "lang": "sv", "rtl_files": ["src/integration/rtl/caliptra_top.sv"], "commit_id": "02f97acf731c1dae6275883b4ccd200cee01e998", "timestamp": "2023-05-29T15:13:01+00:00", "pr_title": "Connection of the SB (debug) bus in Caliptra", "pr_body": "This PR connects `SB` and `LSU` AHB buses together using a 2:1 mux so that access to peripherals is possible via the JTAG port.\r\n\r\n**! This PR is required for the CI in https://github.com/chipsalliance/caliptra-rtl/pull/72 to pass !**", "merge_commit_sha": "b86ce1854884d2064cf6e82f46f406f15c9e7237", "issue_title": "Enable using OpenOCD for interactive debugging of simulated Caliptra core", "issue_body": "This PR adds support for OpenOCD's `remote_bitbang` virtual adapter driver that allows to tap into the running verilated simulation of Caliptra RTL.\r\n\r\nTo achive this several components are added:\r\n- `tcp_server`\r\n  Acts as a communication bridge between OpenOCD and the simulation\r\n- `jtagdpi`\r\n  Parses OpenOCD commands, formats replies and interacts with the simulation via DPI calls\r\n- OpenOCD scripts (`tools/scripts/openocd`)\r\n  These define the interface and target for OpenOCD\r\n\r\nTo connect to a running simulation first build and run the special `infinite_loop` test:\r\n```\r\nmake -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=infinite_loop verilator\r\n```\r\nThen connect to it via OpenOCD (assuming that OpenOCD is installed):\r\n```\r\ncd tools/scripts/openocd\r\nopenocd -f board/caliptra-verilator.cfg\r\n```\r\nFinally start a debugging session with GDB by connecting to OpenOCD. Upon running GDB issue the following command:\r\n```\r\ntarget remote :3333\r\n```\r\nIf everything worked correctly you should be able to eg. dump the RISC-V core registers in GDB:\r\n```\r\ninfo registers\r\n```\r\n\r\nThe PR also includes a new workflow `Interactive debugging` which runs the flow described above in CI and performs various debugging actions. The tests in the new flow include:\r\n\r\n- Core register access via GDB + OpenOCD\r\n- Memory access (ICCM, DCCM and ROM)\r\n- Peripheral access\r\n- Peripheral access while the core is forcibly held in reset", "commit_message": "Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to peripherals\n\nSigned-off-by: Maciej Kurc <mkurc@antmicro.com>", "fix_patch": "diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv\nindex 1dcd23645..f59d9c221 100755\n--- a/src/integration/rtl/caliptra_top.sv\n+++ b/src/integration/rtl/caliptra_top.sv\n@@ -276,6 +276,17 @@ end\n     //========================================================================\r\n     // AHB Master ports\r\n     //========================================================================\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    sb_ahb();\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    lsu_ahb();\r\n+\r\n     CALIPTRA_AHB_LITE_BUS_INF #(\r\n         .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n         .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n@@ -403,34 +414,34 @@ el2_veer_wrapper rvtop (\n     //---------------------------------------------------------------\r\n     // Debug AHB Master\r\n     //---------------------------------------------------------------\r\n-    .sb_haddr               (),\r\n-    .sb_hburst              (),\r\n-    .sb_hmastlock           (),\r\n-    .sb_hprot               (),\r\n-    .sb_hsize               (),\r\n-    .sb_htrans              (),\r\n-    .sb_hwrite              (),\r\n-    .sb_hwdata              (),\r\n-\r\n-    .sb_hrdata              ('0),\r\n-    .sb_hready              ('0),\r\n-    .sb_hresp               ('0),\r\n+    .sb_haddr               ( sb_ahb.haddr   ),\r\n+    .sb_hburst              (                ),\r\n+    .sb_hmastlock           (                ),\r\n+    .sb_hprot               (                ),\r\n+    .sb_hsize               ( sb_ahb.hsize   ),\r\n+    .sb_htrans              ( sb_ahb.htrans  ),\r\n+    .sb_hwrite              ( sb_ahb.hwrite  ),\r\n+    .sb_hwdata              ( sb_ahb.hwdata  ),\r\n+\r\n+    .sb_hrdata              ( sb_ahb.hrdata  ),\r\n+    .sb_hready              ( sb_ahb.hready  ),\r\n+    .sb_hresp               ( sb_ahb.hresp   ),\r\n \r\n     //---------------------------------------------------------------\r\n     // LSU AHB Master\r\n     //---------------------------------------------------------------\r\n-    .lsu_haddr              ( initiator_inst.haddr       ),\r\n-    .lsu_hburst             (                       ),\r\n-    .lsu_hmastlock          (                       ),\r\n-    .lsu_hprot              (                       ),\r\n-    .lsu_hsize              ( initiator_inst.hsize       ),\r\n-    .lsu_htrans             ( initiator_inst.htrans      ),\r\n-    .lsu_hwrite             ( initiator_inst.hwrite      ),\r\n-    .lsu_hwdata             ( initiator_inst.hwdata      ),\r\n-\r\n-    .lsu_hrdata             ( initiator_inst.hrdata[63:0]),\r\n-    .lsu_hready             ( initiator_inst.hready      ),\r\n-    .lsu_hresp              ( initiator_inst.hresp       ),\r\n+    .lsu_haddr              ( lsu_ahb.haddr  ),\r\n+    .lsu_hburst             (                ),\r\n+    .lsu_hmastlock          (                ),\r\n+    .lsu_hprot              (                ),\r\n+    .lsu_hsize              ( lsu_ahb.hsize  ),\r\n+    .lsu_htrans             ( lsu_ahb.htrans ),\r\n+    .lsu_hwrite             ( lsu_ahb.hwrite ),\r\n+    .lsu_hwdata             ( lsu_ahb.hwdata ),\r\n+\r\n+    .lsu_hrdata             ( lsu_ahb.hrdata ),\r\n+    .lsu_hready             ( lsu_ahb.hready ),\r\n+    .lsu_hresp              ( lsu_ahb.hresp  ),\r\n \r\n     //---------------------------------------------------------------\r\n     // DMA Slave\r\n@@ -513,6 +524,51 @@ el2_veer_wrapper rvtop (\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hresp     = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hresp;\r\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hreadyout = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout;\r\n \r\n+    // SB and LSU AHB master mux\r\n+    ahb_lite_2to1_mux #(\r\n+        .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH (`CALIPTRA_AHB_HDATA_SIZE)\r\n+    ) u_sb_lsu_ahb_mux (\r\n+        .hclk                (clk_cg),\r\n+        .hreset_n            (cptra_noncore_rst_b),\r\n+\r\n+        // Initiator 0\r\n+        .hsel_i_0            (1'b1          ),\r\n+        .haddr_i_0           (lsu_ahb.haddr ),\r\n+        .hwdata_i_0          (lsu_ahb.hwdata),\r\n+        .hwrite_i_0          (lsu_ahb.hwrite),\r\n+        .htrans_i_0          (lsu_ahb.htrans),\r\n+        .hsize_i_0           (lsu_ahb.hsize ),\r\n+        .hready_i_0          (1'b1          ),\r\n+        .hresp_o_0           (lsu_ahb.hresp ),\r\n+        .hready_o_0          (lsu_ahb.hready),\r\n+        .hrdata_o_0          (lsu_ahb.hrdata),\r\n+\r\n+        // Initiator 1\r\n+        .hsel_i_1            (1'b1          ),\r\n+        .haddr_i_1           (sb_ahb.haddr  ),\r\n+        .hwdata_i_1          (sb_ahb.hwdata ),\r\n+        .hwrite_i_1          (sb_ahb.hwrite ),\r\n+        .htrans_i_1          (sb_ahb.htrans ),\r\n+        .hsize_i_1           (sb_ahb.hsize  ),\r\n+        .hready_i_1          (1'b1          ),\r\n+        .hresp_o_1           (sb_ahb.hresp  ),\r\n+        .hready_o_1          (sb_ahb.hready ),\r\n+        .hrdata_o_1          (sb_ahb.hrdata ),\r\n+\r\n+        // Responder\r\n+        .hsel_o              (initiator_inst.hsel  ),\r\n+        .haddr_o             (initiator_inst.haddr ),\r\n+        .hwdata_o            (initiator_inst.hwdata),\r\n+        .hwrite_o            (initiator_inst.hwrite),\r\n+        .htrans_o            (initiator_inst.htrans),\r\n+        .hsize_o             (initiator_inst.hsize ),\r\n+        .hready_o            (initiator_inst.hready),\r\n+        .hresp_i             (initiator_inst.hresp ),\r\n+        .hreadyout_i         (initiator_inst.hready),\r\n+        .hrdata_i            (initiator_inst.hrdata)\r\n+    );\r\n+\r\n     // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)\r\n     always_ff @(posedge clk or negedge cptra_rst_b) begin\r\n         if (~cptra_rst_b) begin\r\n", "test_patch": "", "modified_files": ["src/integration/rtl/caliptra_top.sv"], "lines_added": 80, "lines_removed": 24}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "lang": "sv", "rtl_files": ["src/soc_ifc/rtl/soc_ifc_top.sv"], "commit_id": "721cf1171b765533602bbadb9cc94b5f1da480ab", "timestamp": "2023-05-04T16:45:36+00:00", "pr_title": "Moving tool installation to step prior to matrix generation", "pr_body": "Moving tool installation to step prior to matrix generation.  \r\n\r\nIf the tools haven't been cached in a new branch, each test will clobber the cache, causing the tests to install the tools every time.  This re-arranges the order so that we ensure tools are installed prior to creating the test matrix.\r\n\r\nThis also modified the watchdog timer from always_comb to generate as discussed in https://github.com/chipsalliance/caliptra-rtl/issues/71", "merge_commit_sha": "bd79b88789f945225f19884ceb8d5913092fea59", "issue_title": "verilator smoke test (sha512/sha256/iccm_lock/sha_accel) failures", "issue_body": "I ran into the following issue while running some [smoke tests](https://github.com/chipsalliance/caliptra-rtl/actions/runs/4801296942/jobs/8544916590).  I did a few git bisect to see where things broke.\r\n\r\n```\r\n----------------------------------------\r\nRunning SHA512 Smoke Test             !!\r\n----------------------------------------\r\nHit max cycle count (20000000) .. stopping\r\n- /home/runner/work/caliptra-rtl/caliptra-rtl/src/integration/tb/caliptra_top_tb_services.sv:495: Verilog $finish\r\n```\r\n\r\ntestname | commit\r\n--|--\r\nsmoke_test_sha512, smoke_test_sha256, iccm_lock, smoke_test_sha_accel | 51bf68d3c2e3a1499f53d31b1b45f144726041aa \r\n\r\nWondering if these have been fixed internally?", "commit_message": "Changing $display to $error for error messages", "fix_patch": "diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv\nindex a302f0263..e6c5d156f 100644\n--- a/src/soc_ifc/rtl/soc_ifc_top.sv\n+++ b/src/soc_ifc/rtl/soc_ifc_top.sv\n@@ -691,11 +691,9 @@ assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en;\n assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart;\n assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart;\n \n-always_comb begin\n-    for (int i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n-        timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n-        timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n-    end\n+for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n+  assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n+  assign timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n end\n \n //Set WDT status reg\n", "test_patch": "diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml\nindex 0b41a2ebb..5f76eb0d1 100644\n--- a/.github/workflows/build-test-verilator.yml\n+++ b/.github/workflows/build-test-verilator.yml\n@@ -10,31 +10,9 @@ on:\n   workflow_dispatch:\n \n jobs:\n-  build_matrix:\n-    name: Build Smoke Test matrix\n-    runs-on: ubuntu-22.04\n-    outputs:\n-      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n-    steps:\n-      - uses: actions/checkout@v3\n-      - name: Install deps\n-        run: |\n-          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n-            python3-minimal python3-yaml\n-      - name: Build matrix\n-        id: output-matrix\n-        run: |\n-          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n-\n-  build_and_test:\n-    name: Verilator Smoke Test\n+  build_tools:\n+    name: Build Tools\n     runs-on: ubuntu-22.04\n-    needs: build_matrix\n-\n-    strategy:\n-      fail-fast: false\n-      matrix:\n-        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n \n     env:\n       CARGO_INCREMENTAL: 0\n@@ -135,14 +113,93 @@ jobs:\n           path: /opt/riscv\n           key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n \n+      - name: Setup riscv path\n+        run: |\n+          echo /opt/riscv/bin >> $GITHUB_PATH\n+\n+  build_matrix:\n+    name: Build Smoke Test matrix\n+    runs-on: ubuntu-22.04\n+    needs: build_tools\n+    outputs:\n+      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n+    steps:\n+      - uses: actions/checkout@v3\n+      - name: Install deps\n+        run: |\n+          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n+            python3-minimal python3-yaml\n+      - name: Build matrix\n+        id: output-matrix\n+        run: |\n+          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n+\n+  build_and_test:\n+    name: Verilator Smoke Test\n+    runs-on: ubuntu-22.04\n+    needs: build_matrix\n+\n+    strategy:\n+      fail-fast: false\n+      matrix:\n+        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n+\n+    env:\n+      # TODO: is there a way to grab these from build_tools?\n+      CARGO_INCREMENTAL: 0\n+      SCCACHE_VERSION: 0.3.3\n+      RISCV_VERSION: v12.1.0\n+      # TODO: To update to 5.006, clean up lint errors\n+      VERILATOR_VERSION: v5.002\n+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig\n+      SCCACHE_GHA_CACHE_TO: sccache-verilator-10000\n+      SCCACHE_GHA_CACHE_FROM: sccache-verilator-\n+      # Change this to a new random value if you suspect the cache is corrupted\n+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d\n+\n+    steps:\n+      - uses: actions/checkout@v3\n+        with:\n+          submodules: 'true'\n+\n+      - name: Restore Cargo index\n+        uses: actions/cache/restore@v3\n+        id: cargo_index_restore\n+        with:\n+          path: ~/.cargo/registry/index\n+          key: cargo-index-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}-${{ hashFiles('Cargo.lock') }}\n+\n+      - name: Restore sccache binary\n+        uses: actions/cache/restore@v3\n+        id: sccache_bin_restore\n+        with:\n+          path: ~/.cargo/bin/sccache\n+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore verilator dir\n+        uses: actions/cache/restore@v3\n+        id: verilator_restore\n+        with:\n+          path: /opt/verilator\n+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore Risc V Toolchain\n+        uses: actions/cache/restore@v3\n+        id: riscv_restore\n+        with:\n+          path: /opt/riscv\n+          key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n       - name: Setup verilator path\n+        run: |\n+          echo /opt/verilator/bin >> $GITHUB_PATH\n+\n+      - name: Setup riscv path\n         run: |\n           echo /opt/riscv/bin >> $GITHUB_PATH\n \n       - name: Run Caliptra Verilator Smoke Test\n         run: |\n-          # TODO: Add the run_verilator_l0_regression.py script.\n-          # Running a simple test to make sure that there aren't any elaboration issues\n           CALIPTRA_ROOT=$(pwd)\n           cd tools/scripts\n           make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name  }}\ndiff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv\nindex 6ec85caf9..964c67c01 100644\n--- a/src/integration/tb/caliptra_top_tb_services.sv\n+++ b/src/integration/tb/caliptra_top_tb_services.sv\n@@ -488,7 +488,7 @@ module caliptra_top_tb_services\n         cycleCnt <= cycleCnt+1;\n         // Test timeout monitor\n         if(cycleCnt == MAX_CYCLES && !UVM_TB) begin\n-            $display (\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n+            $error(\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n             dump_memory_contents(MEMTYPE_LMEM, 32'h8000_0110, 32'h8000_0180);\n             dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n             dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n@@ -528,12 +528,12 @@ module caliptra_top_tb_services\n             if (UVM_TB) $info(\"INFO: Detected FW write to manually end the test with FAIL; ignoring since the UVM environment will handle this.\");\n             else begin\n                 cycleCntKillReq <= cycleCnt;\n-                $display(\"* TESTCASE FAILED\");\n+                $error(\"* TESTCASE FAILED\");\n                 $display(\" -- Extending simulation for 100 clock cycles to capture ending waveform\");\n             end\n         end\n         if (|cycleCntKillReq && (cycleCnt == (cycleCntKillReq + 100))) begin\n-                $display(\"Dumping memory contents at simulation end due to FAILURE\");\n+                $error(\"Dumping memory contents at simulation end due to FAILURE\");\n                 dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF);\n                 dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n                 dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n", "modified_files": [".github/workflows/build-test-verilator.yml", "src/integration/tb/caliptra_top_tb_services.sv", "src/soc_ifc/rtl/soc_ifc_top.sv"], "lines_added": 89, "lines_removed": 34}

s2/chipsalliance__caliptra-rtl/chipsalliance__caliptra-rtl_s2_02_selected_docs.jsonl

@@ -0,0 +1,4 @@
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "selected_doc_paths": [], "reason": "No official documents are available to match against the RTL module."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "selected_doc_paths": [], "reason": "No official documents provided."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "selected_doc_paths": [], "reason": "No official documents are available for this RTL module."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "selected_doc_paths": ["docs/CaliptraHardwareSpecification.md", "docs/CaliptraIntegrationSpecification.md"], "reason": "Both documents contain relevant information about the mailbox SRAM and error handling necessary for writing a behavioral spec for this sequence."}

s2/chipsalliance__caliptra-rtl/chipsalliance__caliptra-rtl_s2_03_generated_specs.jsonl

@@ -0,0 +1,4 @@
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "spec": "# Security Countermeasure Assertion Macros Specification (Behavioral)\n\n## 1. Purpose\n\nThis specification defines the behavior that must be verified by a set of assertion macros used to enforce security countermeasures in the Caliptra digital system. The macros are instantiated in the verification environment to check that specific security-relevant primitives correctly propagate errors to alert or error outputs within bounded time and under all allowed conditions.\n\nThese assertions ensure that when a security-critical primitive detects an internal error (e.g., illegal state, one‑hot violation, counter overflow, LFSR mismatch), the system promptly raises an alert or terminates an operation gracefully. The checks prevent silent corruption or undetected fault conditions.\n\n## 2. General Behavior\n\n### 2.1 Error-to-Alert Propagation\n\nWhenever any participating primitive asserts its **error output** (a single-bit signal indicating that a fault has been detected), the system must raise a corresponding **alert** (a system‑level signal) within a bounded number of clock cycles. This propagation must occur regardless of the primitive’s internal implementation details, provided the error is not masked by an explicit **gate condition**.\n\nThe **gate condition** is a static or dynamic signal that, when asserted, disables the error‑propagation check. If the gate condition is active, no requirement exists for the alert to be raised. If the gate condition is de‑asserted, the alert must be generated within the specified maximum number of cycles.\n\n### 2.2 Error-to-Error Output Propagation\n\nFor primitives that produce a dedicated **error output signal** (other than an alert), the same timing rule applies: after the primitive’s internal error becomes visible, the error output must be asserted within a bounded number of cycles, unless the gate condition is active.\n\n### 2.3 Timing Bounds\n\nThe maximum number of clock cycles allowed between the rising edge of the primitive’s error output and the assertion of the alert (or other error output) is a configurable parameter. If no explicit value is provided, the default is **30 clock cycles**. The system must meet this worst‑case latency under all operating conditions, including voltage, temperature, and process variations.\n\n### 2.4 Reset Stability Period\n\nImmediately after the system’s reset signal is de‑asserted, all primitive error outputs must remain **stable at zero** for a minimum of **10 consecutive clock cycles**. This period ensures that transient effects of reset are settled before the error‑propagation checks are evaluated. No alert or error output may be raised during this stabilization period, even if an error condition appears to exist earlier.\n\n## 3. Primitive-Specific Requirements\n\nEach primitive type has an error output that is connected to the assertion logic. The macro names identify which error output signal of the primitive is monitored.\n\n### 3.1 Counter Primitives\n\nFor a **counter** primitive (e.g., one used as a digital timer or event counter), the error output (named `err_o`) must propagate to an alert within the configured maximum cycles. This checks that counter malfunctions (e.g., overflow, underflow, illegal count) are reported promptly.\n\n### 3.2 Double LFSR Primitives\n\nFor a **double LFSR** (linear feedback shift register) used for redundancy or mutual checking, the error output (`err_o`) must trigger an alert within the maximum cycles. This ensures that mismatches between redundant shift registers are visible at the system level.\n\n### 3.3 Finite State Machine (FSM) Primitives\n\nFor an **FSM** primitive, the error output is **`unused_err_o`** (a dedicated error signal for invalid state transitions or illegal state codes). This error must be forwarded to an alert within the configured cycles. The naming distinguishes it from other error sources.\n\n### 3.4 One‑Hot Checker Primitives\n\nFor **one‑hot checkers** that verify a bus is either exactly one-hot or all‑zero, the error output (`err_o`) must become an alert within the maximum cycles. This covers primitives that check one‑hot encoding on write‑enable signals or other control busses.\n\n### 3.5 Register Write-Enable One‑Hot Checker (Sub‑Primitive)\n\nWhen a one‑hot checker is used inside a register write‑enable protection block (e.g., to prevent multiple write enables from being active simultaneously), the error propagates through a hierarchy. The macro that validates this behavior monitors the error output of the internal one‑hot checker instance. The same timing and gating rules apply.\n\n## 4. Gating Condition\n\nAll error‑to‑alert/error propagation checks include a **gate condition** input. When this input is asserted (true), the check is **disabled**; the alert or error output may remain low even if the primitive’s error output is asserted. When the gate condition is de‑asserted (false), the alert or error output must rise within the maximum number of cycles after the primitive’s error rises.\n\nThe gate condition allows the design to suppress error propagation during controlled sequences (e.g., while a circuit is being reconfigured or during startup). Outside such windows, error propagation is mandatory.\n\n## 5. Assertion Enable and Unused Connection\n\nIn verification builds where assertions are compiled (e.g., for simulation or formal analysis), a dedicated signal is wired to logic‑1 to indicate that the assertion wrapper is properly connected and active. This signal has no functional impact on the design; it exists solely to confirm structural integrity.\n\n## 6. Summary of Required Behavior\n\n| Condition | Required Behavior |\n|-----------|-------------------|\n| Primitive error rises, gate is de‑asserted | Alert (or designated error output) must assert within **MAX_CYCLES** (default **30**) clock cycles. |\n| Primitive error rises, gate is asserted | No timing requirement for alert/error assertion. |\n| Reset de‑assertion | All primitive error outputs must remain zero for at least **10** consecutive cycles. |\n| After the stabilization period | Error propagation checks become active again. |\n\nThe system must guarantee these behaviors for every instance of the primitives that are encapsulated by these macros, under all functional and environmental conditions."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "spec": "# Behavioral Design Specification: Mailbox SRAM Double-Bit Error Injection Sequence\n\n## 1. Overview\n\nThis module defines a test scenario that validates the hardware response to a double‑bit error (uncorrectable ECC error) in the mailbox SRAM during an active mailbox transaction. The scenario is designed to exercise the error detection, interrupt generation, and error recovery mechanisms of the Caliptra subsystem.\n\nThe test sequence proceeds as follows:\n\n1. Initiate a normal mailbox command from the SoC side with an intentionally invalid (undefined) opcode.\n2. At a random point during the mailbox flow (after lock acquisition, command write, data push, or execute), inject a double‑bit error into the mailbox SRAM.\n3. Observe the system’s response: the error should be reported as a non‑fatal hardware error, the `cptra_error_non_fatal` output pin must be asserted, and an internal error interrupt shall be generated.\n4. After the error is detected, the sequence clears the interrupt and terminates the mailbox flow.\n5. The SoC may then proceed with any of several allowed recovery actions (see Section 5).\n\n## 2. Preconditions and Initial State\n\n- The Caliptra subsystem is out of reset and operational.\n- The mailbox is in the idle state (LOCK = 0, no active flow).\n- No mailbox error conditions are pending.\n- The internal error registers are clear.\n- The `cptra_error_non_fatal` output is de‑asserted.\n\n## 3. Test Flow – Behavioral Steps\n\n### 3.1. Command Setup and Lock Acquisition\n\n- The SoC‑side agent requests the mailbox lock.\n- After the lock is obtained, a command is written to the mailbox command register.  \n  **Constraint:** The command opcode must be undefined (i.e., not one of the defined valid opcodes). This ensures that the mailbox microcontroller (firmware) will eventually detect an error condition (or at least that the command will be processed and cause an error).\n\n### 3.2. Data Transfer Initiation\n\n- The agent writes the data length (DLEN) and then pushes data into the mailbox data‑in register.\n- The agent may write the execute register to signal that the mailbox operation is ready for processing.\n\n### 3.3. SRAM Error Injection\n\n- At a random moment after the mailbox flow has started (but before the flow normally completes), a double‑bit flip is injected into the mailbox SRAM.\n- The injection may occur:\n  - After lock acquisition, before command write.\n  - After command write, before data push.\n  - During data push.\n  - After execute, before firmware reads the command.\n- The randomness of the injection point is intended to exercise different states of the mailbox finite‑state machine.\n\n### 3.4. Expected Hardware Response\n\nWhen the injected double‑bit error is read or otherwise encountered by the mailbox hardware (e.g., when the microcontroller reads the command, data, or status), the following must occur:\n\n- The mailbox ECC logic shall detect an uncorrectable error.\n- The mailbox shall:\n  - Set the status register to indicate an uncorrectable ECC error.\n  - Assert an internal error interrupt to the Caliptra microcontroller.\n  - Assert the `cptra_error_non_fatal` output pin.\n  - Record the error in the non‑fatal hardware error register.\n- The mailbox flow shall be terminated (entry into an error state).\n- No further mailbox operations shall be accepted until the error is serviced.\n\n### 3.5. Error Servicing and Cleanup\n\n- After a brief random delay to allow the microcontroller to observe the interrupt (or for the SoC to observe the asserted error pin), the test sequence performs the following:\n  - Clears the internal error interrupt (by writing to the appropriate interrupt‑clear register).\n  - Resets the mailbox finite‑state machine (by releasing the lock or performing a force‑unlock, as permitted by hardware).\n- The mailbox is then available for new operations.\n\n### 3.6. Teardown\n\n- The sequence inserts an additional medium‑length delay to allow the Caliptra microcontroller to acquire the lock and sanitize the mailbox content (e.g., clear any stale data or error state).\n- The sequence then performs a standard mailbox teardown (release lock, reset state).\n\n## 4. Expected Outcomes\n\n- The mailbox flow **must** be interrupted by the injected double‑bit error.\n- The error **must** be reported as a non‑fatal hardware error:\n  - `cptra_error_non_fatal` is asserted.\n  - The internal non‑fatal error register reflects the uncorrectable ECC error.\n  - A dedicated mailbox error interrupt is generated.\n- After clearing the interrupt, the mailbox **must** return to an idle state.\n- No persistent side‑effects (e.g., corrupted lock state, hung FSM) shall remain after the sequence completes.\n- The mailbox error handling **must** be consistent with the behavior described in the Caliptra Hardware Specification for double‑bit (uncorrectable) ECC errors.\n\n## 5. SoC Recovery Options\n\nThe specification acknowledges that different SoC integration may handle the `cptra_error_non_fatal` signal differently. The test sequence is designed to be compatible with any of the following SoC recovery strategies:\n\n1. **Defer recovery to firmware:** The SoC waits for the Caliptra microcontroller to clear the internal interrupt and/or reset the mailbox FSM. Once the error is handled internally, the `cptra_error_non_fatal` pin is de‑asserted. A subsequent mailbox command may proceed.\n\n2. **Immediate pin clearance:** The SoC clears the `cptra_error_non_fatal` interrupt immediately, then issues a new mailbox command after ensuring the lock is available. The new command may succeed only after the internal error handling has completed.\n\n3. **Full Caliptra reset:** The SoC resets Caliptra (via `cptra_rst_b` assertion) to recover from the error.\n\nThe test sequence does not mandate which recovery path is taken; it only verifies that the error is correctly detected and signaled, and that the mailbox can eventually return to a working state after error servicing.\n\n## 6. Constraints and Special Conditions\n\n- **Undefined opcode:** The command written to the mailbox **must** use an opcode that is not in the set of defined mailbox commands. This prevents the test from inadvertently triggering a valid, long‑running firmware operation that might mask the error response.\n- **Random injection timing:** The exact moment of SRAM error injection is randomized to ensure that the error detection and handling logic is exercised across different mailbox FSM states.\n- **No other errors:** The test assumes a clean environment with no pre‑existing errors in the mailbox or SRAM.\n\n## 7. References\n\n- Caliptra Hardware Specification, Section *Mailbox Errors* – describes the behavior of uncorrectable ECC errors.\n- Caliptra Integration Specification, *Mailbox Protocol Error Handling* – defines the error signals and recovery flows.\n- Caliptra Hardware Specification, Section *SRAM Implementation* – describes ECC protection in mailbox SRAM."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "spec": "# Behavioral Design Specification: `caliptra_top` (Caliptra Root-of-Trust Core)\n\n## 1. Overview\n\n`caliptra_top` is the top-level integration module of the Caliptra security processor. It contains a RISC-V processor core (VeeR EL2), a set of cryptographic accelerators, key and measurement storage, mailbox communication, and external interfaces for system-on-chip (SoC) integration. The module implements a secure boot flow, cryptographic services (hashing, HMAC, ECC, key derivation), and a trusted execution environment.\n\nThe module is designed to operate as an isolated security domain within a larger SoC, providing attestation, measurement, and cryptographic operations under strict lifecycle and debug controls.\n\n## 2. External Interfaces\n\n### 2.1 System Clock and Resets\n- **Main clock**: The module operates on a single input clock.\n- **Power-good reset** (`cptra_pwrgood`): Indicates that the SoC power is stable. Used for internal power-on reset generation.\n- **System reset** (`cptra_rst_b`): Main active-low reset. On deassertion, the module latches the security state and scan mode inputs, and begins its boot sequence.\n- The module internally generates two reset domains:\n  - *Non-core reset*: Resets crypto accelerators, key vaults, and peripherals.\n  - *Core reset*: Resets the RISC-V processor core.\n\n### 2.2 JTAG Interface\n- Supports standard JTAG signals (TCK, TMS, TDI, TDO, TRST_N).\n- Provides debug access to the processor core and to a set of DMI (Debug Module Interface) registers for uncore debug.\n- JTAG is only available when the device is in a debug‑unlocked security state or in scan mode; otherwise, its outputs are inhibited internally.\n\n### 2.3 Memory‑Mapped Control (APB Slave)\n- The SoC communicates with the Caliptra mailbox and status registers via an APB slave interface.\n- Parameters: configurable address width (e.g., 12‑bit) and data width (32‑bit).\n- Supports standard APB protocol (PREADY, PSLVERR).\n- Write and read transactions to this interface control mailbox data, boot‑status indicators, and security‑configuration registers.\n\n### 2.4 AHB‑Lite Bus\n- The internal processor and crypto engines communicate over a shared AHB‑Lite bus.\n- The bus topology includes:\n  - One *initiator* port (connected to the processor’s load/store unit (LSU) and debug SB‑master, multiplexed).\n  - Multiple *responder* ports for internal slaves.\n- Responders include: SHA‑512, SHA‑256, HMAC, ECC (elliptic‑curve crypto), Key Vault, PCR Vault, Data Vault, Mailbox (via SoC interface), AES‑DOE, QSPI, UART, I3C (reserved), instruction memory (IMEM), CSRNG, and Entropy Source.\n- A responder disable mechanism allows the processor to lock certain regions (e.g., ICCM) at runtime – writes to a locked responder are blocked.\n\n### 2.5 QSPI / SPI Host (Optional)\n- When `CALIPTRA_INTERNAL_QSPI` is defined, the module contains an SPI host controller.\n- Provides an external Quad‑SPI interface for connecting flash memory.\n- Outputs: clock, chip select (CS_N), and bidirectional data lines.\n\n### 2.6 UART (Optional)\n- When `CALIPTRA_INTERNAL_UART` is defined, a UART controller is instantiated.\n- Provides a single serial port (RX/TX) for debug or firmware logging.\n\n### 2.7 Mailbox SRAM Interface\n- The module drives a dedicated external SRAM for mailbox data storage.\n- Signals: chip select, write enable, address, write data (including ECC bits), and read data.\n\n### 2.8 Instruction Memory (IMEM) Interface\n- An external SRAM holds the boot firmware and runtime code.\n- The module generates the read address and chip select; the SoC provides the read data.\n\n### 2.9 Memory Export Interface (EL2)\n- Provides an interface to export the processor’s memory content for post‑silicon debug or trace (standard VeeR EL2 export).\n\n### 2.10 Generic I/O Wires\n- 64‑bit input and 64‑bit output wires that are mapped to SoC‑interface registers.\n- Used for platform‑specific control and status signals.\n\n### 2.11 Security State Inputs\n- `security_state`: A struct containing `device_lifecycle` (e.g., production, development) and `debug_locked` (boolean).\n- `scan_mode`: Indicates the SoC is entering scan test mode.\n- These inputs are latched at the deassertion of the system reset and drive all security‑sensitive decisions throughout the module’s operation.\n\n### 2.12 TRNG Interface\n- **External TRNG request** (`etrng_req`): Asserted when the module requires entropy from an external source.\n- **Internal TRNG data** (`itrng_data`, `itrng_valid`): Used only when `CALIPTRA_INTERNAL_TRNG` is defined; provides raw entropy bits from a physical source.\n\n### 2.13 Error and Status Outputs\n- `cptra_error_fatal`: Indicates a non‑recoverable error (e.g., fatal security violation).\n- `cptra_error_non_fatal`: Indicates a recoverable error (e.g., protocol failure).\n- `mailbox_data_avail`: Asserted when a new mailbox command is ready for consumption.\n- `mailbox_flow_done`: Asserted when the mailbox operation completes.\n- `ready_for_fuses`: The module is ready to receive fuse values from the SoC.\n- `ready_for_fw_push`: The module is ready to accept firmware into its instruction memory.\n- `ready_for_runtime`: The module has completed the boot sequence and is awaiting runtime mailbox commands.\n\n## 3. Operational Phases and Boot Flow\n\nUpon power‑up or reset, the module goes through three sequential phases:\n\n### Phase 1 – Fuse Loading\n- After reset deassertion, the module asserts `ready_for_fuses` to indicate it can accept fuse configuration data.\n- The SoC writes fuse values into designated mailbox registers. The module stores these in internal registers (obfuscation key, field entropy, UDS seed).\n- Once fuses are loaded, `ready_for_fuses` deasserts.\n\n### Phase 2 – Firmware Loading\n- The module asserts `ready_for_fw_push`.\n- The SoC writes the boot firmware image into the instruction memory (IMEM) via the mailbox.\n- The module waits for the firmware transfer to complete. When done, `ready_for_fw_push` deasserts.\n\n### Phase 3 – Runtime Execution\n- The module asserts `ready_for_runtime`.\n- The processor core starts executing from a pre‑programmed reset vector (located in the instruction memory).\n- The module is now ready to accept mailbox commands from the SoC.\n\n## 4. Cryptographic and Security Capabilities\n\nThe module includes the following hardware accelerators, accessible via the AHB bus:\n\n- **SHA‑256**: Message digest generation (FIPS 180‑4).\n- **SHA‑512**: Extended hash algorithm.\n- **HMAC‑SHA‑256 / HMAC‑SHA‑512**: Keyed‑hash message authentication.\n- **ECC (ECDSA)**: Elliptic‑curve digital signature generation and verification.\n- **DOE (Derived Key Engine)**: Key derivation from obfuscated secrets (UDS, FE, obfuscation key). Produces usage‑specific private keys.\n- **Key Vault (KV)**: Stores up to 5 key slots; supports read, write, and erase operations. Accessible only by authorized accelerators (SHA, HMAC, DOE, ECC).\n- **PCR Vault (PV)**: Stores platform configuration registers (PCRs) for attestation.\n- **Data Vault (DV)**: A dedicated memory region for sensitive data that is cleared on security state transitions.\n\nAll cryptographic operations can generate two types of interrupts:\n- *Notification interrupt* (informational, e.g., operation complete).\n- *Error interrupt* (fatal or non‑fatal failure).\n\n## 5. Security State and Secret Management\n\n- The `security_state` and `scan_mode` inputs are latched on the rising edge of the system reset deassertion.\n- The latched values determine the module’s behavior:\n  - When `debug_locked` is 0 (debug unlocked) or `scan_mode` is 1, the module substitutes its obfuscation key, UDS seed, and field entropy with synthetic debug values (defined in constants). This prevents real secrets from being exposed during debug.\n  - Additionally, an internal `clear_obf_secrets` signal is generated whenever the security state transitions from locked to unlocked, or when scan mode is entered. This signal triggers the zeroing of all obfuscation secret registers in the SoC interface and DOE blocks.\n- The latched security state is also exported to the processor core (via DMI register) and used to control JTAG debug access.\n\n## 6. Interrupt Structure\n\nThe processor core (VeeR EL2) receives up to 31 interrupt lines. The module maps error and notification interrupts from each accelerator and peripheral to fixed interrupt vectors. Unused vectors are tied low.\n\n| Interrupt Source          | Vector | Type          |\n|---------------------------|--------|---------------|\n| DOE error                 | 1      | Error         |\n| DOE notification          | 2      | Notification  |\n| ECC error                 | 3      | Error         |\n| ECC notification          | 4      | Notification  |\n| HMAC error                | 5      | Error         |\n| HMAC notification         | 6      | Notification  |\n| KV error                  | 7      | Error         |\n| KV notification           | 8      | Notification  |\n| SHA‑512 error             | 9      | Error         |\n| SHA‑512 notification      | 10     | Notification  |\n| SHA‑256 error             | 11     | Error         |\n| SHA‑256 notification      | 12     | Notification  |\n| QSPI error                | 13     | Error         |\n| QSPI notification         | 14     | Notification  |\n| UART error                | 15     | Error         |\n| UART notification         | 16     | Notification  |\n| I3C error                 | 17     | Error         |\n| I3C notification          | 18     | Notification  |\n| SoC interface error       | 19     | Error         |\n| SoC interface notification| 20     | Notification  |\n| SHA (generic) error       | 21     | Error         |\n| SHA (generic) notification| 22     | Notification  |\n\nAdditional interrupts (timer, external, software) are supplied directly by the SoC or internally tied off.\n\n## 7. Error Handling and Fatal Signals\n\n- `cptra_error_fatal` and `cptra_error_non_fatal` are driven from the SoC interface block based on mailbox error codes and security violations.\n- Fatal errors typically indicate an unrecoverable security condition (e.g., tamper detection); the module may stop processing further mailbox commands.\n- Non‑fatal errors allow continued operation after error recovery.\n\n## 8. Debug and Test Features\n\n- JTAG debug access is gated by the latched `debug_locked` bit. When locked, JTAG TDO is held inactive and all debug‑related DMI accesses are blocked.\n- The processor core provides halt/run controls via debug interface (`o_cpu_halt_ack`, `o_cpu_halt_status`, `o_cpu_run_ack`).\n- The module does not drive halt requests from the top level; it only responds to external debugger commands.\n- In scan mode (`scan_mode=1`), the module forces synthetic debug secrets as described in Section 5. Additionally, the core is forced into a scan‑friendly state (scan_mode is passed to the core).\n\n## 9. Clock Gating and Power Management\n\n- The module supports clock gating for power saving.\n- A dedicated clock gating unit generates two gated clocks:\n  - `clk_cg`: Used by all crypto accelerators, AHB bus, and peripherals. It is gated when the core is halted and no APB access is pending.\n  - `soc_ifc_clk_cg`: Used by the SoC interface only. It gates separately based on APB activity.\n- The gating control is driven by:\n  - APB select signal (PSEL)\n  - Processor halt status\n  - Generic input wires (platform‑specific control)\n- The main clock (`clk`) feeds the clock gating unit and the SoC interface directly.\n\n## 10. ICCM (Instruction Cache Memory) Locking\n\n- The processor’s instructional memory region (ICCM) can be locked by firmware via a control register in the SoC interface.\n- When locked, any AHB write transaction from an initiator (processor or debug) targeting the ICCM responder is blocked (hresp = error). Reads remain permitted.\n- The lock status is exported and used to disable the corresponding responder slot in the AHB decoder.\n\n## 11. Mailbox Protocol (Behavioral Summary)\n\n- The SoC initiates mailbox transactions by writing command, data, and destination registers over APB.\n- The module’s SoC interface stores the data in its mailbox SRAM (external).\n- When a complete command is available, `mailbox_data_avail` is asserted.\n- The processor core reads the command from SRAM, executes it, and writes the result.\n- Once the processor writes the response size register, `mailbox_flow_done` is asserted.\n- The SoC reads the response via APB.\n\n## 12. Security‑Sensitive Outputs and Flows\n\n- The module outputs `cptra_error_fatal` and `cptra_error_non_fatal` to the SoC for system‑level error handling.\n- The `generic_output_wires` vector provides a mechanism for the firmware to signal arbitrary status to the SoC (e.g., boot stage indicators).\n- All secret registers (obfuscation key, seeds) are zeroed automatically on any transition that reduces security (debug unlock, scan‑mode entry), preventing leakage during test or debug.\n\n## 13. Assumptions and Dependencies\n\n- The SoC is responsible for providing a stable clock and clean reset sequence.\n- The instruction memory and mailbox SRAM must be accessible and initialized before the module enters the firmware‑loading phase.\n- The security state inputs must be static during normal operation; transitions trigger secret clearing.\n- The internal TRNG (when enabled) expects raw entropy from a random source; timing and quality are not managed by this module.\n\n## 14. Non‑Functional Requirements (Behavioral)\n\n- All internal AHB‑Lite responder outputs must be stable (no unknowns) while the bus is active.\n- APB protocol timing shall be compliant with the standard APB specification.\n- Clock gating must preserve functional correctness: gated clocks may be turned off only when no transaction is in progress on the associated bus segments.\n- Interrupts are level‑sensitive; the core’s interrupt controller uses the vector number to dispatch to the appropriate handler."}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "spec": "# soc_ifc_top Behavioral Design Specification\n\n## 1. Overview\n\nThe `soc_ifc_top` module serves as the primary interface between an external SoC (System-on-Chip) and the Caliptra security subsystem. It manages communication, boot sequencing, mailbox transactions, SHA acceleration, watchdog timers, and system security features. The module arbitrates access between the SoC (via APB) and the internal microcontroller (uC, via AHB-Lite) to shared resources including the mailbox, functional registers, and SHA accelerator.\n\n## 2. Interfaces\n\n### 2.1 SoC APB Interface\nThe module shall implement a full APB slave interface.  \n- **Protocol**: APB (Advanced Peripheral Bus) – the module shall comply with APB timing and handshaking.  \n- **Address width**: 18 bits.  \n- **Data width**: 32 bits.  \n- **User width**: 32 bits (PAUSER signal for access filtering).  \n- **Behavior**:  \n  - The module shall respond to valid PSEL, PENABLE, PWRITE, PADDR, PWDATA, and PAUSER.  \n  - It shall produce PREADY, PRDATA, and PSLVERR.  \n  - A slave error (PSLVERR) shall be asserted if the request targets an invalid address, a write to a read-only register, or violates security/filtering rules.  \n\n### 2.2 uC AHB-Lite Interface\nThe module shall implement an AHB-Lite slave interface for the internal microcontroller.  \n- **Protocol**: AHB-Lite – the module shall respond to HADDR, HWDATA, HSEL, HWRITE, HREADY, HTRANS, HSIZE.  \n- **Address width**: 18 bits.  \n- **Data width**: 32 bits.  \n- **Behavior**:  \n  - The module shall assert HREADYOUT and provide HRDATA for reads.  \n  - It shall assert HRESP (error) only when a protocol error is detected (e.g., invalid address or security violation).  \n  - All transfers from the uC shall be treated as non‑SoC requests.  \n\n### 2.3 Debug and Manufacturing Interface (DMI)\nThe module shall provide a set of DMI registers accessible via dedicated port signals (cptra_uncore_dmi_reg_*).  \n- The DMI interface is used for debug and manufacturing operations.  \n- Supported DMI registers include:  \n  - `BOOTFSM_GO` (write) – allows forcing the boot FSM to continue after a breakpoint.  \n  - `CPTRA_DBG_MANUF_SERVICE_REG` (write) – holds a debug/manufacturing service data word.  \n  - `MBOX_DLEN`, `MBOX_DOUT`, `MBOX_STATUS` (read) – provide access to mailbox internal registers for debug.  \n  - `BOOT_STATUS`, `CPTRA_HW_ERROR_ENC`, `CPTRA_FW_ERROR_ENC` (read) – report status and error codes.  \n- A read to the `MBOX_DOUT` register shall automatically increment the mailbox read pointer when the DMI enable signal is deasserted after the read.  \n\n### 2.4 SRAM Interface\nThe module shall connect to a shared SRAM (mailbox memory) via an arbiter.  \n- The mailbox and SHA accelerator shall both be able to read/write the SRAM.  \n- The module shall generate correct SRAM request signals (address, data, control) and accept SRAM response signals (data, error flags).  \n\n### 2.5 Other Outputs\n- **Boot status outputs**: ready_for_fuses, ready_for_fw_push, ready_for_runtime.  \n- **Mailbox status**: mailbox_data_avail (data available to SoC), mailbox_flow_done.  \n- **Interrupt outputs**: error_fatal, error_non_fatal, trng_req, plus four dedicated interrupt lines (soC_ifc_error_intr, soC_ifc_notif_intr, sha_error_intr, sha_notif_intr).  \n- **Reset outputs**: cptra_noncore_rst_b (to all other blocks), cptra_uc_rst_b (to microcontroller core).  \n- **Clock gating enable**: clk_gating_en.  \n- **ICCM lock**: iccm_lock (locks firmware code memory).  \n- **NMI**: nmi_vector and nmi_intr.  \n- **Obfuscated key outputs**: cptra_obf_key_reg, obf_field_entropy, obf_uds_seed.  \n- **Generic wires**: input wires from SoC, output wires to SoC.  \n\n## 3. Boot Flow and Reset Management\n\n### 3.1 Power-Up Sequence\nThe module includes a boot finite-state machine that controls the Caliptra boot flow:  \n1. After `cptra_pwrgood` is asserted and `cptra_rst_b` is deasserted, the module shall assert `ready_for_fuses`.  \n2. The SoC must write the fuse data (including key manifest, owner keys, UDS, FE, etc.) to the functional registers.  \n3. Once the SoC sets `CPTRA_FUSE_WR_DONE`, the module shall deassert `ready_for_fuses` and assert `ready_for_fw_push`.  \n4. After firmware push is complete, the SoC must issue a `BootFSM_Continue` command (via register write).  \n5. The module shall then assert `ready_for_runtime` and release the microcontroller and peripheral resets (`cptra_noncore_rst_b`, `cptra_uc_rst_b`).  \n6. If firmware update reset is triggered (via `internal_fw_update_reset`), the boot FSM shall wait for a configurable number of cycles before re-entering the sequence.\n\n### 3.2 Reset Types and Reset Reason\nThe module shall maintain a reset reason register (`CPTRA_RESET_REASON`) with bits indicating:  \n- **Warm reset**: asserted when reset occurs without a power-good toggle.  \n- **Firmware update reset**: set when a firmware update reset is requested.  \nThe reset reason bits shall be sticky until the next cold reset or explicit clear.  \n\n### 3.3 Breakpoint Behavior\nIf `BootFSM_BrkPoint` input is asserted while the security state is in debug or manufacturing mode, the boot FSM shall pause at the next breakpoint. The boot FSM shall only continue when the SoC writes `CPTRA_BOOTFSM_GO`. The breakpoint shall be latched on the rising edge of `cptra_rst_b` (reset deassertion).  \n\n## 4. Mailbox Operation\n\n### 4.1 Arbitration\nThe module shall arbitrate between SoC APB requests and uC AHB requests for mailbox access using a round‑robin scheme. The request direction (SoC or uC) is determined by the `soc_req` flag in the request data. Requests from the SoC are filtered by a set of valid PAUSER values before being forwarded to the mailbox.\n\n### 4.2 Mailbox Protocol\nThe mailbox shall support the standard Caliptra mailbox protocol:  \n- SoC and uC can read/write mailbox data and control registers.  \n- The module shall generate interrupts to the uC (via `uc_mbox_data_avail`) when the SoC writes data to the mailbox.  \n- It shall generate `mailbox_data_avail` to the SoC when the uC writes data.  \n- The mailbox shall manage lock signals (`soc_req_mbox_lock`) to prevent concurrent access from both sides.  \n- Error flags (single‑ and double‑bit ECC) from the SRAM shall be propagated to the interrupt controller.  \n\n### 4.3 PAUSER Filtering\nThe module shall maintain a set of five valid PAUSER values for mailbox access from the SoC. These values can be set at integration time via module‑specific parameters or programmed by the SoC. Once locked via the respective `CPTRA_PAUSER_LOCK` register, the PAUSER values cannot be changed until the next reset. Only APB requests whose PAUSER matches a valid PAUSER shall be granted mailbox access.  \n\n## 5. SHA Accelerator\n\nThe module shall instantiate a SHA‑512 accelerator core.  \n- The SHA accelerator is accessible through the arbitration logic.  \n- Both SoC and uC can send requests to the SHA module (reads/writes to SHA registers).  \n- The SHA accelerator shall produce two interrupts: `sha_error_intr` (for errors) and `sha_notif_intr` (for notifications).  \n- The SHA accelerator may share the mailbox SRAM for data storage; arbitration between SHA and mailbox SRAM accesses is handled internally.  \n\n## 6. Watchdog Timer\n\nThe module shall include a two‑stage watchdog timer (WDT).  \n\n### 6.1 Timer Configuration\n- **Timer1** and **Timer2** can be independently enabled via control registers.  \n- Their timeout periods are programmable over multiple 32‑bit words.  \n- Each timer can be restarted by writing to its restart register.  \n\n### 6.2 Timeout Behavior\n- When Timer1 times out, it shall set a status bit (`t1_timeout`) and generate an interrupt pulse via the notification interrupt controller (if enabled).  \n- When Timer2 times out and Timer2 is enabled, it shall set status bit `t2_timeout` and generate an interrupt pulse.  \n- If Timer2 times out **and Timer2 is not enabled** (i.e., cascaded mode where Timer1 is the only active timer), the module shall:  \n  - Assert `cptra_error_fatal`.  \n  - Assert `nmi_intr` with `nmi_vector` value indicating a fatal WDT timeout.  \n  - Set the fatal hardware error code register accordingly.  \n- The WDT interrupt service routine may reset the timer by toggling the interrupt to clear, detected as a falling edge on the notification interrupt.  \n\n## 7. Interrupt Controller\n\nThe module shall aggregate multiple interrupt sources into two global interrupt lines:  \n- **Error interrupt** (`soc_ifc_error_intr`) – asserted if any error interrupt source is pending and enabled.  \n- **Notification interrupt** (`soc_ifc_notif_intr`) – asserted if any notification source is pending and enabled.  \n\n### 7.1 Interrupt Sources\n- **Fatal errors**: ICCM access blocked, SRAM double‑bit ECC error, mailbox ECC uncorrectable.  \n- **Non‑fatal errors**: To be defined.  \n- **Notification events**:  \n  - Command available (uC mailbox data).  \n  - SRAM single‑bit ECC corrected.  \n  - Security state debug locked change (any edge).  \n  - SoC request mailbox lock.  \n  - Watchdog timer1 timeout.  \n  - Watchdog timer2 timeout (if timer2 enabled).  \n- Each interrupt source has a separate enable and status register in the functional register block.  \n\n## 8. Security Features\n\n### 8.1 Obfuscated Key Storage\nThe module shall capture obfuscated key material at power‑up:  \n- Obfuscated key (`cptra_obf_key`) – stored in internal registers.  \n- UDS seed (`fuse_uds_seed`) and field entropy (`fuse_field_entropy`) – stored in fuse registers.  \n- These values shall only be sampled when `cptra_pwrgood` toggles and the security state is in debug locked mode **and** scan mode is disabled.  \n- All obfuscated registers shall be cleared to zero when `clear_obf_secrets` input is asserted.  \n\n### 8.2 Security State\nThe module shall monitor the `security_state` input (lifecycle and debug lock) and:  \n- Update a register reflecting the current security state.  \n- Generate a notification interrupt on any change of the debug locked field.  \n- Restrict certain operations (e.g., fuse burning) based on the lifecycle.  \n\n### 8.3 TRNG Access Filtering\nTRNG data registers and status write (`DATA_WR_DONE`) shall only be writable by the SoC if the request’s PAUSER matches the value programmed in `CPTRA_TRNG_VALID_PAUSER`. The valid PAUSER can be locked via `CPTRA_TRNG_PAUSER_LOCK`.  \n\n## 9. Error Handling\n\n### 9.1 Hardware Error Registers\nThe module shall maintain three error code registers:  \n- `CPTRA_HW_ERROR_FATAL` – set when a fatal hardware error occurs (e.g., WDT cascaded timeout).  \n- `CPTRA_HW_ERROR_NON_FATAL` – reserved for non‑fatal hardware errors.  \n- `CPTRA_FW_ERROR_FATAL`, `CPTRA_FW_ERROR_NON_FATAL` – reserved for firmware‑reported errors.  \n\nThe fatal error code shall be set by hardware; the non‑fatal and firmware error codes shall be written only by software.  \n\n### 9.2 External Error Indications\n- `cptra_error_fatal` – driven when a fatal error is signaled.  \n- `cptra_error_non_fatal` – reserved for future use, currently deasserted.  \n- `pslverr` on APB – asserted for invalid or non‑permitted accesses.  \n\n## 10. Register Access and Security\n\n### 10.1 Functional Registers\nThe module implements a set of memory‑mapped registers that control and report status of all subsystems. Registers are accessible by both SoC and uC, with per‑register read/write permissions as defined in the register specification.  \n\n### 10.2 Fuse Locking\nAfter the SoC sets `CPTRA_FUSE_WR_DONE`, many fuse registers become read‑only for the remainder of the power session. This includes:  \n- Key manifest hash, owner public key hash.  \n- UDS seed, field entropy.  \n- IDEVID certificate attributes and HSM ID.  \n- Runtime SVN values.  \n- Key manifest hash mask, FMC key manifest SVN, anti‑rollback disable, lifecycle state.  \n\nThe fuse‑write‑done bit itself shall only be written by the SoC (not the uC) and only if it is currently zero. The bit is cleared by a cold reset.  \n\n### 10.3 ICCM Lock\nThe module shall output a lock signal for the Instruction Code Memory (ICCM). The lock can be released by the firmware (via hardware clear). When the ICCM is locked, any access (read/write) from the uC shall be blocked, and a blocked-access indication (`iccm_axs_blocked`) shall set the appropriate error interrupt.  \n\n## 11. Clock Gating\n\nThe module shall output a `clk_gating_en` signal based on a register bit. When enabled, the parent module may gate the clock to the Caliptra subsystem for power saving.  \n\n## 12. Generic I/O Wires\n\nThe module shall provide two 32‑bit input wires from the SoC that are captured into a register, and two 32‑bit output wires driven from a register programmed by the SoC or uC. These wires can be used for custom control/status.  \n\n## 13. Reset Outputs\n\n- `cptra_noncore_rst_b`: driven low during boot until the boot FSM releases it; used to reset all non‑core blocks (SHA, mailbox, WDT, etc.).  \n- `cptra_uc_rst_b`: driven low until the boot FSM releases it; used to reset the microcontroller core.  \n- During a firmware update reset, the module shall sequence both resets according to a programmable wait cycle count.  \n\n## 14. Interrupt Outputs Summary\n\n| Signal | Trigger |\n|--------|---------|\n| `cptra_error_fatal` | Watchdog timer2 cascaded timeout, or other fatal HW error. |\n| `cptra_error_non_fatal` | Reserved (currently 0). |\n| `trng_req` | TRNG data request active. |\n| `soc_ifc_error_intr` | Any enabled error source. |\n| `soc_ifc_notif_intr` | Any enabled notification source. |\n| `sha_error_intr` | SHA accelerator error. |\n| `sha_notif_intr` | SHA accelerator notification. |\n| `nmi_intr` | Watchdog timer2 cascaded timeout (same as fatal error). |\n\n## 15. Environmental Constraints\n\n- The module shall operate correctly under the assumption that the SoC clock (`soc_ifc_clk_cg`) and system clock (`clk_cg`) are derived from the same source but may be gated independently.  \n- The module shall behave predictably regardless of scan mode status (scan_mode_f input), except for obfuscated key sampling which is disabled in scan mode.  \n- All outputs shall be driven to known values when the module is in reset.  \n- The module shall not generate X’s on any output under normal operating conditions.  \n\n## 16. Compliance\n\nThis specification is intended to describe the functional behavior of the `soc_ifc_top` module for the purpose of design, verification, and integration. All statements of “shall” and “must” define requirements that the module must satisfy."}

s2/chipsalliance__caliptra-rtl/chipsalliance__caliptra-rtl_s2_04_review_results.jsonl

@@ -0,0 +1,4 @@
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'must' and 'shall' to describe expected behavior, contains no patch details, and includes assertions about mailbox sanitization related to the patch's teardown delay."}
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+{"repo": "lowRISC/ibex", "pr_id": 294, "selected_doc_paths": ["doc/exception_interrupts.rst", "doc/debug.rst", "doc/cs_registers.rst", "doc/instruction_fetch.rst", "doc/integration.rst"], "reason": "These documents cover exception handling, interrupts, debug support, CSR registers, instruction fetch control, and core integration, which are the primary responsibilities of the ibex_controller module."}
+{"repo": "lowRISC/ibex", "pr_id": 295, "selected_doc_paths": ["doc/instruction_fetch.rst", "doc/load_store_unit.rst"], "reason": "These documents describe the memory interface protocol (request, grant, rvalid, rdata) that the slave driver simulates."}
+{"repo": "lowRISC/ibex", "pr_id": 286, "selected_doc_paths": ["doc/cs_registers.rst", "doc/exception_interrupts.rst", "doc/debug.rst", "doc/pmp.rst", "doc/performance_counters.rst"], "reason": "The module implements Control and Status Registers for Ibex, including interrupt handling, debug support, PMP, and performance counters; these documents provide the behavioral specification for those features."}
+{"repo": "lowRISC/ibex", "pr_id": 167, "selected_doc_paths": ["doc/exception_interrupts.rst", "doc/interrupts.rst", "doc/debug.rst", "doc/instruction_fetch.rst", "doc/cs_registers.rst"], "reason": "These documents cover the main functionality of the ibex_controller module, including instruction fetch control, exception and interrupt handling, debug support, and CSR operations."}
+{"repo": "lowRISC/ibex", "pr_id": 54, "selected_doc_paths": [], "reason": "No official document directly describes the compressed instruction decoder or its behavior; the available documents cover other aspects like integration, interrupts, and registers."}
+{"repo": "lowRISC/ibex", "pr_id": 196, "selected_doc_paths": ["doc/cs_registers.rst", "doc/debug.rst", "doc/exception_interrupts.rst", "doc/performance_counters.rst"], "reason": "These documents detail the CSR registers, debug causes, exception causes, and performance counter constants defined in ibex_pkg.sv, which are essential for writing a behavioral spec of the core."}
+{"repo": "lowRISC/ibex", "pr_id": 222, "selected_doc_paths": ["doc/register_file.rst", "doc/instruction_fetch.rst", "doc/exception_interrupts.rst", "doc/load_store_unit.rst", "doc/cs_registers.rst"], "reason": "These documents cover the register file, instruction fetch interface, exception/interrupt handling, load-store unit, and CSR operations directly instantiated or controlled in the instruction decode stage."}
+{"repo": "lowRISC/ibex", "pr_id": 176, "selected_doc_paths": ["doc/cs_registers.rst", "doc/debug.rst", "doc/exception_interrupts.rst", "doc/load_store_unit.rst", "doc/register_file.rst"], "reason": "These documents directly describe the behavior of CSR instructions, debug instructions, exception handling, load/store operations, and register file access, which are all decoded and controlled by the decoder module."}
+{"repo": "lowRISC/ibex", "pr_id": 172, "selected_doc_paths": ["doc/register_file.rst", "doc/load_store_unit.rst", "doc/cs_registers.rst", "doc/exception_interrupts.rst", "doc/debug.rst"], "reason": "These documents describe the register file, load-store unit, CSRs, exception/interrupt handling, and debug support, which are directly controlled by the decoder outputs."}
+{"repo": "lowRISC/ibex", "pr_id": 169, "selected_doc_paths": ["doc/register_file.rst", "doc/instruction_fetch.rst", "doc/load_store_unit.rst", "doc/exception_interrupts.rst"], "reason": "These documents describe the register file, instruction fetch interface, load-store unit interaction, and exception/interrupt handling, which are all key components of the ID stage module."}
+{"repo": "lowRISC/ibex", "pr_id": 166, "selected_doc_paths": ["doc/cs_registers.rst", "doc/exception_interrupts.rst", "doc/register_file.rst"], "reason": "These documents cover CSR operations, exception/interrupt handling, and register file behavior, which are directly relevant to the decoder's outputs and instruction decoding logic."}
+{"repo": "lowRISC/ibex", "pr_id": 48, "selected_doc_paths": [], "reason": "No document in the list is directly relevant to the compressed instruction decoder module."}
+{"repo": "lowRISC/ibex", "pr_id": 113, "selected_doc_paths": ["doc/integration.rst", "doc/instruction_fetch.rst", "doc/load_store_unit.rst"], "reason": "These documents describe the top-level integration, instruction fetch interface, and load-store unit interface, which are directly relevant to the behavioral specification of the ibex_core top-level module."}
+{"repo": "lowRISC/ibex", "pr_id": 157, "selected_doc_paths": ["doc/exception_interrupts.rst", "doc/debug.rst", "doc/instruction_fetch.rst"], "reason": "The controller handles exceptions, interrupts, debug mode entry, and instruction fetch control, making these documents essential for a behavioral specification."}
+{"repo": "lowRISC/ibex", "pr_id": 40, "selected_doc_paths": ["doc/register_file.rst", "doc/cs_registers.rst", "doc/load_store_unit.rst", "doc/exception_interrupts.rst", "doc/performance_counters.rst"], "reason": "These documents describe the register file, CSR operations, load/store unit interface, exception/interrupt handling, and performance counter outputs directly relevant to the decode stage's functionality."}
+{"repo": "lowRISC/ibex", "pr_id": 131, "selected_doc_paths": ["doc/register_file.rst", "doc/load_store_unit.rst", "doc/cs_registers.rst", "doc/exception_interrupts.rst", "doc/debug.rst"], "reason": "These documents describe subsystems (register file, load/store unit, CSRs, exceptions, debug) that are directly controlled by the decoder, providing essential spec details for its outputs."}

s2/lowRISC__ibex/lowRISC__ibex_s2_04_review_results.jsonl

@@ -0,0 +1,89 @@
+{"repo": "lowRISC/ibex", "pr_id": 2241, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses 'shall' to mandate behavior, avoids direct patch signal names, and includes a behavioral assertion about error sources forced to zero when RdataMuxCheck=0."}
+{"repo": "lowRISC/ibex", "pr_id": 2449, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses normative language, avoids patch-specific details, and includes behavioral assertions about clock and reset generation."}
+{"repo": "lowRISC/ibex", "pr_id": 2269, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language, does not reference patch details, and includes behavioral assertions about the legality of immediate ALU instructions based on RV32B configuration, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 2229, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, contains no patch-specific identifiers, and includes a section on target-specific reset behavior directly related to the patch area."}
+{"repo": "lowRISC/ibex", "pr_id": 2224, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall to describe correct behavior, does not contain signal names or line numbers from the patch beyond the inherent parameter name, and includes a behavioral assertion about x0 reads that directly relates to the fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1879, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses 'shall' to describe behavior, contains no patch-specific leaks, and includes behavioral assertions about alert_minor directly related to the icache glitch test."}
+{"repo": "lowRISC/ibex", "pr_id": 1881, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes behavior without negative terms, does not include patch-specific details like line numbers, and includes sufficient detail on register file read signals relevant to the glitch test."}
+{"repo": "lowRISC/ibex", "pr_id": 2307, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly uses shall/should for behavioral descriptions, contains no patch-specific identifiers, and includes a behavioral assertion about read vs write response capture related to the fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1816, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall/should, contains no patch details, and includes behavioral assertions about debug cause recording."}
+{"repo": "lowRISC/ibex", "pr_id": 2250, "passed": false, "checks": {"describes_correct_behavior": false, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec does not use must/shall/should modal verbs to describe correct behavior, but it avoids patch leakage and includes a behavioral assertion about error output when checks disabled."}
+{"repo": "lowRISC/ibex", "pr_id": 1488, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses behavioral language, does not include patch details, and contains a behavioral assertion about write timing."}
+{"repo": "lowRISC/ibex", "pr_id": 2261, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification correctly describes the core controller behavior without patch details, but it does not include any behavioral assertion about the simulation display message that was fixed by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1839, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch details, and includes behavioral assertions about PMP error handling for unaligned instructions, which directly addresses the alignment fix in the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1744, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses appropriate modal verbs to describe expected behavior, contains no patch-specific signal names or line numbers, and includes a behavioral assertion about debug entry priority relevant to the fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1780, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' statements to describe correct behavior, avoids patch-specific details, and includes a behavioral assertion about PMP write suppression under MML."}
+{"repo": "lowRISC/ibex", "pr_id": 1824, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the fixed interrupt behavior (MIE ignored in U mode, interrupts suppressed during single step) using shall statements, contains no patch-specific signal names, and includes behavioral assertions directly related to the modified functional area."}
+{"repo": "lowRISC/ibex", "pr_id": 1917, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (must/shall) to describe correct behavior, contains no patch-specific identifiers, and includes behavioral requirements regarding outstanding data access limits, which relate to the modified assertion logic."}
+{"repo": "lowRISC/ibex", "pr_id": 1975, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification lacks behavioral assertions directly verifying the correct application of the scramble key to icache memory primitives, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1446, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, contains no patch-specific code or line numbers, and includes a behavioral assertion that all parameters, including those from the patch, must be passed through unchanged."}
+{"repo": "lowRISC/ibex", "pr_id": 1735, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses descriptive language but includes normative statements like 'must match', does not leak patch-specific signals, and includes a behavioral assertion about pipeline flushes for PMP CSR writes."}
+{"repo": "lowRISC/ibex", "pr_id": 1554, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "Spec correctly describes port names from fixed RTL, no patch details, and includes behavioral assertion about alert ports."}
+{"repo": "lowRISC/ibex", "pr_id": 1547, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses mandatory language, avoids patch-specific details, and includes behavioral assertions about the ICache parameter handling, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 2251, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language to describe correct behavior, contains no patch-specific details, and includes a behavioral description of the fetch enable mechanism directly related to the modified assertion."}
+{"repo": "lowRISC/ibex", "pr_id": 1725, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes expected behavior using appropriate language, contains no patch-specific internals, and includes relevant behavioral assertions such as the outstanding request tracking and response validity conditions directly related to the data payload X-check fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1643, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses 'shall' for correct behavior, contains no patch-specific identifiers, and includes behavioral description of ICache RAM selection based on ICacheScramble."}
+{"repo": "lowRISC/ibex", "pr_id": 1595, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification accurately describes the behavior of the ram_2p module using normative language, does not contain any elements from the patch, and includes a behavioral assertion about byte enables that is directly relevant to the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1326, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses must/shall/should to describe correct behavior, contains no patch implementation details, and includes a behavioral assertion about valid_i being known, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1620, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the fetch enable behavior using shall-assertions, avoids explicit encoding from the patch, and includes a behavioral assertion about the bottom bit enabling fetch, which is directly related to the patch's modification."}
+{"repo": "lowRISC/ibex", "pr_id": 1107, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses prescriptive language, contains no patch details, and includes behavioral assertions relevant to debug mode and EBREAK handling."}
+{"repo": "lowRISC/ibex", "pr_id": 1443, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must to describe correct behavior, does not contain patch-specific details, and includes assertions that branch instructions only access RS1 and RS2, directly addressing the bug fixed by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1179, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses shall statements to describe correct PMP behavior, contains no patch-specific details, and includes a behavioral assertion about NAPOT address matching that is directly related to the fix for mask generation when PMPGranularity > 0."}
+{"repo": "lowRISC/ibex", "pr_id": 1699, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification includes signal name 'ctrl_fsm_cs' from the patch and lacks behavioral assertions related to DRET privilege checking."}
+{"repo": "lowRISC/ibex", "pr_id": 1300, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification describes ECC errors per bus-width beat, directly addressing the patch's granularity change, uses prescriptive must/shall/should language, and avoids any patch-specific signal names or line numbers."}
+{"repo": "lowRISC/ibex", "pr_id": 1216, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch-specific details, and includes a behavioral requirement about mispredict handling that directly relates to the modified assertion."}
+{"repo": "lowRISC/ibex", "pr_id": 1380, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses proper behavioral language (e.g., 'must', 'shall') and avoids any patch details, while implicitly asserting that mcounteren access legality depends only on privilege level, not on DbgTriggerEn."}
+{"repo": "lowRISC/ibex", "pr_id": 1130, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' for correct behavior, contains no patch-specific identifiers, and includes behavioral requirements for illegal instruction detection that cover the gorci fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1087, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (shall/must) and does not include patch-specific details, and it contains a behavioral assertion about FENCE.I behavior, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1136, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct behavior, avoids patch-specific implementation details, and includes a behavioral assertion that the DCSR 'cause' field is read-only."}
+{"repo": "lowRISC/ibex", "pr_id": 1002, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall/should to describe correct behavior, contains no patch-specific details, and includes behavioral assertions about the constant arrays and functions."}
+{"repo": "lowRISC/ibex", "pr_id": 1054, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses prescriptive language to describe the correct PMP locking behavior and contains a behavioral assertion about blocking writes to pmpaddr when the adjacent region is locked and in TOR mode."}
+{"repo": "lowRISC/ibex", "pr_id": 1037, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the interface behavior using shall statements, avoids direct patch details, and includes assertions about branch tracking relevant to the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1036, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct decoder behavior, contains no patch-specific identifiers, and includes an assertion about illegal instruction detection for all encodings, covering the shift instruction fix."}
+{"repo": "lowRISC/ibex", "pr_id": 1182, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (e.g., 'must read as zero') to describe correct PMP behavior, does not include any patch-specific identifiers or expressions, and includes a relevant behavioral assertion about PMP address read data masking."}
+{"repo": "lowRISC/ibex", "pr_id": 1050, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly describes the required behavior using normative language, contains no patch-specific code elements, and includes sufficient behavioral assertions about the new CSRs."}
+{"repo": "lowRISC/ibex", "pr_id": 699, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct assert macro behavior, contains no patch-specific identifiers, and includes behavioral descriptions of the error reporting mechanism that was modified."}
+{"repo": "lowRISC/ibex", "pr_id": 855, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses must/shall/should to describe correct behavior, contains no patch-specific names or code, and includes a behavioral assertion about ready/valid ordering that relates to the patch's functional area."}
+{"repo": "lowRISC/ibex", "pr_id": 969, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language and correctly describes decoder behavior without referencing patch details, and includes assertions about register address selection, which is the area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 1176, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification describes interface behavior normatively without using bug/fix language, it mentions signal names from the patch only as part of normal interface description, and it includes assertions about stalls and jump_set that directly relate to the single-step next PC fix."}
+{"repo": "lowRISC/ibex", "pr_id": 903, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses signal names introduced by the patch (region_match_gt, region_match_lt, region_match_eq, region_match_all), violating the no_patch_leakage check."}
+{"repo": "lowRISC/ibex", "pr_id": 470, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses declarative language to describe correct behavior without referencing bugs, contains no patch-internal signal names or expressions, and includes a behavioral assertion about the termination countdown delay."}
+{"repo": "lowRISC/ibex", "pr_id": 658, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The specification leaks the signal names instr_rdata_i and instr_rdata_alu_i from the patch, violating no_patch_leakage."}
+{"repo": "lowRISC/ibex", "pr_id": 835, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, avoids patch-specific internals, and includes assertions about load data suppression on error."}
+{"repo": "lowRISC/ibex", "pr_id": 854, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language and describes correct controller behavior without referencing patch details, and includes behavioral statements about exception qualification that relate to the modified area."}
+{"repo": "lowRISC/ibex", "pr_id": 836, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct jump and stall behavior, contains no patch-specific names or lines, and adequately covers the jump handling and stall logic area for diagnosis."}
+{"repo": "lowRISC/ibex", "pr_id": 560, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The specification includes the variable name 'enable_nested_irq' from the patch, violating the no_patch_leakage requirement."}
+{"repo": "lowRISC/ibex", "pr_id": 905, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification does not mention write mask granularity or the DataBitsPerMask parameter, which is the functional area modified by the patch, so it lacks a behavioral assertion directly related to the change."}
+{"repo": "lowRISC/ibex", "pr_id": 507, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language and provides behavioral assertions about the signature address parsing fix."}
+{"repo": "lowRISC/ibex", "pr_id": 640, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes intended behavior using shall statements, contains no leakage from the patch, and includes behavioral assertions about the inject_error function, which is the functional area of the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 813, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "Specification uses correct behavioral language but lacks explicit assertion that PMP error must be cleared when LSU returns to IDLE, which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 613, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly uses normative language to describe the misa register as read-only and hardwired, does not contain any patch-specific signals or expressions, and includes a behavioral assertion about the misa register which is the functional area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 408, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language (shall/should), avoids patch-specific signal names or line numbers, and includes an assertion about invalid compressed encodings mapping to c.unimp, which directly covers the functional change."}
+{"repo": "lowRISC/ibex", "pr_id": 377, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses prescriptive language and describes correct behavior without bug-related terms, avoids patch-specific signal names and implementation details, and includes behavioral assertions directly covering the changed error handling for misaligned accesses."}
+{"repo": "lowRISC/ibex", "pr_id": 693, "passed": false, "checks": {"describes_correct_behavior": false, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification does not use must/shall/should to describe correct behavior, but it accurately covers the reset behavior modified by the patch and avoids any patch-specific identifiers."}
+{"repo": "lowRISC/ibex", "pr_id": 461, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly states that the LSB of dpc is forced to 0, without using terms from the patch or citing specific signals, and this behavioral description directly addresses the change made."}
+{"repo": "lowRISC/ibex", "pr_id": 425, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly uses shall/must to describe behavior, avoids patch-specific implementation details, and includes behavioral assertions about response ordering and state expectations that relate to the modified assertion."}
+{"repo": "lowRISC/ibex", "pr_id": 295, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, avoids patch-specific identifiers, and includes assertions about grant timing and ordering relevant to the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 375, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/should to describe correct behavior, contains no patch-specific implementation details, and includes behavioral assertions about load instruction decoding, which is the area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 316, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly uses shall/should/must, contains no patch details, and includes a requirement about grant assertion directly relevant to the fixed latch."}
+{"repo": "lowRISC/ibex", "pr_id": 289, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, does not reference patch details, and includes a behavioral assertion about core_sleep_o, which is the signal added by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 54, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses 'shall' and 'must' to describe correct behavior, contains no patch details, and includes assertions about hint handling for modified instructions."}
+{"repo": "lowRISC/ibex", "pr_id": 167, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses shall/must to describe correct behavior, avoids patch-specific implementation details, and includes assertions about debug entry saving next PC, directly covering the fix."}
+{"repo": "lowRISC/ibex", "pr_id": 294, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly describes the expected behavior of fast interrupt ID assignment (IDs 16-30) and cause encoding using 'shall' statements, avoiding any patch-specific signal names, and includes relevant behavioral assertions for diagnosis."}
+{"repo": "lowRISC/ibex", "pr_id": 373, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language, contains no patch-specific details, and includes general behavioral assertions about register reporting for compressed instructions that cover the modified area."}
+{"repo": "lowRISC/ibex", "pr_id": 416, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' statements to describe correct behavior, does not leak patch details, and contains behavioral assertions about compressed instruction decoding and register access that directly relate to the fix for C.JALR/C.JAL RD write."}
+{"repo": "lowRISC/ibex", "pr_id": 272, "passed": false, "checks": {"describes_correct_behavior": false, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The specification fails to assert that DRET outside debug mode causes an illegal instruction exception, which is the core fix; thus it does not fully describe correct behavior and is insufficient for diagnosing the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 302, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec correctly describes NMI handling and mode retention without referencing the bug or patch details."}
+{"repo": "lowRISC/ibex", "pr_id": 401, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": false, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses signal names from the patch (e.g., pc_set_o, DBG_TAKEN_IF), which constitutes patch leakage."}
+{"repo": "lowRISC/ibex", "pr_id": 196, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification correctly states that the illegal instruction exception cause is 2, uses 'shall' for behavior, contains no patch details, and includes the relevant assertion."}
+{"repo": "lowRISC/ibex", "pr_id": 286, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification correctly states the reset value of dcsr.xdebugver as STD without referencing the patch or bugs."}
+{"repo": "lowRISC/ibex", "pr_id": 222, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses must/shall/should to describe correct behavior without mentioning bugs or fixes, contains no patch-specific details, and includes behavioral assertions about multi-cycle instruction handling related to the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 176, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct behavior, contains no patch-specific identifiers, and includes an assertion about LWU being illegal."}
+{"repo": "lowRISC/ibex", "pr_id": 169, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification describes correct behavior using prescriptive language, contains no patch-specific details, and includes a behavioral assertion about load errors preventing register file writes."}
+{"repo": "lowRISC/ibex", "pr_id": 48, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'must' and 'shall' to describe correct behavior, contains no patch-specific details, and includes assertions about C.MV and C.JR handling that directly cover the modified functional area."}
+{"repo": "lowRISC/ibex", "pr_id": 172, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses normative language to describe correct behavior, does not include patch-specific signal names or code, and includes a behavioral requirement that illegal instructions must clear jump/branch flags, directly covering the bug fix."}
+{"repo": "lowRISC/ibex", "pr_id": 113, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification describes core behavior using normative language but lacks any mention of the tracer or its signal connections, which is the area modified by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 40, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The spec uses shall statements, avoids patch details, and includes behavioral assertions relevant to the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 131, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The generated specification uses normative language to describe correct behavior, contains no leak of patch-specific signal names or line numbers, and includes sufficient detail on JALR and illegal instruction handling to diagnose the issues addressed by the patch."}
+{"repo": "lowRISC/ibex", "pr_id": 157, "passed": true, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": true}, "reasoning": "The specification uses 'shall' to describe correct debug entry behavior without referencing patch internals, and includes assertions about saving dpc/dcsr when entering debug mode, which is directly relevant to the patch fix."}
+{"repo": "lowRISC/ibex", "pr_id": 166, "passed": false, "checks": {"describes_correct_behavior": true, "no_patch_leakage": true, "sufficient_for_diagnosis": false}, "reasoning": "The generated specification does not include explicit behavioral assertions for the perpetual illegal branch condition detection and the illegal detection when instr[28] is set for register-register ALU operations, which are the key fixes in the patch."}

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+{"repo": "openhwgroup/cva6", "pr_id": 3171, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/RISCV_Instructions_RV32I.rst", "docs/01_cva6_user/Programmer_View.rst"], "reason": "These documents provide detailed behavioral specifications for instruction decoding, exception and interrupt handling, and the RISC-V instruction set, which are core functionalities of the decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 3168, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md"], "reason": "This document directly describes the instruction decode stage, which is the module's functionality, and provides the necessary details for writing a behavioral specification."}
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+{"repo": "openhwgroup/cva6", "pr_id": 3107, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/01_cva6_user/Interfaces.rst"], "reason": "The commit stage document describes the instruction commit ports and logic, which are directly used by the ITI module, while the Interfaces document likely covers the ITI interface signals and protocols."}
+{"repo": "openhwgroup/cva6", "pr_id": 3091, "selected_doc_paths": ["docs/03_cva6_design/issue_stage.md"], "reason": "This document describes the issue stage, which is the primary function of the issue_read_operands module, including operand forwarding and hazard detection."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2945, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst"], "reason": "The MMU.rst design document provides behavioral descriptions of the MMU, including TLB structures and replacement policies, which are directly relevant to the shared TLB module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2944, "selected_doc_paths": ["docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md"], "reason": "These documents directly describe the issue stage and execute stage, which are critical for understanding the instruction issue, operand fetching, and forwarding logic implemented in the issue_read_operands module."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2858, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents describe the CSR register layout, exception handling, MMU-related CSRs, PMP, performance counters, and custom cache control registers that are directly implemented in the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2833, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md"], "reason": "This document describes the design of the instruction decode stage, which is exactly the module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2830, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Custom_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/03_cva6_design/id_stage.md"], "reason": "These documents cover instruction decoding, CSR operations, exception/interrupt handling, custom and coprocessor instructions, and the decode stage design, which are directly relevant to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2809, "selected_doc_paths": [], "reason": "No available documents cover the L1.5 cache adapter or OpenPiton interface, which is the focus of the RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2802, "selected_doc_paths": ["docs/03_cva6_design/MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_CV64A6_MMU_list.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/PMA.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents cover the MMU design, CSR definitions, PMP/PMA access control, and the privileged RISC-V ISA specification that define the behavior of the memory management unit."}
+{"repo": "openhwgroup/cva6", "pr_id": 2751, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/01_cva6_user/Interfaces.rst"], "reason": "These documents describe the pipeline stages and interfaces that provide the signals probed by the RVFI module, essential for understanding the module's behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2728, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/RISCV_Instructions_RV32I.rst", "docs/01_cva6_user/RISCV_Instructions_RV32M.rst", "docs/01_cva6_user/RISCV_Instructions_RV32A.rst", "docs/01_cva6_user/RISCV_Instructions_RV32C.rst", "docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZba.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbc.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst", "docs/01_cva6_user/RISCV_Instructions_RVZbs.rst", "docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst", "docs/01_cva6_user/RISCV_Instructions_RVZicond.rst", "docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst", "docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/03_cva6_design/id_stage.md"], "reason": "These documents cover the instruction decoding, CSR operations, and exception/interrupt handling that are core to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2697, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "The wt_axi_adapter module connects L1 caches to an AXI bus, making the AXI Interface document essential for understanding the bus protocol, while the Cache Control document covers invalidation logic and cache management relevant to the module's operation."}
+{"repo": "openhwgroup/cva6", "pr_id": 2639, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst"], "reason": "This document describes the AXI interface, which is directly relevant to the wt_axi_adapter module that bridges L1 caches to the AXI bus."}
+{"repo": "openhwgroup/cva6", "pr_id": 2599, "selected_doc_paths": ["docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/03_cva6_design/MMU.rst"], "reason": "These documents describe the majority of CSRs implemented in the module (machine, supervisor, hypervisor, debug, floating-point, performance counters, PMP, cache control) and the trap/interrupt/exception handling logic, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 2594, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/03_cva6_design/MMU.rst", "docs/04_cv32a65x/riscv/priv.rst", "docs/06_cv64a6_mmu/riscv/priv.rst"], "reason": "These documents describe the CSR register layout, privilege levels, interrupt handling, MMU translation, and PMP configuration that directly correspond to the functionality implemented in the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2589, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents provide the programmers' view of CSR registers, including machine, supervisor, virtual supervisor, and custom CSRs, as well as exception and interrupt handling, which are essential for writing a behavioral specification of the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2587, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md"], "reason": "These documents directly describe the CSR registers, their behavior, and related features (PMP, interrupts, performance counters) that are implemented in the csr_regfile module."}
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+{"repo": "openhwgroup/cva6", "pr_id": 2469, "selected_doc_paths": ["docs/01_cva6_user/CSR_CV64A6_MMU.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md"], "reason": "These documents provide detailed CSR register descriptions, exception and interrupt handling, PMP configuration, and programmer-level view, which are essential for writing a behavioral spec of the CSR register file."}
+{"repo": "openhwgroup/cva6", "pr_id": 2468, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/04_cv32a65x/riscv/priv.rst"], "reason": "These documents describe the CSR register file behavior, privilege levels, exception handling, and programmer's view, which are essential for understanding the CSR regfile module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2429, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/AXI_Interface.rst"], "reason": "These documents cover the configuration parameters, PMA/PMP regions, and AXI interface that are defined in config_pkg.sv, which are essential for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2374, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents provide detailed descriptions of the CSR register file module and the CSR sets for various configurations, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 2302, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/04_cv32a65x/design/source/parameters_cv32a65x.rst"], "reason": "These documents describe the configuration parameters, PMP settings, CSR registers, and design-specific parameters that directly correspond to the fields and constraints in the uvme_cva6_cfg_c class."}
+{"repo": "openhwgroup/cva6", "pr_id": 2283, "selected_doc_paths": ["docs/04_cv32a65x/design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV32A60X_list.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst"], "reason": "These documents directly describe the CSR register file implementation, its registers, trap handling, and related subsystems, providing essential information for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2282, "selected_doc_paths": ["docs/04_cv32a65x/design/source/port_decoder.rst", "docs/04_cv32a65x/design/source/cva6_id_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents provide direct information about the decoder module's ports, integration in the ID stage, and exception handling, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 2273, "selected_doc_paths": ["docs/04_cv32a65x/design/source/port_load_store_unit.rst", "docs/03_cva6_design/MMU.rst", "docs/04_cv32a65x/design/source/port_load_unit.rst", "docs/04_cv32a65x/design/source/port_store_unit.rst", "docs/04_cv32a65x/design/source/port_lsu_bypass.rst", "docs/04_cv32a65x/design/source/traps.rst"], "reason": "These documents directly describe the LSU ports, MMU interface, load/store units, bypass logic, and exception handling, which are essential for writing a behavioral specification of the load_store_unit module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2259, "selected_doc_paths": [], "reason": "No official document is relevant to the tc_sram module as it is a generic SRAM macro, not directly related to the CVA6 core documentation."}
+{"repo": "openhwgroup/cva6", "pr_id": 2248, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CVA6_user_guide.rst"], "reason": "These documents describe the configuration parameters and overall system integration for the CVA6 core, which directly correspond to the parameters defined in the RTL config package."}
+{"repo": "openhwgroup/cva6", "pr_id": 2233, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst"], "reason": "These documents directly describe the CSR register file module, the list of CSRs, and the programmer's view of CSRs, including PMP, which are implemented by the RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2227, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents provide a behavioral description of the CSR register file module and the programmer-visible CSR registers implemented by this module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2170, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_caches.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents describe the cache architecture, cacheability regions, and cache control registers, which are essential for understanding the cache controller's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 2120, "selected_doc_paths": ["docs/04_cv32a65x_design/source/mmu.rst"], "reason": "The MMU document provides a behavioral specification of the memory management unit, which includes the TLB and its operation."}
+{"repo": "openhwgroup/cva6", "pr_id": 2097, "selected_doc_paths": ["docs/04_cv32a65x_design/source/parameters_cv32a65x.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents directly describe the configuration parameters of the CV32A65X core, which are set in the RTL config package and are essential for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 2035, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/CSRs.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md"], "reason": "These documents describe the CSR register file implementation, its register definitions, and behavior, which are directly relevant for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 2032, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe the instruction decode stage, decoder port, and exception handling, which are directly relevant to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 2019, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60X.rst"], "reason": "These documents provide direct behavioral specs and CSR definitions for the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 2015, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/04_cv32a65x_design/source/port_csr_regfile.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents cover the CSR register file specification, including machine/supervisor/hypervisor CSRs, trap handling, PMP, performance counters, and cache control, which are all implemented in the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1956, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CSR_CV32A60X.rst", "docs/01_cva6_user/CSR_CV32A60X_list.rst", "docs/01_cva6_user/CSR_CV32A60AX.rst", "docs/01_cva6_user/CSR_CV32A60AX_list.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/04_cv32a65x_design/source/CSRs.rst", "docs/04_cv32a65x_design/source/csr.rst", "docs/04_cv32a65x_design/source/csr_list.rst", "docs/04_cv32a65x_design/source/traps.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst", "docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md"], "reason": "These documents provide detailed descriptions of the CSR register file, CSR lists, traps, interrupts, PMP, cache control, performance counters, and the design of the csr_regfile module itself, which are directly relevant to understanding and specifying the behavior of the RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1955, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/04_cv32a65x_design/source/port_decoder.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst"], "reason": "These documents describe instruction decode, decoder ports, and exception handling which are core to the decoder module's behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1954, "selected_doc_paths": ["docs/05_cva6_apu/cva6_apu.rst", "docs/05_cva6_apu/cva6_testharness.md", "docs/04_cv32a65x_design/source/subsystem.rst"], "reason": "These documents describe the top-level APU system and subsystem integration, including FPGA-specific configurations and test harness, which are directly relevant to the ariane_xilinx module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1869, "selected_doc_paths": ["docs/04_cv32a65x_design/source/port_decoder.rst", "docs/04_cv32a65x_design/source/cva6_id_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst"], "reason": "These documents directly describe the decoder module's ports, the instruction decode stage, RISC-V instruction set details, exception handling, and CSR registers, which are essential for writing a behavioral spec for the decoder."}
+{"repo": "openhwgroup/cva6", "pr_id": 1860, "selected_doc_paths": ["docs/04_cv32a65x_design/source/cva6_csr_regfile.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst"], "reason": "These documents directly describe the CSR register file module, its programmable registers, and related exception/trap handling, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1856, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions_RV32I.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Introduction.rst", "docs/04_cv32a65x_design/source/instructions.rst"], "reason": "The RTL module defines legal opcodes for RV32I instructions and imports various verification components, so the instruction set documents and architectural introduction are most relevant for writing a behavioral spec of this verification environment."}
+{"repo": "openhwgroup/cva6", "pr_id": 1821, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/04_cv32a65x_design/source/subsystem.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents cover the AXI interface, cache subsystem architecture, and configuration parameters, which are essential for understanding the miss handler's external interfaces and behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1781, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/03_cva6_design/commit_stage.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst"], "reason": "These documents cover CSR definitions, trap/interrupt handling, PMP, performance counters, and commit stage, which are directly implemented in the csr_regfile module and necessary for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1771, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/issue_stage.md"], "reason": "The commit and issue stage documents describe the pipeline signals (commit_instr, commit_ack, issue_pointer, etc.) used by the RVFI module, which are essential for writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1750, "selected_doc_paths": ["docs/01_cva6_user/CVA6_user_guide.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/index.rst", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/pcgen_stage.md", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst"], "reason": "These documents cover the overall architecture, configuration parameters, and design of the core stages, which are essential for writing a behavioral spec of the ariane_pkg package that defines core constants and types."}
+{"repo": "openhwgroup/cva6", "pr_id": 1743, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/csr-from-ip-xact/cv32a60x/csr.rst", "docs/csr-from-ip-xact/cv32a60x/csr_list.rst", "docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md", "docs/04_cv32a6_design/source/CSRs.rst", "docs/04_cv32a6_design/source/csr.rst", "docs/04_cv32a6_design/source/csr_list.rst"], "reason": "These documents provide detailed descriptions of the CSR registers, their addresses, fields, and side effects, which are essential for understanding and specing the CSR register file behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1719, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/pcgen_stage.md"], "reason": "These design documents describe the execute stage and PC generation, which directly relate to branch unit functionality including target calculation and mispredict handling."}
+{"repo": "openhwgroup/cva6", "pr_id": 1626, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md", "docs/01_cva6_user/ip-xact/cva6_csr.rst", "docs/01_cva6_user/Programmer_View.rst", "docs/03_cva6_design/intro.rst"], "reason": "These documents provide detailed descriptions of the CSR registers, including configuration, cache control, performance counters, PMP, traps/interrupts, and the programmer's view, which are directly relevant to the csr_regfile module's functionality and would aid in writing a behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1610, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Custom_Instructions.rst"], "reason": "These documents describe the supported and custom instruction sets, which are directly relevant to generating unsupported instructions for verification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1589, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/Custom_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover instruction decoding, RISC-V ISA, exception/interrupt handling, CSR operations, custom instructions, and coprocessor interface, which are all essential for the decoder's behavioral specification."}
+{"repo": "openhwgroup/cva6", "pr_id": 1546, "selected_doc_paths": ["docs/01_cva6_user/CSR_Performance_Counters.rst"], "reason": "The document directly describes the performance counters and their CSR interface, which matches the RTL module's purpose."}
+{"repo": "openhwgroup/cva6", "pr_id": 1498, "selected_doc_paths": ["docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Parameters_Configuration.rst"], "reason": "These documents describe the PMP checks and configuration parameters directly used in the MMU module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1467, "selected_doc_paths": ["docs/03_cva6_design/ex_stage.md"], "reason": "The ex_stage.md document describes the execute stage, which includes the branch unit's functionality for branch target calculation, branch prediction resolution, and mispredict handling."}
+{"repo": "openhwgroup/cva6", "pr_id": 1368, "selected_doc_paths": ["docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/ip-xact/cva6_csr.md", "docs/01_cva6_user/ip-xact/cva6_csr.rst"], "reason": "These documents directly describe CSR registers, PMP, cache control, performance counters, traps/interrupts, and the IP-XACT CSR specification, all of which are implemented in the csr_regfile module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1355, "selected_doc_paths": ["docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/CV32A6_Control_Status_Registers.rst", "docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md"], "reason": "These documents cover instruction decoding, CSR operations, exception/interrupt handling, and the decode stage, which are directly relevant to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 1349, "selected_doc_paths": ["docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/intro.rst"], "reason": "These documents describe the commit stage and execute stage, which directly involve store buffer behavior, and the introduction provides context for the design."}
+{"repo": "openhwgroup/cva6", "pr_id": 1335, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/ip-xact/cva6_csr.rst"], "reason": "These documents cover the CSR register file, PMP, performance counters, cache control, traps/interrupts, and the IP-XACT register description, which are all directly implemented in the csr_regfile module and essential for writing a behavioral spec."}
+{"repo": "openhwgroup/cva6", "pr_id": 1329, "selected_doc_paths": ["docs/01_cva6_user/CVA6_user_guide.rst", "docs/01_cva6_user/Introduction.rst", "docs/01_cva6_user/Interfaces.rst", "docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/03_cva6_design/index.rst", "docs/03_cva6_design/intro.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/issue_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst", "docs/03_cva6_design/pcgen_stage.md"], "reason": "These documents cover the top-level module architecture, interfaces, pipeline stages, and configuration, which are essential for writing a behavioral specification of the CVA6 core."}
+{"repo": "openhwgroup/cva6", "pr_id": 1302, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CSR_Cache_Control.rst", "docs/01_cva6_user/PMA.rst", "docs/03_cva6_design/intro.rst"], "reason": "These documents cover cache parameters, control registers, memory attributes, and overall design that are essential for specifying the cache subsystem behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 1280, "selected_doc_paths": ["docs/01_cva6_user/CVX_Interface_Coprocessor.rst", "docs/01_cva6_user/Custom_Instructions.rst"], "reason": "These documents describe the CVX interface and custom instruction support, which are directly related to the coprocessor module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1236, "selected_doc_paths": ["docs/03_cva6_design/id_stage.md", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/RISCV_Instructions.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover instruction decoding, exception/interrupt handling, the RISC-V instruction set, and the CVXIF interface, which are all directly relevant to the decoder module's functionality."}
+{"repo": "openhwgroup/cva6", "pr_id": 1123, "selected_doc_paths": [], "reason": "The module is a simulation trace utility class, not a core functional block, so no official design document directly describes it."}
+{"repo": "openhwgroup/cva6", "pr_id": 1117, "selected_doc_paths": ["docs/01_cva6_user/CV64A6_Control_Status_Registers.rst", "docs/01_cva6_user/Traps_Interrupts_Exceptions.rst", "docs/01_cva6_user/PMP.rst", "docs/01_cva6_user/CSR_Performance_Counters.rst", "docs/01_cva6_user/CSR_Cache_Control.rst"], "reason": "These documents detail the CSR register map, trap and interrupt handling, PMP configuration, performance counters, and cache control CSRs, which are the primary components of the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1105, "selected_doc_paths": ["docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/PMA.rst", "docs/01_cva6_user/PMP.rst", "docs/03_cva6_design/if_stage.md", "docs/03_cva6_design/id_stage.md", "docs/03_cva6_design/ex_stage.md", "docs/03_cva6_design/commit_stage.rst"], "reason": "These documents cover the global configuration parameters, memory region rules (PMA/PMP), and pipeline stage definitions that are directly referenced in the ariane_pkg.sv module."}
+{"repo": "openhwgroup/cva6", "pr_id": 1103, "selected_doc_paths": ["docs/01_cva6_user/AXI_Interface.rst", "docs/01_cva6_user/Core_Integration.rst", "docs/01_cva6_user/Parameters_Configuration.rst", "docs/01_cva6_user/CVX_Interface_Coprocessor.rst"], "reason": "These documents cover the AXI interface, core integration, parameter configuration, and coprocessor interface, which are essential for writing a behavioral spec of the ariane top-level module."}
+{"repo": "openhwgroup/cva6", "pr_id": 957, "selected_doc_paths": ["docs/id_stage.md", "docs/design_spec/source/cva6_frontend.rst"], "reason": "These documents cover instruction decode and frontend logic, which directly involve the compressed decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 937, "selected_doc_paths": ["docs/ex_stage.md"], "reason": "The multiplier module is part of the execute stage, and the ex_stage.md document describes the execute stage which includes multiplication."}
+{"repo": "openhwgroup/cva6", "pr_id": 933, "selected_doc_paths": ["docs/id_stage.md", "docs/issue_stage.md"], "reason": "The decoder module handles instruction decoding and operand fetch, which are described in the instruction decode and issue stage documents."}
+{"repo": "openhwgroup/cva6", "pr_id": 923, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module performs instruction decoding, immediate generation, and exception handling, which are described in the instruction decode stage documentation."}
+{"repo": "openhwgroup/cva6", "pr_id": 922, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module implements instruction decoding, which is the primary subject of the instruction decode stage documentation."}
+{"repo": "openhwgroup/cva6", "pr_id": 921, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The id_stage.md document directly describes the instruction decode stage, which is the primary functionality of the decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 908, "selected_doc_paths": ["docs/specifications/cva6_requirement_specification.rst"], "reason": "This document contains the requirements for the CVA6 core, which would include specifications for the MMU module."}
+{"repo": "openhwgroup/cva6", "pr_id": 823, "selected_doc_paths": [], "reason": "None of the provided documents specifically describe the CSR register file or its behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 796, "selected_doc_paths": ["docs/ex_stage.md", "docs/issue_stage.md"], "reason": "The serdiv module is a serial divider used in the execute stage; these documents describe the execution pipeline and issue stage which are most relevant to its operation."}
+{"repo": "openhwgroup/cva6", "pr_id": 792, "selected_doc_paths": [], "reason": "None of the available documents specifically describe CSR registers or the csr_regfile module behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 765, "selected_doc_paths": ["docs/commit_stage.rst"], "reason": "The commit stage document describes how exceptions are committed and how CSR registers are updated, which is directly related to the CSR register file module."}
+{"repo": "openhwgroup/cva6", "pr_id": 756, "selected_doc_paths": ["docs/if_stage.md", "docs/pcgen_stage.md"], "reason": "The frontend module handles instruction fetch and PC generation, which are described in the if_stage and pcgen_stage documents."}
+{"repo": "openhwgroup/cva6", "pr_id": 734, "selected_doc_paths": [], "reason": "No available document covers the CSR register file module directly."}
+{"repo": "openhwgroup/cva6", "pr_id": 724, "selected_doc_paths": ["docs/id_stage.md"], "reason": "The decoder module is the core of the instruction decode stage, and the id_stage.md document provides the behavioral specification for this stage."}
+{"repo": "openhwgroup/cva6", "pr_id": 695, "selected_doc_paths": ["docs/issue_stage.md"], "reason": "The re_name module performs register renaming, which is part of the issue stage, as described in the issue stage documentation."}
+{"repo": "openhwgroup/cva6", "pr_id": 644, "selected_doc_paths": [], "reason": "No document in the provided list is specifically relevant to the page table walker module."}
+{"repo": "openhwgroup/cva6", "pr_id": 507, "selected_doc_paths": [], "reason": "None of the provided documents cover physical memory protection (PMP) functionality; they focus on pipeline stages."}
+{"repo": "openhwgroup/cva6", "pr_id": 475, "selected_doc_paths": ["docs/_docs/arch/if_stage.md"], "reason": "The frontend module implements the instruction fetch stage, which is described in the IF stage document."}
+{"repo": "openhwgroup/cva6", "pr_id": 395, "selected_doc_paths": [], "reason": "No document covers compressed instruction decoding or the compressed decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 180, "selected_doc_paths": [], "reason": "No available documents cover the debug module memory (dm_mem) or related debug architecture."}
+{"repo": "openhwgroup/cva6", "pr_id": 156, "selected_doc_paths": ["docs/_docs/arch/id_stage.md"], "reason": "The id_stage.md document likely covers instruction decoding, which is the core function of the compressed decoder module."}
+{"repo": "openhwgroup/cva6", "pr_id": 80, "selected_doc_paths": [], "reason": "None of the available documents specifically describe the load unit, memory subsystem, or cache/MMU interfaces needed for a behavioral spec of this RTL module."}
+{"repo": "openhwgroup/cva6", "pr_id": 74, "selected_doc_paths": [], "reason": "No available official document directly describes the cache controller module or its behavior."}
+{"repo": "openhwgroup/cva6", "pr_id": 27, "selected_doc_paths": [], "reason": "None of the available documents cover the multiplier or divider implementation details needed for a behavioral spec of this RTL module."}