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@@ -58,3 +58,8 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 # Video files - compressed
 *.mp4 filter=lfs diff=lfs merge=lfs -text
 *.webm filter=lfs diff=lfs merge=lfs -text
+collect/chipsalliance/chipsalliance__caliptra-rtl_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
+collect/lowRISC/lowRISC__ibex_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -text
+collect/lowRISC/lowRISC__ibex_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text
+collect/openhwgroup/openhwgroup__cva6_s01_01_prs.jsonl filter=lfs diff=lfs merge=lfs -text
+collect/openhwgroup/openhwgroup__cva6_s01_05_patches.jsonl filter=lfs diff=lfs merge=lfs -text

collect/chipsalliance/chipsalliance__caliptra-rtl_s01_05_patches.jsonl

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dc545987dfaf6f3721ac30caa0d84126bd1e5b60660efc0008ae3c2c336fc4ec
+size 176268751

collect/chipsalliance/chipsalliance__caliptra-rtl_s01_06_single_rtl_candidates.jsonl

@@ -0,0 +1,4 @@
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 482, "lang": "sv", "rtl_files": ["src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "commit_id": "55f5f95fb2b352be2f9c6482142fcc63763e0d31", "timestamp": "2024-03-29T19:25:01+00:00", "pr_title": "[UVM] Implement mailbox sanitize feature in val fw to suppress regression failure", "pr_body": "Implement a firmware feature (for the validation code used in UVM tests) to sanitize the mailbox after detecting double-bit ECC error, to mirror the workaround required in 1.1 Firmware as per https://github.com/chipsalliance/caliptra-rtl/issues/399.\r\n\r\nThis is a temporary solution that should be removed for 2.0, as the mailbox should be modified to avoid spurious data prefetches.", "issue_title": "Caliptra uC is reading one extra entry from Mailbox SRAM causing unexpected ECC errors", "issue_body": "Hi, We are bringing up Mailbox testcases and observed the following scenario where an unexpected ECC error is getting fired. Below is our sequence.\r\n\r\n1. SOC acquires the MBOX lock by reading MBOX_LOCK register. It returns 0 indicating that the lock has been acquired by SOC.\r\n2. SOC writes MBOX command register.\r\n3. SOC writes MBOX_DLEN register to 8 indicating that it has 8 bytes of data to write.\r\n4. SOC writes MBOX_DATAIN register twice. This causes two writes to SRAM mailbox at addresses 0x0 and 0x1.\r\n5. SOC writes MBOX_EXECUTE to 1 in order for uC to process the mailbox command.\r\n6. When the mailbox state machine is in MBOX_EXECUTE_UC state, we are observing that Caliptra is reading SRAM mailbox at addresses 0x0, 0x1 and 0x2. The first two are expected as DLEN is 8. However the data at address 0x2 are all X and hence ECC error signal (soc_ifc_top1.i_mbox.sram_double_ecc_error) is going X.\r\n\r\nWe want to understand why the mailbox state machine is reading one extra entry from SRAM (DLEN + 4 bytes instead of DLEN bytes). Since the Mailbox SRAM is not initialized on reset, reading from addresses where there have been no previous writes will cause unexpected ECC errors.\r\n\r\nDo Caliptra ROM initializes Mailbox SRAM during bring up?\r\n\r\nMailbox Command from SOC\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/0e81da11-df93-41e0-a60c-872d2a749bdc)\r\n\r\nECC error while Mailbox state machine is reading from address 0x2\r\n![image](https://github.com/chipsalliance/caliptra-rtl/assets/131188754/b3a0e590-1662-4780-8afc-e0275c8537b4)\r\n", "commit_message": "Typo fix in comment", "fix_patch": "diff --git a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\nindex 2a1bcd3b3..a117b2a0c 100644\n--- a/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n+++ b/src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh\n@@ -40,6 +40,8 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n \n   `uvm_object_utils( soc_ifc_env_mbox_sram_double_bit_flip_sequence )\n \n+  extern virtual task mbox_teardown();\n+\n   // Constrain command to undefined opcode\n   constraint mbox_cmd_undef_c { !(mbox_op_rand.cmd.cmd_s inside {defined_cmds}); }\n \n@@ -105,3 +107,13 @@ class soc_ifc_env_mbox_sram_double_bit_flip_sequence extends soc_ifc_env_mbox_se\n   endtask\n \n endclass\n+\n+//==========================================\n+// Task:        mbox_teardown\n+// Description: At end-of-sequence, inject some stalls to allow\n+//              uC to acquire lock and sanitize the mailbox\n+//==========================================\n+task soc_ifc_env_mbox_sram_double_bit_flip_sequence::mbox_teardown();\n+    do_rand_delay(1, DLY_MEDIUM);\n+    super.mbox_teardown();\n+endtask\n", "test_patch": "diff --git a/src/integration/test_suites/caliptra_rt/caliptra_rt.c b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\nindex 9939a2515..417f10e6d 100644\n--- a/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n+++ b/src/integration/test_suites/caliptra_rt/caliptra_rt.c\n@@ -322,6 +322,7 @@ void caliptra_rt() {\n         if (cptra_intr_rcv.soc_ifc_notif   ) {\n             uint8_t fsm_chk;\n             uint8_t fail = 0;\n+            uint32_t dlen_received;\n             VPRINTF(LOW, \"Intr received: soc_ifc_notif\\n\");\n             if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK) {\n                 CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_notif, ~SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_CMD_AVAIL_STS_MASK)\n@@ -379,6 +380,7 @@ void caliptra_rt() {\n                 }\n                 //read the mbox command\n                 op = soc_ifc_read_mbox_cmd();\n+                dlen_received = op.dlen;\n                 if (op.cmd & MBOX_CMD_FIELD_FW_MASK) {\n                     VPRINTF(MEDIUM, \"Received mailbox firmware command from SOC! Got 0x%x\\n\", op.cmd);\n                     if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {\n@@ -517,6 +519,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else if (fail) {\n                         VPRINTF(LOW, \"Cmd failed\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n@@ -564,6 +574,14 @@ void caliptra_rt() {\n                         CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)\n                         VPRINTF(LOW, \"Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\\n\");\n                         soc_ifc_set_mbox_status_field(CMD_FAILURE);\n+                        // TODO Remove the mailbox sanitization op in Gen2 validation framework.\n+                        //      In Gen2, Caliptra Mailbox code should be modified to avoid spurious\n+                        //      SRAM prefetches that make this sanitization necessary after a double-bit\n+                        //      ECC error\n+                        if (soc_ifc_sanitize_mbox_n_bytes(dlen_received >= (MBOX_DIR_SPAN) ? MBOX_DIR_SPAN : dlen_received, 0xfff) != 0) {\n+                            SEND_STDOUT_CTRL(0x1);\n+                            while(1);\n+                        }\n                     } else {\n                         soc_ifc_set_mbox_status_field(CMD_COMPLETE);\n                     }\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\nindex c7270fb2d..299846807 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.c\n@@ -108,6 +108,15 @@ void soc_ifc_clr_flow_status_field(uint32_t field) {\n     lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS,reg);\n }\n \n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count) {\n+    for(uint32_t ii=0; ii<attempt_count; ii++) {\n+        if((lsu_read_32(CLP_MBOX_CSR_MBOX_LOCK) & MBOX_CSR_MBOX_LOCK_LOCK_MASK) != 0) {\n+            return 0;\n+        }\n+    }\n+    return 1;\n+}\n+\n mbox_op_s soc_ifc_read_mbox_cmd() {\n     mbox_op_s op;\n \n@@ -226,6 +235,22 @@ void soc_ifc_fw_update(mbox_op_s op) {\n         }\n }\n \n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count) {\n+    if (byte_count > MBOX_DIR_SPAN) {\n+        VPRINTF(FATAL, \"SOC_IFC: Illegal byte_count 0x%x\\n\", byte_count);\n+        SEND_STDOUT_CTRL(0x1);\n+    }\n+    if (soc_ifc_mbox_acquire_lock(attempt_count) != 0) {\n+        VPRINTF(ERROR, \"ERROR: Failed to acquire lock for mbox sanitize operation\\n\");\n+        return 1;\n+    }\n+    for (uint32_t ii=0; ii < byte_count; ii+=4) {\n+        lsu_write_32(MBOX_DIR_BASE_ADDR+ii, 0x0);\n+    }\n+    lsu_write_32(CLP_MBOX_CSR_MBOX_UNLOCK, MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK);\n+    return 0;\n+}\n+\n void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {\n     uint32_t reg;\n     VPRINTF(MEDIUM,\"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\\n\", wait_cycles, wait_cycles > 5 ? \"will override\" : wait_cycles > 0 ? \"will use default 5\" : \"won't override\");\ndiff --git a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\nindex 22e415442..84f6ad365 100644\n--- a/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n+++ b/src/integration/test_suites/libs/soc_ifc/soc_ifc.h\n@@ -112,9 +112,11 @@ inline void soc_ifc_set_iccm_lock() {\n     lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);\n }\n // Mailbox command flows\n+uint8_t soc_ifc_mbox_acquire_lock(uint32_t attempt_count);\n mbox_op_s soc_ifc_read_mbox_cmd();\n void soc_ifc_mbox_fw_flow(mbox_op_s op);\n void soc_ifc_fw_update(mbox_op_s op);\n+uint8_t soc_ifc_sanitize_mbox_n_bytes(uint32_t byte_count, uint32_t attempt_count);\n \n // SHA Accelerator Functions\n void soc_ifc_sha_accel_acquire_lock();\n", "modified_files": ["src/integration/test_suites/caliptra_rt/caliptra_rt.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.c", "src/integration/test_suites/libs/soc_ifc/soc_ifc.h", "src/soc_ifc/uvmf_soc_ifc/uvmf_template_output/verification_ip/environment_packages/soc_ifc_env_pkg/sequences/mbox/soc_ifc/soc_ifc_env_mbox_sram_double_bit_flip_sequence.svh"], "lines_added": 57, "lines_removed": 0}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 204, "lang": "sv", "rtl_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "commit_id": "76d7c90fc8eab682519676e12d3e1599040df43b", "timestamp": "2023-09-08T16:04:47+00:00", "pr_title": "Fixing LEC reported in caliptra_prim_assert_sec_cm.svh", "pr_body": "This error was flagged in https://github.com/chipsalliance/caliptra-rtl/issues/186.  Removing the assertions altogether since they are not used in the current design.", "issue_title": "Formality LEC Failure Verilog 527:   (error) Syntax error found in the definition of argument macro ", "issue_body": "LEC Formality_Error_Code  reported in caliptra_prim_assert_sec_cm.svh\r\n\r\nError: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 49)  (Formality_Error_Code)\r\n1361:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 52)  (Formality_Error_Code)\r\n1362:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 55)  (Formality_Error_Code)\r\n1363:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 58)  (Formality_Error_Code)\r\n1364:Error: Syntax error found in the definition of argument macro `CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR`. (File: RTL/inc/caliptra_prim_assert_sec_cm.svh Line: 61)  (Formality_Error_Code)\r\n\r\n[caliptra_fm_errors.tar.gz](https://github.com/chipsalliance/caliptra-rtl/files/12352228/caliptra_fm_errors.tar.gz)\r\n\r\n", "commit_message": "Fixing LEC Formality_Error_Code reported in caliptra_prim_assert_sec_cm.svh\n\nhttps://github.com/chipsalliance/caliptra-rtl/issues/186", "fix_patch": "diff --git a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\nindex 11ba287e0..096b7b61f 100644\n--- a/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n+++ b/src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh\n@@ -45,21 +45,4 @@\n   `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \\\n     REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_)\n \n-// macros for security countermeasures that will trigger other errors\n-`define CALIPTRA_ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, unused_err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = 2, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, err_o, CLK_, RST_)\n-\n-`define CALIPTRA_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(NAME_, REG_TOP_HIER_, ERR_, GATE_ = 0, MAX_CYCLES_ = `_CALIPTRA_SEC_CM_ALERT_MAX_CYC, CLK_ = clk_i, RST_ = !rst_ni) \\\n-  `CALIPTRA_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ERR(NAME_, \\\n-    REG_TOP_HIER_.u_caliptra_prim_reg_we_check.u_caliptra_prim_onehot_check, ERR_, GATE_, MAX_CYCLES_, CLK_, RST_)\n-\n `endif // PRIM_ASSERT_SEC_CM_SVH\n", "test_patch": "", "modified_files": ["src/caliptra_prim/rtl/caliptra_prim_assert_sec_cm.svh"], "lines_added": 0, "lines_removed": 17}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 92, "lang": "sv", "rtl_files": ["src/integration/rtl/caliptra_top.sv"], "commit_id": "02f97acf731c1dae6275883b4ccd200cee01e998", "timestamp": "2023-05-29T15:13:01+00:00", "pr_title": "Connection of the SB (debug) bus in Caliptra", "pr_body": "This PR connects `SB` and `LSU` AHB buses together using a 2:1 mux so that access to peripherals is possible via the JTAG port.\r\n\r\n**! This PR is required for the CI in https://github.com/chipsalliance/caliptra-rtl/pull/72 to pass !**", "issue_title": "Enable using OpenOCD for interactive debugging of simulated Caliptra core", "issue_body": "This PR adds support for OpenOCD's `remote_bitbang` virtual adapter driver that allows to tap into the running verilated simulation of Caliptra RTL.\r\n\r\nTo achive this several components are added:\r\n- `tcp_server`\r\n  Acts as a communication bridge between OpenOCD and the simulation\r\n- `jtagdpi`\r\n  Parses OpenOCD commands, formats replies and interacts with the simulation via DPI calls\r\n- OpenOCD scripts (`tools/scripts/openocd`)\r\n  These define the interface and target for OpenOCD\r\n\r\nTo connect to a running simulation first build and run the special `infinite_loop` test:\r\n```\r\nmake -f ${CALIPTRA_ROOT}/tools/scripts/Makefile TESTNAME=infinite_loop verilator\r\n```\r\nThen connect to it via OpenOCD (assuming that OpenOCD is installed):\r\n```\r\ncd tools/scripts/openocd\r\nopenocd -f board/caliptra-verilator.cfg\r\n```\r\nFinally start a debugging session with GDB by connecting to OpenOCD. Upon running GDB issue the following command:\r\n```\r\ntarget remote :3333\r\n```\r\nIf everything worked correctly you should be able to eg. dump the RISC-V core registers in GDB:\r\n```\r\ninfo registers\r\n```\r\n\r\nThe PR also includes a new workflow `Interactive debugging` which runs the flow described above in CI and performs various debugging actions. The tests in the new flow include:\r\n\r\n- Core register access via GDB + OpenOCD\r\n- Memory access (ICCM, DCCM and ROM)\r\n- Peripheral access\r\n- Peripheral access while the core is forcibly held in reset", "commit_message": "Added 2:1 AHB lite mux on LSU and SB buses to allow debug access to peripherals\n\nSigned-off-by: Maciej Kurc <mkurc@antmicro.com>", "fix_patch": "diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv\nindex 1dcd23645..f59d9c221 100755\n--- a/src/integration/rtl/caliptra_top.sv\n+++ b/src/integration/rtl/caliptra_top.sv\n@@ -276,6 +276,17 @@ end\n     //========================================================================\r\n     // AHB Master ports\r\n     //========================================================================\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    sb_ahb();\r\n+    CALIPTRA_AHB_LITE_BUS_INF #(\r\n+        .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n+    )\r\n+    lsu_ahb();\r\n+\r\n     CALIPTRA_AHB_LITE_BUS_INF #(\r\n         .AHB_LITE_ADDR_WIDTH(`CALIPTRA_AHB_HADDR_SIZE),\r\n         .AHB_LITE_DATA_WIDTH(`CALIPTRA_AHB_HDATA_SIZE)\r\n@@ -403,34 +414,34 @@ el2_veer_wrapper rvtop (\n     //---------------------------------------------------------------\r\n     // Debug AHB Master\r\n     //---------------------------------------------------------------\r\n-    .sb_haddr               (),\r\n-    .sb_hburst              (),\r\n-    .sb_hmastlock           (),\r\n-    .sb_hprot               (),\r\n-    .sb_hsize               (),\r\n-    .sb_htrans              (),\r\n-    .sb_hwrite              (),\r\n-    .sb_hwdata              (),\r\n-\r\n-    .sb_hrdata              ('0),\r\n-    .sb_hready              ('0),\r\n-    .sb_hresp               ('0),\r\n+    .sb_haddr               ( sb_ahb.haddr   ),\r\n+    .sb_hburst              (                ),\r\n+    .sb_hmastlock           (                ),\r\n+    .sb_hprot               (                ),\r\n+    .sb_hsize               ( sb_ahb.hsize   ),\r\n+    .sb_htrans              ( sb_ahb.htrans  ),\r\n+    .sb_hwrite              ( sb_ahb.hwrite  ),\r\n+    .sb_hwdata              ( sb_ahb.hwdata  ),\r\n+\r\n+    .sb_hrdata              ( sb_ahb.hrdata  ),\r\n+    .sb_hready              ( sb_ahb.hready  ),\r\n+    .sb_hresp               ( sb_ahb.hresp   ),\r\n \r\n     //---------------------------------------------------------------\r\n     // LSU AHB Master\r\n     //---------------------------------------------------------------\r\n-    .lsu_haddr              ( initiator_inst.haddr       ),\r\n-    .lsu_hburst             (                       ),\r\n-    .lsu_hmastlock          (                       ),\r\n-    .lsu_hprot              (                       ),\r\n-    .lsu_hsize              ( initiator_inst.hsize       ),\r\n-    .lsu_htrans             ( initiator_inst.htrans      ),\r\n-    .lsu_hwrite             ( initiator_inst.hwrite      ),\r\n-    .lsu_hwdata             ( initiator_inst.hwdata      ),\r\n-\r\n-    .lsu_hrdata             ( initiator_inst.hrdata[63:0]),\r\n-    .lsu_hready             ( initiator_inst.hready      ),\r\n-    .lsu_hresp              ( initiator_inst.hresp       ),\r\n+    .lsu_haddr              ( lsu_ahb.haddr  ),\r\n+    .lsu_hburst             (                ),\r\n+    .lsu_hmastlock          (                ),\r\n+    .lsu_hprot              (                ),\r\n+    .lsu_hsize              ( lsu_ahb.hsize  ),\r\n+    .lsu_htrans             ( lsu_ahb.htrans ),\r\n+    .lsu_hwrite             ( lsu_ahb.hwrite ),\r\n+    .lsu_hwdata             ( lsu_ahb.hwdata ),\r\n+\r\n+    .lsu_hrdata             ( lsu_ahb.hrdata ),\r\n+    .lsu_hready             ( lsu_ahb.hready ),\r\n+    .lsu_hresp              ( lsu_ahb.hresp  ),\r\n \r\n     //---------------------------------------------------------------\r\n     // DMA Slave\r\n@@ -513,6 +524,51 @@ el2_veer_wrapper rvtop (\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hresp     = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hresp;\r\n     always_comb responder_inst[`CALIPTRA_SLAVE_SEL_IDMA].hreadyout = responder_inst[`CALIPTRA_SLAVE_SEL_DDMA].hreadyout;\r\n \r\n+    // SB and LSU AHB master mux\r\n+    ahb_lite_2to1_mux #(\r\n+        .AHB_LITE_ADDR_WIDTH (`CALIPTRA_AHB_HADDR_SIZE),\r\n+        .AHB_LITE_DATA_WIDTH (`CALIPTRA_AHB_HDATA_SIZE)\r\n+    ) u_sb_lsu_ahb_mux (\r\n+        .hclk                (clk_cg),\r\n+        .hreset_n            (cptra_noncore_rst_b),\r\n+\r\n+        // Initiator 0\r\n+        .hsel_i_0            (1'b1          ),\r\n+        .haddr_i_0           (lsu_ahb.haddr ),\r\n+        .hwdata_i_0          (lsu_ahb.hwdata),\r\n+        .hwrite_i_0          (lsu_ahb.hwrite),\r\n+        .htrans_i_0          (lsu_ahb.htrans),\r\n+        .hsize_i_0           (lsu_ahb.hsize ),\r\n+        .hready_i_0          (1'b1          ),\r\n+        .hresp_o_0           (lsu_ahb.hresp ),\r\n+        .hready_o_0          (lsu_ahb.hready),\r\n+        .hrdata_o_0          (lsu_ahb.hrdata),\r\n+\r\n+        // Initiator 1\r\n+        .hsel_i_1            (1'b1          ),\r\n+        .haddr_i_1           (sb_ahb.haddr  ),\r\n+        .hwdata_i_1          (sb_ahb.hwdata ),\r\n+        .hwrite_i_1          (sb_ahb.hwrite ),\r\n+        .htrans_i_1          (sb_ahb.htrans ),\r\n+        .hsize_i_1           (sb_ahb.hsize  ),\r\n+        .hready_i_1          (1'b1          ),\r\n+        .hresp_o_1           (sb_ahb.hresp  ),\r\n+        .hready_o_1          (sb_ahb.hready ),\r\n+        .hrdata_o_1          (sb_ahb.hrdata ),\r\n+\r\n+        // Responder\r\n+        .hsel_o              (initiator_inst.hsel  ),\r\n+        .haddr_o             (initiator_inst.haddr ),\r\n+        .hwdata_o            (initiator_inst.hwdata),\r\n+        .hwrite_o            (initiator_inst.hwrite),\r\n+        .htrans_o            (initiator_inst.htrans),\r\n+        .hsize_o             (initiator_inst.hsize ),\r\n+        .hready_o            (initiator_inst.hready),\r\n+        .hresp_i             (initiator_inst.hresp ),\r\n+        .hreadyout_i         (initiator_inst.hready),\r\n+        .hrdata_i            (initiator_inst.hrdata)\r\n+    );\r\n+\r\n     // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)\r\n     always_ff @(posedge clk or negedge cptra_rst_b) begin\r\n         if (~cptra_rst_b) begin\r\n", "test_patch": "", "modified_files": ["src/integration/rtl/caliptra_top.sv"], "lines_added": 80, "lines_removed": 24}
+{"repo": "chipsalliance/caliptra-rtl", "pr_id": 70, "lang": "sv", "rtl_files": ["src/soc_ifc/rtl/soc_ifc_top.sv"], "commit_id": "721cf1171b765533602bbadb9cc94b5f1da480ab", "timestamp": "2023-05-04T16:45:36+00:00", "pr_title": "Moving tool installation to step prior to matrix generation", "pr_body": "Moving tool installation to step prior to matrix generation.  \r\n\r\nIf the tools haven't been cached in a new branch, each test will clobber the cache, causing the tests to install the tools every time.  This re-arranges the order so that we ensure tools are installed prior to creating the test matrix.\r\n\r\nThis also modified the watchdog timer from always_comb to generate as discussed in https://github.com/chipsalliance/caliptra-rtl/issues/71", "issue_title": "verilator smoke test (sha512/sha256/iccm_lock/sha_accel) failures", "issue_body": "I ran into the following issue while running some [smoke tests](https://github.com/chipsalliance/caliptra-rtl/actions/runs/4801296942/jobs/8544916590).  I did a few git bisect to see where things broke.\r\n\r\n```\r\n----------------------------------------\r\nRunning SHA512 Smoke Test             !!\r\n----------------------------------------\r\nHit max cycle count (20000000) .. stopping\r\n- /home/runner/work/caliptra-rtl/caliptra-rtl/src/integration/tb/caliptra_top_tb_services.sv:495: Verilog $finish\r\n```\r\n\r\ntestname | commit\r\n--|--\r\nsmoke_test_sha512, smoke_test_sha256, iccm_lock, smoke_test_sha_accel | 51bf68d3c2e3a1499f53d31b1b45f144726041aa \r\n\r\nWondering if these have been fixed internally?", "commit_message": "Changing $display to $error for error messages", "fix_patch": "diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv\nindex a302f0263..e6c5d156f 100644\n--- a/src/soc_ifc/rtl/soc_ifc_top.sv\n+++ b/src/soc_ifc/rtl/soc_ifc_top.sv\n@@ -691,11 +691,9 @@ assign timer2_en = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_EN.timer2_en;\n assign timer1_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_CTRL.timer1_restart;\n assign timer2_restart = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_CTRL.timer2_restart;\n \n-always_comb begin\n-    for (int i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n-        timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n-        timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n-    end\n+for (genvar i = 0; i < WDT_TIMEOUT_PERIOD_NUM_DWORDS; i++) begin\n+  assign timer1_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER1_TIMEOUT_PERIOD[i].timer1_timeout_period.value;\n+  assign timer2_timeout_period[i] = soc_ifc_reg_hwif_out.CPTRA_WDT_TIMER2_TIMEOUT_PERIOD[i].timer2_timeout_period.value;\n end\n \n //Set WDT status reg\n", "test_patch": "diff --git a/.github/workflows/build-test-verilator.yml b/.github/workflows/build-test-verilator.yml\nindex 0b41a2ebb..5f76eb0d1 100644\n--- a/.github/workflows/build-test-verilator.yml\n+++ b/.github/workflows/build-test-verilator.yml\n@@ -10,31 +10,9 @@ on:\n   workflow_dispatch:\n \n jobs:\n-  build_matrix:\n-    name: Build Smoke Test matrix\n-    runs-on: ubuntu-22.04\n-    outputs:\n-      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n-    steps:\n-      - uses: actions/checkout@v3\n-      - name: Install deps\n-        run: |\n-          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n-            python3-minimal python3-yaml\n-      - name: Build matrix\n-        id: output-matrix\n-        run: |\n-          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n-\n-  build_and_test:\n-    name: Verilator Smoke Test\n+  build_tools:\n+    name: Build Tools\n     runs-on: ubuntu-22.04\n-    needs: build_matrix\n-\n-    strategy:\n-      fail-fast: false\n-      matrix:\n-        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n \n     env:\n       CARGO_INCREMENTAL: 0\n@@ -135,14 +113,93 @@ jobs:\n           path: /opt/riscv\n           key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n \n+      - name: Setup riscv path\n+        run: |\n+          echo /opt/riscv/bin >> $GITHUB_PATH\n+\n+  build_matrix:\n+    name: Build Smoke Test matrix\n+    runs-on: ubuntu-22.04\n+    needs: build_tools\n+    outputs:\n+      test_names: ${{ steps.output-matrix.outputs.test_names  }}\n+    steps:\n+      - uses: actions/checkout@v3\n+      - name: Install deps\n+        run: |\n+          sudo apt-get update -qy && sudo apt-get install -qy --no-install-recommends \\\n+            python3-minimal python3-yaml\n+      - name: Build matrix\n+        id: output-matrix\n+        run: |\n+          echo \"test_names=$(python3 .github/scripts/build_tests_matrix.py)\" >> $GITHUB_OUTPUT\n+\n+  build_and_test:\n+    name: Verilator Smoke Test\n+    runs-on: ubuntu-22.04\n+    needs: build_matrix\n+\n+    strategy:\n+      fail-fast: false\n+      matrix:\n+        test_name: ${{fromJSON(needs.build_matrix.outputs.test_names)}}\n+\n+    env:\n+      # TODO: is there a way to grab these from build_tools?\n+      CARGO_INCREMENTAL: 0\n+      SCCACHE_VERSION: 0.3.3\n+      RISCV_VERSION: v12.1.0\n+      # TODO: To update to 5.006, clean up lint errors\n+      VERILATOR_VERSION: v5.002\n+      PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig\n+      SCCACHE_GHA_CACHE_TO: sccache-verilator-10000\n+      SCCACHE_GHA_CACHE_FROM: sccache-verilator-\n+      # Change this to a new random value if you suspect the cache is corrupted\n+      SCCACHE_C_CUSTOM_CACHE_BUSTER: f3e6951f0c1d\n+\n+    steps:\n+      - uses: actions/checkout@v3\n+        with:\n+          submodules: 'true'\n+\n+      - name: Restore Cargo index\n+        uses: actions/cache/restore@v3\n+        id: cargo_index_restore\n+        with:\n+          path: ~/.cargo/registry/index\n+          key: cargo-index-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}-${{ hashFiles('Cargo.lock') }}\n+\n+      - name: Restore sccache binary\n+        uses: actions/cache/restore@v3\n+        id: sccache_bin_restore\n+        with:\n+          path: ~/.cargo/bin/sccache\n+          key: sccache-bin-${{ env.SCCACHE_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore verilator dir\n+        uses: actions/cache/restore@v3\n+        id: verilator_restore\n+        with:\n+          path: /opt/verilator\n+          key: verilator-${{ env.VERILATOR_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n+      - name: Restore Risc V Toolchain\n+        uses: actions/cache/restore@v3\n+        id: riscv_restore\n+        with:\n+          path: /opt/riscv\n+          key: riscv-${{ env.RISCV_VERSION }}-${{ env.SCCACHE_C_CUSTOM_CACHE_BUSTER }}\n+\n       - name: Setup verilator path\n+        run: |\n+          echo /opt/verilator/bin >> $GITHUB_PATH\n+\n+      - name: Setup riscv path\n         run: |\n           echo /opt/riscv/bin >> $GITHUB_PATH\n \n       - name: Run Caliptra Verilator Smoke Test\n         run: |\n-          # TODO: Add the run_verilator_l0_regression.py script.\n-          # Running a simple test to make sure that there aren't any elaboration issues\n           CALIPTRA_ROOT=$(pwd)\n           cd tools/scripts\n           make verilator CALIPTRA_ROOT=$CALIPTRA_ROOT TESTNAME=${{ matrix.test_name  }}\ndiff --git a/src/integration/tb/caliptra_top_tb_services.sv b/src/integration/tb/caliptra_top_tb_services.sv\nindex 6ec85caf9..964c67c01 100644\n--- a/src/integration/tb/caliptra_top_tb_services.sv\n+++ b/src/integration/tb/caliptra_top_tb_services.sv\n@@ -488,7 +488,7 @@ module caliptra_top_tb_services\n         cycleCnt <= cycleCnt+1;\n         // Test timeout monitor\n         if(cycleCnt == MAX_CYCLES && !UVM_TB) begin\n-            $display (\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n+            $error(\"Hit max cycle count (%0d) .. stopping\",cycleCnt);\n             dump_memory_contents(MEMTYPE_LMEM, 32'h8000_0110, 32'h8000_0180);\n             dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n             dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n@@ -528,12 +528,12 @@ module caliptra_top_tb_services\n             if (UVM_TB) $info(\"INFO: Detected FW write to manually end the test with FAIL; ignoring since the UVM environment will handle this.\");\n             else begin\n                 cycleCntKillReq <= cycleCnt;\n-                $display(\"* TESTCASE FAILED\");\n+                $error(\"* TESTCASE FAILED\");\n                 $display(\" -- Extending simulation for 100 clock cycles to capture ending waveform\");\n             end\n         end\n         if (|cycleCntKillReq && (cycleCnt == (cycleCntKillReq + 100))) begin\n-                $display(\"Dumping memory contents at simulation end due to FAILURE\");\n+                $error(\"Dumping memory contents at simulation end due to FAILURE\");\n                 dump_memory_contents(MEMTYPE_LMEM, 32'h0000_0000, 32'h001_FFFF);\n                 dump_memory_contents(MEMTYPE_DCCM, `RV_DCCM_SADR, `RV_DCCM_EADR);\n                 dump_memory_contents(MEMTYPE_ICCM, `RV_ICCM_SADR, `RV_ICCM_EADR);\n", "modified_files": [".github/workflows/build-test-verilator.yml", "src/integration/tb/caliptra_top_tb_services.sv", "src/soc_ifc/rtl/soc_ifc_top.sv"], "lines_added": 89, "lines_removed": 34}

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